EC1303 – Microprocessor & its applications
Unit III
Intel 8086:
Features: 1. 16-bit Data bus 2. Computes 16 bit / 32 bit data. 3. 20-bit address bus. 4. More memory addressing capability (220 = 1MB) 5. 16 bit Flag register with 9 Flags 6. Can be operated in Minimum mode and Maximum mode 7. Has two stage pipelined architecture 8. No internal clock generation 9. 40 pin DIP IC - HMOS technology 10. Operates on +5V supply voltage 11. Has more powerful instruction set
8086 PIN CONFIGURATION: •
The 16-bit 8086 microprocessor has 40 pins.
•
It is available in 5 MH, 8MHz and 10 MHz.
•
It can operate in two modes, i.e. single processor (minimum mode) or multiprocessor (maximum mode) configuration.
•
The signals are categorized in three groups as follows (i) Common signal, which are used in minimum as well as maximum mode (ii) Signal for minimum mode (iii) Signals for maximum mode.
•
The pin diagram for 8086 processor is shown in fig.
Fig.1 – Pin diagram of 8086. 1
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
MINIMUM MODE CONFIGURATION OF 8086 SYSTEM: When MN/MX (low) pin is in logic 1, the 8086 microprocessor operates in minimum mode system. In this mode, the microprocessor chip itself gives out all the control signals. •
This is a single processor mode.
•
The remaining components in the system are latches, transceivers, clock generator, memory or I/O devices.
•
The latches are used for separating the valid address from the multiplexed address/data signals and the controlled by the ALE signal generated by 8086.
•
Transceivers are the bi-directional buffers. They are required to separate the valid data from the time multiplexed address/data signal. This is controlled by two signals, DEN & DT/R (low).
•
DT/R (low) indicates that the direction of data, i.e. from or to the indicator.
•
DEN signal indicates the valid data is available on the data bus.
•
The clock generator in the system is used to generate the clock and to synchronize some external signals with the system clock.
The minimum mode system organization is,
Fig. 2-Minimum mode of 8086
2
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
MAXIMUM MODE CONFIGURATION OF 8086 SYSTEM: If the MN/MX (low) pin is low i.e. zero, then the 8086 can operate in maximum mode. In this mode, the Bus controller (8288) chip used to generate control signals I/O W, I/O R, RD, WR (Active low) etc., by receiving the active low status signals (S2, S1 & S0) from the microprocessor. •
MRDC (low) : Memory read command – It instructs the memory to put the contents of the addressed location to the data bus.
•
MWTC (low) : Memory write command – It instructs the memory to accept the data on the data bus and load that data into the address memory location.
•
IORC (low) : I/O read command – It instructs an I/O device to put the data contained in the addressed port on the data bus.
•
IOWC (low) : I/O write command – It instructs an I/O device to accept the data on the data bus and load the data into the addressed port.
•
AIOWC (low) / AMWC (low) : Advance IO write command / Advance memory write command – These are similar to IOWC and MWTC except that they are activated one clock pulse earlier. This gives slow interfaces an extra clock cycle to prepare to input the data.
•
This system also consists of latches, tristate buffer, memory input-output device, etc.
•
The DEN, DT/R, ALE, etc is derived by the bus controller from the information available on the active low status signals (S2, S1 & S0).
•
In this mode, Request/Grant pin (RQ/GT) is checked at each rising pulse of clock I/P when the request is detected and if Hold request are satisfied, the processor issues a grant pulse over RQ/GT pin immediately during T4 or next T1 state to accept the control of the bus. Therefore, the requesting controller uses the bus till it requires.
•
When it is ready to relinquish the bus, it sends a release pulse to the processor using the RQ/GT pin.
The figure below shows 8086 processor in maximum mode.
Fig. 3-Maximum mode of 8086 3
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
8086 – ARCHITECTURE: The 8086 processor is divided into two independent functional units. They are, • •
The bus interface unit (BIU). The Execution Unit (EU).
These two units are linked using an internal data bus.
Fig.4 - 8086 Architecture
4
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
Bus Interface Unit: The Bus interface unit (BIU) fetches instruction, reads data from memory and peripherals and writes data into memory and peripherals. It contains the following blocks to provide functions such as fetching & queuing of instructions and bus control. 1. 2. 3. 4. 5.
Segment registers Instruction pointer Instruction queue Address generation Bus control circuit
1. Segment Registers: 8086 processor has capability to address memory of size 1 MB and the memory is divided into 16 segments of up to 64 Kbytes each. Each 64KB segment can be used to store the code, data, stack, etc., separately and the segment address of the same is stored in corresponding segment registers. The four 16-bit segment registers in BIU are
Code Segment (CS) registers Data Segment (DS) registers Stack Segment (SS) registers Extra Segment (ES) registers
Code segment (CS) All program instructions must be stored in main memory and its location is pointed by segment address in 16-bit CS register and 16-bit offset in the code segment contained in the 16 bit Instruction pointer (IP). The 20-bit physical address of program instruction is computes as [CSx10]+[IP]. Eg : If [CS] = 456AH and [IP] = 1620H ; then 20 bit Physical Address (PA) = 456A0H + 1620H = 46CC0H Stack segment (SS) A segment (64KB) of memory is allocated for stack operations in 8086 and its current location of the stack is pointed by Stack Segment (SS) register and Stack pointer (SP). The 20-bit physical stack address is calculated as [SSx10] + [SP]. Data segment (DS) The Data segment (DS) register points the segment allocated in memory to store data, i.e. operands for most instructions are fetched from this segment. The 16-bit offset address in the data segment can be stored in 1. Base Pointer (BP) 2. Source Index (SI) 3. Destination Index (DI) 5
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
Extra segment (ES) This register points to the Extra segment in which the excess data is stored. The DI is used as offset for calculating the 20-bit physical address. String instruction always uses ES and DI to calculate the 20-bit address for the destination. 2. Instruction Queue: The BIU’s instruction queue is a First In First Out (FIFO) group of registers in which up to six bytes of instruction code are projected from memory. This is done to speed up program execution by overlapping instruction fetch with execution. This mechanism is referred to as pipe lining. •
If queue is full, the BIU does not perform any bus cycle i.e., BIU does not prefetch any instructions. Therefore, BIU may prefetch the instructions from memory until queue is full.
•
While fetching the instruction from memory, if the Execution Unit (EU) interrupts the BIU for memory access, the BIU first complete fetching and then services the EU.
•
If a subroutine call or Jump instructions are encountered, the BIU will reset the queue and begin refilling after passing the new instruction to the EU.
3. Address Generation: BIU contains an adder, which is used to produce the 20-bit physical address of memory by addressing the contents of segment address and offset address. 4. Bus Control Logic: The bus control logic of the BIU generates all the bus control signals such as read and write signals for memory and I/O.
Execution Unit: The Execution unit (EU) takes instruction from instruction queue, decodes and executes instructions one after another. It contains the following blocks to provide functions such as decoding and execution of instructions. 1. 16-bit ALU 2. 8x16-bit Registers (AX, BX, CX, DX, SP, BP, SI & DI). 3. 16-bit Flag Register
1. ALU The ALU has the capacity to handle 16-bit data and it performs several arithmetic and logical operations on 16-bit / 32-bit data. 6
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
2. General Registers There are eight 16-bit general registers in EU of 8086 to store 16 bit/8 bit data. They are AX, BX, CX, DX, SP, BP, SI & DI
The four 16-bit registers, AX, BX, CX and DX are combination of two 8-bit registers ie., H-higher byte and L-lower byte. These registers can be used to store a 16-bit data when used as a whole 16-bit register or store 8-bit data when used separately. AX - 16-bit accumulator used in the Arithmetic & Logical operations. AL is the 8-bit accumulator. BX - the only general-purpose 16-bit register & also used for addressing memory. CX register is the 16-bit counter register used along with LOOP instructions. DX is the data register is used to hold excess 16-bit result while performing multiplication, division, etc. SP & BP are point registers, which are used to access data in stack segment and other segments.
3. Flag Register: The EU also contains a 16-bit flag register which holds the status flags typically after an ALU operation. The flag register of 8086 micro processor is,
O – D – I – S – Z – AC– P – CY–
Overflow flag Direction flag Interrupt flag Sign flag Zero flag Auxiliary carry flag Parity flag Carry flag 7
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
The flags are divided into two classifications. They are, A- CONDITION CODE FLAGS These flags reflect the result of Operations Performed by ALU. They are,
Over flow flag (O): This flag is set, if an overflow occurs during the arithmetic operation of two signed numbers. Sign flag (S): This flag is set, if an MSB of the accumulator is set after any computation. Zero flag (Z): This flag is set, if the result of any computation is zero. Auxiliary carry flag (AC): This flag is set, if there is a carry from the third bit, during addition or borrow. Parity flag (P): The flag is set, if the lower byte result contains even number of 1’s. Carry flag (CY): This flag is set, if any computation result contains a carry. B- MACHINE CONTROL FLAGS Direction Flag: This flag is set, if the string is processed from higher address towards lower address. Otherwise, the flag is reset. This is used only in string manipulation instructions. Interrupt flag: This flag is set, only when maskable interrupts are recognized. Trap flag: When a trap interrupt is received by the processor, this flag is set, which indicates, the processor to execute the current instruction and to transfer the control to trap service routine. In Other words, When 8086 enters in single step mode, this flag is set.
8
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
ADDRESSING MODES: 1. Addressing modes for accessing Immediate and Register data. 2. Addressing modes for accessing data in Memory. 3. Addressing modes for accessing I/O ports. 4. Relative Addressing mode. 5. Implied Addressing mode.
(1). Addressing modes for accessing immediate and register data: (i) Register addressing mode: The registers, which is having the data to be operated is specified in the instruction. MOV BX, CX : [CX]
[BX]
MOV CL, BL
[CL]
: [BL]
(ii) Immediate addressing mode: A signed 8 bit or an unsigned 16 bit immediate data is specified in the instruction. MOV BL, 26H
: 26H
[BL]
MOV CX, 4567H : 4567H
[CX]
(2). Addressing modes for accessing data in memory:
(i) Direct addressing mode: •
• • • •
An Effective Address (EA), which is the offset (an unsigned 16 bit data or signed 8 bit data) from the data segment register, is directly specified in the instruction. Eg. : MOV CX, [9823H] The effective address is, EA = 9823H. The base address is, BA = [DS] x 1610 The memory address, which is having the data, is, MA = [EA] + [BA]. The MA content will be copied into the register CX.
9
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
(ii) Register indirect addressing mode: • • • • • •
An Effective Address (EA), which is the offset (an unsigned 16 bit data or signed 8 bit data) from the data segment register, is indirectly specified in the instruction. The registers used to hold the effective address are BX, SI and DI. Eg. : MOV CX, [BX] The effective address is, EA = [BX]. The base address is, BA = [DS] x 1610 The memory address, which is having the data, is, MA = [EA] + [BA]. The MA content will be copied into the register CX.
(iii) Based Addressing Mode: •
• • • •
In this addressing mode the BX or BP register is used to hold the base value for EA and an unsigned 16 bit data or signed 8 bit displacement will be specified in the instruction. Eg. : MOV AX, [BX + 08H] (ie., 08H 0008H) The effective address is, EA = [BX] + [0008H] The base address is, BA = [DS] x 1610 The memory address, which is having the data, is, MA = [EA] + [BA]. The MA content will be copied into the register AX.
(iv) Indexed Addressing Mode: •
• • • •
In this addressing mode the SI or DI register is used to hold the index value for EA and an unsigned 16 bit data or signed 8 bit displacement will be specified in the instruction. Eg. : MOV AX, [DI + 08H] 08H 0008H The effective address is, EA = [DI] + [0008H] The base address is, BA = [DS] x 1610 The memory address, which is having the data, is, MA = [EA] + [BA]. The MA content will be copied into the register AX.
(v) Based Indexed Addressing Mode: •
• • • •
In this addressing mode the SI or DI register is used to hold the index value for EA and BX or BP register is used to hold the base value for EA an unsigned 16 bit data or signed 8 bit displacement will be specified in the instruction. Eg. : MOV AX, [BX +DI + 08H] 08H 0008H The effective address is, EA = [DI] + [BX] + [0008H] The base address is, BA = [DS] x 1610 The memory address, which is having the data, is, MA = [EA] + [BA]. The MA content will be copied into the register AX. 10
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
(vi) String Addressing Mode: •
• • • • • • • •
In this addressing mode the EA for source is stored in Si register and EA for destination is stored in DI register. Eg. : MOVS BYTE The effective address for source is, EA = [SI] The base address for source is, BA = [DS] x 1610 The memory address, which is having the data, is, MA = [EA] + [BA]. The effective address for destination is, EAD = [SI] The base address for destination is, BAD = [ES] x 1610 The memory address in where the data to move is, MAD = [EA] D + [BA] D. The MA content will be copied into MAD. After moving the byte, If DF = 1, SI and DI will be decremented by 1. If DF = 0, SI and DI will be incremented by 1.
(3). Addressing modes for I/O ports: (i) Direct I/O port Addressing Mode: • The address of port is directly given in instruction itself. Eg. : IN AL, [09H] PortAddr = 09H [Port] [AL] (ii) Indirect I/O port Addressing Mode: • The address of port is indirectly given in instruction itself. Eg. : IN AL, [CL] PortAddr = [CL] [Port] [AL] (4). Relative Addressing: •
• • • • • •
The effective address of a program instruction is specified relative to IP by an 8 bit signed displacement. Eg. : JZ 0AH The signed 8 bit will be extended to 16 bit data as 000AH. The IP content is, [IP]new = [IP]old + 000AH. The effective address is, [EA] = [IP]new + 000AH. The base address is, BA = [CS] x 1610 The memory address is, MA = [EA] + [BA]. Program control jump into the new MA.
(5). Implied Addressing: • •
The instruction itself specifies the data to be operated. Eg. : CLC – It clears the carry flag.
11
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
ASSEMBLY LANGUAGE PROGRAMME: The general format of an assembler instruction is, Label: Mnemonics Opcode, Operand; comment. The 8086 instruction set is classified as follows. 1. Data Transfer Instructions 2. Arithmetic Instructions 3. Bit manipulation instruction. 4. String instruction. 5. Program execution transfer instruction. 6. Processor control instruction.
I. DATA TRANSFER INSTRUCTIONS: The instructions that transfer data between registers, memory locations or segment registers. It is again classified into four types. They are, 1. General purpose byte or word transfer instructions 2. Special address transfer instructions 3. Flag transfer instructions 4. Simple input and output Port transfer instructions
A. General purpose byte or word transfer instructions MOV: It copies the content of source to the destination. Eg. : MOV BX, 5978H ; Load the immediate number 5978H to BX. MOV CL, [453AH] ; Copies the content of memory location which is at a distant of 453AH from the data segment into CL register. MOV DS, CX ; Copies the word from CX to data segment. PUSH • It decrements the stack pointer by 2. • It stores the 16 bit data from the source to the address in the stack pointer. Eg. : SP = 80983H CX = 49A3H PUSH CX [CX] SP SP = 80981H POP • •
It stores the 16 bit data from the destination to the stack pointer. It increments the stack pointer by 2. Eg. : SP = 80983H CX = 49A3H POP CX [CX] SP SP = 80985H 12
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
XCHG: It exchanges the contents of source with the destination. Eg. : XCHG BX, CX ; Exchange word in CX with word in BX. XCHG BL, CL ; Exchange byte in CL with byte in BL. XLAT : • IT replaces byte in AL register. • BX is having the offset value of memory location. • It copies byte from address pointed by [BX + AL ] into AL register.
B. Special address transfer instructions: LEA: • Load effective address. • The mnemonics is LEA register, source. • Source is having the offset of the memory location and this instruction load this address into 16 bit register. LDS: • The mnemonics is LDS register, memory address of first word. • It copies a word from two memory locations into the register. • It then copies a word from next two memory locations into the DS register. Eg. : LDS CX, [391AH] LES: • The mnemonics is LES register, memory address of first word. • It copies a word from two memory locations into the register. • It then copies a word from next two memory locations into the ES register. Eg. : LES CX, [391AH]
C. Flag Transfer Instructions: LAHF: This instruction copies the contents of lower byte of 8086 flag register to AH register. SAHF: The contents of the AH register are copied into the lower byte of the 8086 flag register. PUSHF: This instruction decrements the stack pointer by 2 and copies the word in the flag register to the memory locations pointed by the stack pointer. POPF: This instruction copies a word the two memory locations at the top of the stack to the flag register and increments the stack pointer by 2.
D. Simple Input and Output Port Transfer Instructions: IN: • •
This instruction will copy data from a port to the accumulator. If an 8 bit port is read the data will go to AL and if an 16 bit port is read the data will go to AX. © NSS/ECE 13
EC1303 – Microprocessor & its applications
Unit III
OUT: • This instruction will copy data from a port to the accumulator. • The OUT instruction copies a byte from AL or a word from AX to the specified port.
II. ARITHMETIC INSTRUCTIONS: A. Addition Instructions: ADD – Add the destination and source contents. Eg.: ADD AL, 0FH – Add immediate number 0FH to the contents of AL. ADC – Add the destination and source contents with carry. Eg.: ADC DL, CL – Add the content of DL with CL content with carry and stores the results in DL. ie., [DL] + [CL] + CY [DL] ADC DX , CX - Add the content of DX with CX content with carry and stores the results in DX. ie., [DX] + [CX] + CY [DX] INC – increment the destination value by one Eg. : INC AL – Add 1 to contents of AL INC BX - Add 1 to contents of AX AAA – ASCII adjust for addition • The numbers from 0-9 are represented as 30H-39H in ASCII code. • After addition of two decimal digits, which are represented in ASCII code, AAA is used to store the result in ASCII. DAA – Decimal Adjust Accumulator • After addition of two decimal digits, which are represented in BCD code, DAA is used to store the result in BCD. • It add 0110(6H) with the nibbles which is greater than 1001(9H) to give the result in BCD. Eg. – AL = 0011 1001 = 39 BCD CL = 0001 0010 = 12 BCD ADD AL, CL ; AL = 0100 1011 = 4BH DAA ; add 06H = 0000 0110 to 4B; because 1011 >9 ; AL = 0101 0001 = 51 BCD
B. Subtraction Instructions: SUB SBB DEC NEG CMP AAS DAS
– Subtracts the source from the destination. – Subtracts the source and carry from the destination – Decrement the destination by 1 – Negate instruction forms 2’s complement of the destination. – Compares the source and destination. – ASCII adjust after subtraction. – Decimal adjust after subtraction. 14
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
C. Multiplication Instruction: MUL: • It is used to multiply an unsigned byte from the source and unsigned byte in AL register and stores the result in AX. • It is used to multiply an unsigned word from the source and unsigned word in AX register and stores the high word of result stored in DX and low word in AX. Eg. : MUL BL - AL x BL, result stored in AX. MUL BX – AX x BX, High word of result stored in DX and low word in AX. IMUL – It multiplies the word or byte with sign. AAM – BCD adjust after multiply.
D. Division Instruction: DIV
- It is used to divide an unsigned word (16 bit) by a byte (8 bit) or to divide an unsigned double word (32 bit) by a word (16 bit). Eg. : DIV CL Word in AX / Byte in CL, Quotient stored in AL and remainder in AH. DIV CX - Double word in AX and DX / Word in CX, Quotient stored in AX and remainder in DX.
IDIV - It is used to divide a signed word (16 bit) by a byte (8 bit) or to divide a signed double word (32 bit) by a word (16 bit). AAD - Binary adjust before division.
E. Sign Extension Instruction: CBW – It copies the D7 bit of AL into all the bits in AH. Eg.:
AX = 0000 000 1001 1000 D7 bit is 1. Now, AX = 1111 1111 1001 1000
CWD - It copies the D15 bit of AX into all the bits in DX. Eg.: DX = 0000 0000 0000 0000 AX = 1111 0000 1100 0001 D15 of AX is 1. Now, DX = 1111 1111 1111 1111 AX = 1111 0000 1100 0001 15
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
III. BIT MANIPULATION INSTRUCTIONS (Logical Instructions): NOT: The NOT instruction inverts each bit of a byte or a word. The destination can be register or a memory location. Eg.:
if AL = 0110 1100 NOT AL ; AL = 1001 0011 if CX = 1010 1111 0010 0010 NOT CX ; CX = 0101 0000 1101 1001
AND: This instruction logically ANDs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination. Eg. : AL = 1001 0011 = 93H BL = 0111 0101 = 75H AND BL, AL
; AND Byte in AL with byte in BL ; BL = 0001 0001 = 11H
OR : This instruction logically ORs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination. Eg. : AL =1001 0011 = 93H BL =0111 0101 = 75H OR BL, AL
; OR byte in AL with byte in BL ; BL =1111 0111 = F7H
XOR : This instruction logically XORs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination. TEST: This instruction logically ANDs each bit of the source byte or word with the corresponding bit in the destination and updates the flags but not stores results in anywhere. Eg.: AL = 1001 0011 = 93H BL = 0111 0101 = 75H AND BL, AL
; AND Byte in AL with byte in BL ; Result = 0001 0001 = 11H (not stored) ; Z = 0, P = 1 (flag affected))
AND BX, AX
; AND word in AX with word in BX ; updates the flag and result is not stored.
16
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
IV. SHIFT INSTRUCTIONS SAL / SHL: • • •
The mnemonics is SAL / SHL destination, count. It shift each bit in the destination to the left and 0 is stored in LSB position. The MSB is shifted to the carry flag.
Eg. : 1. SAL / SHL CX, 1 2. MOV CL, 05H SAL / SHL AX, CL SHR : • The mnemonics is SHR destination, count. • It shift each bit in the destination to the right and 0 is stored in MSB position. • The LSB is shifted to the carry flag.
Eg. : 1. SHR CX, 1 2. MOV CL, 05H SHR AX, CL SAR: • The mnemonics is SAR destination, count. • It shift each bit in the destination to the right and the old MSB is stored in MSB position. • The LSB is shifted to the carry flag.
Eg. : 1. SAR CX, 1 2. MOV CL, 02H SAR AX, CL 17
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
V. RORATE INSTRUCTIONS ROL: • The mnemonics is ROL destination, count. • It rotates each bit in the destination to the left. • The MSB is shifted to the carry flag and to the LSB position.
Eg. : 1. ROL CX, 1 2. MOV CL, 02H ROL BL, CL
ROR : • The mnemonics is ROR destination, count. • It rotates each bit in the destination to the right. • The LSB is shifted to the carry flag and to the MSB position.
Eg. : 1. ROR CX, 1 2. MOV CL, 03H ROR BL, CL RCL: • The mnemonics is RCL destination, count. • It rotates each bit in the destination to the left along with carry. • The MSB is shifted to the carry flag and the carry to the LSB position.
Eg. : 1. RCL CX, 1 2. MOV CL, 03H RCL BL, CL 18
© NSS/ECE
EC1303 – Microprocessor & its applications
• • •
Unit III
RCR: The mnemonics is RCR destination, count. It rotates each bit in the destination to the right along with carry. The LSB is shifted to the carry flag and carry to the MSB position.
Eg. : 1. RCR CX, 1 2. MOV CL, 03H RCR AL, CL
VI. PROGRAM EXECUTION TRANSFER INSTRUCTION (a) Unconditional transfer instruction: CALL: It is used to transfer the instruction to a sub program or to a procedure. RET : It is used to transfer the execution from a sub program or from a procedure to the instruction in the main program which is after the CALL instruction. JMP : This instruction will always cause the 8086 to fetch its instruction from the location specified in the instruction.
(b) Conditional transfer instruction: J : This instruction will always cause the 8086 to fetch its instruction from the location specified in the instruction if the condition given is true. Otherwise it executes the instruction followed by the jump instruction.
19
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
VII. ITERATION CONTROL INSTRUCTION • •
These instructions are used to execute a group of instructions some number of time. The instructions are, S.No
Instruction Code
1
LOOP
2
LOOPE / LOOPZ
3
LOOPNE / LOOPNZ
Description Loop through a sequence of instructions Loop through a sequence of instructions Loop through a sequence of instructions
Condition for Exit CX = 0 CX = 0 or ZF = 0 CX = 0 or ZF = 1
VIII. PROCESSOR CONTROL INSTRUCTIONS STC: It sets the carry flag to one; STC does not affect any other flag. CLC: It resets the carry flag to zero; CLC does not affect any other flag. CMC: It complements the carry flag; CMC does not affect any other flag. STD: It sets the direction flag to one so that SI and / or DI can be automatically decremented after execution of string instructions. STD does not affect any other flag. CLD: It resets the direction flag to zero so that SI and / or DI can be automatically incremented after execution of string instructions. CLD does not affect any other flag. STI:
It sets the interrupt flag to one; this enables INTR interrupt of the 8086. STI does not affect any other flag.
CLI: It resets the interrupt flag to zero. Due to this 8086 will not respond to an INTR interrupt input. CLI does not affect any other flag.
IX. EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS HLT:
This causes the 8086 to stop fetching and execution of instructions.
WAIT: This cause the 8086 enter into idle condition up to TEST (low) pin low. ESC:
This is used to pass the instruction to a coprocessor.
LOCK: • • • NOP:
Each microprocessor is having its own system bus and memory. In multiprocessor system, they will communicate with each other through the bus. After LOCK instruction, they cannot communicate with each other. At the time of execution of NOP instruction, no operation is performed except fetching and decoding. 20
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
X. INTERRUPT INSTRUCTIONS INT: • • • •
The mnemonics is INT Type. It is used to call a far procedure. Type is referred as a number between 0 and 255, which identifies the interrupt. The address of the procedure is calculated by multiplying the type number by 4.
INTO: If the overflow flag is set, this instruction will cause the 8086 to call a far procedure. IRET: It is used to end of the ISR to return execution to the main program/.
XI. STRING INSTRUCTIONS • • • • • •
REP / REPE / REPZ / REPNE / REPNZ MOVS / MOVSB / MOVSW CMPS / CMPSB / CMPSW SCAS / SCASB / SCASW LODS / LODSB / LODSW STOS / STOSB / STOSW
21
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
INTERRUPT SYSTEM: INTERRUPT is a signal applied / instruction given to the microprocessor to stop the current process done by it and carry out a specific task requested by the interrupted device. In response to an interrupt, the processor completes the execution of the current instruction and transfers the program control to execute a procedure called ISR (Interrupt Service Routine). After the complete execution of ISR, the processor returns the program control back to the original suspended process.
Interrupt in 8086 are initiated in three ways. They are, 1. Hardware interrupt 2. Software interrupt 3. Exceptional conditions interrupts
A.HARDWARE INTERRUPTS: There are two hardware interrupts in 8086 processor. 1. NMI – Non maskable interrupt 2. INTR – Interrupt • •
NMI interrupt has highest priority out of the two hardware interrupts. When two or more interrupts are received from different I/O devices, Intel 8259 Programmable Interrupt Controller is used to handle multiple interrupts.
B.SOFTWARE INTERRUPTS: •
There are 256 software interrupts with mnemonic INT followed by the interrupt number.
•
Each software interrupt is two bytes long and it has a format as shown below. Opcode for INT
•
Interrupt no. in HEX
It is represented as INT 00H … INT FFH.
C. EXCEPTIONAL CONDITIONS INTERRUPTS: An error condition created by the 8086 processor during the execution of an instruction leads to exceptional interrupts.
22
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
PREDEFINED INTERRUPTS: The first five interrupts are reserved by INTEL for specific functions. TYPE 0 TYPE 1 TYPE 2 TYPE 3 TYPE 4
: : : : :
INT 0 INT 1 INT 2 INT 3 INT 4
-
Divide by zero Single step Non maskable interrupt Break point Interrupt on Overflow
TYPE 0 Interrupt – Divide by Zero: Division operation is performed in 8086 using DIV or IDIV instructions. Division is performed either on 16-bit dividend by 8-bit divisor or 32-bit dividend by 16-bit divisor. In either case, if the quotient is too large to fit in the destination registers (AL/AX) or if a 16/32-bit number is attempted to be divided by zero, then TYPE 0 – interrupt is initiated.
TYPE 1 Interrupt – Single step Interrupt: If the TRAP flag is SET, 8086 automatically generates the TYPE 1 – Interrupt after execution of each instruction. Single step interrupt (TYPE 1) is a non-maskable interrupt. The user can write an ISR at the interrupt address to display the memory locations and/or the register content to debug the program.
TYPE 2 Interrupt – Non-maskable Interrupt: The TYPE 2 interrupt is initiated in response to the interrupt received at NMI pin of 8086 processor. The TYPE 2 interrupt is normally used to save the program data in case of power failure.
TYPE 3 Interrupt – Break point Interrupt: TYPE 3 interrupt is initiated using INT03 instruction, to create break point in program execution for debugging purpose.
TYPE 4 Interrupt – Overflow Interrupt: TYPE 4 interrupt is initiated either when OF(Overflow flag) is SET or when INT00 is executed.
23
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
INTERRUPT VECTOR TABLE: The first 1KB of the EPROM memory (i.e., memory address from 00000H to 003FFH) is allocated to store the interrupt vector table (IVT). This table contains the memory address (segment & offset address) of the ISR associated with each interrupt in 8086. Each interrupt is allocated 4 Bytes in IVT-Interrupt Vector Table, with 2 Bytes for Segment address and next 2 Bytes for Offset address. In response to an interrupt, the processor loads segment and offset address into CS and IP registers respectively to execute the corresponding ISR of the interrupt.
Address
Interrupt
Description
00000H 00004H 00008H 0000CH 00010H
INT 00 INT 01 INT 02 INT 03 INT 04
00014H
INT 05 – INT 1F
Divide by Zero Error Single Step Non maskable Break point interrupt Overflow Reserved by manufacturer for future expansion of interrupts
00080H
INT 20 – INT FF
24
User defined Interrupts
© NSS/ECE
EC1303 – Microprocessor & its applications
Unit III
Part A: 1. What are the segments registers in 8086?* 2. List the merits of Memory segmentation.* 3. Name the external hardware synchronization instruction 8086 processor.* 4. What is segment override prefix? Give an example.* 5. What is the function of TEST pin in 8086 processor?* 6. How does the 8086 processor access a word at on odd address?* 7. What are the differences between 8085 and 8086?* 8. Briefly explain the interrupts in 8086. 9. Draw the Flag register and label the flags with its bit positions. 10. What is minimum and maximum mode configuration?* 11. What is meant by pipelined architecture? 12. What is the significance of Trace flag in flag register of 8086? 13. What is the significance of Interrupt flag in flag register of 8086? 14. What is the significance of Direction flag in flag register of 8086?
Part B: 1. With neat diagram, explain the architecture of 8086 processor.* 2. Explain the instruction set of 8086 with examples.* 3. Explain the addressing modes of 8086 with examples.* 4. Explain the Interrupt structure of 8086 processor.* 5. Explain the memory segmentation in 8086. 6. Explain the minimum and maximum mode configuration of 8086 with neat diagrams. (or) Explain the working of 8086 in maximum mode. Explain the working of 8086 in minimum mode. 7. Design an 8086 based system in minimum modes to interface 64 KB EPROM and 64KB RAM with starting address 00000H and 80000H respectively.*
* - AU questions
25
© NSS/ECE
