Bridge Axi Ahb

QSOCs

AXI TO AHB BRIDGE

1. INTRODUCTION

Integrated circuits has entered the era of System -on-a-Chip (SoC), which refers to integrating all components compone nts of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio -frequency functions – functions – all all on a single chip substrate. With the increasing design size, IP is an inevitable choice for SoC design. And the widespread use of all kinds of IPs has changed the nature of the design flow, making On-Chip Buses (OCB) essential to the design. Of all OCBs existing in the market, the Advanced Microcontroller Bus Architecture (AMBA) bus system is widely used u sed as the de facto standard SoC bus. It facilitates development of multi-processor designs with large numbers of controllers and peripherals. Since its inception, the scope of AMBA has, despite its name, gone far beyond micro mic ro controller devices. Today, To day, AMBA is widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like smartphones. AMBA was introduced by ARM in 1996. The first AMBA buses were Advanced System Bus (ASB) and Advanced Peripheral Bus. It is very commonly used bus architecture. In order to support high-speed pipelined data transfers, AMBA 4.0 supports a rich set of bus signals, making the analysis of AMBA-based embedded systems a challenging Proposition. The goal of this project is to verify a AXI to AHB bridge. The bridge provides interface between the high performance AXI and high bandwidth ban dwidth peripherals of AHB domain. The AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4 transactions into AHB-Lite transactions. It has a slave interface which receives the AXI4 master transactions and converts them to AHB master transactions and initiates them on the AHB bus.

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QSOCs

1.1

AXI TO AHB BRIDGE

AMBA AXI (Advanced eXtensible Interface)

The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-speed submicron interconnects. The key features of the AXI protocol are: • Separate address/control and data phases • Support for unaligned data transfers using byte strobes • Burst-based transactions with only start address issued • separate read and write data channels to enable low-cost low-cost Direct Direct Memory Access (DMA) • Ability to issue multiple outstanding addresses • Out-of-order transaction completion • Easy addition of register stages to provide timing closure. As well as the data transfer protocol, the AXI protocol includes optional extensions that cover signaling for low-power operation. The AXI protocol is burst-based. Every transaction has address and control information on the address channel that describes the nature of the data to be transferred. The data is transferred between master and slave using 5 channels including Write Address Channel, Write Data Channel, Write Response Channel, Read Address Channel, Read Data Channel (Write data channel to the slave or a read data channel to the master).In write transactions, in which all the data flows from the master to the slave, the AXI protocol has an additional write response channel to allow the slave to signal to the master the completion of the write transaction.

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QSOCs

AXI TO AHB BRIDGE

1.2

Advanced High-performance Bus (AHB)

AMBA AHB-Lite addresses the requirements of high-performance s ynthesizable designs. It is a bus interface that supports a single bus master and provides high-bandwidth operation. AHB has address and data phase. Pipelining is done by the overlapping both the phases. AHB-Lite implements the features required for high-performance, high clock frequency systems including: • burst transfers • Single-clock Single-clock edge operation • Non-tristate Non-tristate implementation • Wide data bus configurations, 64, 128, 256, 512, and 1024 bits. It is highly pipelined. The most common AHB-Lite slaves are internal memory devices, external memory interfaces, and high bandwidth peripherals. Although low-bandwidth peripherals can be Included as AHB-Lite slaves, for system performance reasons they typically reside on the AMBA Advanced AMBA Advanced Peripheral Bus (APB). Bridging between this higher level of bus and APB is done using a AHB-Lite slave, known as an APB bridge

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QSOCs

AXI TO AHB BRIDGE

2. AXI TO AHB BRIDGE The AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4 transactions into AHB-Lite transactions. It has a slave interface which receives the AXI4 master transactions and converts them to AHB master transactions and initiates them on the AHB bus. AXI has five channels such as write address channel, Write data channel, write response channel, Read address channel and Read data channel. AXI clock is Operating independent of AHB clock. AXI to AHB converts AXI read and write transactions to corresponding AHB read and write transactions. This bridge provides an interface between high performance AXI processors and high bandwidth peripherals of AHB protocol like memory controller, DMA controller, and Touchpad, SD card. AXI uses hand shake mechanism for data transfer in all the five channels. The VALID signal is asserted from master when valid address or control and data information is available. The READY signal is asserted from slave when it can accept address or control and data information. The AHB Bridge buffers address, control and data from AXI4 drives the AHB peripherals and returns data and response signal to the AXI4. It decodes the address using an internal address map to select the peripheral. The bridge is designed to operate when the AHB and AXI4-Lite have independent clock frequency and phase. For every AXI channel, invalid commands are not forwarded and an error response generated. That is once a peripheral accessed does not exist, the AHB Bridge will generate DECERR as response through the response channel (read or write). And if the target peripheral exists, but asserts ERR, it will give a SLVERR response. The DUT used to verify in this project is LogiCORE IP AXI to AHB-Lite Bridge (v1.00a) from Xilinx.

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QSOCs

AXI TO AHB BRIDGE

2.1

Features and Limitations of the Bridge

The Xilinx AXI to AHB-Lite Bridge is a soft IP co re with the following features: AXI4 Slave Interface: AXI interface is based on the AXI4 specification Supports 1:1 (AXI to AHB) synchronous clock ratio Connects as a 32/64-bit slave on 32/64-bit 3 2/64-bit AXI4 Supports incrementing burst transfers (of length 1 to 256) Supports wrapping burst transfers of length 2, 4, 8, and 16 Supports fixed burst transfers (of length 1 to 16) Supports narrow transfers (8/16-bit transfers on a 32-bit bus and 8/16/32-bit transfer on a 64-bit data bus) Supports limited cache encoding and limited protection unit support Supports address/data phase time out AHB-Lite Master Interface.       

 

AHB-Lite Master Interface: Supports AHB-Lite interface Connects as a 32/64-bit Master on 32/64-bit 32/64 -bit AHB-Lite Supports single burst transfers Supports wrapping burst transfers of length 4, 8 and 16 and undefined burst length     

 

AHB-Lite master does not issue incrementing burst transfers that cross 1 kB address boundaries Supports limited protection control Supports narrow transfers (8/16-bit transfers on a 32-bit data bus and 8/16 /32-bit transfers on a 64-bit data bus)

Not Supported Features/Limitations AXI4 Slave Interface Data bus widths greater than 64 are not supported No registers are implemented because posted writes are not supported Locked, Barrier, trust zone, and exclusive operations are not supported Out-of-order read transaction completion Out-of-order write transaction completion Unaligned/Sparse transfers (holes in strobes) are not supported EXOKAY and DECERR responses to AXI4 are not supported Low-power state is not supported Secure accesses are not supported AHB-Lite Master interface Data bus widths greater than 64 are not supported No cacheable access support         

 

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QSOCs

AXI TO AHB BRIDGE

3. Test Bench Architecture

axi_ahb_top

axi_ahb_test axi_sequence Sequence

Sequence item

env Axi intf

SQR SQR

S C O R E B O A R D

Driver Monitor monitor

DUT

ahb_agent

driver Driver

SQR

Monitor monitor ahb_agent

ahb_seq_item

ahb_sequence

Testbench Architecture

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Ahb

AXI TO AHB

intf

BRIDGE

QSOCs

AXI TO AHB BRIDGE

4. AXI TO AHB BRIDGE BLOCK DIAGRAM Protocols Using: AXI4, AHB Lite – (with Data Width 32/64)

AHB Lite AXI SLAVE

Master

AHB

AXI

AXI WRITE

STATE

STATE

MACHINE

AHB

MACHINE

AXI READ STATE MACHINE

TIME OUT MODULE

AXI TO AHB BRIDGE

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QSOCs

AXI TO AHB BRIDGE

5. STIMULUS DRIVING FROM AXI MASTER

Write Address Write

Queue

Sequence Write Data Queue Driving Logic

Read Sequence

AXI Interface

Read Address Queue

Matching Queue

ID of Requests

Write Address RESPONSE

Response

HANDLER

Queue

Write Data Response AXI SEQUENCE

Queue

AXI DRIVER

Stimulus Driving Logic For AXI Master

1.) Axi to Ahb Bridge The bridge translates translates AXI4 transactions transactions into AHB AHB lite transactions. transactions. Data Bus may may be 32 or 64. 2.) Axi_seq_item,Ahb_seq_item Describes the transaction level items for the Stimulus Driving. For axi part it has size, address data like items. Page | 9

QSOCs

AXI TO AHB BRIDGE

3.) Sequence It creates sequences and drives it to the driver. Here we have write sequence and read sequence for the axi master. 4.) Axi /Ahb Sequencer It selects multiple sequences and serves as an arbiter for controlling transaction flow of UVM. 5.) Axi/Ahb Driver It drives the stimulus on to the DUT interface. 6.) Axi/Ahb Monitor It samples the DUT interface and captures the information there in transactions that are sent out to the scoreboard for further analysis. 7.) Axi/Ahb Agents For Axi to Ahb Bridge, we have two different signal interfaces, each of which have their own protocol. The UVM agent collects together a group of uvm_components focused around a specific pin-level interface. The purpose of the agent is to provide a verification component which allows users to generate and a nd monitor pin level transactions. 8.) Scoreboard It compares the data coming from axi and ahb interface. 9.) Environment The environment, environment, or env, is a container component component for grouping grouping together together subcomponents orientated orientated around a block, or around a collection of blocks at higher levels of integration.

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QSOCs

AXI TO AHB BRIDGE

6. STIMULUS DRIVING FROM AHB SLAVE

A H B

DUT AHB_DRIVER

S E

Ahb_Interface

Q U

AXI To AHB

E

Bridge

N C MEMORY

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E

QSOCs

AXI TO AHB BRIDGE

7. AXI TO AHB BRIDGE TEST PLAN

AXI TO AHB BRIDGE TEST BRIDGE TEST PLAN DUT: AXI to AHB BRIDGE

SL NO

TEST CASE

DESCRIPTION

FEATURE

STATUS

PASS/FAIL

BASIC TRANSACTIONS

1 reset_check

2 basic_write_transaction

3 basic_read_transaction

4 multiple_read_write

Checking the functionality of DUT when it is in reset condition by randomly driving data to all the inputs

During reset condition the ouputs of DUT will be some pre-configured value even if we toggle the values to the inputs

Writing to DUT with a basic write transfer of single beat and size as 4

Driving data and control information through 2 different channel to a peripheral and getting response from another channel through flow control signals READY and VALID

Writing to DUT with a basic Read transfer of single beat and size as 4 Randomly driving basic read and write transfers for multiple times

Completed PASS

Reading data from a peripheral using two different channels using flow control mechanisms

Completed PASS

Completed PASS

any number of transactions is possible in AXI to AHB bridge Completed PASS

BURST TRANSACTIONS

4 fixed_burst_single_beat

5

multiple_fixed_ burst_varying_length Page | 12

Driving data as a burst with single beat

Data is written to a fixed or fifo type memory

Repeated driving of data as fixed burst with varying length

AXI4 protocol supports maximum beats of 256

Completed PASS

Completed PASS

QSOCs

6 INCR_burst_single_beat

7 INCR_length_check

8 INCR_burst_length_2




12

WRAP_length_check

13 WRAP_burst_length_2




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AXI TO AHB BRIDGE

Driving data as burst of INCR with length as 1

Data is written as a burst by giving start address only.Then address is incremented w.r.t INCR parameters

Driving data as burst of INCR with varying Length

AXI4 protocol supports maximum beats of 256


AXI to AHB bridge maps INCR burst with length 2 as INCR2 in AHB side







Driving Data as a WRAP with varying Length

There is only of wrap 2,4,8 and 16.All others may throw an error

Driving data as burst of WRAP with length as 2

AXI to AHB bridge maps WRAP burst with length 2 as WRAP2 in AHB side

Driving data as burst of WRAP with length as 4

AXI to AHB bridge maps WRAP burst with length 4 as WRAP4 in AHB side

Driving data as burst of with length as 8

AXI to AHB bridge maps INCR burst with length 8 as WRAP8 in AHB side


AXI to AHB bridge maps INCR burst with length 2 as WRAP16 in AHB side

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

QSOCs

AXI TO AHB BRIDGE

Driving random bursts with 17 burst_beat_size_with_aligned_addr aligned address and varying size

AHB protocol supports aligned transfers only Completed PASS

UNALIGNED TRANSACTIONS

18

FIXED_unaligned_address

19 INCR_unaligned_address

20 WRAP_unaligned_address

Driving data as a FIXED burst with unaligned address with different size and lengths Driving data as a INCR burst with unaligned address with different size and lengths Driving data as a WRAP burst with unaligned address with different size and lengths

DUT converts unaligned transfers into aligned address using STROBE signals.AXI supports unaligned address,but AHB not DUT converts unaligned transfers into aligned address using STROBE signals.AXI supports unaligned address,but AHB not DUT converts unaligned transfers into aligned address using STROBE signals.AXI supports unaligned address,but AHB not

ATOMIC ACCESS & OTHER FEATURES

21

protection_check

22 exclusive_access

23 locked_access

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Driving random bursts with different levels of Protection Checking of Exclusive access of AXI by using LOCK signal by driving random bursts Checking of Locked access of AXI by using LOCK signal by driving random bursts

AXI protocol supports NORMAL,PRIVILEGED and SECURE access.But DUT doesn't support all the features. AXI4 supports LOCKED,NORMAL and EXCLUSIVE access to the slave.But DUT and AHB doesn't support AXI4 supports LOCKED,NORMAL and EXCLUSIVE access to the slave.But DUT and AHB doesn't support

Completed

Completed

Completed

QSOCs

AXI TO AHB BRIDGE

24 normal_access

Checking of Normal access of AXI by using LOCK signal by driving random bursts

AXI4 supports LOCKED,NORMAL and EXCLUSIVE access to the slave.But DUT and AHB doesn't support

25

Checking the cache unit of AXI

Bridge supports only limited features of Cache

26 out_of_order_txn

Checking out of Order Transaction

Bridge doesn't support out of order transaction.it helps finishing transfers from fast devices reather than slower.

27

outsatnding_address_check

Checking outstanding addresses transactions

AXI supports outstanding address transactions,but AHB doesn't.

28

data_interleaving_Check Driving random burst with out of boundary conditions

AXI supports 4KB locations and AHB supports 1KB locations

29

cache_support_check

boundary_cross_check

ERROR RESPONSES

30 error_response_check

Cheecking for different errors AXI having responses OKAY,EXOKAY,DECERR associated and AHB having OKAY withAXI to AHB and ERROR. bridge CORNER CASES

31 same_id_check

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Giving Same Id's to different address for a transaction

QSOCs

AXI TO AHB BRIDGE

8. Functional Coverage

Functional Coverage Sl No

Cover group

1

Cover Point

Access

2

Description Write Read

Fixed

It is writing to the same address .DUT converts unaligned transfers into aligned address using STROBE signals.AXI supports unaligned address,but AHB does not

Increment

DUT converts unaligned transfers into aligned address using STROBE signals.AXI supports unaligned address,but AHB not

5

Wrap

Here the address will wrap after the address boundary(Here its 4)

6

Protect_NSD

7

Protect_PSD

8

Protect_NND

3

Burst

4

CG-AXI

9 10

Protect

Protect_NSI Protect_PSI

11

Protect_NNI

12

Protect_PNI

13

Protect_PNI

14

Cache

15 16 17

Page | 16

Cache Okay

Response

EXOKAY SLVERR

Cache

Status

Hit/Fail

QSOCs

AXI TO AHB BRIDGE

18 19

DECERR Address_type

20 21

Addr_align Addr_unalign

Address

0-1000

Divisible by 4

22

Single

This will transfer single transfer i,e single beat

23

Increment

24

Undefined

Undefined length burst that has burst of length one

25

INCR4

The previous address is increments by 4

26

INCR 8

The previous address increments by 8

27

INCR 16

The previous address is incremented by 16

Burst

Here to single address the data is written

28 29

Wrap

30

Wrap 4

The address will incrent with 4 wrap to boundary

Wrap 8

The address will increment by 8 and wrap to the boundary

Wrap 16

The address will increment by 16 and wrap to the boundary

Idle

Undefined length burst that has burst of length one

Busy

Burst is taking place but transfer cannot take place immediately , Undefined length can have busy as last transition

Non Sequential

It is single or first transfer of the burst . Single transfer on the bus are treated as burst of length one

31

32

33

34

35

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Transaction Type

QSOCs

AXI TO AHB BRIDGE

36

Sequential

If its sequencial address is related to the previous transfer , The control information is same as previous transfer

37

Byte

When size is byte

38 39

Size

40 41 42

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Half_word Word Double Word

When size is half_byte

Address 1000 to 2000

Address lying between 1k and 2k

QSOCs

AXI TO AHB BRIDGE

9. STRUCTURE FOR AXI TO AHB BRIDGE PROJECT

AXI_TO AHB Bridge

doc

script

sim

src

testlib

verif

agent

env

Directory Structure 

Doc : Keep all the related documents in this file



Script : Keep all the Scripting file like run_test ,regression files



Sim : All the simulations has to done here



Src : keep all the source rtl file in this directory



items,sequences,test files for Testlib : it having all the sequence items,sequences,test verification



:Includes three sub directories agent, env and intf Verif :Includes 

Intf :Keep all the interface files in here



environment, top, scoreboard scoreboard and packages. packages. Env: it consist environment,



Agent : it consists sequencer, driver monitor related files

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intf

Bridge Axi Ahb

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