2.1

Introduction

2.2 2.2

The Sili Siliccon/ on/Sil Silicon icon Dioxi ioxide de Sys System tem

2.3 2.3

Band and Bendin ndingg in the MOS MOS Capa Capaccitor itor

2.4 2.4

Solu Soluti tion on of Pois Poisso son' n'ss Equa Equati tion on for for the the MOS MOS Capa Capaci cito tor r 2.4. 2.4.11 Depl Deplet etio ionn Appr Approx oxim imat atio ionn 2.4. 2.4.22 The Thre hresho shold Volt oltage age 2.4.3 Accurate Sol Solution 2.4.4 2.4.4 Thresh Threshold old Voltag Voltagee usin usingg the the Accur Accurate ate Soluti Solution on

2.5 2.5

Capa Capaci cita tanc ncee-Vo Volt ltag agee (CV (CV)) Plo Plott of of the the Idea Ideall MOS MOS Capa Capaci cito tor r 2.5.1 2.5.1 SmallSmall-sig signal nal Capaci Capacitan tance ce and Equiv Equivale alent nt Circu Circuit it 2.5.2 2.5.2 Low-fr Low-frequ equenc encyy Capaci Capacitan tancece-Vol Voltag tagee (LFCV) (LFCV) Charac Character terist istics ics 2.5.3 2.5.3 High-f High-freq requen uency cy Capac Capacita itance nce-Vo -Volta ltage( ge(HFC HFCV) V) Chara Characte cteris ristic ticss 2.5.4 Deep De Depletion 2.6 2.6 Conc Conclu lusi sion onss

Chapter 2

THE IDEAL MOS CAPACITOR 2.1

Introduction

In this chapter, we discuss discuss the physics of the ideal MOS MOS capacitor. This includes a description description of the semiconductor surface and the semiconductor insulator interface, a solution of the Poisson equation to find the charge in the semiconductor, and the derivation of an expression for threshold voltage V T T. We will also derive the capacitance-voltage (CV) characteristics of the ideal MOS capacitor. By ideal , we mean an MOS system in which the insulator has no trapped charges or free carriers, the semiconductor-insulator interface has no defects (like interface states), there is no work function difference between the semiconductor and the highly-conducting gate material, and quantum effects are ignored. These contraints will will be relaxed in the next chapter. chapter. The MOS capacitor is an important important device for several reasons. reasons. Firstly, it allows us to understand understand the basic MOS phenomena for a simple simple one-dimensional structure. structure. Secondly, the MOS capacitor capacitor is an important test structure used to obtain information about the MOS system, usually in a simpler manner than can be done with a MOS transistor. Finally, the MOS capacitor is an important important semiconductor device in its own right, used in CCDs , analog circuits, memories and so on.

2.2

The Silicon/Silicon-Dioxide Silicon/Silicon- Dioxide System

The silicon/silicon-dioxide (Si/SiO2) system is the most common semiconductor-insulator system used in MOS devices. Indeed, as mentioned in Chapter Chapter 1, it is the outstanding properties of the Si/SiO Si/SiO 2 interface which has made silicon technology dominant today. Figure 2.1 shows the physical structure of the MOS capacitor. The semiconductor is usually silicon. We will consider consider mainly the case of a p-type substrate, substrate, which corresponds to an n-channel n-channel MOS transistor. The insulator is usually silicon dioxide (SiO2) and its thickness t ox ox is in the range 2-50 nm (20– 500 Å). The top “metal” may be aluminum aluminum or some other metal, metal, or heavily-doped polysilicon polysilicon in the case of silicon-gate technology. technology. The metal (or polysilicon) polysilicon) layer is called the gate to which a gate voltage voltage V G can be applied.

Figure 2.1

Phys Physiical cal struc ructur ture of a MOS MOS capac capacito itor. r. Note Note that that this is is not drawn to scale; the typical thickness of the wafer is 300 µ m, of the oxide (t ox ox) 10 nm, and of the polysilicon gate 100 nm.

Chapter 2

THE IDEAL MOS CAPACITOR 2.1

Introduction

In this chapter, we discuss discuss the physics of the ideal MOS MOS capacitor. This includes a description description of the semiconductor surface and the semiconductor insulator interface, a solution of the Poisson equation to find the charge in the semiconductor, and the derivation of an expression for threshold voltage V T T. We will also derive the capacitance-voltage (CV) characteristics of the ideal MOS capacitor. By ideal , we mean an MOS system in which the insulator has no trapped charges or free carriers, the semiconductor-insulator interface has no defects (like interface states), there is no work function difference between the semiconductor and the highly-conducting gate material, and quantum effects are ignored. These contraints will will be relaxed in the next chapter. chapter. The MOS capacitor is an important important device for several reasons. reasons. Firstly, it allows us to understand understand the basic MOS phenomena for a simple simple one-dimensional structure. structure. Secondly, the MOS capacitor capacitor is an important test structure used to obtain information about the MOS system, usually in a simpler manner than can be done with a MOS transistor. Finally, the MOS capacitor is an important important semiconductor device in its own right, used in CCDs , analog circuits, memories and so on.

2.2

The Silicon/Silicon-Dioxide Silicon/Silicon- Dioxide System

The silicon/silicon-dioxide (Si/SiO2) system is the most common semiconductor-insulator system used in MOS devices. Indeed, as mentioned in Chapter Chapter 1, it is the outstanding properties of the Si/SiO Si/SiO 2 interface which has made silicon technology dominant today. Figure 2.1 shows the physical structure of the MOS capacitor. The semiconductor is usually silicon. We will consider consider mainly the case of a p-type substrate, substrate, which corresponds to an n-channel n-channel MOS transistor. The insulator is usually silicon dioxide (SiO2) and its thickness t ox ox is in the range 2-50 nm (20– 500 Å). The top “metal” may be aluminum aluminum or some other metal, metal, or heavily-doped polysilicon polysilicon in the case of silicon-gate technology. technology. The metal (or polysilicon) polysilicon) layer is called the gate to which a gate voltage voltage V G can be applied.

Figure 2.1

Phys Physiical cal struc ructur ture of a MOS MOS capac capacito itor. r. Note Note that that this is is not drawn to scale; the typical thickness of the wafer is 300 µ m, of the oxide (t ox ox) 10 nm, and of the polysilicon gate 100 nm.

The band diagram in equilibrium ( V G = 0 V) of the ideal MOS capacitor capacitor is shown in Fig 2.2. 2.2. Here the semiconductor is p-type silicon, the oxide (or insulator) is SiO 2 and the gate is made of a hypothetical conductor whose work function φ m is the same as that of silicon φ s, so that the work function difference φ ms = 0 V. Note some some importa important nt definitio definitions ns and values values in Fig. 2.2. 2.2. The silico siliconn bandgap bandgap (at room room temperature) is is 1.12 eV, and the oxide oxide bandgap is 9.1eV. The electron affinity χ in silicon is 4.1 eV and in the oxide 0.9 eV, so that the electron barrier at the Si/SiO 2 interface is 3.2 3.2 eV. (The hole barrier barrier is much larger at 4.9 eV). The silicon bulk potential φ B is defined as the difference between the intrinsic fermi level ε i and the fermi level ε f in the bulk. Figure 2.2

Band diagram in equilibrium of an idea ideall MOS MOS capa capaci cito torr for for whic whichh φ ms = 0. (Not to scale.)

We know from basic basic semiconductor semiconductor theory [2.1–2.3] that p

o

= ni exp{( ε i − ε f ) / kT } ,

(2.1)

where po is the equilibrium number of holes in the p-type semiconductor, ni is the intrinsic carrier density, temperature. We can write (assuming (assuming complete ionization ionization of the k is Boltzmann’s constant and T is the temperature. acceptor impurities, and that the acceptor density N a >>ni), φ B =

kT q

ln

N a , ni

(2.2)

N a = 1016 where N a is the doping (acceptor) doping and q is the electronic charge. For a typical value of N N a =1017 cm –3, cm –3 ,and ni = 1.5 X 1010 cm –3 the bulk potential φ B = 0.34 V at room room temperature. temperature. For N N a.a. φ B = 0.38V; because of the ln dependence in Eq. (2.2), φ B is a weak function of N

From Fig 2.2, we can also see why silicon dioxide is such a good material for use in MOS devices. Besides the fact that SiO 2 (especially when thermally grown) forms an almost ideal interface with silicon, producing very few defects, we see that (1) it has a large bandgap (9.1eV) and therefore very few intrinsic carriers, and (2) it has large barriers for both electrons and holes in silicon (as well as the gate), so that the carriers can be effectively contained in the silicon, and do not get injected easily into the insulator.

2.3

Band Bending in the MOS Capacitor

This section explores what happens when a voltage is applied to the gate of the MOS capacitor, and the different band bendings that result at the semiconductor surface. For the ideal MOS capacitor that we are currently considering, the equilibrium condition at V G = 0 V is also the flat-band condition. In this case the bands in the silicon (and oxide) are flat (Fig 2.3a). As a consequence there is no net charge in the semiconductor or on the metal and the electric field is zero everywhere. It may be recalled from semiconductor theory that the presence of an electric field E causes a bending of the bands, given by qE =

d ε i

d ε c dx

=

dx

d ε v =

dx

.

(2.3)

When the gate voltage applied is negative (V G < 0 V), majority carriers (holes) are attracted to the surface of the semiconductor from the bulk. The excess carriers produce a positively charged layer at the surface, which is matched by negative charge at the metal-oxide interface. There is an electric field in the oxide which penetrates slightly into the semiconductor, producing band-bending, as shown in Fig. 2.3b. Note that the fermi levels in the semiconductor and metal are separated by qV G. This condition is called accumulation since it results in an accumulation of majority carriers at the Si/SiO 2 interface.

Figure 2.3

Band bending in the ideal MOS capacitor for various conditions. (a) Flat bands (b) Accumulation

(c) Depletion Mid-gap.

(d) Inversion (e)

We now define the surface potential ψ s . This is the total amount of band bending at the surface of the semiconductor measured with respect to the bulk. The band bending can be measured on ε ,i ε c or ε v. In this case the bands bend upwards and ψ s (by definition) will be considered to be negative. Note that the value of ψ s can never be very large, since that would imply a very large number of holes at the surface (remember that the number of holes increases exponentially with reduction in the difference between ε f and ε i , p0 = N v exp {− ( ε f − ε v )/kT } ). The surface could even become degenerate as the valence band crosses the fermi level. Such a large number of holes would imply large fields in the oxide, and therefore large gate voltages to sustain such a charge. For typical applied voltages in accumulation, ψ s is limited to −0.1-0.2 V. When the gate voltage applied is positive and not too large (V G > 0 V), the majority carriers are repelled away from the surface of the semiconductor producing a depletion region. The depletion region contains a negative charge corresponding to the ionized acceptors (much like the depletion region in an n + p junction). The bands now bend downwards and ψ s is positive (Fig 2.3c). This condition is known as depletion. Finally, when the gate voltage applied is positive and sufficiently large, the bands in the semiconductor bend enough that the conduction band comes close to the fermi level. This means that, the surface of the semiconductor layer has effectively become n-type, and there are mobile minority carriers (electrons) present at the surface (Fig 2.3d). This condition is known as inversion, because the surface has been effectively inverted from p-type to n-type. It is the carriers in the inversion layer which contribute to conduction in a MOS transistor. A common definition of the onset of inversion is that the surface is as n-type as the bulk is p-type, that is , n s = po. This implies that ni exp {− ( ε f − ε

is

)/kT } = ni exp {− ( ε

ib

− ε f )/kT },

(2.4)

where the subscript s is used for the surface and b for bulk. This gives, at inversion, ψ s = 2φ B .

(2.5)

In inversion, the negative charge in the inversion layer adds to the negative charge in the depletion region. As in the case of accumulation, the bands in inversion cannot bend much further than ψ s = 2φ B , as this would put too much charge in the conduction band at the surface, and very large voltages would be required at the gate to support this charge. ‘ An intermediate condition of interest is the mid-gap condition. In this case, the semiconductor surface is intrinsic (Fig 2.3e), and ψ s = φ B. Sometimes the condition φ B < ψ s < 2 φ B is referred to as weak inversion, and ψ s ≥ 2φ B , as strong inversion . In summary, for an ideal MOS capacitor, the conditions of interest are Accumulation

ψ s < 0

Flat-band Depletion Mid-gap Weak Inversion Strong Inversion

ψ s = 0 2φ B>ψ s>0 ψ s = φ B φ B < ψ s < 2 φ B ψ s ≥ 2φ B

The weak inversion condition is often subsumed as part of depletion, since there are yet very few mobile minority carriers. An important question which can be asked is: in a non-equilibrium condition ( V G ≠ 0 V) is it possible to draw a fermi level in the semiconductor, as we have been doing in Fig 2.3? As is well known (for a p-n junction, for example), for non-equilibrium conditions, quasi-fermi levels should be used. In the MOS capacitor, fortunately, the current flowing is almost zero because of the presence of the intervening insulator. Since J n = − n µ n∇ ε fn and J p = + p µ p ∇ ε fp where ε fn and ε fp are the quasi-fermi levels [3], we can write (using J n = J p = 0) ∇ ε fn ≅ ∇ ε fp ≅ 0 in the semiconductor. Now, ε fn = ε fp deep in the bulk; therefore ε fn = ε fp throughout the semiconductor, and we can conveniently designate this common level as the fermi level ε f even in non-equilibrium. The fact that we are indeed looking at non-equilibrium conditions becomes clear when we try to draw fermi levels in the oxide. Now we need to recognize that though the oxide is an excellent insulator, it is not, in reality, an ideal one. So a small leakage current will indeed be flowing in the MOS structure. Though for the semiconductor, this current is small enough that the argument in the last paragraph holds, this is not so for the oxide. Here, because n and p are also very small, ∇ ε fn and ∇ ε fp are not zero, and we do have distinct, non-coincident quasi-fermi levels in the oxide. These quasi-fermi levels are difficult to determine without knowing the details of the conduction process in the oxide, so we normally would not draw the fermi or quasi-fermi levels in the oxide, as in Fig 2.3.

2.4

Solution of Poisson's Equation for the MOS Capacitor

We now solve Poisson's equation to determine quantitatively the band bending in the oxide and the semiconductor, as well as the charge in the semiconductor (the oxide in the ideal capacitor is assumed to contain no charge). We also compute the threshold voltage of the MOS system in this section. First, Poisson's equation is solved using the depletion approximation, and later more accurately by including the effects of the mobile carriers as well. 2.4.1

Depletion Approximation

The depletion approximation is often used in the analysis of semiconductor devices. It divides the semiconductor into two regions, one of which is depleted of free carriers and therefore has a space charge density corresponding to the ionized impurities, and the other where the free carriers neutralize the ionized impurities and which is therefore neutral (or quasi-neutral). The depletion approximation is extremely useful for getting a physical feel for the problem without getting mired right away in tedious calculations. In the context of the MOS capacitor, we focus attention on the depletion (including weak inversion) condition. The band bending is shown again for this condition in Fig 2.4. The depletion approximation allows us to divide the semiconductor into two regions A and B. In Region A, we assume

that there are no mobile carriers (as can be seen by the fact that the fermi level is quite far from both band edges), so that the space charge density is given by ρ (x) = qN a. In Region B, we assume that there is no space charge , ρ (x). We further assume that there is a sharp transition between the two regions at a point x = xd called the depletion width. The postulate of the depletion edge which demarcates the two regions is the crux of the depletion approximation; in reality there is gradual transition between the fully depleted region near the surface and the neutral region deep in the bulk. There is no band bending in Region B because the space charge density there is zero. In Region A, the band ending, designated by ψ (x), can be easily found by solving Poisson's equation: 2 d ψ ( x) 2 dx

= −

ρ ( x) ε s

= +

qN a ε s

.

(2.6)

Figure 2.4

Band bending for an ideal MOS capacitor in depletion, illustrating the two regions in the semiconductor arising from the use of the depletion approximation.

We assume here that the semiconductor is uniformly doped, that is, N a is constant. The solution of Eq. (2.6), with the reasonable boundary conditions ψ = 0 and d ψ /dx = 0 at x = xd is ψ ( x)

=

qN a ( x − xd )2. 2ε s

(2.7)

This shows that the band-bending in the semiconductor is parabolic. The surface potential ψ s can be found by putting x = 0 in Eq. (2.7): ψ s

or alternatively,

=

qN a 2ε s

2

x d ,

2ε sψ s

xd =

qN a

.

(2.8)

In depletion, the total charge in the semiconductor QS is just the depletion charge Q D, given by Q D = − qN a xd . Using Eq. (2.8), Q D =

−

2ε

s

(2.9)

qN ψ a s

The value of V G required to produce the surface potential ψ s can be easily computed as follows. The charge on the gate QG is equal to and opposite that of Q D . Using Gauss' law, the electric field emanating from the gate into the oxide is E ox =

QG ε ox

=

2ε s qN aψ s ε ox

.

(2.10)

Since there are no charges in the oxide, the electric field is constant there, with the result that the bands bend linearly in the oxide. The voltage drop V ox across the oxide is then simply V ox = E ox t ox =

2ε s qN aψ s C ox

,

(2.11)

where t ox is the oxide thickness, and C ox ≡ ε ox / t ox is defined as the oxide capacitance per unit area. By Kirchoff's voltage law, V G is given by V G = ψ s + V ox. So, V G = ψ s +

2ε s qN aψ s

.

C ox

(2.12) So, given ψ s, V G can be computed using Eq. (2.12). Altematively, if V G is given, a solution of the quadratic equation reveals ψ s. The electric field in the oxide (Eq.(2.10)) can alternatively be found as follows. From Eq. (2.7), the electric field at the surface of the semiconductor, E s (= − d ψ /dx at x = 0) is E s =

qN a ε s

x d .

(2.13)

Using Eq. (2.8), E s =

2ε s qN aψ s

ε s

.

(2.14)

Since the D vector is continuous across the semiconductor oxide-interface (there being no charge at the interface in depletion), we can write ε s E s = ε ox E ox.

(2.15)

This then results in the same E ox as Eq. (2.10). A plot of the potential V ( x) versus x is shown in Fig. 2.5. It can be seen that V ( x) varies linearly in the oxide and parabolically in the semiconductor, and there is a discontinuity in the slope at the surface due to the difference in the dielectric constants.

Figure 2.5

Plot of the potential V ( x) in a MOS capacitor as obtained from the depletion approximation. The discontinuity in the slope at x = 0 (the Si/SiO2 interface) is due to the change of dielectric constant.

2.4.2

The Threshold Voltage

The depletion approximation can be used to find the threshold voltage of the MOS capacitor. The threshold voltage is one of the most important parameters of a MOS system. It is defined as the gate voltage required to just produce inversion at the surface. We saw in Section 2.3 that the onset of inversion corresponds to ψ s = 2φ B . Using this condition, the threshold voltage V T of the ideal MOS capacitor can be written, from Eq. (2.12), as: V T = 2φ B +

4ε S qN a φ B C ox

.

(2.16)

This simple equation is quite accurate and very useful. It tells us, for example, that as doping increases, V T increases (due to an increase in φ B as well as N a in the numerator of the second term), and that as oxide

thickness decreases, V T decreases. For a typical doping of N a = 1x1016 cm −3 and an oxide thickness of t ox = 25 nm, the threshold voltage of an ideal MOS system is V T = 0.67 + xx = yy. For N a = 1x1017 cm −3 and t ox = 10 nm, V T = zz V. What if a gate voltage larger than V T is applied? As argued in Sec.2.3, the band bending in the semiconductor will hardly exceed 2 φ B. This means that the surface potential is, for all practical purposes, pinned to about 2φ B. This in turn implies that the depletion width will not go beyond a maximum value given by 2ε s

xdmax =

qN a

2φ B

,

(2.17)

and therefore the charge in the depletion region will not exceed Q Dmax =

4ε s qN a φ B

.

For V G > V T , charge in the inversion layer Q I cannot be ignored. The total semiconductor charge Qs is now QS = Q I + Q Dmax ,

(2.18)

and this total charge is balanced on the gate side. Using this in Eq. (2.10), we get V G = 2 φ B +

4ε S qN a φ B C ox

+

Q I C ox

,

(2.19) or, using Eq. (2.16), Q I = C ox (V G - V T ) .

(2.20)

This equation tells us that beyond threshold , the inversion layer charge increases linearly with V G , and the device behaves like a parallel plate capacitor of value C ox per unit area. The depletion approximation is quite successful in giving some idea of what is happening in the MOS capacitor, especially in the depletion condition. For a more accurate analysis, especially in accumulation and inversion when the presence of mobile carriers near the surface cannot be ignored, the full Poisson equation needs to be solved without making the depletion approximation. This is done in the next section. 2.4.3

Accurate Solution

We now solve the Poisson equation accurately. Poisson's equation can be written for the semiconductor as [2.1, 2.4] d 2ψ dx 2

= −

ρ ( x ) ε s

(2.21) In the expression for ρ (x) we will now include the mobile carriers also, so that −

ρ (x) = [ N d + − N a + p(x) – n(x)] ,

(2.22)

where N d + and N a− are the ionized donor and acceptor impurities respectively, and p(x) and n(x) are the position-dependent densities of mobile holes and electrons. For generality, we assume that the semiconductor has both acceptors and donors; however, they are uniformly distributed so that there are not

functions of x. Furthermore, we can usually assume (except at very low temeratures) that the impurities are fully ionized, so that N d + = N d and N a − = N a. The mobile carriers are given by (refer to Fig 2.4) qψ (x) kT

n(x) = no e

−qψ ( x ) kT

p(x) = p o e

,

(2.23) where no and po are the (equilibrium) densities in the bulk of the semiconductor where ψ = 0. As expected, as the bands bend downwards ( ψ positive), n increases exponentially as the conduction band comes closer to the fermi level, and p decreases exponentially. Note that Eqs. (2.23) are based on MaxwellBoltzmann statistics, and will not be valid if the conduction or valence bands come too close to the fermi level. In that case, Fermi-Dirac statistics would have to be used, which would, however, make the equations analytically intractable. In the bulk, where ψ = 0, space charge neutrality exists. From Eq. (2.22), N d – N a = po – n o in the bulk, and therefore everywhere, since N d and N a are not functions of x. So, Poisson's equation can be written as d 2ψ dx 2

=

q ε s

{ po(e

−qψ

qψ

kT

kT

– 1) – no(e

– 1)} .

(2.24) Integrating Eq.(2.24) with respect to ψ from deep in the bulk ( x = ∞ ) where ψ = 0 and d ψ /dx = 0, towards the surface and using (d 2ψ /dx2) · d ψ = (d ψ /dx) · d (d ψ /dx), we get

ψ

d ψ dx

∫ 0

(

d ψ d ψ ) d ( ) dx dx

q

= –

ε s

∫

− qψ

qψ

{ po (e k T − 1) − no (e k T − 1) }d ψ .

(2.25)

0 This gives 2

2

d ψ = − 2q p o kT ε s dx

−qψ qψ n −1 + o e kT + kT p o

qψ qψ e kT − −1 . kT

(2.26)

Since the electric field E at any point x is – d ψ /dx, we can write E =

±

2

kT qL D

qψ no , , kT p o

F

(2.27)

qψ no , where F = kT p o

−qψ n qψ −1 + o e kT + kT p o

1/ 2

qψ qψ e kT − −1 kT

,

(2.28) and L D is the extrinsic Debye length given by kT ε s

L D =

2

q N a

.

(2.29)

In Eq. (2.27), the positive sign holds for ψ > 0 (bands bending downwards), and the negative sign holds for ψ < 0. This equation gives us the value of electric field at any point in the semiconductor where we know ψ . Unfortunately we cannot find ψ (or d ψ /dx) as a function of x, but being able to find the electric field allows us to find the charge QS in the semiconductor. The electric field at the surface E s is given by E s = ±

2

kT qL D

qψ s kT

F

,

. p o

no

(2.30)

Using Gauss' law, the total charge QS in the semiconductor is given by

QS = −ε s E s =

2

kT qL D

−qψ n qψ ε s e kT + 1 + o − p o kT

1/ 2

qψ qψ e kT − −1 kT

.

(2.31) This equation allows the total charge in the semiconductor QS to be calculated, including both ionized impurities and mobile carriers, since all these have been taken into account in the Poisson Equation (2.21). We analyze Eq. (2.31) under the different biasing conditions of the MOS capacitor. (a) Accumulation (ψ s < 0) For ψ s < 0, the term exp(– qψ s/kT ) in F dominates, and as a consequence, in accumulation, Q s ≈ +

2

kT qL D

ε s e

−

qψ s

2 kT

(2.32) Note that the term exp(– qψ s/kT ) in F arose from the term po exp(– qψ /kT ) in Eq. (2.24), and this is the majority carrier term. (b) Flat Bands (ψ s = 0) At flat bands, ψ s = 0, and as can be seen from Eq.(2.31), Q s = 0,

as expected.

(2.33)

(c) Depletion (0 < ψ s < 2φ B) As ψ s goes positive, and the semiconductor enters the depletion condition, the dominant term is qψ the {( s /kT ) − 1} term in the first parentheses of Eq. (2.31). Although the exp(qψ s/kT ) term within the second parentheses starts to become large, its premultiplicative constant no /po (which is << 1) ensures that its effect is yet negligible. So in depletion, 1

qψ s 2 Q s ≈ − 2 −1 ε s qL D kT kT

(2.34)

The term {( qψ s /kT ) − 1} arises from the integration of po (and hence N A ) in Eq. (2.24) which is the dominant charge in the semiconductor in depletion. It can easily be seen that (for qψ s /kT >> 1), Eq. (2.34) is the same as Eq. (2.9) found using the depletion approximation. This confirms the relative accuracy of Eq. (2.9) when the MOS capacitor is in depletion. −

(d) Inversion (ψ s > 2 φ B) When ψ s becomes sufficiently positive (≥ 2φ B), the exp(qψ s/kT ) term becomes sufficiently large to overpower its pre-multiplicative no /po term. So, in strong inversion,

Q s

≈ − 2

kT qL D

ε s (

no p o

)

1

qψ s

2 e 2kT

(2.35) The exp(qψ s/kT ) term in F arose from n in Eq.(2.22) and hence refers to minority carriers, which eventually become dominant in strong inversion. Note that the total inversion layer charge goes as exp( qψ s/2kT ), and therefore increases rapidly for even small increases in ψ s. The number of electrons n s at the surface ( x = 0), of course, increases as exp(qψ s/kT ) (as long as Maxwell-Boltzmann statistics hold), but since the inversion charge includes electrons further away as well, the total Q I goes only as exp(qψ s/2kT ). A numerical solution of Poisson's equation can give ψ s and hence n(x). Such a plot is shown in Fig 2.6[2.5], which tells us that the inversion layer thickness is ∼ 5 nm, and that n(x) increases rapidly for even a small increase in ψ s.

Figure 2.6

Simulated plot of the number of electrons n( x) near the surface in a MOS capacitor for two values of ψ s. After Taur and Ning [2.4].

A plot of QS (on a log scale) versus ψ s, from Eq. (2.31), is shown in Fig.2.7 for N a = 1x 1016 cm−3 shows the exponential dependance of QS in strong accumulation, and inversion, and the relatively slow dependence of QS on ψ s in depletion (including weak inversion).

Figure 2.7

Plot of Q s versus ψ s for an ideal MOS capacitor for N a = 1x 1016 cm –3 showing the various regions of operation.

The chare Q I in the inversion layer is the total semiconductor charge QS less the charge in the depletion region Q D: Q I = Q s − Q D

=− 2

kT qL D

n qψ s ε s ( −1) + o p o kT

qψ s

e

kT

1

2

1 qψ s 2 − ( −1) , kT

(2.36) where only the relevant terms have been retained. This equation will be useful when we wish to compute the current carried by inversion layer charge in the MOS transistor. The condition ψ s = 2φ B, which is the one we have been using to designate the onset of inversion, is (as seen from Fig 2.7) too early. At this value of band bending , the surface has just become as n-type as the bulk is p-type. This means that for a p-type semiconductor doped to 1x1016 atoms/cm−3 , the surface

concentration n s has just reached 1x1016 cm−3. Considering that the electron density falls off very steeply (Fig 2.6), there are not near enough carriers in the inversion layer. Two other definitions for the onset of inversion have been proposed. The first, suggested by Lindner [2.4, 2.6], is that the contribution to the (square of the) surface electric field by the minority carrier charge is the same as that by the charge in the depletion region. From Eqs. (2.30) and (2.28), this gives i qψ s −1 = n0 kT p 0

qψ si

e

kT

,

(2.37) where ψ i s refers to the surface potential at the onset of inversion. Unfortunately, this is a transcendental equation; however an approximate solution of this is [2.4]: i

ψ s

= 2.1φ B + 2 kT . q

(2.38)

Another condition sometimes used is the Brews' condition [2.7], which defines the onset of strong inversion as the point where charge in the inversion layer Q I is equal to charge in the depletion region Q D. Using Eq. (2.36), this results in the condition

qψ i ( s −1) + n o kT p o

qψ si

e

kT

1

2

−

qψ si

(

kT

−1)

1

=

2

(

qψ si kT

−1)

1

2

,

(2.39) or,

qψ si −1 3 = kT

no p o

qψ si exp kT

(2.40)

−

−

i For N a = 1x1016 cm 3 and N a = 1x1017 cm 3, the values of ψ s at the onset of inversion as computed by the different methods are given in Table 2.1.

i

Table 2.1 Comparison of ψ s obtained by different methods for two dopings i ψ s

at onset of inversion (V)

Definition −

N a=1x1016cm 3

−

N a = 1x 1017 cm 3

ψ s = 2φ B

0.697

0.817

Exact Lindner [Eq.(2.37)]

0.785

0.909

Approx .Lindner [Eq.(2.38)]

0.784

0.910

0.814

0.938

Brews' [Eq.(2.40)] The three values for N a = 1016 cm−3 are shown in Fig 2.7. It can be seen that the Lindner and Brews conditions offer a better estimate for the distinction between depletion (or weak inversion) and strong inversion. Nevertheless, because of the simplicity of the ψ s = 2φ B condition, it continues to be widely used. This completes our discussion of the accurate solution of Poisson's equation. Despite our inability to compute ψ and E as a function of x into the semiconductor, the fact that we would compute QS accurately makes this solution very useful. Nevertheless, it is worthwhile to point out (or reiterate) the limitations of this "accurate" solution of the ideal MOS capacitor. Firstly, it is a one-dimensional solution, in which the dopant distributions are assumed to be uniform. Second, it uses Maxwell-Boltzmann and not the more accurate Fermi-Dirac statistics. Third, it ignores quantum effects which become important when large fields exist at the semiconductor surface, for which the Schrödinger equation must be solved selfconsistently with the Poisson equation.

2.4.4

Threshold Voltage using the Accurate Solution

The gate voltage V G of the ideal MOS capacitor is still given by Eq. (2.12a) where V ox = + (QG /C ox) = – (QS /C ox), where QS is given by the accurate Eq. (2.31). Hence, the gate voltage for any surface potential ψ s is V G =

±

2

kT

ε s

qL D C ox

qψ s kT

F

,

p o no

+ ψ s ,

(2.41)

where the positive sign is used for ψ s positive. For the MOS capacitor in any condition, including accumulation and inversion, V G for a given ψ s can be found analytically from Eq. (2.41). This was something we were not able to do with the depletion approximation. A plot of ψ s versus V G for N a = 1x1016 cm−3 and t ox = 25 nm is shown in Fig. 2.8. It can be seen that in both accumulation and strong inversion, the value of ψ s does tend to saturate, but does not undergo a hard limit as implied by the depletion approximation.

Figure 2.8

A plot of ψ s versus V G for an ideal MOS capacitor. Note that the Brews condition provides a better estimate of the onset of inversion than the ψ s = 2φ B condition.

The threshold voltage V T of the ideal MOS capacitor can be found by using Eq. (2.41) with substituted for ψ s: V T =

2

kT ε s qL D C ox

i

F (

qψ s kT

,

no po

) + ψ s , i

i ψ s

(2.42)

i where ψ s can be obtained from any appropriate definition of Table 2.1. Two of these are marked in Fig 2.8, and again it can be seen that, from the point of view of the onset of saturation of ψ s, the Brews condition provides a better estimate that the 2 φ B condition. −

The values of threshold voltage V T for an ideal MOS capacitor with N a = 1x1016 cm 3 and t ox = 25 i nm for different ψ s conditions, using the accurate solution and the depletion approximation, are shown in Table 2.2. It can be seen that the values of V T found by the accurate solution are not too different from those by the depletion approximation. This is understandable since the depletion approximation is not too bad as long as we do not go too far into accumulation or inversion. All the calculations done so far have been for a p-type substrate. The equations for an n-type substrate are very similar. For example, Eq. (2.31) for QS would have ψ s replaced by − ψ s and (no /po) replaced by ( po /no); and same with Eq. (2.42) for threshold voltage plus a reversal in sign for F. For an ideal MOS capacitor with the same doping and oxide thickness, this would result in a V T which is negative for an n-type substrate, but equal in magnitude to that of a capacitor with a p-type substrate. Comparison of V T using two definitions and the depletion approximation as well as accurate solution.

Table 2.2

Definition of ψ

i s

Threshold Voltage V T (V) N a = 1016 cm –3 t ox =25nm

Accurate Solution

Depletion Approx.

2φ B

1.047

1.047

Lindner

1.301

1.099

2.5 Capacitance-Voltage (CV) Plot of the Ideal MOS Capacitor The capacitance voltage (CV) characteristic of the MOS capacitor is a plot of small signal capacitance C as a function of the gate voltage V G. It is an important plot because it gives a great deal of information about the MOS structure, and makes the MOS capacitor a useful diagnostic tool. 2.5.1

Small -signal Capacitance and Equivalent Circuit

The small-signal capacitance is defined, for the MOS capacitor, as C =

dQ G dV G

,

(2.43)

where QG is the charge on the gate. Since V G = V ox + ψ s and QG = − QS , we can write

1

C

=

−

dV ox dQ S

−

d ψ s dQ S

(2.44)

From Eq.(2.10), − dV ox /dQS = 1/ C ox. We define d( −Q S )/d ψ s as the semiconductor capacitance C S. This is the differential change in the semiconductor charge with respect to a change in the semiconductor (surface) potential. The negative sign is included because as ψ s increases, − Q s increases. Therefore, 1 C

=

1 C ox

+

1 C S

.

(2.45) This shows that the MOS capacitance C can be represented by a series combination of the oxide capacitance and the semiconductor capacitance. The oxide capacitance is constant, whereas the semiconductor capacitance varies as ψ s (and V G ) vary. The equivalent circuit of the MOS capacitor is shown in Fig. 2.9.

Figure 2.9

Equivalent circuit of the MOS capacitor: a series combination of the oxide capacitance C ox and the voltage-dependent semiconductor capacitance C S .

We can find C S by differentiating Eq. (2.31). Before doing so, however, we can get a qualitative idea of the shape of the C-V curve by appealing to the depletion approximation. For negative V G (MOS capacitor in accumulation), the capacitor acts like a parallel plate capacitance of value C ox, with negative and positive charge sheets at the two insulator interfaces. As V G goes positive, the semiconductor goes into depletion, and C S comes in series with C ox. From the depletion approximation (Eq. (2.9)), d Q s /d ψ s = d Qd /d ψ s = qN a / 2ε sψ s . Using Eq. (2.8), we get C S =

ε s

x d

,

(2.46)

a familiar result from p-n junction theory. As V G and ψ s increase, xd increases, and hence C S and C reduce. Beyond threshold, the inversion charge Q I increases rapidly. Since this resides at the semiconductor oxide interface, the MOS capacitor again behaves like a parallel-plate capacitor of value C ox . We now calculate the CV curve in detail using the accurate solution for QS , Eq. (2.31). As we shall see, the CV curve is different depending on whether a low-frequency or a high-frequency small (sinusoidal) signal is employed to measure the capacitance. 2.5.2

Low-frequency Capacitance-Voltage (LFCV) Characteristics

When a sufficiently low-frequency small signal is applied, we can assume that all charges, both majority and minority carriers, can follow the changes in gate voltage. In that case, a straightforward differentiation of Eq. (2.31), which contains all the charges, yields C S :

− qψ no qψ 1 − e kT + (e kT − 1) p o . qψ s no F kT , p o s

C S =

d Q s

ε s

=

d ψ s

2 L B

s

(2.47) This equation, coupled with Eq. (2.41), gives C S as a function of V G. However, it is instructive to consider the different conditions of the MOS capacitor separately, which we do below. (a) Accumulation (ψ s < 0) When ψ s < 0, C S simplifies (in accumulation) to

−qψ e kT −1 s

C S

≈

ε s 2 L B

e

1

−qψ s kT

+

qψ s kT

2 −1

.

(2.48)

In strong accumulation, C S ≈ (ε s/ 2 L B) exp (– qψ s/2kT ), so C S increases rapidly as ψ s becomes more negative. As a consequence, the total capacitance C tends to C ox in strong accumulation. (b) Flat Bands (ψ s = 0) At ψ s = 0, the equation for C S (using L'Hôpital's) at flat bands becomes C S,FB =

ε s L B

,

(2.49)

where C S,FB is called the semiconductor flat-band capacitance . This is a result which would not have been derived from the depletion approximation (a naïve application of those equations would have yielded xd ≈ 0 and hence C S,FB ≈ ∞ at flat bands). (c) Depletion (0< ψ s ≤ 2φ B) In depletion, the 1 in the numerator and the {( qψ s/kT ) – 1} term in the denominator of Eq. (2.47) are dominant. So, the semiconductor capacitance in depletion is ε s C S =

2 L B

1 1

qψ s 2 − 1 kT

(2.50)

It can easily be verified that for ( qψ s/kT ) >> 1, C S ≈ (ε s /xd ), as found from the depletion approximation. This is not surprising since we know that here the depletion approximation is quite accurate. (d) Mid-gap (ψ s = φ B)

For reasons which will become clear later, the midgap capacitance is of particular interest. This capacitance corresponds to ψ s = φ B , and is given by ε s C S, MG

≈

1

2 L B

1

qφ B 2 − 1 kT

.

(2.51)

(e) Inversion (ψ s ≥ 2φ B) As ψ s becomes large enough, the exp (qψ s/kT ), term in both the numerator and denominator dominate. As a result, in inversion , C S =

ε s 2 L B

1

no 2 qψ s . 2kT p o e

(2.52) As in accumulation, C S increases rapidly beyond threshold, and C therefore tends towards C ox. A plot of C S versus ψ s is shown in Fig. 2.10 for N a = 1x 1016 cm−3. The minimum value of C S occurs in the weak inversion region at ψ s < 2φ B, and not ψ s > 2φ B as might have been expected.

Figure 2.10

Plot of semiconductor capacitance C S as a function of ψ s. Note that the minimum value C S,min occurs at φ B < ψ s < 2φ B.

Using such a plot of C S versus ψ s , together with the ψ s -V G relationship (Fig 2.8) and Eq. (2.45), we can obtain the full low-frequency CV plot of an ideal MOS capacitor. This is shown in Fig.2.11 − for N a = 1x1016cm 3 and t ox = 25 nm. Some points of interest are noted here. In both deep accumulation and deep inversion, C tends to C ox . An important capacitance is the flat-band capacitance C FB given by 1 C FB

=

1 C ox

+

1 C S , FB

(2.53)

Figure 2.11

Calculated HFCV for an ideal MOS capacitor. Since it is ideal, C = C FB at V G = 0 V.

Values of C FB /C ox for different oxide thicknesses and dopings are shown in Fig.2.12. Another important capacitance, the mid-gap capacitance C MG (defined similarly as in Eq. (2.53) except with the subscript FB replaced by MG) is also indicated in Fig.2.11, and values of C MG /C ox are shown in Fig 2.13. The value of gate voltage at which C = C MG is called the mid-gap voltage V MG. If doping increases , the semiconductor depletion region becomes thinner, thereby increasing C S . As a result, the CV curve becomes "shallower", and also spreads out more since V T increases. If the oxide thickness decreases, the ration of C max /C min increases, and hence the CV curve becomes "deeper" and gets compressed due to a reduction in V T . These effects are shown schematically in Fig. 2.14.

Figure 2.12

Values of C FB/C ox for different oxide thickness t ox and doping N a. Note that as t ox and N a reduce, C FB also reduces.

Figure 2.13

Values of C MG/C ox for different oxide thickness t ox and doping

N a.Note that as t ox and N a reduce, C MG also reduces.

Figure 2.14

LFCV plots for two different values of oxide thickness t ox and doping N a. Note that increasing oxide thickness or doping makes the CV plot “shallower”.

2.5.3

High-frequency Capacitance -Voltage (HFCV) Characteristics

In deriving the low-frequency CV characteristic, we have assumed that both majority and minority carriers can respond to the changes in gate voltage. This is not true at high frequencies. Majority carriers, of course, respond rapidly, in times of the order of the dielectric relaxation time [2.1], which is a few picoseconds. Therefore, in accumulation and depletion, where mainly majority carriers are involved, the high-frquency CV (HFCV) characteristic follows the LFCV characteristic very closely.

Minority carriers, on the other hand, are typically sluggish in their response. As we approach inversion, the response time of minority carriers becomes important. We need to understand (at least qualitatively) how the minority carriers come to form the inversion layer and what their response time is. There are two main sources for electrons to arrive at the surface when the MOS capacitor is in inversion. Consider that the capacitor is biased in inversion, and a small increase in the gate voltage takes place. Initially, majority carriers from just outside the depletion region are repelled quickly, thereby causing a non-equilibrium situation. The minority carriers then slowly come to the surface through two processes. The first is generation in the depletion region, and the second is diffusion from the surrounding bulk into the depletion region and thence to the surface. This is shown schematically in Fig. 2.15. Note that the field in the semiconductor is in a direction which guarantees that any electron being generated in or entering the depletion region is quickly swept to the surface. Generation normally takes place through generation-recombination centers located at ε GR , near the middle of the silicon band gap. The holes generated are swept to the edge of the depletion region, replenishing holes there, and helping restore equilibrium.

Figure 2.15

Band diagram showing the two processes which lead to the production of minority carrier electrons at the surface in a MOS capacitor: generation in the depletion region, and diffusion from the bulk.

Of the two processes, the generation process is dominant for silicon at room temperature. The generation rate is about n / where τ G is the generation lifetime, whereas the diffusion rate is i τ G 2 proportional to ni /N aτ R where τ R is the recombination lifetime in the bulk. At room temperature, the former is much larger than the latter, but at higher temperatures the diffusion component dominates. (This is exactly analogous to the situation for a silicon p-n junction, where the reverse leakage current at room temperature is dominated by generation in the depletion region rather than diffusion of minority carriers form the bulk [2.3].) To estimate the time taken for the generation process, consider the following argument. Let there be an initial increment in the depletion width by repulsion of the majority carriers of amount ∆ xd . The generation rate in this region is ( n / i τ G) ∆ x d A (where A is the cross-sectional area of the capacitor), and the charge contained in it is qN a ∆ xd A. Eventually, electrons of that order of number must be generated to restore equilibrium. This will take a time t s ≈ [qN a ∆ xd A] / [( n / i τ G) ∆ xd A], or t s

≈

N a ni

τ G

,

(2.54)

where t s is called storage time. For a typical value of τ order of 1−10 s, which is very large.

G

of about 1 µ s , it can be seen that t s is of the

We conclude from this digression that when the frequency of the small signal used to measure the capacitance is greater than perhaps 1-10 Hz, the minority carriers will not be able to respond adequately. For frequencies in the range kHz to MHz, the minority carriers are completely "frozen" at the value corresponding to the dc bias, and only the majority carriers respond to the small ac signal. Qualitatively, the HFCV characteristic in inversion can be described as follows. Beyond threshold, the depletion width is limited to approximately xdmax (Eq. (2.17)). A small high-frequency variation in the gate voltage now produces no change in the inversion charge (minority carriers) but only in the depletion width and depletion charge (majority carriers). Since the variation of charge on the gate is now matched by variation at the opposite end of the depletion region (see Fig. 2.16), the total capacitance C will be given by (using the depletion approximation) 1 C H F

=

1 C ox

+

1 C HF S , min

,

(2.55)

where C ≈ ε s/ xdmax . The HF capacitance therefore remains constant at a minimum value (often S , m in called C min ) after V G = V T , instead of going back up to C ox as at low frequencies.

Figure 2.16

Illustrating the variation of charge due to a small variation in the gate voltage, and the resulting equivalent circuit for (a) LF and (b) HF.

Quantitatively, we can find the ideal HF semiconductor capacitance C HF from Eq. (2.47) by S removing all terms corresponding to the minority charges:

−qψ 1 − e kT s

C HF S

ε s

≈

2 L B

e

1

−qψ s kT

+

qψ s kT

2 −1

.

(2.56) In Eq. (2.56), the value of ψ s for a particular value of V G is found by using Eq. (2.41). Note that in Eq. (2.41) we must retain the minority carrier terms in F since this equation serves to define the dc value of ψ s for the applied dc bias V G . The HFCV plot for an ideal MOS capacitor with N a = 1x1016 cm−3 and t ox = 25 nm is shown in Fig 2.17, together with the LFCV curve. As can be seen, the two follow each other closely until just before threshold. The value of C min at which the HFCV curve saturates in inversion is 1 C min

=

1 C ox

+

1

ε s

2 L B

1

qψ s kT

. −1

(2.57)

Note that the term in curly braces, obtained from Eq. (2.56) is almost ε s/ xd . The value of ψ s in Eq. (2.57) would be one of the ψ si values defined in Table 2.1.

Figure 2.17

Calculated HFCV and LFCV curves for an ideal MOS capacitor. Because of the ideal nature, the curves are identical over much of the depletion region, and start to deviate only as they approach inversion.

−

−

Figure 2.18 shows the ideal HFCV plots for N a = 1x1016 cm 3 and 1x1017 cm 3, and t ox = 25nm and 10 nm. The same trends as discussed for the LFCV plots (Fig. 2.14) hold here also. A typical HFCV plot would be taken at frequencies between 10 kHz and 1 MHz, since at these frequencies, minority carriers cannot respond. An LFCV plot would be taken at 0.1 − 1 Hz. At intermediate frequencies, the CV curve in inversion falls somewhere between the HF and LF CV curves, as shown in Fig. 2.19. The exact nature of the curves depends on the dynamics of generation of the minority carriers. Since this is not easy to predict, generally the CV characteristic would be measured at sufficiently low or sufficiently high frequencies so that a true LFCV or HFCV plot results.

Figure 2.18

HFCV plots for two different values of oxide thickness t ox and doping N a. Note that increasing

oxide thickness or doping makes the CV plot “shallower”.

Figure 2.19

HFCV plots for different frequencies. Note that as the frequency reduces, the HFCV curve begins to look more and more like an LFCV curve.

If temperature is increased, the generation and diffusion rates speed up exponentially (because of the ni and ni2 terms respectively). As a result, a CV plot taken at say 10 kHz may resemble an LFCV plot since now minority carriers are generated sufficiently rapidly to follow the "high-frequency" small signal. However, at high enough temperatures, both majority and minority carriers are large enough in number (as the silicon approaches intrinsicity), that it becomes more difficult to form a depletion region. The dip in the CV curve then reduces and eventually disappears. The temperature effects on the CV curve are shown in Fig. 2.20.

Figure 2.20

Effects of temperature on the HFCV plots. As the temperature increases and the generation and diffusion rates increase, the curves start resembling LFCV curves.

2.5.4

Deep depletion

A CV plot would normally be taken by superimposing a small-signal ac voltage (usually sinusoidal) on a slowly varying (almost dc) ramp voltage which sweeps the capacitor very gradually from accumulation to inversion. The (almost) dc bias ensures that the capacitor is in equilibrium, and the superimposed ac voltage is used to monitor the HF or LF capacitance. If the ramp voltage moves too rapidly, then the capacitor is never in equilibrium, and enters a state of deep depletion. In general, whenever the gate voltage increases too rapidly, the minority carriers do not have time to respond, and charge neutrality is maintained by repelling away the responsive majority carriers, thereby creating a depletion region whose width is larger than the equilibrium depletion width xdmax defined in Eq. (2.17). This is deep depletion. Figure 2.21 shows the non-equilibrium band diagram for a MOS capacitor in which V G has been rapidly increased, and there has not been enough time to generate minority (inversion) carriers. It can be seen that ψ s can now be much larger than 2φ B, and xd much larger than xdmax (if there are no minority carriers, then Eq.(2.8) relating ψ s and xd holds). Further, note that in this non-equilibrium condition we cannot draw the fermi level in the semiconductor, but only quasi-fermi levels.

Figure 2.21

Band bending in the MOS capacitor under deep depletion conditions. Note that the band bending ψ s in this case can be much large than 2φ B, and the depletion width xd can be much larger than the so-called xdmax.

If an HFCV plot was being taken with a fast ramp, the capacitor would not go into inversion, but rather into deep depletion. Further, as V G keeps increasing, ψ s (see Eq. (2.12)) and hence xd keep H F

increasing. This means that the semiconductor capacitance does not saturate at a value C S , m in

≈

ε s/ xdmax, but keeps decreasing below that, thereby causing C to go below C min. This is shown in Fig. 2.22. If V G becomes too large, the field in the semiconductor can reach the avalanche breakdown field. This

creates electron-hole pairs by impact ionization and creates a ready source for minority carriers. Once that happens, the capacitor cannot go any further into deep depletion, and the value of C finally saturates at a value C br . One way of avoiding deep depletion (besides changing the bias voltage slowly enough) is to shine light on the device. This creates a shower of electron-hole pairs which quickly brings the device out of deep depletion. (However the capacitance should not be measured while the light is on, since this itself is a non-equilibrium condition; the excess holes generated decrease xd to less than its equilibrium value and hence raise C above its correct value.) The deep depletion condition is discussed in more detail in Chapter 4, where it is shown how deep depletion can be used to estimate the generation lifetime τ G.

Figure 2.22

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