Chapter 5 Homework Advanced Accounting Strayer University ACC410
Full description
test banks for chapter 5 OB
earh fill dam design
CHAPTER 5 Sequential Circuits & Flip-Flops
1.
Objectives Upon completion of this chapter, chapter, student should be able to: Describe the operation and use of latch and flip-flops (S R, D, J K) Draw the flip-flops logic symbol. Draw timing diagram based on flip-flop operation. Recognize the difference between a latch and a flip-flop. Understand the flip-flops operating characteristics Apply flip-flops in basic applications.
2.
Sequential Circuits Combinational
– output depends only on
the input. Do not have memory Cannot store state
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Sequential
– output depends on input and past behavior. Require use of storage elements. Contents of storage elements are called state. Circuit goes through sequence of states as a result of changes in inputs.
Figure 1 2.1 Sequen Sequentia tiall Circui Circuits ts Type Types s a)Synchronous State changes synchronized by one or more clocks Easier to analyze because can factor out gate delays Set clock so changes allowed to occur before next clock pulse
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b)Asynchronous Changes occur independently Potentially faster Harder to analyze
3.
Simple Me Memory El Elements
Figure 2 A
simple memory element: feedback will hold value
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Figure 3 A
4.
memory element with NOR gates: Use Set/Reset to change stored value
Latch Used in computer system for multiplexing data Latch is a type of temporary storage device that has two states.
4.1 SR La Latch
Two versions of SET-RESET (S-R) latches. a) Acti Active ve HIGH IGH inpu inputt S-R latc latch h (NOR gate latch)
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•
Logic diagram:
•
Truth table
Se Rese Outpu Function t t t 0 0 Qo No change 0 1 0 Reset 1 0 1 Set 1 1 ? Not allowed
• •
•
Graphical symbol
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b)
Active LOW input SR latch (NAND gate latch) •
Graphical symbol and logic diagram
•
Truth table
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Example 1: 5.
a) Gated SR Latch Gated latch requires an enable input, EN. Logic diagram and graphical symbol for a gated S-R latch
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Example 2
b) Gated D Latch It
differs from the S-R latch because it has only one input in addition to EN. No illegal state. This input is called the D (Data) input
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Logic diagram, graphical symbol and timing diagram for gated D latch.
6. Edgedge-T Trigg rigger ered ed Fli Flip-Fl p-Flop ops s Synchronous •
input Change state either at positive edge or negative edge of a clock pulse.
3 types of edge triggered flip-flops 9
• • •
S-R flip flop D flip-flop J-K flip-flop
Symbols
– Edge-Triggered
6.1 Edge Edge trigg triggere ered d S-R S-R flip flip-fl -flop op •
Graphical diagram for +ve edge triggered S-R ff
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•
Truth Truth table for a +ve edge triggered S-R ff
•
Timing diagram
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Edge-triggering-pulse
transition detector, detector, produces a very short-duration spike during the transition of the clock pulse.
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6.2. Edge triggered triggered D Flip-Flop Flip-Flop Graphical
diagram and truth table
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Timing
diagram
6.3 Edge Edge trig trigger gered ed JK Flip-Fl Flip-Flop op Graphical
symbol
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Truth
table
Timing
diagram
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7.
Asynchronous Inputs Most
IC ff also has asynchronous inputs. State of the flip-flop change independent of the clock They are normally labeled preset (PRE) and clear (CLR)
8. Flip Flip-F -Flo lop p Ope Opera rati ting ng Char Charac acte teri rist stic ics s • Propagation delay times • Set-up time • Hold time • Maximum clock frequency • Pulse widths • Power dissipation
