!"#$%&'(()*# ,- '#. /#),., 0&)%12%)(. 3 4*5)(. !" $%&"'( )' *$+ &(,-*.+)(/+ '0 0* *$1)+) +/1.,2.1&+ 3 "451&+ ( 6789 !0 +:*; )($)' 0' ""'<+$ + &+=( "+0 (-'/+&1($'0 &(,( 0*,+0> /'0.+0 3 (-'/+&1($'0 "451&+09 ?' -*')' &($0./*1/ + -+/.1/ )' "(0 ="(:*'0 "451&(0 :*' 3+ 0' @+$ <10.( +$.'/1(/,'$.' A&(,-*'/.+0 6BC> DE> 1$<'/0(/'0 3 ,*".1-"'F(/'0G9
04/ ,- 6 7)% 7+ &($0./*&&14$ )' *$+ 678 0' -*')' @+&'/ + -+/.1/ )' '"','$.(0 ,*3 01,-"'0H "+0 (-'/+&1($'0 "451&+0 0($ ,*3 01,-"'0H &($010.'$ '$ ',-"'+/ " +0 &(,-*'/.+0 &($(&1)+0 6BC 3 DE 3 0' &($'&.+$ + ./+<20 )' *$ ,*".1-"'F(/ -+/+ 0'"'&&1($+/ "+0 0+"1)+0 )' 20.+0 + "+ 0+"1)+ )'" ,*".1-"'F(/9 7+ I15*/+ J9K9L "( ,*'0./+H Operation a
0 Result 1
b FIGURE B.5.1
The 1-bit logical unit for AND and OR.
!" ,*".1-"'F(/ 0'"'&&1($+ "+ (-'/+&14$ + 6BC = 4 + DE = )' +&*'/)( &($ '" <+"(/ )' "+ '$./+)+ !"#$%&'()9 !"#$%&'()9 6,=+0 (-'/+&1($'0 0' ""'<+$ + &+=( +" ,10,( .1',-( 3 "+ ";$'+ )' !"#$%&'() &($./("+ !"#$%&'() &($./("+ +" /'0*".+)( 0'"'&&1($+)(9 !0.' )10'M( 0' +,-"1+/N @+0.+ .'$'/ *$+ 678 )'" +$&@( )' =1.0 :*' 0' $'&'01.' -+/+ "+ &(,-*.+)(/+ AOP> QR =1.0> '.&G9 7+ I*$&14$ ?8S6 '0 "+ 015*1'$.' :*' 0' &($0./*3'H )'=' .'$'/ )(0 '$./+)+0 -+/+ "(0 (-'/+$)(0 3 *$ =1. )' 0+"1)+ -+/+ '" +&+//'(9 T(,( '$ *$+ 0*,+ .+,=12$ 0' .1'$' :*' .(,+/ '$ &*'$.+ '" +&+//'( )' '$./+)+> '0.' 0' +5/'5+ .+,=12$ '$ *$ )10'M( :*' 0' -/'0'$.+ &(,( *$+ U&+V+ $'5/+U> .+" 3 &(,( 0' ,*'0./+ '$ "+ I15*/+ J9K9P9 T*+$)( 0' 1$&"*3'$ "(0 +&+//'(0 )' '$./+)+ 3 )' 0+"1)+ '0.(0 0*,+)(/'0 0' ""+,+$ U0*,+)(/'0 &(,-"'.(0W T*+$)( 04"( @+&'$ "+ 0*,+> 0' ""+,+$ U,')1(0 0*,+)(/'0U CarryIn
a +
Sum
b
CarryOut A 1-bit adder. Tis adder is called a full adder; it is also called a (3,2) adder because it has 3 inputs and 2 outputs. An adder with only the a and b inputs is called a (2,2) adder or half-adder. FIGURE B.5.2
7+0 I*$&1($'0 )' +&+//'( 3 )' 0*,+ 0' -*')'$ '0&/1=1/ &(,( '&*+&1($'0 "451&+0 :*' 0' -*')'$ &($0./*1/ &($ &(,-*'/.+0H CarryOut
(b CarryIn)
(a CarryIn)
(a b)
(a b CarryIn)
7+ .+="+ )' <'/)+) -+/+ '0.' &1/&*1.( 0' ,*'0./+ '$ 0'5*1)+H Inputs
Outputs
a
b
CarryIn
CarryOut
Sum
Comments
0
0
0
0
0
0 + 0 + 0 = 00 two
0
0
1
0
1
0 + 0 + 1 = 01 two
0
1
0
0
1
0 + 1 + 0 = 01 two
0
1
1
1
0
0 + 1 + 1 = 10 two
1
0
0
0
1
1 + 0 + 0 = 01 two
1
0
1
1
0
1 + 0 + 1 = 10 two
1
1
0
1
0
1 + 1 + 0 = 10 two
1
1
1
1
1
1 + 1 + 1 = 11 two
FIGURE B.5.3
Input and output specification for a 1-bit adder.
X+/+ +/,+/ +" &1/&*1.( &($ &(,-*'/.+0> -()',(0 <'/ "+ .+="+ )' <'/)+) -+/+ &*+$)( '" +&+//'( )' 0+"1)+ ( U&+//3 (*.U '0
a Inputs a
b
CarryIn
0
1
1
1
0
1
1
1
0
1
1
1
FIGURE B.5.4
b
CarryOut
Values of the inputs when CarryOut is a 1.
!" =1. )' 0*,+ 0' +&.1<+ &*+$)( *$+ '$./+)+ '0 L 4 &*+$)( "+0 ./'0 '$./+)+0 A+> => T+//3Z$G 0($ L9 !0.( /'0*".+ '$ "+ '&*+&14$ J(("'+$+H Sum
(a b CarryIn)
( a b CarryIn)
( a b CarryIn)
(a b CarryIn)
4. &-.8)9.()*# ,- -$%. -('.()*# . :.&%)& ,- ()&(')%"$ ,-7-&; <.(-&$- :"& :.&%,-8 -$%',).#%-= 7+ I15*/+ J9K9Q ,*'0./+ "+ 678 )' L =1. &(,-"'.+9 6 <'&'0 '" )10'M+)(/ )' &(,-*.+)(/+0 )'0'+ +5/'5+/ (./+0 (-'/+&1($'0 01,-"'0 &(,( 5'$'/+/ *$ &'/(9 7+ ,+$'/+ ,N0 01,-"' '0 'F-+$)'/ '" ,*".1-"'F(/ &($./("+)( -(/ "+ ";$'+ )' (-'/+&14$ -+/+ +5/'5+/ "+ I*$&14$ +$.'0 )' "+ 0+"1)+H
Operation CarryIn a 0
1
b
Result
2
CarryOut FIGURE B.5.6
A 1-bit ALU that performs AND, OR, and addition (see Figure B.5.5).
04/ ,- >? 7)%$ 7+ &($0./*&&14$ )' *$+ 678 )' OP =1.0 0' @+&' +" &($'&.+/ OP ,4)*"(0 )' *$ =1.9 Operation CarryIn
a0 b0
a1 b1
a2 b2
.. .
a31 b31
CarryIn ALU0 CarryOut
Result0
CarryIn ALU1 CarryOut
Result1
CarryIn ALU2 CarryOut
Result2
.. .
CarryIn ALU31
.. .
Result31
A 32-bit ALU constructed from 32 1-bit ALUs. CarryOut of the less signi �cant bit is connected to the CarryIn of the more signi�cant bit. Tis organization is called ripple carry. FIGURE B.5.7
7(0 =1.0 )' '$./+)+ +[> =[> +L> =L> 999+OL> =OL 0' +&(,()+$ '$ -+/+"'"( 3 0("( 0' &($'&.+$ "+0 ";$'+0 )' (-'/+&14$ )' ,+$'/+ &(,%$ -+/+ .()+0 "(0 ,4)*"(0 3 "(0 +&+//'(0 0' &($'&.+$ '$ &+0&+)+> )' .+" ,+$'/+ :*' .'$)/',(0 OP =1.0 )' )+.(0 0(=/' "(0 &*+"'0 0' (-'/+ 01,*".N$'+,'$.'9 6*$:*' '$ "+ -/N&.1&+ .'$'/ .+$.+0 &(,-*'/.+0 '$ &+0&+)+ -()/;+ @+&'/ "+ (-'/+&14$ )' "+ 678 ,+0 "'$.+> ,1'$./+0 0' -/(-+5+$ "(0 +&+//'(0> 0' -*')' )10'M+/ *$ &1/&*1.( "451&( :*' @+5+ '" &N"&*"( )' 20.(0 +$.1&1-+)+,'$.' A0' ""+,+$ &1/&*1.(0 )' U&+//3 "((\+@'+)U> -'/( $( 0' <'/N '" .',+ +:*;G9 ]+ 0' @+=;+ ,'$&1($+)( :*' "+ /'0.+ '0 "( ,10,( :*' 0*,+/ "+ <'/014$ $'5+.1<+ )' *$ (-'/+$)(> -(/ "( :*' '0.( '0 "( :*' 0' @+&' '$ "+0 67809 7+ ,+$'/+ )' @+&'/"( '0 @+&1'$)( "+ 1$<'/014$ )' &+)+ =1. A"( :*' 0' ""+,+ &(,-"','$.( + *$(G 3 0*,+/ L9 X+/+ 1$<'/.1/ *$ =1.> 01,-"','$.' 0' +5/'5+ *$ ,*".1-"'F(/ PHL :*' -'/,1.' '0&(5'/ '$./' "+ '$./+)+ $(/,+" 3 "+ '$./+)+ $'5+)+ )' &+)+ ,4)*"( )' L =1.9 -+/+ '0&(5'/ '$./' = 3 = $'5+)+ A^=G9 Binvert
Operation CarryIn
a 0
1
b
0
Result
2
1
CarryOut A 1-bit ALU that performs AND, OR, and addition on a and b or a and b. By selecting b (Binvert 1) and setting CarryIn to 1 in the least signi �cant bit of the ALU, we get two’s complement subtraction of b from a instead of addition of b to a. FIGURE B.5.8
C'0-*20 )' '0.( '0 $'&'0+/1( 0*,+/ *$ *$( +" <+"(/ $'5+)( -+/+ .'$'/ '" <+"(/ )' &(,-"','$.( + )(0 )' =9 !0.( 0' @+&' -($1'$)( '" <+"(/ )'" =1. )' +&+//'( )'" -/1,'/ ,4)*"( _L 3 .'$)/',(0 "+ (-'/+&14$ +`=`LH a
b
1
a
(b
1)
a
( b)
a
b
T(,( 0' <'> +5/'5+/ "+ (-'/+&14$ )' /'0.+ '0 ,*3 01,-"' 3 +0; 0' @+&' '$ .()(0 "(0 -/(&'0+)(/'09 !$ *$ )10'M( )' *$+ +/:*1.'&.*/+ @+3 (./+0 $'&'01)+)'09 X(/ 'V',-"(> -+/+ SZX? 0' /':*1'/'$ (./+0 I*$&1($'0 "451&+0 3 I*$&1($'0 )' &($./(" )'" -/(5/+,+9 X+/+ '0.'
-/(&'0+)(/ 0' /':*1'/' )' "+ (-'/+&14$ BDE9 !$ <'Y )' +5/'5+/ (./+ &(,-*'/.+> 0' /'*.1"1Y+$ &(,-($'$.'09 ?' -*')' <'/ '0.( + -+/.1/ )'H
(a
b)
a b
!0 )'&1/ BDE _ BDa + 6BC BDa = A+ -+/.1/ )' "(0 .'(/',+0 )' C'S(/5+$G 3 &(,( 3+ .'$',(0 *$+ BDa => 04"( +5/'5+,(0 *$ 1$<'/0(/ '$ + .+" 3 &(,( 0' ,*'0./+H Ainvert
Operation Binvert
a
CarryIn
0 0
1
1
b
0
Result
2
1
CarryOut FIGURE B.5.9
A 1-bit ALU that performs AND, OR, and addition on a and b or a and b. By
selecting a (Ainvert 1) and b (Binvert 1), we get a NOR b instead of a AND b.
$8% !$ .()+ &(,-*.+)(/+ '0 '0'$&1+" .'$'/ 1$0./*&&1($'0 -+/+ '" &($./(" )' "(0 -/(5/+,+09 8$+ 1$0./*&&14$ '0'$&1+" '0 U0'. ($ "'00 .@+$U A*+, G ( -($'/ *$+ =+$)'/+ 01 '" /'0*".+)( '0 U,'$(/ :*'U9 !$ '" &($V*$.( )' 1$0./*&&1($'0 SZX? '" /'0*".+)( '0 L 01 )' "(0 /'510./(0 )'" -/(&'0+)(/ "+ &(,-+/+&14$ )' *$( '0 ,'$(/ :*' '" (./( ( $*-$, 9 7+ 1$0./*&&14$ *+, -($)/N + .()(0 "(0 =1.0 _[ 'F&'-.( '" =1. ,'$(0 015$1I1&+.1<(9 X+/+ +@+&'/ '0.(> 0' 'F-+$)' '" ,*".1-"'F(/ )' ./'0 =1.0 -+/+ +5/'5+/ *$+ '$./+)+ -+/+ '" /'0*".+)( )' *+,. X+/+ '0.( '0 $'&'0+/1( &($'&.+/ *$ [ + "+0 '$./+)+0 )' "(0 OL =1.0 ,+0 015$1I1&+.1<(0> 3+ :*' 01',-/' )'='/N$ 0'/ &'/(9 ?' )'='/N <'/ +@(/+ &(,( &(,-+/+/ 3 &($./("+/ "+ ";$'+ )' 0'. -+/+ '" =1. ,'$(0 015$1I1&+.1<(9 ?1 +" /'0.+/ = )' +> "+ )1I'/'$&1+ '0 $'5+.1<+> '$.($&'0 +b= 3+ :*' (a
b)
0
((a b) b ⇒ a ⇒
b)
(0
b)
c*'/',(0 :*' '" =1. ,'$(0 015$1I1&+.1<( )' *+, 0'+ L 01 +b=W '0 )'&1/> L 01 +d= '0 $'5+.1<( 3 [ 01 '0 -(01.1<(9 !0.' /'0*".+)( &(//'0-($)' 'F+&.+,'$.' + "(0 =1.0 )' 015$(H *$ L '0 :*' '0 $'5+.1<( 3 [ :*' '0 -(01.1<(9 C'=1)( + '0.( 04"( 0' $'&'01.+ &($'&.+/ '" =1. )' 015$( )' "+ 0+"1)+ )'" 0*,+)(/ +" =1. ,'$(0 015$1I1&+.1<( -+/+ .'$'/ *+, 9 X'/( /'0*".+ :*' &($ "(0 &1/&*1.(0 )' "+ -+/.' +".+ )' "+ I15*/+ J9K9L[> :*' 0($ &($ "(0 :*' &($.+,(0> "+ ";$'+ )' /'0*".+)( $( '0 "+ 0+"1)+ )'" 0*,+)(/9 ?' /':*1'/' *$+ 678 )' L =1. )1I'/'$.'> :*' .'$5+ *$+ 0+"1)+ ,N0> "+ 0+"1)+ )'" 0*,+)(/9 7+ -+/.' =+V+ )' "+ I15*/+ J9K9L[ ,*'0./+ '0.' )10'M(9 6)1&1($+",'$.'> 3+ :*' '0.' ,4)*"( )' L =1. )'=' 0'/ )1I'/'$.' 0' "' @+ +5/'5+)( +"5( ,N0 )' "451&+ -+/+ 5'$'/+/ "+ )'.'&&14$ )' &($)1&1($'0 )' 0(=/'I"*V(9 7+ I15*/+ J9K9LL ,*'0./+ "+ 678 )' OP =1.09 T*+$)( 0' )'0'+ @+&'/ *$+ /'0.+> 0' -($'$ T+//3Z$ 3 J1$<'/. _ L9 X+/+ 0*,+0 3 (-'/+&1($'0 "451&+0 "+0 ";$'+0 )'='$ 0'/ [9 60; 0' -*')' 01,-"1I1&+/ '" &($./(" )' "+ 678 +" &(,=1$+/ T+//3Z$ 3 J1$<'/. '$ *$+ 0("+ ""+,+)+ 0)#1%,# '$ '" ,4)*"( ,'$(0 015$1I1&+.1<( )' "+ 6789 6)1&1($+",'$.' 0' /':*1'/' -()'/ 'V'&*.+/ 1$0./*&&1($'0 )' 0+".(0 &($)1&1($+)(09 !0.+0 1$0./*&&1($'0 0+".+$ 01 '$ "+ &(,-+/+&14$ '$./' /'510./(0 0' .1'$'$ 15*+")+)'0 ( )'015*+")+)'09 7+ ,+$'/+ ,N0 IN&1" )' -/(=+/ 15*+")+)'0 '0 )' -/(=+/ +d= 3 -/(=+/ 01 'F10.' *$ &'/( &(,( /'0*".+)(> 3+ :*'H (a
b
0) ⇒ a
b
+0; :*' 01 +5/'5+,(0 @+/)e+/' -+/+ -/(=+/ 01 '" /'0*".+)( '0 &'/( -()',(0 -/(=+/ '0.+ &($)1&14$9 7+ ,+$'/+ ,N0 IN&1" '0 )' +"+,=/+/ .()+0 "+0 0+"1)+0 &($ *$+ &(,-*'/.+ DE 1$<'/.1)+9 7+ I15*/+ J9K9LP ,*'0./+ "+ 678 &($ '0.+0 ,()1I1&+&1($'09 !$ /'+"1)+) +@(/+ -()',(0 <'/ "+0 &(,=1$+&1($'0 )' ";$'+0 )'61$<'/.> J1$<'/. 3 "+0 P ";$'+0 )' (-'/+&14$ &(,( *$ 5/*-( )' R ";$'+0 )' &($./(" :*' )'I1$'$ "+ 'V'&*&14$ )' "+0 (-'/+&1($'0H 6BC DE ?8S6 E!?a6 ?!a DB 7!?? af6B 7+ I15*/+ J9K9LO ,*'0./+ "+ &(,=1$+&14$ )' ";$'+0 )' &($./(" 3 0* &(//'0-($)1'$.' (-'/+&14$9 g1$+",'$.' "+ I15*/+ J9K9LR ,*'0./+ '" 0;,=("( *$1<'/0+" -+/+ *$+ 678 &(,-"'.+9
Operation
Ainvert Binvert
a
CarryIn
0
0
1 1 Result b
0
2
1 Less
3
CarryOut
Operation
Ainvert Binvert
a
CarryIn
0
0
1 1 Result b
0
2
1 Less
3 Set Overflow detection
Overflow
FIGURE B.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b , and (bottom) a 1-bit ALU for the most significant bit. Te top drawing includes a direct input that is
connected to perform the set on less than operation (see Figure B.5.11); the bottom has a direct output from the adder for the less than comparison called Set. (See Exercise B.24 at the end of this appendix to see how to calculate over�ow with fewer inputs.)
Operation
Binvert Ainvert CarryIn
a0 b0
CarryIn ALU0 Less CarryOut
Result0
a1 b1 0
CarryIn ALU1 Less CarryOut
Result1
a2 b2 0
CarryIn ALU2 Less CarryOut
Result2
.. .
. . . . . . . . . a31 b31 0
.. . CarryIn
CarryIn ALU31 Less
.. .
Result31 Set
Overflow
FIGURE B.5.11 A 32-bit ALU constructed from the 31 copies of the 1-bit ALU in the top of Figure B.5.10 and one 1-bit ALU in the bottom of that figure. Te Less inputs are connected
to 0 except for the least signi�cant bit, which is connected to the Set output of the most signi �cant bit. If the ALU performs a b and we select t he input 3 in the multiplexor in Figure B.5.10, then Result 0 … 001 if a b, and Result 0 … 000 otherwise.
ALU control lines
Function
0000
AND
0001
OR
0010
add
0110
subtract
0111
set on less than
1100
NOR
FIGURE B.5.13 The values of the three ALU control lines, Bnegate, and Operation, and the corresponding ALU operations.
Operation
Bnegate Ainvert
CarryIn ALU0 Less CarryOut
a0 b0
a1 b1 0
a2 b2 0
a31 b31 0
FIGURE B.5.12
CarryIn ALU1 Less CarryOut
Result1 .. .
CarryIn ALU2 Less CarryOut .. .
. . . . . . . . .
Result0
Result2
.. . CarryIn
Zero
.. .
.. .
Result31
CarryIn ALU31 Less
Set
Overflow
The final 32-bit ALU. Tis adds a Zero detector to Figure B.5.11.
ALU operation
a Zero ALU
Result Overflow
b
CarryOut FIGURE B.5.14 The symbol commonly used to represent an ALU, as shown in Figure B.5.12. Tis symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
