PAGE [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32]
RULE RU LES: S: 1.) 2.) 2.) 3.)) 3. 4.)) 4. 5.)) 5. 6.)) 6. 7.)) 7. 8.)) 8. 9.)) 9. 10.) 10 .) 12.) 12 .) 13.) 13 .) 14.) 15.) 15 .)
CONTENTS
PAGE
COVER PAGE CLOCK DIAGRAM RESET/ENABLE DIAGRAM CPU, CLOCKS + EEPROM + ST STRAPPING CPU, FS F SB CPU, FSB POWER + P LL LL POWER CPU, CORE POWER CPU, PO P OWER CPU, DECOUPLING CPU, DECOUPLING CPU, DECOUPLING GPU, FS FSB GPU, VIDEO + PC PCIEX + EE EEPROM GPU, MEMORY CONTROLLER A + B GPU, MEMORY CONTROLLER C + D GPU, PLL POWER + FS F SB POWER GPU, CORE PO POWER + MEM POWER GPU, DE DECOUPLING DUAL ET ETHERNET PHY MEMORY, A (TOP) MEM EMO ORY, A MIRR RRO ORED (BO (BOTT TTO OM) MEMORY, B (TOP) MEM EMO ORY, B MIRR RRO ORED (BO (BOTT TTO OM) MEMORY, C (TOP) MEM EMO ORY, C MIRR RRO ORED (BO BOTT TTO OM) MEMORY, D (TOP) MEM EMO ORY, D MIRR RRO ORED (BO BOTT TTO OM) ANA, CLOCKS + ST STRAPPING ANA, VIDEO + FA FAN + JT JTAG ANA, POWER + DE DECOUPLING DEBUG MA MAPPING, WN DBG VS VS WN XDK POWER TRACE E MI MI CAPS
(APPL (A PPLIE IED D
[33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64]
SCHEMATIC K7
CONTENTS
REV
PB NUMBER X803600-011
SB, PCIEX + SM SMM GPIO + JT JTAG SB, SM SMC SB, FLASH + US USB + SP SPI SB, ETHERNET + AU AUDIO + SA SATA SB, STA TAN NDBY POWER + DE DECOUPLE SB, MAIN POWER + DE DECOUPLE SB OUT, ETHERNET SB OUT, AUDIO SB OUT, FLASH SB OU OUT, FAN + INFRARED + BU B UTTONS CONN, AVIP CONN, RJ45 + US USB COMBO CONN, GAME PORTS + MEMORY PORTS BACKUP C LO LOCK + V_ V_5P0 DUAL CONN, ODD AND HDD CONN, ARGON + PO POWER VREGS, INPUT + OU OUTPUT FI FILTERS VREGS, CPU CONTROLLER VREGS, GPU OUTPUT PHA PHASE 1,2 1,2,3 VREGS, GPU CONTROLLER VREGS, GPU OUTPUT PHASE 1,2 VREGS, SWITCHED 1. 1.8, 5.0V VREGS, LINEAR REGULATO TOR RS XDK, DEBUG CONN DEBUG BO BOARD, CPU + GPU BR BREAKOUT DEBUG BOARD, CPU CONN DEBUG BO BOARD, CPU CO CONN + T ER ERM DEBUG BOARD, CPU TERM DEBUG BOARD, TITAN + YE YETI CONN DEBUG BO BOARD, GPU CO CONN + T ER ERM XDK, LE L EDS LABELS AND MOUNTING
RETAIL REV K7 FAB K
XENON PLEA PL EASE SE
BOM RELEAS RELEASE E
DATE DAT E
SIGNATURE DRN BY C HK HK B Y ENGR APVD
DRAWING
PAG PA GE]
BOM RELEASE DA DATE XX/XX/XX
XENON
WHEN WH EN POS POSSI SIBLE BLE))
MSB TO LSB LSB IS TOP TO BOT BOTT TOM WHEN PO WHEN POSS SSIIBL BLE: E: INPU IN PUT TS ON LE LEFT FT,, OUT OU TPU PUT TS ON RIG IGH HT ORDE OR DER R OF OF PAG PAGES ES=C =CHI HIP P INT IN TER ERFA FACE CES, S, TERM TE RMIN INAT ATIO ION, N, POWE PO WER, R, DECOU DECOUPL PLIN ING G AVO VOID ID US USIN ING G OF OFF F PA PAGE GE CO CONN NNEC ECT TOR ORS S FO FOR R ON PA PAGE CO CONN NNEC ECTI TION ONS S LANE LA NED D SI SIGN GNA ALS ARE GROUP GROUPED ED ON SYM SYMBO BOLS LS TRA TR ANS NSIM IMIT ITTE TER R NAME USED USED AS PREFI PREFIX X WIT WI TH RX AND AND TX TX CO CONN NNEC ECTI TION ONS S SUFF SU FFIX IX V_ IS USE SED D FOR FOR VOL VOLT TAGE RAIL SIGN SI GNA AL NAMES SUFF SU FFIX IX _DP _D P AND _DN _DN ARE USE SED D FOR DI DIFF FFER ERIIEN ENT TAL PAIR PA IRS S UNNAMED NET ETS S ARE NAM NAMED WIT WITH /2 TEX EXT T SI SIZE ZE SUFF SU FFIIX _N FOR FOR ACT ACTIV IVE E LOW LO W OR OR N JU JUNCTION SUFF SU FFIIX _P FOR FOR P JU JUNCTIO ION N SUFF SU FFIIX _EN _E N FO FOR R EN ENABL BLE E 'CL 'C LK' FOR FO R CLOCKS KS,, 'RST 'R ST' FOR FO R RESETS PWRG PW RGD D FOR FOR POWER POWER GOO GOOD D
[PAG [P AGE_ E_TI TITL TLE= E=CO COVE VER R
VER RETAIL
XENON_FABK
W ed ed Au Au g 2 4 0 9 :4 :4 1: 1: 55 55
2 00 00 5
REFE RE FER R
XX/XX/XX
DATE
TO THE THE
PB NUM NUMBER BER
XENO XE NON N DE DESI SIGN GN
X803600-011
MICR MI CRO OSO SOFT FT TITLE
SPEC SP EC
SCH SC H,
APVD
MICROSOFT
APVD
CONFIDENTIAL
PBA BA,,
XBOX XB OX XEN XE NON
PROJECT NAME XENON_RETAIL
PAGE 1/73
REV K7
AVIP CONN
RJ45/USB CONN
POWER CONN
FAN CONN
CLOC CL OCK K DI DIAG AGRA RAM M
ENET_CLK(25MHZ)
ENET PHY
I2S_MCLK(12.288MHZ) I2S_BCLK(3.072MHZ)
AUDIO DAC
ANA_XTAL_IN(27MHZ)
GPU VR
DEBUG CONN ANA BCKUP
SB DVD SATA CONN
ANA GPU VR CNTL
STBY_CLK(48MHZ) SATA_CLK_REF(25MHZ) SATA_CLK_DP/DN(100MHZ) PCIEX_CLK_DP/DN(100MHZ) AUD_CLK(24.576MHZ) CPU_CLK_DP/DN(100MHZ) GPU_CL GPU _CLK_D K_DP/DN P/DN
DVD PWR CONN ANA BCKUP
1 P8 P8
MEM
CLAM CL AM C+ C+D D
MC_CLK1_DP/DN(800MHZ) MC_CLK0_DP/DN(800MHZ) MD_CLK1_DP/DN(800MHZ) MD_CLK0_DP/DN(800MHZ)
CPU
GPU GP U ) ) ) ) Z Z Z Z H H H H M M M M 0 0 0 0 0 0 0 0 8 ( 8 ( 8 ( 8 ( N N N N D / D / D / D / P P P P D D D D _ _ _ _ 1 0 1 0 K K K K L L L L C C C C _ _ _ _ A A B B M M M M
VR FLSH
HDD CONN
3 P3 P3
RISCWATCH CONN
PIX_CLK_OUT_DP/DN(100MHZ) (100MHZ) (100MH Z)
VR
VMEM VM EM VR 5P0
MPORT MP ORT VR
MEM CLAM CL AM A+ A+B B
TITAN TITA N CONN EFUS EF USE E
CPU VR
JTAG JT AG
VR
CPU VR CPU CNTL
VR
GAME CONN IR
EJECT SW
MEM CONN
DIAG DI AGRA RAM> M>
MEM CONN
BIND SW
ARGON CONN
DRAWING XENON_FABK W ed ed J ul ul 2 7 21 21 :5 :5 3: 3: 30 30
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 2/73
REV K7
AVIP CONN
RJ45/USB CONN
ENET PHY
ENET_RST_N
N _ N O _ R W P _ T X E
POWER CONN
FAN CONN
RESE RE SET/ T/EN ENAB ABLE LE AUD_CLAMP AUD_RST_N
AUDIO DAC
PSU_V12P0_EN
GPU GP U VR ANA_CLK_OE ANA_RST_N
ANA
VREG_GPU_EN_N
SB
VREG_GPU_PWRGD EXT_PWR_ON_N CPU_CHECKSTOP_N CPU_RST_N CPU_PWRGD GPU_RST_N
DVD PWR CONN
RISCWATCH CONN
GPU_RST_DONE
N E _ G B D N _ E _ C 3 M P S 3 _ G E R V
HDD CONN
GPU VR GPU CNTL
SMC_RST_N
N _ T S R _ B S
DVD SATA CONN
DIAG DI AGRA RAM M
D G R W P _ U P C _ G E R V
MEM CLAM CL AM C+ C+D D
MEM_RST MEM_SCAN_EN MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN
GPU
CPU
N N N E E _ E _ T _ P N O O T A T B S C _ _ R S N N _ _ A A M M C C S E E S _ _ M M M M E E M M
3P3 VR
DEBUG CONN
CPU VR
VREG_1P8_EN_N VREG_5P0_EN_N
CPU_PWRGD TITAN TITA N CONN
MEM CLAM CL AM A+ A+B B
VMEM VM EM VR 5P0
EFUSE EFU SE
JTAG JT AG
VR
CPU VR CPU CNTL
VR VREG_EFUSE_EN VREG_CPU_EN
GAME CONN IR
EJECT SW
[PAG [P AGE_ E_TI TITL TLE= E=RE RESE SET/ T/EN ENAB ABLE LE
MEM CONN
MEM CONN
DIAG DI AGRA RAM] M]
BIND SW
ARGON CONN
DRAWING XENON_FABK W ed ed J ul ul 2 7 21 21 :5 :5 3: 3: 44 44
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 3/73
REV K7
CPU,
FSB POWER + PLL
POWER
V_1P8 V_GPUCORE
V_CPUPLL
U7D1
FB7R1
1
C7R1
1
1
2
1K
FB 603
0.2A 0.7DCR
1
.1UF 10%
2 1
C7R7
.1UF
6.3V X5R 402
2
C7R116 .1UF 10% 6.3V X5R 402
1
4 of of
.1UF 10% 6.3V X5R 402
2
10%
6.3V X5R 402
6.3V X5R 603
2 ST7R1 2
1
V_EFUSE SHORT 2
FB6D1
1
C6D1
10K 402
1
2
1K
FB 603
0.2A 0.7DCR
1
5% CH
2
V_CPU_CORE_HF_VDDA_PLL V_CPU_CORE_HF_GNDA_PLL
ST6D1
V_CPU_CORE_IF_VDDA_PLL
2
1
CPU_VDDE
V_CPU_CORE_IF_GNDA_PLL
SHORT
V_CPU_FSB_HF_VDDA_PLL V_CPU_FSB_HF_GNDA_PLL
FB6R1
1
C6R2
V_CPU_FSB_IF_VDDA_PLL
1
2
1K
FB 603
0.2A 0.7DCR
V_CPU_FSB_IF_GNDA_PLL V_CPU_VDDA_RNG
1
VDD_IO VDDE VDDE_SEC
AJ19 AH19
CORE_HF_VDDA_PLL CORE_HF_GNDA_PLL
AK19 AK18
CORE_IF_VDDA_PLL CORE_IF_GNDA_PLL
AF22 AG22
FSB_HF_VDDA_PLL FSB_HF_GNDA_PLL
AF20 AG20
FSB_IF_VDDA_PLL FSB_IF_GNDA_PLL
AK13 AJ13
VDDA_RNG GNDA_RNG
2.2UF
10%
2
V_CPU_GNDA_RNG
C6R4
.1UF
AK6 A6 B6
2.2UF 10% 6.3V X5R 603
10%
2
1
C6D4
.1UF
6.3V X5R 402
R7T2
10%
6.3V X5R 402
6.3V X5R 603
2 ST6R1 2
1
SHORT
FB6R2
1
C6R3
1
2
1K
FB 603
0.2A 0.7DCR
1
.1UF
20 VDD_FSB0 VDD_FSB1 VDD_FSB2 VDD_FSB3 VDD_FSB4 VDD_FSB5 VDD_FSB6 VDD_FSB7 VDD_FSB8 VDD_FSB9 VDD_FSB10 VDD_FSB11 VDD_FSB12 VDD_FSB13 VDD_FSB14 VDD_FSB15 VDD_FSB16 VDD_FSB17 VDD_FSB18 VDD_FSB19 VDD_FSB20 VDD_FSB21 VDD_FSB22 VDD_FSB23 VDD_FSB24 VDD_FSB25 VDD_FSB26 VDD_FSB27 VDD_FSB28 VDD_FSB29 VDD_FSB30 VDD_FSB31 VDD_FSB32 VDD_FSB33 VDD_FSB34 VDD_FSB35 VDD_FSB36 VDD_FSB37 VDD_FSB38 VDD_FSB39 VDD_FSB40 VDD_FSB41 VDD_FSB42 VDD_FSB43 VDD_FSB44 VDD_FSB45 VDD_FSB46
AA27
AB26 AC27
AD26 AE27
AF26 AG27
AH26 AJ27
AK26 B9 B12 B15 B18 B21 B24 B27 C8 C11 C14 C17 C20 C23 C26 D10 D13 D17 D21 D25 D27 D29 E26 F27 G26 H27 J26 K27 L26 M27 N26 P27 R26 T27 U26 V26 W27 Y26
C6R5 2.2UF
10%
2
IC
10
CPU VERS VERSIO ION N
C7R114
2.2UF
10%
2
C7R115
10%
6.3V X5R 402
2 ST6R2
X02046-002
6.3V X5R 603
2
1
SHORT
FB7D1
1
C7D1
1
2
1K
FB 603
0.2A 0.7DCR
1
1UF 10%
2
C7D2 2.2UF 10%
50V EMPTY 603
2 ST7D1
6.3V X5R 603
2
1
SHORT
[PA [P AGE_TIT ITL LE=CPU,
FSB
POWER + PLL PLL
POWER]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 01 01
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 6/73
REV K7
V_CPUCORE
V_CPUCORE
CPU, CP U,
1
C7D21
2
4.7UF 10% 6.3V X5R 805
1
C7T94
2
4.7UF 10% 6.3V X5R 805
1
C7T101
2
4.7UF 10% 6.3V X5R 805
1
C7T87
2
4.7UF 10% 6.3V X5R 805
1
C7R2
2
4.7UF 10% 6.3V X5R 805
1
C7E3
2
4.7UF 10% 6.3V X5R 805
1
C7T32
2
4.7UF 10% 6.3V X5R 805
1
C7R28
2
4.7UF 10% 6.3V X5R 805
1
C7D20
2
4.7UF 10% 6.3V X5R 805
C7R122
1
2
10% 4.7UF 6.3V X5R 805
1
C7E8
2
10% 4.7UF 6.3V X5R 805
1
C7E14
2
10% 4.7UF 6.3V X5R 805
1
C7T93
2
10% 4.7UF 6.3V X5R 805
1
C7D16
2
10% 4.7UF 6.3V X5R 805
1
C7E12
2
10% 4.7UF 6.3V X5R 805
1
C7E10
2
10% 4.7UF 6.3V X5R 805
1
C7E11
2
10% 4.7UF 6.3V X5R 805
1
C7T33
2
10% 4.7UF 6.3V X5R 805
[PAG [P AGE_ E_TI TITL TLE= E=C CPU PU,,
1
C7T85
2
4.7UF 10% 6.3V X5R 805
1
C7E6
2
4.7UF 10% 6.3V X5R 805
1
C7D12
2
4.7UF 10% 6.3V X5R 805
1
C7D19
C7T36
2
4.7UF 10% 6.3V X5R 805
1
C7R118
2
4.7UF 10% 6.3V X5R 805
1
C7E5
2
4.7UF 10% 6.3V X5R 805
1
C7D14
2
4.7UF 10% 6.3V X5R 805
1
C7R121
C7R6
2
4.7UF 10% 6.3V X5R 805
DEC ECO OUP UPLI LIN NG]
2
1
C7R94
2
10% 4.7UF 6.3V X5R 805
1
C7E1
2
10% 4.7UF 6.3V X5R 805
C7R119
2
4.7UF 10% 6.3V X5R 805
1
1
10% 4.7UF 6.3V X5R 805
1
2
10% 4.7UF 6.3V X5R 805
1
C7E7
2
10% 4.7UF 6.3V X5R 805
1
C7D13
2
10% 4.7UF 6.3V X5R 805
1
C7T83
2
10% 4.7UF 6.3V X5R 805
1
C7D11
2
10% 4.7UF 6.3V X5R 805
1
C7T84
2
10% 4.7UF 6.3V X5R 805
DECO DE COUP UPLIN LING G
1
C7D9
2
4.7UF 10% 6.3V X5R 805
1
C7R5
2
4.7UF 10% 6.3V X5R 805
1
C7T34
2
4.7UF 10% 6.3V X5R 805
1
C7R26
2
4.7UF 10% 6.3V X5R 805
1
C7R117
2
4.7UF 10% 6.3V X5R 805
1
C7T96
2
4.7UF 10% 6.3V X5R 805
1
C7R92
2
4.7UF 10% 6.3V X5R 805
1
C7D6
2
4.7UF 10% 6.3V X5R 805
1
C7D17
2
4.7UF 10% 6.3V X5R 805
1
C7R27
2
10% 4.7UF 6.3V X5R 805
1
C7D8
2
10% 4.7UF 6.3V X5R 805
1
C7D4
2
10% 4.7UF 6.3V X5R 805
1
C7D18
2
10% 4.7UF 6.3V X5R 805
1
C7D7
2
10% 4.7UF 6.3V X5R 805
1
C7E16
2
10% 4.7UF 6.3V X5R 805
1
C7R91
2
10% 4.7UF 6.3V X5R 805
1
C7R29
2
10% 4.7UF 6.3V X5R 805
1
C7E4
2
10% 4.7UF 6.3V X5R 805
1
C7D10
2
10% 4.7UF 6.3V X5R 805
1
C7R4
2
10% 4.7UF 6.3V X5R 805
1
C7T35
2
10% 4.7UF 6.3V X5R 805
1
C7D5
2
10% 4.7UF 6.3V X5R 805
1
C7R93
2
10% 4.7UF 6.3V X5R 805
1
C7T95
2
10% 4.7UF 6.3V X5R 805
1
C7D3
2
10% 4.7UF 6.3V X5R 805
1
C7R120
2
10% 4.7UF 6.3V X5R 805
1
C7D15
2
10% 4.7UF 6.3V X5R 805
1
C7R3
2
1
4.7UF 10% 6.3V X5R 805
1
C7R30
2
1
4.7UF 10% 6.3V X5R 805
1
C7R90
C7E2
2
1
2 1
C7E15
C7E9
2
C7T86
1
2
C7T97
1
2
C7D22
1
2
2
1
C7R16
2
.1UF 10% 6.3V X5R 402
2
C7T88
2
C7R12
2
C7R10
2
1
C7R11
2
.1UF 10% 6.3V X5R 402
2
1
4.7UF 10% 6.3V X5R 805
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 03 03
C7T76
C7T45
.1UF 10% 6.3V X5R 402
4.7UF 10% 6.3V X5R 805
1
2
1
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
4.7UF 10% 6.3V X5R 805
1
C7T77
2
.1UF 10% 6.3V X5R 402
4.7UF 10% 6.3V X5R 805
1
2
C7T1
1
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
4.7UF 10% 6.3V X5R 805
1
C7T78
.1UF 10% 6.3V X5R 402
4.7UF 10% 6.3V X5R 805
1
2
.1UF 10% 6.3V X5R 402
4.7UF 10% 6.3V X5R 805
1
C7T79
.1UF 10% 6.3V X5R 402
C7R13
2
.1UF 10% 6.3V X5R 402
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 9/73
REV K7
GPU, GP U, PL PLL L
POW PO WER + FSB PO POWE WER R
V_GPUCORE FB4D1 2
1
120
0 .5 .5
0.2A D CR CR
FB 603
1
C4D6
1
2.2UF 10%
6.3V X5R 603
2
2
C4D5 .1UF 10% 6.3V X5R 402
1
C4D4 0.01UF
2
10% 16V
X7R 402
V_GPUCORE V_GPUPCIE
U4D1
2
120
0 .5 .5
0.2A D CR CR
V_PVDDA
FB 603
1
C4T48
1
2.2UF 10%
6.3V X5R 603
2
2
1
C4T30 .1UF 10% 6.3V X5R 402
C4T37 0.01UF 10% 16V
X7R 402
2
C5R7 .1UF 10% 6.3V X5R 402
V_PVDDA_MEM
FB4R1 2
1
120
0 .5 .5
0.2A D CR CR
8
V_PVDDA_ED
FB 603
1
C4R68
1
2.2UF 10%
2
6.3V X5R 603
2
C4R4 .1UF 10% 6.3V X5R 402
C4R6 0.01UF 10% 16V
X7R 402
V_PVDDA_FSB
1
2
C4R8 .1UF 10% 6.3V X5R 402
A20 A21 C27
PVDDA PVSSA
C26
VDD_BSB1 VSS_BSB1
C25 C24
VDD_BSB0 VSS_BSB0
AG10 AG9
PVDDA_MEM PVSSA_MEM
A18 A19
PVDDA_ED PVSSA_ED
B25 B24
PVDDA_PEX PVSSA_PEX
G34 F34
PVDDA_FSB PVSSA_FSB
V_GPUPCIE
IC
OF 1 2
GPU VERSI VERSION ON
FB4T1 1
57 VDD_FSB24 VDD_FSB23 VDD_FSB22 VDD_FSB21 VDD_FSB20 VDD_FSB19 VDD_FSB18 VDD_FSB17 VDD_FSB16 VDD_FSB15 VDD_FSB14 VDD_FSB13 VDD_FSB12 VDD_FSB11 VDD_FSB10 VDD_FSB9 VDD_FSB8 VDD_FSB7 VDD_FSB6 VDD_FSB5 VDD_FSB4 VDD_FSB3 VDD_FSB2 VDD_FSB1 VDD_FSB0
AA27 AB28 AB32 AC27 AD28 AD31 K28 K31 L27
M28 M32 N27
P28 P31
R28 R32 T27
U28 U31 V27
V30 W28 W32 Y28 Y31
X02056-010
1
2
C4R5 .1UF 10% 6.3V X5R 402
C4R7 0.01UF 10% 16V
X7R 402
FB5R1 1
120
0 .5 .5
0.2A D CR CR
2
FB 603
1
2
[PA [P AGE_TIT ITL LE=GPU,
C5R19 2.2UF 10% 6.3V X5R 603
PLL
1
2
C5R13 .1UF 10% 6.3V X5R 402
C5R15 0.01UF 10% 16V
X7R 402
POWER + FSB FSB
POWER]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 10 10
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 16/73
REV K7
GPU,, GPU
DECOUP DEC OUPLIN LING G
V_GPUCORE
V_GPUCORE
1
C4R20
2
.1UF 10% 6.3V X5R 402
1
C4R37
2
.1UF 10% 6.3V X5R 402
1
C4R59
2
.1UF 10% 6.3V X5R 402
1
C4T6
2
.1UF 10% 6.3V X5R 402
1
C4T9
2
.1UF 10% 6.3V X5R 402
1
C4R57
2
.1UF 10% 6.3V X5R 402
1
C4T11
2
.1UF 10% 6.3V X5R 402
1
C4T3
2
.1UF 10% 6.3V X5R 402
1
C4R52
2
.1UF 10% 6.3V X5R 402
1
C4R18
2
.1UF 10% 6.3V X5R 402
[PAG [PA GE_ E_TIT TITLE LE=G =GPU PU,,
1
C4R11
2
.1UF 10% 6.3V X5R 402
1
C4R17
2
.1UF 10% 6.3V X5R 402
1
C4R55
2
.1UF 10% 6.3V X5R 402
1
C4R47
2
.1UF 10% 6.3V X5R 402
1
C4T20
2
.1UF 10% 6.3V X5R 402
1
C4R36
2
.1UF 10% 6.3V X5R 402
1
C4R34
2
.1UF 10% 6.3V X5R 402
1
C4R42
2
.1UF 10% 6.3V X5R 402
1
C4T16
2
.1UF 10% 6.3V X5R 402
1
C4T1
2
.1UF 10% 6.3V X5R 402
1
C4R16
2
.1UF 10% 6.3V X5R 402
1
C4R21
2
.1UF 10% 6.3V X5R 402
1
C4T5
2
.1UF 10% 6.3V X5R 402
1
C4T21
2
.1UF 10% 6.3V X5R 402
1
C4R46
2
.1UF 10% 6.3V X5R 402
1
C4T8
2
.1UF 10% 6.3V X5R 402
1
C4R35
2
.1UF 10% 6.3V X5R 402
1
C4R54
2
.1UF 10% 6.3V X5R 402
1
C4R63
2
.1UF 10% 6.3V X5R 402
1
C4T2
2
.1UF 10% 6.3V X5R 402
DECO DE COUP UPLI LING NG]]
1
C4R28
2
.1UF 10% 6.3V X5R 402
1
C4R22
2
.1UF 10% 6.3V X5R 402
1
C4T23
2
.1UF 10% 6.3V X5R 402
1
C4R44
2
.1UF 10% 6.3V X5R 402
1
C4T24
2
.1UF 10% 6.3V X5R 402
1
C4T19
2
.1UF 10% 6.3V X5R 402
1
C4T18
2
.1UF 10% 6.3V X5R 402
1
C4R62
2
.1UF 10% 6.3V X5R 402
1
C4R43
2
.1UF 10% 6.3V X5R 402
1
C4R56
2
.1UF 10% 6.3V X5R 402
1
C4R13
2
.1UF 10% 6.3V X5R 402
1
C5R17
2
.1UF 10% 6.3V X5R 402
1
C4R53
2
.1UF 10% 6.3V X5R 402
1
C4R41
2
.1UF 10% 6.3V X5R 402
1
C4T26
2
.1UF 10% 6.3V X5R 402
1
C4T25
2
.1UF 10% 6.3V X5R 402
1
C4T4
2
.1UF 10% 6.3V X5R 402
1
C4R58
2
.1UF 10% 6.3V X5R 402
1
C4T10
2
.1UF 10% 6.3V X5R 402
1
C4T15
2
.1UF 10% 6.3V X5R 402
1
C5R9
2
.1UF 10% 6.3V X5R 402
1
C5R16
2
.1UF 1 0 % 6.3V X5R 402
2
C5R10
1
.1UF 10% 6.3V X5R 402
1
C5R12
1
C4R39
2
.1UF 10% 6.3V X5R 402
1
C4R49
2
.1UF 1 0 % 6.3V X5R 402
2
C4R67
1
.1UF 10% 6.3V X5R 402
2
C4R24
C4R40
2
C5R8
C4R9
2
C5R14
C4R14
2
1
C5R4
C5R2
2
2
2
1
2
2
2
2
1
C5R11
2
2
C5R6
2
1
2 00 00 5
C6R47
1
C4R69
1
C5D3
1
C5D4
1
C5D6
1
10% 4.7UF 6.3V X5R 805
2
1
10% 4.7UF 6.3V X5R 805
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 12 12
1
10% 4.7UF 6.3V X5R 805
10% 4.7UF 6.3V X5R 805
.1UF 10% 6.3V X5R 402
C6E1
10% 4.7UF 6.3V X5R 805
10% 4.7UF 6.3V X5R 805
2
1
10% 4.7UF 6.3V X5R 805
1
C5R3
2
C6E2
10% 4.7UF 6.3V X5R 805
10% 4.7UF 6.3V X5R 805
2
1
10% 4.7UF 6.3V X5R 805
2
C5R1
2
C4T17
10% 4.7UF 6.3V X5R 805
1
C5R20
1
.1UF 10% 6.3V X5R 402
1
C5R5
2
1
10% 4.7UF 6.3V X5R 805
10% 4.7UF 6.3V X5R 805
.1UF 10% 6.3V X5R 402
1
2
1
10% 4.7UF 6.3V X5R 805
2
.1UF 10% 6.3V X5R 402
1
C4R30
10% 4.7UF 6.3V X5R 805
.1UF 10% 6.3V X5R 402
1
2
C4R29
10% 4.7UF 6.3V X5R 805
10% 4.7UF 6.3V X5R 805
.1UF 10% 6.3V X5R 402
1
2
1
10% 4.7UF 6.3V X5R 805
2
.1UF 10% 6.3V X5R 402
1
C5D2
2
10% 4.7UF 6.3V X5R 805
C5D5
1
10% 4.7UF 6.3V X5R 805
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 18/73
REV K7
V_1P8 FB1N1 2
1
2
46
39
1
TP
44
19
39
V_ENET
IN
39
1
36
33
39
36
39
4.7K
36
39
EMPTY 402
36
39
36
39
36
39
36
39
39
36
R1B12 5%
2 36
39
OUT
MII_RXD0
39
39 39
36 36
19
IN
39
36
39
36
39
36
ENET_REF_CLK2_OUT
10
20
MII_RXDV MII_RXER
19 21
RXC RX_DV/TEST0 RX_ER/TEST1
OUT OUT OUT
MII_RXD3 MII_RXD2 MII_RXD1
15 16 17 18
RXD3/ISOLATE RXD2/F100 RXD1/ANEN RXD0/PHYAD0
OUT
MII_TX_CLK
23 24
TXC TX_EN
MII_TXEN
28
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
27
26 25 14 13
39
36
39
OUT OUT
29
MII_COL MII_CRS
ENET_AVDD 1
2
[PA [P AGE_TI TITL TLE E=DUAL
ETH ET HERNET
PHY] PHY]
19
C1N14 .1UF 10%
2
6.3V EMPTY 402
EMPTY BCM5241
MII_RX_CLK
MII_MDIO
36
10UF 20% 6.3V EMPTY 805
1
XTALI2 XTALO2
ENET_RST_N
IN IN IN IN
C1N7
U1B1 1 2
MII_MDC_CLK_OUT
IN BI
2
OUT OUT OUT
IN
IN
36
1
10UF 10% 6.3V EMPTY 1206
DB1N1
OUT
EMPTY 603
C1N8
ENET_CLK
IN
ENET_AVDD
1
60
0.5A 0.1DCR
RESET_N
OVDD2 OVDD1 AVDD LINK# ACT# TDP TDN
TXD3 TXD2 TXD1 TXD0
RDP RDN
RDAC MDC_CLK_OUT MDIO
30
COL/ENERGYDET CRS/LOWPWR0
31 32
REGVDDIN REGVDDOUT
GND
22 9
V_ENET
ENET_AVDD
7
12 11
ENET_LINK_N ENET_ACT_N
3 4
ENET_RX_DP
6 5
ENET_TX_DP
ENET_RX_DN
ENET_TX_DN
IN
39
IN
19
OUT OUT
39
44
39
44
OUT OUT
39
44
39
44
OUT OUT
39
44
39
44
19
44
8
33
C A D R _ T E N E
1
R1N8 1.27K
C1N6
.1UF 10% 6.3V EMPTY 402
1%
X 801554-001
LC C32 2
EMPTY 402
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 13 13
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 19/73
REV K7
ANA NA,,
V_12P0
CLO CL OCK CKS S + ST STRA RAPP PPIN ING G
ANA_V_12P0_DET_R
V_3P3STBY
R4B9
1
1% CH
FT2P7
1
FTP
1
1K 5%
FT3N1
FTP
1
of of
1
1K 5%
95
IN
1
138 16
ANA_POR_BYPASS
V_12P0_DET CORE_RST_N*
POR_BYPASS
V_RST_OK V_12P0_OK SMC_RST_N*
120
46
34
IN
FTP
ANA_XTAL_IN
FT2P4
130 131
XTAL_IN XTAL_OUT
ANA_CLK_OE
1K
2
1
2
122 140
1
R2P1
2
SMC_RST_N_R
ANA_CLK_OE_R
139
ANA_CLK_OE
36
ANA_PLL_BYP_VID_VREF
CH
402
30 29
ANA_CPU_CLK_DP
NB_CLK_DP NB_CLK_DN
27 26
ANA_GPU_CLK_DP
XTAL_BYPASS
R4B16
10K 5%
CPU_CLK_DP CPU_CLK_DN
24
ANA_CLK_DRV_RSET
VREFGEN_18S1 CLK_DRV_RSET
1
1 1 1 1
ANA_PCIEX_CLK_DN ANA_SATA_CLK_DP
SATA_CLK_REF
13
ANA_SATA_CLK_REF
1 1
ANA_SATA_CLK_DN
1
CH 46 46
56 56
34 34
33 32
ANA_PIX_CLK_2X_DP_R
ENET_CLK
11
ANA_ENET_CLK
1
STBY_CLK
136
ANA_STBY_CLK
1
14
AUD_CLK_R
BI IN
SMB_DATA SMB_CLK
8 9
35
PLL_BYP_VID
AUD_CLK SMB_DATA SMB_CLK
PLL_BYP_VID
1
AV_CLK
R4P4 72 69 71 70
ANA_TCLK
CH
ANA_TDO
402
ANA_TDI ANA_TMS
1
R4P3
1
332 1%
CH 2
402
FTP
FT3P4
TP
DB3C3
TP
DB3C4
TP
DB3C1
TP
DB3C2
TP
DB3B4
TP
DB3B3
TP
DB3B2
TP
DB3B1
2
56
ANA_PIX_CLK_2X_DN_R DB3N2 TP
DB4N4 TP
R3C14
1
127
1
AV_CLK
FTP
TCK TDO
2
1% CH
ANA_PIX_CLK_2X_DP ANA_PIX_CLK_2X_DN R3C13 5% CH
33
402
R3C19
1
2
49.9 402
2
1 1
1% CH
402
2
1
R3B15
FT4P1
FTP
2
AUD_CLK
1
1%
2
1 3
4
5
6
1
R5C3
CH
CH
J5C1
402
402
1%
CLOCKS
STITCH STITC H
V_3P3
STITCH STITC H
1
402
+ ST STR RAPP PPIN ING G
C1B4
1
.1UF
CH
[PAG [P AGE_ E_TI TITL TLE E=ANA,
2
SATA_CLK_REF SATA_CL K_REF
V_3P3 ENET_CLK ENET_CL K
EMPTY
1.5K
2
50V EMPTY 402
10K 5%
1.5K
1%
C3B12
R4P5
R5C1
1.5K
2
36
10PF
1
1
R5C2
2X3HDR
FT2P2
5%
2
2
FTP
OUT
1
V_1P8STBY
402
FT4P2 FT4P3
5% CH
33
402
CH
13
FTP FTP
CH
QFP144
1
1
13
10K 5%
.1UF 10% 6.3V X5R 402
V_1P8STBY
OUT OUT
R4B7
TMS X02014-005
C4P6
49.9 402
FT4N5
1
TDI
R3C20
1
2
5% CH
33
402
1
332 1%
2
FT2N3
DB3N3
1%
402
46
FTP
TP
PIX_CLK_OUT_DP PIX_CLK_OUT_DN
475
1 1
ANA_PCIEX_CLK_DP
19 18
R4P1
2
48
34
1
ANA_GPU_CLK_DN
SATA_CLK_DP SATA_CLK_DN
1
V_1P8STBY
34
5% CH
ANA_CPU_CLK_DN
22 21
PCIEX_CLK_DP PCIEX_CLK_DN
5% CH
402
XTAL_VSS
126
ANA_XTAL_BYPASS
R4B17
2
FT4N2
402
10K
132
1
FTP
OUT OUT
R2P3
IC
3
402
46
1
CH
ANA_RST_N
IN
ANA_VRST_OK ANA_V12P0_PWRGD SMC_RST_N
ANA VERSI SION ON 112
ANA_V_12P0_DET 34
U4B1
10K 402
402
1
2
68.1 402 1
50V EMPTY 402
2
2
5% CH
CH
1% CH
402
5%
R3B1
1
R4B2
1
2 75
1% CH
C4N28 470PF
2
R4B3
R4B8
1
2 1K
402
2
6.3V X5R 402
1
C2B14 .1UF
10%
10%
2
6.3V X5R 402
2
C2B17 .1UF 10% 6.3V X5R 402
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 18 18
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 28/73
REV K7
ANA,
VIDEO U4B1
V_1P8STBY
13
IN
13
IN
GPU_PIX_CLK_1X
PIX_CLK_IN
67 66 64
52 49 48 47 46 44
PIX_DATA14 PIX_DATA13 PIX_DATA12 PIX_DATA11 PIX_DATA10 PIX_DATA9 PIX_DATA8 PIX_DATA7 PIX_DATA6 PIX_DATA5 PIX_DATA4 PIX_DATA3 PIX_DATA2 PIX_DATA1 PIX_DATA0
GPU_VSYNC_OUT GPU_HSYNC_OUT
42 41
HSYNC_IN VSYNC_IN
ANA_VID_VREF
54
VREFGEN_18S0
14 13 12 11 10
1
R4P7 332 1%
8
CH
2
63 61 60 58 57 53
9
402
7
6 5 4
1
1
R4P6 332 1%
2
10%
1 0
.1UF
2
CH
2
3
C4P12
402
6.3V X5R 402
13 13
IN IN
R4B12
2
IC
2 OF 3 ANA AN A VERSION ON
55
PIX_DATA<14..0>
+ FAN + JTAG 95
128
ANA_VID_INT
OUT
33
DAC_A_OUT_DP DAC_A_OUT_DN
92 91
VID_DACA_DP VID_DACA_DN
OUT
43
DAC_B_OUT_DP DAC_B_OUT_DN
95 94
VID_DACB_DP VID_DACB_DN
OUT
43
DAC_C_OUT_DP DAC_C_OUT_DN
99 100
VID_DACC_DP VID_DACC_DN
OUT
43
DAC_D_OUT_DP DAC_D_OUT_DN
102 103
VID_DACD_DP VID_DACD_DN
OUT
43
HSYNC_OUT VSYNC_OUT
115 116
VID_HSYNC_OUT_R VID_VSYNC_OUT_R
OUT OUT
43
VID_INT
1
ANA_DAC_RSET
97
DAC_RSET
86 87
FAN_OP2_DP FAN_OP2_DN
FAN_OUT2
88
FAN2_OUT
82 83
FAN_OP1_DP FAN_OP1_DN
FAN_OUT1
84
FAN1_OUT
76
TEMP_N
1%
CH
CH
CH
402
37.4
2
SMC_PWM1
R4B15
1
1% CH
205K 402
FAN_OP2_DP
1
10%
2
42
IN
FAN2_FDBK
42
IN
FAN1_FDBK
C4N24 .22UF
IN
SMC_PWM0
2
205K 402
R4C1
1
1% CH
FTP
FAN_OP1_DP
1
OUT
42
R4B14
37.4
37.4
1% CH
402
2
2
402
OUT
42
FT4N4
111
BND_GAP_CAP
C4P2
78
TEMP_RSET
.22UF
BND_GAP_CAP TEMP_RSET
TP
1 DB4P2
DB5P2
TP
TP
1
TEMP3_P TEMP2_P TEMP1_P TEMP0_P TEMPCAL_P
75 77 79 80 73
CUSTOM THERMAL CALIBRAT CALI BRATION PADS LOCATI LOC ATION ON MUS MUST T REMAIN LOCKED
DB5P1
TP
1
6.3V X5R 402
1 34
402
2
DB4P1
IN
1
R4B13
1%
1% CH
806 402
34
1
R4B11
1%
37.4
2
1
1
R4B10
43
1
CAL_TEMP_P
CAL_TEMP_N CPU_TEMP_P GPU_TEMP_P EDRAM_TEMP_P BRD_TEMP_P
OUT OUT OUT OUT OUT
29 4 13 13
29
10%
2
6.3V X5R 402
X02014-005
QFP144 1
DB4P3
4
IN
CPU_TEMP_N
2
2
ST4C1
13
IN
2
GPU_TEMP_N
0.01UF
IN
EDRAM_TEMP_N
2
29
IN
BRD_TEMP_N
2
10% 16V
1
X7R 402
1
SHORT 13
C4B3
1
SHORT ST4C2
ST4C5
FT4N1
1
IN
2
CAL_TEMP_N
ST4C3
.1UF
11K 1%
CH 2
402
STBY_CLK STBY_CL K 1
STITCH
V_1P8STBY
V_3P3STBY
V_3P3STBY
MMBT3906 XSTR
2
1
1
1
2
3
C2R2 .1UF 10% 6.3V X5R 402
29
[PAG [P AGE_ E_T TIT ITLE LE= =AN ANA, A,
OUT
BRD_TEMP_P BRD_TEMP_N
VIDE VI DEO O
1
C2R1
1
.1UF
6.3V X5R 402
C3N10 .1UF
10%
2
1
10%
2
6.3V X5R 402
C2P50 .1UF 10%
2
V_1P8STBY
3
IN
V_1P8STBY
Q1G3
SHORT
29
V_1P8
10%
6.3V X5R 402
2
1
SHORT 29
C1P13
R4C2
SHORT ST4C4
2
STITCH
V_3P3
10%
50V EMPTY 402
1
1
FTP
SATA_CLK_REF SATA_CLK _REF
C5C6
1000PF
TP
1
6.3V X5R 402
Q1G1
1
2
MMBT2222 EMPTY
+ FAN FAN + JTAG JTAG]]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 19 19
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 29/73
REV K7
ANA, AN A,
POWE PO WER R + DE DECO COUP UPLI LING NG
V_1P8STBY FB3B2 2
1
1
V_1P8STBY
1
OUT
FB 603
0.2A D CR CR
1
C4N13 10UF 10% 6.3V X5R 1206
2
10%
ANA_VDD_DAC18S
2
1
120
0 .5 .5
C4N26
1
2.2UF
1
C4B6
.1UF
10%
6.3V X5R 603
2
6.3V X5R 402
2
10%
of of
ANA VERSI SION ON 104 90 105
FB4N4 60
FB 603
0.5A 0.1DCR
ANA_VDD_I18S
2
C4P4 10UF 20% 6.3V X5R 805
C4N21
C4P7
.1UF 10% 6.3V X5R 402
C4P3
.1UF 10% 6.3V X5R 402
C4P11
.1UF
.1UF
10%
10%
6.3V X5R 402
C4P9 .1UF 10%
6.3V X5R 402
6.3V X5R 402
V_1P8STBY
FB4N3 1
2
60
FB 603
0.5A 0.1DCR
C4N14 10UF 10% 6.3V X5R 1206
20 43 51 65 17 28 34 56 62
VSS_I18S4 VSS_I18S3 VSS_I18S2 VSS_I18S1 VSS_I18S0
121 134 10 25 45
ANA_VDD_C18S
1
2
C4N15 C4N19 10UF 20% 6.3V X5R 805
.1UF 10% 6.3V X5R 402
C4 P8
C4P10
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
C4P1 .1UF 10% 6.3V X5R 402
59
C4N11 .1UF 10% 6.3V X5R 402
C4N7 .1UF 10%
6.3V X5R 402
119 133 7
23 50 68 117 125 123 124 135 12
V_3P3STBY 118 137 15
C4N5 .1UF 10%
6.3V X5R 402
C4N6 .1UF
C4N8 .1UF
10%
10%
6.3V X5R 402
6.3V X5R 402
95
2
0 .5 .5
10UF 20% 6.3V X5R 805
FB 603
0.2A D CR CR
VSS_C18S5 VSS_C18S4 VSS_C18S3 VSS_C18S2 VSS_C18S1 VSS_C18S0
VAA_PLL18S6 AVSS_PLL18S6
142 141
VSS_I33S2 VSS_I33S1 VSS_I33S0
VAA_PLL18S5 AVSS_PLL18S5
144 143
VAA_PLL18S4 AVSS_PLL18S4
2
VAA_PLL18S3 AVSS_PLL18S3
4
VAA_PLL18S2 AVSS_PLL18S2
6
1
2
.1UF 10%
X02014-005
1 5
VAA_PLL18S0 AVSS_PLL18S0
40
ANA_VAA_PLL18S0
129
VAA_FAN33S AVSS_FAN33S
85 89
V_3P3STBY R4N1
1
ANA_VAA_XTAL33S
1 00
VAA_POR33S AVSS_POR33S
114 110
VAA_RTS33S AVSS_RTS33S
74 81
VAA_DAC33M2 VAA_DAC33M1 VAA_DAC33M0
96 101 106
1
2
C4N22 .1UF 10% 6.3V X5R 402
1
1
C4N9 .1UF 10% 6.3V X5R 402
2
.22UF 10% 6.3V X5R 402
1
2
2
5% CH
C3B9 .22UF 10% 6.3V X5R 402
C4N4
V_1P8STBY
.1UF 10%
2
6.3V X5R 402
FB4C2
C4C4
1
.22UF 10%
93 98
2
S 3 3 S T R _ A A V _ A N A
107 108
2
C4P5 .1UF 10% 6.3V X5R 402
0 .5 .5
1
1
2
120
M 3 3 C A D _ A A V _ A N A
6.3V X5R 402
2
C4C5
0 .5 .5
10UF 20% 6.3V X5R 805
120 0.2A D CR CR
FB
603
V_3P3STBY FB4P1
ANA_VDD_DAC18S 1
2
1
1
1
IN
C3B8
39
VAA_XTAL33S
QFP144
30
.22UF 10% 6.3V X5R 402
3
38 37
NC<1> NC<0>
C4B9
1
VAA_PLL18S1 AVSS_PLL18S1
AVSS_DAC33M1 AVSS_DAC33M0
.22UF 10% 6.3V X5R 402
ANA_VAA_PLL18S1
402
VDD_I33S3 VDD_I33S2<2> VDD_I33S2<1> VDD_I33S2<0> VDD_I33S1 VDD_I33S0
C4B5
113 109
2
VDD_C18S5 VDD_C18S4 VDD_C18S3 VDD_C18S2 VDD_C18S1 VDD_C18S0
C4N17 6.3V X5R 402
6.3V X5R 402
IC
3 VAA_POR18S AVSS_POR18S
VDD_DAC18S1 VDD_DAC18S0 VSS_DAC18S VDD_I18S4 VDD_I18S3 VDD_I18S2 VDD_I18S1 VDD_I18S0
31
1
1
.1UF
3
V_1P8STBY
2
2
C4N10
10%
6.3V X5R 402
6.3V X5R 402
2
120
C3B3
C4B7
.1UF
10%
2
V_1P8STBY
30
U4B1
1
1
C4B4 .22UF
FB4N2
0.2A D CR CR
10%
2 1
C4P13 2.2UF
C4N23
6.3V X5R 402
10UF
10%
10%
6.3V X5R 603
2
C4C3 .22UF
FB 603
2
6.3V X5R 1206
V_3P3 FB4N1
1
C4N18
1
.1UF
[PAG [P AGE_ E_TI TITL TLE= E=AN ANA, A,
POWE PO WER R + DE DECO COUP UPLIN LING] G]
6.3V X5R 402
1
.1UF
10%
2
C4N16 6.3V X5R 402
1
.1UF
10%
2
C4N12 10%
2
6.3V X5R 402
2
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 20 20
C4N2 10UF 20% 6.3V X5R 805
2 00 00 5
1
2
60
FB 603
0.5A 0.1DCR
1
2
C4N3 10UF 10% 6.3V X5R 1206
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 30/73
REV K7
DEBUG DEB UG BOA BOARD RD MAPP MAPPIN ING G
IN
CPU_DBGSEL_DEBUG<0..69> N:CONNECT N:CONNEC T TO CPU DEBUG OUT
[PAG [P AGE_ E_TI TITL TLE E=DEBU BUG G
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18 19 20
10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26
21 22 23 24 25 26
27 28 29 30 31
27 28 29 30 31
32
32
33 34 35 36 37 38
33 34 35 36 37 38
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
XDK BOAR BOARD D MAPP MAPPIN ING G
CPU_DBG_TERM<0..69>
MAP APPI PIN NG,
57
OUT
IN
CPU_DBGSEL_XDK<0..69> N:CONNECT N:CONNEC T TO CPU DEBUG OUT
1 1 1
FTP FTP FTP
52 53 54
56 57 58 59 60 61 62
63
WN DEBU BUG G VS WN XD XDK K]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 21 21
FT6U11 FT6U9 FT6U10
1 1 1
DBG_WN_POST_OUT0 DBG_WN_POST_OUT1 DBG_WN_POST_OUT2 DBG_WN_POST_OUT3 DBG_WN_POST_OUT4 DBG_WN_POST_OUT5 DBG_WN_POST_OUT6 DBG_WN_POST_OUT7
2 00 00 5
MICROSOFT CONFIDENTIAL
1 1 1 1 1 1 1 1
DB6E1 DB6E2 DB6E3
FTP FTP FTP FTP FTP FTP FTP FTP
FT6U8 FT6U2 FT6U3 FT6U4 FT6U5 FT6U6 FT6U7 FT6U1
PROJECT NAME XENON_RETAIL
PAGE 31/73
REV K7
POWER PO WER TRACE TRACE DEC DECOUP OUPLING LING V_12P0
V_12P0
1
C7G2
0.01UF
16V
2
10%
X7R 402
1
C4N27
0.01UF
2
10%
16V
X7R 402
1
C9F2
0.01UF
16V
2
10%
X7R 402
1
C9E2
0.01UF
16V
V_5P0STBY
1
C3N2
1
C1N12
1
1
C1C7
16V
2
2
10%
X7R 402
1
C1C15
0.01UF
2
10%
16V
X7R 402
1
C7N1
0.01UF
16V
2
10%
X7R 402
1
C6N1
0.01UF
16V
2
10%
X7R 402
1
C5N1
0.01UF
16V
2
.1UF 10% 6.3V X5R 402
10%
C9C7
2
.1UF 10% 6.3V X5R 402
X7R 402
0.01UF
2
.1UF 10% 6.3V X5R 402
V_5P0
1
C7B1
2
.1UF 10% 6.3V X5R 402
1
C6B1
2
.1UF 10% 6.3V X5R 402
1
C4B8
2
.1UF 10% 6.3V X5R 402
1
C1D8
V_3P3STBY
1
C5V1
2
.1UF 10% 6.3V X5R 402
1
C3U3
2
.1UF 10% 6.3V X5R 402
1
C2T4
2
.1UF 10% 6.3V X5R 402
2
C1B2
C1C1
2
C1D10
C1B3
1
C2G1
2
.1UF 10% 6.3V X5R 402
1
C3G3
2
.1UF 10% 6.3V X5R 402
1
2
C5G3
2
C1C12
1
C1C8
2
.1UF 10% 6.3V X5R 402
1
C8G2
2
.1UF 10% 6.3V X5R 402
1
C1F1
2
.1UF 10% 6.3V X5R 402
1
C5G5
2
.1UF 10% 6.3V X5R 402
54
1
C9N1
IN
V_VREG_V1P8V5P0
2
1
1
C5N2
1
2
C3N1
2
C5G1
2
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
1
C4F13
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
2
.1UF 10% 6.3V X5R 402
1
C7N2
2
.1UF 10% 6.3V X5R 402
2
1
C1N13
2
.1UF 10% 6.3V X5R 402
2
1
.1UF 10% 6.3V X5R 402
1
2
V_1P8
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
1
C2F2
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
1
1
.1UF 10% 6.3V X5R 402
1
.1UF 10% 6.3V X5R 402
1
V_5P0DUAL
C1G1
2
.1UF 10% 6.3V X5R 402
2
1
.1UF 10% 6.3V X5R 402
C1F2
2
.1UF 10% 6.3V X5R 402
2
10%
X7R 402
1
C4N1
0.01UF
2
10%
16V
X7R 402
[PAG [P AGE_ E_TI TITL TLE= E=PO POW WER
TRAC TR ACE E
EMII EM
CAPS PS]]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 22 22
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 32/73
REV K7
SB,
SMC V_12P0
46 56
46
28
STBY_CLK SMC_RST_N
IN
IN
2
R8N17 4.7K 5% CH
1
OUT
47
R2N15
2
TRAY_OPEN
1
402
50V X7R 603
2
VREG_GPU_PWRGD U2C1
56
43
IN
R2M1
2
EXT_PWR_ON_N
10K
402
1
35
R2P4
5%
5%
2.2K
FT2P24 FT2P15
C17
SMC_RST_N*
G20
SB_RST_N*
34
IN
SB_MAIN_PWRGD
G19
MAIN_PWR_OK
D16
SMC_UART1_RXD
56
IN
SMC_DBG_EN
C16
SMC_DBG
A18 B18 C18 D18 A19 B19 C19 A20
SMC_P4_GPIO7 SMC_P4_GPIO6 SMC_P4_GPIO5 SMC_P4_GPIO4 SMC_P4_GPIO3 SMC_P4_GPIO2 SMC_P4_GPIO1 SMC_P 4_ 4_GPIO0
SMC_P2_GPIO7 SMC_P2_GPIO6 SMC_P2_GPIO5 SMC_P2_GPIO4 SMC_P2_GPIO3 SMC_P2_GPIO2 SMC_P2_GPIO1 SMC_P 2_ 2_GPIO0
E22
46
56
28
46
28
56
43
BI BI
SMB_DATA SMB_CLK
IN
AV_MODE2
2
F20 F19
ANA_RST_N VREG_GPU_EN_N PSU_V12P0_EN ANA_CLK_OE
AV_MODE2_R
B20 C20 C22
SMC_P1_GPIO7 SMC_P1_GPIO6 SMC_P1_GPIO5 SMC_P1_GPIO4 SMC_P1_GPIO3 SMC_P1_GPIO2 SMC_P1_GPIO1 SMC_P1_GPIO0
VREG_CPU_EN
B21
AV_MODE0_R
SMC_P3_GPIO7 SMC_P3_GPIO6 SMC_P3_GPIO5 SMC_P3_GPIO4 SMC_P3_GPIO3 SMC_P3_GPIO2 SMC_P3_GPIO1 SMC_P3_GPIO0
Y21
AV_MODE1_R
AB20 Y20 AA19 AB19
VREG_V5P0_EN_N VREG_V5P0_SEL VREG_V1P8_EN_N BINDSW_N TILTSW_N EJECTSW_N
1 0K
402 43
IN
10K
402
SMC_P0_GPIO7 SMC_P0_GPIO6 SMC_P0_GPIO5 SMC_P0_GPIO4 SMC_P0_GPIO3 SMC_P0_GPIO2 SMC_P0_GPIO1 SMC_P0_GPIO0
J20
GPU_RST_DONE_R
43
IN
AV_MODE0
H21 H19 H20
CPU_RST_N SB_MAIN_PWRGD_R SB_RST_N
1 0K 43
56
13
56 56
35
IN
BI BI BI
402
DDC_CLK
40
1
AUD_CLAMP
D22
1
D21
D20
5% CH
5% CH
DBG_LED3 DBG_LED2 DBG_LED1
42
2
1
EMPTY 402
R2B18
2K 1%
1
IR_DATA
A16
SMC_IR_IN
2
R2B19
2K 1%
IN
EMPTY 402
2K 1%
1
DB2P8
TP
1
TP
1
DB2P9
EMPTY 402
EN_TEST1_N EN_TEST0_N
G22 G21
56
OUT
SMC_UART1_TXD
B16
SMC_DBG_TXD_R
R2N9
1
402
SMC_PWM1 SMC_PWM0
E21
E20 E19 F22 F21
Y22 AA20 AA21
J19 J22
PWRSW_N VREG_3P3_EN_N ANA_V12P0_PWRGD
2
R7V4
10K
V_5P0
2
5% CH
402
5% CH
VREG_CPU_PWRGD
IN
28
OUT OUT OUT OUT
28
OUT
50
OUT OUT OUT
54
55 48
R3P7
2
52
1K
48 28
50
IN
48
OUT OUT
52
1% CH
1.82K 402
1
IN
2
N: TI TIED ED TO V_ME V_MEMP MPOR ORT T FOR BETTER ROUTING
47
1
R2B16
BI
OUT
C21
2
56
IN
5% CH
R2A2
2
TRAY_STATUS EXT_PWR_ON_R
402
2
R2M5
2
AV_MODE1
FTP
TRAY_OPEN_R 47
CH
402
R2M3
2
FT2P10
2.2K
CH
1 1
FTP FTP
SMC_DBG_TXD
106
SB_RST_N
1
R2P6
STBY_CLK
R8N18
1
E MPTY
IN
V_3P3STBY
1
1
Y12
6
34
DDC_DATA_OUT DDC_CLK_OUT
BI BI
2 of SB VERSI VERSION ON
5% CH
V_3P3STBY 35
402
1
1UF 10%
5% CH
33
C2P51
1
5% CH
402
46
GPU_RST_DONE
IN
13
2
R3P6 10K 5% CH 1
46
402
54
IN IN IN
42
OUT
4
OUT
34
42 42
47
1
R2P15
2 1K
402
1
FTP
SB_MAIN_PWRGD
5% CH
FT2P5
OUT
34
2
J21 H22
GPU_RST_N CPU_PWRGD
A17 B17
SMC_PWM1 SMC_PWM0
OUT OUT OUT OUT
13
R2P10 10K 5%
4
CH
29 29
402
1
ENTEST1_N* ENTEST0_N*
X02047-012
V_1P8STBY
DBG_LED0 FT3P3 FT2R1 FT2P25 FT1U2
FTP FTP FTP FTP
1 1 1 1
N: DBG DBG_LE _LED0 D0 ST STUF UFFE FED D = ICS CL CLOC OCK K DBG_LED0 DBG_ LED0 EMP EMPTY TY = ANA CLOCK CLOCK
1
1
R2P12
R2P13
10K 5%
10K 5% CH
CH
2
402
2
402
ARGON_DATA ARGON_CLK
[PA [P AGE_TIT ITL LE=SB,
SMC]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 24 24
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
BI BI
48 48
PAGE 34/73
REV K7
SB,
FLASH U2C1
56 56 56
41
41
SPI_CLK SPI_MOSI SPI_SS_N
IN IN IN
FLSH_DATA<7..0>
BI
FLSH_WP_N
OUT
V_3P3STBY 2
41
IN
FT2P20 FT2P21
FTP F TP FTP FTP 45 45 45 45
1
AA5
Y2
7 6
AA2
5
Y3
4 3
AA3 AB3
2
Y4
1 0
AA4 AB4
5% CH
2.2K 402
FLSH_READY
FT2P22 FT2P23
R1P7
U3 Y5
Y1 V1
1 1
USBPORTA3_DP USBPORTA3_DN
1 1
USBPORTA2_DP USBPORTA2_DN
BI BI
GAMEPORT2_DP GAMEPORT2_DN
BI BI
GAMEPORT1_DP GAMEPORT1_DN
W18 Y18 AA17 AB17 W16 Y16 AA15 AB15 W12
+ USB + SPI 3
of of
SB VERSI VERSION ON SPI_CLK SPI_MOSI SPI_SS_N*
6
EMPTY 106
AB5
SPI_MISO
SPI_MISO_R
R1R1
2
1
SPI_MISO
W1
FLSH_CLE
FLSH_CE_N*
V3
FLSH_CE_N
FLSH_RE_N*
V2
FLSH_RE_N
FLSH_WE_N*
W3
FLSH_WE_N
FLSH_ALE
W2
FLSH_ALE
USBB_D4_DP USBB_D4_DN
Y10 W10
USBPORTB4_DP USBPORTB4_DN
USBA_D2_DP USBA_D2_DN
USBB_D3_DP USBB_D3_DN
Y8 W8
MEMPORT1_DP MEMPORT1_DN
BI BI
45
USBA_D1_DP USBA_D1_DN
USBB_D2_DP USBB_D2_DN
AB7 AA7
EXPPORT_DP EXPPORT_DN
BI BI
44
USBA_D0_DP USBA_D0_DN
USBB_D1_DP USBB_D1_DN
AB9 AA9
MEMPORT2_DP MEMPORT2_DN
BI BI
45
AB11 AA11
ARGONPORT_DP ARGONPORT_DN
BI BI
48
USB_RBIAS
USBB_D0_DP USBB_D0_DN
FLSH_DATA7 FLSH_DATA6 FLSH_DATA5 FLSH_DATA4 FLSH_DATA3 FLSH_DATA2 FLSH_DATA1 FLSH_DATA0
FLSH_CLE
FLSH_WP_N* FLSH_READY
USBA_D3_DP USBA_D3_DN
1 1
OUT
41
OUT
41
OUT
41
OUT
41
OUT
41
FTP F TP
56
OUT
5% CH
33
402
FT2P8 FT2P9 45
44
45
V_5P0STBY
48
X02047-012
1
S A I B R _ B S U _ B S
1
2
6.3V EMPTY 402
34
BI
2
DDC_DATA_OUT
R2N10
49.9 402
2
FB2N1
1
1
2
1K
FB 603
DDC_DATA_OUT_R
1% CH
1
0.2A 0.7DCR
C2N2
CH
402
2
5%
402
50V NPO 402
2
V_5P0STBY
2 M 2 D 2
R3N1
2
1
0
5%
402
EMPTY
BI
DDC_CLK_OUT
2
2.2K 402
R2N12
1
DDC_CLK_OUT_R
5% CH
2
2.2K 402 1
5%
R3N3
1
FLASH
+ USB USB + SP SPI]
43
DDC_CLK
BI
43
34
9 O S I 9 3 D V 2 A T B O S
3
Q2N2
1
MMBT2222 XSTR
5% CH
2
2
R2N11
DDC_CLK_OUT_E
3 M 2 D 2
1
49.9
50V X7R 402
1%
CH
1
[PAGE_TITLE=SB,
BI
DDC_CLK_OUT_B
C3N4 470PF
2
DDC_DATA
1
3 34
402
9 O S I 9 3 D V 2 A T B O S
3
62PF
CH
2
5%
CH
113 1%
10%
2.2K
5%
R2P14
.1UF
R2M8
2.2K
1
C2P40
1
R2M7
402
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 24 24
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 35/73
REV K7
SB,
39
19
IN
R1B9
MII_TX_CLK
19
IN
MII_TX_CLK_R
5% CH
33
402
39
U2C1
R1B10
MII_RX_CLK
MII_RX_CLK_R
402 39
19
39
19
39
19
39
19
39
19
39
19 19
39
19
39 19
28
4
of of
SB VERSI VERSION ON
5% CH
33
39
ETHERNET + AUDIO + SA SAT TA
B3 C3
MII_TX_CLK MII_RX_CLK
IN IN IN IN
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
D1 D2 D3 C1
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
IN IN
MII_RXDV MII_RXER
C2 B2
MII_RXDV MII_RXER
IN IN BI
MII_COL MII_CRS MII_MDIO
B5 A5
MII_COL MII_CRS MII_MDIO
E1
6
R1C3
MII_MDC_CLK_OUT_R
EMPTY
MII_MDC_CLK_OUT
C5 A4 B4 C4
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
MII_TXEN
A3
MII_TXEN
OUT OUT OUT OUT
19
39
19
39
19
A8
AUD_CLK
39
R2B11
C7 B8 A7 B7 C6
402
5% CH
402
I2S_MCLK_R
47
I2S_SD_R
R2B12
I2S_WS_R SPDIF_R
47
5% CH
402
47
47 47
HDD_RX_DP HDD_RX_DN
N4 P4
SATA1_RX_DP SATA1_RX_DN
SATA1_TX_DP SATA1_TX_DN
R2 P2
HDD_TX_DP HDD_TX_DN
IN IN
ODD_RX_DP ODD_RX_DN
L3 M3
SATA0_RX_DP SATA0_RX_DN
SATA0_TX_DP SATA0_TX_DN
N1 M1
ODD_TX_DP ODD_TX_DN
U2
SATA_RBIAS
SATA_RBIAS
1
1
R1C8
C1C9 10%
2
[PAG [P AGE_ E_T TIT ITLE LE= =SB SB,,
47
OUT OUT
47
I2S_SD I2S_WS 2
SPDIF
5% CH
OUT
40
OUT
40
OUT
40
OUT
40
OUT
43
47
47
X02047-012
374 1%
.1UF
6.3V X5R 402
402
OUT OUT
I2S_BCLK
5% CH
R2A10
1 47
IN IN
I2S_MCLK
5% CH
R2B13
I2S_BCLK_R
402
47
39
39
19
47
I2S_MCLK_OUT I2S_BCLK_OUT I2S_SD I2S_WS SPDIF
19
39
19
OUT
47
AUD_CLK
OUT
E2
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
R2B14
IN
MII_MDC_CLK_OUT
5% CH
33
402
106
CH
2
402
ETH ET HER ERN NET + AUDI AUDIO O + SA SAT TA]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 25 25
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 36/73
REV K7
SB,, SB
STAN ST ANDB DBY Y PO POWE WER R + DE DECO COUP UPLI LING NG U2C1
5
of of
SB VERSI VERSION ON
V_1P8STBY
FB2P4 2
V_AVDD_USB
FB 603
V_AVSS_USB
1
120
0.2A D CR CR
0 .5 .5
C2R5 10UF 10% 6.3V X5R 1206
1
C2P47
1
2.2UF 10%
1
ST2P3
2
C2P43
V_CMPAVDD18_USB
.1UF
V_CMPAVSS18_USB
6.3V X5R 402
V_VDD18_USB
10%
6.3V X5R 603
2
2
1
2
120
FB
0.2A D CR CR
603
1
1
C2P46 2.2UF
2
C2P42 .1UF
10%
ST2P2
VDD18_USB<9> VDD18_USB<8> VDD18_USB<7> VDD18_USB<6> VDD18_USB<5> VDD18_USB<4> VDD18_USB<3> VDD18_USB<2> VDD18_USB<1> VDD18_USB<0>
V9 V8 V7 Y6 W6 V6
2 1
CMPAVDD18_USB CMPAVSS18_USB
V13 V12 V10
FB2P3
10%
6.3V X5R 603
2
V_CMPAVSS33_USB
6.3V X5R 402
V_VDD33_USB
Y14 W14
CMPAVDD33_USB CMPAVSS33_USB
V17
VDD33_USB<3> VDD33_USB<2> VDD33_USB<1> VDD33_USB<0>
V16 V15 V14
SHORT
AVDD_USB AVSS_USB
Y13 W13
V11
SHORT
0 .5 .5
AB13 AA13
FB2R1
1
C2R3
1
2
120
FB
0.5A 0.2DCR
603
1
C2P45
10UF
10UF 20% 6.3V X5R 805
10%
2
6.3V X5R 1206
2
1
C2P41
1
.1UF
2
C2P2
1
.1UF
10%
6.3V X5R 402
2
C2P3 .1UF
10%
6.3V X5R 402
10%
2
6.3V X5R 402
V_3P3STBY
120
FB 603
0.2A D CR CR
0 .5 .5
1
10UF
C2P48
1
2.2UF
10%
6.3V X5R 1206
2 1
V_1P8STBY
EMPTY 106 VDD18_AUX<9> VDD18_AUX<8> VDD18_AUX<7> VDD18_AUX<6> VDD18_AUX<5> VDD18_AUX<4> VDD18_AUX<3> VDD18_AUX<2> VDD18_AUX<1> VDD18_AUX<0>
J18 H18 G18 J15 H15 R14 H14 R12 P12 R9
VDD33_AUX<14> VDD33_AUX<13> VDD33_AUX<12> VDD33_AUX<11> VDD33_AUX<10> VDD33_AUX<9> VDD33_AUX<8> VDD33_AUX<7> VDD33_AUX<6> VDD33_AUX<5> VDD33_AUX<4> VDD33_AUX<3> VDD33_AUX<2> VDD33_AUX<1> VDD33_AUX<0>
V19 D19 V18 F18 E18 E17 D17 E16 E15 W5 V5 U5 W4 V4 U4
VSS_USB<25> VSS_USB<24> VSS_USB<23> VSS_USB<22> VSS_USB<21> VSS_USB<20> VSS_USB<19> VSS_USB<18> VSS_USB<17> VSS_USB<16> VSS_USB<15> VSS_USB<14> VSS_USB<13> VSS_USB<12> VSS_USB<11> VSS_USB<10> VSS_USB<9> VSS_USB<8> VSS_USB<7> VSS_USB<6> VSS_USB<5> VSS_USB<4> VSS_USB<3> VSS_USB<2> VSS_USB<1> VSS_USB<0>
SB BALL BALLS S V1 V18 8 AN AND D V19 V19 AR ARE E IN TH THE E LOWER LOWE R RIGHT RIGHT HAND OF THE CHIP THEY THE Y HAVE BEEN ISOL ISOLATE ATED D FOR BETTER POWER ROUTING V_CMPAVDD33_USB
IN
37
V_3P3STBY
Y19 W19
AB18 AA18 Y17 W17
AB16 AA16 Y15 W15
AB14 AA14 AB12 AA12
V_1P8STBY
Y11 W11
1
AB10 AA10
C2P38 .1UF 10%
Y9 W9 AB8 AA8 Y7 W7 AB6 AA6
2
6.3V X5R 402
C2P37 .1UF 10% 6.3V X5R 402
X02047-012
C2P23 .1UF 10%
6.3V X5R 402
C2P24 .1UF 10%
6.3V X5R 402
V_3P3STBY
2
1
C2R6
V_CMPAVDD33_USB
OUT
37
FB2P5
6
ST2P4
2
C2P44
1
.1UF
10%
10%
6.3V X5R 603
6.3V X5R 402
2
C2P6
C2N1
.1UF
2
.1UF
C2P5 .1UF
10%
10%
10%
6.3V X5R 402
6.3V X5R 402
6.3V X5R 402
SHORT
FB2P1 1
C2P8
0 .5 .5
120 0.2A D CR CR
10UF 10% 6.3V X5R 1206
[PAG [P AGE_ E_TI TITL TLE= E=SB SB,,
2
FB 603
1
C2P34
1
2.2UF 6.3V X5R 603
C2P35 .1UF
10%
2
10%
2
6.3V X5R 402
STAN ST ANDB DBY Y PO POWE WER R + DECOU DECOUPL PLIN ING] G]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 26 26
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 37/73
REV K7
N: N:
123.8 123.8 OHM OH M TE TERM RMIN INAT ATION ION REQ REQUIR UIRED ED FO FOR R ICS 100 OHM TER TERMIN MINATIO ATION N REQU REQUIRED IRED FOR BROADCO BROADCOM M ENET_RX_DP
BI
44
19
1 44
19
39
R1A4
V_ENET
IN
61.9 1%
CH
1
R1B7
2
CH
1
1K 5%
19
46
ENET_CLK
IN
2
TP
1
2
R1C1 10K
5% CH
402
1
19
44
19
36
39
MII_MDC_CLK_OUT
IN
2
V_ENET
IN
R1B11
1.5K 402 36
19
ENET_REF_CLK_OUT
ENET_RST_N
IN
1
1% CH
36
19
36
19
36
19
36
19
36
19
36
19
36
19
36
19
19
36
19
36
19
36
19
36
19
36
19
36
19
OUT OUT OUT OUT
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
28 29 30
MII_TX_CLK
37
MII_RXDV MII_RXER
10K 5%
31
MII_TXEN
38
TXCLK TXEN
IN IN IN IN
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
42 41 40 39
TXD<3> TXD<2> TXD<1> TXD<0>
MII_COL MII_CRS
R1N4
44
19
39
IN
V_ENET
27 26
MDC MDIO
43 44
COL CRS
10
AMDIX_EN
20 19
EMPTY
TP_AP TP_AN
12 13
ENET_RX_DN
BI
19
44
TP_BP TP_BN
16 15
ENET_TX_DP
BI
19
44
CH
2
402
2
P4RD P3TD
8
P2LI
4
P1CL P0AC
1
VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>
36 25 21 17
R1A1 61.9 1%
L C 1 P _ T E N E
D R 4 P _ T E N E
D T 3 P _ T E N E
1
11
2 10K 5%
2
R1M2 ENET_LINK_N
1
CH 2
1
402
5% 1
ENET_TX_DP_R
CH
10K
2
402
5%
44
19
CH
1K 5%
CH
402
2
R1B5
10K 5%
2
0
OUT
1
R1N5
402
402
R1B4
2
R1N6
5
CH
ETHERNET
CH
1
R1N7
10/100 10/1 00 PIN PI N INDICAT INDI CATION ION
402
44
OUT
1
CH
2
402
R1A2 61.9
EMPTY FOR BROADCOM STUFF STU FF FOR ICS
ENET_10_100_OUT
603 ENET_TX_DN_R
AMDIX_EN AMDIX_E N HAS INTERNA ERNAL L PULL PULLUP UP AUTO MDIX MDIX IS ON BY DEFAUL DEFAULT T
CH
402
1
DB1N3
2K 1%
1
CH
ENET_P2LI_R
X800188-002
R1N3
1%
402
1%
44
3
9
2
CH 1
19
OUT
6
10/100
1
1.58K
1
61.9
ENET_ACT_N
TP
R1N2
EMPTY 402
R1A3
24 22 18
100TCSR 10TCSR
ENET_10BIAS
603 ENET_RX_DN_R
7
10K
ENET_100BIAS
2
CH
330 1%
48 45 33 14
5%
1% CH
9.53K 402
1
5%
1
5%
2
VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>
RXD<3> RXD<2> RXD<1> RXD<0>
IN
100 402
R1N1
RXCLK RXDV RXER
STUFF FOR BROADCOM STUFF BROADCOM EMPTY EMP TY FOR ICS R1B13
2
ENET_AMDIX_EN
2
RESET_N*
OUT OUT OUT
OUT OUT
2
23 34 32 35
OUT
36
REF_IN REF_OUT
MII_RX_CLK
MII_MDIO
BI
47 46
0
1
R1B6
DB1N4
33
R1M1 44
OUT
1
ICS1893BF
19
ENET_RX_DP_R
402 ENET_POAC_R
IC
U1B2
402
1%
CH 2
IS FO FOR R OUT OUTPU PUT T OF CONNEC CONNECTIO TION N SPEED
402
ENET_TX_DN
BI
19
44
ADDRESS="00001"
V_3P3 FB1B1 1
60
0.5A 1
2
0.1DCR 603
C1A5
100UF 20% 16V
2 ELEC RDL
[PAG [P AGE_ E_TI TITL TLE E=S =SB B
OUT, OU T,
V_ENET 2
ETHERNE ETHER NET] T]
1
C1B1 10UF 20% 6.3V X5R 805
C1N1 .1UF 10%
6.3V X5R 402
C1N4 .1UF 10%
6.3V X5R 402
C1N5 .1UF 10%
6.3V X5R 402
C1N3 .1UF 10% 6.3V X5R 402
C1N9 .1UF 10% 6.3V X5R 402
C1N11 .1UF 10%
6.3V X5R 402
C1N2 .1UF
10%
6.3V X5R 402
OUT
19
39
44
C1N10 .1UF 10%
6.3V X5R 402
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 28 28
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 39/73
REV K7
V_12P0 R2B3
2
1
FTP
V_3P3 R2B1
1 0
1
R2B6
1 0
603
FTP
FT2N1
4.7UF 10% 16V X5R 1206
AUD_VDD
5% CH
1
C2B11 4.7UF 10%
2
C2B5
2
1
FB2A2 2
1
AUD_CLAMP_R
1K
5% CH
0.7DCR 603
0.2A
X5R 1206 2
C2B7 0.1UF 10% 25V X7R 603
1
R2B5 10K
5% CH
.1UF
EG2B2
1
10%
6.3V X5R 805
402
AUD_AC_R
16V
AUD_VAA
C2A7
2
1K
2
10UF 20%
2
5% CH
603
C2B10 1
FT2M1
PGB0010603
6.3V X5R 402
1
402
2
C2B3 470PF 5%
X801161-001
603 IC
U2B1
50V X7R 402
1
EMPTY
XDAC 2
14 36
IN IN IN IN
36
FT2N2 33
IN
FTP
36
1
36
I2S_MCLK I2S_BCLK I2S_SD I2S_WS
2 5 12 11
AUD_DCAP
1
R2N3 1K 5% CH
2
402
C2B1 10UF 10% 6.3V X5R 1206
C2B6
SD WS
VOUTR VOUTL
6
AUD_VOUTR
10
AUD_VOUTL
NC PDN
AVREF
8
DVREF
1
AUD_R_OUT
AVDD
9
MCLK BCLK
3
AUD_RST_N
AUDIO
DVDD
13 4
AGND
C2 B4 .1UF 10% 6.3V X5R 402
.1UF
X02238-002
C2 B8 10UF 10% 6.3V X5R 1206
1
EG2B1
PGB0010603
R2B4
603
10K
5%
EMPTY
2
CH 1
C2B2
402
470PF 5%
50V X7R 402
1
1
C2B9
10UF
16V
2
AUD_AC_L
20%
R2B2
2
X5R 1206
1K
402
1
1
FB2A1 1K
2
3
AUD_CLAMP_C
Q2N1 1
V_3P3STBY 1
4.7K 402
MMBT3906 XSTR
R2M12 5% CH
2
R2N2
2 1K
402
1
AUD_CLAMP_B2
0.7DCR 603
0.2A
CR2N1
AUD_CLAMP
IN
2
1
AUD_CLAMP_L
5% CH
MBT3904 34
43
2
X801161-001
2
FTP
43
OUT
7
DGND
FT2P1
OUT
AUD_ACAP
10%
6.3V X5R 402
AUD_L_OUT
3
6
4
1
5
2
5% CH
AUD_CLAMP_B3
R2N1
2 1K
402
XSTR
1
5% CH
AUD_CLAMP_B1
1
R2M13 1K 5% CH 2
[PA [P AGE_TI TITL TLE E=SB
OUT,
AUDIO AUD IO]]
402
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 29 29
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 40/73
REV K7
N: N:
FLSH_DATA0 1 A T A 0 D _ H S 1 L F
0
RETAIL=16M RETAIL= 16MB B XDK=64M XDK= 64MB B
1
8MB
16MB
32MB
64MB
V_3P3STBY
1
1
R2D7 FT1R3 FT1R4 FT1R5 FT2R3 FT2R4 FT2R5 FT2R6 FT2R7 35
IN
FTP FTP FTP FTP FTP FTP FTP FTP
FLSH_DATA<7..0>
5% CH 2
402
2
EMPTY 402
1
R1E2
10K 5%
10K
1 1 1 1 1 1 1 1
1
R2D6
10K 5%
10UF
2
402
1
C2E5 .1UF
10%
CH
2
1
C2E6
10%
6.3V X5R 1206
2
6.3V X5R 402
2
C2R11 .1UF 10% 6.3V X5R 402
N:
STUF ST UFFE FED D AT CONFIG CONFIG LEV LEVEL EL
N:
UPDAT UPD ATE E TO RECENT RECENT PART NO#
IC
U2E1 NAND FLASH RDY
37
1
FTP
FT1T1
12
44 43 42
7
6 5 4
41 32 31
3 2
30 29
1
0 35 35
1
1
1
1
1
1
R2D5
R2D4
R2D3
R2D1
R1D4
EMPTY 402
CH
CH
CH
CH
CH
402
402
402
402
402
10K 5%
2
1
R2D8
10K 5%
2
10K 5%
2
10K 5%
2
10K 5%
2
10K 5%
2
1
R1D2
35
5%
5%
35
CH
CH
402
402
10K
2
35
R1D3
10K
2
35
IN IN IN IN IN IN
FLSH_CE_N FLSH_RE_N FLSH_WE_N FLSH_WP_N FLSH_ALE FLSH_CLE
9 8
18 19 17 16 6 36 13
NC<27> NC<26> NC<25> NC<24> NC<23> NC<22> NC<21> NC<20> NC<19> NC<18> NC<17> NC<16> NC<15> NC<14> NC<13> NC<12> NC<11> NC<10> NC<9> NC<8> NC<7> NC<6> NC<5> NC<4> NC<3> NC<2> NC<1> NC<0>
VCC1 VCC0 DATA<7> DATA<6> DATA<5> DATA<4> DATA<3> DATA<2> DATA<1> DATA<0> CE_N* RE_N* WE_N* WP_N* ALE CLE VSS/NC VSS1 VSS0
X803471-003
[PA [P AGE_TI TITL TLE E=SB
OUT,
FLASH FLAS H]
FLSH_READY
7
38
48 47 46 45 40 39 35 34 33 28 27 26 25 24 23 22 21 20
FLSH_NC38
R2D2
2
OUT
35
1
0
5%
402
EMPTY
15 14 11 10 5 4 3
2 1
TSOP
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 30 30
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 41/73
REV K7
V_3P3STBY BINDING BIND ING
V_12P0
BUTTON BUT TON
FAN CO CONT NTRO ROL L 1
1
R5V3
SWITCH
TH
3
CH 2 1 2
4 3
R5V2
1 0K
1
BINDSW_N
OUT
5% CH
402
29
34
IN
FAN1_OUT
2
10%
1
50V X7R 402
2
V_FAN1
R3A1 249
R1G4
1
1%
10K
C3M1 1UF 10%
CH
CH
1 2
D3A1 1N4148 SOT23 DIO
Q _ 1 N A F
C4N25
5%
4 3
3
1
E _ 1
2700PF 1
2
4
MMBT2222 XSTR 2
V_3P3STBY
SW1G1 THR
2
Q3A1
1
X02246-002
TH
BCP51 XSTR
3
BINDSW_N_R
SWITCH
Q3M1
1
FAN1_Q1_C
402 2
ODD EJECT EJECT BUT BUTTON TON
1
1% CH
5.11K 402
10K
5%
SW5G1 THR
R3A8
2
R _ K B D F _ 1 N A F
402
R1G3
2
EJECTSW_N_R
10K
1
EJECTSW_N
5% CH
402
OUT
34
47
50V X7R 603
2 30K 1%
CH
R4P2
402
2
1
FAN1_FDBK
1% CH
5.11K 402
V_3P3STBY
1
R3A7
2
X02246-002
402
1
29
OUT
J3A1
1
2X2HDR
R3A2 TILT TI LT
11K 1%
1
SWIT SW ITCH CH
R2G2
SM
2
CH
10K
5%
3
HDR
402
2
1
4
CH
SW2G1 SM
2 1 2
4 3
402
R2G3
2
TILTSW_N_R
10K
X800550-001
1
TILTSW_N
OUT
5% CH
402
V_12P0
FAN FA N CO CONT NTRO ROL L 2
34
R3B16
2
5.11K 402
1
1% CH
FAN2_Q1_C
3
Q3A2
1
TILT TI LT
SWIT SW ITCH CH
29
SM
IN
FAN2_OUT
2
Q3M4
1
3
BCP51 XSTR
3
4
MMBT2222 XSTR
1
D3B1 1N4148 SOT23 DIO
2
SW2G2
E _ 1 Q _ 2 N A F
SM 1 2
4 3
2
C4N20
R3M4
50V X7R 402
249
V_IR 1
C2V1 10%
6.3V X5R 805
IR
VCC
DATA GND ME2 ME1
1% CH
2
C2V2
R2N7 10K 5%
10%
2
6.3V X5R 402 1
3 1 2 5 4
CH
2
2
CH
5.11K 402
402
50V X7R 603
30K 1%
402
R _ K B D F _ 2 N A F
2
.1UF
4.7UF IC
U1G1
49.9 402
R2V1
R3A5
CH
1
2
1
1%
V_3P3STBY 1
C3A7 1UF 10%
10%
1
1
2
2700PF
X800550-001
V_FAN2
R4N8
402
FAN2_FDBK
OUT
29
1
1% CH 1
IR_DATA
R3M5 OUT
11K 1%
34
CH
2
402
X803473-002
[PAG [P AGE_ E_TI TITL TLE= E=CO CONN NN,,
FAN FA N + IN INFR FRAR ARED ED
+ SW SWIT ITCH CHES ES]]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 30 30
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 42/73
REV K7
AARON: AAR ON:
THIS TH IS
PAGE PAG E HAS TOO TOO MUCH MUCH ON IT. IT.
L3A3 29
2
1
VID_DACA_DP
IN
S 3 9 2 9 T V O I O A D S B
.27UH 0.45A
1
R3A4
1
62PF
402
5%
50V NPO 402
2
2
50V NPO 402
36
IN
C2A6
S 3 9 2 9 T V O I O A D S B
5%
L3A2 2
1
VID_DACB_DP S 3 9 2 9 T V O I O A D S B
75 1%
3 A 3 D
V_3P3
C3A5
1
C2M5
C2A1
10%
5%
470PF
6.3V X5R 805
50V X7R 402
50V NPO 402
T V O I O A D S B
2
1
VID_DACC_DP
.27UH 0.45A
1 75 1%
2 A 3 D
V_3P3 2
VID_DACC_OUT
C3A4
2
43
V_12P0
IN
VID_DACA_OUT
4 2
IN
VID_DACB_OUT
3 1
IN
VID_DACC_OUT
8 6
C3A1 75PF
5%
402
43
OUT
43
1
62PF
CH 2
1
1
1
5%
50V NPO 402
2
H %
C 8 1 A 2 R
50V NPO 402
K 2 2 0 8 . 4 1
2
33
1
WSS_CNTL1
IN
R2A6
43
IN
VID_DACD_OUT
43
IN
VID_HSYNC_OUT
43
2
1% CH
5.36K 402
WSS_CNTL0
IN
1
VID_DACD_DP
T V O I O A D S B
.27UH 0.45A
1
R2A3
3
2 A 2 D
V_3P3 2
75 1%
NA
2
2
1
R2A7
IN
2
VID_DACD_OUT
OUT
40
1
WSS_CNTL_E
43
62PF
C2A2
50V NPO 402
5%
29
IN
49.9 402
V_3P3STBY
3 M 3 D 2
R3M3
2
1
OUT
33
43
SCART_RGB
IN
2
H % 1 C
4 A 2 R
N/A
N/A
PB
PB
B
D
CVBS(COMP)
CVBS(COMP)
CVBS
N/A
CVBS
B
CVBS
402
1
5% CH
C2A8 75PF
5%
1
50V NPO 402
49.9 402 1
9 O S I 9 3 D V 2 A T B O S
3
V_3P3STBY
2 M 3 D 2
AVIP AV IP]]
R3M2 1% CH
2
VID_HSYNC_OUT
1
OUT
43
0 1 M 2 R 2
H % 5 C
K 2 0 0 1 4
402
AV_MODE2 AV_MODE1 AV_MODE0
35
34
34
35
OUT OUT OUT
34
43
34
43
34
43
MTGB<8-1> MTGA<8-1>
TH
56
43
34
43
34
43
34
43
IN IN IN IN
EXT_PWR_ON_N AV_MODE2 AV_MODE1 AV_MODE0
2
1
1
C2M4 0.01UF 10% 16V X7R 402
R2M4
CH
CH
CH
402
402
402
C2A3
10K 5%
2
50V X7R 402
1
1
MICROSOFT 2 00 00 5
CONFIDENTIAL
C2M3
2
1
C2M2
10K 5% CH 2
1
470PF
5%
50V X7R 402
R2M2
10K 5%
470PF 2
LAYOUT: LAYO UT:PLAC PLACE E
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 31 31
1
R2M6
5%
2
1
R2A1
470PF
5% CH
2
28 24 20
56
OUT BI BI
WSS_CNTL SCART_RGB
2
1
DDC_CLK DDC_DATA
34 33 32 31
10K 5%
3
R2M9
23
18
SHIELD<3> SHIELD<2> SHIELD<1> SHIELD<0>
1
MMBT3906 XSTR
1
EXT_PWR_ON_N
V_3P3STBY
34
33
1
VID_HSYNC_OUT_R
SPDIF
30 21
26 22
GND<2> GND<1> GND<0>
X800055-001
Q2M1
SCART_RGB_OUT_R
IN
25
T U O _ B G R _ T R A C S
2
5% CH
VID_VSYNC_OUT VID_VSYNC_RET
AUD_L_OUT AUD_L_RET
2
1
12 10
17 19
402
AV_MODE2 AV_MODE1 AV_MODE0
VID_HSYNC_OUT VID_HSYNC_RET
16 14
WSS_CNTL_OUT
DDC_CLK DDC_DATA
VID_DACD_OUT VID_DACD_RET
1
% H 5 C
SCART_RGB_R
EXT_PWR_ON VID_DACC_OUT VID_DACC_RET
AUD_L_OUT
R2A5
CONN CONNECTO ECTOR R
VID_DACB_OUT VID_DACB_RET
IN
2 2 K 1 0 0 0 0 3 4 1 1 4
R2M11
10K
1% CH
29
[PAG [P AGE_ E_TI TITL TLE= E=[C [CO ONN,
C
AUD_R_OUT AUD _R_RE T
1K
50V NPO 402
VID_VSYNC_OUT
9 O S I 9 3 D V 2 A T B O S
3
R
15 13
V_3P3
1
G
R
AUD_R_OUT
2
2
9 A 2 R
75PF
1
XSTR WSS_CNTL_OUT_R
2
2
C2A5
2
4
IND
1
VID_VSYNC_OUT_R
G
PR
IN
2
1% CH
1210
5%
CH
402
1
4.75K 402
L2A1
S 3 9 2 9
Y
PR
VID_DACA_OUT VID_DACA_RET
7 5
VID_VSYNC_OUT
6
3
MBT3904 5
33
IN
Y
C(CHROMA)
XENON XENO N AVIP V_AVIP V_AVIP_RET
11 9
WSS_CNTL_B
CR2A1
40
29
Y(LUMA)
N/A
J2A1
IND 1210
NA
R3A6
N/A
B
C3A2
27
3
A
75PF
2
43
S 3 9 2 9
VGA
5%
50V NPO 402
L3A1 IN
SCART
1
29
29
HDTV
1 A 2 D 2
5%
2
SDTV
V_3P3 1
62PF
CH
402
2 2
1
ADVANCED
3
43
OUT
1210
NA
R3A3
VID_DACB_OUT
50V NPO 402
IND
.27UH 0.45A
1 3
1
2
22PF
IN
THRMSTR 1206
4.7UF
1
STANDARD
V_AVIP
2
SPDIF
2
29
RT2M1
1.1A 0.21DCR
C3A3 75PF
5%
1
DAC
43
1
C3A6
CH 2
2
1
75 1%
4 A 3 D
V_3P3
OUT
IND 1210
NA
3
V_5P0
VID_DACA_OUT
50V X7R 402
C2M1 470PF
5%
2
402
5%
2
50V X7R 402
CLOSE CLOS E TO CONNECTOR CONNECTOR EMI CA EMI CAPS PS PROJECT NAME XENON_RETAIL
PAGE 43/73
REV K7
43
V_5P0DUAL RT1B1 44
2
V_EXPPORT
IN
D1A2
V_EXPPORT
1
1.1A 0.21DCR
THRMSTR 1206
1
10V
603 L1B1 35
35
BI
EXPPORT_DN
1
BI
EXPPORT_DP
4
2 ELEC RDL
3
5% CH
NA SM
CMCHOKE
BAV99 SOT23S DIO
2
470PF 5%
1
50V X7R 402
1
1
FTP
FT1N2
C1M2 4.7UF 10% 6.3V X5R 805
EXPPORT_DN_CM
3
EXPPORT_DP_CM
D1A1
X801560-001
2
1 3
R1B1
EG1A2 PGB0010603 X801161-001 EMPTY 603
1
1
5% CH
0
C1A3
2
1
EMPTY
603
2
220UF 20%
2
R1B2 0
C2A4
BAV99 SOT23S DIO
2
EG1A1 PGB0010603 X801161-001 EMPTY 603
2
J1A1 XENON XEN ON RJ45/ RJ45/USB USB
48
IN
ARGON_NTX D1B1
44
IN
V_EXPPORT
2
2
5%
1
50V X7R 402
39 39
1
19
39
BAV99 SOT23S DIO 19
39
IN
VBUS
15
GND
16
V_ENET
R1M3
1
2
0
5%
4 02 02
E MP MP TY TY
R1A5
1
2
0
5%
402
EMPTY
IN IN
OMNI
IN IN
ENET_P2LI_R ENET_LINK_N
1 2
ENET_POAC_R
3
ENET_ACT_N
4
39
19
39
19
IN
ENET_TX_DP
11
ENET_TX_CT
10
39
19
IN
ENET_TX_DN
7
39
19
IN
ENET_RX_DP
9
ENET_RX_CT
6
IN
ENET_RX_DN
5
39
19
C1M1
C1A2
10%
10%
.1UF
6.3V X5R 402
.1UF
6.3V X5R 402
LED_LEFT_A LED_LEFT_C LED_RIGHT_A LED_RIGHT_C XFMER2_P XFMER2_C XFMER2_N XFMER1_P XFMER1_C XFMER1_N
8
CAP
20 19 18 17
EMI4 EMI3 EMI2 EMI1
21
CONN COMBO COM BO
DD+
C1A4 470PF
3
12 13 14
ME1
X806148-001
[PAG [P AGE_ E_TI TITL TLE= E=C CONN,
ETH ET HER ERN NET ET]]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 32 32
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 44/73
REV K7
V_MEMPORT1
RT2G1
RT8G1 1
1.1A 0.21DCR
V_GAMEPORT2
THRMSTR 2 1206
1
C8V14 10%
1
2
C9G2 220UF 20%
4.7UF
1
50V X7R 402
BI
BI
35
GAMEPORT2_DN GAMEPORT2_DP
35
1
EG9G1 PGB0010603 X801161-001 603 EMPTY
2
D9G1
X801560-001
6.3V X5R 805
1
1
BI
MEMPORT2_DP
4
CMCHOKE
2
MEMPORT2_DN_CM
2
V_5P0DUAL
1
1
2
C9G3
VBUS
6 7
DD+
C9G4
220UF 20%
GND
5 GAMEPORT1_DP_CM
V_GAMEPORT1
4.7UF 10% 6.3V X5R 805
2
5% CH
EG4G1 PGB0010603 X801161-001 603 DIO
J3G1
8
GND
9
10
EMI1 EMI2
11
ME1
12
ME2
470PF
1
2
C2G2 220UF 20%
1
50V X7R 402
4.7UF 10% 6.3V X5R 805
1
35
BI
MEMPORT1_DN
1
35
BI
MEMPORT1_DP
4
EMPTY
CMCHOKE
GND GND VBUS DD+
GND EMI4 EMI3 EMI2 EMI1
15 16 17 18
NA SM L2G1
DD+
14 13 12 11
5% CH
603
GND VBUS
6 7 8 9 10
C2G3
5%
10V
0
2
470PF
2 ELEC RDL
R3G4
C3V5
2
MEMPORT1_DN_CM
3
MEMPORT1_DP_CM
ME4 ME3 ME2 ME1 MTGA<8-1> MTGB<8-1> MTGC<8-1>
5%
10V
50V X7R 402
1
2 ELEC RDL
X800245-003
X800059-001
X801560-001 1
V_5P0DUAL R2G5
D9V2
0
603
1 3
5% CH 1
NA SM L9V1 35
35
BI
BI
GAMEPORT1_DN
4
BAV99 SOT23S DIO
EMPTY
CMCHOKE
3
2
1
X801560-001
D9V1 2
EG9V1 PGB0010603 X801161-001 603 EMPTY
R9V1 0
[PAG [P AGE E_TI TITL TLE E=CONN,
5% CH
1
EG3G1 PGB0010603 X 80 80 11 11 61 61 -0 01 603 DIO
2
3
1
C1U2 1.0UF
2
2
IC
U1F2
1
2
TH
EG2G1 PGB0010603 X 80 80 11 11 61 61 -0 01 01 603 DIO
V_MPORT
V_5P0
3
603
603
EG9V2 PGB0010603 X801161-001 603 EMPTY
2
1
GAMEPORT1_DP
5% CH
0
2
R9V2
CONN
XENON MU 1 2 3 4 5
2
DD+
4
GAMEPORT1_DN_CM
RT8G2
C9V3
603
1
EG4G2 PGB0010603 X801161-001 603 DIO
VBUS
3
GAMEPORT2_DP_CM
BAV99 SOT23S DIO
THRMSTR 1206 2
MEMPORT2_DP_CM
1
R4G4
1 2
GAMEPORT2_DN_CM
1
1
3
XENON GAME CONN
5% CH
1.1A 0.21DCR
MEMPORT2_DN
TH CONN
J9G1
3
2
BI
0
2
603
10%
50V X7R 402
EMPTY
X801560-001
BAV99 SOT23S DIO
2
0
4.7UF
5%
NA SM 35
3
1
1
C5G6
470PF 2
5% CH
L4G1
1
NA SM EMPTY
R9G1
2
C4V6
3
CMCHOKE
4
0
603
2
5% CH
L9G1 35
1
C5G4
R4G5
EG9G2 PGB0010603 X801161-001 603 EMPTY
2
D9G2
603
1
220UF 20% 10V ELEC 2 RDL
5%
ELEC 2 RDL
2
FB 603
C9G1
V_5P0DUAL
R9G2
V_MEMPORT2
1
120 0.5A 0.2DCR
THRMSTR 1206
470PF
10V
6.3V X5R 805
2
1
1.1A 0.21DCR
1
0
FB5G1
2
2
1
OUT
V_MPORT
V_5P0DUAL
10% 16V
NCP1117 IN
OUT
ADJUST/GND
2
1
1
X800499-001 2
X7R 805
C1F6 0.1UF 10% 25V X7R 603
1
FTP
FT1V1
C1F4
100UF 20% 16V
2 ELEC RDL
1
BAV99 SOT23S DIO
MEM EMO ORY PO PORTS + GAME POR PORTS TS]]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9: 9: 27 27 :3 :3 3
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 45/73
REV K7
V_3P3STBY
V_5P0DUAL
FB3P2 2
1
60
V_3P3STBY
1
1
R1G2
20 1%
CH
2
1
C3N9 .1UF 10% 6.3V X5R 402
402
2
2
20 1%
CH
2
C3P6 4.7UF
.1UF 10% 6.3V X5R 402
1
2 C _ R E D E E L B
2
C3P4
C3P8
.1UF
10%
1 C _ R E D E E L B
.1UF 10% 6.3V X5R 402
10%
6.3V X5R 805
1
6.3V X5R 402
1
2
C3P2 .1UF 10% 6.3V X5R 402
1
2
1
.1UF 10% 6.3V X5R 402
MMBT2222 XSTR
34
10K
1
2
ANA_BCKUP_X2
402
402
V_1P8STBY
2
2
C3B13
22 23
C3B14 22PF
5%
C3N3
17 5
5%
50V NPO 402
50V NPO 402
1
1
V_3P3STBY
2 3 34
ANA_CLK_OE
IN
R3P3
2 1K
402
1
5% CH
1
1
8
ANA_BCKUP_OE
5% CH
28
56
56
34
34
28
27
SMB_CLK SMB_DATA
IN IN
26 20
ANA_BCKUP_RSET
21
25
12 9 4
2
R3P2
VCC3_5 VCC3_4 VCC3_3 VCC3_2 VCC3_1
R3C16
R3C7 28
X1_BCKUP
15 16 18 19
GPU_CLK_DP_R GPU_CLK_DN_R
14 13
PCIEX_CLK_DP_R PCIEX_CLK_DN_R
BCKUP_OE SMB_CLK SMB_DATA
11 10
SATA_CLK_DP_R SATA_CLK_DN_R
BCKUP_RSET
5% CH
33
402
BCKUP_F48M
2
R3C15 1% CH
49.9 402
R3C10
GPU_CLK_DP_R GPU_CLK_DN_R
1
5% CH
33
402
R3C9
2
1% CH
49.9 402
PCIEX_CLK_DP_R
PCIEX_CLK_DP PCIEX_CLK_DN
PCIEX_CLK_DN_R
R3C6
1
SATA_CLK_DP_R
2
1
R3C5
5% CH
6 7
402
24
1
R3C4
2
5% CH
33
1
R3C3
402
402
ANA_BCKUP_F25MA
1
220UF 20%
10K
2
10K 402
VREG_V5P0_SEL_C
R1R5
1
3 4
VREG_V5P0_SEL_PGATE
FT1R1
FTP
1
4.7K 402
R1D6
2
.1UF
1
VREG_V5P0_SEL_B2
XSTR
5 8 7 6
1
FTP
2
OUT 1
G1 S1 ANA_BCKUP_F48M
R3B7
1 33
X801132-001
CLOCK
+ V_5P0
DUAL]
33
FT2N4
402
2
50V EMPTY 402
STBY_CLK
5% CH
OUT 1
C3C4
1
FTP
34
FT2R2
10PF
5%
2
VREG_5P0_SEL
VREG_5P0_SEL NGATE/PGATE
V_5P0DUAL
HIGH
LOW
V_5P0STBY
LO W
HI G H
V_5P0
CH
[PA [P AGE_TIT ITL LE=[B [BA ACKUP
FTP
10PF
5%
402
1
C3C3 5%
2
4.7K
1
50V EMPTY 402
SATA_CLK_REF
5% CH
FT1R2
2
R1D5
R3C27
1 33
D<3> D<2> D<1> D<0> 2 1
6.3V X5R 402
ANA_BCKUP_F25MB
402
C1R3 10%
VREG_V5P0_SEL_B1
5% CH
39
C3B4
IC
SI4501DY
V_5P0 2
19
33
FT1P2 FT1P1
10PF
S2 G2
VREG_V5P0_SEL_NGATE
5% CH
CR1D1
1
OUT 1
FTP FTP
5%
402
MBT3904
VREG_V5P0_SEL
1% CH
2
U1R1
CH
402 2
IN
1 1
ENET_CLK
33
OUT OUT
2
10K
5%
CH
34
49.9 402
ELEC 2 RDL
R1R3
5%
2
2
R3C1
5% CH
402
V_5P0DUAL
1
33
FT3P2 FT3P1
2
10V
1
R1R2
R3B8
1 33
C1D11
2
5% CH
33
V_12P0
1
R3C2
1
FTP FTP
1% CH
49.9 402
SATA_CLK_DP SATA_CLK_DN
TSSOP28
V_5P0STBY
V_5P0STBY
1 1
1% CH
49.9 402
33
OUT OUT
2
SATA_CLK_DN_R
CH 1
13
CPU_CLK_DN_R
402
X803897-001
13
2
475 1%
4
CPU_CLK_DP_R
33
BCKUP_F25MA BCKUP_F25MB
GND_5 GND_4 GND_3 GND_2 GND_1
1
4
1% CH
49.9 402
GPU_CLK_DP OUT GPU_CLK_DN OUT
CLK GEN
CPU_CLK_DP_R CPU_CLK_DN_R
BCKUP_X1 BCKUP_X2
OUT OUT
2
1% CH
49.9 402
5% CH
33
402
R3C17
IC
BACKUP BACK UP
22PF 1
28
2
1% CH
2 U3B4
10%
R3C18
49.9 402
R3C8 NOTE: SWAP POLAR NOTE: POLARITY ITY FOR ROUTIN ROUTING G
XTAL
.1UF
1
5% CH
28
OUT
CPU_CLK_DP CPU_CLK_DN 33
SM
6.3V X5R 402
R3C12
ANA_BCKUP_X1
2
1
1
ANA_XTAL_IN
R3C11
Y3B1 27MHZ
2
.1UF 10% 6.3V X5R 402
5% CH
1M
MMBT2222 XSTR
5% CH
402
R3B4
1
Q1V1
1
BLEEDER_B
2
1
5% CH
33
V_3P3STBY
3
R1V1
2
.1UF 10% 6.3V X5R 402
R3B5
2
402
C3P5
V_1P8STBY
Q1G2 2
SMC_RST_N
1
1
C3P7
33
3
IN
2
C3P1
402
1
56 28
STITCH STITC H ANA_XTAL_BACKUP
2
C3N8
1
STBY_CLK STBY_CL K
V_CLKGEN
0.1DCR 603
0.5A
1206
2
ONE ON E CAP PER POWER POWER PIN
2
1
60
CH
1206
2
N:
FB3P1
R1V2
R1G1
1K 5%
0.1DCR 603 EMPTY
0.5A
V_3P3
1
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 34 34
2 00 00 5
MICROSOFT CONFIDENTIAL
50V EMPTY 402
PROJECT NAME XENON_RETAIL
PAGE 46/73
REV K7
V_5P0 D1E4 2 3 36
HDD_TX_DP
IN
C1E4
1
2
1
0.01UF
10%
16V X7R 402
BAV99 SOT23S DIO
HDD_TX_DP_C
HDD SA SATA TA AN AND D PO POWE WER R
HDD_TX_DN_C
HDD_TX_DN
IN
36
D1E3
C1E3
1
0.01UF
2
J1E1 1 2 3 4 5 6 7
3
16V X7R 402
1
BAV99 SOT23S DIO
8 9 10 11 12 13 14
V_5P0 D1E2 2
1
1
EG1E4 X 801161-001 PGB0010603 603 EMPTY
3
HDD_RX_DN
OUT
36
1
C1E2
2
1
0.01UF
16V
10% BAV99 SOT23S DIO
X7R 402 HDD_RX_DN_C
2
1
EG1E3 PGB0010603 X801161-001 603 EMPTY
1
EG1E2 PGB0010603 X 80 80 11 11 61 61 -0 -0 01 01 603 EMPTY
2
EG1E1 PGB0010603 X 80 80 11 11 61 61 -0 01 01 603 EMPTY
2
15 16
2
17 18
HDD_RX_DP
OUT
1
C1E1
V_5P0
D1E1 2
RT1U1
2 2
0.01U 0.0 1UF F
16V
10%
X7R 402
1
1.5A 0.11DCR
36
IN
ODD_TX_DP
1
1
C1E5
1
C1T5
100UF 20% 16V
2 ELEC RDL
1UF 10% 50V X7R 603
2
1
0.01UF
16V
ODD POWER DECOUPLIN DECOUPLING G
ODD_TX_DP_C
V_12P0
X7R 402
C1T4
C1T3
50V X7R 603
50V X7R 402
1UF 10%
2
GND GND GND GND V_HDD V_HDD V_HDD V_XPOD EMI1 EMI2 ME1
ME2
TH
470PF 5%
RT1R1 2
10%
DD+
V_HDD
THRMSTR 1812
V_5P0DUAL
2
GND
3
ODD OD D SATA C1C6
D+ D-
X800351-002
BAV99 SOT23S DIO
1
GND
XENON HDD CONN
MTGA<8-1> MTGB<8-1>
HDD_RX_DP_C
36
CONN
2
10%
1
1.1A 0.21DCR
V_XPOD
THRMSTR 1206
V_3P3 1
2
V_3P3
C1T1
V_3P3
C1T2
1UF 10% 50V X7R 603
470PF 5%
50V X7R 402
ODD OD D POW POWER ER AND CO CONTR NTROL OL CR1D2
CR1D3 2
36
IN
ODD_TX_DN
1
C1C5
0.01UF
16V
J1C1 2
ODD_TX_DN_C
SATA
1
100UF 20% 16V 2 ELEC RDL
9
10%
X7R 402
1 2
C1C4
4
C1C10
1
C1C1 4 1UF 10%
C1C11
1
100UF 20%
0.1UF 10%
50V X7R 603
2
1
C1C1 3
16V
25V X7R 603
2 ELEC RDL
C1D6 1UF 10%
2
50V X7R 603
C1R1
OUT
ODD_RX_DN
1
2
ODD_RX_DN_C
10%
1
6.3V X5R 402
TRAY_STATUS_R
16V
10%
36
OUT
ODD_RX_DP
1
C1C3
0.01UF
16V
V_5P0
7
X7R 402
34
CONN 2
TRAY_STATUS
1 100
402
ODD_RX_DP_C
1
C1D9
1
100UF 20% 16V
10%
2 ELEC RDL
X7R 402
[PA [P AGE_TIT ITL LE=CONN,
OUT
8
C1D4
1
1UF 10%
2
50V X7R 603
2
C1D1 1UF 10% 50V X7R 603
C1D3
R1R4
2
V_3P3
5% CH
1
BAV99 SOT23S EMPTY
5 6
0.01UF
3
.1UF
3
36
2
3
J1D1
V_5P0
1 3 5 7 9
4 6 8
V_12P0
.1UF 10% 6.3V X5R 402
BAV99 SOT23S EMPTY
10 12
EJECTSW_N TRAY_OPEN
42
34
34
C1R4 75PF
5%
CONN
ODD + HD HDD]
1
11
IN IN
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 35 35
2 00 00 5
MICROSOFT CONFIDENTIAL
2
50V NPO 402
PROJECT NAME XENON_RETAIL
PAGE 47/73
REV K7
DB8M1 TP
1 DB8M2 TP
1
V_12P0
V_3P3STBY
FTP
1
FT9N1
DB8M3 TP
1
1
2
C6G5
100UF 20% 16V ELEC 2 RDL
1
1500UF 20%
C6G2 470PF
34
R6G7
1 0
603
IN
2
R8A1
5% CH
L6G1
ARGONPORT_DN
BI
J9A1
1
C8A1 .1UF
1 2 3
GND GND GND
4 5 6
V12P0 V12P0 V12P0
7
2
402
8
C8A2 470PF
10%
9 10 13 14
5%
6.3V X5R 402
2
50V EMPTY 402
11 12
3 TH
35
ARGONPORT_DP
BI
J6G1
2
1
CONN
1
C6G3
1
C6G4
470PF 5%
2
R6G8
1 0
603
2
50V EMPTY 402
470PF
ARGON_DN_CM
1 2
50V EMPTY 402
ARGON_DP_CM
3
5%
2
5% CH
GND
5
SPARE C_DATA C_CLK GND NTX
7
8 9
USE LC NET NETWOR WORK K FOR USB 1.1 USE USB CH CHOKE OKE FOR FOR USB 2.0
V_3P3STBY 1
R3N7
VSB5P0 EMI1 EMI2 EMI3 EMI4 ME1
ME2
FT8N1
TH
X02285-004
DD+
4
6
FTP
XENON RF CONN
VCC
PSU_EN
MTGA<8-1> MTGB<8-1>
V_5P0STBY 1
X801560-001
CONN XENON PWR
EMPTY
CMCHOKE
4
0.1UF 10% 25V X7R 603
2
PSU_V12P0_EN_R 1
CH 2
0.1UF 10% 25V X7R 603
2
C9A2
1
5% CH
10K 5%
NA SM
35
R8A2
1
C9A6
10%
25V X7R 603
2
100 402
1
1
0.1UF
25V X7R 603
PSU_V12P0_EN
2
C9A5
10%
2
ALUM 2 RDL
50V X7R 402
1
C9A1 0.1UF
16V
5%
1
1
C9B1
C5B7
1
10 11
EMI1
12 13
ME1
1
100UF 20%
C8B1
1
C9A4
100UF 20%
16V
16V
2 ELEC RDL
470PF 5%
50V X7R 402
2
2 ELEC RDL
EMI2
V_5P0STBY
ME2
V_12P0
V_12P0
10K
5% CH
402
2 34
IN
PWRSW_N
2 10K
402
R3N6 5% CH
X800095-001 1
1
1
R8B5
PWRSW_N_R
R7B2
2.2K 2
C6V15
5%
CH
470PF 5%
1
2.2K
5%
2
50V X7R 402 34 34
BI BI
CH
402
2
C6V11
2
470PF 50V X7R 402
C6V10 5%
1
50V X7R 402
44
OUT
ARGON_NTX 2
5%
[PA [P AGE_T _TIT ITLE LE=C =CO ONN NN,,
ARG RGO ON + POWE POWER] R]
1
5% CH
BLEEDER_V12P0_B1
Q8B4
Q8N1 2
BCP51 XSTR 4
1
2
2
1
1
R7N3
R7N1
CH
CH
CH
CH
805
805
805
805
10 1%
MMBT2222 XSTR
Q8B5
3 1
BLEEDER_V12P0_B2
1 3
1
1
1% CH
R7N4
2
R7N2
10 1%
10 1%
2
10 1%
2
MMBT2222 XSTR 2
C6V12 470PF
1
R8A4
R8N1
BLEEDER_V12P0_LOAD
1
3
2
2.2K 402
549 402
P 2 1 V _ R E D E E L B
P 2 1 V _ R E D E E L B
470PF
5%
1
2
2 C _ 0
1 C _ 0
ARGON_DATA ARGON_CLK
402
2
50V X7R 402
34
28
IN
ANA_V12P0_PWRGD
2
2.2K 402
R8A3
1
5% CH
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 35 35
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 48/73
REV K7
4
IN
CPU_VREG_APS5
IN
CPU_VREG_APS4
R7E3
4
5
5% CH
0
402
0 4
IN
CPU_VREG_APS3
4
IN
CPU_VREG_APS2
R7E5
402
5% CH
0
402
IN
CPU_VREG_APS1
IN
CPU_VREG_APS0
R7E2 0
4
402
5% CH
402
4
5% CH
3
1
R7E4 0
4
V_GPUCORE
R7E1
5% CH
1K
R7T6 EMPTY 402
2
5% CH
5
4
1
CH
402
2
402
EMPTY 402
2
2
1
1
2
EMPTY 402
0
1
1
VREG_CPU_VID<5..0>
1
R7T15
R7T14
R7T12
R7T16
EMPTY 402
EMPTY 402
EMPTY 402
CH
CH
402
402
10K 5%
2
10K 5%
2
10K 5%
2
1
2
N:CPU N:CP U
INPUT INPU T
5%
50V NPO 402
N:GPU N:GP U
1.6UH
C9B2
10A NA
2
V_VREG_CPU
IND TH
C9C4
2
C9C1
1500UF 20% 16V ALUM RDL
4.7UF 10% 16V
X5R 1206
1500UF 20% 16V
ALUM RDL
C9E3
1500UF 20% 16V
ALUM RDL
C9D2
1500UF 20% 16V ALUM RD L
1
2
C9B4
10UF 20% 16V EMPTY 1206
1
2
2200UF 20% 6.3V ALUM RDL
[PA [P AGE_T _TIT ITLE LE=V =VRE REGS GS,,
1
OUTPUT OUT PUT FILTER FILTER
C8E3
2200UF 20% 6.3V ALUM RDL
INP IN PUT
C8F2
2200UF 20% 6.3V ALUM RDL
C8E8
2200UF 20% 6.3V ALUM RDL
51
1
FILTER FIL TER
2
C8B2
10A NA
IND TH
4.7UF
V_CPUCORE
C8F1
50
2
10UF 20% 16V EMPTY 1206
C8D1
2200UF 20% 6.3V ALUM RDL
+ OUT OUTP PUT FI FILT LTER ERS] S]
10% 16V
V_VREG_GPU 1
C6B3
1500UF 20% 16V
ALUM 2 RDL
X5R 1206
1
1
C7B3
1500UF 20%
C8B4
1
10UF 20%
16V
2
ALUM 2 RDL
16V
1
16V
X5R 1206
OUT 1
C6N2
10UF 20% 2
X5R 1206
C6B5
10UF 20% 16V X5R 1206
2
C7B4
1
10UF 20% 2
16V
X5R 1206
2
52
53
C7N3 10UF 20% 16V X5R 1206
DB8P1
1
1 C8F3 2200UF 20% 6.3V 2 ALUM RDL
1.6UH
OUT
C9C3
1
N:CPU N:CP U
INPUT INPU T
L8B1 1
1
50
220PF 2
FILTER FIL TER
L9B1 1
OUT
C7E13
10K 5%
V_12P0 V_12P0
WATERNOSE=011100=1.1625 WATERNOSE=01110 0=1.1625V V DD1. DD 1.0 0 RE REQU QUIR IRES ES VID0 VID0 RC DD2. DD 2.0 0 NO ST STUF UFF F RC
10K 5%
R7T11 10K 5%
10K
5%
2
R7T9
10K 5%
CH
402
3
1
R7T13
2
2
N: N: N:
1
R7T5
10K 5%
CH
402
1
R7T7
10K 5%
CH 2
1
R7T8
10K 5%
5%
1
0
1
R7T4
10K
R7E6 402
1
2
DB8P2
V_GPUCORE
F TP FT7U1
C8C1
2200UF 20% 6.3V ALUM RDL
N:GPU N:GP U
C8D4
2200UF 20% 6.3V ALUM RDL
1 C7C2 2200UF 20% 6.3V 2 ALUM RDL
1 C7C1 2200UF 20% 6.3V 2 ALUM RDL
1
OUTPUT OUT PUT FIL FILTER TER
1 C6C3 2200UF 20% 6.3V 2 ALUM RDL
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 36 36
1 C6C2 2200UF 20% 6.3V 2 ALUM RDL
2 00 00 5
1
F TP FT5R2
C6C1
820UF 20% 4V
2 POLY RDL
MICROSOFT CONFIDENTIAL
1
C5C4 820UF 20% 4V
2 POLY RDL
PROJECT NAME XENON_RETAIL
PAGE 49/73
REV K7
49
51
V_VREG_CPU
IN
R7V5
2 10
34
IN
FT2P17
FTP
1
VREG_CPU_VCC
1% CH
805
VREG_CPU_EN
1
1
1
1
C7V1
R7F5
50V X7R 603
2
10K 5%
C7G1
R8U3
100UF 20% 16V 2 ELEC RDL
1UF 10%
1
294K 1%
CH 2
402 1
FTP
CH 2
VREG_CPU_PWRGD
IN
R7V1
VREG_CPU_PHASE3 0
5% CH
603 51
IN
VREG_CPU_PHASE2
5% CH
0
603 51
IN
VREG_CPU_RAMPADJ
R7V2 DB7U3
R7V3
VREG_CPU_PHASE1
2
R8V2
R8V1 47.5K
1
R8V4
47.5K
1%
47.5K
1%
1%
CH
CH
CH
603
603
603
1
R _ P M O C S C _ U P C _ G E R V
2
1
VREG_CPU_PHASE3_R VREG_CPU_PHASE2_R VREG_CPU_PHASE1_R
1
2
VREG_CPU_SW4
1
TP
5% CH
0
603
RT8F1
NA
2
THRMSTR 603
100K
R8V3
1
VREG_CPU_CSCOMP
TEMP SENSOR
2
1% CH
35.7K 603
ADP3188
28
VCC
14
RAMPADJ
11
EN
20 21 22 23
PWRGD
SW4 SW3 SW2
R8V5 76.8K
C8V1
5
PWM4 PWM3 PWM2 PWM1
24 25 26 27
1
4
2
3
3
2
4
1 0
5
VREG_CPU_VID<5..0>
18
CSCOMP
17
CSSUM
16
CSREF
8
FB
9 7
VREG_CPU_PWM3 VREG_CPU_PWM2 VREG_CPU_PWM1
2
603
50V NPO 603
2
12
VREG_CPU_DELAY
COMP
RT
13
VREG_CPU_RT
FBRTN
GND
19
51 51
2
1
294K
2
R8U1
R8U4
10% 16V
1%
1%
X7R 603
324K
603
2
205K
CH 1
OUT
51
2
C8U1
.047UF
2
R8U2
2
51
VREG_CPU_DRV_EN
DELAY
VREG_CPU_FBRTN
603
OUT OUT OUT
15
ILIMIT
8200PF 10% 16V CH
49
IN
SW1
1%
CH 1
402
C8U2
1000PF 10%
1
50V EMPTY 402
CH
ST7T1 1
1
402
SHORT 2
VREG_CPU_CSSUM
C7U4
1000PF 10%
V_CPUCORE
1
LAYOUT:ATT LAYOUT: ATTACH ACH TO CLOSEST INDUCTO INDUCTOR R ST8F1 2
6
X803045-001
C8U3
360PF
CH
1
1
10%
1%
1
10
VID5 VID4 VID3 VID2 VID1 VID0
2
1
34
OUT
IC
U7U1 51
FT2P16
402
R8G3
1
VREG_CPU_CSREF
10
SHORT
402
2
1% CH
N:
TARGET TAR GET FSW=233KH FSW=233KHZ Z
50V X7R 402
VREG_CPU_CSREF_R
2
C8G1
1000PF 10%
1
2
C7U2
1
50V X7R 402
VREG_CPU_FB
0.1UF 10% 25V EMPTY 603
2
R7U1
1
1.33K 603
[PAG [P AGE_ E_TI TITL TLE= E=VR VREG EGS, S,
1% CH
2
C7U3 360PF
10%
1 1
C7U1
2
VREG_CPU_COMP_R
3000PF 10% 50V X7R 603
CPU CP U CO CONT NTRO ROLL LLER ER]]
1
4.02K 402
R7U2
2
50V NPO 603 VREG_CPU_COMP
1% CH
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 36 36
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 50/73
REV K7
50
51
51
50
49
IN
R9P2
1
V_VREG_CPU
D9C1 1N4148
2
1
VREG_CPU3_VCC
1% CH
2.2 805
1
2
1.0UF 10% 16V X7R 805
U9P1
IN
IN
50
VREG_CPU_DRV_EN
2 3
6
R9P1
MOS DRIVER BST VCC
1 8
DRVH SW
IN
2
2
VREG_CPU_BST3_R
1% CH
2.2 805
IC
OD_N* PGND
C9P3
1
D
0.01UF 10% 50V X7R 805 1
4 50
3 VREG_CPU_BST3
3
SOT23 DIO
C9P4
VREG_CPU_PWM3
V_VREG_CPU
IN
49
NTD60N02R DPAK C9P2
1
0.015UF
16V
G
2
S
Q9D1
D
Q9D2
1
NTD60N02R DPAK
1 S
G
FET
FET
2
C9D3
1
10UF 20% 2
16V
X5R 1206
C9D1 4.7UF
2
10% 16V
X5R 1206
VREG_CPU_PHASE3
L8D1 2
1
VREG_CPU_DRVH3
7
0.6UH
D
Q9C1
D
G
2
2.2
Q8C1
NTD85N02R DPAK S
TH
R9C1
3
1
IND
30A NA
1 3 G B _ U P C _ G E R V
X801233-001
50
V_CPUCORE
X7R 805
5
DRVL
OUT
5%
1%
NTD85N02R DPAK S
G
FET
2
EMPTY 805
FET
VREG_CPU_SW3_R
1
C9C5
4700PF 10%
R9T2
1
D9E1 1N4148
2
1
VREG_CPU2_VCC
1% CH
2.2 805
1
2
1.0UF 10% 16V X7R 805
VREG_CPU_PWM2
IN
VREG_CPU_BST2
1
R9T1
1 U9T1
2 3
6
MOS DRIVER BST VCC
1 8
DRVH SW
IN
2
3
2
D
10%
50V X7R 805 VREG_CPU_BST2_R
1% CH
2.2 805
IC
OD_N* PGND
C9T2
0.01UF
SOT23 DIO
C9T3
4 50
3
2
C9T1
1
0.015UF
Q9E1 NTD60N02R DPAK
1
2
3
G
S
2
5%
Q9D4
D
NTD60N02R DPAK
1 S
G
FET
1
1
10UF 20% 2
FET
2
C9D4 16V
X5R 1206
C9E1 4.7UF
2
10% 16V
X5R 1206
VREG_CPU_PHASE2
50
L8E1 2
1
VREG_CPU_DRVH2
0.6UH
1
5
R9E1
2 G B _ U P C _ G E R V
X801233-001
OUT
16V
X7R 805
7
DRVL
50V EMPTY 603
30A NA
IND TH
2.2 D
Q9E3
D
NTD85N02R DPAK G
S
1%
Q9D3 2
NTD85N02R DPAK S
G
FET
EMPTY 805
FET
VREG_CPU_SW2_R
1
C9E4
4700PF
R9U2
1
1% CH
2.2 805
2
1
VREG_CPU1_VCC
1
2
VREG_CPU_BST1
R9U1
1
2 3
6
IN
2.2 805
IC
MOS DRIVER BST VCC OD_N* PGND
C9U2
0.01UF
1.0UF 10% 16V X7R 805
VREG_CPU_PWM1
1
SOT23 DIO
C9U3
4
IN
2
3
U9U1
50
10%
D9F1 1N4148
DRVH SW
DRVL
X801233-001
1 8
1% CH
2
2
3 D
10%
50V X7R 805
VREG_CPU_BST1_R
1
C9U1
0.015UF
NTD60N02R DPAK
2
5%
Q9F1
G
S
16V X7R 805
FET
Q9F4
D
NTD60N02R DPAK
1 S
G
FET
2
1
C9F4
1
10UF 20% 2
16V
X5R 1206
50V EMPTY 603
C9F1 4.7UF
2
10% 16V
X5R 1206
VREG_CPU_PHASE1
OUT
50
L8F1 1
VREG_CPU_DRVH1
7
0.6UH
5
1 1 G B _ U P C _ G E R V
R9F1 D
Q9F2
D
NTD85N02R DPAK G
S
FET
S
2 IND TH
2.2
Q8F1
1%
NTD85N02R DPAK G
30A NA
2
EMPTY 805 VREG_CPU_SW1_R
FET 1
C9F3
4700PF 10%
2
[PA [P AGE_TI TITL TLE= E=VR VRE EGS,
CPU OUTP TPU UT
PHAS ASE E
1,2 ,2,3 ,3]]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 37 37
2 00 00 5
MICROSOFT CONFIDENTIAL
50V EMPTY 603
PROJECT NAME XENON_RETAIL
PAGE 51/73
REV K7
53
52
49
V_VREG_GPU
IN
53
52
49
IN
V_VREG_GPU
V_GPUCORE 1
R8N7
VREG_GPU_VID4
1%
CH
2
1
2
805
VREG_GPU_VID3
10000=1.150V
SHORT
2
1
NA
VREG_GPU_VFB_R
2
R8P7
R8P9
2
1
2
1% CH
1.21K 402
THRMSTR 603
10K
1.0UF
R8P4
2
1
10% 16V
10% 16V
X7R 805
C8P2
2
1
52
C8P1
5VSB VFFB
VCCH
7.5K 603
C9P1
2
.047UF
1
R8P1
1
VREG_GPU_COMP_C
10% 16V
C8N5
1
VREG_GPU_VFB
1
VFB
VREG_GPU_VDRP
2
VDRP
VREG_GPU_COMP
32
2
VREG_GPU_SEN
10
CBOUT
NSEN
PGD
CS2
GH2 GL2
19 17
GH1 GL1
22 24
VREG_GPU_CSREF
5
CSREF
VREG_GPU_ROSC
9
ROSC
VREG_GPU_CPGD
28 27
42.2K
CS1
COVC
CH
R8P5
2
1
C8N4
0.01UF 2
1
2
2
C8B3
2
1
2
R8P6
2
VREG_GPU_PHASE1
IN
2
10%
805
2
1
1
C8N1 0.1UF 10% 25V X7R 603
52
OUT
2
LGND GND2 GND1
18 23
1
R8B4
D8B1 MMSZ18 SOD123 DIO
2
2
2
1% CH
7.5K 603
2
3
C9C2
R8C1
10%
1%
0.1UF 1
6.19K
25V X7R 603
CH 1
X800631-001
R5N1 10K 5%
X7R 402 2
25V X7R 603
34
402
IN
FT2P6
1
FTP
25V X7R 603
1
VREG_GPU_GH2_R
R8N5
1
2
1A CH
SHORT
402 2
1
805 VREG_GPU_GH1_R
2
[PAG [P AGE_ E_TI TITL TLE= E=VR VREG EGS, S,
750K
1
C8B7
470PF 5% 50V NPO 603
2
1
R8N3
1 0
R8B3
C8B8 0.1UF 10% 25V X7R 603
FET 2N7002 SOT23
2
5% CH
805
1A CH
VREG_GPU_GL1_R
2
2
VREG_GPU_GL2 VREG_GPU_GH1
R8N4
1
1%
0
CH
805
2
OUT
34
OUT
53
OUT
53
OUT
53
OUT
53
FT2P3
1A CH
0
1
1% CH
FTP
VREG_GPU_GH2 R8N6
1
VREG_GPU_GL2_R
R8B2
R9B1
10K 402
1
VREG_GPU_PWRGD
C8P4
0
2K
1
VREG_GPU_EN_N
Q8B3
R _ N _ N E _ U P G _ G E R V
1
10% 16V
805 2
2
402
C8P3
2
VREG_GPU_CSREF_R
1
V_5P0STBY
10%
2
25V X7R 603
1
CH
0.1UF
ST5D1
52
1
V_GPUCORE
1
53
0.1UF
330 5%
1% CH
7.5K 603
OUT
C9B3
R8N2
10%
52
VREG_GPU_PHASE1
VREG_GPU_NPNC
1
0.1UF
53
1
0.1UF 10% 25V BAV99 X7R 603 SOT23S DIO
CH
1% CH
7.5K 603
603
2
3
2
29
3
CPGD
1%
1
V_GPUCORE
COMP
21
1
2
VREG_GPU_PHASE2
VREG_GPU_5VREF
4
SHORT
IN
VREG_GPU_ILIM
ILIM
3
5% CH
402
31
6
R8P2
VREG_GPU_VCCH
R8N12
1
2
5% CH
0
8
VREG_GPU_CS1
2
20
VREG_GPU_VID0
5VREF
VREG_GPU_CS2
ST5R1 1
VCCL
1% CH
10% 6800PF 50V X7R 603
X7R 603
26
R8N11
1
402
15 14 13 12 11
D8B2 1N4148 SOT23 DIO
5% CH
0
7
VREG_GPU_VFFB
1% CH
4.02K 402
10% 6800PF 50V X7R 603
2
R8P3
2
VREG_GPU_COMP_R
2
VREG_GPU_VID1
NCP5331 VCCL2 VCCL1
30
VREG_GPU_5VREF
IN
10% 1000PF 50V EMPTY 402
IC
U8N1 16 25
VID4 VID3 VID2 VID1 VID0
VREG_GPU_VCCL
1
1
53
2
X7R 805
R8N10
1
VREG_GPU_PHASE1_C
1
1
5% CH
402
1.0UF
1% CH
5.11K 402
1% CH
1.1K 402
R8N9
1
0
C8N2
D8B3
5%
EMPTY
0
VREG_GPU_VID2
1
C8N3
2
0
402
402 1
RT7C1
R8N8
1
2.2 ST5R2
VREG_GPU_GL1
1A CH
603
GPU GP U CO CONT NTRO ROLL LLER ER]]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 38 38
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 52/73
REV K7
52
49
V_VREG_GPU
IN
3 D
52
4.7UF 10% 16V
X5R 1206
NTD60N02R DPAK
1
VREG_GPU_GH2
IN
C6B2 Q6B1
G
S
2
V_GPUCORE VREG_GPU_PHASE2
FET
OUT
52
L6C1 2
1
IND TH
0.6UH 3 D
Q6B2
D
30A NA
1
3
R6B3
Q6C1
2.2 1%
52
1
VREG_GPU_GL2
IN
NTD85N02R DPAK G
S
2
NTD85N02R DPAK
1 S
G
FET
2
CH 2
FET R _ 2 H P _ U P G _ G E R V
2 3 D
52
1
VREG_GPU_GH1
IN
NTD60N02R DPAK G
S
2
C6B4
4700PF
C7B2
10%
4.7UF 10% 16V X5R 1206
Q7B1
805
1
50V X7R 603
FET L7C1 2
1
0.6UH 3 D
1
3
Q7B2
D
R7B6
Q7C1
IND TH
30A NA
VREG_GPU_PHASE1
2.2 1%
52
1
VREG_GPU_GL1
IN
NTD85N02R DPAK G
S
2
NTD85N02R DPAK
1 G
FET
S
2
OUT
52
CH 2
805
FET R _ 1 H P _ U P G _ G E R V
2
C8B6
4700PF 10%
1
V_1P8
V_5P0
IC
U1E1 NCP1117 3 1
1
2
[PA [P AGE_T _TIT ITL LE=V =VRE REGS GS,,
C1T6 1.0UF 10% 16V X7R 805
50V X7R 603
IN
ADJUST/GND X800499-001 DPAK 3.3V
OUT
NCP1117
V_V3P3TOV1P8
1
1
C2T5 0.1UF 10%
2
3
25V X7R 603
GPU OUT UTP PUT PHA PHASE 1,2 1,2]
1
IN
ADJUST/GND
C2E7
100UF 20% 16V
2 ELEC RDL
V_1P8
IC
U2T1 2
X800500-001 DPAK 1.8V
OUT
1
2
1
2
FTP
FT2R8
V_MEM R2T8
1
1A
0
C2R4 0.1UF 10% 25V X7R 603
1
805
C2D6
100UF 20% 16V 2 ELEC RDL
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 39 39
EMPTY
R2T7
1
2
2
0
1A
805
EMPTY
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 53/73
REV K7
54
32
R3V1
1
V_VREG_V1P8V5P0
IN
54
R3V7
54
54
IN
10
V_VREG_V1P8V5P0
IN
2
1% CH
603
54 54
25V X7R 603
D4V2
2
R3V8
2
BAV99 SOT23S DIO
10
1
VREG_5P0_BST_R
C3V6
1
1% CH
402
C6F3
10%
1
805
R3V2
2
1% CH
22.1K 402
IC
VCC
11
COMP2
R4V3
1
1
54
2
2
VFB2
17
ROSC
4
VREG_5P0_BST
1
V_5P0 R6U1
2
D
Q2G1
S
C4V5
VREG_5P0_VREF2
X7R 603
IS+1 IS-1
9
VREG_5P0_VFB1
10% 10V
20 19
GATEH1 GATEL1
1
VREG_5P0_GATEH1
2
VREG_5P0_GATEL1
NC<1> NC<0>
5 6
VREF2
16
MODE
3
FET
2
805 1
54 32
1
C6U1
1
4.7UF 2
R5F5 1%
1
1% CH
5.36K 402 2
10.7K 402
1
VREG_5P0_VFB1_C
R6V1 1% CH
C6V1
1
2
D
805
10% 16V
X5R 1206
2
VREG_5P0_GATEH1_R
G
S
2
1
2
2
R6V2 2K 1%
402
R4G1
1
Q6F1
12.1K 402
IN
FT2P18
C3V3
1
VREG_V5P0_EN_N FTP
1
0.1UF 10%
2
[PA [P AGE_T _TIT ITL LE=V =VRE REGS GS,,
R5F6 1A
25V X7R 603
V1P 1P8 8
AND V5 V5P P0]
1
D
10K
402
R4G6 5% CH
2
Q4G1 FET 2N7002 SOT23
1
2
2
Q3G1 FET SOT23 2N7002
1
10K 402
NTD60N02R DPAK
1
VREG_5P0_GATEL1_R
G
S
2
R3G5 5% CH
2
1
1
FTP
IN
34
2
FT2P19 1
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 39 39
54
FTP
FT6V1
V_5P0 DB6G1 TP
1
NA TH
4.0UH
12A
1
2
805
C7V2
10UF 10% 6.3V EMPTY 1206
C6G1 10UF 10%
6.3V X5R 1206
1
C7F1
2200UF 20% 6.3V 2 ALUM RDL
R _ T U O _ 0 P 5 _ G E R V
FET
402
VREG_V1P8_EN_N
2
1% CH
1%
1
1
2
CH
CH
3
1
R4G2
16.9K 402
54
OUT OUT
1
10% 0.1UF 25V X7R 603
2.2
Q6F2
10K 5%
VREG_ V1 P8 _EN_ N_ R 3
1
C4G1
R6G1 3
805
R3G1
402
2
1
2
0
V_3P3STBY
VREG_ V5 P0 _EN_ N_ R
CH
402 34
1
OUT
54
2
1% CH
FET 1
2 10K 5%
CH
1
54
R4G3
10K 5%
CH
1
OUT
2
R3V5
POLY 2 RDL
VREG_5P0_PHASE VREG_5P0_IS1P
2
CH
V_3P3STBY
POLY 2 RDL
C5F8
220UF 20% 10V ELEC 2 RDL
4V
C6F7
L6F1
4700PF 10% 50V X7R 603
1
C2F3
820UF 20%
4V
4.7UF 10% 16V X5R 1206
NTD60N02R DPAK
1
X800762-001
VREG_V1P8_EN
820UF 20%
C3V7
1%
R6V3
1
C3F2
4700PF 10% 50V X7R 603
51.1K
2
1
6.3V X5R 1206
805
3
CH 1
VREG_V5P0_EN
TP
C3U6
2
2.2
EMPTY 402
DB3F1
V_VREG_V1P8V5P0
IN
2
2
V_5P0
V_MEM
2
1% CH
VREG_1P8_GATEL2
GND
R4V2
FT2U1
VREG_1P8_GATEH2
VFB1
13
FTP
R _ T U O _ 8 P 1 _ G E R V
CH
COMP1
7
1
R3V6
10UF
CH
NTD60N02R DPAK
1
10% 0.1UF 25V X7R 603
10%
1%
0 1A
GATEH2 GATEL2
1
2.2
2
1
12A
R2V2 3
805
R3V9
BST
8
VREG_5P0_IS1M
1
1% CH
402 402
VREG_5P0_IS1P
IN
220NF
VREG_V5P0_EN_R
D4V1 MMSZ18 SOD123 DIO
10%
12
VREG_1P8_ROSC
10
2
1% CH
43.2 402 0.1UF
VREG_1P8_VFB2
54
OUT 1
1
1
NA TH
4.0UH
C3V2
15.4K 402
2
1 2
CH
NCP5425
18
VREG_1P8_IS2M
VREG_V5P0_EN
IN
54
1
2
1% CH
13.3K 402
1%
IS+2 IS-2
402
2
1
R3U2
14 15
VREG_1P8_IS2P
R3V4
FET
2
CH
VREG_1P8_IS2P
1
2.2
G
R3G7
10% 16V
X5R 1206
VREG_1P8_OUT
VREG_1P8_GATEL2_R
CH
1
S
2
1%
0.1UF
C3F6 4.7UF
L2F1
U4V1
330 5%
25V X7R 603
G
EMPTY 402
2
X5R 1206
NTD60N02R DPAK
1
VREG_1P8_GATEH2_R
1
1.07K
C4V2
2
1500UF 20% 16V 2 ALUM RDL
2
1
R4V1
C4V3
C7F2
1%
2
1
1
1500UF 20% 16V ALUM RDL
18.7K
1
1
2
Q3F1
D
R3V3
2
1% CH
1.47K 402
54
32
10% 16V
3
2
10% 4700PF 50V X7R 603
R3G6
2
25V X7R 603
10A
2
1% CH
402 402
V_MEM
3
OUT
NA TH
1.6UH
R _ 0 P 5 V 8 P 1 V _ G E R V _ V
VREG_1P8_VFB2_C
2
X7R 805
V_VREG_V1P8V5P0
VREG_1P8_IS2P
IN
R2U1
1
1 VREG_5P0_PHASE_C
2
1
V_MEM
10%
1
2
2
L7F1
10% 16V
C4V4 0.1UF
1
2
C3U5 4.7UF
C3V1
470NF 10% 10V X7R 603
VREG_5P0_PHASE
2
C3V4
1
VREG_V1P8_EN_R
V_VREG_V1P8V5P0
IN
1 1
1.0UF
1
54
32
V_12P0
VREG_V1P8_EN
IN
32
2
1% CH
2.2 805
2 00 00 5
C5G2
4700PF 10% 50V X7R 603
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 54/73
REV K7
U6T2
V_5P0
V_5P0 R2F2
1
V_5P0 2
1
1
R1F7 1K 5%
3
CH 2 34
IN
1A
EMPTY
1
SOT23 NTR2101P FET
R1F8
1
2
1 VREG_3P3_EN_N_R
Q2F2
U1F1
IN
1
C1U1
2
GND
10% 16V
4
TAB
1
X800498-001 3.3V
X7R 805
2
1
C1F5
FTP
CH
CH 2
16V
2 ELEC RDL
3
ENABLE
C7T100
V OUT
5
GND
2 4
X803461-001 SOT23_5 3.5V
1UF 10%
402
1 C _ N E _ E S U F E _ G E R V
C1F3
VIN
NC
10K 5%
50V X7R 603
FT1U1
100UF 20%
0.1UF 10% 25V X7R 603
R6T3
402
2
1
2
OUT
R7T10 10K 5%
IC
NCP1086
3
1.0UF
5% CH
1K
402
LP2980 1
1
V_3P3
VREG_V3P3_IN
402
VREG_3P3_EN_N
0
805
EMPTY
V_5P0
2
V_EFUSE IC
U6T1 NCP502D
VREG_EFUSE_EN_C2
1
VIN
3
ENABLE
1
5
V OUT
4
NC
4
IN
R6T4
2
VREG_EFUSE_EN
1K
FT7T8
V_5P0STBY
1
1
ADJUST/GND
C5B3
1
2
OUT
1
10% 16V
X7R 805
1
C5B1
5
VREG_EFUSE_EN_R
4
2
10%
2
1
FT5N1
NCP1117
1
IN
1
C5B2
1
2
X800500-001 DPAK 1.8V
X7R 805
2
1
C5B6
1
FTP
BAV99 SOT23S EMPTY
D _ Y B T S 8 P 1 V _ Y B T S 3 P 3 V
FT5N2
NCP1117
1
C2C5 1.0UF
2
10% 16V
X7R 805
3
IN
1
ADJUST/GND
TARG TA RGET ET IS
3
4
R3C22
R3C21
499
X800501-001 SOT223 1.2V
1
402
R5C6
R2C3
C2C6
243
.1UF
1%
10%
6.3V X5R 402
CH
2
0402
1A CH
0
805
1A
EMPTY
2
402 1
R5C4
1
805
2
VREG_CPUPLL_IN
1A CH
1
2
C6P1 1.0UF 10% 16V X7R 805
EMPTY
IN
ADJUST/GND
LIN INE EAR
VREGS VREG S]
6.3V X5R 805
TARG TA RGET ET IS
2.20 2. 20V V 1
2
OUT
1
4
OUT/TAB
EMPTY 402
VREG_CPUPLL_ADJUST
1
1
R6R2
C6R1
374 1%
.1UF 10%
C3C1
1
1%
2
2
6.3V EMPTY 402
6.3V X5R 805
2
EMPTY 402
1% CH
2
0402
R _ L L P U P C _ G E R V
1
2
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 40 40
2 00 00 5
FT7R3
R6R1
499
X800501-001 SOT223 1.8V
FTP
1
R6R3
10%
[PA [P AGE_T _TIT ITLE LE=[ =[VR VREG EGS S,
N:
NCP1117 3 1
4.7UF 2
C5C5
V_CPUPLL
U6R1
R _ X E P _ D D V _ G E R V
1
2
2
0
805
CH 2
VREG_VDD_PEX_ADJ
1
FT2P26
1
10%
R6C1
1
1%
1%
CH
2
FTP
CH
402
4.7UF
V_3P3
0
1
5%
2
0402
R _ X E I C P _ G E R V
R5P1
2
V_1P8 1
1
1
1%
2
0
.1UF 10% 6.3V X5R 402
2
FT5R1
CH
402
1
C5P1
FTP
R5C9
CH
2
1
1.87V 1.8 7V
1 1
VREG_PCIEX_ADJUST
BAV99 SOT23S EMPTY
2
OUT OUT/TAB
1.25 1. 25V V
1K 1%
X800501-001 SOT223 1.2V
10% 16V
X7R 805
1
1
N:
TARG TA RGET ET IS 1
4
R5P2
1.0UF
V_SBPCIE IC
N:
2
OUT OUT/TAB
2
V_3P3 U3P1
IN
ADJUST/GND
C4C6
2
NCP1117
3 1
CR4P2
V_1P8STBY
C5B4
IC
U5C1
3
100UF 20% 16V ELEC 2 RDL
0.1UF 10% 25V X7R 603
V_GPUPCIE
V_3P3
1
2 ELEC RDL
1
1.0UF 10% 16V
XSTR
CR4N1
16V
25V X7R 603
2
OUT
ADJUST/GND
C5B5
1UF 10%
402
V_3P3STBY
IC
U5B2
50V EMPTY 603
5%
FTP
V_1P8STBY
3
1
50V X7R 603
10K
2
V_5P0STBY
X800489-002 SC70 3.5V
2
FT7T6
R6T1
100UF 20%
0.1UF
X800499-001 DPAK 3.3V
1.0UF
2
1
5% CH
C7T99
CH
NCP1117 IN
FTP
V_3P3STBY
IC
U5B1 3
402
1
6
3
C7T98 1UF 10%
CR6T1 MBT3904
FTP
2
GND
MICROSOFT CONFIDENTIAL
C7P1 4.7UF 10% 6.3V X5R 805
PROJECT NAME XENON_RETAIL
PAGE 55/73
REV K7
XDK,, XDK
DEBUG DEB UG CONN CONNECT ECTORS ORS V_5P0DUAL KER_DBG_RXD
J1D2 2X5HDR_10 35
OUT
35
IN
SPI_SS_N SPI_MISO
SPI_MOSI SPI_CLK
1 3 5 7 9
2 4 6 8
33
OUT
V_5P0STBY 35
OUT OUT
J1F1
35
1X6HDR
1
C1D7
EMPTY
R2P18
100
.1UF 10% 6.3V X5R 402
2
SMC_RST_N
IN
28
34
46
34
5% CH
402
34 34
V_3P3STBY
13
34
IN IN IN IN
1 2 3 4 5 6
DBG_LED0 DBG_LED1 DBG_LED2 DBG_LED3
EMPTY TH N _ K D X _ T S R _ C M S
J2B1
V_3P3
C3B5
C2B15 1UF 10%
.1UF 10% 6.3V X5R 402
50V X7R 603
2X7HDR_14 33 34 34
KER_DBG_TXD SMC_DBG_TXD SMC_DBG_EN
IN IN
OUT
SMB_CLK_R
1
10 12
.1UF
6.3V X5R 402
46
28
34
BI
SMB_CLK
1
R2N13
100
EMPTY
R2B7
1
EXT_PWR_ON_DBG
2
2
SMB_DATA
28
BI
34
46
V_12P0
5% CH
100 402
1K
2
EXT_PWR_ON_N
43
OUT
5% CH
402
5% CH
402
R2N14
1
SMB_DATA_R
11 13
C1R2 10%
2
1 3 5 7 9
2 4 6 8
56
34
V_5P0STBY
1
D8B4 GREEN SM
2
1
1
C2B13
C2B12
10%
1UF 10%
6.3V X5R 402
50V X7R 603
.1UF
2
V_12P0
R8B6 2K 1%
EMPTY 402
2
V_5P0STBY R7V7
1
V_5P0
2
3
1X2HDR
1A
805
EMPTY
R8A5
1
J9A2
0
EMPTY
1
2
1K
5%
4 02 02
E MP MP TY TY
Q8B6
1
MMBT2222 EMPTY
2
2
R7V6
1
2
0
1A
805
EMPTY
N A F U P G _ V
SM
EMPTY
C9A3
V_1P8
V_1P8
.1UF 10% 6.3V X5R 402
2
J7G1 1X3HDR
1
C7G3
1
4.7UF 2
10% 16V
EMPTY 2 805
C7G4
2
R8C3
1 2
10K 5%
3
EMPTY 402
1
EMPTY
0.01UF 10% 16V EMPTY 402
2
R8C4
1
EMPTY 402
2
R8C5
10K 5%
1
EMPTY 402
2
R8C6
10K 5%
1
10K 5%
1
R8P8
C8P5
10K 5%
.1UF 10%
EMPTY 402
2
6.3V X5R 402
CH 1
402
J8C1 4
CPU_RST_V1P1_N
IN
R8C2
2 1K
57 57 57
57
OUT OUT IN
OUT
CPU_TMS CPU_TRST_N CPU_TDO CPU_TDI FT7R7
FTP
1
402
2X5HDR 1
5% CH
CPU_RST_N_2_R
2
CPU_CHECKSTOP_N
1
4
3
6
5
8
7
10
9
CPU_TCLK EXT_PWR_ON_N
57
IN
OUT OUT
57
43
56
34
EMPTY 1
C7D23 .1UF 10%
2
[PA [P AGE_TI TITL TLE E=XDK.
DEBU BUG G CONN]
6.3V EMPTY 402
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 6: 6: 59 59
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 56/73
REV K7
V_GPUCORE U4D1
GPU VERSI VERSION ON
DEBU DE BUG G BO BOAR ARD, D,
CPU CP U + GP GPU U DE DEBU BUG G BR BREA EAKO KOUT UT]]
IC
7 OF 8 57 TBCLK3 TBCLK2 TBCLK1 TBCLK0
U7D1 E25 D29 G30
56
F32
56
56 56
G21 G22 F22 G23 D23 G24 E23 E24 D24 G25 G26 E26 D26 E27 D27 E28 D28 H29 E29 H30 C30 B30 A30 G31 B31 A31 B32 A32 F33 E33 D33 E34
TB31 TB30 TB29 TB28 TB27 TB26 TB25 TB24 TB23 TB22 TB21 TB20 TB19 TB18 TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB10 TB9 TB8 TB7
TB6 TB5 TB4 TB3 TB2 TB1
TB0
IN IN IN IN
CPU_TCLK CPU_TDI CPU_TMS CPU_TRST_N
AH7 AK8 AK4 AK7
TDI
TMS TRST_B
C6T35
1
.1UF
2
C7T90 .1UF
10%
6.3V X5R 402
1
.1UF
10%
2
C6T36
1
2
6.3V X5R 402
C7T91 .1UF
10%
6.3V X5R 402
10%
2
6.3V X5R 402
V_GPUCORE
1
C7T89
1
.1UF
2
C6T34
1
.1UF
10%
6.3V X5R 402
2
C7T92
1
.1UF
10%
2
6.3V X5R 402
C6T31 .1UF
10%
6.3V X5R 402
10%
2
6.3V X5R 402
X02056-010
TP7M2 TDRX2 1 2
TDR_SINGLE_XDK2
1 2
TDR_DIFF_XDK2_DN
EMPTY
SIG GND
TP8A1 TDRX2
[PAG [P AGE_ E_TI TITL TLE= E=DE DEBU BUG G
1 2 3 4
BOAR BO ARD, D,
DN
GND
1 2 3 4
EMPTY
DP
GND DN
GND
EMPTY
DP
GND DN
GND
TP8M2 TDRX4
EMPTY
SIG GND
GND
TP8M1 TDRX4 TDR_DIFF_XDK1_DP
EMPTY
DP
TP7A2 TDRX4 1 2 3 4
TDR_DIFF_XDK1_DN
1 2
1 2 3 4
EMPTY
SIG GND
TP8A2 TDRX2 1 2
TDR_SINGLE_XDK1
TDR_DIFF_XDK2_DP
SIG GND
TP7M1 TDRX2
TP7A1 TDRX4
EMPTY
EMPTY
20 TDO CHECKSTOP_B DEBUG_CLKOUT_DP DEBUG_CLKOUT_DN DEBUG_OUT0 DEBUG_OUT1 DEBUG_OUT2 DEBUG_OUT3 DEBUG_OUT4 DEBUG_OUT5 DEBUG_OUT6 DEBUG_OUT7 DEBUG_OUT8 DEBUG_OUT9 DEBUG_OUT10 DEBUG_OUT11 DEBUG_OUT12 DEBUG_OUT13 DEBUG_OUT14 DEBUG_OUT15 DEBUG_OUT16 DEBUG_OUT17 DEBUG_OUT18 DEBUG_OUT19 DEBUG_OUT20 DEBUG_OUT21 DEBUG_OUT22 DEBUG_OUT23 DEBUG_OUT24 DEBUG_OUT25 DEBUG_OUT26 DEBUG_OUT27 DEBUG_OUT28 DEBUG_OUT29 DEBUG_OUT30 DEBUG_OUT31 DEBUG_OUT32 DEBUG_OUT33 DEBUG_OUT34 DEBUG_OUT35 DEBUG_OUT36 DEBUG_OUT37 DEBUG_OUT38 DEBUG_OUT39 DEBUG_OUT40 DEBUG_OUT41 DEBUG_OUT42 DEBUG_OUT43 DEBUG_OUT44 DEBUG_OUT45 DEBUG_OUT46 DEBUG_OUT47 DEBUG_OUT48 DEBUG_OUT49 DEBUG_OUT50 DEBUG_OUT51 DEBUG_OUT52 DEBUG_OUT53 DEBUG_OUT54 DEBUG_OUT55 DEBUG_OUT56 DEBUG_OUT57 DEBUG_OUT58 DEBUG_OUT59 DEBUG_OUT60 DEBUG_OUT61 DEBUG_OUT62 DEBUG_OUT63 DEBUG_OUT64 DEBUG_OUT65 DEBUG_OUT66 DEBUG_OUT67 DEBUG_OUT68 DEBUG_OUT69
V_GPUCORE
1
IC
3 OF 1 0 CPU VERS VERSIO ION N
TCLK
AJ7 AK2
CPU_TDO CPU_CHECKSTOP_N
E25 F25
CPU_DBG_CLK_DP OUT CPU_DBG_CLK_DN OUT CPU_DBGSEL_XDK<0..69>
C7 F13 B7 A7 A8 A9 C10 B10 A10 E11 E12 E13 A11 F15 E14 D12 A12 D14 E15 C13 B13 E16 A13 A14 A15 D16 C16 B16 E17 F17 A17 A16 A18 E18 A19 D18 B19 A20 C19 A21 E19 D20 F19 A22 B22 E20 A23 C22 A24 A25 E21 D22 A26 B25 F21 E22 A27 A28 C25 D24 A29 E23 A30 B28 C29 F23 B30 E24 C28 C30
0 1 2 3
OUT OUT
56 56
OUT
31
N:CPU_DBGSEL_DEBUG<0..69> N:CPU_DBGSEL_XDK<0..69>
4 5 6 7
8 9
10 11 12 13 14 15 16 17 18 19 20 21
22 23 24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
63 64 65 66 67 68 69
X02046-002
DP
GND DN
GND
CPU CP U + GP GPU U DEBU DEBUG G BRE BREAK AKOU OUT] T]
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 41 41
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 57/73
REV K7
INTELLI INT ELLIGEN GENT T
SERIAL SERI AL
NUMBER NUM BER TAR TARGET GET..
LB7G1 LABEL
1
1375X250_TARGET X801181-001
WEST PCB MOU MOUNTI NTING NG HOLE HOLES S
MIDDLE MID DLE
EDGE MTG1B1 MTG_HOLE NC9
NC9
9
NC9
9
CTR
9
NC9
9
NC9
EMPTY GND=1,2,3,4,5,6,7,8
HEAT SINK STD
NC9
STD
NC9
9
EMPTY GND=1,2,3,4,5,6,7,8
STD
MTG3E1 MTG_HOLE 9
EMPTY GND=1,2,3,4,5,6,7,8 STD
NC9
9
EMPTY GND=1,2,3,4,5,6,7,8 STD
MTG6C1 MTG_HOLE
MTG8E1 MTG_HOLE 9
EMPTY GND=1,2,3,4,5,6,7,8
STD
NC9
9
EMPTY GND=1,2,3,4,5,6,7,8
STD
MTG5C1 MTG_HOLE NC9
MOUNTI MOU NTING NG HOLES STD
MTG3C1 MTG_HOLE
NC9
9
EMPTY GND=1,2,3,4,5,6,7,8
MTG6E1 MTG_HOLE 9
EMPTY GND=1,2,3,4,5,6,7,8
NC9
9
EMPTY GND=1,2,3,4,5,6,7,8 EDGE MTG9B1 MTG_HOLE
MTG5B1 MTG_HOLE
MTG8C1 MTG_HOLE
MTG5E1 MTG_HOLE 9
EMPTY GND=1,2,3,4,5,6,7,8
AND AN D MO MOUN UNTI TING NG]]
EDGE MTG9G1 MTG_HOLE
EMPTY GND=1,2,3,4,5,6,7,8
EMPTY GND=1,2,3,4,5,6,7,8
[PAG [P AGE_ E_TI TITL TLE= E=LA LABE BELS LS
EAST PCB MOUNTING MOUNTING HOLE HOLES S
CTR
MTG5G1 MTG_HOLE
EMPTY GND=1,2,3,4,5,6,7,8 EDGE MTG1G1 MTG_HOLE NC9
PCB MOUNTING HOLE HOLES S
NC9
9
EMPTY GND=1,2,3,4,5,6,7,8
DRAWING XENON_FABK W ed ed Au Au g 2 4 0 9 :2 :2 7: 7: 41 41
2 00 00 5
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 64/73
REV K7
R8G3
RESN RE
50
S T8F1
SHORT
50
R8N1
RESN RE
48
S W1 G1
S WI TCH
42
R8N2
RESN RE
52
S W2 G1
S WI TCH
42
R8N3
RESN RE
52
S W2 G2
S WI TCH
42
R8N4
RESN RE
52
S W5 G1
S WI TCH
42
R8N5
RESN RE
52
TP6D1
PROBE PR
4
R8N6
RESN RE
52
TP6R1
PROBE PR
R8N7
RESN RE
52
TP6R2
PROBE PR
4
R8N8
RESN RE
52
TP 7A1
TDRX 4
57
R8N9
RESN RE
52
TP 7A2
TDRX 4
57
R8N10
RESN
52
TP 7M1
TDRX 2
57
R8N11
RESN
52
TP 7M2
TDRX 2
57
R8N12
RESN
52
TP7R1
PROBE PR
4
R8N17
RESN
34
TP7R2
PROBE PR
4
R8N18
RESN
34
TP7R3
PROBE PR
R8P1
RESN RE
52
TP7R4
PROBE PR
4
R8P2
RESN RE
52
TP 8A1
TDRX 2
57
R8P3
RESN RE
52
TP 8A2
TDRX 2
57
R8P4
RESN RE
52
TP 8M1
TDRX 4
57
R8P5
RESN RE
52
TP 8M2
TDRX 4
57
R8P6
RESN RE
52
U1 B1 B1
B CM5 24 24 1
R8P7
RESN RE
52
U 1B 2
I CS 18 18 93 93 BF BF
39
R8P8
RESN RE
56
U1 E1 E1
NCP 11 11 17
53
4
4
19
R8P9
RESN RE
52
U1 F1
NCP 10 10 86
55
R8U1
RESN RE
50
U1 F2
NCP 11 11 17
45
R8U2
RESN RE
50
U1G1 U1 G1
IR_W _WHO HOLD LDER
R8U3
RESN RE
50
U1 R1
S I4 50 50 1DY
46
R8U4
RESN RE
50
U2B1
XDAC XD
40
R8V1
RESN RE
50
U2C1
SB
R8V2
RESN RE
50
U2D1 U2 D1
SN74 SN 74LVC LVC1G 1G12 125 5
R8V3
RESN RE
50
U2E1
NAND NA
R8V4
RESN RE
50
U2E2 U2 E2
R8V5
RESN RE
50
U2R1 U2 R1
SN74 SN 74LVC LVC1G 1G12 125 5
R9B1
RESN RE
52
U2 T1
NCP 11 11 17
R9C1
33
SN74 SN 74LVC LVC1G 1G12 125 5
51
U3B4 U3 B4
MK14 MK 1493 93RE REV1 V13 3
51
U3 D1
GDDR1 36 36
24
U3 E1 E1
GDDR1 36 36
26
45
U3 P1 P1
RESN RE
45
U3 R1
GDDR1 36 36
25
R9P1
RESN RE
51
U3 T1
GDDR1 36 36
27
RESN RE
51
U4B1
ANA
R9T1
RESN RE
51
U 4C 1
A T2 T2 50 50 20 20 A
13
R9T2
RESN RE
51
U4D1
NB
12
R9U1
RESN RE
51
U4 F1
GDDR1 36 36
20
R9U2
RESN RE
51
U4 U1
GDDR1 36 36
21
28
54
RESN RE
45
U4 V1 V1
NCP 54 54 25
R9V2
RESN RE
45
U5 B1 B1
NCP 11 11 17
RT1B1 RT 1B1
THERM THE RMIST ISTOR OR
44
U5 B2 B2
NCP 11 11 17
55
RT1R1 RT 1R1
THERM THE RMIST ISTOR OR
47
U5 C1
NCP 11 11 17
55
RT1U1 RT 1U1
THERM THE RMIST ISTOR OR
47
U5 F1
GDDR1 36 36
22
29
30
13
14
17
57
55
45
U5 U1
RT2M1 RT 2M1
THERM THE RMIST ISTOR OR
43
U6 R1
NCP 11 11 17
55
RT7C1 RT 7C1
THERM THE RMIST ISTOR OR
52
U6 T1
NCP 50 50 2D
55
RT8F1 RT 8F1
THERM THE RMIST ISTOR OR
50
U6T2
LP2980
55
RT8G1 RT 8G1
THERM THE RMIST ISTOR OR
45
U 7D 1
W AT AT ER ERN OO SE SE
RT8G2 RT 8G2
THERM THE RMIST ISTOR OR
45
U7 E1 E1
A T2 50 50 20 A
4
ST1P 1
S HORT
38
U7 U1
A DP 31 31 88
50
ST1P 2
S HORT
38
U8 N1
ST1P 3
S HORT
38
U9P1 U9 P1
MOSD SDRI RIVER VER
51
ST2P 1
S HORT
38
U9T1 U9 T1
MOSD SDRI RIVER VER
51
ST2P 2
S HORT
37
U9U1 U9 U1
MOSD SDRI RIVER VER
51
ST2P 3
S HORT
37
Y 3B 3B 1
CRY ST ST AL AL
46
ST2P 4
S HORT
37
ST4C1
S HORT
29
ST4C2
S HORT
29
ST4C3
S HORT
29
ST4C4
S HORT
29
ST4C5
S HORT
29
ST5D1
S HORT
52
ST5R1
S HORT
52
ST5R2
S HORT
52
ST6D1
SHORT SH
6
ST6R1
SHORT SH
6
ST6R2
SHORT SH
6
ST7D1
SHORT SH
ST7R1
SHORT SH
6
ST7T1
SHORT SH
50
NCP 53 53 31
16
55
R9P2
GDDR1 36 36
15
46
R9G2
THERM THE RMIST ISTOR OR
38
12
51
RT2G1 RT 2G1
37
12
RESN RE
R9V1
36
53
RESN RE
NCP 11 11 17
35
12
R9F1
RESN RE
34
41
R9E1 R9G1
RESN RE
42
23
4 5
6 7
8 57
52
6
MICROSOFT CONFIDENTIAL
PROJECT NAME XENON_RETAIL
PAGE 73/73
REV K7 
