FLIPFLOP: (Answer is in BOLD letter) 1.Which statement BEST describes the operation of a negative-edgetriggered D flip-flop? The logic level at the D input A. is transferred to Q on NGT of CLK. The Q output is ALWAYS identical B. to the CLK input if the D input is HIGH. The Q output is ALWAYS identical C. to the D input when CLK = PGT. The Q output is ALWAYS identical D. to the D input. 2.How is a J-K flip-flop made to toggle? A. J = 0, K = 0 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 1, K = 1 3.How many flip-flops are in the 7475 IC? A. 1 B. 2 C. 4 D. 8 4. How many flip-flops are required to produce a divide-by-128 device? A. 1 B. 4 C. 6 D. 7 5.What is the difference between the enable input of the 7475 and the clock input of the 7474? A. The 7475 is edge-triggered. B. The 7474 is edge-triggered. 6.The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________. A. parity error checking B. ones catching C. digital discrimination D. digital filtering
7.On a master-slave flip-flop, when is the master enabled? A. when the gate is LOW B. when the gate is HIGH C. both of the above D. neither of the above 8. One example of the use of an S-R flip-flop is as a(n): A. racer B. astable oscillator C. binary storage register D. transition pulse generator 9. What is the difference between the 7476 and the 74LS76? A. the 7476 is master-slave, the 74LS76 is master-slave B. the 7476 is edge-triggered, the 74LS76 is edge-triggered C. the 7476 is edge-triggered, the 74LS76 is master-slave D. the 7476 is master-slave, the 74LS76 is edge-triggered 10. Which of the following is correct for a gated D flip-flop? A. The output toggles if one of the inputs is held HIGH. B. Only one of the inputs can be HIGH at a time. C. The output complement follows the input when enabled. D. Q output follows the input D when the enable is HIGH. 11. With regard to a D latch, ________. A. the Q output follows the D input when EN is LOW B. the Q output is opposite the D input when EN is LOW C. the Q output follows the D input when EN is HIGH D. the Q output is HIGH regardless of EN's input state 12. How can the cross-coupled NAND flip-flop be made to have activeHIGH S-R inputs? A. It can't be done. B. Invert the Q outputs. C. Invert the S-R inputs.
13. When is a flip-flop said to be transparent? A. when the Q output is opposite the input B. when the Q output follows the input C. when you can see through the IC packaging 14. Master-slave J-K flip-flops are called pulse-triggered or leveltriggered devices because input data is read during the entire time the clock pulse is at a LOW level. A. True B. False 15. A J-K flip-flop is in a "no change" condition when ________. A. J = 1, K = 1 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 0, K = 0 16. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the: A. B. C. D.
clock is LOW slave is transferring flip-flop is reset clock is HIGH
17. Which of the following describes the operation of a positive edgetriggered D flip-flop? A. If both inputs are HIGH, the output will toggle. B. The output will follow the input on the leading edge of the clock. C. When both inputs are LOW, an invalid state exists. D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock. 18. What does the triangle on the clock input of a J-K flip-flop mean? A. level enabled B. edge-triggered
19. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________. A. constantly LOW B. constantly HIGH C. a 20 kHz square wave D. a 10 kHz square wave 20. The toggle condition in a masterslave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________. A. opposite, active clock edge B. inverted, positive clock edge C. quiescent, negative clock edge D. reset, synchronous clock edge 21. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________. A. the clock pulse is LOW B. the clock pulse is HIGH C. the clock pulse transitions from LOW to HIGH D. the clock pulse transitions from HIGH to LOW 22. What is the hold condition of a flip-flop? A. both S and R inputs activated B. no active S or R input C. only S is active D. only R is active 23. f an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the Q input goes to 0, the latch will be ________. A. SET B. RESET C. clear D. invalid 24. Does the cross-coupled NOR flipflop have active-HIGH or active-LOW set and reset inputs? A. active-HIGH B. active-LOW 25. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses? A. 16 B. 8 C. 4 D. 2
26. What is the significance of the J and K terminals on the J-K flip-flop? A. There is no known significance in their designations. B. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH. C. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit. D. All of the other letters of the alphabet are already in use.
7. Which of the following is the most widely used alphanumeric code for computer input and output? A. C.
Gray B. Parity D.
ASCII EBCDIC
8. Convert 59.72 to BCD. A.
111011 B. 01011001.01110010 C. 1110.11 D.0101100101110010 9. Convert 8B3F to binary.
NUMBER SYSTEMS:
A. 35647B. 011010 C.1011001111100011 D.1000101100111111
1. Convert hexadecimal value 16 to decimal. A. 22 B. 16 C. 10 D. 20
10. Which is typically the longest: bit, byte, nibble, word?
2. Convert the following decimal number to 8-bit binary. 187 A.10111011 B. 11011101 C.10111101 D. 10111100
A. C.
Bit B. NibbleD.
Byte Word
11. Convert hexadecimal value C1 to binary.
3. Convert binary 111111110010 to hexadecimal.
A. C.
A. C.
12. Convert the following octal number to decimal. 17
EE2 2FE
B. D.
FF2 FD2
11000001 B. 111000100 D.
4. Convert the following binary number to decimal. 01011
A. C.
A. C.
13. The BCD number for decimal 347 is ________.
11 15
B. D.
35 10
5. Convert the binary number 1001.0010 to decimal. A. C.
90.125 125 D.
B. 12.5
9.125
6. One hex digit is sometimes referred to as a(n): A. C.
byte B. grouping
nibble D. instruction
A. B. C. D.
51 57
B. D.
1000111 111000001
82 15
1100 1011 1000 0011 0100 0111 0011 0100 0001 1100 1011 0110
14. The sum of 11101 + 10111 equals ________. A. C.
110011 110100
B. D.
100001 100100
15. Convert binary 01001110 to decimal.
A. C.
4E 76
B. D.
A. C.
78 116
16. Which is not a word size? A. C.
64 16
B. D.
28 8
100 001
B. D.
111 110
24. The binary number 11101011000111010 can be written in hexadecimal as ________. A. C.
DD63A 1D33A
B. D.
1D63A 1D631
17. The octal numbering system: A. simplifies tasks B. groups binary numbers in groups of 4 C. saves time D. simplifies tasks and saves time
25. Determine the decimal equivalent of the signed binary number 11110100 in 1's complement. A. C.
116 –11
B. D.
–12 128
18. Convert 1100101000110101 to hexadecimal.
COUNTERS:
A. C.
1.How many flip-flops are required to make a MOD-32 binary counter? A. 3 B. 45
121035 53AC1
B. D.
CA35 530121
19. Hexadecimal letters A through F are used for decimal equivalent values from: A. B. C. D.
00010010 B. 00100011 D.
D. 6
2.A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses? A. 10002 B. 10102
1 through 6 9 through 14 10 through 15 11 through 17
20. Convert the following decimal number to 8-bit binary. 35 A. C.
C. 5
00010011 00100010
C. 10112
D. 11012
3.The terminal count of a modulus11 binary counter is ________. A. 1010 B. 1000
21. A decimal 11 in BCD is ________.
C. 1001
A. C.
4.Integrated-circuit counter chips are used in numerous applications including: timing operations, counting A. operations, sequencing, and frequency multiplication
00001011 B. 00010001 D.
00001100 00010010
22. What is the resultant binary of the decimal problem 49 + 01 = ? A. C.
01010101 B. 00110010 D.
00110101 00110001
23. The difference of 111 – 001 equals ________.
D. 1100
timing operations, counting B. operations, sequencing, and frequency division
timing operations, decoding C. operations, sequencing, and frequency multiplication data generation, counting D. operations, sequencing, and frequency multiplication
9.A BCD counter is a ________. A. binary counter B. full-modulus counter C. decade counter D. divide-by-10 counter
5.Synchronous construction reduces the delay time of a counter to the delay of: A. all flip-flops and gates B.
all flip-flops and gates after a 3 count
C. a single gate D. a single flip-flop and a gate 6.When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers. A. product B. sum C. log
D. reciprocal
7.A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz. A. 500 kHz
10.How many flip-flops are required to construct a decade counter? A. 10 B. 8 C. 5
D. 4
11.The terminal count of a typical modulus-10 binary counter is ________. A. 0000 B. 1010 C. 1001
D. 1111
12.To operate correctly, starting a ring counter requires: clearing one flip-flop and A. presetting all the others. B. clearing all the flip-flops. C.
presetting one flip-flop and clearing all the others.
D. presetting all the flip-flops.
B. 1,500 kHz C. 6 MHz D. 5 MHz 8.Which segments of a sevensegment display would be required to be active to display the decimal digit 2? A. a, b, d, e, and g B. a, b, c, d, and g C. a, c, d, f, and g D. a, b, c, d, e, and f
13.The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on: external logic circuits that decode the various states of A. the counter to apply the correct logic levels to the J-K inputs modifying BCD counters to change B. states on every second input clock pulse C. modifying asynchronous counters to change states on every second
input clock pulse elimination of the counter stages and the addition of combinational D. logic circuits to produce the desired counts
18.Three cascaded modulus-5 counters have an overall modulus of ________. A. 5 B. 25 C.125
D. 500
14.Select the response that best describes the use of the Master Reset on typical 4-bit binary counters. When MR1 and MR2 are both A. HIGH, all Qs will be reset to zero.
19.A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse? A. 1101 B. 1011
When MR1 and MR2 are both
20.The terminal count of a 3-bit binary counter in the DOWN mode is ________. A. 000 B. 111
B.
HIGH, all Qs will be reset to one. MR1 and MR2 are provided to
C. synchronously reset all four flipflops. D.
To enable the count mode, MR1 and MR2 must be held LOW.
15.For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________. A. Cp, the same clock input line B. CE, the same clock input line C. D.
C. 1111
C. 101
D. 010
21.Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the: input clock pulses are applied only A. to the first and last stages. B.
input clock pulses are applied only to the last stage.
C.
input clock pulses are applied simultaneously to each stage.
D.
input clock pulses are not used to activate any of the counter stages.
, the terminal count output , both clock input lines
D. 0000
16.How many different states does a 3-bit asynchronous counter have? A. 2 B. 4
22.A counter with a modulus of 16 acts as a ________. A. divide-by-8 counter
C. 8
B. divide-by-16 counter
D. 16
17.Once an up-/down-counter begins its count sequence, it cannot be reversed. A. True B. False
C. divide-by-32 counter D. divide-by-64 counter 23.A ripple counter's speed is limited by the propagation delay of:
A. each flip-flop B. all flip-flops and gates C. the flip-flops only with gates D. only circuit gates
the five output leads on a 74148 octal-to-binary encoder. I0 = 1 I3 = 1 I6 = 1 I1 = 1 I4 = 0 I7 = 1 I2 = 1 I5 = 1 EI = 0
24.How many natural states will there be in a 4-bit ripple counter? A. 4 B. 8 C. 16
B. flip-flops
B.
GS = L, A0 = H, A1 = L, A2 = L, EO =H
C.
GS = L, A0 = L, A1 = H, A2 = L, EO =H
D.
C. 2 flip-flops D. synchronous clocking
CODE CONVERTERS & MULTIPLEXERS: 1.How many outputs are on a BCD decoder? A. 4 B. 16 D. 10
2.In a Gray code, each number is 3 greater than the binary representation of that number. A. True B. False 3.Which digital system translates coded characters into a more useful form? A. encoder B. display C. counter
GS = L, A0 = L, A1 = L, A2 = H, EO =H
D. 32
25.A modulus-10 counter must have ________. A. 10 flip-flops
C. 8
A.
D. decoder
GS = L, A0 = H, A1 = H, A2 = L, EO = H
5.What is the function of an enable input on a multiplexer chip? A. to apply Vcc B. to connect ground C. to active the entire chip D. to active one half of the chip 6.A basic multiplexer principle can be demonstrated through the use of a: A. single-pole relay B. DPDT switch C. rotary switch D. linear stepper 7.How many inputs will a decimal-toBCD encoder have? A. 4 B. 8 C. 10
4.From the following list of input conditions, determine the state of
D. 16
8.One multiplexer can take the place of:
A. several SSI logic gates
A. data generation
B. combinational logic circuits
B. serial-to-parallel conversion
C. several Ex-NOR gates
C. parity checking
D.
several SSI logic gates or combinational logic circuits
9.How many exclusive-NOR gates would be required for an 8-bit comparator circuit? A. 4 B. 6 C. 8
D. 10
10.A BCD decoder will have how many rows in its truth table? A. 10 B. 9 C. 8
D. 3
11.How many possible outputs would a decoder have with a 6-bit binary input? A. 16 B. 32
D. data selector 15.The primary use for Gray code is: coded representation of a A. shaft's mechanical position B. turning on/off software switches to represent the correct ASCII code C. to indicate the angular position of a shaft on rotating machinery to convert the angular position of D. a shaft on rotating machinery into hexadecimal code 16.Why is a demultiplexer called a data distributor? The input will be distributed to A. one of the outputs. B.
One of the inputs will be selected for the output.
12.Most demultiplexers facilitate which type of conversion? A. decimal-to-hexadecimal
C.
The output will be distributed to one of the inputs.
B. single input, multiple outputs
17.What is the status of the inputs S0, S1, and S2 of the 74151 eight-line multiplexer in order for the output Y to be a copy of input I5?
C. 64
D. 128
C. ac to dc D. odd parity to even parity
A. S0 = 0, S1 = 1, S2 = 0
13.The inputs/outputs of an analog multiplexer/demultiplexer are: A. bidirectional
B. S0 = 0, S1 = 0, S2 = 1
B. unidirectional
D. S0 = 1, S1 = 0, S2 = 1
C. even parity
C. S0 = 1, S1 = 1, S2 = 0
D. binary-coded decimal
18.One way to convert BCD to binary using the hardware approach is: A. with MSI IC circuits
14.One application of a digital multiplexer is to facilitate:
B. with a keyboard encoder
C. with an ALU D. UART 19.How is an encoder different from a decoder? The output of an encoder is a A. binary code for 1-of-N input. B.
The output of a decoder is a binary code for 1-of-N input.
20.Why is the Gray code more practical to use when coding the position of a rotating shaft? A. All digits change between counts. B. Two digits change between counts. C.
Only one digit changes between counts.
be determined from the logic symbol? A. A bubble indicates active-HIGH. B. A bubble indicates active-LOW. C. A square indicates active-HIGH. D. A square indicates active-LOW. 24.How many select lines would be required for an 8-line-to-1-line multiplexer? A. 2 B. 3 C. 4
A circuit that responds to a specific set of signals to produce a related digital signal output is called a(n): A. BCD matrix B. display driver
21.When two or more inputs are active simultaneously, the process is called: A. first-in, first-out processing B. priority encoding C. ripple blanking D.
first-in, first-out processing or priority encoding
22.In a BCD-to-seven-segment converter, why must a code converter be utilized? to convert the 4-bit BCD into A. 7-bit code B.
to convert the 4-bit BCD into 10bit code
C.
to convert the 4-bit BCD into Gray code
D. No conversion is necessary. 23.How can the active condition (HIGH or LOW) or the decoder output
D. 8
C. encoder D. decoder
