Digital Logic Design Lab Manual

Department of Electrical Engineering,

Lab Manual

Prepared & Edited by: Engr.Kamal Shahid (Lecturer) Engr. Abubakar Sharif (Lab Engr.)

Verified by: Engr. Kashif Nisar Paracha (Lec.)

Approved by: Engr. Muhammad Afzal Sipra, TI (M) Associate Professor, Chairman, Department of Electrical Engineering

Digital Logic Design Lab Manual

1

TABLE OF LAB EXPERIMENTS Sr.

Experiment

Page

No. 

1. 

Familiarization with the RIMS ePAL Trainer (digital logic design prospective) and ICs of all logic gates Verification of truth tables of all logic gates

5

2.

Construction of all Logic Gates by using universal gates, NAND gate and NOR gate. Verifying their results

3.

Design and implementation of HALF-ADDER, FULL-ADDER, 4-BIT Parallel Adder circuit.

15

4.

Design and implementation of HALF-SUBTRACTOR, FULL-SUBTRACTOR, 4-BIT Parallel SUBTRACTOR circuit.

19

5. 6.

7.

12

Design and implementation of Gray to BCD converter. 22

To check the operation of 2-to-4 line Decoder and 3-to-8 line Decoder. Using the 74LS139 IC, design a Binary Code Decimal to the seven segment decoder. 

Designing Binary Code Decimal encoder, its understanding and its analysis.



Designing of octal to binary encoder and decimal to binary encoder .

25

30

Designing of 2-to-1, 4-to-1 line multiplexer and a quadruple 2-to-1 line MUX. Also implement 1-to-4 line demultiplexer.

34

9.

Designing of 4-BIT Magnitude comparator and magnitude comparison using 74LS85 IC.

38

10.

Introduction, design and testing of Basic flip flop circuits – SC or SR, JK, D and TFF using NAND gate. Also with IC7476 and IC7474.

40

8.

Designing of SISO, SIPO, PISO and PIPO shift register using D flip flop. 11. 12. 13. 14.

45

Designing of simple ring counter circuits and Johnson counter circuits. Introduction and Designing of synchronous Up and Down counter and its implementation of using J-K flip flop IC. Analysis of Presetable counters.


48 50 53

2

PREFACE The laboratory of each and every subject taught in the degree of Bachelors in Electrical Engineering is of very much importance in every University. Fully equipped laboratory meeting the industrial demands under the supervision of qualified, talented and practically motivated lab assistants and lab engineers is also a basic criterion of the Pakistan Engineering Council. This Manual has been formulated considering all these above mentioned points. This manual is according to the equipment supplied by the RIMS, USA and meets the requirements of all the course of Digital Logic Design as per the curriculum of GC University Faisalabad. Special thanks to the staff and students for assisting me in the preparation of this manual.

With Regards Engr. Kamal Shahid


3

General Lab Instructions  Each

student group consists of a maximum of 2-4 students. Each group member is

responsible in submitting lab report upon completion of each experiment on their practical Note book.  Students

are to wear proper attire i.e shoe or sandal instead of slipper. Excessive

jewelleries are not advisable as they might cause electrical shock. A

permanent record in ink of observations as well as results should be maintained by each

student and enclosed with the report.  The

recorded data and observations from the lab manual need to be approved and

signed by the lab instructor upon completion of each experiment.  Before

beginning connecting up, it is essential to check that all sources of supply at the

bench are switched off.  Start

connecting up the experiment circuit by wiring up the main circuit path, then adds the

parallel branches as indicated in the circuit diagram.  After

the circuit has been connected correctly, remove all unused leads from the

experiment area, set the voltage supplies at the minimum value, and check the meters are set for the intended mode of operation.  The

students may ask the lab instructor to check the correctness of their circuit before

switching on.  When

the experiment has been satisfactory completed and the results approved by the

instructor, the students may disconnect the circuit and return the components and instruments to the locker tidily. Chairs are to be slid in properly.


4

Experiment No. 1

OBJECTIVE 



Familiarization with the RIMS ePAL Trainer (digital logic design prospective) and ICs of all logic gates Verification of truth tables of all logic gates

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 

IC Type 7400 Quadruple 2-input NAND gates



IC Type 7402 Quadruple 2-input NOR



gates IC Type 7404 Hex Inverters







IC Type 7432 Quadruple 2-input OR gates IC Type 7486 Quadruple 2-input XOR gate

IC Type 7408 Quadruple 2-input AND gates

THEORY An integrated circuit (IC) is a small electronic device made out of a semiconductor material. A semiconductor material is a one which is neither a good conductor of electricity nor a good insulator. Semiconductors make it possible to miniaturize electronic components, such as transistors. Not only does miniaturization mean that the components take up less space, it also means that they are faster and require less energy. Logic gates are the digital circuits with one output and one or more inputs. They are the basic building blocks of any logic circuit. Different logic gates are: AND, OR, NOT, NAND, NOR, EX-OR. There logic is briefly explained below. AND: Logic eqn. Y = A.B The output of AND gate is true when the inputs A and B are True. OR: Logic eqn. Y = A+B. The output of OR gate is true when one of the inputs A and B or both the inputs are true. NOT: Logic eqn. Y = Ā.


5

The output of NOT gate is complement of the input. NAND: Logic eqn. Y = A.B The output of NAND gate is true when one of the inputs or both the inputs are low level. NOR: Logical eqn. Y = A+B. The output of NOR gate is true when both the inputs are low. EX-OR: Logic eqn. Y=AB+AB. The output of EX-OR gate is true when both the inputs are low.

Fig. 1.1 Symbol for digital logic gates

In a circuit, logic variables (values 0 and 1) can be represented as levels of voltage. The most obvious way of representing two logic values as voltage levels is to define a threshold voltage; any voltage below the threshold represents one logic value and voltages above the threshold Correspond to the other logic value. To implement the threshold – voltage concept, a range of low and high voltage levels is defined, as shown in Fig. 1.2. This figure indicates that voltages in the range Gnd to Vo, max represent logic value 0. Similarly, the range from V1, min to Vcc corresponds to logic value 1. Logic signals do not normally assume voltages in undefined range except in transition from one logic value to the other.


6

Fig. 1.2 Representation of logic values by voltage levels

CONNECTION DIAGRAM

Figure 1.3 IC 74LS00 (NAND Gate)

Figure 1.4 IC 74LS02 (NOR Gate)


7

Figure 1.5 IC 74LS04 (NOT Gate)

Figure 1.6 IC 74LS08 (AND Gate)

Figure 1.7 IC 74LS32 (OR Gate)


8

Figure 1.8 IC 74LS00 (XOR Gate)

PROCEDURE 1. First get above mentioned apparatus and component from the lab staff. 2. Turn ON the RIMS (ePAL trainer) and the required functions i.e. input, output terminals, Vcc and GND etc. 3. Take IC 74LS00 and place it on bread board. Apply Vcc and GND to the specified pins as shown in the pin configuration below. Apply four combination of input to each gate of the IC and fill the following table 1.1. And compare your result with truth table. 4. Take IC 74LS02 and place it on bread board. Apply Vcc and GND to the specified pins as shown in the pin configuration below. Apply four combination of input to each gate of the IC and fill the following table 1.2. And compare your result with truth table. 5. Take IC 74LS04 and place it on bread board. Apply Vcc and GND to the specified pins as shown in the pin configuration below. Apply four combination of input to each gate of the IC and fill the following table 1.3. And compare your result with truth table. 6. Take IC 74LS08 and place it on bread board. Apply Vcc and GND to the specified pins as shown in the pin configuration below. Apply four combination of input to each gate of the IC and fill the following table 1.4. And compare your result with truth table. 7. Take IC 74LS32 and place it on bread board. Apply Vcc and GND to the specified pins as shown in the pin configuration below. Apply four combination of input to each gate of the IC and fill the following table 1.5. And compare your result with truth table. 8. Take IC 74LS86 and place it on bread board. Apply Vcc and GND to the specified pins as shown in the pin configuration below. Apply four combination of input to each gate of the IC and fill the following table 1.6. And compare your result with truth table.


9

RESULTS & CALCULATIONS Table 1.1

IN A

B

L

L

L

H

H

L

H

H

OUT Gate 1 (V)

Gate 1 (H/L)

Gate 2 (V)

Gate 2 (H/L)

Gate 3 (V)

Gate 3 (H/L) Gate 4 (V)

Gate 4 (H/L)


Gate 4 (H/L)


Gate 4 (H/L)

Table 1.2

IN A

B

L

L

L

H

H

L

H

H

OUT Gate 1 (V)

Gate 1 (H/L)

Gate 2 (V)

Gate 2 (H/L)

Gate 3 (V)

Table 1.3

IN A

B

L

L

L

H

H

L

H

H

OUT Gate 1 (V)

Gate 1 (H/L)

Gate 2 (V)

Gate 2 (H/L)

Gate 3 (V)

Table 1.4

IN A B

L

L

L

H

OUT Gate 1 (V)

Gate 1 (H/L)

Gate 2 (V)

Gate 2 (H/L)

Gate 3 (V)

Gate 3 (H/L)

Gate 4 (V)

Gate 4 (H/L)

Gate 5 (V)

Gate 5 (H/L)

Gate 6 (V)

Gate 6 (H/L)

H L H H


10

. Table 1.5 IN A

B

L

L

L

H

H

L

H

H

OUT Gate 1 (V)

Gate 1 (H/L)

Gate 2 (V)

Gate 2 (H/L)

Gate 3 (V)


Gate 4 (H/L)


Gate 4 (H/L)

Table 1.6

IN A

B

L

L

L

H

H

L

H

H

OUT Gate 1 (V)

Gate 1 (H/L)

Gate 2 (V)

Gate 2 (H/L)

Gate 3 (V)

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


11

Experiment No. 2

OBJECTIVE 

Construction of all Logic Gates by using universal gates, NAND gate and NOR gate. Verifying their results

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 




IC Type 7402 Quadruple 2-input NOR gates

THEORY A universal gate is a gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates. Both NAND and NOR gates can realize basic logic gates (AND, OR and NOT) logic circuits singlehandedly. Therefore, AOI logic can be converted to NAND logic or NOR logic.

CONNECTION DIAGRAM


12

Figure 2.1

PROCEDURE 1. Verify the gates. 2. Make the connections as per the circuit diagrams given in Figure 2.1 3. Switch on Vcc and apply various combinations of input according to the truth table for each circuit. 4. Note down the output readings for AOI logic using NAND and AOI logic using NOR.

RESULTS & CALCULATIONS Table 2.1

Inputs A

Outputs (Inverter) Y (using NAND gate)

Y (using NOR gate)

0 1


13

Table 2.2

Inputs A

Outputs (Buffer) Y (using NAND gate)

Y (using NOR gate)

0 1

Table 2.3

Inputs A

B

0

0

0

1

1

0

1

1

Outputs (AND Logic) Y (using NAND gate)

Y (using NOR gate)

Table 2.4

Inputs A

B

0

0

0

1

1

0

1

1

Outputs (OR Logic) Y (using NAND gate)

Y (using NOR gate)

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


14

Experiment No. 3

OBJECTIVE 

Design and implementation of HALF-ADDER, FULL-ADDER, 4-BIT Parallel Adder circuit

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 




IC Type 7486 Quadruple 2-input XOR gate



IC Type 7432 Quadruple 2-input OR gates

THEORY In digital circuit theory, combinational logic (sometimes also referred to as combinatorial logic) is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, sequential logic has memory while combinational logic does not. Arithmetic circuits are type of combinational circuits that performs arithmetic operations. Half adder adds two binary digits, giving a sum bit and a carry bit. A full adder is an arithmetic circuit that adds two bits and a carry and outputs a sum bit and a carry bit. A full adder is capable of adding two 1-bit binary numbers and a carry-in. when two n-bit binary numbers are to be added, the number of full-adders required will be equal to the number of bits n in each number. Of course, the addition of LSB’s can be done by using either a half -adder or a full adder with Cin terminal grounded. The carry-out of each full-adder is connected to the carryin of next higher order adder. In practical parallel adders, the least significant stage is also a fulladder to facilitate cascading.


15

CONNECTION DIAGRAM

Figure 3.1

Half Adder

Figure 3.2

Full Adder

Figure 3.3


4-Bit Parallel Adders

16

PROCEDURE 1. 2. 3. 4. 5.

Connect the RIMS Trainer to the 220V AC supply. Verify all gates of 74LS08, 74LS86 and 74LS32. For half adder make connections as shown in Figure 3.1 and complete table 3.1. For full adder make connections as shown in Figure 3.2 and complete table 3.2. Now first make a circuit diagram for 4-Bit parallel adder with help of block diagram given in figure 3.3 and then implement it.

RESULTS & CALCULATIONS Inputs A

B

0

0

0

1

1

0

1

1

Outputs SUM

CARRY

Table 3.1

Inputs

Outputs

A

B

Cin

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

SUM

Cout

Table 3.2


17

Application of ADDERs

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


18

Experiment No. 4

OBJECTIVE Design and implementation of HALF-SUBTRACTOR, FULL-SUBTRACTOR, 4-BIT Parallel SUBTRACTOR circuit



EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 










IC Type 7404 Hex Inverters

THEORY In digital circuit theory, combinational logic (sometimes also referred to as combinatorial logic) is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, sequential logic has memory while combinational logic does not. A half-subtractor is an arithmetic circuit that subtracts one bit from the other. It is used to subtract the LSB of the subtrahend from LSB of the minuend when one binary number is subtracted from the other. The half-subtractor can be used for LSB subtraction. If there is a borrow during the subtraction of the LSB’s, it affects the subtraction in the next higher column; the subtrahend bit is subtracted from the minuend bit, considering the borrow form that column used for the subtraction in the preceding column. Such a subtraction is performed by a full-subtractor.


19

CONNECTION DIAGRAM

Figure 4.1

Half Subtractor

Figure 4.2

Full Subtractor

Figure 4.3 4-Bit Parallel Subtractor


20

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS08, 74LS86, 74LS04 and 74LS32. 3. For Half Subtractor make connections as shown in Figure 4.1 and complete table 4.1. 4. For Full Subtractor make connections as shown in Figure 4.2 and complete table 4.2. 5. Now first make a circuit diagram for 4-Bit parallel subtractor with help of block diagram

given in figure 4.3 and then implement it.

RESULTS & CALCULATIONS Inputs A

B

0

0

0

1

1

0

1

1

Outputs Difference

Borrow

Table 4.1

Inputs

Outputs

A

B

0

0

Bin Difference 0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Borrow

Table 4.2


21

Experiment No. 5

OBJECTIVE 

Design and implementation of Gray to BCD converter

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 








THEORY The Gray Code belongs to a class of codes called minimum-change codes, in which only one bit in the code group changes when going from one step to the next. The gray code is unweighted code. Because of this, it is not suitable for arithmetic operations but finds applications in input/output devices and some types of analog-to-digital converters. The Gray Code is referred digital code with special property that two adjacent Gray code numbers differ by only one bit. This type of encoding is called a unit distance code. It is suited for encoding a physical parameter, such as a shaft position of a motor. As the shaft turns continuously from one position to the next, only one bit in the code changes and avoids any ambiguity and improper representation of the shaft position.


22

CONNECTION DIAGRAM

Figure 5.1 implementation of Gray to BCD converter


23

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS08, 74LS04 and 74LS32. 3. Implement the circuit as shown in Figure 5.1.

RESULTS & CALCULATIONS Decimal

Gray Code

BCD

A

B

C

D

W

X

Y

Z

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

1

2

0

0

1

1

0

0

1

0

3

0

0

1

0

0

0

1

1

4

0

1

1

0

0

1

0

0

5

0

1

1

1

0

1

0

1

6

0

1

0

1

0

1

1

0

7

0

1

0

0

0

1

1

1

8

1

1

0

0

1

0

0

0

9

1

1

0

1

1

0

0

1

Table 5.1

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


24

Experiment No. 6

OBJECTIVE 

To check the operation of 2-to-4 line Decoder and 3-to-8 line Decoder. Using the 74LS139 IC, design a Binary Code Decimal to the seven segment decoder.

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 







IC Type 7446/7447 BCD-to-Seven segment decoder/driver



Seven Segment Display

THEORY A decoder is a logic circuit that accepts a set of inputs that represents a binary number and activates only the output that corresponds to that input number. In other words, a decoder circuit looks at its inputs, determines which binary number is present there, and activates the one output that corresponds to that number; all other outputs remain inactive. Decoder can be referred to in several ways. For example 3-to-8 line decoder means that it has 3 input lines and 8 output lines. It can also be called binary-to-octal decoder or convertor because it takes a three bit binary input code and activates one of the eight (octal) outputs corresponding to that code. 7-segment display is used to display decimal characters 0 through 9 and sometimes the hex characters A through G.


25

Its is called as 7-segment display because it has 7 segments ( a to g ) which glow in different combinations to show decimal numbers from 0 to 9. Our task for this lab session is to design a circuit that takes BCD input and produces an output that makes only required segments to glow which could produce the display of exactly the same number whose BCD code has been given as input to the circuit. So it can be decided that the circuit will have 4 input lines and 7 output lines each being able to control one of the 7 segments of the display.

CONNECTION DIAGRAM

Figure 6.1 2-to-4 line decoder


26

Figure 6.2

3-to-8 line decoder

Figure 6.3: BCD-to-7 Segment Decoder Circuit


27

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS08 and 74LS04. 3. For 2-to-4 line decoder make connections as shown in figure 6.1 and verify table 6.1. 4. For 3-to-8 line decoder make connections as shown in figure 6.2 and verify table 6.2. 5. For BCD-to-7 Segment Decoder Circuit make connection as shown in figure 6.3 and verify table 6.3.

RESULTS & CALCULATIONS Inputs A B

Outputs D1 D2

D0

× 0 0

× 0 1

0 1 0

0 0 1

0 0 0

0 0 0

1 1

0 1

0 0

0 0

1 0

0 1

D3

Table 6.1

Inputs

Outputs

A 0 0 0 0

B 0 0 1 1

C 0 1 0 1

D0 1 0 0 0

D1 0 1 0 0

D2 0 0 1 0

D3 0 0 0 1

D4 0 0 0 0

D5 0 0 0 0

D6 0 0 0 0

D7 0 0 0 0

1 1 1 1

0 0 1 1

0 1 0 1

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

Table 6.2


28

Table 6.3: Truth Table for BCD to 7-Segment Decoder

Application using encoder decoder

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


29

Experiment No. 7

OBJECTIVE 

Designing Binary Code Decimal encoder, its understanding and its analysis.



Designing of octal to binary encoder and decimal to binary encoder .

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 


THEORY An encoder is a combinational circuit that performs the inverse operation of a decoder. If a device output code has fewer bits than the input code has, the device is usually called an encoder. e.g. 2 n-to-n, priority encoders. The simplest encoder is a 2 n-to-n binary encoder, where it has only one of 2 n inputs = 1 and the output is the n-bit binary number corresponding to the active input. Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-to-8 decoder does. At any one time, only one input line has a value of 1. For an 8-to-3 binary encoder with inputs D0-D7 the logic expressions of the outputs A0-A2. A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7 Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of what the 4to-10 decoder does. At any one time, only one input line has a value of 1. For 10-to-4 binary encoder with inputs D0-D9 the logic expressions of the outputs A0-A3 A3 = D8 + D9 A2 = D4 + D5 + D6 + D7 A1 = D2 + D3 + D6 + D7 A0 = D1 + D3 + D5 + D7 + D9


30

CONNECTION DIAGRAM

Figure 7.1 Equivalent Circuit of 4 input OR-Gate

Figure 7.2 Equivalent Circuit of 5 inputs OR-Gate

Figure 7.3 Octal to Binary Encoder


31

Figure 7.4 Decimal to BCD Encoder

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS32. 3. For octal to binary encoder make connections as shown in figure 7.3 and verify the table 7.1. 4. For decimal to BCD encoder make connections as shown in figure 7.4 and verify the table 7.2. 5. As 4 input OR gate is used in figure 7.1 so to make 4 input OR gate with the help of 2 input OR gate follow the figure7.1. 6. As 5 input OR gate is used in figure 7.2 so to make 5 input OR gate with the help of 2

input OR gate follow the figure 7.1.


32

RESULTS & CALCULATIONS Decimal Digit 0 1 2

D0 1 0 0

D1 0 1 0

D2 0 0 1

3 4 5 6 7

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

Input D3 D4 0 0 0 0 0 0 1 0 0 0 0

D5 0 0 0

D6 0 0 0

D7 0 0 0

A2 0 0 0

Output A1 0 0 1

A0 0 1 0

0 0 1 0 0

0 0 0 1 0

0 0 0 0 1

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

0 1 0 0 0 Table 7.1

Decimal Digit

Input

BCD Code (output)

0

D0 1

D1 0

D2 0

D3 0

D4 0

D5 0

D6 0

D7 0

D8 0

D9 0

A3 0

A2 0

A1 0

A0 0

1

0

1

0

0

0

0

0

0

0

0

0

0

0

1

2

0

0

1

0

0

0

0

0

0

0

0

0

1

0

3

0

0

0

1

0

0

0

0

0

0

0

0

1

1

4

0

0

0

0

1

0

0

0

0

0

0

1

0

0

5

0

0

0

0

0

1

0

0

0

0

0

1

0

1

6

0

0

0

0

0

0

1

0

0

0

0

1

1

0

7

0

0

0

0

0

0

0

1

0

0

0

1

1

1

8

0

0

0

0

0

0

0

0

1

0

1

0

0

0

9

0

0

0

0

0

0

0

0

0

1

1

0

0

1

Table 7.2

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


33

Experiment No. 8

OBJECTIVE 



Designing of 2-to-1, 4-to-1 line multiplexer and a quadruple 2-to-1 line multiplexer Also implement 1-to-4 line demultiplexer.

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 








THEORY Multiplex means “many into one”. Multiplexing is the process of transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer (MUX) or data selector is a combinational circuit that selects digital information from several sources (2n) lines and transmits information on a single output line. The multiplexer has several data-input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Demultiplex means one into many. Demultiplexing is the process of taking information from one input and transmitting the same over several outputs. A demultiplexer is a logic circuit that receives information on a single input and transmits the same information over several (2n) output lines. A demultiplexer is the opposite of a multiplexer in its operation. The functional diagram for a demultiplexer is shown below. The circuit has one input signal, m control signals and n output signals. The select input code determines to which output the DATA input will be transmitted. As the serial data is changed to parallel data, the multiplexer is also called a distributor or decoder.


34

Figure 8.1: Block diagrams of MUX and DMUX

CONNECTION DIAGRAM

Figure 8.2: 2- input multiplexer

Figure 8.3: 4-input multiplexer


35

Figure 8.4: 2-to-4 line Demultiplexer

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS08, 74LS08 and 74LS32. 3. For 2 input multiplexer connect the circuit as shown in figure 8.2 and verify table 8.1. 4. For 4-input multiplexer connect the circuit as shown in figure 8.3 and verify table 8.2. 5. For 2-to-4 line demultiplexer connect the circuit as shown in figure 8.4 and verify table 8.3.

RESULTS & CALCULATIONS .

S

Z

0

D0

1

D1

Table 8.1

S1

S0

Z

0

0

D0

0

1

D1

1

0

D2

1

1

D3

Table 8.2


36

Table 8.3: 2-to-4 demultiplexer

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


37

Experiment No. 9

OBJECTIVE 

Designing of 4-BIT Magnitude comparator and magnitude comparison using 74LS85 IC

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 

IC Type 74LS85 4-bit magnitude comparator










THEORY The basic function of a magnitude comparator is to compare the magnitudes of two quantities and determines the relationship of those quantities. The outcomes of the comparison is specified by three binary variables that indicate whether (two quantities A and B) A>B, A=B or A
CONNECTION DIAGRAM

Figure 9.1: 4-bit magnitude comparator


38

Figure 9.2:

1-bit magnitude comparator

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS08, 74LS86 and 74LS04. 3. For one bit comparator make connections as shown in figure 9.2 and verify the table. 4. For 4 bit comparator make connections as shown in figure 9.1 and verify the table.

RESULTS & CALCULATIONS

A3,B3 A3>B3 A3
Comparing Inputs A2,B2 A1,B1 × × × × A2>B2 ×

A3=B3 A3=B3 A3=B3

A2
× A1>B1 A1
× × ×

× × ×

× × ×

× × ×

L H L

H L H

L L L

A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3

A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2

A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1

A0>B0 A0
× × H L × H

× × L H × H

× × L L H L

H L H L L L

L H L H L L

L L L L H L

A3=B3

A2=B2

A1=B1

A0=B0

L

L

L

H

H

L

A0,B0 × × ×

Cascading Inputs A>B A
A>B H L H

Outputs A
Table 9.1


39

Experiment No. 10

OBJECTIVE 

Introduction, design and testing of Basic flip flop circuits – SC or SR, JK, D and T FF using NAND gate. Also with IC7476 and IC7474

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 




IC Type 7476 Dual J K- type flip-flops



IC Type 7474 Dual D-Type flip-flops

THEORY The circuits considered so far are examples of combinations circuits. The logic circuits whose output at any instant of time is entirely dependent upon the input signals present at that time are known as combinational circuits. In particular, the output of combinational circuits does not depend upon any past inputs or outputs so that circuits do not possess any memory. Flip flops are synchronous bistable devices. The term synchronous means that the output changes state only at a specified point on a triggering input called the clock (clk), which is designed as control input. An edge trigger flip-flopchanges state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock. As shown in figure below.


40

Types of Flip-Flop: Three types of edge-triggered flip-flops are 1. S-R FLIP-FLOP 2. D FLIP-FLOP 3. J-K FLIP-FLOP 4. T FLIP-FLOP In S-R flip-flop the S and R inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge of the clock pulse. The D flip-flop is useful when the signal bit data (1 or 0) is to be stored. The additional of an inverter to an S-R flip-flop creates a basic D flip-flop. D flip-flop has only one input, the D input, in addition to the clock. The J-K flip-flop is versatile and is perhaps the most widely used type of flip-flop. The functioning of the J-K flip-flop is identical to that of the S-R flip-flop in the SET, RESET and no change conditions of operation. The difference is that the J-K flip-flop has no invalid state. The T or toggle flip-flop changes its output on each clock edge.

CONNECTION DIAGRAM

Figure 10.1 SR flip flop


41

Figure 10.2

JK flip flop

Figure 10.3

D Flip flop

D flip-flop using 7476

T flip-flop using 7476

Figure 10.4


42

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates 74LS00. 3. For SR flip-flop make connections as shown in Figure 10.1 and verify table 10.1. 4. For JK flip-flop make connections as shown in Figure 10.2 and verify table 10.2. 5. For D flip-flop make connections as shown in Figure 10.3 and verify table 10.3. 6. For T flip-flop make connections as shown in Figure 10.4 and verify table 10.4. 7. Using IC7476 and check JK flip-flop. And then implement D and T flip-flop as shown in figure 10.4.

RESULTS & CALCULATIONS Inputs

Output

Comments

S

R

CLK

Q

Q’

0

0

↑

Q0

Q0 ’

0

1

↑

01

RESET

1

0

↑1

0

SET

1

1

↑?

?

Invalid

No change

Table 10.1

Inputs

Output

Comments

J

K

CLK

Q

Q’

0

0

↑

Q0

Q0 ’

0

1

↑

01

RESET

1

0

↑1

0

SET

1

1

↑

Q0 ’

Q0

No change

Toggle

Table 10.2

Inputs


Outputs

Comments

43

D

CLK

Q

Q’

1

↑

1

0

SET stores a 1

0

↑

0

1

RESET stores a 0

Table 10.3

INPUT

OUTPUTS

PRESET

CLEAR

CLOCK

J

K

Q

Q

0

0

×

×

×

1

1

0

1

×

×

×

1

0

1

0

×

×

×

1

1

↑ 0

0

0

Q

1

1

↑ 1

0

1

0

1

1

↑ 0

1

0

1

1

1

↑

1

TOGGLE

1

1

0

1

×

0

×

Q

1

Q

Table10.4 JK flip-flop using IC7476

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


44

Experiment No. 11

OBJECTIVE 

Designing of SISO, SIPO, PISO and PIPO shift register using D flip flop .

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 





THEORY A register capable of shifting its binary information either to the right or to the left is called a shift register. An n-bit shift register consists of n-FFs and the gates control the shift operation. Shift registers are used in a digital system for temporary information storage and data manipulation and transferring. SISO type of shift register accepts data serially that is, one bit at a time on a single line. It produces the stored information on its output also in serial form. SIPO is used in order to shift the data in parallel, it is necessary to have all the data available outputs at the same time. Once the data are stored, each bit appear on its respective output line and all bits are available simultaneously, rather on a bit-by-bit basis as with the serial output. PIPO type of register data can be shifted either into or out of the register in parallel. PISO shift register the data is entered simultaneously into the respective stages, but the data bits are transferred out of the register serially, i.e. is bit-by-bit basis over a single line.


45

CONNECTION DIAGRAM

Figure 11.1: Serial in serial out

F Figure 11.2: Serial in parallel out

Figure 11.3: Parallel in serial out


46

Figure 11.4: Parallel in parallel out

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates 74LS00. 3. For SISO make connections as shown in Figure 11.1. 4. For SIPO make connections as shown in Figure 11.2. 5. For PISO make connections as shown in Figure 11.3. 6. For PIPO make connections as shown in Figure 11.4.

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


47

Experiment No. 12

OBJECTIVE 

Designing of simple ring counter circuits and Johnson counter circuits

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 


THEORY Shift register can be arranged to form several types of counters. All shift-register counters use feedback, whereby the output of the last FF in the shift register is connected back to the first FF. The ring counter and Johnson counter are most widely used shift register counters. A ring counter is a circular shift register with only one FF being set at any particular time: all other are cleared. The FFs are connected so that information shifts from left to right and back around from Q0 to Q3. In most cases only a single 1 is in the register and it is made to circulate around the register as long as clock pulses are applied. For this reason it is called ring counter. The basic ring counter can be modified slightly to produce another type of shift-register counter, which will have somewhat different properties. The Johnson or twisted-ring counter is constructed exactly like a normal ring counter except that the inverted output of the last FF is connected to the input of the first FF.

CONNECTION DIAGRAM

Figure 12.1


Ring counter

48

Figure12. 2

Johnson counter

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. For Ring Counter make connections as shown in Figure 12.1. 3. For Johnson Counter make connections as shown in Figure 12.2.

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


49

Experiment No. 13

OBJECTIVE 

Introduction and Designing of synchronous Up and Down counter and its implementation of using J-K flip flop IC.

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 








THEORY A counting circuit is the simplest form of sequential circuit, which is most widely used in digital systems. Like all other sequential circuits, the counting circuits are composed of memory elements such as flip-flops and combinational elements such as logic gates. A counter, by function, is a sequential circuit consisting of a set of FFs that counts the number of input pulses it receives. There are two types of counters A synchronous counter is a synchronous or parallel sequential circuit. An asynchronous or ripple counter, as is sometimes called, is an asynchronous or serial sequential circuit. An up-down counter has capability of counting upwards as well as downwards. In an UP counter each flip-flop is triggered by the normal output of the preceding flip-flop; in a Down counter each flip-flop is triggered by the inverted output of the preceding flip-flop. In both the counters, the first flip-flop is triggered by the input pulses.

. Digital Logic Design Lab Manual

50

CONNECTION DIAGRAM

Figure 13.1: Up counter

Figure 13.2: Down counter


51

Figure 13.3: Up down counter

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS08 and 74LS32. 3. For UP counter make connections as shown in Figure 13.1. 4. For DOWN counter make connections as shown in Figure 13.2. 5. For UP-DOWN counter make connections as shown in Figure13.3.

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


52

Experiment No. 14

OBJECTIVE 

Analysis of Presetable counters.

EQUIPMENT 

ePAL Trainer Board



2 resisters 1K ohm



Connecting wires

COMPONENTs 











THEORY Many synchronous (parallel) counters that are available as ICs are designed to be presettable: in other words, they can be preset to any desired starting count either asynchronously (independent of the clock signal) or synchronously (on the active transition of the clock signal). This presenting operation is also referred to as parallel loading the counter.

PROCEDURE 1. Connect the RIMS Trainer to the 220V AC supply. 2. Verify all gates of 74LS08, 74LS00and 74LS04. 3. For Presettable parallel counter with asynchronous preset make connections as shown in Figure 14.1

.


53

CONNECTION DIAGRAM

Figure14.1

Presettable parallel counter with asynchronous preset

CONCLUSION 1. ------------------------------------------------------------------------------------------2. ------------------------------------------------------------------------------------------3. --------------------------------------------------------------------------------------------


54

Digital Logic Design Lab Manual

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