Nagpu gpurr Institut Insti tutee of Techn Technolo ology, gy, Na Nagpu gpur r Depa epartment rtment of Compu omputer ter Science & Engineering Engineering Question Question Bank with Solutions
Digital Circu Circuits its & Fundamentals Fundamentals of Micro Processor (III Sem-CSE) Compiled By Ms. Shit Shital al Tiwaskar Email:
[email protected]
Question Bank Bank :: DCFM III Sem CSE Q.1) Perform the following conversions. I] (110101.011) binary = (?) decimal Solutions: = 1 × 2 5 + 1 × 2 4 + 0 × 2 3 + 1 × 2 2 + 0 × 2 1 + 1 × 2 0 + 0 × 2 −1 + 1 × 2 −2 + 1 × 2 −3 + 1 × 2 −4 Ans: (53.4375 )decimal
⎛
a] ⎜ (15 . 73 ⎜
⎝
)×
2 .5
22 7
⎞ ⎟ O = (? ) D ⎟ ⎠
Solutions:
Ans:
(15.73) octal
= 1 × 81 + 5 × 8 0 + 7 × 8 −1 + 3 × 8 −2 = (13.92136) decimal
(22) octal
= 2 × 81 + 2 × 8 0 = (18) decimal
(7) octal
=7 × 80 = (7) decimal
(2.5)octal
= 2 × 8 0 + 5 × 8 −1 =(2.653)decimal
(
⎛ ⎜ 13 . 92136 × 18 ⎜ 7 ⎝
(
b] 110
÷ (2 A ) DC
)
2 . 653
H
)
⎞ ⎟ ⎟ ⎠ decimal
= (?)
D
Solutions: (110)H = (1 × 16
2
+ 1 × 16
+ 0 × 16
1
= (272) decimal (2A) H = (2 × 16 1 + A × 16
0
= (42)D (DC)H = ( D × 16 1 + C × 16 = (220)D Ans:
[(272 ) × (42) ] 220
decimal
Nagpur Institute of of Technology, Technology, Nagpur
) 0
)
0
)
Question Bank Bank :: DCFM III Sem CSE Q.1) Perform the following conversions. I] (110101.011) binary = (?) decimal Solutions: = 1 × 2 5 + 1 × 2 4 + 0 × 2 3 + 1 × 2 2 + 0 × 2 1 + 1 × 2 0 + 0 × 2 −1 + 1 × 2 −2 + 1 × 2 −3 + 1 × 2 −4 Ans: (53.4375 )decimal
⎛
a] ⎜ (15 . 73 ⎜
⎝
)×
2 .5
22 7
⎞ ⎟ O = (? ) D ⎟ ⎠
Solutions:
Ans:
(15.73) octal
= 1 × 81 + 5 × 8 0 + 7 × 8 −1 + 3 × 8 −2 = (13.92136) decimal
(22) octal
= 2 × 81 + 2 × 8 0 = (18) decimal
(7) octal
=7 × 80 = (7) decimal
(2.5)octal
= 2 × 8 0 + 5 × 8 −1 =(2.653)decimal
(
⎛ ⎜ 13 . 92136 × 18 ⎜ 7 ⎝
(
b] 110
÷ (2 A ) DC
)
2 . 653
H
)
⎞ ⎟ ⎟ ⎠ decimal
= (?)
D
Solutions: (110)H = (1 × 16
2
+ 1 × 16
+ 0 × 16
1
= (272) decimal (2A) H = (2 × 16 1 + A × 16
0
= (42)D (DC)H = ( D × 16 1 + C × 16 = (220)D Ans:
[(272 ) × (42) ] 220
decimal
Nagpur Institute of of Technology, Technology, Nagpur
) 0
)
0
)
Question Bank Bank :: DCFM III Sem CSE IV] (243.62) D = (?) octal Solutions: Decimal no
÷ ÷ ÷ ÷
243 30 3
Base (8)
=
Quotient
Remainder
8 8
= =
30 3
3
8
=
0
3
6
Ans: (363.4753)O
c]
(9310 .25 )10 = (? ) H
Solutions:
÷ ÷ ÷ ÷ ÷
Decimal no
9310 581 36 2
=
Quotient
16 16
=
581
14
=
36
5
16
=
2
4
16
=
0
2
×
Decimal no
Base (8)
×
0.25
16
Ans: (245 E . 4 ) H
VI] (273 . 45 )O = (? ) H Solutions:
( )O = ( ) B = ( ) H
(273.45) = (0
10 11
1011
.
Ans: (0 BB.94) H
d] (10110111) gray = (?)B Solutions: Nagpur Institute of of Technology, Technology, Nagpur
1001
Remainder
Base (8)
01)
=
Quotient result
=
4.0
Question Bank Bank :: DCFM III Sem CSE 1
0
1
1
0
1
1
1
1
0
1
0
0
1
0
1
Decimal no
0.62 0.96 0.68 0.44
× × × × ×
Base (8)
8 8 8 8
=
Quotient result
= = = =
4.96 7.68 5.44 3.52
Ans: (10100101) B e) i] BCD Additions:
(256.2) D + (743.9 ) D Solutions: 0 0 1 0 0 1 0 1 0 1 1 0 . 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 . 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 . 1 0 1 1 (invalid BCD) 0 0 0 0 0 0 0 0 0 0 0 0 . 0 1 1
0
1 0 0 1 1 0 0 1 1 0 1 0 . 0 0 0 1 (invalid BCD) 0 0 0 0 0 0 0 0 0 1 1 0 . 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 . 0 0 0 1 (invalid BCD) 0 0 0 0 0 1 1 0 0 0 0 0 . 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 . 0 0 0 1 (invalid BCD) 0 1 1 0 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 1 (Valid BCD) Ans: (10001.1)
Nagpur Institute of of Technology, Technology, Nagpur
Question Bank : DCFM III Sem CSE f] BCD Subtraction (76.53)D – (59.27)D Solutions:
0 1 1 1 0 1 1 0 . 0 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 . 0 0 1 0 0 1 1 1 0 0 0 1 1 1 0 1 . 0 0 1 0 1 1 0 0 (invalid BCD) 0 0 0 0 0 1 1 0 . 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 . 0 0 1 0 0 1 1 0 (valid BCD)
Ans: (17.26)decimal g] (253) D – (315) D Solutions:
(253)D + (315)D (?)D (253)D = (128 + 64 + 32 + 16 + 8 + 4 + 1) =(11111101)B (315)D= 256 + 32 + 16 + 8 + 2 +1 =(100111011)B (+253) (+315)
0 0
011111101 100111011
1’s Compliment of (315)D = ( 1 0 1 1 0 0 0 1 0 0 ) +
1
2’s Compliment of (315)D = ( 1 0 1 1 0 0 0 1 0 1 )B = (-315)D (+253)D + (-315)D =
0 1
011111101 011000101
1
111000010
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Verification:- (z)=
1
111000010
1’s Compliment =
0
000111101 +
0
1
000111110
h] Excess 3 Code Additions i] (956.2) D + (873.4)D (?)D Solutions: 1100 1000 1001 . 1010 1011 1010 0110 . 0111 1 00 0 0 01 0 1 11 1. 11 00 0 01 1 0 01 1 0 0 11 0 0 11 .0 01 1 0 10 0 1 01 1 1 1 01 .1 1 00 1 00 1 1
8
2
.
9
i] Excess 3 code Subtractions (47.59)D (28.38)D (?)D Solutions:
0111 1010 . 1000 1100 0101 1011 . 0110 1011 0001 1111 . 0010 0001 0011 0011 . 0011
0011
0000 0000 . 1111 0100
Nagpur Institute of Technology, Nagpur
6
Question Bank : DCFM III Sem CSE Q.2) a] Why NAND gate and NOR gates are called universal gates? Answer: all the logical ckt. are made by using basic 3 logic gates OR, AND, NOT gates, by using only NAND gate . We can design these 3 basic gates OR, AND, NOT gates. Hence any logical ckt. can be completely by using only NAND gate. So NAND gate is called UNIVERSAL gate. Similarly, OR, AND, NOT gate can be designed by using only NOR gats, so a ny logical ckt. can be completely designed by using only NOR gates. Hence NOR gate is also universal gate. (a) NAND gate as universal gate: 1] Not gate using NAND gate. Input
Y = A . A = A
NOT gate is obtained by shorting by both the input of NAND gate as shown in fig. 2] AND gate using NAND gate:
AND gate is opposite of NAND gate. S o, AND gate is Obtained by Connecting NOT at the output of NAND gate as shown in fig. 3] OR gate using NAND gate:
st
The output of NOR gate is Y = A + B = A + B = A . B [de-morgan’s 1 thermo then]………….. (1) The logical ckt. og eg.(1) can be obtained by using NAND gate. OR, AND, NOT gate are designed by using only NAND gate. So, NAND gate is Universal. (a) NOR gate as universal gate: 1] NOT gate using NOR gate:
Y = A + A = A i/p NOT gate is obtained from NOR gate by shorting both inputs as shown in fig. 2] OR gate using NOR gate:
OR gate is opposite of NOR gate. So, gate is obtained by connecting NOT gate at the output of NOR gate as shown in Fig. 3] AND gate using NOR gate:
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE
The output of 2 input AND gate is Y = A. B = A + B [De- morgans 2nd theorem]…………..(2) The logical ckt. of eg.(2) can be obtained by using NOR gate as shown in fig.
Q.2) b] Prove that: A . B + A . B + A . B = A + B L . H . S = A . B + A . B + A . B
= [( A . B + A . B )] + [( A . B + A . B )] = [ A .( B + B )] + [( A + A ). B ] = ( A . 1 ) + ( B . 1) = A + B = R . H . S . 2) X Y Z + XYZ + XY Z + XYZ = 1 L . H .S = X Y Z + XYZ + XY Z + XYZ
= ( XYZ + XYZ ) + Y Z ( X + X ) = 1 + Y Z ∴ [ XYZ + XYZ = 1]∴ A + A = 1 = 1[∴ 1 PLUSANYTHI NG = 1] = R . H .S Q.2 ) c] State principal of duality. Answer: Principal of duality is used for writing dual equations or for designing dual ckt. for a given local equations, replace each term on L.H.S. and R.H.S. by the corresponding dual terms. The equations obtained will be dual equation of the given equations. Similarly, if any logical ckt. is given then replace each gate by corresponding dual gate. The logical ckt.obtained will be dual of the given ckt. In dual logical ckt. the output will be dual of each other. The different dual terms and dual gates are given in the table below,
0
1
OR gate
AND gate
+
.
NOR gate
NAND gate
X-OR gate
X-NOR gate
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE (+)
(.) st
nd
De-morgans 1 theorem
Demorgans 2
Product term(.)
Sum term (+)
SOP equations
POS equations
theorem
Q.2) d] Prove that De-morgans theorem. Answer: DEMORGANS FIRST THEROM: st The logical equations of De-morgans 1 theorem for two input is, Y = A + B = A . B ……..(1)
Similarly for 3 inputs is, Y = A + B + C = A . B .C ……………(2)
STATEMENT: De-morgans first theorem state that complement of ORing will be equal to the ANDing of complements. PROOF: De-morgans first theorem can be proved by using truth table. Truth table:
Inputs
A
B
(A+B)
( A + B )
A . B
(L.H.S)
(R.H.S)
A
B
0
0
1
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
st
As L.H.S. =R.H.S. of equations (1) hence 1 theorem is proved that. The logical Ckt. of L.H.S. and R.H.S. is shown in fig. below.
= Y = A + B
NOR gate L.H.S
A + B = A . B
=
Bubbled input AND gate R.H.S
DE-MORGANS SECOND THEROM: The logical equations of De-morgans 2nd theorem for two input is, Y = A . B = A + B ……..(3)
Similarly for 3 inputs is, Y = A . B .C = A + B + C ……..(4)
STATEMENT: De-morgans second theorem state that complement of ANDing will be equal to the ORing of complements. PROOF: De-morgans second theorem can be proved by using truth table.
Nagpur Institute of Technology, Nagpur
Qu stion Bank : DCF
III Sem CSE
Truth ta le:
In uts
(A. )
A
( A.B )
A + B + C
(L.H.S)
(R.H.S)
A
B
0
0
1
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
nd
As L.H.S. =R.H. . of equatio s (3) hence 2 theorem is proved th t. The logical Ckt. f L.H.S. an R.H.S. is shown in fig. below.
= Y = A . B
A . B =
NAND gate L.H.S
=
+ B
Bubbled input OR gate R. .S
Q.3 ] design a quaring ckt. Which will generate sq are of the 3 bit no. applied at the i/p ? Solu tion: as i/ is a 3 bits so the max imum vale be (ABC) (111) = (7 ) B i n a r y He n e the maxi mum value of o/p will be,
7* 7
(49) = 32 16+1 (1 1 0001) Binary As o /p is of 6 b its so we h ave to desi n a logical ckt. In whiich i/p will be of 3 bits and o/p wiill be of 6 bits as given in the truth t ble. Inputs A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Dec. no. X 0 1 2 3 4 5 6 7
Output X2 0 1 4 9 16 25 36 49
Binary output Y5 Y4 Y3 Y2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0
Y0 0 1 0 1 0 1 0 1
If a logical ckt is designed using k m p then we will get onl y one bit o utput. Henc e for obtai ing o/p of 6 bi s, we have to design l ogical ckt. or each o/ p bit separ tely. Desi gn for Y5 A A A
BC
B C
BC
0
BC
0 m0
0
0 m1
m3
0 m4
B
2 1
m5
m7
Nag ur Institute of Technology, Nagpur
6
Y 5 = A . B
Question Bank : DCFM III Sem CSE Design for Y4 A
BC
A
BC
B C
BC
B C
0
0
0
0
m0 1
m1 1
m3 1
m2 0
m4
m5
m7
m6
Y 4 = A B
A
+ AC
Design for Y3 A
BC
BC
B C
BC
B C
A
0 mo
0 m1
1 m3
0 m4
A
0 m5
1 m6
0 m7
0 m6
B C
BC
Y 3 = A BC + A B C
Design for Y2 A
BC
BC
B C
A
0 mo
0 m1
0 m3
1 m4
A
0 m5
0 m6
0 m7
1 m6
Y 2 = B C
Design for Y1 A
BC
BC
B C
BC
B C
A
0 mo
0 m1
0 m3
0 m4
A
0 m5
0 m6
0 m7
0 m6
Y 1 = 0
Design for Y0 A
A
A
BC
BC
B C
BC
B C
0 mo
1 m1
1 m3
0 m4
0 m5
1 m6
1 m7
0 m6
Nagpur Institute of Technology, Nagpur
Y 0 = C
Qu stion Bank : DCF
III Sem CSE
Logical ckt.
Obtaining from e . (1) to (6) a d it is show in the fig. b low. A
A
B
C
C
5
Y4
Y3S
2 1 Gnd.
0
Gnd.
Nag ur Institute of Technology, Nagpur
Qu stion Bank : DCF
III Sem CSE
Q.3. b] Design Code Co verter Wh ich Will C onvert 3 B its Binary 0. Applie s at the In ut into equi valent Gr y Code. Solu tions: The i/p ill be 3 bi t binary no. ABC . so, the o/p gra y code will also be of 3 bits i.e., 2 G1 G0 . INPUT
esign for G
OUT UT
A
0
B
C
G2
G1
G0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
0
1
0
0
0
1
1
0
A
0
1
1
1
1
A
1
0
1
0
1
1
1
1
0
0
A
BC
0 mo 0 m4
A
BC
BC
BC
0 mo 1 m5
B C
0 m1 1 m6
BC
0 m3 1 m7
Logical Ckt:
Nag ur Institute of Technology, Nagpur
BC
1 m1 1 m
0 m3 0 m7
B C
1 m2 1 m6
G 0 = B C +
C
B C
B C
0 o
0 m1
1 m3
1 m2
1 4
1 m5
0 m7
0 m6
B
0 4 1 6
BC
BC
Desi n for G2 A
B C
esign for G A
1
BC
G 2 A
G1 = A B + A B
Qu stion Bank : DCF
III Sem CSE
Q.3 C] Design a NAND g te ckt. To convert 3 Solu tions : IN UT GRAY CODE G2 G1
UTPUT BINARY NU
0
B2
it gray co de into eq ivalent 3
BER
B1 B0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
1
1
0
1
0
0
1
1
1
Desi n for B2 A
BC
B C
BC
B C
A
o
0 m1
0 m3
0 m4
A
5
1 m6
1 m7
1 m6
BC
B 2 = A
Desi n for G1 A
B
BC
B C
BC
B C
A
0 mo
0 m1
1 m3
1 m2
A
1 m
1 m5
0 m7
0 m6
1 = A B + B
Desi n for G0 A
A
A
BC
BC
0 mo 1 m4
BC
B
1 5
0 m3 1 m7
Logical Ckt:
Nag ur Institute of Technology, Nagpur
B C
1 m2 0 m6
B0 = ABC + A BC + A C + ABC
it binary
umbers.
Question Bank : DCFM III Sem CSE Q.3 d] Design a NAND gate ckt. To detect illegal or invalid BCD number applied at the input. Solutions: if 4 bit number ABCD applied at the input is valid BCD(0000 to 1001)then output Y should be zero. If input ABCD is invalid BCD (1010 to 1111) then output should be 1. Truth Table: Inputs Output Symbol of Output A B C D Y
Valid BCD
Invalid BCD
0
0
0
0
0
m0
0
0
0
1
0
m1
0
0
1
0
0
m2
0
0
1
1
0
m3
0
1
0
0
0
m4
0
1
0
1
0
m5
0
1
1
0
0
m6
0
1
1
1
0
m7
1
0
0
0
0
m8
1
0
0
1
0
m9
1
0
1
0
1
m1 0
1
0
1
1
1
m1 1
1
1
0
0
1
m1 2
1
1
0
1
1
m1 3
1
1
1
0
1
m1 4
1
1
1
1
1
m1 5
Design k-map : AB
C D
CD
0 mo
0 m1
0 m3
0 m2
0 m4
0 m5
0 m7
0 m6
AB
1 m12
1 m13
1 m15
1 m14
A B
0 m8
0 m9
1 m11
1 m10
AB
A B
CD
CD
C D
Y = AC + AB
Nagpur Institute of Technology, Nagpur
Qu stion Bank : DCF
III Sem CSE
Logical Ckt: A
B
C
D
Y = AC + AB
Q.3. E] Design a code co verter whi ch convert 4 bit BCD input nu ber into c rresponding X-S3 cod . Solu tions : The truth table showing de cimal digit , BCD num ber input a d required X-S3 code given belo w. BC D Input
Deci mal digit
X- S3 output
0
A 0
C 0
D 0
Y3 Y 2 0 0
Y1 Y0 1 1
1
0
0
1
0
1
0
0
2
0
1
0
0
1
0
1
3
0
1
1
0
1
1
0
4
0
0
0
0
1
1
1
5 0 0 1 1 0 0 0 As 4 bit input ill be BCD 0num er from 00 00 to 110010 , heance 6 1 0 0 1 re set o 7
0
1
1
1
0
1
0
8
1
0
0
1
0
1
1
9
1
0
1
1
1
0
0
f the , 4 bit nu ber from 1 010 to 111 1 will not b e applied a t the input. So have to take the corr esponding utput bits. m 10 to m 15= X(don’ t care). Desi n k-map fo Y3: AB AB
A B AB A B
CD
CD
C D
CD
0 m0 0 m4 X m12 1 m8
0 m1 1 m5 X m13 1 m9
0 3 1 7
Nag ur Institute of Technology, Nagpur
m15 m11
C D
0 m 1 m X m14 X m10
Y 3 = A + BD + B
Question Bank : DCFM III Sem CSE Design k-map for Y2: AB
CD
CD
C D
CD
C D
AB
0 m0
1 m1
1 m3
1 m2
A B
1 m4
0 m5
0 m7
0 m6
AB
m12
X m13
X m15
X m14
A B
0 m8
1 m9
X m11
X m10
Y 2 = B CD + B D + B C
Design k-map for Y1: AB
CD
CD
1 m0 1 m4 X m12 1 m8
AB
A B
AB A B
C D
0 m1 0 m5 X m13 0 m9
CD
1 m3 1 m7 X m15 X m11
C D
0 m2 0 m6 X m14 X m10
Y 1 = CD + CD
Design k-map for Y0: AB
CD
CD
C D
CD
C D
1 m0
0 m1
0 m3
1 m2
1 m4
0 m5
0 m7
1 m6
AB
X m12
X m13
X m15
X m14
A B
1 m8
0 m9
X m11
X m10
AB
A B
Nagpur Institute of Technology, Nagpur
Y 0 = D
Qu stion Bank : DCF
III Sem CSE
Logical Ckt:
Q.3 F] Design in p t. Solu tion :
AND gat ckt. To o tain 9’s c mpliment of the 4 bi BCD num ber applie
Input BC number
1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
m10 TO m15= (DON’T
Deci al dig it
D 0 1 0 1 0 1 0 1 0 1 ARE)
Nag ur Institute of Technology, Nagpur
X 0 1 2 3 4 5 6 7 8 9
co
9’s pliment
9-X 9 8 7 6 5 4 3 2 1 0
9’s co
Y3 1 1 0 0 0 0 0 0 0 0
pliment o utput
Y2 0 0 1 1 1 1 0 0 0 0
Y1 0 0 1 1 0 0 1 1 0 0
Y0 1 0 1 0 1 0 1 0 1 0
at the
Question Bank : DCFM III Sem CSE Design k-map for Y3: AB
CD
AB
A B
AB A B
CD
1 m0 0 m4 X m1 2 0 m8
C D
CD
C D
1 m1 0 m5 X m1 3 0 m9
0 m3 0 m7 X m1 5 X m1 1
0 m2 0 m6 X m1 4 X m1 0
Y 3 = ABC
Design k-map for Y2: AB
CD
CD
C D
CD
C D
AB
0 m0
0 m1
1 m3
1 m2
A B
1 m4 X m1 2 0 m8
1 m5 X m1 3 0 m9
0 m7 X m1 5 X m1 1
0 m6 X m1 4 X m1 0
AB A B
Design k-map for Y1: AB
AB A B
AB A B
CD
CD
0 m0 0 m4 X m1 2 0 m8
C D
CD
C D
0 m1 0 m5 X m1 3 0 m9
1 m3 1 m7 X m1 5 X m1 1
1 m2 1 m6 X m1 4 X m1 0
Y 1 = C
Design k-map for Y0: AB
AB
A B
AB A B
CD
CD
1 m0 1 m4 X m1 2 1 m8
C D
0 m1 0 m5 X m1 3 0 m9
CD
0 m3 0 m7 X m1 5 X m1 1
Nagpur Institute of Technology, Nagpur
C D
1 m2 1 m6 X m1 4 X m1 0
Y 0 = D
Y 2 = B C + B C
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III Sem CSE
Logical Ckt:
Q.3 G] Design NAND gat ckt. For he functio
f=
∑m(0 ,1,5,9,12 )
d(3,7,11, 5)
Solu tions: AB
CD
CD
D
AB
1 m0
1 1
X m3
0 m2
A B
0 m4
1 5
X m7
0 m6
AB
1 m12
0 13
X m15
0 m14
A B
0 m8
1 9
X m11
0 m10
CD
Nag ur Institute of Technology, Nagpur
C D
F = AB C D + ABC + B D + A D
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Logical Ckt:
Q.3 h] Design
AND gat ckt. For t he functio
f=
∑m(1 2,7,9,15 )
d(0,8,12) design NA D ckt.
For the functi n f’. Solu tions: th e functions “ ” is opposi te of “f’”. ence logic zero of fu ction. “f w ill be logic input in “f”. But don’t c ares will r main unch nged. Hen e f’= (3,4, 5,6,10,11,1 3,14) + d(0 ,8,12) k-m p for funct ions f is, Desi n k-map: AB AB
A B
AB A B
CD
CD
X m0 1 m4 X m12 X m8
D
0 m1 1 m5 1 m13 0 m9
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CD
1 3 0 7 0 m15 1 m11
C D
0 m2 1 m6 1 m14 1 m1
f = B D + B C + A BC + BCD
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Logical Ckt:
Q.3 i] Design
multiplie
ckt. whic
will mult iply 2 num ber A1A0* B1B0
Solu tions: The maximum value of in ut 2 bit nu mber will b e A1A0 = ( 11)B =(3) =B1B0. H nce the ma x imum valu of output result will e (A1A0)* (B1B0)=3* 3=9=(1001 )B. So we h ave to desi gn the ckt for bit output . i put A1 A 0 B1 B0 (A) (B ) (C) (D) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Decimal result (A1A0) *(B1B0) 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3
* * * * * * * * * * * * * * * *
0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
= = = = = = = = = = = = = = = =
0 0 0 0 0 1 2 3 0 2 4 6 0 3 6 9
Binary re ult Y3 Y2 Y 1Y0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0
0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1
m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
Question Bank : DCFM III Sem CSE Design k-map for Y3: AB
CD
CD
C D
CD
C D
0 m1 0 m5 0 m13 0 m9
0 m3 0 m7 1 m15 0 m11
0 m2 0 m6 0 m14 0 m10
C D
CD
C D
0 m1 0 m5 0 m13 0 m9
0 m3 0 m7 0 m15 1 m11
0 m2 0 m6 1 m14 1 m10
C D
CD
C D
0 m1 0 m5 1 m13 1 m9
0 m3 1 m7 0 m15 1 m11
0 m2 1 m6 1 m14 0 m10
CD
C D
CD
C D
0 m0
0 m1
0 m3
0 m2
A B
0 m4
1 m5
1 m7
0 m6
AB
0 m12
1 m13
1 m15
0 m14
0 m8
0 m9
0 m11
0 m10
0 m0 0 m4 0 m12 0 m8
AB
A B AB A B
Y 3 = ABCD
Design k-map for Y2: AB
CD
CD
0 m0 0 m4 0 m12 0 m8
AB
A B AB A B
Y 2 = AC D + A B C
Design k-map for Y1: AB
CD
AB
A B AB A B
CD
0 m0 0 m4 0 m12 0 m8
Design k-map for Y3: AB CD AB
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Y 1 = A B D + AC D + BC D + A BC
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Y 3 = BD
Logical Ckt:
Q.4 a] Design and explai n of two bi t compara tor. Solu tions: Co parator is a device out ut result. ( a) One bit for A < B ( b) One bit for A > B ( c) One bit for A = B
hich will c ompare th e given tw
COMPA ATOR
The truth tabl showing wo single com parator is given belo ,
it number A and B a nd the cor responding output of
2 i/p n mber
Usi g two inpu ts K-map
B
0
utput
A
B
A < B
A = B
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
we have t
Desi n k-map fo (A < B) A . B
ber and g ives 3 bit
A < B A > B A=
One bit c mparator
DES IGN OF S INGLE BI
input nu
B
1
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> B
design th ree differe nt ckt. For 3 bit outp ut .
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0
III Sem CSE 0
A ( A < B ) = A B
Desi n k-map fo (A = B) A . B
A
A
B
1 0
B
0 1
( A
= B ) = AB
( A
> B ) = A B
AB
Desi n k-map fo (A > B) A . B
A
A
B
0 1
B
0 0
Logical Ckt:
Q . 4 b] Design
nd explai
of two bi comparat o r.
Solu tions: T wo bit compa rator is use to compa e two num ers of two bits each. Lets first numb er A=A1 A and secon d number =B1B0. If th e first two bit number is A=A1 A 0 and the s cond bit n mber B=B 1 B0,then t he MSB’s 1,B1are appl ied first on e bit comp rator and L SB’s A0,B 0 are appli d to secon one bit co mparator. he cond itions for t hree bit ou put of com parator are given belo w. A < B :(A1
B :(A1>B1 )OR [(A1= 1) AND ( 0>B0)] S o , A>B) = (A 1>B1) + [( 1=B1). (A 0>B0)]… ………. (3 ) T wo bit compa ator using one bit com parator is btaining fr om equatio ns 1,2,3 an d it is show n in below,
A1 < B1 One bit Nag ur Institute of of Technolog Technolog y, Nagpur compar tor
A0 < B 0 One bit co parator
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A1
A A1=B1
A0 = B 0
B1
B A1>B1
2 i/p A0 (B ) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 (A) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
umber B1 (C) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 > B 0
B0 (D ) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A
O u tput A =B
A>B
0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
Desi n k-map fo (A < B) AB
CD
CD
C D
CD
C D
AB
0 m0
1 m1
1 m3
1 2
A B
0 m4
0 m5
1 m7
1 6
AB
0 m12
0 m13
0 15
0 14
A B
0 m8
0 m9
1 11
0 10
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( A < B ) = AC + AB D + BC
Question Bank Bank :: DCFM III Sem CSE
Design k-map for (A=B) AB
CD
CD
1 m0 0 m4 0 m12 0 m8
AB
A B AB
A B
C D
0 m1 1 m5 0 m13 0 m9
CD
0 m3 0 m7 1 m15 0 m11
C D
0 m2 0 m6 0 m14 1 m10
( A = B) = ABCD + A BC D + ABCD + A BC D
Design k-map for (A > B) AB AB
A B AB
A B
CD
CD
0 m0 1 m4 1 m12 1 m8
C D
0 m1 0 m5 1 m13 1 m9
Logical Ckt:
Nagpur Institute of of Technology, Technology, Nagpur
CD
0 m3 0 m7 0 m15 0 m11
C D
0 m2 0 m6 1 m14 0 m10
( A > B) = AC + BCD + AB D
Question Bank Bank :: DCFM III Sem CSE
Nagpur Institute of of Technology, Technology, Nagpur
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Q.5] what is a parity generat r? Explain he diagram even and odd parity generator. Solu ions: In ”n” bits data, the count of nu ber of one’s bit is called s parity. If t e count of n mber of once bit in “n” bit d ta is odd no. then it is called odd parit data.X-OR gate is used to detect the parity of “n” its data. (a) If the parity of input d ta of X-OR ate is alway zero. (b) If the parity of input d ta of X-OR ate is odd th en output of _OR gate is always zero. (1)the truth table howing 3 bit input number X-OR gate, then parity f input data nd the corre ponding out ut of X-OR gate is given belo w. Add all the input it’s and write the sum ne lecting the carry for 3 I/P X-or gate.
A
Input number B
C
0
0
0
0 0
0 1
1 0
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
X-O gate O /P
Parity of output I/P ven
1 1
dd dd ven
1
dd ven ven
1
dd
Pari y generator
Parit generator i used to gen rate “n” bits no. of a particular parity. here are tw types of parity generator. ( )Even parit generator ( )Odd parit generator (a)
ven parity generator:
Even parity generator iis used to generate even p rity number. The 8 bit nu ber D7 to D0 is applied t the i/p of even parity gener tor. The parity generator enerates one parity bit D . So, the output number of even parity generator will e of 9 bits ( p and D7 to D0) .The pa ity of this 9 its output wi ll be always ven. 1] If the parity of 8 bit input nu mber D7 to 0 is already even parity it output willl be always e en output d ta will remain even. 2] If the parity of 8 bit input d ta (D7 to D0 odd then parity bit Dp=1 . So parity o 9 bits output data will be ome even.
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(b)Odd parity generator:
Odd parity generator is used to generate odd parity number. The 8 bit number D7 to D0 is appli d at the input odd parity generator. The pa ity genaerat r generates one parity bit Dp. Hence the output pari ty generator
ill be of 9 b its. (Dp and
D7 t D0). The p rity of this 9 bits output will be always odd. (1) If the parity of inp t number D7 to D0 is already odd then parity bit D =0, So, the parity of 9 bit’ s output will remain odd. (2) If the parity of 8 bit input numb r D7 to D0 i s even then parity bit Dp=1. So the parity of 9 bits o utput will become odd.
Q.6] Explain cla sification of logic famili s and properties of logic families. Solu ions: Depending upon th main comp nents which are used to f abricate logic gate. Logic gates familie are divided
into ollowing typ es. (1)RTL [resistance transistor logic] famil :
The logic gates of RT family are
ade by usin resistance and transistor as main com onents.
(2)DTL [diode transistor logic] family:
The main components of DTL family gates are diodes and transistors. (3)T L [transist r transistor logic] famil :
The logic gates of TT family are obtained from logic gates o f DTL famil by replacin diodes with transistors. (4)
CL [emitter couple logic] family:
The logic gates of EC family are (5)C
ade emitter oupled transistor as main components.
OSEFET (complemen ary MOSE ET) logic:
The logic gates of CMOSFET logic family are channel and one “n” channel
OSFET.
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ade by using complementary pair of MOSFET i.e., one P
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Pro erties or ch racteristics of logic families (1)PROPOGATION DELAY TI
I/P A
E [TD OR
P]:
O/ Y
The ime differen e between the install at which i/p is applied and the installed at
hich o/p is obtained is callled as
prop gation delay time: if propagation time is less then l gic gates is ast and vice versa the pro agation delay time is measured betwee the instant t which 50% of the i/p signal is applie (a) and the instant at which 50% of th o/p signals obtained (b). (2)POW R DISSIPATION (PD):
The ower that is obtained in one gate is called ad power dissipation er gate. If power dissipati on per gate is less then logic gate is bette and vice ve sa. (3)PRODUCT OF T
OR PD
For etter logic g tes the value of propagation delay tim as well as p wer dissipation should be small be. B t in some logic gates Td is small and Pd is large and vice versa. So for selecting logic gates, he product o propagation delay time (td) nd power di sipation(Pd)iis obtained. The logic family in which t his products (td * pd) is minimum is the family and vice versa. (4) FAN N
The
aximum number of o/p f gates whic can be connected to a single i/p of on gate is called as FAN IN. if FAN IN
is m re than logic gates is bett r and vice v rsa.
(5) FAN
The
UT
aximum number of inputs of other gates which ca be connected to output of one gate is alled as FA
FAN OUT is mor than logic ates is better and vice ver a. Nag ur Institute of Technology, Nagpur
OUT. If
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(6) NOISE MARGIN
In logic gates, the gates input nd output signals are in the form of voltage which i denoted by llogic 1. If noiise voltage is supe imposed on o/p voltage of logic gates hen the valu of o/p volta ge will chan e. The maxi um value o noise voltage which can be superposed on o/p because of which the o/p logic remains unchanged is c lled ad noise voltage margin. Q. 9 a] Explain alf adder Ckt. Solu ions: a logi ckt. Which performs additions of onl two binary its is called as half adder. The two bin ary bit A and B ar applies ti th input of Haft Adder. HA performs th addition (A B and gives 2 bit o/p res lt. A (a) One bit f r sum (S) an Half Adder (b) One bit f r carry gene ated (Co). ( A+B
The Truth
Co able of hal adder:
Input (A + B) A 0 0 1 1
B 0 1 0 1
The llogical ckt. o half adder can be design d using K-Map: Desi n for Sum( ): A
B
A
B 1
m0
A
m1 0
m2
m3 S = A B + A B
Nag ur Institute of Technology, Nagpur
Su S 0 1 1 0
S Ca ry Co 0 0 0 1
Question Bank : DCFM III Sem CSE Design for Carry (Co): A
B
A
B
0
B 0
m0
A
0
Co = AB
m1 1
m2
m3
Logical Circuit A
B S = A B + A B
Co = AB
Q. 9] b] Explain Full Adder Ckt. Solutions: when we perform additions of two multibit number then we have to perfume additions of 3 bits. A logical ckt. Which is used to perform additions of 3 binary bits is called as full adder. The 3 binary bits A, B, C in applied of the i/p of Full adder. So, gives 2 bit output result. (1) One bit for sum(A + B + Cin) (2) One bit for carry out(Co.) A B Full Adder (A +B + Cin)
Co The truth able for full adder ckt. Inputs (A + B + Cin) A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Design K Map For Full Adder Ckt.
Nagpur Institute of Technology, Nagpur
Cin 0 1 0 1 0 1 0 1
Sum So 0 1 1 0 1 0 0 1
Cin
S Carry Co 0 0 0 1 0 1 1 1
Question Bank : DCFM III Sem CSE Design for Sum(S): A
BC
A
0
BC 1
0
m0 1
BC
BC
1
m1 0
m3 1
m4
BC m2
A
0
m5
m7
m6
S = A BC + A BC + A BC + ABC Design for Sum(S): A
BC
A
0
BC 0
1
m0 0
BC
BC m1 1
0 m3
1
m4
m5
BC m2
A
1 m7
m6
Co = AC + AB + BC
The logical ckt of full adder
Q. 9] c] Explain Half Subtractor Ckt. Solutions: A logic ckt. Which performs Subtractions of only two binary bits is called as half Subtractor. The two binary bit (A – B). Is called as Half Subtractor A B (a) One bit for Difference (D) and (b) One bit for Borrow Required to perfume the subtraction Half (A-B) i.e., borrow out (Bo). Subtractor The truth table of half Subtractor: ( A B) Input (A - B) A B
Difference D
Borrow Bo
0 0 1
0 1 0
0 1 1
0 1 0
1
1
0
0
The logical ckt. of half Subtractor can be designed using K-Map:
Nagpur Institute of Technology, Nagpur
Bo
D
Question Bank : DCFM III Sem CSE Design for Difference (D): A
B
B
A
0
B 1
m0
A
1
m1 0
m2
m3
D = A B + A B Design for Borrow (Bo): A
B
B
A
0
B 1
m0
A
0
m1 0
m2
m3
Co = A B A
A
B
D = A B + A B Bo = A B
Q. 9] d] Explain Full Subtractor Ckt. Solutions: when we perform Subtractions of two multibit number then we have to perfume Subtractions of 3 bits. A logical ckt. Which is used to perform Subtractions of 3 binary bits is called as full Subtractor. The 3 binary bits A, B, C in applied of the i/p of Full Subtracto. So, gives 2 bit output result. (1) One bit for Difference(A - B - Cin) (2) One bit for Borrow out(Bo.) A B Full Subtractor (A B Cin)
The truth able for full Subtracto ckt. Inputs (A - B - Cin) A B Cin 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1
Difference D 0 1 1 0 1 0
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Bo Borrow Bo 0 1 1 1 0 0
D
Cin
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1 1 0 1 1 1 Desi n K Map For Full Adder Ckt. Desi n for Sum( ): A
BC
B
A
0 1
0 1
BC 1
BC 0
m0
1
m1
m3
0
1
m4
BC m2
A
0
m5
m7
m6
D
A BC + A BC + A BC + BC
Desi n for Borrow(Bo): A
BC
B
A
BC
BC
1 m0
1
m4
1
m1 0
BC
m3 1
m2
A
0
m5
m7
m6
Bo = AC + A B + BC Logical Ckt. of Full S btractor A B CS
Difference
Borrow
Q. 1 ] Explain i parallel binary adder. Solu ions: A3 B3 A2
Full Adder 3
C3
Full
S3
C
B2
dder
S2
A1
B1
Full Ad er 1
C1
S1
A0
B
Full Adder 0
C0
S0
The bloc diagram of bits parallel binary adde is shown in figure; it is used to perfor number without carry
additions o f two 4 bit
If A3 A2 A1 A0 and B3 B2 B1 B0 re two 4 bit number then parallel bina y adder perf rms the additions as give below,
Nag ur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Carry generated st
1 number 2
nd
number
Result
C3
C2
C1
CO
A3
A2
A1
A0
B3
B2
B1
BO
S3
S2
S1
S0
FA2
FA1
FA3
FA0
The 4 bit parallel binary adder performs the additions of two 4 bit number and given 5 bit result of additions. To performs additions of two C1 bit number with carry. We have to replace half adder HA0 by Full adder FA0. Q.11] explain parallel binary subtractor. Solutions: A3 B3 A2 B2
Full Subtractor 3
B3
A1
Full Subtractor 2
D3
B2
B1
A0
Full Subtractor
Full Subtractor 1
D2
B1
B0
0
D1
B0
Do
The block diagram of 4 bits parallel binary Subtractor is shown in figure; it is used to perform subtractions of two 4 bit numbers. If A3 A2 A1 A0 and B3 B2 B1 B0 are two 4 bit number then parallel binary Subtractor performs the Subtractions as given below,
FA3
FA2
FA1
FA0
A3
A2
A1
A0
B3
B2
B1
BO
Borrow Required
B’2
B’1
B’0
Result
D3
D2
D1
st
1 number 2
nd
number
D0
B’3 If the last borrow B’3=1 then it indicates that the result is –ve represented in 2’s compliment from. If the last borrow B’3=0 then it indicates that result is either zero or +ve. This 4 bit parallel binary subtractor performs subtractions of two 4 bit number without borrows. To performs subtractions of two 4 bit numbers with borrow, we have to replace half subtractor HDo by full Subtractor FSo.
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Q. 1 ] design an explain 1’s compliment ckt or controlled invert rs. Solu ions: 3
B2
B1
Bo I Control Input
Y3
Y2
Y1
Y0
The llogical ckt of 4 bit controlled inverter i shown in fi . Operations: (1) B3 B2 B1 Bo is 4 bit umber applied at the in ut .if contr l input “I” is made zero then in X-OR gate; 0 (+) B = B. Henc th 4 bit outpu will be Y3 Y2 Y Yo = B3 B2 B1 Bo i.e., output = in ut. (2) If control input “I” is made 1, then in X-OR gate, 1 (+) B = B Hence th 4 bit output will be, Y3 Y2 Y Yo = B3 B B1 Bo That is; utput = 1’s ompliment of input. If lo ic 1 is added to this 1’s c mpliment th n we will get 2’s compli ent of B3 B B1 Bo and it will repres nt its –ve valu i.e. (-B3 B2 B1 Bo)
Q. 1 ] Design an explain parallel arithmetic unit or lement. Solu ions:
A3
B I
A2
2
A1
B1
Ao
Bo
I/O Control I/P
A3
Y3
B3 Full A der 3
C3
S3
A2 C2
B2 Full Add r 2
C2
S2
Nag ur Institute of Technology, Nagpur
Y2 C1
A1 B1 Full Adder 1
C1
S1
Y1 Co
Ao Bo F ll Adder 0
C o
So
Yo I/O
Question Bank : DCFM III Sem CSE The bloc diagram of 4 bit parallel arithmetic unit is shown in fig. it can additions as well as subtractions using 2’s compliment method. OPERATIONS: (1)Additions operations: The two 4 bit binary numbers A3 A2 A1 Ao and B3 B2 B1 Bo are applied at the i/p and control input is made zero. So output of X-OR gate will be Y3 Y2 Y1 Yo = B3 B2 B1 Bo. Hence 4 bit parallel binary adder performs the following additions. Carry generated C2 C1 CO st
1 number 2nd number
A3
A2
A1
Ao
B3
B2
B1
Bo
Controlled i/p Result
0 C3
S3 FA3
S2
S1
FA2
S0
FA1
FAo
(2)Subtraction operations: To perfoms the subtraction A3 A2 A1 Ao minus (-) B3 B2 B1 Bo the two number applied at the i/p and control i/p “I” is made. So, output of X-OR gate will be 1’s compliment of the input that is; Y3 Y2 Y1 Yo = B3 B 2 B1 Bo Hence the 4 bit parallel binary adder performs the following additions. Carry generated C2 C1 CO st
1 number
A3
A2
A1
Ao
2nd number Controlled i/p
B3
B2
B1
Bo
Result
(2’s compliment)
0 C3
S3
S2
S1
S0
FA3 FA2 FA1 If the last carry C3 is neglected then we will get 4 bit result of subtractions i.e., S3, S2, S1, So.
FAo
Q.14] Design and explain BCD ADDER or 8421 ADDER or SINGLE DIGIT DECIMAL ADDER. Solutions: the block diagram of 4 bit or single adder is shown in fig.(1) OPERATIONS: (1) If A3 A2 A1 Ao and B3 B2 B1 Bo are two 4 bit BCD number, then using FA’s. FAo to FA3. These two BCD number are added with carry (Cin). To performs additions without carry Cin is made zero. The additions of BCD number with carry is perfomed as given below,
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Qu stion Bank : DCF
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3
B3
A2
Full Adder 3
C3
2
A1
Full Ad er 2
3
C2
B1
Ao
Full Adder
Full Adder 1
S2
1
S1
B
Co
So
Y Cout (Ca ry Out)
Full Adder 3
C’3 (2)
Full Adder 1
Full Ad er 2
Z3
’2
Z2
C’1
Z
Zo
he logical ckt to detect 4 LSB’s of result S3 S2 S1 So for invali BCD can d signing usin g K-map as given below.
s3s 2
s1so s1so
s3s 2
0
0 m0
0
s3s2
0
1
0
1
0
s 3s 2
m7
m13
m6 1
m15 1
m9
m2 0
1
0 m8
0 m3
m5
m12
1so
0 m1
m4
s 3s 2
s1so
s1so
m14 1
m11
m10
s 2s3.s3s1
Y
If 4 SB’s of result S3 S2 S1 So is greater than 9 (invali BCD)OR l st carry C3=1then we have to add 6(0110)to the 4 LSB’s of result S S2 S1 So . the logical ck . To check t ese two con itions is obt ined using th e equations. Y= (S3 S2 S1 S0) + (C3)…… …….(1) This logical ckt. f eq. (1) can be designed using AND- R gate or N ND-NAND gate. (3) Using HAo,
A1,FA4 ,(0 Y Y 0)number is added t the 4 LSB’s of result S3 S2 S1 So, as given below.
Car y generated 4 LSB’S of Result Number 0YY0 ( ) Cor ect BCD result
Nag ur Institute of Technology, Nagpur
HA1
FA4
C’2
C’1
H o
S3
S2
S1
S0
Y
Y
Y
0
Z3
Z2
Z1
Z0
Question Bank : DCFM III Sem CSE If 4 LSB’s of result is greater than, 9 or last carry C3=1 then Y= 1. So, 0 Y Y 0=0 1 1 0=6. Hence 6 is added to the 4 LSB’s of result S3 S2 S1 S0 and the final result obtained Z3 Z2 Z1 Z0 is correct BCD result, the last carry out will be equal to “Y”. Q.15] Obtain using MUX the logical ckt. For the SOP eq. Y = A B + AC + ABC Solutions: the standard form of given eq. is;
Y = A BC + A BC + A BC + ABC + ABC ………………… (1) The given SOP equations can be expressed. F=
∑ m (2, 3, 4, 6, 7)………………….. (2) +ve D0 D1 D2 D3
8 to 1
D4
MUX
Output Y
D5 D6 D7 0 ve A
B C Control Inputs
Q. 15) B] using 8 to 1 MUX implement the eq. Y = ABC + ABD + AC . Assume ABD as control inputs. Solutions:
Y = ABCD + ABC D + ABCD + ABC D + ABC + A BC Y = ABCD + ABC D + ABCD + ABC D + ABC D + ABC D + A BC D + A BC D (0 0 1 1, 0 0 1 0 , 1 1 1 1 , 1 1 0 1 ,
1100,1001,1000)
INPUTS A
B
D
C
Y
SYMBOL OF O/P
0
0
0
0
0
m0
0
0
0
1
0
m1
0
0
1
0
1
m2
0
0
1
1
1
m3
0
1
0
0
0
m4
0
1
0
1
0
m5
Nagpur Institute of Technology, Nagpur
OUTPUT
RELATION OF Y&C
Y=0=Do
Y=1=D1
Y=0=D2
Question Bank : DCFM III Sem CSE 0
1
1
0
0
m6
0
1
1
1
0
m7
1
0
0
0
1
m8
1
0
0
1
1
m9
1
0
1
0
0
m10
1
0
1
1
0
m11
1
1
0
0
1
m12
1
1
0
1
1
m13
1
1
1
0
0
m14
1
1
1
1
1
m15
Y=0=D3
Y=1=D4
Y=0=D5
Y=1=D6
Y=B=D7
+ 5ve Do D1 D2 D3
8 TO 1
D4
MUX
D5 D6 D7
0 ve
Nagpur Institute of Technology, Nagpur
C
A
B
D
Qu stion Bank : DCF
III Sem CSE
Q.15) E] Obtain 8 to 1 MUX Using 4 to 1 MUX. Solu ions: (1) We have o use 2 Ic’s f 4 to 1 MU . (2) One IC o 2 to 1 MUX.
Do D1
4 TO 1
D2
MUX
Y1
D3 B
Y
C
Y
2:1 MUX
Output Y
D4 D5
4 O1
D6
Y2
A
UX
D7
Q. 1 ) f] implem nt the functions f =
∑ m(1,2,5,7) using 1:8 DE MUX having low level a tive output.
Solu ions: As output DE-MUX is low le el active, h nce in De-MUX , instea of AND ga e NAND gate is used. So the corr sponding o tput of De=MUX will b connected o NAND ga e instead of OR gate, th t is we get ANDNA D gate ckt. Y0
Y1
Di
1 TO 8
Y4
EMUX
Y5 Y6 Y7
Nag ur Institute of Technology, Nagpur
Output F
Qu stion Bank : DCF
III Sem CSE
Q.15) G] Design Full Adder sing DE-M ltiplexer. Solu ions: Full adder will perf orms additio of 3 bit bin ry bits as given in the truth table. Inp t A +
Outp t
B + C
Sum(S)
C rry (Co)
0 0
0 0
0 1
0 1
0 0
m0 m1
0
1
0
1
0
m2
0
1
1
0
1
m3
1
0
0
1
0
m4
1
0
1
0
1
m5
1
1
0
0
1
m6
1
1
1
1
1
m7
For sum m1 = m = m4 = m7 1 So we have to connect Y1, Y2, Y4, Y7 outp ut of De-Mux. For carry out m3 m5 = m6 = m7 = 1. So, e have to c nnect Y3, Y , Y6, Y7 ou put of De-Mux.
Yo Y1
Di
1 TO 8
Y2
De‐Mu
Y3
Sum
Y4 Y5 Y6
Carry
Y7
A
B
Q.16) A] implement the func ion f =
C
∏ m (1, 2 , 4 , 6 ) using decoder having low level active
utput.
Solu ions: as out ut of decoder’s low level active, hence the decoder consist of N ND gates. So, instead of OR gate we have to connect NAND hate. In th given function; m1 = m2 = m4 = m6 = 0 So.m0 = m3 = m5 = m7 = 1 So we have to correct the o/p’s Y0, Y3, Y5, Y7 of decoder to NAND gate.
Nag ur Institute of Technology, Nagpur
Qu stion Bank : DCF
III Sem CSE Y Y 3 to 8
Y
ecoder
Y
Input Di
output f
Y Y Y Y 7
Q.16) B] design f ull Subtract r using dec der. Solu ions: Truth T ble Input
Outp t
A -
B - C
Diff rence(D)
Borrow (Bo)
0 0
0 0
0 1
0 1
0 1
m0 m1
0
1
0
1
1
m2
0
1
1
0
1
m3
1
0
0
1
0
m4
1
0
1
0
0
m5
1
1
0
0
0
m6
1
1
1
1
1
m7
Yo Y1 3 to 8
Y
Decoder
Y3
Borrow
Y Y
Input Di
Y Y
Nag ur Institute of Technology, Nagpur
Differenc
Question Bank : DCFM III Sem CSE Q. 18) A] Explain BCD to 7 Segment Decode. Solutions: (a) Segment display: 7 segment display consist of LED’s “a to g” in the form of segment . these 7 segments are physically arranged like decimal digit 8. There is one circular LED for a decimal point (dp).these 8 LED’s are connected either in common cathode configuration (Fig 2)or in common anode configuration (fig3) in fig(2) by giving logic 1/0 to the anode. LED can be made on/off resp. similarly in fig (3) by giving logic 0/1 to the cathode LED can be made on/off resp. a
a f
b ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ c
b 0 ve (Common cathode connection) Fig(2)
e
c
+5 ve
d (Common anode connection) Fig(3) (b) Design of BCD to 7 segment decode: When 4 bit no is applied to the input of decoder then decoder will give corresponding will give corresponding 7 bit output Ya to Yg, if these 7 bits are applied to the 7 Led’s a to g of 7 segment display then the decimal digit corresponding to the BCD input is displayed on 7 segment display. If 7 segment display is connected in common cathode configuration then to make the LED on/off , decode will give logic input to the anode it LED.
Ya A
Yb
B
BCD
Yc
C
to
Yd
D
7 segment
Ye
Decoder
Yf Yg
(Physical structure)
Nagpur Institute of Technology, Nagpur
(7 segment display in common cathode configuration)
Question Bank : DCFM III Sem CSE
The truth table showing BCD input and the required output of decoder for displaying equivalent decimal digit to given below. A
Input B C
0
0
0
7 segment output Yb Yc Yd Ye
D
Equation Decimal Digit
Ya
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
0
2
1
1
0
0
1
1
3
1
0
1
0
0
4
0
1
0
1
0
1
1
0
1
1 1
Yf
Yg
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
5
1
0
1
1
0
1
1
0
6
1
0
1
1
1
1
1
1
1
7
1
1
1
0
0
0
0
0
0
0
8
1
1
1
1
1
1
1
0
0
1
9
1
1
1
1
0
1
1
The logical ckt. Of decoder can be designed using K-Map,DRAW 4 INPUT K- MAP AB CD
C D
CD
C D
CD
AB
m0
m1
m3
m2
m4
m5
m7
m6
m12
m13
m15
m14
m8
m9
m11
m10
A B AB A B
As inputs BCD, So, m10 to m15=X (Don’t care); Design for Ya AB CD CD
C D
AB
0
A B AB A B
1 0 X 1
CD
C D
1
1
1
1
1
X
X
X
1
X
Nagpur Institute of Technology, Nagpur
X
Ya = A + C + BD + BD
Question Bank : DCFM III Sem CSE Design K-Map Yb
AB CD CD AB
CD
C D
C D
1
1
1
1
A B
1
0
1
0
AB
X
X
X
X
A B
1
X
X
X
Yb = CD + CD + B
Design K-Map for Yc: AB CD CD
AB
C D
CD
C D
1
1
1
0
A B
1
1
1
1
AB
X
X
X
X
A B
1
1
X
X
Yc = C + D + B Design K-Map for Yd: AB CD CD
AB
A B AB A B
1 0 X 1
C D
0
CD
C D
1
1
1
0
1
X
X
1
X
X X
Yd = C D + A + BC + BC D + BD
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Design for Ye:
AB CD CD AB
C D
CD
C D
1
0
0
1
A B
0
0
0
1
AB
X
X
X
A B
1
0
X
X X
Ye = BD + C D
Design for Yf:
AB CD CD AB
CD
C D
C D 0
1
0
0
1
1
0
1
A B
X
X
X
X
AB
1
1
X
X
A B Yf = A + BC + CD + B D
Design for Yg:
AB CD CD AB
CD
C D
C D
0
0
1
1
1
1
0
1
A B
X
X
X
X
AB
1
1
1
X
A B Yg = A + B D + C D + BC
Nagpur Institute of Technology, Nagpur
Qu stion Bank : DCF
III Sem CSE
Q.1 ) b] Expla in binary t o 7 segme t decoder. Solu tions:
Ya A
Yb
B
BCD
Yc
C
to
Yd
D
7 segment
Ye
Decoder
Yf Yg
(Ph sical structure)
(7 seg ent display iin common cathode configuration)
When 4 bit binary no. is applie d of the inpu of decoder, then decoder will gate cor responding 7 bits output a to Yg. If these 7 bits are applied to the anode of 7 LED’s “a to g” hen the hexadecimal digi correspondi g to the bin ry input is displayed on 7 se ment displa .the table showing 4 bit inary input and the required output of ecoder for displaying equi alent hexadecimal digit i given below.
Nag ur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE
A
Input B C
0
0
0
7 segment output Yb Yc Yd Ye
D
Equation Decimal Digit
Ya
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
0
2
1
1
0
0
1
1
3
1
0
1
0
0
4
0
1
0
1
0
1
1
0
1
1
Yf
Yg
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
5
1
0
1
1
0
1
1
0
6
1
0
1
1
1
1
1
1
1
7
1
1
1
0
0
0
0
0
0
0
8
1
1
1
1
1
1
1
1
0
0
1
9
1
1
1
1
0
1
1
1
0
1
0
10(A)
1
1
1
0
1
1
1
1
0
1
1
11(B)
0
0
1
1
1
1
1
1
1
0
0
12(C)
1
0
0
1
1
1
1
1
1
0
1
13(D)
0
1
1
1
1
0
1
1
1
1
0
14(E)
1
0
0
1
1
1
1
1
1
1
1
15(F)
1
0
0
0
1
1
1
Design for Ya AB
AB A B AB
A B
CD
CD
C D
1
0
0 1 1
CD
C D
1
1
1
1
1
0
1
1
0
Nagpur Institute of Technology, Nagpur
1 1
Ya = BD + AC + BC + A D + A B + A BD
Question Bank : DCFM III Sem CSE
Design K-Map Yb
AB CD CD AB
C D
CD
C D
1
1
1
1
A B
1
0
1
0
AB
0
1
0
0
A B
1
1
0
1
Yb = AB + ACD + ACD + BD + AC D
Design K-Map for Yc:
AB CD CD AB
CD
C D
C D
1
1
1
0
A B
1
1
1
1
AB
0
1
0
0
A B
1
1
1
1
Yc = AC + A D + A B + A B + C D
Design K-Map for Yd
AB CD CD AB
C D
CD
C D
1
0
1
1
A B
0
1
0
1
AB
1
1
0
1
A B
1
1
1
0
Nagpur Institute of Technology, Nagpur
Yd = BCD + AC + BC D + BCD + BC D + AC D
Question Bank : DCFM III Sem CSE
Design for Ye
AB CD CD
C D
CD
C D
1
0
0
1
A B
0
0
0
1
AB
1
1
1
1
1
0
1
1
C D
CD
1
0
0
0
A B
1
1
0
1
AB
1
0
1
1
1
1
1
1
AB
A B
Ye = BD + AB + AC + C D
Design for Yf
AB CD CD AB
A B
C D
Yf = CD + A B + A B + A B + BC D
Design for Yg
AB CD CD AB
A B
AB A B
0 1
C D
CD
C D
0
1
1
1
0
1
0
1
1
1
1 1
1 1
Yg = BC + C D + A B + AD + A BC
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Logical Ckt.
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Q.23) Conversions: Solutions: Excitations Table of different Flip Flop. Previous O/P Qn 0 0 1 1
Next Required O/P Qn+1 0 1 0 1
J 0 1 X X
K X X 1 0
Inputs to Flip/ Flop S R D 0 X 0 1 0 1 0 1 0 X 0 1
1) Convert J-K Flip Flop into S-R Flip Flops. Solutions: Flip Flop available=> J-K Flip Flop. Flip Flop => S-R Flip Flop. Inputs S R 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Truth table
Next Required O/P Qn+1 0 1 0 0 1 1 X X
Qn 0 1 0 1 0 1 0 1
Inputs to Flip/ Flop Available J K 0 X X 0 0 X X 1 1 X X 0 X X X X Excitation Table
Design for J
Pr S
S S
RQn RQ
RQ
RQ
R Q
0
X
X
0
1
X
X
X
J = S
J
Q
K
Q
Clr
Nagpur Institute of Technology, Nagpur
T 0 1 1 0
Question Bank : DCFM III Sem CSE Design for K S
RQn RQ
S S
RQ
RQ
R Q
X
0
1
X
X
0
X
X
K = R 2) Convert S-R Flip Flop into J-K Flip Flops. Solutions: Flip Flop available=> S-R Flip Flop. Flip Flop => J-K Flip Flop. Inputs J K 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Truth table
Next Required O/P Qn+1 0 1 0 0 1 1 1 0
Qn 0 1 0 1 0 1 0 1
Design for S J
KQn
J
KQ
0
J
1
KQ
K Q
K Q
X
0
0
X
0
1
S = JQ Design for K J
J J
KQn
K Q
KQ
X
0
1
X
0
0
1
0
KQ
R = KQ
Nagpur Institute of Technology, Nagpur
K Q
Inputs to Flip/ Flop Available S R 0 X X 0 0 X 0 1 1 0 X 0 1 0 0 1 Excitation Table
Question Bank : DCFM III Sem CSE Logical Circuit
3) Convert S-R Flip Flop into D Flip Flops. Solutions: Flip Flop available=> S-R Flip Flop. Flip Flop => J-K Flip Flop.
D 0 0 1 1
Inputs Qn 0 1 0 1
Next Required O/P Qn+1 0 0 1 1
Design for S D
Q
Q
Q
0 D
0
1
D
X
S = D
Design for R D
D
Q
Q
Q
X
1
0
0
D
R = D
Nagpur Institute of Technology, Nagpur
Inputs to Flip/ Flop Available S R 0 X 0 1 1 0 X 0 Excitation table
Question Bank : DCFM III Sem CSE Logical Ckt.
4) Convert T Flip Flop into S-R Flip Flops. Solutions: Flip Flop available=> T Flip Flop. Flip Flop Required => S-R Flip Flop. Inputs S 0 0 0 0 1 1 1 1 Truth table
Next Required O/P Qn+1
R 0 0 1 1 0 0 1 1
Qn 0 1 0 1 0 1 0 1
0 1 0 0 1 1 1 0
Design for T RQn RQ
S
S S
0 1
RQ
RQ
0
1
0
X
T = RQ + S Q
Nagpur Institute of Technology, Nagpur
R Q
0 X
Inputs to Flip Flop Available T 0 0 0 1 1 0 X X Excitation Table
Question Bank : DCFM III Sem CSE
5) Convert T Flip Flop into D Flip Flops. Solutions: Flip Flop available=> D Flip Flop. Flip Flop Required => T Flip Flop. Inputs D 0 0 1 1
Qn 0 1 0 1
Design for T D
Q
Q
D
0
D
1
Q
1 0
T = DQ + DQ
Nagpur Institute of Technology, Nagpur
Next Required O/P Qn+1
0 0 1 1
Inputs to Flip Flop Available T 0 1 1 0
Question Bank : DCFM III Sem CSE Logical Circuit.
6) Convert D Flip Flop into J-K Flip Flops. Flip Flop available=> D Flip Flop. Solutions: Flip Flop Required => J-K Flip Flop. Inputs J K 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Truth table
Next Required O/P Qn+1 Qn 0 1 0 1 0 1 0 1
Design for D J
J
J
KQn
KQ
K Q
KQ
K Q
0
1
1
0
0
1
1
0
D = Q
Nagpur Institute of Technology, Nagpur
0 1 0 0 1 1 1 0
Inputs to Flip Flop Available D 0 1 0 1 0 1 0 1 excitation table
Question Bank : DCFM III Sem CSE Logical Circuit:
7) Convert D Flip Flop into T Flip Flops. Flip Flop available=> D Flip Flop. Solutions: Flip Flop Required => T Flip Flop. Inputs T 0 0 1 1
Qn 0 1 0 1
Design for D T
Q
Q
0 T T
1
Q
1 0
D = T Q + T Q Logical Circuit
Nagpur Institute of Technology, Nagpur
Next Required O/P Qn+1
0 1 1 0
Inputs to Flip Flop Available D 0 1 1 0
Question Bank : DCFM III Sem CSE Q. 24) Explain various types of shift register. Solutions: “n bits are read together then it is called parallel output.” So, depending upon the type of input and output, shift register are divides into following types. A) SERIAL INPUT SERIAL OUTPUT (SISO) SHIFT REGISTER. B) SERIAL INPUT PARALLEL OUTPUT (SIPO) SHIFT REGISTER. C) PARALLEL INPUT SERIAL OUTPUT (PISO) SHIFT REGISTER. D) PARALLEL INPUT PARALLEL OUTPUT (PIPO) SHIFT REGISTER. A) SERIAL INPUT SERIAL OUTPUT (SISO) SHIFT REGISTER:
4 bit SISO Serial I/P
Shift
Serial O/P
Register
The logical ckt. Of 4 bits SISO shift register using D-type flip flop is shown in Fig. (1) and using S-R/ J-K Flip Flop is shown in fig. (2). Operations: (1) Initially Clr =0 So, Q3 Q2 Q1 Q0=0 0 0 0. During the operations Clr =1. (2) If ABCD=1011 is 4 bit number to br stored in 4 bit register , then initially MSB A=1 is applied at serial input Do. After +ve edge of point clk cycle , as Do=1 . So, Qo become ⊥ . nd (3) As Qo=1, so, D1=1. Hence after +ve edge if 2 clk cycle Q1=1 and so on. (4) Finally after 4 clk cycles. 4 bit number ABCD=1011 is stored in the 4 flip flops i.e., Q3 Q2 Q1 Q0=1011 (5) As input binary bit applied as well as output binary bt read is serial hence it is called SISO shift register. B) SERIAL INPUT PARALLEL OUTPUT (SIPO) SHIFT REGISTER:
4 bit SIPO Serial I/P
Q3 Q2
Shift Register
Q1
Parallel O/P
Qo
The logical ckt. of 4 bit serial input parallel O/P shift register is shown in fig.(1). Operations: (1) Initially Clr=0 So, Q3 Q2 Q1 Q0=0 0 0 0. During the operations Clr=1. (2) If ABCD=1011 is 4 bit number to br stored in 4 bit register , then initially MSB A=1 is applied at serial input Do. So, Do = A = 1. Hence after +ve edge of 1st clk cycle, Q0 = A= 1.
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE (3) As Qo =A= 1, So, D1= A=1and the next bit B=0 is applied at serial input Do. Hence sfter +ve edge of 2 nd clk cycle, Q1 = A= 1 and Qo =B= 0. In this way the binary bit goes on shifting from one flip flop to another towards right and finally in 4 clk cycles, the 4 bit number is stored I the register i.e., Q3 Q2 Q1 Qo = A B C D = 1 0 1 1. (4) All these 4 bits are read together in parallel. As input is serial and output is parallel, so, it is called SIPO shift register.
C) PARALLEL INPUT SERIAL OUTPUT (PISO) SHIFT REGISTER.
Do Parallel I/P
4 bit PISO
D1 D2 D3
Serial I/P
Shift Register
The logical ckt. Of 4 bit PISO shift register is shown in fig.(1). Operations:
(1) Initially Clr=0 . So, Q3 Q2 Q1 Qo= 0 0 0 0, during the operation clr=1. (2) If ABCD is 4 bit number to be stored then these 4 bits are applied to the corresponding 4 parallel input pins x and control signal I is made zero(0). When I=0 the And gates number ”0” are enabled, AND gates number 1 are disables. So, the inputs ABCD are applied through gates 0, 2 ti the inputs of flip flop i.e., D3 D2 D1 Do= A B C st
D, at the positive edge if 1 clk cycle, all these 4 bits are stored in the 4 flip flop i.e., Q3 Q2 Q1 Qo= A B C D. (3) As output is serial hence for obtaining serial output at Q3, we have to performs shift operations. the control input I is made 1. So, AND gates number 0 are disabled, And gats number 1 are enabled. Hence the output of one flip flop gets connected to the input of next flip flop through gates 1, @ i.e., D3=q2. D2=Q1, D1= Q0. At +ve edge of each clk cycle the binary data goes on shifting from one flip flop to another towards right and we get serial output at Q3.
D) PARALLEL INPUT PARALLEL OUTPUT (PIPO) SHIFT REGISTER. D1
4 bit PIPO
D2 D3 D4
Shift Register
DESCRIPTIONS: (1) INITIALLY Clr=0. So, Q3, Q2, Q1,Qo=0 0 0 0. During the operation Clr=1. Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE (2) If ABCD is 4 bit number to be stored then initially MSB A is applied at serial input.D3. At the +ve edge of 1 st clk cycle ,as input D3=A, So Q3=A. nd
(3) As D3=A. So,input D2=A and at the +ve edge of 2 clk cycle Q2=A and so on. Hence the binary bit goes on shifting from 1 flip flop to another towards left i.e., Q3= Q2, Q1 and Qo. And Q1, Q0. Hence it is called shift register.
Q. 25) a] Design MOD 8 Synchronous Counter. Solutions: MOD 8 counters will count 8 numbers from 0 to 7. (7) decimal = (111)binary i.e. Maximum 8 bit binary number. So, we have to design 8 flip flop counter. Given synchronous counter. Clk input
Output Q2
1
st
nd
2
rd
3
0 0 0
Q1
0 0 1
Clk input Qo
0 1 0
4
th
0
1
1
5
th
1
0
0
Nagpur Institute of Technology, Nagpur
Output Q2
Q1
Qo
th
1
0
1
th
1
1
0
th
1
1
1
th
0
0
0
6 7 8 9
Question Bank : DCFM III Sem CSE e] Design a counter for the following sequence. 0 5 7
4
6
Solutions: (7) decimal = (111) binary Previous flip flop output (n)
Next required output (n+1)
Input to flip flop
Q2n
Q1n
Qon
Q2(n+1)
Q1(n+1)
Qo(n+1)
J2
K2
J1
K1
Jo
Ko
0
0
0
1
0
1
1
X
0
X
1
X
m0
1
0
1
1
1
1
X
0
1
X
X
0
m5
1
1
1
1
0
0
X
0
X
1
X
1
m7
1
0
0
1
1
0
X
0
1
X
0
X
m4
1
1
0
0
0
0
X
1
X
1
0
X
m6
Design for J2 Q1Qo Q 1 Q o
Q2 Q2
Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
1
X
X
X
X
X
X
X
J 2 = 1
Design for K2 Q 2
Q1Qo Q 1 Q o
Q2
Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
0
0
0
1
K 2 = Q 1Q o Design for J1 Q 2 Q2
Q 2
Q1Qo Q 1 Q o
0 1
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
1
X
X
J 1 = Q 2
Nagpur Institute of Technology, Nagpur
Qu stion Bank : DCF
III Sem CSE
Desi gn for K1 Q 2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
Q 2
X
X
X
X
X
1
Q 1Q 0
Q 1Q 0
1
X
X
0
X
X
1
K 1 1 Desi gn for J0 Q 2
Q1Qo Q 1 Q o
Q2
Q 2
Q 1Q 0
Jo = Q 2 Desi gn for Ko Q 2 Q2
Q 2
Ko
Q1Qo Q 1 Q o
X X
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
1
X
0
Q1
Nag ur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Q.25) g] Design lock free or lock out counter to count in the following sequence. 0
5
2
4 6 Solutions: in lock free counter or lock out counter if due to any error the counter enters into any unused state (1, 3, 7) then in the next clk cycle the output of counter should charge from unused state to the used state. 1 0 5 2 Unused state 3 7 4 6 TRANSITION TABLE Previous flip flop output (n)
Next required output (n+1)
Input to flip flop
Q2n
Q1n
Qon
Q2(n+1)
Q1(n+1)
Qo(n+1)
J2
K2
J1
K1
Jo
Ko
0
0
0
1
0
1
1
X
0
X
1
X
0
1
0
1
0
1
0
X
1
1
X
X
1
5
0
1
0
1
1
0
1
X
X
0
0
X
2
1
1
0
1
0
0
X
0
X
1
0
X
6
1
0
0
0
0
0
X
1
0
X
0
X
4
0
0
1
0
0
0
0
X
0
X
X
1
1
0
1
1
0
0
0
0
X
X
1
X
1
3
1
1
1
0
0
0
X
1
X
1
X
1
7
Design for J2 Q 2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
1
0
0
1
X
X
X
X
Q 1Q 0
Q2
Q 2
J 2 = Q 0
Design for K2 Q 2 Q2
Q 2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
1
1
1
0
K 2 = Q 1 + Qo
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE
Design for J1 Q 2
Q1Qo Q 1 Q o
Q2
0 0
Q 2
Q 1Q 0
Q 1Q 0
X
X
X
X
Q 1Q 0
Q 1Q 0
X
1
0
X
1
1
Q 1Q 0
Q 1Q 0
Q 1Q 0
0 1
J 1 = Q 2 Design for K1 Q 2
Q1Qo Q 1 Q o
Q2
X
Q 2
X
Q 1Q 0
K 1 = Q 2 + Qo Design for Jo Q 2
Q1Qo Q 1 Q o
Q2
Q 2
Q 1Q 0
1
X
X
0
0
X
X
0
JO = Q 2Q1 Design for Ko Q 2 Q2
Q 2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
1
1
X
X
1
1
X
Ko = 1
Nagpur Institute of Technology, Nagpur
Qu stion Bank : DCF
III Sem CSE
h] D sign MOD lock free c unter for the following equence. 2 7 1
6
4
5
If th counter ce ters into unused state then the next utput should be 5 Solu ions:
2
7
1 0
6
4
5
3
Previous flip flop output (n)
Next required output (n+1)
Q2n
Q1n
Qon
2(n+1)
0
1
0
1
1
1
1
0
Qo(n+1)
J
K2
1
K1
Jo
Ko
1
1
1
X
X
0
1
X
2
0
0
1
X
1
X
1
X
0
7
1
1
0
1
1
X
0
X
X
0
1
1
1
1
0
0
X
0
0
X
X
1
5
1
0
1
1
0
X
0
1
X
0
X
4
0
0
1
0
X
0
X
0
1
X
6
0
0
1
0
1
1
X
0
X
1
X
0
0
1
1
0
1
1
X
X
1
X
0
3
1
1
Nag ur Institute of Technology, Nagpur
1(n+1)
Inp t to flip flop
Question Bank : DCFM III Sem CSE Design for J2 Q 2
Q1Qo Q 1 Q o
Q2
Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
1
1
X
X
1
1
X
J 2 = 1 Design for K2 Q 2
Q1Qo Q 1 Q o
Q2
Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
0
0
1
0
Q 1Q 0
Q 1Q 0
K 2 = Q 1 Q 0
Design for K1 Q 2
Q1Qo Q 1 Q o
Q2
Q 2
Q 1Q 0
X
X
1
0
X
X
1
0
K 1 = Q 0
Design for J1 Q 2
Q1Qo Q 1 Q o
Q2
0
Q 2
1
Q 1Q 0
Q 1Q 0
0
X
0
X
J 1 = Q 2 Qo
Nagpur Institute of Technology, Nagpur
Q 1Q 0
X X
Qu stion Bank : DCF
III Sem CSE
Desi gn for Jo Q 2
Q1Qo Q 1 Q o
Q2
Q 2
Jo
Q 1Q 0
Q 1Q 0
Q 1Q 0
1
X
X
1
0
X
X
1
Q 1Q 0
1Q 0
Q 2 + Q1
Desi gn for Ko Q 2 Q1Qo Q 1 Q o
Ko
Q2
X
Q 2
X
Q 1Q 0
0
0
X
1
0
X
Q2Q1
Nag ur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE i] Design 3 bit gray code counter. Solutions: The sequence of 3 bit gray code number is, INPUT
Previous flip flop output (n)
OUTPUT
A
B
C
G2
G1
G0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
0
0
1
3
2
4
5
7
6
Next required output (n+1)
Input to flip flop
Q2n
Q1n
Qon
Q2(n+1)
Q1(n+1)
Qo(n+1)
J2
K2
J1
K1
Jo
Ko
0
0
0
0
0
1
0
X
0
X
1
X
0
0
0
1
0
1
1
0
X
1
X
X
0
1
0
1
1
0
1
0
0
X
X
0
X
1
3
0
1
0
1
1
0
1
X
X
0
0
X
2
1
1
0
1
1
1
X
0
X
0
1
X
6
1
1
1
1
0
1
X
0
X
1
X
0
7
1
0
1
1
0
0
X
0
0
X
X
1
5
1
0
0
0
0
0
X
1
0
X
0
X
4
Design for J2 Q 2 Q1Qo Q 1 Q o Q2
Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
0
0
0
1
X
X
X
X
J 2 = Q1Qo
Nagpur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Design for K2 Q 2 Q1Qo Q 1 Q o Q2
Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
1
0
0
0
K 2 = Q1Qo
Design for J1 Q 2 Q1Qo Q 1 Q o Q2
Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
0
1
X
X
0
0
X
X
J 1 = Q2Qo Design for K1 Q 2 Q1Qo Q 1 Q o Q2
Q 2
X X
Q 1Q 0
X X
Q 1Q 0
Q 1Q 0
0
0
1
0
K 1 = Q 2 Qo
Design for Jo Q 2 Q1Qo Q 1 Q o Q2
Q 2
Q 1Q 0
1
X
0
X
Jo = Q2Q1 + Q2Q1
Nagpur Institute of Technology, Nagpur
Q 1Q 0
X X
Q 1Q 0
0 1
Qu stion Bank : DCF
III Sem CSE
Desi gn for Ko Q 2 Q1Qo Q 1 Q o
Ko
Q2
X
Q 2
X
Q 1Q 0
1Q 0
Q 1Q 0
0
1
X
1
0
X
Q 2Q1 + Q Q1
k] D sign Ex-3 c de counter. Solu ions: INPUT
OUTPUT Ex-3 code)
A
B
C
D
Y3
Y2
Y1
Y0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
1
0 0
1 1
0 1
1 0
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
Nag ur Institute of Technology, Nagpur
Question Bank : DCFM III Sem CSE Example: (7)ex-3 = (10) decimal= (1010)binary Previous flip flop output (n)
Next required output (n+1)
Input to flip flop
Q3n
Q2n
Q1n
Qon
Q3(n+1)
Q2(n+1)
Q1(n+1)
Qo(n+1)
J3
K3
J2
K2
J1
K1
Jo
Ko
0
0
1
1
0
1
0
0
0
X
1
X
X
1
X
1
3
0
1
0
0
0
1
0
1
0
X
X
0
0
X
1
X
4
0
1
0
1
0
1
1
0
0
X
X
0
1
X
X
1
5
0
1
1
0
0
1
1
1
0
X
X
0
X
0
1
X
6
0
1
1
1
0
0
0
0
1
X
X
1
X
1
X
1
7
0
0
0
0
1
0
0
1
X
0
0
X
0
X
1
X
8
1
0
0
1
1
0
1
0
X
0
0
X
1
X
X
1
9
1
0
1
0
1
0
1
1
X
0
0
X
X
0
1
X
10
1
0
1
1
1
1
0
0
X
0
1
X
X
1
X
1
11
1
1
0
0
0
0
1
1
X
1
X
0
1
X
1
X
12
Design for J3 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2
Q 1Q 0
Q 1Q 0
0
Q 1Q 0
X
X
X
0
0
1
0
X
X
X
X
X
X
X
X
Q 3Q 2
Q 3Q 2
J 3 = Q2Q1Q0 Design for K3 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
X
X
X
X
1
X
X
X
0
0
0
0
Q 3Q 2 Q 3Q 2
K 3 = Q 2
Nagpur Institute of Technology, Nagpur
Q 3Q 2
Question Bank : DCFM III Sem CSE Design for J2 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
1
X
X
X
X
X
X
X
X
X
0
0
1
0
Q 3Q 2
J 2 = Q 1Q 0
Design for K2 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2 Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
0
0
1
0
0
X
X
X
X
X
X
X
Q 1Q 0
Q 1Q 0
Q 3Q 2
K 2 = Q 1Q 0
Design for J1 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2
Q 1Q 0
X
X
X
X
0
1
X
X
1
X
X
X
0
1
X
X
Q 3Q 2
J 1 = Q 0 + Q 3 Q 2
Nagpur Institute of Technology, Nagpur
Q 3Q 2
Question Bank : DCFM III Sem CSE Design for K1 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
1
X
X
X
1
0
X
X
X
X
X
X
1
0
Q 3Q 2
Q 3Q 2
Q 3Q 2
K 1 = Q 0
Design for Jo Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
1
X
X
1
1
X
X
X
1
X
X
1
Q 3Q 2
Q 3Q 2
Jo = 1 Design for Ko Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
1
X
X
1
1
X
X
X
X
X
X
1
1
X
Q 3Q 2
Ko = 1
Nagpur Institute of Technology, Nagpur
Q 3Q 2
Qu stion Bank : DCF
III Sem CSE
i] Design5 4 -2 -1 code conve ters. Solu ions: 4 -2 -1 cod converters is used for decimal digit as given below. Decimal digits
ode 5
4
-2
0
0
0
0
1
0
1
1
2
0
1
1
3
0
1
0
4
0
1
0
5
1
0
0
6
1
1
1
7
1
1
1
8
1
1
0
9
1
1
0
Nag ur Institute of Technology, Nagpur
-
1
1
1
1
Question Bank : DCFM III Sem CSE Previous flip flop output (n)
Next required output (n+1)
Input to flip flop
Q3n
Q2n
Q1n
Qon
Q3(n+1)
Q2(n+1)
Q1(n+1)
Qo(n+1)
J3
K3
J2
K2
J1
K1
Jo
Ko
0
0
0
0
0
1
1
1
0
X
1
X
1
X
1
X
0
1
1
1
0
1
1
0
0
X
X
0
X
0
X
1
0
1
1
0
0
1
0
1
0
X
X
0
X
1
1
X
0
1
0
1
0
1
0
0
0
X
X
0
0
X
X
1
0
1
0
0
1
0
0
0
1
X
X
1
0
X
0
X
1
0
0
0
1
1
1
1
X
0
1
X
1
X
1
1
1
1
1
1
1
1
1
0
X
0
0
X
X
0
1
X
1
1
1
0
1
1
0
1
X
0
X
0
X
1
X
1
1
1
0
1
1
1
0
0
X
0
X
0
0
X
X
X
1
1
0
0
0
0
0
0
X
1
X
1
0
X
0
1
Design for J3 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
0
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
1
0
0
0
Q 3Q 2
X
X
X
X
Q 3Q 2
X
X
X
X
Q 3Q 2
J 3 = Q2Q1Qo Design for K3 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
X
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
X
X
X
1
0
0
0
0
X
X
X
Q 3Q 2
Q 3Q 2
K 3 = Q 2Q1Qo
Nagpur Institute of Technology, Nagpur
Q 3Q 2
Question Bank : DCFM III Sem CSE Design for J2 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2 Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
1
X
X
X
X
X
X
X
X
X
0
X
1
X
X
X
Q 3Q 2
J 2 = Q1
Design for K2 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
1
0
0
0
1
0
X
X
X
X
X
X
Q 3Q 2
Q 3Q 2
Q 3Q 2
K 2 = Q 1Qo Design for J1 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
1
X
X
X
0
0
X
X
0
X
X
X
X
X
0 Q 3Q 2 Q 3Q 2
1
J 1 = Q2
Nagpur Institute of Technology, Nagpur
Q 3Q 2
Question Bank : DCFM III Sem CSE
Design for K1 Q 3Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
X
X
X
X
X
X
0
1
Q 3Q 2
X
X
0
1
Q 3Q 2
X
X
X
X
Q 3Q 2
Q 3Q 2
K 1 = Qo
Design for Jo Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
1
X
X
X
0
X
X
1
X
X
1
X
X
X
Q 1Q 0
Q 1Q 0
Q 1Q 0
0 Q 3Q 2
1
Q 3Q 2
Q 3Q 2
Jo = Q 2 + Q 1Q 0 Design for Ko Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2 Q 3Q 2
X
X
X
X
X
1
1
X
X
1
1
X
X
X
X
X
Ko = 1 (+5v)
Nagpur Institute of Technology, Nagpur
Q 3Q 2
Qu stion Bank : DCF
III Sem CSE
m]
counter to count the following sequence.
esign MOD 3 UP-DOW
0
3
1
Solu ions: For up-down count r one additi nal control i put I will be used. If I =
then counte will operates as up down
counter and the c unting sequence will be 0,3,1. If I = 1 then coun er will operates as down counter and t e counting s quence will be 1,3,0. Control input
Previous flip flop output (n) Q1n
I
Input t flip flop
Next equired outp t (n+1)
Q0
Q1(n+1)
Q0(n+1)
J1
K1
Jo
Ko
0
0
0
1
1
1
1
1
X
Up
0
1
1
0
1
X
X
X
0
counter
0
0
1
0
0
0
X
X
1
1
0
1
1
1
X
X
X
0
Do n
1
1
1
0
0
1
1
X
1
Co nter
1
0
0
0
1
X
X
1
X
Desi gn for J1 I Q1Qo Q 1 Q o I
I
1 0
Q 1Q 0
0 1
Jo I Qo + IQo
Nag ur Institute of Technology, Nagpur
Q 1Q 0
Q 1Q 0
X
X
X
X
Qu stion Bank : DCF
III Sem CSE
Desi gn for K1 I Q1Qo Q 1 Q o I
I
Q 1Q 0
Q 1Q 0
Q 1Q 0
1
X
X
X
X
X
1
X
K 1 = 1 Desi gn for J0 I Q1Qo Q 1 Q o I
I
Q 1Q 0
Q 1Q 0
Q 1Q 0
1
X
X
X
1
X
X
X
J 0 = 1 Desi gn for K0 I Q1Qo Q 1 Q o I
I
K 0
Q 1Q 0
X
1
X
0
I Q 1 + IQ 1
Nag ur Institute of Technology, Nagpur
Q 1Q 0
0 1
Q 1Q 0
X X
Question Bank : DCFM III Sem CSE
n] Design 3 bit synchronous UP-DOWN counter. Solutions: Transition table: Control input
Previous flip flop output (n)
Next required output (n+1)
Q2n
Q1n
Q0n
Q2(n+ 1)
Q1(n+ 1)
Q0(n+ 1)
J2
K2
J1
K1
Jo
Ko
0
0
0
0
0
0
1
0
X
0
X
1
X
0
0
0
1
0
1
0
0
X
1
X
X
1
Counter 0
0
1
0
0
1
1
0
X
X
0
1
X
0
0
1
1
1
0
0
1
X
X
1
X
1
0
1
0
0
1
0
1
X
0
0
X
1
X
0
1
0
1
1
1
0
X
0
1
X
X
1
0
1
1
0
1
1
1
X
0
X
0
1
X
0
1
1
1
0
0
0
X
1
X
1
X
1
1
1
1
1
1
1
0
X
0
0
X
1
X
1
1
1
0
1
0
1
X
0
1
X
X
1
1
1
0
1
1
0
0
X
0
X
0
1
X
Counter 1
1
0
0
0
1
1
X
1
X
1
X
1
1
0
1
1
0
1
0
0
X
0
X
1
X
1
0
1
0
0
0
1
0
X
1
X
X
1
1
0
0
1
0
0
0
0
X
X
0
1
X
1
0
0
0
1
1
1
1
X
X
1
X
1
I
Up
Down
Jo = Ko = +5V = LOGIC 1 Design for J2 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
0
0
1
0
X
X
X
X
X
X
X
X
1
0
0
0
Q 3Q 2
Ko
Input to flip flop
= 1 (+5v)
Nagpur Institute of Technology, Nagpur
Q 3Q 2
Question Bank : DCFM III Sem CSE Design for K2 Q 3Q 2 Q1Qo Q 1 Q o Q 3Q 2
X
Q 1Q 0
X
X
X
0
1
0
1
0
0
0
X
X
X
X
0 Q 3Q 2 Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 3Q 2
Ko = 1 (+5v)
Design for J1 Q 3Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
0
1
X
X
0
1
X
X
1
0
X
X
1
0
X
X
Q 1Q 0
Q 3Q 2
Q 3Q 2
Q 3Q 2
Q 3Q 2
J 1 = Q 3Q 0 + Q 3 Q 0
Design for K1 Q 3Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
X
X
1
0
X
X
1
0
X
X
0
X
X
X
0
1
Q 1Q 0
Q 3Q 2
Q 3Q 2
Q 3Q 2
Q 3Q 2
Nagpur Institute of Technology, Nagpur
K 1 = Q 3Q 0 + Q 3 Q 0