ECE 1201 BJT Transistors

Semiconductor Devices 2005


Bipolar Junction Transistors

Part I

First reported in 1948 by Bardeen, Brattain and Shockley.


Emitter

Collector

[1] Structure and function of a BJT Semiconductor

[2] Modes of operation

I. Shih

VII-1


Four regions of operation:

E

C Emitter

Base

Collector

P

N

VII-2

Effect of base region width on BJT: Wide Base P

N

P

[1] Active region VEB > 0, VCB < 0 [2] Saturation region

B E

N


PNP

-

P

I. Shih


VEC

N

Base

[3] Current components and gain of the BJT

+

P

C

VEB > 0, VCB > 0

Narrow Base

[3] Cutoff region

P

VEB < 0, VCB < 0

N

P

[4] Inverted active region B I. Shih

VEB < 0, VCB > 0 VII-3

I. Shih

VII-4

1


Effect of base region width on BJT: Base Base contact

Collector

Emitter


Possible configurations of BJT amplifiers Common Base

Emitter contact

E

B

C

P

N

P

IE

Collector contact

Top view

IC

IB IE

IE > 0

-IC

IE = 0 -VCB

Crosssectional view

Base Collector I. Shih

VEB Collector-base junction reverse biased

Emitter-base junction forward biased VII-5

I. Shih

VII-6


E-B and B-C junctions at zero bias P


E-B and B-C junctions at zero bias ξ ( electric field )

P

ξ ( electric field )

EC

EC

N

EF Ei EV

EF Ei EV

WE

ρ

I. Shih

ξ qNB

qNB

-qNE

-qNC VII-7

I. Shih

W

WC

ξ

VII-8

2


E-B junction forward biased, B-C junction reverse biased (Active region) EC

ξ ( electric field )


Ideal Junction Transistor Assumptions: (1) One-dimensional device (2) W << LB (3) No recombination and generation in E-B, B-C junctions and base

EF

NAE

EV

NDB

IE

IC

x” I. Shih

NAC

VII-9

x

x’

I. Shih

VII-10


Current in a BJT:

holes

Current in a Junction:

electrons

Procedure to find IE and IC:

Long base junction: with the width of neutral regions > diffusion length of minority carriers. Currents are due to majority carriers in regions far away from the depletion region.


N-base

holes

electrons

(1) Solve equation for ∆pB(x)

JN(x)

(2) Apply BCs ∆pB(0), ∆pB(w) to evaluate C1 and C2

JP(x)

IEn(0”)

IEp(0)

(3) Solve equation for ∆nE(x”) -xp

P

(4) Apply BCs ∆nE(∞) and ∆nE(0”) to evaluate C1 and C2

xn

0”

0

(5) Obtain IEn and IBp

JN/diff

JN/drift

-xp

P

N

JN/diff

JN/drift

N

xn

J = JN(-xp) + JP(xn) I. Shih

P-emitter

J = JN(-xp) + JP(xn) VII-11

I. Shih

-xp

xn VII-12

3



N-base

P-collector

electrons

Procedure to find IC:

holes

(1) Solve equation for ∆nC(x’)


P-emitter

Procedure to find IE and IC:

= qADB

ICn(0’) ICp(w)

IB = IE - IC

d∆p B dx

x =0

− qADE

d∆nE dx"

x "=0

0”

P

JN/diff

JN/drift

J = JN(-xp) + JP(xn) VII-13

N-base

electrons

P-collector

x=w

ICn(0’) x ' =0

ICp(w)

IB = IE - IC

w

N JN/drift

0’

JN/diff

P

J = JN(-xp) + JP(xn) I. Shih

N

VII-15

-xp

xn VII-14


PNP transistor: pB qV  = exp  p Bo  kT 

holes

I C = I Cp ( w) + I Cn (0' ) d∆n E dx'

JN/diff

I. Shih


+ qADC

0

P

I. Shih


IEp(0)

JN/drift

J = JN(-xp) + JP(xn)

d∆p B dx

electrons

IEn(0”)

0’

w

N

= − qADB

N-base

holes

I E = I Ep (0) + I En (0" )

(2) Apply BCs ∆nC(∞) and ∆nC(0’) (3) Obtain IEp and ICn


P-emitter

holes

N-base

electrons

pB(0) p B '   qV   = exp  − 1 pB(x) p Bo   kT   nE(0”)   qV   ∴ pB ' (0) = pBo exp EB  − 1   kT   pB(w) qV   p B ' (w ) = pBo exp CB  − 1   kT   x” x 0” 0 w Continuity equation: p' dp ∂p j  j p = − qD p = − − div  p  + g τp dx ∂t q d 2 p ' d 2 ∆p B ( x ) ∆p B ( x ) ∴ 2 = = dx dx 2 D pτ B I. Shih

VII-16

4

Semiconductor Devices 2005 Base

For a transistor with w << Lp:


Current in a BJT:

d 2 p ' d 2 ∆p B ( x ) ∆p B ( x ) = = = 0 [τ B = ∞ ] dx 2 dx 2 D pτ B

P-emitter

pB’(0) pB’(x)

holes

N-base

pB’(w)

Solution : ∆pB ( x ) = Ax + B

P-Collector

electrons

holes

pB(0) nE(0”)

pBo

ICn(0’)

pB(w)

Boundary conditions:

at x = 0 ∆p B (0) = B

0

at x = w ∆p B (w ) = Aw + B

w

qV x qV     x ∴ pB ' ( x ) = p Bo exp EB  − 11 −  + pBo exp CB  − 1    kT   w    kT   w 

I. Shih

x”

x

VII-17

(1) (2) (3) (4) (5) (6)

0”

0

Low level injection Electric fields small No other generation Steady state ∆pB(0) is a function of VEB ∆PB(w) is a function of VCB

w

x

Ideal BJT : w << LB ⇒ τ B = ∞

d 2 ∆p B ( x ) ∆pB ( x ) = =0 dx 2 DBτ B x

∆pB ( x ) = C1e LB + C2 e

P-emitter

VII-18

nE(0”)

x”

0

x

0’

nEo

∆p B ( x ) = C2 + C1 x

ICn(0’) w

x”

0”

0

wx

Saturation +

x’

VCB=0

x’

0’ -

Active

IC

Inverted active

Boundary conditions: qV   ∆nE (0") = nEo exp EB  − 1,

qV   ∆pB (0 ) = pBo exp EB  − 1   kT     kT   qV qV     ∆pB (w) = pBo exp CB  − 1, ∆nC (0') = nCo exp CB  − 1   kT     kT  

I. Shih

P-Collector

pBo

d 2 ∆p B ( x ) ∆p B ( x ) = =0 dx 2 τB

pB(w)

N-base nCo

nCo

0”

P-emitter

holes

pB(0)

nEo


P-collector

electrons

pBo

x LB

Different operation modes:

N-base

holes

−

I. Shih


Current in a BJT:

x’

0’

IB > 0 VII-19

I. Shih

IE < 0

Cutoff

VEC

IC > 0

VII-20

5


Current in an ideal BJT: P-emitter

PNP BJT:

N-base

holes


pB(0)

P-Collector

electrons

nCn(0’)

nE(0”)

holes

pB(w)

∆pB(0) ∆nE(0”)

x” ∆nC(0’)

∆pB(w) x”

0”

0

w

x

0’

d 2 ∆pB ( x ) ∆pB ( x ) = =0 dx 2 τB

∆pB (0) = C2 , C1=

wx

0

IE

x’

∆p B ( x ) = C2 + C1 x

Ideal BJT : w << LB ⇒ τ B = ∞

0”

IB

I C = I Cp + I Cn

d∆pB = qADB dx

IC

d∆nC − qADC dx ' x= w

x ' =0

qADB = [∆pB (0) − ∆pB (w)] − qADC nCo  qVCB  − 1 w LC  kT    ∴ I C = qA DB pBo  e  w  

∆pB (0) − ∆pB (w) w

I. Shih

VII-21

qVEB kT

 D n D p   qV  − 1 − qA C Co + B Bo   CB − 1 w   kT   LC 

I. Shih

VII-22


PNP BJT:


PNP BJT: pB(0)

pB(0)

nCn(0’)

nE(0”)

x”

0”

pB(w)

wx

0

IE

IB

x”

x’

0’

wx

0 IB

qVCB kT

x’

0’ IC

d∆p B d∆nE − qADE dx" x"= 0 dx x =0 d∆nE ( x")  d∆nB ( x )    + qADE  = −qADB     dx"  x =0  dx  x"= 0

I E = I Ep (0 ) + I En (0") = −qADB

qV qV D n D p  EB  D p   CB  I C = qA B Bo  e kT − 1 − qA C Co + B Bo  e kT − 1 w   w   LC  

D n   D n   EB  I B = I E − I C = qA E Eo  e kT − 1 + qA C Co  e  LE    LC    ni2 ni2 n2 nEo = , p Bo = , nCo = i NE NB NC

0” IE

IC

qV qV D n D p   EB   D p  CB   I E = qA E Eo + B Bo   e kT  − 1 − qA B Bo   e kT  − 1 L w w     E      

qV

nCn(0’)

nE(0”)

pB(w)

I. Shih

x’

0’

 qVEB   1 = qADE nEo  e kT  − 1 + qADB nBo [∆pB (0 ) − ∆p B (w)]   LE 

 − 1 

∴ I E = qA DE nEo + DB pBo  (e  LE

VII-23

I. Shih

w



qVEB kT

 D p  ) − 1 − qA B Bo   e  w   

qVCB kT

   − 1  

VII-24

6


Active region:


Cutoff region: pB(0)

nE(0”)

nE(0”) pB(w)

x”

0”

nCn(0’) wx

0

0’

IB

IE

pB(0) pB(w)

x’

x”

0”

IC

 D   qVEB  I C = qAni2  B  e kT  = I Ep  wN B   

IB

 D  I E ⇒ −qAni2  E   LE N E  2  DC  I C = qAni    LC N C 

 qVEB >> 1  qVCB << 1   kT   kT

qV  D   EB  I B = I E − I C = qAni2  E  e kT  = I En  LE N E   

wx

0

IE

qV  D D   CB  I E = qAn  E + B  e kT  = I Ep + I En  LE N E wN B    2 i

nCn(0’)

IC

 qVEB << 1  qVCB << 1  kT   kT 

 D   D  I B = I E − I C = − qAni2  E  − qAni2  C   LE N E   LC N C 

I. Shih

VII-25

I. Shih

VII-26



  I α dc =  Cp   I Ep + I En 

Inverted active region: nCn(0’)

x”

Common Base

wx

0

IE

IB

0’

IE

x’

 D  I B = I E − I C = qAni2  C  e  LC N C   I. Shih

 qVEB   kT << 0 qVCB kT

VCB = 0

+

VCB=0 IC

-

Active

IC

qV  D D   CB  I C = − qAni2  C + B  e kT   LC N C wN B    qV  D   CB  I E = − qAni2  B  e kT   wN B   

Saturation

VCB < -3kT/q

pB(w) 0”

IC IB

β dc =

pB(0)

nE(0”)

x’

0’

VEB  qVCB   kT >> 0

Cutoff

VBC

    DB pBo  I Cp + I Cn    1 w α dc =  = = D p D n D N w B Bo E Eo E B  I Ep + I En   1 + + LE   DB N E LE   w

   VII-27

I. Shih

VII-28

7


Common Emitter

Ebers-Moll Equations: Saturation

VEC = 0 IC


VEC > 3kT/q

IC

VEB = 0

+

-

Active

D n D n   qV  D p   qV   I E = qA E Eo + B Bo   EB − 1 − qA B Bo   CB − 1 L L kT   w   kT   E  B D n D n   qV  = I F − α R I R = qA C Co + B Bo   CB − 1 w   kT   LC

IB=0 VEB

VEC

Cutoff  D  I C = qApBo  B  e  w 

qV EB kT

  

qV  D   EB  I B = qAnEo  E  e kT   LE   

qV D n D n   qV   D p   EB  I C = qA B Bo  e kT − 1 − qA C Co + B Bo   CB − 1 L w kT    w    C  = αF IF − IR

I B = I E − I C = (1 − α F )I F + (1 − α R )I R

β dc =

DB N E LE I C = DE N B w I B

I. Shih

An equivalent circuit can be constructed VII-29

I. Shih

VII-30


Ebers-Moll equivalent CKT – PNP: IE = IF −αR IR

Collector

Recombination in Base: ∆pB ( x ) = −

IC

d 2 ∆p B ( x ) ∆p B ( x ) ∆p B ( x ) = = 2 dx 2 DBτ B LB

IR

αFIF

∆p B ( x ) =

Base

IE = -------

IB αRIR

Emitter I. Shih

∆pB (0) − ∆pB (w) x + ∆pB (0) w

electrons

N-base pB(0)

In a practical PNP BJT:

IC = α F I F − I R

I B = (1 − α F )I F + (1 − α R )I R


IC = -------

IF

  w− x  x  1 x 0  + ∆p B (w) sinh   ∆p B (0 ) sinh  w LB  LB   w    sinh    LB       w DB  1 2  DE   exp qVEB  − 1 I B = qAni  + coth  −   L N L N L   w   B  sinh      kT   B B  E E     LB       D  D + qAni2  C + B  LC N C LB N B 

IE VII-31

I. Shih

pB(w)

    1  exp qVCB  − 1 coth w  −   L   w   B  sinh     kT      LB    

VII-32

8


Active region (PNP BJT)


Input resistance: EC

If NA(emitter) >> ND(base)

IE ⇒ IC

EF

Emitter Input kT 1 26 mV =γ = = = 2.6 ohms resistance: q I E 10 mA

EV

Collector input resistance ⇒ ∞ IE=IEp+IEn IE

Large load resistor RL will not affect IC. RL > r

IC

ICp IEp

IC is independent of VCB.

IC=ICp+IEn

IB1 IB2 IB3 IEn

ICn IB

I. Shih

VII-33

I. Shih

VII-34



Possible configuration of BJT amplifiers:

Active region (NPN BJT)

Active region

IE=IEn+IEp

+

VCB=0

-

IB > 0

IC EC

VEB

EF

Active

Saturation

EV VCB IE

ICn IEn

IC

Cutoff

IB > 0

IB1 IB2 IB3 IEp

Inverted active region

ICp

Output characteristics

IB I. Shih

VEC

Inverted

VII-35

I. Shih

VII-36

9


Bipolar Junction Transistors N+


Bipolar Junction Transistors N+

N+ P+

5 um

NE(x)

N

P N

N+ P-region is formed for isolation

P

P+

NB(x)

P

P Discrete

P+NP

NC
transistor

Integrated P+NP transistor

I. Shih

VII-37

I. Shih

VII-38


Current in E-B junction

ICp IEp

Transport Factor and Injection Efficiency

IE=IEp+IEn

IE

IC

IE

IB1 IB2 IB3 ICn

 = I o e  I. Shih

 − 1 

ICn IB

I E = I Ep + I En

I E = I Ep + I En D   qVA  D = qA n n po + p pno  e kT − 1 Lp   Ln 

IB1 IB2 IB3 IEn

IB

IC

ICp IEp

IEn

qV A kT


IE=IEp+IEn

I C = I Cp + I Cn Dn ≈ D p Ln ≈ L p

I B = I B1 + I B 2 − I B 3

p po = 1018 cm −3 ⇒ n po = 102 cm −3

Base Transport Factor : α T =

nno = 1016 cm −3 ⇒ pno = 10 4 cm −3

∴ I Ep = 100 I En

I Cp I Ep

→1

Emitter Injection Efficiency : γ = VII-39

I. Shih

I Ep IE

→1 VII-40

10


DC Alpha:

DC Beta:

IE

ICp IEp

=

IB1 IB2 IB3 IEn

ICn

IE=IEp+IEn

IE=IEp+IEn

IB

0

( I Cn → 0 )

   1  I   = Cp I Ep 1 + I En   I Ep 

β dc =

 I Ep     I Ep + I En 

VII-41

IC IC = I B I E − IC

 IC   I  α dc = E  = I − α dc 1 C 1 −   I E 

α dc = α T γ ⇒ 1

I. Shih

Base Transport Factor : α T =

Common Base: ICp

I. Shih

→1

VII-42

IE

IC

ICp IEp

ICn

IE=IEp+IEn

IB

IE=IEp+IEn

IC

IB1 IB2 IB3 IEn

I C = α dc [I C + I B ] + I CBO ∴ I C [1 − α dc ] = α dc I B + I CBO α dc 1 IC = I + I [1 − α dc ] B [1 − α dc ] CBO

I C = I Cp + I Cn = α T I Ep + I Cn + I Cn = α dc I E + I Cn

I C = α dc I E + I CBO

IE


ICn IB

γ

I Ep

I. Shih

IB1 IB2 IB3 IEn

I Ep

→1

Common Emitter:

IE

= αT γ

I Cp I Ep

Emitter Injection Efficiency : γ =


IEp

IC

ICp

ICn

I C I Cp + I Cn = I E I Ep + I En

I Ep

IE IEp

IB

I Cp

IC

IB1 IB2 IB3 IEn

α dc =


= β dc I B + [1 + β dc ] I CBO

Collector-Base current with emitter open VII-43

I C = β dc I B + I CEO I. Shih

Collector-Emitter current with base open VII-44

11

Bipolar Junction Transistors Structure and principle of operation

A bipolar junction transistor consists of two back-to-back p-n junctions, that share a thin common region called the base. If the base region is n-type, the transistor is a pnp. If the base is p-type, the transistor is an npn. Contacts are made to all three regions. The two outer regions called the emitter and the collector. The structure of an npn bipolar transistor is shown below. The device is called “bipolar” since its operation involves both types of mobile carriers, electrons and holes. Figure 1

VBE

Emitter

VBC

Base

Collector

For an npn device, VBE and VBC are both positive in the normal operating mode, called forward active. That is, the base is put at a higher potential that the emitter or the collector. For example, one might ground the collector, then bias the base at 5.0 V and the emitter at 4.3 V. The currents are defined as positive flowing into the base and collector, and out of the emitter, for an npn. For a pnp device all of the biases and currents are reversed. VBE and VBC are both negative in forward active. And the currents are defined as positive flowing out of the base and the collector and into the emitter. In either case: Eq. 1 The operation of the device is illustrated below for an npn. Only the first order effects for the forward active bias mode of operation are shown. The base-emitter junction has been forward biased and the basecollector junction has been reverse biased. Under these conditions, electrons diffuse from the emitter into the base and holes diffuse from the base into the emitter. The bipolar device is constructed in such a way that two important effects occur under these conditions. The first is that the emitter is normally doped with a much higher concentration of impurities than the base. As a result, when the emitter base junction is forward biased, many more electrons enter the base from the emitter than holes from the base entering the emitter. There is a strict ratio between these two currents. The number of electrons from the emitter is

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proportional to the number of holes from the base. The second effect is that the base is physically narrow. This means that most of the electrons sent from the emitter find their way into the collector and constitute the vast majority of the collector current. Most of the base current typically is injected into the emitter or recombines with the electrons injected from the emitter. Figure 2

Hole current for npn transistor

Emitter

Base

Collector

Electron current for npn transistor

The transport factor, α, is defined as the ratio of the collector and emitter current: Eq. 2 Using Kirchoff’s current law, we show that the base current equals the difference between the emitter and collector current. The current gain, β, is defined as the ratio of the collector and base current. From Equations 1 and 2 one can show that: (5.2.15) This explains how a bipolar junction transistor can provide current amplification. If the collector current is almost equal to the emitter current, as is the case for most devices, the transport factor, α, approaches one. The current gain, β, can therefore become much larger than one. Thus a small base current can be used to modulate (control) a much larger collector current. Finally it should be noted that α and β are not constants, but vary slightly with the bias conditions.

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9-BIPOLAR JUNCTION TRANSISTOR (BJT) I. Basic Structure and Band Diagrams Basic bipolar transistor structure: Two pn junctions J1 and J2 are placed back-to-back a distance W apart, forming an n-p-n structure. The simple, idealized transistor shown below has doping density of 1016 cm-3 in the emitter and collector and 1014 cm-3 in the base.

EE 216 Bipolar Transistor (Winter 2005)

(a) Equilibrium

(b) Cutoff

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Energy-band diagrams and electron-density for the ideal transistor sketched on page 1 for the following conditions: (a) thermal equilibrium (zero bias) (b) both junctions reverse-biased (cutoff mode) (c) both junctions forward-biased (saturation mode) (d) J1 forward-biased and J2 reverse-biased (active mode)

(c) Saturation

(d) Active


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1

Current voltage characteristics


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Structure and Model of Bipolar Transistor C B

C B

E

E

pnp

npn Symbol

Discrete pnp transistor

Integrated circuit npn bipolar transistor EE 216 Bipolar Transistor (Winter 2005)

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2

Doping profile in a realistic IC npn transistor

Collector is formed by epitaxy and base and emitter by ion implantation

XB E

N+

P

N–

N+

C

most of the e–

e–

B

holes for recombination and injection into emitter

! 0.7 volts EE 216 Bipolar Transistor (Winter 2005)

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Basic Operation in Forward Active Region XB E

N+

P

C

N

B Ec EF Ev

The E-B junction is forward biased and the C-B junction is reverse biased

V x

"

x !

x


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3

The BJT operates basically as follows: 1. An external voltage is applied to forward bias the B-E junction (≈ 0.7 volts). 2. Electrons are injected from the emitter into the base (holes are also injected from the base into the emitter, but their numbers are much smaller because NdE > NaB).

IC

3. If xB << Ln in the base, most of the injected electrons get to the collector without recombining. A few do recombine; the holes necessary for this are supplied as base current. 4. The electron reaching the collector are collected across the B-C depletion region. 5. Since most of the injected electrons reach the collector and only a few holes are injected into the emitter, or recombine with the electrons in the base, IB << IC . The device has a substantial current gain. EE 216 Bipolar Transistor (Winter 2005)

derive the basic relationship for electron current flowing between the E and C, first assume the device current gain is high. The hole current in the base is small. This assumption allows a rough estimation of the ε field.  Note that for uniform doping in the base, εx ≈ 0 and the electrons traveling through the base will move only by diffusion.

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 To


J P = qµ pB p" x # qD pB

"x #

dp $ 0 (1) dx

D pB 1 dp kT 1 dp = µ pB p dx q p dx

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4



J n = qµnB n"x + qDnB

In a modern ion implanted base transistor, dp/dx ≠ 0, hence εx ≠ 0. The direction of this field aids electron flow from E to C, and retards electron flow from C to E.

kTµnB dp dn n + qDnB p dx dx qD # dp dn & = nB %n + p ( p $ dx dx ' =

=



The electron flow between ! emitter and collector is given by

dn dx

xB

Jn

qDnB d ( pn ) p dx

p

" qD 0

xB

dx =

nB

" d( pn) 0

= pn ( x B ) # pn (0)

!


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From diode analysis, the pn products at the edge of the depletion regions are given by pn( x = 0 ) = ni2 eqVBE / kT pn( x B ) = ni2 eqVBC / kT

Jn =

qni2 eqVBC / kT " eqVBE / kT

[

xB

]

p dx 0 DnB

(2)

#

Assuming Dn is constant in the base

[

I n = I s eqVBC / kT " eqVBE / kT

where


Is =

]

q 2 Ani2 DnB QB

(3)

(4)

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5

xB

QB = q " p dx

(5)

0

Which is the total undepleted charge in the base A = E-B cross-sectional area 1. Only one of the two exponential terms is important in forward or reverse active bias region. When the device is in saturation, both junctions are forward biased and both terms must be included. 2. The quantity xB QB x B = " p dx # " N aB dx q 0 0 is called the base Gummel number.


(6)

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QB is the total integrated base charge (atoms/cm2). Since I ∝1/QB, it is important to minimize QB, i.e., use low doping levels in the base (this is a good strategy to achieve maximum dc current gain, but we will see that this does not work for high frequencies). If the base is uniformly doped,

ε

= 0, QB = q NaB xB

qAni2 DnB qVBE / kT qVBC / kT In = " e "e N aB x B

(

="

)

q 2 Ani2 DnB qVBE / kT qVBC / kT e "e QB


(

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(7)

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6

III. Current Gain A number of factors can contribute to base current in a BJT. We consider them individually. N+

pn pn o

np n p

npo

N

pno

A. Recombination in the Neutral Base Region Some of the electrons traversing the base will recombine with majority carrier holes. (This is usually unimportant in modern IC BJTs). EE 216 Bipolar Transistor (Winter 2005)

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For simplicity if we assume that the base is uniformly doped so that εx = 0, then the electron transport and the continuity equations are reduced to

dn dn # qDnB dx dx d 2n p n p " n po DnB " =0 dx 2 # nB

"

J n = qµnB n

x

+ qDnB

As!discussed in the case of the P-N junction, the general solution to these equations is

!

n p " n po = K1e" x / LnB + K 2 e x / LnB

where LnB = (DnB τnB)1/2 = diffusion length The appropriate boundary conditions are

n p ( x = 0) = n po eqVBE / kT =

ni2 qVBE / kT e Na

n p ( x = XB ) " 0


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7

Excess Minority Carrier Profiles for Different xB/Ln Ratios With these boundary conditions, the solution is

) sinhsinh[( x(BxB# /xL) nB/ LnB) ]

(

n p " n po eqVBE /kT #1

Most minority carriers make it across the base if xB ≤ Ln N+

pn pn o


N

np n p

pno

npo

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The emitter and collector electron currents are

I nE = I n ( x = 0 ) =

qADnB n po

I nC = I n ( x = X B ) =

LnB

(eqV

qADnB n po LnB

BE / kT

(eqV

)

"1 coth

BE /kT

)

xB LnB

"1 csch

xB LnB

(9)

(10)

The ratio of these two currents is defined as the base transport factor. I x "T = nC = sech B I nE LnB


(11)

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8

In modern IC BJTs, xB << LnB and there is little recombination in the neutral base. The minority carrier distribution is nearly linear. 1 x2 "T # 1$ 2B (12) 2 L nB In a typical modern BJT, xB ≤ 1 µm and LnB ≥ 30 µm so that α T ≈ 0.9994. αT is NOT a limiting factor in current gain. Using Eq. 9, 11 and 12 the base current due to αT is I BREC = I nE " I nC

= (1" # T ) I n $

qAni2 xB qVBE / kT e "1 2N aB% nB

(

where τnB = electron lifetime in base = EE 216 Bipolar Transistor (Winter 2005)

(13)

) L2n Dn

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B. Hole Injection into the Emitter The dominant mechanism in limiting β in modern BJTs is hole injection from B into E. This process occurs because VBE not only decreases the barrier to electron flow from E to B, but also the barrier for hole flow from B to E.

xE >> LPE “Long Base” Emitter


xE << LPE “Short Base” Emitter

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9

The injected hole currents in each case come directly from the analysis of the long and short base pn junction diodes. I pE =

I pE =

qAni2 D pE N dE L pE

qAni2 D pE

(eqV

BE / kT

(eqV

BE / kT

)

"1 for x E >> L pE

(14)

)

"1 for x E << L pE (15) N dE x E (The subscript E is used to refer to emitter properties.) The emitter injection efficiency is defined as

"=

I nE I nE + I pE

=

I nE I TOT

1 = x N D 1+ B aB pE xE N dE DnB


(16)

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If xB >> LnB or xE >> LpE, then xB or xE is replaced with LnB or LpE. This equation is only approximately correct in IC structures because NaB and NdE are not constant. Typically, γ ≥ 0.98 which implies a current gain ≥ 50. Such values are typically observed in IC BJTs.

γ is maximized (close to unity) by 1. Making NdE >> NaB 2. Making xE large or alternatively by preventing hole recombination at the emitter contact. 3. Making xB small. This is also desirable for increasing fτ.


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10

Summarizing our discussion of current gain,

I nC In InE I "F = C = = C = "T # I E InE + I pE InE InE + I pE

(17)

In modern BJTs αT is nearly 1 and γ is the main factor limiting the performance. I IC #F ! = C = = (18) IB I E " IC 1 " #F By combining Eq. (12) and (16) and making appropriate approximations it can be shown that /1 )D N x # x &2 , DnB N dE L pE 1 pE aB B B " =+ + % ( . 0 +* DnB N dE L pE 2 $ LnB ' .D pE N aB xB

The main parameter to achieve high gain is the ratio of NdE/NaB EE 216 Bipolar Transistor (Winter 2005)

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Deviations from the Ideal Base Width Modulation V EB

IE

V EB

p+ Emit.

n+ Base

n+ Base

p Collect. Constant base width, independent of V CB

IE

p+ Emit.

VCB

p Collect. More depletion with V CB : smaller x B

VCB

 As

VC increases, the reverse bias across the B-C increases, the depletion region widens. Hence the neutral base width W↓ resulting in an increase in β thus and IC ↑  An extreme case of base width modulation is punch through EE 216 Bipolar Transistor (Winter 2005)

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11

Base Width Modulation: Early Voltage

This is known as Early effect (after Jim Early) and is usually modeled as

" V % IC = IS eqVBE / kT ! 1 $ 1 + CE ' VA & # 2 qN aBWB VA " #Si

(

Where

)

(19)

is known as the Early voltage, which is a measure of how independent the base width xB is from VCB . Small |VA| means large base width modulation. EE 216 Bipolar Transistor (Winter 2005)

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Preventing Base Width Modulation V EB

V EB p+ Emit.

p+ Emit.

n+ Base

n+ Base

p Collect.

VCB

IC

p– collect.

VCB

IC

• Base width modulation is caused by the CB depletion region growing into the base. • To prevent this, collector doping should be much lower than base doping, so depletion region extends much farther into the collector than into the base. EE 216 Bipolar Transistor (Winter 2005)

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12

Avalanche Multiplication and Breakdown P-N-P transistor

Breakdown! Base current is held constant in the common emitter configuration, so the only place that excess electrons in the base (4) can go is into the emitter. This produces an internal bias that causes an injection of holes, Ip = βIn, which is regenerative and leads to a much lower breakdown voltage EE 216 Bipolar Transistor (Winter 2005)

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The common expression for collector current IC =

" dc 1 IB + I 1# " dc 1# " dc CB0

can be modified to account for the avalanche multiplication and resulting emitter injection by replacing αdc by Mαdc IC =

"dc 1 IB + I 1# M" dc 1# M" dc CB0

Since αdc ~ 0.99, M need only be ~1.01 to have IC ⇒ ∞. Recall in PN junction avalanche, M ⇒ 10-100 before I ⇒ ∞. ⇒ Lower voltage for the onset of avalanche breakdown. Collector doping must be light to prevent avalanche breakdown. (Also prevents base width modulation.) EE 216 Bipolar Transistor (Winter 2005)

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13

IV. Low and High Current Level Effects on β Theoretically,∝T and γ are independent of VBE, implying that the ratio of collector current to base current (i.e., current gain β) is a constant, independent of VBE or IC. In practice, the ratio of the two currents is NOT independent of IC.


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A. B-E Depletion Region Recombination At low current levels, the dominant reason for the reduced β is recombination in the B-E depletion region. E e– injection

B

*

C

recombination hole injection

In the P-N junction discussion, it has been shown that some recombination of the carriers moving through the depletion qAniWE qVBE /2kT region will occur, and that I e REC = "o

(19)

where τo = lifetime in the depletion region. 1. This current flows in the B-E circuit and does not directly affect IC. Thus as IREC becomes important, the ratio IC/IB decreases. 2.

qVBE e 2 kT

dependence − important at low current levels.


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14

High Current Effects A. High Level Injection in the Base E

B

Nd

C

Na + n

e– injection

If injection levels are very high, the assumption of n << Na in the base is no longer valid. In that case, for the base to remain quasi-neutral, p( x ) = NaB ( x ) + n( x )

QB = q " oX B pdx #


and

$ %

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B. High Level Injection in the Collector (Kirk Effect) E

B

Depletion region under high level injection

C e-

J = qv(x) Original depletion region

The collector is doped lightly to obtain reasonable B-C reverse breakdown voltage. The doping is lighter than the base to minimize Early effect. As a result high level injection occurs rather easily. At high current levels, our assumption of complete depletion in the BC depletion region is no longer valid. EE 216 Bipolar Transistor (Winter 2005)

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15

If the electrons are traveling at the saturated drift velocity, vsat, then at any given time, the density of electrons in the depletion region is J/qv(x), hence the net charge density is

" = N ( x) #

!

J qv(x)

where N(x) = Nd -Na

As a result there is excess negative charge on the base side of the depletion region and less positive charge on the collector side. The net result is that to maintain charge neutrality the depletion region shrinks in the base side and widens in the collector side. As a result the neutral base region widens. This phenomenon is first important in the collector side because it is usually the most lightly doped.

XB !

and


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D. Base Resistance

The effective emitter bias becomes VBE - IBRB

" V !I R % IC = IS exp$ q BE B B ' # & kT EE 216 Bipolar Transistor (Winter 2005)

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E.

Current Crowding

As IB and IC increase, the voltage drop across RB becomes significant. This means that the effective VBE across the active (center) portion of the device is not as great as the externally applied VBE. The edge of the emitter thus has the highest electron current density (current crowding). This plays a double role as the bandgap of the material shrinks with increased temperature, further increasing the injection around the emitter periphery. The total collector current decreases below the ideal eqVBE/kT behavior. To minimize the impact of this (1) The emitter should be made narrower. For higher current capability multiple emitters can be used in a single base. (2) In the extrinsic base region a N+ diffusion should be done. EE 216 Bipolar Transistor (Winter 2005)

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Heterojunction Bipolar Transistor (HBT)

Motivation: Reduce IEp by making hole injection into the emitter more difficult. Solution: Use different materials with different bandgaps: Barrier to hole injection.


Emitter

Base

Si

SiGe

Ec

Ev

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HBT Current Gain If we go back to eqs. (7) and (14) used to calculate the injection efficiency, but do not cancel out the ni2 terms since they will be different when you have an emitter and base with different Eg ’s. The injection ratio becomes

"=

1 2 & D W N B # niE %% 2 (( 1+ E DB LE N E $ niB '

And if β is limited by injection efficiency, it becomes

"~

2 # D L N %n ( ~ B E E ' iB * 1$ # DE W N B & niE )

And if Δεg = 0.356 eV, then

" niB %2 $ ' = 10 6 # niE &

Which means NB can be 100-1000NE and we still have very high current gain. EE 216 Bipolar Transistor (Winter 2005)

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Big Wins for HBTs 1. Eliminates base width modulation because depletion regions are in the more lightly doped emitter and collector regions 2. Current gain limited only by recombination in the E-B junction or the base 3. Current crowding and base resistance are greatly reduced because of high base doping 4. Completely eliminates Punch-thru due to high base doping 5. Improved high frequency performance from decreased base resistance and E-B capacitance


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18

!

VI. High Frequency Limitations A. Base Transit Time

E

B

C

np

How long does it take from the time a voltage is applied at the input (E-B) until a voltage appears at the output (CB) ?

!0

X

In the absence of ε fields in the base (NaB = constant, low level injection), then the injected electron concentration varies linearly across the base The total electron charge in the base is

1 1 qB = qAn p x B = qAn p o (e q VBE / kT ) x B 2 2 Since

IC =

qADn n po xB

!

(eqV

BE /kT

)

"1

The transit time across the base is simply EE 216 Bipolar Transistor (Winter 2005)

q x2 "B = B # B I C 2DnB

(21)

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If the base doping is graded (typical in IC BJTs), an aiding ε field speeds up the carriers and τB is reduced.



Also, under high level injection, to maintain base neutrality, the hole concentration in the base ↑ and has a gradient similar to the electron gradient. This sets up an ε field which also speeds up the electron.



τB is usually NOT the dominant frequency limitation in modern BJTs.


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B. Emitter Capacitance Charging Time E

B

C

re Cje

From the earlier pn diode discussion, re =

dVBE kT " dI E qI E

Cje depends upon the doping levels and current levels (VBE) in the transistor. A rough approximation is that Cje ≈ 2 CBE(0) where CBE(0) is the zero voltage B-E junction capacitance. kT ! E = re C je " 2C (0 ) (22) qI E BE EE 216 Bipolar Transistor (Winter 2005)

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C. Collector Capacitance Charging Time Rc

E Cµ

B

The B-C junction is reverse biased so the junction impedance is very high.

" C = R CC µ

(23)

where RC = collector series resistance Cµ = B-C depletion capacitance EE 216 Bipolar Transistor (Winter 2005)

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D. Collector Depletion Layer Transit Time For moderate or high B-C reverse biases, the ε field across the depletion layer is high, so the electrons can be assumed to move at VSAT xDBC (24) "D # 2VSAT Where xDBC = B-C depletion width The factor of 2 in the denominator is one of the most erroneously quoted equations in semiconductor device physics. It arises because the carriers are moving by drift and a current starts to appear at the output when the carriers just enter the base side of the B-C depletion region


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All of the time delays we have considered add, so that (25)

! TOT " ! B + ! E + ! C + ! D

The cutoff frequency of the device is simply fT =

(26)

1 2 "# TOT

This is approximately the frequency at which β is reduced to 1. Above this frequency, the device is not useful as an amplifier.


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21

VII. Ebers-Moll Model "E

"C !R " R

E

"F = "ES

qVBE e kT – 1

!F " F "B B

C qVBC

"R = "C S e kT – 1

I E = "I F + # R I R

(27)

IC = " F IF # I R

(28)

I B = (1" # F ) I F + (1" # R ) I R

(29)


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where

αF = forward alpha ≈ IC/IE if VBE is +ve and VBC is -ve αR = reverse alpha ≈ IE/IC if VBC is +ve and VBE is -ve IES = emitter reverse saturation current ICS = collector reverse saturation current The Ebers-Moll model may be used under all junction bias conditions (i.e., cut-off, forward active, reverse active and saturation) to estimate the terminal currents.


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VIII. Hybrid π Equivalent Circuit A useful small signal, AC equivalent circuit for the BJTs in forward active region is shown below. r

C

b

B

µ

C

+ r!

Cd +

vbe

C je

–

E

gmvbe

The parameters are defined as follows gm = transconductane=

dIC qI " C dVBE kT


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r" = base/emitter resistance = C je

(30)

45

(31)

Cd = Diffusion capacitance of the B-E Junction (due to stored minority carriers) dq B dqB dI C = = = " B gm (32) dVBE dIC dVBE Cµ = depletion capacitance of B - C junction I "0 = C = gm r# The DC current gain is IB

Considering only the input E-B capacitance, the AC gain is

"=

"0 1+ j#r$ C $


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23

The AC gain decreases to 0.707β0 when "r# C # = 1 or 1 f" = 2 #r# C# A more widely used measure is when the current gain goes to 1 "r# C # = $0 = g mr# and g 1 f% = m & 2 #C # 2 #% EC Even if the current gain is less than unity, the transistor can still produce power gain due to the impedance transformation and the unity power gain or maximum frequency of oscillation is 1 This is the performance parameter $ ' 2 f" which is dramatically improved by fmax = & ) % 8# rBC BC ( HBTs because of the ability to heavily dope the base region and lower rB EE 216 Bipolar Transistor (Winter 2005)

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BIPOLAR JUNCTION TRANSISTOR (BJT) Strengths 1. Threshold Voltage controlled by Eg (only very weak dependence on doping and process parameters) 2. Very high transconductance (gm) and high non–linearity • Lower voltage swing in logic • Lower sensitivity to parasitics 3. Vertical device (diffusion, ion implantation and epitaxy) are easier to achieve small vertical dimensions than lithography to achieve small lateral dimensions. 4. High current/unit area – High drive capability for driving long off chip lines or for high current devices, such as LEDs or lasers


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BIPOLAR JUNCTION TRANSISTOR (BJT) Weaknesses 1. High Power ⇒ relatively low levels of integration 2. No effective complementary circuit technology 3. Device based upon minority carriers ⇒ charge storage and diffusion rather than drift 4. Difficult compromises for device optimization • Base resistance: RC time constants and transit time favor a very thin, highly doped base • high injection efficiency requires NE >> NB • Bandgap shrinkage, lower defect densities and E-B capacitance all favor moderate emitter doping 5. Far greater processing complexity, larger number of mask levels with tight alignment tolerances on high performance devices. EE 216 Bipolar Transistor (Winter 2005)

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25

Bipolar-Junction (BJT) transistors References: Barbow (Chapter 7), Hayes & Horowitz (pp 84-141), Rizzoni (Chapters 8 & 9) A bipolar junction transistor is formed by joining three sections of semiconductors with alternatively different dopings. The middle section (base) is narrow and one of the other two regions (emitter) is heavily doped. Two variants of BJT are possible: NPN and PNP. C

NPN Transistor C

n B

B

p n+ E

C C

B

E Circuit Symbols

C

p B

E

PNP Transistor

B

n p+ E

C B

E

E

Circuit Symbols

We will focus on NPN BJTs. Operation of a PNP transistor is analogous to that of a NPN transistor except that the role of “majority” charge carries reversed. In NPN transistors, electron flow is dominant while PNP transistors rely mostly on the flow of “holes.” Therefore, to zeroth order, NPN and PNP transistors behave similarly except the sign of current and voltages are reversed. i.e., PNP = − NPN ! In practice, NPN transistors are much more popular than PNP transistors because electrons move faster in a semiconductor. As a results, a NPN transistor has a faster response time compared to a PNP transistor. At the first glance, a BJT looks like 2 diodes placed back to back. Indeed this is the case if we apply voltage to only two of the three terminals, letting the third terminal float. This is also the way that we check if a transistor is working: use an ohm-meter to ensure both diodes are in working conditions. (One should also check the resistance between CE terminals and read a vary high resistance as one may have a burn through the base connecting collector and emitter.) The behavior of the BJT is different, however, when voltage sources are attached to both BE and CE terminals. The BE junction acts like a diode. When this junction is forward biased, electrons flow from emitter to the base (and a small current of holes from base to emitter). The base region is narrow and when a voltage is applied between collector and emitter, most of the electrons that were flowing from emitter to base, cross the narrow base region and are collected at the collector region. So while the BC junction is reversed biased, a large current can flow through that region and BC junction does not act as a diode. The amount of the current that crosses from emitter to collector region depends strongly on the voltage applied to the BE junction, vBE . (It also depends weakly on voltage applied ECE60L Lecture Notes, Spring 2004

55

between collector and emitter, vCE .) As such, small changes in vBE or iB controls a much larger collector current iC . Note that the transistor does not generate iC . It acts as a valve controlling the current that can flow through it. The source of current (and power) is the power supply that feeds the CE terminals. A BJT has three terminals. Six parameters; iC , iB , iE , vCE , vBE , and vCB ; define the state of the transistor. However, because BJT has three terminals, KVL and KCL should hold for these terminals, i.e., iE = i C + i B

vBC = vBE − vCE

iC

iB

vCB + _ + vBE

+ vCE

_ _ iE

Thus, only four of these 6 parameters are independent parameters. The relationship among these four parameters represents the “iv” characteristics of the BJT, usually shown as i B vs vBE and iC vs vCE graphs.

The above graphs show several characteristics of BJT. First, the BE junction acts likes a diode. Secondly, BJT has three main states: cut-off, active-linear, and saturation. A description of these regions are given below. Lastly, The transistor can be damaged if (1) a large positive voltage is applied across the CE junction (breakdown region), or (2) product of iC vCE exceed power handling of the transistor, or (3) a large reverse voltage is applied between any two terminals. Several “models” available for a BJT. These are typically divided into two general categories: “large-signal” models that apply to the entire range of values of current and voltages, and “small-signal” models that apply to AC signals with small amplitudes. “Low-frequency” and “high-frequency” models also exist (high-frequency models account for capacitance of each junction). Obviously, the simpler the model, the easier the circuit calculations are. More complex models describe the behavior of a BJT more accurately but analytical calculations become difficult. PSpice program uses a high-frequency, Eber-Mos large-signal model which is a quite accurate representation of BJT. For analytical calculations here, we will discuss a simple low-frequency, large-signal model (below) and a low-frequency, small-signal model in the context of BJT amplifiers later.

ECE60L Lecture Notes, Spring 2004

56

A Simple, Low-frequency, Large Signal Model for BJT: As the BE junction acts like a diode, a simple piece-wise linear model can be used : BE Junction ON:

vBE = vγ ,

and

iB > 0

BE Junction OFF:

vBE < vγ ,

and

iB = 0

where vγ is the forward bias voltage (vγ ≈ 0.7 V for Si semiconductors). When the BE junction is reversed-biased, transistor is OFF as no charge carriers enter the base and move to the collector. The voltage applied between collector and emitter has not effect. This region is called the cut-off region: Cut-Off:

vBE < vγ ,

iB = 0,

i C ≈ iE ≈ 0

Since the collector and emitter currents are very small for any vCE , the effective resistance between collector and emitter is very large (100’s of MΩ) making the transistor behave as an open circuit in the cut-off region. When the BE junction is forward-biased, transistor is ON. The behavior of the transistor, however, depends on how much voltage is applied between collector and emitter. If vCE > vγ , the BE junction is forward biased while BC junction is reversed-biased and transistor is in active-linear region. In this region, iC scales linearly with iB and transistor acts as an amplifier. Active-Linear:

vBE = vγ ,

iB > 0,

iC = β ≈ constant, iB

vCE ≥ vγ

If vCE < vγ , both BE and BC junctions are forward biased. This region is called the saturation region. As vCE is small while iC can be substantial, the effective resistance between collector and emitter in saturation region is small and the BJT acts as a closedcircuit. Saturation:

vBE = vγ ,

iB > 0,

iC < β, iB

vCE ≈ vsat

Our model specifies vCE ≈ vsat , the saturation voltage. In reality in the saturation region 0 < vCE < vγ . As we are mainly interested in the value of the collector current in this region, vCE is set to a value in the middle of its range in our simple model: vCE ≈ vsat ∼ 0.5vγ . Typically a value of vsat ≈ 0.2 − 0.3 V is used for Si semiconductors. ECE60L Lecture Notes, Spring 2004

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The above simple, large-signal model is shown below. A comparison of this simple model with the real BJT characteristics demonstrates the degree of approximation used. iC

iB

Saturation

BJT ON

Active Linear

BJT OFF vγ

vBE

vsat

Cut Off

vCE

How to Solve BJT Circuits: The state of a BJT is not known before we solve the circuit, so we do not know which model to use: cut-off, active-linear, or saturation. To solve BJT circuits, we need assume that BJT is in a particular state, use BJT model for that state to solve the circuit and check the validity of our assumptions by checking the inequalities in the model for that state. A formal procedure will be: 1) Write down a KVL including the BE junction (call it BE-KVL). 2) Write down a KVL including CE terminals (call it CE-KVL). 3) Assume BJT is in cut-off (this is the simplest case). Set iB = 0. Calculate vBE from BE-KVL. 3a) If vBE < vγ , then BJT is in cut-off, iB = 0 and vBE is what you just calculated. Set iC = iE = 0, and calculate vCE from CE-KVL. You are done. 3b) If vBE > vγ , then BJT is not in cut-off. Set vBE = vγ . Solve above KVL to find iB . You should get iB > 0. 4) Assume that BJT is in active linear region. Let iE ≈ iC = βiB . Calculate vCE from CE-KVL. 4a) If vCE > vγ , then BJT is in active-linear region. You are done. 4b) If vCE < vγ , then BJT is not in active-linear region. It is in saturation. Let vCE = vsat and compute iC from CE-KVL. You should find that iC < βiB . You are done. ECE60L Lecture Notes, Spring 2004

58

Example 1: Compute the parameters of this circuit (β = 100).

12 V

Following the procedure above:

1 kΩ

BE-KVL: CE-KVL:

iC

4 = 40 × 103 iB + vBE

40 kΩ

3

12 = 10 iC + vCE , + -

Assume BJT is in cut-off. Set iB = 0 in BE-KVL: BE-KVL:

4 = 40 × 103 iB + vBE

+

iB + vBE

4V

vCE _ _ iE

vBE = 4 > vγ = 0.7 V

→

So BJT is not in cut off and BJT is ON. Set vBE = 0.7 V and use BE-KVL to find iB . BE-KVL:

4 = 40 × 103 iB + vBE

iB =

→

4 − 0.7 = 82.5 µA 40, 000

Assume BJT is in active linear, Find iC = βiB and use CE-KVL to find vCE : iC = βiB = 100iB = 8.25 mA CE-KVL:

12 = 1, 000iC + vCE ,

→

vCE = 12 − 8.25 = 3.75 V

As vCE = 3.75 > vγ , the BJT is indeed in active-linear and we have: vBE = 0.7 V, iB = 82.5 µA, iE ≈ iC = 8.25 mA, and vCE = 3.75 V. 12 V

Example 2: Compute the parameters of this circuit (β = 100). Following the procedure above: BE-KVL:

4 = 40 × 103 iB + vBE + 103 iE

CE-KVL:

12 = 1, 000iC + vCE + 1, 000iE

1 kΩ iC 40 kΩ + -

Assume BJT is in cut-off. Set iB = 0 and iE = iC = 0 in BE-KVL:

4V

+

iB + vBE

vCE _ _ iE 1 kΩ

BE-KVL:

4 = 40 × 103 iB + vBE + 103 iE

→

vBE = 4 > 0.7 V

So BJT is not in cut off and vBE = 0.7 V and iB > 0. Here, we cannot find iB right away from BE-KVL as it also contains iE . ECE60L Lecture Notes, Spring 2004

59

Assume BJT is in active linear, iE ≈ iC = βiB : BE-KVL:

4 = 40 × 103 iB + vBE + 103 βiB 4 − 0.7 = (40 × 103 + 103 × 102 )iB iB = 24 µA

CE-KVL:

→

iE ≈ iC = βiB = 2.4 mA

12 = 1, 000iC + vCE + 1, 000iE ,

→

vCE = 12 − 4.8 = 7.2 V

As vCE = 7.2 > vγ , the BJT is indeed in active-linear and we have: vBE = 0.7 V, iB = 24 µA, iE ≈ iC = 2.4 mA, and vCE = 7.2 V. Load line The operating point of a BJT can be found graphically using the concept of a load line. A load line is the relationship between iC and vCE that is imposed on BJT by the external circuit. For a given value of iB , the iC vCE characteristics curve of a BJT is the relationship between iC and VCE as is set by BJT internals. The intersection of the load line with the BJT characteristics represent a pair of iC and vCE values which satisfy both conditions and, therefore, is the operating point of the BJT (often called the Q point for Quiescent point) The equation of a load line for a BJT should include only iC and vCE (no other unknowns). This equation is usually found by writing a KVL around a loop containing vCE . For the example above, we have (using iE ≈ iC ): KVL: 12 = 1, 000iC + vCE + 1, 000iE

→

2, 000iC + vCE = 12

An example of a load line, iC vCE characteristics of a BJT, and the Q-point is shown below.


60

BJT Switches and Logic Gates The basic element of logic circuits is the transistor switch. A schematic of such a switch is shown. When the switch is open, iC = 0 and vo = VCC . When the switch is closed, vo = 0 and iC = VCC /RC . In an electronic circuit, mechanical switches are not used. The switching action is performed by a transistor with an input voltage switching the circuit, as is shown. When vi = 0, BJT will be in cut-off, iC = 0, and vo = VCC (open switch). When vi is in “high” state, BJT can be in saturation with vo = vCE = Vsat ≈ 0.2 V and iC = (VCC − Vsat )/RC (closed switch). When Rc is replaced with a load, this circuit can switch a load ON or OFF (LED and motor drive circuits of ECE20A Lab).

VCC iC

RC vo

vi

VCC iC

vi

RB

RC vo

iB

The above BJT circuit is also an “inverter” or a “NOT” logic gate. Let’s assume that the “low” states are voltages between 0 to 0.5 V, “high” states voltages are between 4 to 5 V, and VCC = 5 V. When the input voltage is “low” (vi ≈ 0), BJT will be in cut-off and vo = VCC = 5 V (“high” state). When input voltage is “high,” with proper choice of RB , BJT will be in saturation, and vo = vCE = Vsat ≈ 0.2 V (“low” state). Resistor-Transistor Logic (RTL) The inverter circuit discussed above is a member of RTL family of logic gates. Plot of v o as a function of vi is called the transfer characteristics of the gate. To find the transfer characteristics, we need to find vo for a range of vi values. When vi < vγ , BJT will be in cut-off, iC = 0 and vo = VCC . Therefore, for input voltages below certain threshold (denoted by VIL ), the gate output is high. For our circuit, VIL = vγ . When vi exceeds vγ , BE junction will be forward biased and a current iB flows into BJT: iB =

vi − v γ RB

As BE junction is forward biased, BJT can be either in saturation or active-linear. Let’s assume BJT is is in saturation. In that case, vo = vCE = Vsat and iC /iB < β. Then: iC =

VCC − Vsat RC

→


iB >

iC VCC − Vsat = β βRC 61

Therefore, BJT will be in saturation only if iB exceeds the value given by the formula above. This ouccrs when vi become large enough: v i = v γ + R B iB > v γ + R B ×

VCC − Vsat = VIH βRC

Therefore, for input voltages larger than the a certain value (VIH ) , the gate output is low. For vi values between these two limits, the BE junction is forward biased but the BJT is NOT in saturation, therefore, it is in active linear. In this case, the output voltage smoothly changes for its high value to its low value as is shown in the plot of transfer characteristics. This range of vi is a “forbidden” region and the gate would not work properly in this region. This behavior can also seen in the plot of the BJT load line. For small values of vi (iB = 0) BJT is in cut-off. As vi is increased, iB is increased and the operating point moves to the left and up on the load line and enters the active-linear region. When iB is raised above certain limit, the operating point enters the saturation region.

A major drawback of the this RTL inverter gate is the limited input range for the “low” signal (VIL ). Our analysis indicated that VIL = vγ , that is the gate input is low for voltages between 0 and vγ ≈ 0.7 V. For this analysis, we have been using a piecewise linear model for the BE junction diode. In reality, the BJT will come out of cut-off (BE junction will conduct) at smaller voltages (0.4–0.5 V). To resolve this shortcoming, one can add a resistor between the base and ground (or between base and a negative power supply) as is shown. (You have seen this circuit in ECE20A, motor drive circuit.)

VCC iC

vi

RB

RC vo

iB

i2 R1

i1

To see the impact of this resistor, note that VIL is the input voltage when BJT is just leaving the cut-off region. At this point, vBE = vγ , and iB is positive but very small (effectively ECE60L Lecture Notes, Spring 2004

62

zero). Noting that a voltage vBE has appeared across R1 , we have: i1 =

vBE R1

i2 = i B + i 1 ≈ i 1 =

VIL = vi = RB i2 + vBE = vBE

vBE R1

RB RB + vBE = vγ 1 + R1 R1

This value should be compared with VIL = vγ in the absence of resistor R1 . It can be seen that for RB = R1 , VIL is raised from 0.7 to 1.4 V and for RB = 2R1 , VIL is raised to 2.1 V. R1 does not affect VIH as iB needed to put the BJT in saturation is typically several times larger than i1 . V

CC

RTL NOR Gate

RC

By combining two or more RTL inverters, one obtains the basic logic gate circuit of RTL family, a “NOR” gate, as is shown. More BJTs can be added for additional input signals. (You have seen in 20B that all higher level logic gates, e.g., flip-flops, can be made by a combination of NOR gates or NAND gates.)

vo

v1

RB

v2

RB

Exercise: Show that this ia NOR gate, i.e., the gate output will be low as long as at least one of the inputs is high. RTLs were the first digital logic circuits using transistors. They were replaced with other forms (DDT, TTL, and ECL) with the advent of integrated circuits. The major problem with these circuits are the use of large resistors that would take large space on an IC chip (in today’s chip, resistor values are limited to about 20 kΩ and capacitance to about 100 pF). Before we move on to more modern gates, we consider two important characteristics of a digital gate.


63

Switching Time and Propagation Delay: Consider the inverter gate with an input voltage close to zero (and/or negative). In this case, the BJT is in cut-off, iC = 0 and the output of the gate is high. Suppose a “high” voltage is applied instantaneously to the gate at some point. We expect BJT to enter saturation with iC = ICsat and output to drop to the “low”state. However, this does not occur instantaneously. When the BJT is in cut-off, BE junction is reversed biased. When a forward voltage is applied to the BE junction, it takes some time for the BE junction transition capacitance to charge up. Time is also required for minority carries to diffuse across the base and enter the collector. This results in the delay time td , which is of the order of a nanosecond for a typical BJT.

Before BJT can enter saturation, it should traverse the active-linear region. The rise time, tr (on the order of 1-10 ns) account for this transition. The time that takes for the gate to switch “ON” is represented by ton . Suppose that the input voltage to gate is then reduced instantaneously to low state. BJT will leave saturation region and go to cut-off. Again, this not occur instantaneously. When a BJT is in saturation, both BE and BC junctions are forward biased and conducting. As such, an excess minority charge is stored in the base. For the transistor to leave saturation and enter active-linear (BC junction to become reversed biased), this excess charge must be removed. The time required for the removal of excess charge determines the storage time, t s (order of 100 ns). Then, transistor traverses the active-linear region before entering cut-off. This account for the fall time tf (1-10 ns). The total time it takes for the gate to switch “OFF’ is represented by tof f . As can be seen, BJT switching is mainly set by the storage time, ts . Propagation delays introduced by transistor switching time are important constraints in designing faster chips. Gate designs try to minimize propagation delays as much as possible. Fan-out: All digital logic circuits are constructed with cross-coupling of several basic gates (such as NOR or NAND). As such, a basic gate may be attached to several other gates. The maximum number of gates that can be attached to a digital gate is called “fan-out.” Obviously, one would like to have large fan-out. ECE60L Lecture Notes, Spring 2004

64

Diode-Transistor Logic (DTL) The basic gate of DTL logic circuits is a NAND gate which is constructed by a combination of a diode AND gate and a BJT inverter gate. Diode AND Gate: First, let’s consider the diode AND gate as is shown. To study the behavior of the gate we will consider the state of the circuit for different values of v1 and v2 (either 0 or 5 V corresponding to low and high states). To aid the analysis, let’s assume VCC = 5 V and RA = 1 kΩ. We note that by KCL, iA = i1 + i2 (assuming that there is no current drawn from the circuit).

V

CC

iA

v1 v2

D1

i1

D2

i2

RA vo

Case 1, v1 = v2 = 0: Since the 5-V supply will tend to forward bias both D1 and D2 , let’s assume that both diodes are forward biased. Thus, vD1 = vD2 = vγ = 0.7 V and i1 > 0, i2 > 0. In this case: vo = v1 + vD1 = v2 + vD2 = 0.7 V 5 − 0.7 VCC − vo = = 4.3 mA iA = RA 1, 000 Current iA will be divided between two diodes by KCL, each carrying one half of iA (because of symmtery). Thus, i1 = i2 = 2.1 mA. Since diode currents are positive, our assumption of both diode being forward biased is justified and, therefore, vo = 0.7 V. So, when v1 and v2 are low, D1 and D2 are ON and vo is low. Again, we note that the 5-V supply will tend to forward bias Case 2, v1 = 0, v2 = 5 V: D1 . Assume D1 is ON: vD1 = vγ = 0.7 V and i1 > 0. Then: vo = v1 + vD1 = 0.7 V vo = v2 + vD2

→

vD2 = −4.3 V < vγ

and D2 will be OFF (i2 = 0). Then: VCC − vo 5 − 0.7 = = 4.3 mA RA 1, 000 i1 = iA − i2 = 4.3 − 0 = 4.3 mA

iA =

Since i1 > 0, our assumption of D1 being forward biased is justified and, therefore, vo = 0.7 V. So, when v1 is low and v2 is high, D1 is ON and D2 is OFF and vo is low. ECE60L Lecture Notes, Spring 2004

65

Case 3, v1 = 5 V, v2 = 0 V: Because of the symmetry in the circuit, this is exactly the same as case 2 with roles of D1 and D2 reversed. So, when v1 is high and v2 is low, D1 is OFF and D2 is ON and vo is low. Case 4, v1 = v2 = 5 V: Examining the circuit, it appears that the 5-V supply will NOT be able to forward bias D1 and D2 . Assume D1 and D2 are OFF: i1 = i2 = 0, vD1 < vγ and vD2 < vγ . Then: iA = i 1 + i 2 = 0 vo = VCC − i1 RA = 5 − 0 = 5 V vD1 = vo − v1 = 5 − 5 = 0 < vγ

and

vD2 = vo − v2 = 5 − 5 = 0 < vγ

Thus, our assumption of both diodes being OFF arejustified. So, when v1 and v2 are high, D1 and D2 are OFF and vo is high. Overall, the output of this circuit is high only if both inputs are high (Case 4) and the output is low in all other cases (Cases 1 to 3). Thus, this is an AND gate. This analysis can be easily extended to cases with three or more diode inputs. DTL NAND Gate: The basic gate of DTL logic circuits is a NAND gate which is constructed by a combination of a diode AND gate and a BJT inverter gate as is shown below (left figure). Because R B is large, on ICs, this resistor is usually replaced with two diodes. The combination of the two diodes and the BE junction diode leads to a voltage of 2.1 V for the inverter to switch and a VIL = 1.4 V for the NAND gate (Why?). Resistor R1 is necessary because without this resistor, current iB will be too small and the voltage across D3 and D4 will not reach 0.7 V although they are both forward biased (Recall LED driver circuit of ECE20A in which the LED started to lit for vin about 0.8 V instead of estimated 1.4 V). VCC iC iA

v1 v2

D1

i1

D2

i2

VCC iC

RC iA

RA RB

iB


vo v1 v2

D1

i1

D2

i2

RA D3

D4

iB

RC vo

R1

66

DTLs were very popular in ICs in 60s and early 70s but are replaced with TransistorTransistor Logic (TTL) circuits. TTL are described later, but as TTLs are evolved from DTLs, some examples of DTL circuits are given below. VCC

Example: Verify that the DTL circuit shown is a NAND gate. Assume that “low”state is 0.2 V, “high” state is 5 V, and BJT βmin = 40. Case 1: v1 = v2 = 0.2 V It appears that the 5-V supply will forward bias D1 and D2 . Assume D1 and D2 are forward biased: vD1 = vD2 = vγ = 0.7 V and i1 > 0, i2 > 0. In this case:

iC iA

v1 v2

D1

i1

D2

i2

1kΩ

5kΩ

v3

i4

vo

iB

D4

D3

i5

5kΩ

v3 = v1 + vD1 = v2 + vD2 = 0.2 + 0.7 = 0.9 V Voltage v3 = 0.9 V is not sufficient to froward bias D3 and D4 as v3 = vD3 + vD4 + vBE and we need at least 1.4 V to forward bias the two diodes. So both D3 and D4 are OFF and i4 = 0. (Note that D3 and D4 can be forward biased without BE junction being forward biased as long as the current i4 is small enough such that voltage drop across the 5 kΩ resistor parallel to BE junction is smaller than 0.7 V. In this case, i5 = i4 and iB = 0.) Then: i1 + i 2 = i A =

5 − v3 5 − 0.9 = = 0.82 mA 5, 000 5, 000

And by symmetry, i1 = i2 = 0.5iA = 0.41 mA. Since both i1 and i2 are positive, our assumption of D1 and D2 being ON are justified. Since i4 = 0, iB = 0 and BJT will be in cut-off with iC = 0 and vo = 5 V. So, in this case, D1 and D2 are ON, D3 and D4 are OFF, BJT is in cut-off, and vo = 5 V. Following arguments of case 1, assume D1 is ON. Again, Case 2: v1 = 0.2 V, v2 = 5 V v3 = 0.7 + 0.2 = 0.9 V, and D3 and D4 will be OFF with i4 = 0. We find that voltage across D2 is vD2 = v3 − v2 = 0.9 − 5 = −4.1 V and, thus, D2 will be OFF and i2 = 0. Then: i1 = i A =

5 − 0.9 5 − v3 = = 0.82 mA 5, 000 5, 000

and since i1 > 0, our assumption of D1 ON is justified. Since i4 = 0, iB = 0 and BJT will be in cut-off with iC = 0 and vo = 5 V. So, in this case, D1 is ON, D2 is OFF, D3 and D4 are OFF, BJT is in cut-off, and vo = 5 V. ECE60L Lecture Notes, Spring 2004

67

Case 3: v1 = 5 V, v2 = 0.2 V Because of the symmetry in the circuit, this is exactly the same as case 2 with roles of D1 and D2 reversed. So, in this case, D1 is OFF, D2 is ON, D3 and D4 are OFF, BJT is in cut-off, and vo = 5 V. Case 4: v1 = v2 = 5 V Examining the circuit, it appears that the 5-V supply will NOT be able to forward bias D1 and D2 . Assume D1 and D2 are OFF: i1 = i2 = 0, vD1 < vγ and vD2 < vγ . On the other hand, it appears that D3 and D4 will be forward biased. Assume D3 and D4 are forward biased: vD3 = vD4 = vγ = 0.7 V and i4 > 0. Further, assume the BJT is not in cut-off vBE = vγ = 0.7 V and iB > 0. In this case: v3 = vD3 + vD4 + vBE = 0.7 + 0.7 + 0.7 = 2.1 V vD1 = v3 − v1 = 2.1 − 5 = −2.9 V < vγ

vD2 = v3 − v2 = 2.1 − 5 = −2.9 V < vγ

Thus, our assumption of D1 and D2 being OFF are justified. Furthermore: 5 − 2.1 5 − v3 = = 0.58 mA 5, 000 5, 000 0.7 vBE = = 0.14 mA i5 = 5, 000 5, 000 iB = i4 − i5 = 0.58 − 0.14 = 0.44 mA i4 = i A =

and since i4 > 0 our assumption of D3 and D4 being ON are justified and since iB > 0 our assumption of BJT not in cut-off is justified. We still do not know if BJT is in active-linear or saturation. Assume BJT is in saturation: vo = vCE = Vsat = 0.2 V and iC /iB < β. Then, assuming no gate is attached to the circuit, we have iC =

5 − 0.2 5 − Vsat = = 4.8 mA 1, 000 1, 000

and since iC /iB = 4.8/0.44 = 11 < β = 40, our assumption of BJT in saturation is justified. So, in this case, D1 and D2 are OFF, D3 and D4 are ON, BJT is in saturation and vo = 0.2 V. Overall, the output in “low” only if both inputs are “high”, thus, this is a NAND gate. Note: It is interesting to note that at the input of this gate, the current actually flows out of the gate. In the example above, when both inputs were high i1 = i2 = 0, when both were low i1 = i2 = 0.4 mA, and when one input was low, e.g., v1 was low, i1 = 0.8mA. The input current flowing in (or out of the gate in this case) has implications for the fan-out capability of logic gates as is shown in the example below. ECE60L Lecture Notes, Spring 2004

68

Example: Find the fan-out of this NAND DTL gate. Assume that “low”state is 0.2 V, “high” state is 5 V, and BJT β = 40. VCC iR iA

v1 v2

iL

5kΩ

D1

i1

D2

i2

1kΩ

iB

D4

D3 i4

i5

iC

Other gates i

vo

5kΩ

The circuit is the same DTL NAND gate of previous example and we can use results from previous example here. “N ” other NAND gates are attached to the output of this gate. Fan-out is the maximum value of N . Since we want to make sure that our gate operates properly under all conditions, we should consider the worst case, when all of the second stage gates have maximum currents. For a NAND DTL gate, the maximum current i occurs when all of the inputs are high with exception of one input. We found this value to be 0.82 mA (Cases 2 & 3 in the previous example). Therefore, the worst case is when the input of all second stage gates are low (for the first stage, vo = 0.2 V) and each draw a current 0.82 mA (a total of iL = N × 0.82 mA is drawn from the first stage gate). Considering the first stage gate, we had found that vo = 0.2 V only for Case 4. For that case, we found iB = 0.44 mA. Then: 5 − 0.2 5 − Vsat = = 4.8 mA 1, 000 1, 000 iC = iR + 0.82N = 4.8 + 0.82N iR =

The first stage gate operates properly as long as the BJT is in saturation, i.e., iC < βiB

→

4.8 + 0.82N < 40 × 0.44

→

N < 13.7

As the fan-out should be integer, the fan-out for this gate is 13. Fan-out of DTL gates can be greatly increased by a small modification. Fan-out can be increased by increasing the base current of the BJT. iB is, however, limited by the current iA (and i4 ). Reducing the value of RA in the AND diode part of the circuit will have increase iB . Unfortunately, as this resistor is reduced, power dissipation in the gate increases and the fan-out capability decreases dramatically. ECE60L Lecture Notes, Spring 2004

69

A simple solution which keeps current iA small but increases iB drastically is to replace diode D3 with a BJT as is shown. As can be seen, the DTL NAND gate is now made of 3 stages: 1) input stage (diodes), 2) driver stage (first BJT) and 3) output stage (2nd BJT).

VCC iA

v1 v2

D1

i1

D2

i2

RA iC

D4

RC vo

iB

R1

Transistor-Transistor Logic (TTL) A simplified version of an IC-chip NPN transistor is shown. The device is fabricated on a p-type substrate (or body) in a vertical manner by embedding alternating layers of N and P-type semiconductors. By embedding more than one Ntype emitter region, one can obtain a multiple-emitter NPN transistor as shown. The multiple-emitter NPN transistors can be used to replace the input diodes of a DTL NAND gate and arrive at a NAND gate entirely made of transistors, hence Transistor-Transistor Logic (TTL) gates. A simple TTL gate is shown with the multiple-emitter BJT replacing the input diodes. This transistor operates in “reverse-active” mode, i.e., like a NPN transistor in activelinear mode but with collector and emitter switched. Operationally, this BJT acts as two diodes back to back as shown in the circle at the bottom of the figure. As such the operation of this gate is essentially similar to the DTL NAND gate described above (note position of driver transistor and D4 diode is switched). Similar to DTL NAND gates, a typical TTL NAND gate has three stages: 1) Input stage (multi-emitter transistor), 2) driver stage, and 3) output stage. Modern TTL gates basically have the same configuration as is shown with the exception that the output stage is replaced with the “TotemPole” output stage to increase switching speed and gate fanout. For a detailed description of TTL gate with “TotemPole” output stage, consult, Sedra and Smith (pages 1175 to 1180).


Circuit Symbol

VCC iA

RA

R2 iC

v1 v2

iB

RC vo

R1

70

5.9. Bipolar Power Devices Power devices can be classified into bipolar-based devices, MOSFET-based devices and devices such as the IGBT that combine a bipolar transistor with a MOSFET. Bipolar power devices are the traditional power devices because of their capability to provide high currents and high blocking voltages. The bipolar-based power devices include high-power bipolar transistors, Darlington transistors consisting of two transistors with a common collector, thyristors – also called silicon controlled rectifiers (SRCs) and triacs, a complementary thyristor structure suitable to control AC power. Power MOSFETs and power devices that combine MOSFETs and bipolar transistors are covered in chapter 7.

5.9.1. Power BJTs High power bipolar transistors are conceptually the same as the bipolar transistors described in chapter 8. The main difference is that the active area of the device is distinctly higher, resulting in a much higher current handling capability. Power BJTs also have a thick and low-doped collector region. Such collector regions result in a large blocking voltage. Extremely low doping densities, down to 1013 cm-3 , are use to obtain blocking voltages as large as x000 V. As a result, one finds that the structure needs to be redesigned to a) effectively manage the power dissipation and b) avoid the Kirk effect. The power dissipation is managed by minimizing the power dissipation and spreading the resulting heat dissipation onto a large area. The Kirk effect is normally avoided by increasing the collector doping density. However, for devices with a very high blocking voltage, this may not be an option. Power BJTs therefore are operated at rather low current density of 100 A/cm2 since the lower current density reduces the power dissipation per unit area and eliminates the Kirk effect. Large currents – up to 1000 A – are obtained by making a large area device. Silicon BJTs dominate the power device market, in part because of the low cost of large area silicon devices and the high thermal conductivity of silicon compared to GaAs. Silicon carbide (SiC) has been hailed as the perfect material for high-power BJTs. The higher thermal conductivity (3x) and breakdown field (10x) compared to silicon give it a clear performance advantage. The high saturation velocity (3x compared to silicon) also shifts the onset of the Kirk effect to higher current densities. The proliferation of its use will heavily depend on the material cost and quality of the SiC wafers.

5.9.2. Darlington Transistors Darlington transistors contain two transistors connected in an emitter-follower configuration, while sharing the same collector contact. This structure can be fabricated with the same technology as a single BJT as shown in Figure 5.9.1. The key advantage of the Darlington configuration is that the total current gain of the circuit equals the product of the current gain of the two devices. The disadvantage is the larger saturation voltage. Since the two devices share the same collector, the saturation voltage of the Darlington pair equals the forward bias voltage of transistor Q2 plus the saturation voltage of transistor Q1. Since the forward bias voltage is much larger than the saturation voltage, the saturation voltage of the Darlington pair is also significantly larger. This larger voltage results in a larger on-state power dissipation in the device.

Q1 Collector

Q2

Base

Emitter

Base Q1

p

n+

p

n+

n-

Q2 n+ substrate Emitter

a)

Collector

b)

Figure 5.9.1. Darlington transistor structure a) equivalent circuit b) device crosssection.

5.9.3. Silicon Controlled Rectifier (SRC) or Thyristor The silicon controlled rectifier is 4-layer device with alternating n-type and p-type layers as shown in Figure 5.9.2. This devices is also referred to as a pnpn structure or Thyristor. Such device can in principle be made using any semiconductor. However, silicon thyristors are the most common thyristors. The advantage of the structure is that it provides a high power handling capability, high blocking voltage and high gain with a very low on-state resistance. The operation of the device is best explained by considering the equivalent circuit, shown in Figure 5.9.2. It consists of two bipolar transistors, a n-p-n transistors, Q1, and a p-n-p transistor, Q2. Both transistors share a p-type and n-type layer. For instance, the p-type base layer of transistor Q1 is also the collector layer of transistor Q2, while the n-type base of transistor Q2 is also the collector of transistor Q1. The Thyristor is controlled by the gate electrode, which is the gate of Q1. By applying a current to the gate one forward biases the base-emitter junction of Q1, which leads to a collector current in Q1, which in turn provides a base current to Q2. Since Q2 is a complementary p-n-p transistor, this negative current also forward biases the base-emitter junction of transistor Q2, resulting in collector current which forms an additional base current into the base of transistor Q1. The applied current to the gate of the Thyristor therefore causes an additional current into Q1, which can be large enough that both transistors remain in turned on even if the original gate current is removed. This latching behavior is not unlike that of a flipflop, where the inputs of two devices are connected to the output as shown in Figxxx. This selfsustaining effect will occur if the product of the current gain of both transistors equals unity, while one of the transistors can have a current gain less than unity. As a result one has considerable flexibility to choose the doping density and thickness of each of the layers to obtain a high blocking voltage and high Early voltage for each transistor, while maintaining sufficient current gain. The Thyristor has a lower on-state voltage than the Darlington pair and typically requires an

even smaller turn-on current, which only needs to be applied temporarily because of the internal positive feedback between the two transistors of the equivalent circuit. This latter property is also the main disadvantage of the Thyristor: since the device latches into the on-state once sufficient gate current is supplied, the device can not be turned off by removing the gate current. Instead one has to disconnect the power supply to turn off the device. Furthermore, since both transistors are in saturtion in the on-state, a significant amount of minority carriers are accumulated in the base region of each transistor. These minority carriers must be remove prior to reconnecting the power supply since these carriers would temporarily lead to a base current in each device and trigger the turn-o of the Thyristor. Finally, one has to slowly ramp up the power supply voltage to avoid the so-called dV/dt effect. Since a rapid increase of the applied voltage with time causes a displacement current proportional to the capacitance of the junctions, this displacement current could again provide a temporary base current in Q1 and Q2, which is large enough to trigger the Thyristor.

Cathode

Gate

Cathode

Q1 Anode

Cathode

n+ p

p+ Q1

n Gate

Gate

Q2

Q2

p+ substrate Anode Anode

Figure 5.9.2. Thyristor structure: a) circuit symbol, b) device cross-section and c) equivalent circuit. A very attractive feature of a Thyristor is that it can be scaled easily to very large area devices even if that causes a significant lateral resistance though the thin and lowly-doped base and collector regions. As one applies a current to the gate electrode, the Thyristor would be triggered locally. The turned-on region would then spread laterally thoughout the structure without a need for an additional gate current. The local triggering also exists in the light-controlled Thyristor. This structure does not contain a gate electrode. Instead the p-n-p-n structure is locally illuminated with photons whose energy exceeds the bandgap energy of the semiconductor. The photogenerated current then acts as the gate current, which triggers the Thyristor. Gate turn-off Thyristor (GTO)

5.9.4. DIode and TRiode AC Switch (DIAC and TRIAC) The diode AC switch and the triode AC switch are very similar to the thyristors, since they both are latching multi-layer device structures. Both are meant to be used in AC powered systems and therefore respond similarly to positive and negative applied voltages. The circuit symbols and layer structures are shown for both devices in Figure 5.9.3. The diode AC switch also referred to

as DIAC consists of a gate-less pnpn structure connected in parallel to a gate-less npnp structure. This device therefore acts like an open circuit until the threshold voltage is reached - either positive or negative – after which the device acts as a short. To achieve this function one starts with a pnp structure. An n+ region is added to the front and the back to yield the DIAC structure. The triode AC switch (TRIAC) also contains the same vertical structure as a DIAC. In addition a contact is made to the p-type gate of the npnp structure as well as the n-type gate of the pnpn structure. This additional gate contact allows lowering the threshold for latching for both positive and negative applied voltages applied between terminal 1 and terminal 2.

Terminal 1

Terminal 2

Terminal 1

Terminal 1

Terminal 1

n+ p

n+ p

n

n

p

n+

Terminal 2

p

Terminal 2

Gate

Gate

n+

n+

Terminal 2

Figure 5.9.3. Circuit symbol and device cross-section of a) a Diode AC switch (DIAC) and b) a Triode AC switch (TRIAC).

PHY2003 (Practical Electronics II)

Homework

Worksheet 9

Bipolar Junction Transistors Introduction PHY2003 does not require a knowledge of the semiconductor physics underlying how transistors work, they are treated as nonlinear three-terminal devices. Figure 1 defines the current conventions used in PHY2003. The rules-of-thumb for analysing bipolar junction transistor (BJT) circuits at lowfrequencies are: NPN: VC > V B = V E + 0.6 V

(9.1)

PNP: VC < V B = V E − 0.6 V NPN: V B < V E + 0.6 V  if   then IC = 0 else IC = hFE IB  PNP: V B > V E − 0.6 V 

(9.2)

typically 50 < hFE < 500 therefore IE ≈ −IC .

(9.3)

Required Reading Storey (1998) chapter 7, sections 7.1–7.6, pages 234–287. Another source of the required information are the WWW references listed under:

+12V

VC

VB

NPN IB

VE PNP

IC VB IE VE

R1 R2 C1 X1

1M 3K3 10N BC107

R1

3

C1

IE

IB

V1

R2

2

V3 X1

IC VC

Figure 9.1 Current conventions

Circuit 9.1 Common Emitter Amplifier 1

PHY2003 (Practical Electronics II)

Homework

Worksheet 9

12V R1

C1

R3 4

V1

V4

2

C1 R1 R2 R3 R4 X1

X1

0µ1 33K 10K 2K7 1K0 BC107

3

R2

R4

Circuit 9.2 Series Feedback Amplifier

Exercise 9.1

Analyse circuit 9.1 using typical values from the BC107 datasheet and find: (a) the quiescent voltage at node 3, (b) the DC impedance of node 2 and hence the low-frequency –3 dB point (c) the small-signal voltage gain v3 v1 at 1 kHz and 10 kHz.

Answers:

(a) 6.4 V (assuming HFE = 150) (b) 2.2 kΩ, 7.2 kHz (c) –60 and –400

Exercise 9.2

Analyse circuit 9.2 using typical values from the BC107 datasheet and find: (a) the quiescent voltage at node 3 (b) the quiescent voltage at node 4 (c) the small-signal gain v4 v1 at 1kHz

Answers:

(a) 2.1 V (b) 6.3 V (b) –60 and –400 (c) v4 v1 = −2.7

© Copyright CDH Williams University of Exeter 2003 CW030907/1 2

University of Geneva

TPA-Electronique

Circuits with Transistors Contents 1 Transistors

1

2 Amplifiers 2.1 h parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 3

3 Bipolar Junction Transistor (BJT) 3.1 BJT as a switch . . . . . . . . . . . . 3.2 Small signal BJT amplifiers . . . . . 3.2.1 r parameters . . . . . . . . . 3.2.2 Common Emitter Amplifier . . 3.2.3 Common Collector Amplifier . 3.2.4 Common Base Amplifier . . .

. . . . . .

3 6 6 9 9 10 11

4 Field Effect Transistors (FET) 4.1 Small signal FET amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 11

5 Power amplifiers 5.1 Class A power amplifiers . . . . . . . . 5.1.1 Voltage and power gain . . . . 5.1.2 Power gain . . . . . . . . . . . 5.1.3 Efficiency . . . . . . . . . . . . 5.2 Class B and class AB power amplifiers 5.2.1 Efficiency . . . . . . . . . . . . 5.3 Class C power amplifiers . . . . . . .

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11 12 12 12 12 13 14 15

6 Differential amplifier 6.1 Two inputs and two ouputs . 6.2 One input and two ouputs . 6.3 Two inputs and one ouputs 6.4 One input and one ouput .

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7 Darlington and Sziklai connections

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17

Transistors

Transistors are three terminal semicounductor amplifying device that regulates current or voltage. A small change in the current or voltage at an inner semiconductor layer (which acts as the control electrode) produces a large, rapid change in the current passing through the entire component. The component can thus act as a switch, opening and closing an electronic gate. A transistor is a active device that can amplify, producing an output signal with more power in it than the input signal

E. Cortina

Page 1


TPA-Electronique RS vs

ii

vi

Ri

Input source

RO

Avi

vo

Amplifier

RL

Load

Figure 1: Thevenin’s equivalent of an amplifier with signal source connected to input and a load impedance connected to the ouput

There are two kind of transistors, the bipolar transistor (also called the junction transistor), and the field effect transistor (FET). Invented in 1947 at Bell Labs, transistors have become the key ingredient of all digital circuits, including computers. Prior to the invention of transistors, digital circuits were composed of vacuum tubes, which had many disadvantages: they were much larger, required more energy, dissipated more heat, and were more prone to failures. For a good introduction about vacuum tubes and how to use them visit the web page http://www.hans-egebo.dk

2

Amplifiers

An amplifier is a device that takes an input signal and magnifies it by a factor A where vout = Avin . These gain is the so called open-loop gain. In order to study how an ideal amplifier looks like, an amplifier has been sketched in figure 1. In this figure the amplifier has been replaced by a Thevenin’s equivalent and an input source and output load have been added. In these conditions the “real” amplification factor (Ar ) can be expressed as: Av

Ar =

i io R L vo R R = = o L RL vs vs vs

taking into account that the input source equivalent circuit we can state vi = vs

Ri Rs + Ri

and substituting in the upper expression Ar = A

Ri RL Rs + Ri Ro + RL

Looking that expression we can easily sees that the real gain is smaller than the open-loop gain. For an ideal amplifier we can express that: a) Ri → ∞, so the entire source voltage vs is developed across Ri . In other words all vs is placed across the amplifier input and the input source vs does not have to develop any power (ii = 0 when Ri = ∞) b) Ro → 0 so all the availabe voltage is developed across RL and none of it is lost internally. c) A → ∞ for obvious reasons. d) A should be constant with frequency, that is, amplify all frequencies equally.

E. Cortina

Page 2


TPA-Electronique

i1

i2

v1

h

v2

h

11

v

12 2

h

i

21 1

h

22

Figure 2: h parameters definition

2.1

h parameters

An amplifier can be seen as a quadrupole. h parameters cames from a direct application of Thevenin theorem to the input dipole and Norton theoreme to the output dipole. See figure 2. The Kirchoff equations for this model are: v1 = h11 i1 + h12 v2 i2 = h21 i1 + h22 v2 If the output is short-circuited v2 = 0 then h11 =

v1 i1

= hi

input impedance

h21 =

i2 i1

= hf

current gain

If the input is open i1 = 0 h12 =

v1 v2

= hr

inverse voltage gain

h22 =

i2 v2

= ho

output admitance

These four last relations gives the meaning of the h parameters. Beware, that the meaning is with the conditions imposed up, that is, output short-circuit (no load) and open input (no input). Typical values of these parameters are: h11 = 3.5kΩ h12 = 1.3 × 10−4 h21 = 120 h22 = 8.5µS

3

Bipolar Junction Transistor (BJT)

A bipolar junction transistor is a device based in three area semiconductor material with two diode junction. There are two types of BJT, the so called npn and pnp transistors, dependig obviously on doping of each area. It is called bipolar because both electrons and holes are involved in its operation. The trhee regions are called emiter, base and collector. In figure 3 are shown both types of BJT and the majority current flow. In order to show the transistor effect, the diode polarization should be correct, that is, the emitter-base is in forward bias and the base-collector in reverse bias. In a NPN transistor:

E. Cortina

Page 3


TPA-Electronique

forward biased

reverse bias

n+

p

emiter

base

n

collector

VEE

n

emiter

base

p

collector

VEE

VCC

I c = αIe

Ie

p+

VCC

I c = αIe

Ie

Ι b = (1−α ) Ιe

e

Ι b = (1−α ) Ιe

c

e

b

c b

Figure 3:

a) Electrons are majoritary carriers in the emitters, so they can pass with no problems to the base. As the emitter is intended to provide the charge carriers will be heavely doped. b) The base is slightly doped and made very thin. This allows that the recombination current, that will exit by the base is small and that the diffussion length is longer than the base length and consequently almost all electrons from emitter will pass to the collector c) Once in the collector, the electrons will exit by the lead. For PNP transistors the explanation is exactly the same just changing electrons for holes and inversing the currents. In order to study the transistor we are going to mount the so called common emitter configuration. In figure 4 is shown how this configuration. The parameters αcc and βcc , defined for direct current are: αcc =

IC ∼ 0.99 IE

βcc =

IC ∼ 100 IB

αcc 1 − αcc In the right side of the figure 4 have been plotted a family of characterisic courbes of a transistor. For a fixed value of VBB , that fix IB , we can increase VCC from 0V. For lower values of VCC both diodes are forward bias so VCE will increase accordingly, this region is called saturation. With VCC high enough will enter in the active or linear region, where the base-collector jounction is reverse bias. At this moment IC becames stable (or almost) and IE = IB + IC → βcc =

E. Cortina

Page 4


TPA-Electronique

Rc Rb

VCB VBE

vs

+ VCE

−

VCC

+ VBB

− Breakdown region

IC I B8

I B7

Saturation regeion

I B6

I B5

I B4

I B3

I B2

I B1

IB = 0 Blockage region

VCE

Figure 4: Transistor charactersitic curves IB1 < IB2 < IB3 ,etc

E. Cortina

Page 5


TPA-Electronique IC

Ic

Ib A

Q

I CQ

I BQ B

VCEQ

VCE Vce

Figure 5: Q point. Variations induced in collector current IC and VCE by a variation of the base current IB

does not change with VCE . In fact, IC increas just a bit due to the larger depletion region in the base-collector junction. So in this region the value of IC is controlled by IB in such a way that IC = βCC IB . With VCE large enough the base-collector junction breakdown increasing IC quickly. Note that if IB = 0 then IC = 0 so the transistor does not conduct. In this situation thetransistor is in the so called blockage state. Applying directly Kirchoff’s laws to the circuit we can find directly in the output circuit that the summation of voltages around the loop gives VCC − IC RC − VCE = 0 IC =

1 VCC − VCE RC RC

this is the equation of a straight line, known as load line. Superimposing the load line on the output characteristics in effect gives us a graphical solution to two simultaneous equations: one equation, belonging to the transistor, non-linear equation given by the family of IC −V CE graphs, and the other the load line. The intersection points show the possible values that may exist in the circuit. In absence of the any input signal, vs = 0, the operational point is called Q-point. In case of an input signal provoques the variation of the VCE value, modifiyng consequently the operational point. In figure 5 is shown how the operational point moves in the transistor characteristic-plot.

3.1

BJT as a switch

One of main utilities of BJT are as electronic switches. If the transistor is in blockage, then the transistor can be seen as an open circuit. On the other hand, if the transistor is in saturation, then the transistor can be seen as a closed circuit.

3.2

Small signal BJT amplifiers

We can found three types of small signal BJT amplifier configurations as shown in figure 7:

E. Cortina

Page 6


TPA-Electronique +VCC

+VCC

IC = 0

RC RB

+VCC

RC

I sat C

RC

RC

RB

C

0V

C

+VBB

E

IB = 0

+VCC

E

IB

Figure 6: Transistor view as an electronic switch

• Common Emitter. From AC point of view the emitter is connected to the ground. Input signal is in the base and output in the collector • Common Collector. From AC point of view the collector is connected to the ground. Input signal is in base and output in the emitter. • Common base. From AC point of view the base is connected to the ground. Input signal is in the emitter and output in the collector. +VCC

R1 RS

V in

RC

+VCC

C3

R1

V out

C1

Rs

V in

C1 C2

R load v

s

R2

RE

v

C2

R2

s

RE

V out R load

+VCC

C2

V in s

RC

C3

V out

R load

C1

Rs v

R1

R2

RE

Figure 7: The three amplifier configurations. On the left the common emitter amplifier, in the center the common collector amplifier and on the left the common base amplifier

In figure 8 are shown the definition of h parameters for these three configurations. In table 1 are shown the ratios for the three configurations.

E. Cortina

Page 7


TPA-Electronique

Common Emmiter

Common Base

Common Collector

hie = Vb /Ib

hib = Ve /Ib

hic = Vb /Ib

hre = Vb /Vc

hrb = Ve /Vc

hrc = Vb /Ve

hf e = Ic /Ib

hf b = Ic /Ib

hf c = Ie /Ib

hoe = Ic /Vc

hob = Ic /Vc

hoc = Ie /Ve

Table 1: h parameters ratios for the three amplifier configurations

h

h

ie

Base

Collector ib

h

re

vc

h

fe

ib

h

ic

Emitter

Base ib

oe

h

rc

ve

h

fc

ib

h

oc

Collector

Emitter

Common Collector

Common Emitter

h

ib

Collector

Emitter ie

h

rb

vc

h

fb

ie

h

ob

Base Common Base

Figure 8: h parameters definition

E. Cortina

Page 8

University of Geneva 3.2.1

TPA-Electronique

r parameters

It is much more easy to work with resistances than with h-parameters. This is why has been defined a second set of parameters, called r-parameters. Their definitions are: αca

Alpha AC (Ic /Ie )

βca

Alpha AC (Ic /Ib )

re0

AC resistance at emitter

rb0

AC resistance at base

rc0

AC resistance at collector

The relationship between both set of parameters is αca = hf b βca = hf e 25mV hre ' hoe IE hre + 1 rc0 = hoe hre rb0 = hie − (1 + hf e ) hoe re0 =

3.2.2

Common Emitter Amplifier

• The input is at base and the output is at collector • There is a phase inversion between input and output • C1 and C3 are coupling capacitors for input and output signals • C2 is the so called derivation capacitor allows the maximum gain at the setup. • The reactance of all capacitors should be negligable at operational frequency. • Emitter is connected to ground from AC point of view. Direct current relations

VB =

R2 ||βCC RE R1 + R2 ||βCC RE

VCC

VE = VB − VBE VE IE = RE VC = VCC − IC RC Alternative current relations re0 =

E. Cortina

25mV IE Page 9


TPA-Electronique Rin = βca re0 Rout ' RC RC Av = 0 re Vb Av Vout IC Ai = Iinp

A0v =

Ap = A0v Ai 3.2.3

Common Collector Amplifier

• Input is at base and output at the emitter. • There is no phase inversion between input and output • Input resistance is high and output resistance is low • Maximal gain in voltage is 1. • The collector is connected to ground from the AC point of view. • The capacitor reactance must be negligable at the operating frequency Direct current relations

VB =


VCC

VE = VB − VBE VE IE = RE VC = VCC Alternative current relations re0 =

25mV IE

Re = RE ||Rcharge Rin = βca (re0 + Re ) Rs Rout = ||RE βca Av =

Re re0 + Re

Ai =

Ie Iinp

A p = Ai

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University of Geneva 3.2.4

TPA-Electronique

Common Base Amplifier

• Input is at emitter and output at collector • There is no phase inversion between input and output • Input resistance is low and output resistance is high • Maximal current gain is 1. • Base is connected to AC ground Direct current relations

VB =


VCC

VE = VB − VBE VE IE = RE VC = VCC − IC RC Alternative current relations re0 =

25mV IE

Rin ' re0 Rout ' RC Rc = RC ||Rcharge Av '

Rc re0

Ai ' 1 A p ' Av

4 4.1

5

Field Effect Transistors (FET) Small signal FET amplifiers

Power amplifiers

Up to now we have studied single stage amplifiers, but a practical amplifier consists of several stages which are cascaded to produce a gain high enough in order to drive a signal. Typically input signals (from a microphone, a radio station or a particle detector), are on the order of µV , whereas usable signals should be in the volt range. Once the signal is in this range, it can be considered inmune from interference by noise or other disturbing signals. Firsts stages of the amplifier are voltage gain amplifiers as the ones we have seen previously coupled either directly or via a capacitor or a transformer. Usually the last stage of an amplifier is a power amplifier. This section does not contribute to voltage gain, it is basically

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TPA-Electronique

a current amplifier. Another way of looking at it is that the voltage section is a signal amplifier with no significant power an its output. It is the task of the power amplifier to produce substantial power at the output, which it does by amplifying the currents. Power amplifiers should be feed by large noise-free voltage signals. There are four different power amplifiers, called of class A, class B, class AB and class C. This classification is determined by the percentage of input cycle that the amplifier works in the linear region.

5.1

Class A power amplifiers

A class A amplifier is an amplifier polorized in such a way that it works in the linear region for the whole cycle (360o ). In this mode the transistor never enters in the blockage or saturation region so the output signal is an amplified copy of the input one. A class A amplifier is equal as any of the small signal amplifier presented before. As an example we will use a common emitter amplifier in the same configuration as in figure 7. As we are dealing with big signals the optimal operational Q-point is the one that is centered in the load line. In case of asymmetry the output signal will be limited by the closest point of blockage or saturation. The condition needed to center the Q-point in the case of an common emitter amplifier is: VCEQ = ICQ Rc 5.1.1

Voltage and power gain

Voltage and power gain are the same as in small signal amplifiers, Av =

Rc re0

Ai = βCC the only difference is that the formule re0 ∼ 25mV /IE is not longer valid because the big oscillations of the signals almost covers the transconductance curve IC vs VBE , as is shown in figure 9. As re0 = ∆VBE /∆IC the value is bigger in the lower part of the curve than in the upper part. This behaviour can produce some distorsions due to the different gain. The only way to reduce this distorsion is to work in the most linear region. 5.1.2

Power gain

The gain in power is: Ap = Ai Av = βCC Av = βCC 5.1.3

RC re0

Efficiency

Efficiency (η) is given by the ratio of AC signal power to DC power supplied. η=

E. Cortina

PAC 0.5 = = 0.25 PDC 2 Page 12


TPA-Electronique IC

∆I C2

Q

∆I C1

∆VBE

∆VBE

Figure 9: Variation of re0 over the transconductance curve V cc

v v

in

v

in

v

out

out

RE

Figure 10: Class B amplifier in common collector

where

5.2

1 1 PAC = √ VCEQ √ ICQ = 0.5VCEQ ICQ 2 2 PCC = 2VCEQ ICQ

Class B and class AB power amplifiers

A class B power amplifier is an amplifier in which the transistor is polarized at the blockage point, in such a way that will operate in the linear region only half of the cycle (180o ). The advantage of this kind of setups is that the efficiency is bigger than in a class A amplifier, on the other hand, if we need to amplify the whole cycle we need to build a set up with two transistors in the so called push-pull amplifier. In figure 10 is shown how it works a class B common collector a mplifier. As it has been said the operational Q-point is at blockage, so while the signal is in the positive region the transistor will be in the linear reagion, but once the signal is lower enough to make VBE < 0.7V then the transistor is in blockage and will not conduct. Due to this the output signal is not a copy of the input signal. In order to amplify the whole cycle, we have to build the push-pull setup, composed by two follower emitters, once made with a npn and the oter with a pnp. In figure 11 is shown the principle of this setup. The principle is the same as explained before for the npn. The pnp will have the same behavour but when the signals polarities changed. As it has been said

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TPA-Electronique V cc

V cc

Q1

v

in

v

Q2

Q1 out

v

RL

in

−Vcc

Q2

v

out

RL

−Vcc

v

in

v

out

Figure 11: In the upper plot is shown how a class push-pull works. In the lower plot is shown the distorsion in the push-pull amplifier. The transistors onlye are propoerly polarized in the shadowed regions.

around a base polarisation region around 0V none of the transistors will conduct, because both base-emitter junctions will not be properly polarized, what produces a gap in the output, known as crossover distorsion. In order to avoid this gap, both transistors should be slightly polarized before the blocakge point. This variation is called as class AB amplifier. In the case of the push-pull setupt this polarization can be done either by a resistor divider or with a couple of diodes. This last configuration is prefered because its behaviour with the temperature is much stable. In figure 12 are shown both setups. 5.2.1

Efficiency η=

PAC = 0.25π = 0.79 PDC

where

1 1 PAC = √ VCEQ √ ICQ = 0.5VCC ICsat 2 2 For each transistor, output is a half-wave signal, so the current mean value is PCC =

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VCC ICsat π

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TPA-Electronique V cc

C1

R1

C1 Q1

v

V cc

C3

v

R2

in

Q1 D1

out

v Q2

C2

R1

R3

v

out

D2

in

RL

C3

Q2 C2

RL

R2

Figure 12: Push-pull polarization in class AB in order to avoid the crossover distorsion

5.3

Class C power amplifiers

Class C amplifiers are polarized in order to allow conduction in less that half cycle. The efficiency is much higher that the rest of power amplifiers, but the wave form is severely distorted. They are used usually for radio frequency resonance amplifiers.

6

Differential amplifier

Is a configuration used to amplify the difference voltage between two input signals. In the ideal case the output is enterely independent of the individual signals levels (only difference matters). When both inputs change levels togethers that’s a common-mode input change. A differential change is called normal-mode. With discrete components one can imagine four configurations, show in figure 13, regarding the number of input and outputs possibles. The output tension in all cases can be expressed in the form: vo = Adif f (v1 − v2 ) The input that is in phase with the output (v1 ) is called non-inverting input, while the other (v2 ), that has opposite phase with the output is called inverting output. The gain Adif f will change for each configuration. This gain is called differential gain.

6.1

Two inputs and two ouputs

This amplifier is sketched in figure 13-a . This is the most general differential amplifier. The output is taken between both collectors. Ideally the circuit is symetric, that is both transistors and resistors are identical everywhere. In this case, if v1 = v2 the output will be 0. The gain is calculated as: RC Adif f = (R1 + RE + re0 )

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TPA-Electronique

+VCC

+VCC

RC

RC

RC

RC

vo

vo

v1

v2 RE

v1

RE

RE

RE

R1

R1

−VEE

−VEE

+VCC

+VCC

a)

b)

RC

RC vo

v1

v2 RE

RE

vo v1 RE

RE

R1

−VEE

c)

R1

−VEE

d)

Figure 13: Differential amplifiers: a) Two inputs, two outputs. b) One input, two outputs. c) Two inputs, one output. d) One input, one output

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6.2

TPA-Electronique

One input and two ouputs

In case that one of the inputs it is not used, this should be connected to the ground. This amplifier is sketched in figure 13-b. The gain is also Adif f = RC /(R1 + RE + re0 ). The applications of two outputs differential amplifiers are quite rare because they need a floating charge, that should be connected between both collectors, while usual charges has one end connected to the ground.

6.3

Two inputs and one ouputs

This amplifier, sketched in figure 13-c is by far the most useful. Please note that the amplifier is not symetric anymore, and the non-inverting input is clearly defined. Usually one people talk about operational amplifier is talking about this configuration. The gain is calculated as: Adif f =

RC 2(RE + re0 )

. The factor 2 cames from the fact that there is only one RC . The input impedance (for any of both inputs) is: ri = 2βre0 . The common mode input gain is expressed as: ACM = −

RC 2R1 + RE + re0

An important parameter is the so called Common Mode Rejection Ratio (CMRR), that express, usually in db, the ratio of responso of normal mode signal to the response for a common-mode signal of the same amplitude. CMRR is defined then as: CM RR =

Adif f 2R1 + RE + re0 = ACM 2(RE + re0 )

For usual configurations R1 >> RE + re0 so CM RR '

R1 RE + re0

The discussion about differential amplifiers in “Principes d’Electronique” by P. Malvino is excellent.

6.4

One input and one ouput

Sketched in figure 13-d. One of the inputs is not used so it is connected to ground. The gain is Adif f = RC /2(RE + re0 ).

7

Darlington and Sziklai connections

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ECE 1201 BJT Transistors

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