lec1-10 opamp

Electrical engineering

Analog Circuits

Prof.Pramod Agarwal

Operational Amplifier > Lecture 1 > Lecture 2 > Lecture 3 > Lecture 4 > Lecture 5 > Lecture 6 > Lecture 7 > Lecture 8 > Lecture 9 >Lecture 10

Lecture - 4: Biasing of Differential Amplifiers

Constant Current Bias: In the dc analysis of differential amplifier, we have seen that the emitter current IE depends upon the value of βdc. To make operating point stable IE current should be constant irrespective value of βdc. For constant IE, RE should be very large. This also increases the value of CMRR but if RE value is increased to very large value, IE (quiescent operating current) decreases.

OPAMP Apllications >Lecture 11 > Lecture 12 > Lecture 13 > Lecture 14 > Lecture 15 > Lecture 16 > Lecture 17 > Lecture 18 > Lecture 19 > Lecture 20

To maintain same value of IE, the emitter supply VEE must be increased. To get very high value of resistance RE and constant IE, current, current bias is used.

Oscillator > > > > > >

Lecture Lecture Lecture Lecture Lecture Lecture

21 22 23 24 25 26

Voltage Regulator > > > >

Lecture Lecture Lecture Lecture

27 28 29 30

file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec4a.htm (1 of 4) [12/5/2010 1:54:29 AM]

Figure 5.1


Fig. 1, shows the dual input balanced output differential amplifier using a constant current bias. The resistance RE is replace by constant current transistor Q3. The dc collector current in Q3 is established by R1, R2, & RE. Applying the voltage divider rule, the voltage at the base of Q3 is

Because the two halves of the differential amplifiers are symmetrical, each has half of the current IC3.

The collector current, IC3 in transistor Q3 is fixed because no signal is injected into either the emitter or the base of Q3. Besides supplying constant emitter current, the constant current bias also provides a very high source resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all the performance equations obtained for differential amplifier using emitter bias are also valid. As seen in IE expressions, the current depends upon VBE3. If temperature changes, VBE changes and current IE also changes. To improve thermal stability, a diode is placed in series with resistance R1as shown in fig. 2.



Fig. 2 This helps to hold the current IE3 constant even though the temperature changes. Applying KVL to the base circuit of Q3.

Therefore, the current IE3 is constant and independent of temperature because of the added diode D. Without D the current would vary with temperature because VBE3 decreases approximately by 2mV/° C. The diode has same temperature dependence and hence the two variations cancel each other and IE3 does not vary appreciably with temperature. Since the cut – in voltage VD of diode approximately the same value as the base to emitter voltage VBE3 of a transistor the above condition cannot be satisfied with one diode. Hence two diodes are used in series for VD. In this case the common mode gain reduces to zero.



GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 4: Biasing of Differential Amplifiers Some times zener diode may be used in place of diodes and resistance as shown in fig. 3. Zeners are available over a wide range of voltages and can have matching temperature coefficient The voltage at the base of transistor QB is


Fig. 3 The value of R2 is selected so that I2 ≈ 1.2 IZ(min) where IZ is the minimum current required to cause the zener diode to conduct in the reverse region, that is to block the rated voltage VZ.



21 22 23 24 25 26



27 28 29 30

Current Mirror: The circuit in which the output current is forced to equal the input current is said to be a current mirror circuit. Thus in a current mirror circuit, the output current is a mirror image of the input current. The current mirror circuit is shown in fig. 4.

file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec4b.htm (1 of 3) [12/5/2010 2:13:57 AM]


Fig. 4 Once the current I2 is set up, the current IC3 is automatically established to be nearly equal to I2. The current mirror is a special case of constant current bias and the current mirror bias requires of constant current bias and therefore can be used to set up currents in differential amplifier stages. The current mirror bias requires fewer components than constant current bias circuits. Since Q3 and Q4 are identical transistors the current and voltage are approximately same



For satisfactory operation two identical transistors are necessary. GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal




Example - 1 Design a zener constant current bias circuit as shown in fig. 5 according to the following specifications. (a). Emitter current -IE = 5 mA (b). Zener diode with Vz = 4.7 V and Iz = 53 mA. (c). βac = βdc = 100, VBE = 0.715V (d). Supply voltage - VEE = - 9 V. Solution: From fig. 6 using KVL we get

Fig. 5



21 22 23 24 25 26

Practically we use RE = 820 kΩ



27 28 29 30

Practically we use R2 = 68 Ω The designed component values are: RE = 860 Ω

file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec4c.htm (1 of 3) [12/5/2010 2:11:43 AM]


R2 = 68 Ω

Example - 2 Design the dual-input balanced output differential amplifier using the diode constant current bias to meet the following specifications. 1. supply voltage = ± 12 V. 2. Emitter current IE in each differential amplifier transistor = 1.5 mA. 3. Voltage gain ≤ 60.

Solution: The voltage at the base of transistor Q3 is

Assuming that the transistor Q3 has the same characteristics as diode D1 and D2 that is VD = VBE3, then

Practically we take RE = 240 Ω.


Fig. 6


Practically we take R2 = 3.6 kΩ.

To obtain the differential gain of 60, the required value of the collector resistor is

The following fig. 7 shows the dual input, balanced output differential amplifier with the designed component values as RC = 1K, RE = 240 Ω, and R2 = 3.6KΩ.

Fig. 7

GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal








21 22 23 24 25 26



27 28 29 30


Figure 5.1











GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal







21 22 23 24 25 26



27 28 29 30










Analog Circuits

Prof.Pramod Agarwal





Fig. 5



21 22 23 24 25 26




27 28 29 30




R2 = 68 Ω






Fig. 6





Fig. 7

GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal








21 22 23 24 25 26



27 28 29 30


Figure 5.1











GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal







21 22 23 24 25 26



27 28 29 30










Analog Circuits

Prof.Pramod Agarwal





Fig. 5



21 22 23 24 25 26




27 28 29 30




R2 = 68 Ω






Fig. 6





Fig. 7

GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 5: The Operational Amplifiers

The operation amplifier: An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential (OPAMP) amplifiers and followed by a level translator and an output stage. An operational amplifier is available as a single integrated circuit package. The block diagram of OPAMP is shown in fig. 1.




21 22 23 24 25 26

Fig. 1 The input stage is a dual input balanced output differential amplifier. This stage provides most of the voltage gain of the amplifier and also establishes the input resistance of the OPAMP.The intermediate stage of OPAMP is another differential amplifier which is driven by the output of the first stage. This is usually dual input unbalanced output. Because direct coupling is used, the dc voltage level at the output of intermediate stage is well above ground potential. Therefore level shifting circuit is used to shift the dc level at the output downward to zero with respect to ground. The output stage is generally a push pull complementary amplifier. The output stage increases the output voltage swing and raises the current supplying capability of the OPAMP. It also provides low output resistance.



27 28 29 30



Level Translator: Because of the direct coupling the dc level at the emitter rises from stages to stage. This increase in dc level tends to shift the operating point of the succeeding stages and therefore limits the output voltage swing and may even distort the output signal. To shift the output dc level to zero, level translator circuits are used. An emitter follower with voltage divider is the simplest form of level translator as shown in fig. 2. Thus a dc voltage at the base of Q produces 0V dc at the output. It is decided by R1 and R2. Instead of voltage divider emitter follower either with diode current bias or current mirror bias as shown in fig. 3 may be used to get better results. In this case, level shifter, which is common collector amplifier, shifts the level by 0.7V. If this shift is not sufficient, the output may be taken at the junction of two resistors in the emitter leg.

Fig. 2

Fig. 3 Fig. 4, shows a complete OPAMP circuit having input different amplifiers with balanced output, intermediate stage with unbalanced output, level shifter and an output amplifier.



Fig. 4 GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


OPAMP Apllications

Lecture - 5: The Operational Amplifiers Example-1: For the cascaded differential amplifier shown in fig. 5, determine: ● ● ● ●

The collector current and collector to emitter voltage for each transistor. The overall voltage gain. The input resistance. The output resistance.

Assume that for the transistors used hFE = 100 and VBE = 0.715V

>Lecture 11 > Lecture 12 > Lecture 13 > Lecture 14 > Lecture 15 > Lecture 16 > Lecture 17 > Lecture 18 > Lecture 19 > Lecture 20



21 22 23 24 25 26



27 28 29 30

Fig. 5 Solution: (a). To determine the collector current and collector to emitter voltage of transistors Q1 and Q2, we assume that the inverting and non-inverting inputs are grounded. The



collector currents (IC ≈ IE) in Q1 and Q2 are obtained as below:

That is, IC1 = IC2 =0.988 mA. Now, we can calculate the voltage between collector and emitter for Q1 and Q2 using the collector current as follows: VC1 = VCC = -RC1 IC1 = 10 – (2.2kΩ) (0.988 mA) = 7.83 V = VC2 Since the voltage at the emitter of Q1 and Q2 is -0.715 V, VCE1 = VCE2 = VC1 -VE1 = 7.83 + 0715 = 8.545 V Next, we will determine the collector current in Q3 and Q4 by writing the Kirchhoff's voltage equation for the base emitter loop of the transistor Q3: VCC – RC2 IC2 = VBE3 - R'E IC3 - RE2 (2 IE3) + VBE= 0 10 – (2.2kΩ) (0.988mA) - 0.715 - (100) (IE3) – (30kΩ) IE3 + 10=0 10 - 2.17 - 0.715 + 10 - (30.1kΩ) IE3 = 0

Hence the voltage at the collector of Q3 and Q4 is VC3 = VC4= VCC – RC3 IC3 = 10 – (1.2kΩ) (0.569 mA) = 9.32 V Therefore, VCE3 = VVCE4 = VC3 – VE3 = 9.32 – 7.12 = 2.2 V Thus, for Q1 and Q2: ICQ = 0.988 mA VCEQ = 8.545 V file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec5b.htm (2 of 4) [12/5/2010 2:14:02 AM]


and for Q3 and Q4: ICQ = 0.569 mA VCEQ = 2.2 V [Note that the output terminal (VC4) is at 9.32 V and not at zero volts.] (b). First, we calculate the ac emitter resistance r'e of each stage and then its voltage gain.

The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is

Where Ri2 = input resistance of the second stage

The second stage is dual input, unbalanced output differential amplifier with swamping resistor R'E, the voltage gain of which is

Hence the overall voltage gain is Ad= (Ad1) (Ad2) = (80.78) (4.17) = 336.85 Thus we can obtain a higher voltage gain by cascading differential amplifier stages. (c).The input resistance of the cascaded differential amplifier is the same as the input resistance of the first stage, that is file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec5b.htm (3 of 4) [12/5/2010 2:14:02 AM]


Ri = 2βac(re1) = (200) (25.3) = 5.06 kΩ (d). The output resistance of the cascaded differential amplifier is the same as the output resistance of the last stage. Hence, RO = RC = 1.2 kΩ GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 5: The Operational Amplifiers Example-2: For the circuit show in fig. 6, it is given that β =100, VBE =0715V. Determine ● ● ●

The dc conditions for each state The overall voltage gain The maximum peak to peak output voltage swing.




21 22 23 24 25 26



27 28 29 30

Fig. 6 Solution: (a). The base currents of transistors are neglected and VBE drops of all transistors are assumed same.



From the dc equivalent circuit,

and

b) The overall voltage gain of the amplifier can be obtained as below:

Therefore, voltage gain of second stage

The input impedance of second stage is

The effective load resistance for first stage is

Therefore, the voltage gain of first stage is



The overall voltge gain is AV = AV1 AV2

(c). The maximum peak to peak output votage swing = Vopp = 2 (VC7 - VE7) = 2 x (5.52 - 3.325) = 4.39 V GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 6: Practical Operational Amplifier The symbolic diagram of an OPAMP is shown in fig. 1.




21 22 23 24 25 26


Parameters of OPAMP: The various important parameters of OPAMP are follows: 1.Input Offset Voltage: Input offset voltage is defined as the voltage that must be applied between the two input terminals of an OPAMP to null or zero the output fig. 2, shows that two dc voltages are applied to input terminals to make the output zero. Vio = Vdc1 – Vdc2 Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Vio is the difference of Vdc1 and


741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.

27 28 29 30

Vdc2. It may be positive or negative. For a 741C OPAMP the maximum value of Vio is 6mV. It means a voltage ± 6 mV is required to one of the input to reduce the output offset voltage to zero. The smaller the input offset voltage the better the differential amplifier, because its transistors are more closely matched.


Fig. 2


2. Input offset Current: The input offset current Iio is the difference between the currents into inverting and non-inverting terminals of a balanced amplifier. Iio = | IB1 – IB2 | The Iio for the 741C is 200nA maximum. As the matching between two input terminals is improved, the difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases further.For a precision OPAMP 741C, Iio is 6 nA 3.Input Bias Current: The input bias current IB is the average of the current entering the input terminals of a balanced amplifier i.e. IB = (IB1 + IB2 ) / 2 For 741C IB(max) = 700 nA and for precision 741C IB = ± 7 nA 4. Differential Input Resistance: (Ri) Ri is the equivalent resistance that can be measured at either the inverting or noninverting input terminal with the other terminal grounded. For the 741C the input resistance is relatively high 2 MΩ. For some OPAMP it may be up to 1000 G ohm. 5. Input Capacitance: (Ci) Ci is the equivalent capacitance that can be measured at either the inverting and noninverting terminal with the other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C. 6. Offset Voltage Adjustment Range: 741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this purpose. It can be done by connecting 10 K ohm pot between 1 and 5 as shown in fig. 3.



Fig. 3 By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to zero volts. Thus the offset voltage adjustment range is the range through which the input offset voltage can be adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is ± 15 mV. GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal





21 22 23 24 25 26


Parameters of OPAMP: 7. Input Voltage Range : Input voltage range is the range of a common mode input signal for which a differential amplifier remains linear. It is used to determine the degree of matching between the inverting and noninverting input terminals. For the 741C, the range of the input common mode voltage is ± 13V maximum. This means that the common mode voltage applied at both input terminals can be as high as +13V or as low as –13V. 8. Common Mode Rejection Ratio- (CMRR). CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM CMRR = Ad / ACM. For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching between two input terminals and the smaller is the output common mode voltage. 9. Supply voltage Rejection Ratio: (SVRR) SVRR is the ratio of the change in the input offset voltage to the corresponding change in power supply voltages. This is expressed in µ V / V or in decibels, SVRR can be defined as SVRR = ∆ Vio / ∆ V Where ∆ V is the change in the input supply voltage and ∆ Vio is the corresponding change


Lecture - 6: Practical Operational Amplifier

27 28 29 30

in the offset voltage. For the 741C, SVRR = 150 µ V / V. For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with R3 ≤ 10K. For same OPAMPS, SVRR is separately



specified as positive SVRR and negative SVRR. 10. Large Signal Voltage Gain: Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the amplifier is defined as

Because output signal amplitude is much large than the input signal the voltage gain is commonly called large signal voltage gain. For 741C is voltage gain is 200,000 typically. 11. Output voltage Swing: The ac output compliance PP is the maximum unclipped peak to peak output voltage that an OPAMP can produce. Since the quiescent output is ideally zero, the ac output voltage can swing positive or negative. This also indicates the values of positive and negative saturation voltages of the OPAMP. The output voltage never exceeds these limits for a given supply voltages +VCC and –VEE. For a 741C it is ± 13 V. 12. Output Resistance: (RO) RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and the ground. It is 75 ohm for the 741C OPAMP. Example - 1 Determine the output voltage in each of the following cases for the open loop differential amplifier of fig. 4: a. vin 1 = 5 m V dc, vin 2 = -7 µVdc b. vin 1 = 10 mV rms, vin 2= 20 mV rms



Fig. 4 Specifications of the OPAMP are given below: A = 200,000, Ri = 2 M Ω , R O = 75Ω, + VCC = + 15 V, - VEE = - 15 V, and output voltage swing = ± 14V. Solution: (a). The output voltage of an OPAMP is given by

Remember that vo = 2.4 V dc with the assumption that the dc output voltage is zero when the input signals are zero. (b). The output voltage equation is valid for both ac and dc input signals. The output voltage is given by

Thus the theoretical value of output voltage vo = -2000 V rms. However, the OPAMP saturates at ± 14 V. Therefore, the actual output waveform will be clipped as shown fig. 5. This non-sinusoidal waveform is unacceptable in amplifier applications.



Fig. 5 13. Output Short circuit Current : In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power device and so its output current is limited. The 741C can supply a maximum short circuit output current of only 25mA. 14. Supply Current : IS is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply current is 2.8 m A. 15. Power Consumption: Power consumption (PC) is the amount of quiescent power (vin= 0V) that must be consumed by the OPAMP in order to operate properly. The amount of power consumed by the 741C is 85 m W. GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 6: Practical Operational Amplifier

Parameters of OPAMP: 16. Gain Bandwidth Product: The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is reduced to 1. From open loop gain vs frequency graph At 1 MHz shown in. fig. 6, It can be found 1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000 and cut off frequency is 10Hz.




21 22 23 24 25 26



27 28 29 30

Fig. 6 17. Slew Rate: Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal conditions and is expressed in volts / µ secs.

To understand this, consider a charging current of a capacitor shown in fig. 7. file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec6c.htm (1 of 3) [12/5/2010 2:13:55 AM]


Fig. 6 If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is also limited. Slew rate indicates how rapidly the output of an OPAMP can change in response to changes in the input frequency with input amplitude constant. The slew rate changes with change in voltage gain and is normally specified at unity gain. If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the slew rate is low 0.5 V / µ S. which limits its use in higher frequency applications. 18. Input Offset Voltage and Current Drift: It is also called average temperature coefficient of input offset voltage or input offset current. The input offset voltage drift is the ratio of the change in input offset voltage to change in temperature and expressed in µ V /° C. Input offset voltage drift = ( ∆ Vio / ∆ T). Similarly, input offset current drift is the ratio of the change in input offset current to the change in temperature. Input offset current drift = ( ∆ Iio / ∆ T). For 741C, ∆ Vio / ∆ T = 0.5 µ V / C. ∆ Iio/ ∆ T = 12 pA / C. file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec6c.htm (2 of 3) [12/5/2010 2:13:55 AM]


GOTO >> 1 || 2 || 3 || Home



Analog Circuits


Lecture - 7: Parameters of an OPAMP

Example - 1 A 100 PF capacitor has a maximum charging current of 150 µA. What is the slew rate? Solution: C = 100 PF=100 x 10-12 F I = 150 µA = 150 x 10-6 A


Example - 2


Slew rate is 1.5 V / µs.


21 22 23 24 25 26

An operational amplifier has a slew rate of 2 V / µs. If the peak output is 12 V, what is the power bandwidth? Solution: The slew rate of an operational amplifier is



27 28 29 30 As for output free of distribution, the slews determines the maximum frequency of


Prof.Pramod Agarwal


operation fmax for a desired output swing.

so So bandwidth = 26.5 kHz.

Example - 3 For the given circuit in fig. 1. Iin(off) = 20 nA. If Vin(off) = 0, what is the differential input voltage?. If A = 105, what does the output offset voltage equal?

Fig. 1 Solutin: Iin(off) = 20 nA Vin(off) = 0 (i) The differential input voltage = Iin(off) x 1k = 20 nA x 1 k = 20µ V (ii) If A = 105 then the output offset voltage Vin(off) = 20 µ V x 105 = 2 volt Output offset voltage = 2 volts. GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 7: Parameters of an OPAMP

Example - 4 R1 = 100Ω, Rf = 8.2 k, RC = 10 k. Assume that the amplifier is nulled at 25°C. If Vin is 20 mV peak sine wave at 100 Hz. Calculate Er, and Vo values at 45°C for the circuit shown in fig. 2.




21 22 23 24 25 26

Fig. 2 Solution:



27 28 29 30

The change in temperature ΔT = 45 - 25 = 20°C.



Error voltage = 51.44 mV

Output voltage is 1640 mV peak ac signal which rides either on a +51.44 mV or -51.44 mV dc level.

Example - 5 Design an input offset voltage compensating network for the operational amplifier µA 715 for the circuit shown in fig. 3. Draw the complete circuit diagram.

Fig. 3 Solution: From data sheet we get vin = 5 mV for the operational amplifier µA 715. file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec7b.htm (2 of 4) [12/5/2010 2:13:57 AM]


V = | VCC | = | - VEE | = 15 V Now,

If we select RC = 10Ω, the value of Rb should be Rb = (3000) RC = 30000Ω = 304Ω Since R > Rmax, let RS = 10 Rmax where Rmax = Ra / 4. Therefore,

If a 124Ω potentiometer is not available, we may prefer to use to the next lower value avilable, such as 104Ω, so that the value of Ra will be larger than Rb by a factor of 10. If we select a 10 kΩ potentiometer a s the Ra value, Rb is 12 times larger than Ra, Thus Ra = 10 kΩ potentiometer Rb = 30 kΩ Rc = 10Ω. The final circuit, which also includes the pin connections for the µA 715, shown in fig. 4.



Fig. 4 GOTO >> 1 || 2 || 3 || Home



Analog Circuits





21 22 23 24 25 26

Lecture -7: Parameters of an OPAMP

The ideal OPAMP : An ideal OPAMP would exhibit the following electrical characteristic. 1. Infinite voltage gain Ad 2. Infinite input resistance Ri, so that almost any signal source can drive it and there is no loading of the input source. 3. Zero output resistance RO, so that output can drive an infinite number of other devices. 4. Zero output voltage when input voltage is zero. 5. Infinite bandwidth so that any frequency signal from 0 to infinite Hz can be amplified without attenuation. 6. Infinite common mode rejection ratio so that the output common mode noise voltage is zero. 7. Infinite slew rate, so that output voltage changes occur simultaneously with input voltage changes. There are practical OPAMPs that can be made to approximate some of these characters using a negative feedback arrangement.

Equivalent Circuit of an OPAMP: Fig. 5, shows an equivalent circuit of an OPAMP. v1 and v2are the two input voltage voltages. Ri is the input impedance of OPAMP. Ad Vd is an equivalent Thevenin voltage source and RO is the Thevenin equivalent impedance looking back into the terminal of an OPAMP.



27 28 29 30


Prof.Pramod Agarwal


Fig. 5 This equivalent circuit is useful in analyzing the basic operating principles of OPAMP and in observing the effects of standard feedback arrangements vO = Ad (v1 – v2) = Ad vd. This equation indicates that the output voltage vO is directly proportional to the algebraic difference between the two input voltages. In other words the OPAMP amplifies the difference between the two input voltages. It does not amplify the input voltages themselves. The polarity of the output voltage depends on the polarity of the difference voltage vd.

Ideal Voltage Transfer Curve: The graphic representation of the output equation is shown in fig. 6 in which the output voltage vO is plotted against differential input voltage vd, keeping gain Ad constant.



Fig. 6 The output voltage cannot exceed the positive and negative saturation voltages. These saturation voltages are specified for given values of supply voltages. This means that the output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter the output voltage remains constant. Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be zero. If the curve is drawn to scale, the curve would be almost vertical because of very large values of Ad. GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal



Lecture - 8: Open loop OPAMP Configuration

Open loop OPAMP Configuration: In the case of amplifiers the term open loop indicates that no connection, exists between input and output terminals of any type. That is, the output signal is not fedback in any form as part of the input signal. In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open loop OPAMP configurations.

The Differential Amplifier: Fig. 1, shows the open loop differential amplifier in which input signals vin1 and vin2 are applied to the positive and negative input terminals.



21 22 23 24 25 26

Fig. 1



27 28 29 30

Since the OPAMP amplifies the difference the between the two input signals, this configuration is called the differential amplifier. The OPAMP amplifies both ac and dc input signals. The source resistance Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage drop across these resistances can be assumed to be zero.



Therefore v1 = vin1 and v2 = vin2. vo = Ad (vin1 – vin2 ) where, Ad is the open loop gain.

The Inverting Amplifier: If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is called inverting amplifier.This configuration is shown in fig. 2. v1= 0, v2 = vin. vo = -Ad vin

Fig. 2 The negative sign indicates that the output voltage is out of phase with respect to input 180 ° or is of opposite polarity. Thus the input signal is amplified and inverted also.

The non-inverting amplifier: In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is ground as shown in fig. 3. v1 = +vin

v2 = 0



vo = +Ad vin This means that the input voltage is amplified by Ad and there is no phase reversal at the output.

Fig. 3 In all there configurations any input signal slightly greater than zero drive the output to saturation level. This is because of very high gain. Thus when operated in open-loop, the output of the OPAMP is either negative or positive saturation or switches between positive and negative saturation levels. Therefore open loop op-amp is not used in linear applications. GOTO >> 1 || 2 || 3 || Home



Analog Circuits





21 22 23 24 25 26

Lecture - 8: Open loop OPAMP Configuration

Closed Loop Amplifier: The gain of the OPAMP can be controlled if fedback is introduced in the circuit. That is, an output signal is fedback to the input either directly or via another network. If the signal fedback is of opposite or out phase by 180° with respect to the input signal, the feedback is called negative fedback. An amplifier with negative fedback has a self-correcting ability of change in output voltage caused by changes in environmental conditions. It is also known as degenerative fedback because it reduces the output voltage and,in tern,reduces the voltage gain. If the signal is fedback in phase with the input signal, the feedback is called positive feedback. In positive feedback the feedback signal aids the input signal. It is also known as regenerative feedback. Positive feedback is necessary in oscillator circuits. The negative fedback stabilizes the gain, increases the bandwidth and changes, the input and output resistances. Other benefits are reduced distortion and reduced offset output voltage. It also reduces the effect of temperature and supply voltage variation on the output of an op-amp. A closed loop amplifier can be represented by two blocks one for an OPAMP and other for a feedback circuits. There are four following ways to connect these blocks. These connections are shown in fig. 4. These connections are classified according to whether the voltage or current is feedback to the input in series or in parallel: ● ● ●



●

Voltage – series feedback Voltage – shunt feedback Current – series feedback Current – shunt feedback

27 28 29 30


Prof.Pramod Agarwal


Fig. 4 In all these circuits of fig. 4, the signal direction is from input to output for OPAMP and output to input for feedback circuit. Only first two, feedback in circuits are important. GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 8: Open loop OPAMP Configuration Voltage series feedback: It is also called non-inverting voltage feedback circuit. With this type of feedback, the input signal drives the non-inverting input of an amplifier; a fraction of the output voltage is then fed back to the inverting input. The op-amp is represented by its symbol including its large signal voltage gain Ad or A, and the feedback circuit is composed of two resistors R1 and Rf. as shown in fig. 5




21 22 23 24 25 26

Fig. 5



27 28 29 30 The feedback voltage always opposes the input voltage, (or is out of phase by 180°



with respect to input voltage), hence the feedback is said to be negative. The closed loop voltage gain is given by

The product A and B is called loop gain. The gain loop gain is very large such that AB >> 1

This shows that overall voltage gain of the circuit equals the reciprocal of B, the feedback gain. It means that closed loop gain is no longer dependent on the gain of the op-amp, but depends on the feedback of the voltage divider. The feedback gain B can be precisely controlled and it is independent of the amplifier. Physically, what is happening in the circuit? The gain is approximately constant, even though differential voltage gain may change. Suppose A increases for some reasons (temperature change). Then the output voltage will try to increase. This means that more voltage is fedback to the inverting input, causing vd voltage to decrease. This almost completely offset the attempted increases in output voltage. Similarly, if A decreases, The output voltage decreases. It reduces the feedback voltage vf and hence, vd voltage increases. Thus the output voltage increases almost to same level.

Different Input voltage is ideally zero. Again considering the voltage equation, v O = Ad v d file:///C|/Users/Public/Documents/ANALOG%20INTEGRATED%20CIRCUITS/lec8c.htm (2 of 3) [12/5/2010 2:14:03 AM]


or

vd = vO / Ad

Since Ad is very large (ideally infinite) ∴ vd ≈ 0. and

v1 = v2 (ideal).

This says, that the voltage at non-inverting input terminal of an op-amp is approximately equal to that at the inverting input terminal provided that Ad is very large. This concept is useful in the analysis of closed loop OPAMP circuits. For example, ideal closed loop voltage again can be obtained using the results

GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 9: Closed Loop Amplifier

Input Resistance with Feedback: fig. 1, shows a voltage series feedback with the OPAMP equivalent circuit.

OPAMP Apllications >Lecture 11 > Lecture 12 > Lecture 13 > Lecture 14 > Lecture 15 > Lecture 16 > Lecture 17 > Lecture 18 > Lecture 19 > Lecture 20 Fig. 1



21 22 23 24 25 26

In this circuit Ri is the input resistance (open loop) of the OPAMP and Rif is the input resistance of the feedback amplifier. The input resistance with feedback is defined as



27 28 29 30



Since AB is much larger than 1, which means that Rif is much larger that Ri. Thus Rif approaches infinity and therefore, this amplifier approximates an ideal voltage amplifier.

Output Resistance with Feedback: Output resistance is the resistance determined looking back into the feedback amplifier from the output terminal. To find output resistance with feedback Rf, input vin is reduced to zero, an external voltage Vo is applied as shown in fig. 2.

Fig. 2 The output resistance (Rof ) is defined as



This shows that the output resistance of the voltage series feedback amplifier is ( 1 / 1 +AB ) times the output resistance Ro of the op-amp. It is very small because (1+AB) is very large. It approaches to zero for an ideal voltage amplifier. GOTO >> 1 || 2 || 3 || Home



Analog Circuits




Reduced Non-linear Distortion: The final stage of an OPAMP has non-linear distortion when the signal swings over most of the ac load line. Large swings in current cause the r'e of a transistor to change during the cycle. In other words, the open loop gain varies throughout the cycle of when a large signal is being applied. It is this changing voltage gain that is a source of the nonlinear distortion. Noninverting voltage feedback reduces non-linear distortion because the feedback stabilizes the closed loop voltage gain, making it almost independent of the changes in open loop voltage gain. As long as loop gain, is much greater than 1, the output voltage equals 1/B times the input voltage. This implies that output will be a more faithful reproduction of the input . Consider, under large signal conditions, the open loop OPAMP circuit produces a distortion voltage, designated vdist. It can be represented by connecting a source vdist in series with Avd. Without negative feedback all the distortion voltage vdist appears at the output. But with negative feedback, a fraction of vdist is feedback to inverting input. This is amplified and arrives at the output with inverted phase almost completely canceling the original distortion produced by the output stage.



21 22 23 24 25 26

The first term is the amplified output voltage. The second term in the distortion that appears at the final output. The distortion voltage is very much, reduced because AB>>1



27 28 29 30

Bandwidth with Feedback: The bandwidth of an amplifier is defined as the band of frequencies for which the gain remains constant. Fig. 3, shows the open loop gain vs frequency curve of 741C OPAMP. From this curve for a gain of 2 x 105 the bandwidth is approximately 5Hz. On the other hand, the bandwidth is approximately 1MHz when the gain is unity.


Prof.Pramod Agarwal


Fig. 3 The frequency at which gain equals 1 is known as the unity gain bandwidth. It is the maximum frequency the OPAMP can be used for. Furthermore, the gain bandwidth product obtained from the open loop gain vs frequency curve is equal to the unity gain bandwidth of the OPAMP. Since the gain bandwidth product is constant obviously the higher the gain the smaller the bandwidth and vice versa. If negative feedback is used gain decrease from A to A / (1+AB). Therefore the closed loop bandwidth increases by (1+AB). Bandwidth with feedback = (1+ A B) x (B.W. without feedback) ff= fo (1+A B) GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal





21 22 23 24 25 26



27 28 29 30


Output Offset Voltage: In an OPAMP even if the input voltage is zero an output voltage can exist. There are three cause of this unwanted offset voltage. 1. Input offset voltage. 2. Input bias voltage. 3. Input offset current. Fig. 4, shows a feedback amplifier with an output offset voltage source in series with the open loop output AVd. The actual output offset voltage with negative feedback is smaller. The reasoning is similar to that given for distortion. Some of the output offset voltage is fed back to the inverting input. After amplification an out of phase voltage arrives at the output canceling most of the original output offset voltage.

When loop gain AB is much greater than 1, the closed loop output offset voltage is much smaller than the open loop output offset voltage.

Voltage Follower: The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1. When the non-inverting amplifier gives unity gain, it is called voltage follower because the output voltage is equal to the input voltage and in phase with the input voltage. In other words the output voltage follows the input voltage. To obtain voltage follower, R1 is open circuited and Rf is shorted in a negative feedback amplifier of fig. 4. The resultant circuit is shown in fig. 5.


Fig. 4


vout = Avd= A (v1 – v2) v1 = vin v2 =vout v1 = v2 if A >> 1 vout = vin. The gain of the feedback circuit (B) is 1. Therefore Af = 1 / B = 1

Fig. 5

GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal


Lecture - 10: Voltage Shunt Feedback

Voltage shunt Feedback: Fig. 1, shows the voltage shunt feedback amplifier using OPAMP.




21 22 23 24 25 26



Fig. 1 The input voltage drives the inverting terminal, and the amplified as well as inverted output signal is also applied to the inverting input via the feedback resistor Rf. This arrangement forms a negative feedback because any increase in the output signal results in a feedback signal into the inverting input signal causing a decrease in the output signal. The non-inverting terminal is grounded. Resistor R1 is connected in series with the source. The closed loop voltage gain can be obtained by, writing Kirchoff's current equation at the input node V2.

27 28 29 30



The negative sign in equation indicates that the input and output signals are out of phase by 180. Therefore it is called inverting amplifier. The gain can be selected by selecting Rf and R1 (even < 1).

Inverting Input at Virtual Ground: In the fig. 1, shown earlier, the noninverting terminal is grounded and the- input signal is applied to the inverting terminal via resistor R1. The difference input voltage vd is ideally zero, (vd= vO/ A) is the voltage at the inverting terminals (v2) is approximately equal to that of the noninverting terminal (v1). In other words, the inverting terminal voltage (v1) is approximately at ground potential. Therefore, it is said to be at virtual ground.



GOTO >> 1 || 2 || 3 || Home



Analog Circuits

Prof.Pramod Agarwal



Input Resistance with Feedback: To find the input resistance Miller equivalent of the feedback resistor Rf, is obtained, i.e. Rf is splitted into its two Miller components as shown in fig. 2. Therefore, input resistance with feedback Rif is then


Output Resistance with Feedback: The output resistance with feedback Rof is the resistance


Fig. 2


21 22 23 24 25 26

measured at the output terminal of the feedback amplifier. The output resistance can be obtained using Thevenin's equivalent circuit,shown in fig. 3. i O = ia + ib Since RO is very small as compared to Rf +(R1 || R2 )



27 28 29 30

Therefore,i.e. iO= ia vO = RO iO + A vd. vd= vi – v2 = 0 - B vO



Similarly, the bandwidth increases by (1+ AB) and total output offset voltage reduces by (1+AB).

Fig. 3 GOTO >> 1 || 2 || 3 || Home



Analog Circuits



Example - 1 (a).An inverting amplifier is implemented with R1 = 1K and Rf = 100 K. Find the percentge change in the closed loop gain A is the open loop gain a changes from 2 x 105 V / V to 5 x 104 V/V. (b) Repeat, but for a non-inverting amplifier with R1 = 1K at Rf = 99 K. Solution: (a). Inverting amplifier


Here

Rf = 100 K R1 = 1K

When,



21 22 23 24 25 26



27 28 29 30

(b) Non-inverting amplifier

Here

Rf = 99 K


Prof.Pramod Agarwal


R1 = 1K

Example - 2 An inverting amplifier shown in fig. 4 with R1 = 10Ω and R2 = 1MΩ is driven by a source v1 = 0.1 V. Find the closed loop gain A, the percentage division of A from the ideal value R2 / R1, and the inverting input voltage VN for the cases A = 100 V/V, 105 and 105 V/V. Solution:

we have when A = 103,

Fig. 4



Example - 3 Find VN, V1 and VO for the circuit shown in fig. 5. Solution: Applying KCL at N

or

Now

2VN + VN = VO.

VO - Vi = 6 as point A and N are virtually shorted. VO - VN = 6 V

Therefore, VO = VN + 6 V

Fig. 5

Therefore, VN = Vi = 3 V.

GOTO >> 1 || 2 || 3 || Home


lec1-10 opamp

Recommend Documents