microprocessor and its applications

UNIT I THE 8086 PROCESSOR SOFTWARE ASPECTS A. B. C. D. E. F.

Evol Evolu ution tion of of Micr Microp opro roce cess ssor ors s 8086 architecture Addressing m mo odes Instru Instructi ction on set and assemb assemble lerr dire directi ctive ves s Asse Assemb mbly ly lang langua uage ge prog progra ramm mmin ing g Inte In terr rrup upts ts and and int inter erru rupt pt ser servi vice ce rou routi tine nes. s.

IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Evolution of Microprocessors Need to learn MuP: • The microprocessor is the core of computer systems. • Nowadays many communication, digital entertainment, portable devices, are controlled by them. • A designer should know what types of components he needs, ways to reduce production costs and product reliable. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Picture of Microprocessor


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What are microprocessor-based systems?  Microprocessor-based systems are electrical systems consisting

of microprocessors, memories, I/O units, and other peripherals. 

Microprocessors are the brains of the systems



Microprocessors access memories and other units through buses

The operations of microprocessors are controlled by instructions stored in memories



Microprocessor Bus

Control unit Datapath ALU Reg.

Memory

Output units

Input units


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What are microprocessors?  A microprocessor is a processor (or Central Processing Unit, CPU)

fabricated on a single integrated circuit. Address bus

MAR PC IR Control unit

Control bus

X Y Data bus

ALU

ACC

A simple microprocessor architecture


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Evolution of Computers  First generation (1939-1954) - vacuum tube  Second generation (1954-1959) - transistor  Third generation (1959-1971) - IC  Fourth generation (1971-present) - microprocessor


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Evolution of Computers  First generation (1939-1954) - vacuum tube

IBM 650, 1954


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Evolution of Computers  Second generation (1954-1959) - transistor

Manchester University Experimental Transistor Computer


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Evolution of Computers  Third generation (1959-1971) - IC

PDP-8, Digital Equipment Corporation Thanks to the use of ICs, the DEC PDP-8 is the least expensive general purpose small computer in 1960s




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Evolution of Computers  Fourth generation (1971-present) - microprocessor 

In 1971, Intel developed 4-bit 4004 chip for calculator calculator applications. ROM/RAM buffer

Timing

Reset

Control logic Program counter

Instruction decoder ALU

Reg.

I/O

Refresh logic

http://www.intel.com

System bus

Block diagram of Intel 4004

4004 chip layout


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Evolution of Intel Microprocessors Minimum transistor sizes (µm)

Number of transistors 100,000,000

80386

1,000,000

8088

100,000 10,000 1,000

8080

P III

Pentium

10,000,000

7

P4

P II

6 5

80486

4

80286

8088

3

8080

80386

2

100

Pentium P II 80486

80286

1

10

0

1 1 97 97 4

1 97 97 9

1 98 98 2

1 98 98 5

1 98 98 9

1 99 99 3

1 99 99 7

1 99 99 9

1974

2 00 00 0

1979

1982

1985

Clock frequencies (MHz)

1989

1993

1997

P III P 4 1999

2000

MIPS

10000

10000

P4

P III

1000

1000

Pentium

P II II Pentium

100

80386 8088

10

8080

P II

100

P III

80386

10

80486

1

80286

1

P4

8080

80486

8088 80286

0.1 1974

1979

1982

1985

1989

1993

1997

1999

2000

1974 1974 1979 1979 1982 1982 1985 1985 1989 1989 1993 1993 1997 1997 1999 1999 2000 2000


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Other Commercial Microprocessors  PowerPC ( IBM, Motorola)  Athlon, Dulon, Hammer ( AMD)  Crusoe (Transmeta)  SPARC, UltraSPARC (Sun Microsystems)  TI’s TMS DSP chips (Texas Instruments)  StarCore ( Motorola, Agere)  ARM cores ( Advanced RISC Machines)  MIPS cores ( MIPS Technologies) 

     


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Applications of Microprocessor-Based Systems  Computers 

System performance is normally the most important design concern

...

Keyboard

Monitor

Disk

Other peripherals

Bus

Microprocessor

Memory

Timing & control

...

Interrupt control

Block diagram of a computer


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Applications of Microprocessor-Based Systems  Microcontrollers 



A microcontroller is a simple computer implemented in a single VLSI chip. In general, microcontrollers are cheap and have low performance

 Microcontrollers are widely used in industrial control, automobile and home applications

OSC.

RAM

ROM

CPU I/O port Timer

USART

Interrupt

A/D, D/A

Block diagram of a microcontroller IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Features of 8086 microprocessor • The 8086 is a 16 bit microprocessor. – The term 16-bit means that its arithmetic logic unit, internal registers and most of its instructions are designed to work with 16-bit binary words.

• The 8086 has a 16 bit data bus, so it can read data from or write data to memory and ports either 16 bits or 8 bits at a time. – The 8088 however has an 8 bit data bus, so it can only read data from or write data to memory and ports 8 bits at a time.


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• The 8086 has 20 bit address bus so it can directly access 2^20 or 1048576 (1Mb) memory location. • The 8086 can generate 16 bit I/O address, hence it can access 2^16 = 65536 I/O ports. • The 8086 provides fourteen 16 bit registers. • 8086 requires one phase clock with a 33% duty cycle to provide optimized internal timing. – Range of clock: • 5 MHz for 8086 • 8Mhz for 8086-2 • 10Mhz for 8086-1 IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• 8086 has multiplexed address and data bus which reduces the number of pins need but slows down the transfer of data(drawback) • 8086 performs arithmetic and logical operations on bit,byte,word and decimal numbers including multiply and divide • 8086 operates in 2 modes: – Minimum- one CPU & it issues control signals – Maximum- Multiple CPU, DMA controller issues control signals IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• 8086 supports multiprogramming – Two or more codes in memory and it is executed in multiplexed fashion

• Fetches six instructions bytes from memory and stores them in queue to speed up the program execution • Supports powerful instruction set with the following addressing modes. – For accessing immediate and register data – For accessing data in memory – For accessing I/O ports – Relative addressing mode Implied addressing mode – IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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8086 architecture • Divided into two functional units: – Bus interface unit (BIU) – Execution unit (EU)

• Works at a time to improve speed and throughput • BIU: – Interface to the outside world – Provides16 bit bidirectional data bus – Provides 20 bit address bus IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• Functions of BIU: – Sends address of the memory or I/O – Fetches instructions from memory – Reads data from port/memory – Writes data into port/memory – Supports instruction queuing – Provides address relocation facility

• To provide above all it contains: – Instruction queue – Segment registers instruction pointer – Address summer – Bus control logic IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• Instruction queue • To speed up the execution BIU fetches 6 instructions ahead of time from memory • These prefetched instructions are stored in group of registers called queue.Operates on the principle of FIFO • Feature of fetching the next instruction while the current instruction is executing is called pipelining • Segment registers: • Physical address of the 8086 is 20 bits wide to access1 Mbyte of memory locations. • But registers and memory locations contain logical address of 16 bits wide. Hence memory segmentation is MuP/MC9232 used /Unit I / PPT/ Version 1.1 IFET CE/ MCA/ II yr/ III sem/

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• Memory is divided into active segments each 64 kbytes. • For the selection of the segments 4 16 bit registers are used, they are: – CODE SEGMENT REGISTER (CS) – DATA SEGMENT REGISTER (DS) – EXTRA SEGMENT REGISTER (ES) – STACK SEGMENT REGISTEER (SS)

• Starting address of the segment register is called as segment base or base address IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• BIU always inserts zeros for the lowest 4 bits in the contents of the segment register to generate 20 bit base address. – For eg, if the code segment register contains 348H then code segment will start at addres 3480H

• Functions of segment registers: – CS holds the upper 16 bits of the starting address of the segment from which the BIU is currently fetching the instruction code byte – SS used for the upper 16 bits of the starting address for the program stack IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• ES register and DS register hold the upper 16 bits of the starting address of the 2 memory segments which are used for the data. • Rules for memory segmentation: – 4 segments can overlap. In minimum system starting address 00000H – Starting / Ending address must by divisible by 16


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• Major Advantages: – Memory addressing capacity of 1Mbyte even though the individual instruction is only 16 bit – Separate memory areas for code, data and stack – Permits address relocation which is useful in multiprogramming

• Instruction pointer – Holds the 16 bit address of the next code byte within the code segment. – Value in IP is offset IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• Generation of 20 bit physical address: CS 348A0 IP 4214 (+) 38AB4

[CS- 348AH, add 0] - > Physical address


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Execution unit: • The EU of 8086 tells the BIU from where to fetch instruction or data decodes instruction and executes instruction. It contains – Control circuitry( directs the internal operation) – Instruction decoder ( translates instruc to actions) – ALU( 16 bit ,performs Arithmetic and logic operations) – Flag register – General purpose register – Pointers and index registers


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Flag register • A flag is a flip-flop which indicates some condition produced by the execution of an ins or controls certain operations of the EU. • The flag register contains nine active flags. Six of them are used to indicate some condition: • Carry flag – in case of addition this flag is set if there is a carry out of the MSB. The carry flag also serves as a borrow flag for subtraction. In case of sub it is set when borrow is needed. • Parity flag – it is set to 1 if result of byte operation or lower byte of the word operation contain an even number of ones, otherwise it is zero. • Auxiliary flag – this flag is set if there is an overflow out of bit 3. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Flag register • Zero flag – the ZF sets if the result of operation in ALU is zero and flag resets if the result in nonzero. The zero flag is also set if a certain reg content becomes zero following an inc or dec operation to that reg. • Sign flag – After the execution of arithmetic or logical operation if the MSB of the result is 1, the sign bit is set. Sign bit 1 indicates the result is negative otherwise it is positive. • Overflow flag – this flag is set if result is out of range. For addition this flag is set when there is a carry into the MSB and no carry out of the MSB. For sub it is set when MSB needs a borrow and there is no borrow from the MSB. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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The three remaining flags are used to control certain operations of the processor: • Trap flag- one way to debug a program is to run the pgm one ins at a time and see the contents of used reg and memory variables after execution of every ins. This process is called single stepping through a pgm. • Interrupt flag – it is used to allow the interruption of a pgm. If set a certain type of interrupt can be recognized by the 8086, otherwise these interrupts are ignored. • Direction flag – it is used with string ins. If DF = 0, the string is processed from its beginning with the first element having the lowest address. Otherwise the string is processed from the high address towards the low address. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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n erna arc

ec ure


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General purpose register • The 8086 has four 16 bit general purpose registers labeled AX, BX, CX, DX. Each 16 bit general purpose reg can split into two 8 bit reg. the letter L and H specify the lower and higher bytes of a particular reg. • for eg BH means the higher byte(8 bits) of the BX reg and BL means the lower byte of the BX reg. the letter X s used to specify the complete 16 bit reg. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Pointer and Index register • All segment reg are 16 bit wide. But it is necessary to generate 20 bit address on the address bus. To get 20 bit physical address one or more pointer or index reg are associated with each segment reg. • The pointer reg IP,BP and SP are associated with code, data and stack segments.


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• Stack pointer: – Contains the 16 bit offset from the start of the segment to the top of the stack – Physical address is produced by adding the contents of stack pointer to the segment base address in SS – SS – SP (+) – Physical address

• The BP, index reg DI and SI are used as a general purpose registers. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• Base pointer: • For accessing the stack using based addressing mode use BP instead of SP. • 20 bit physical address is formed by using BP and SS

• Source index • Holds the offset of a data word in the data segment • 20 bit physical address is formed by using SI and DS

• Destination index • ES register points to the extra segment in which data is stored • String instructions always use ES and DI to determine the physical address IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Pin diagram of 8086


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8086 BUSES THE 8086 HAS 20 ADDRESS LINES 16 DATA LINES 4-10 CONTROL LINES.

WITH THIS THE 8086 IS ABLE TO ADDRESS 1048576 (2 20 ) MEMORY

LOCATIONS/PORTS. TO MANIPULATE AND/OR OPERATE ON 16-BITS(2-

BYTES) OF DATA AT A TIME. TO GENERATE NECESSARY CONTROL SIGNALS. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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THE INTERNAL ARCHITECTURE OF 8086 CAN BE MAINLY DIVIDED INTO TWO UNITS: BUS INTERFACE UNIT (BIU) EXECUTION UNIT (EU)

THE BIU CONTAINS : CODE SEGMENT REGISTER (CS)  DATA SEGMENT REGISTER (DS)  EXTRA SEGMENT REGISTER (ES) STACK SEGMENT REGISTEER (SS) AND  INSTRUCTION POINTER (IP) IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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THE EU CONTAINS THE FOLLOWING 8-BIT REGISTERS: AH & AL (AX-16 BIT) BH & BL (BX-16 BIT) CH & CL (CX-16 BIT) DH & DL (DX-16 BIT)

IT ALSO INCLUDES THE FOLLOWING 16-BIT REGISTERS: STACK POINTER (SP) BASE POINTER (BP) SOURCE INDEX (SI) DESTINATION INDEX (DI)


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Register organization of 8086 • The 8086 has a powerful set of reg. it includes the following: – General purpose register – Segment register – Flag register – Pointer and index register


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Register organization of 8086 General data registers

AH

AL

BH

BL

CH

CL

DH

DL

Segment registers

CS

Pointers and index registers

DS

SP

ES

BP

SS

SI DI IP

Flags/PSW IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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General purpose register • The 8086 has four 16 bit general purpose registers labeled AX, BX, CX, DX. Each 16 bit general purpose reg can split into two 8 bit reg. the letter L and H specify the lower and higher bytes of a particular reg. • for eg BH means the higher byte(8 bits) of the BX reg and BL means the lower byte of the BX reg. the letter X s used to specify the complete 16 bit reg. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Segment register • Here the four registers are : – – – –

code segment reg (CS) data segment reg (DS) stack segment reg, (SS) extra segment reg. (ES)

• These are used to hold the upper 16 bits of the starting addresses of the four memory segments on which 8086 works at a particular time. • Starting address the lowest addressed byte in the active code segment. The starting address is also known as base address or segment base. • Physical address is calculated from segment address and offset • Advantage is instead of maintaining a 20 bit register for a physical address, this maintains two 16 bit registers IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Pointer and Index register • All segment reg are 16 bit wide. But it is necessary to generate 20 bit address on the address bus. To get 20 bit physical address one or more pointer or index reg are associated with each segment reg. • The pointer reg IP,BP and SP are associated with code, data and stack segments. • The index reg DI and SI are used as a general purpose register. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Execution unit (EU) • The EU of 8086 tells the BIU from where to fetch ins or data decodes ins and executes ins. It contains • Control circuitry • Instruction decoder • ALU • Flag register • General purpose register • Pointers and index registers IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Control Circuitry, Instruction decoder, ALU • The control circuitry in the EU directs the internal operation. • A decoder translates the ins fetched from memory into a series of actions which the EU performs. • ALU is 16 bit. It can add, subtract, AND, OR, XOR, increment, decrements, complement and shift binary numbers. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Flag register • A flag is a flip-flop which indicates some condition produced by the execution of an ins or controls certain operations of the EU. The flag register contains nine active flags. • Carry flag – in case of addition this flag is set if there is a carry out of the MSB. The carry flag also serves as a borrow flag for subtraction. In case of sub it is set when borrow is needed. • Parity flag – it is set to 1 if result of byte operation or lower byte of the word operation contain an even number of ones, otherwise it is zero. • Auxiliary flag – this flag is set if there is an overflow out of bit 3. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Flag register • Zero flag – the ZF sets if the result of operation in ALU is zero and flag resets if the result in nonzero. The zero flag is also set if a certain reg content becomes zero following an inc or dec operation to that reg. • Sign flag – After the execution of arithmetic or logical operation if the MSB of the result is 1, the sign bit is set. Sign bit 1 indicates the result is negative otherwise it is positive. • Overflow flag – this flag is set if result is out of range. For addition this flag is set when there is a carry into the MSB and no carry out of the MSB. For sub it is set when MSB needs a borrow and there is no borrow from the MSB. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Flag register • Trap flag- one way to debug a program is to run the pgm one ins at a time and see the contents of used reg and memory variables after execution of every ins. This process is called single stepping through a pgm. • Interrupt flag – it is used to allow the interruption of a pgm. If set a certain type of interrupt can be recognized by the 8086, otherwise these interrupts are ignored. • Direction flag – it is used with string ins. If DF = 0, the string is processed from its beginning with the first element having the lowest address. Otherwise the string is processed from the high address towards the low address. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Addressing Modes • We have seen how the 8086 fetches code bytes from memory by generating 20 bit physical address with the help of IP and CS. • We have also seen how the 8086 accesses the stack using SS and SP. • In this section we will see the different ways that an 8086 can access the data. • The different ways that a processor can access data are referred to as addressing modes. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Data addressing modes • The data addressing modes can be further classified as 1. Addressing modes for accessing immediate and register data 2. Addressing modes for accessing data in memory 3. Addressing modes for accessing I/O ports 4. Relative addressing mode 5. Implied addressing mode


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1. Addressing modes for accessing immediate and register data • Register addressing mode

This mode specifies the source operand, destination operand or both to be contained in an 8086 register. • Example : MOV BX, CX – copies the 16bit  contents of CX into BX MOV CL,BL - COPIES THE 8 BIT  content of BL into CL IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• Immediate addressing mode • In an immediate mode, 8 or 16 bit data can be specified as a part of instruction. Examples: MOV BL, 26H – copies the 8 bit data 26H into BL MOV CX, 4567H – copies the 16 bit data 4567H into CX.


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2. ADDRESSING MODES FOR ACCESSING DATA IN MEMORY • The EU has direct access to all registers and data for register and immediate operand. • However the EU cannot directly access the memory operands. It must use the BIU segment registers to access memory operands. • For e.g. when the EU needs to access a memory location, it sends an offset value to the BIU. This offset is also called the effective address (EA). IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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SIX WAYS TO SPECIFY EFFECTIVE ADDRESS IN THE INSTRUCTION

A. B. C. D. E. F.

Direct addressing mode Register indirect addressing modes Based addressing mode Indexed addressing mode Based indexed addressing modes String addressing modes.


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A. Direct addressing mode • In this mode the 16 bit effective is taken directly from the displacement field of the ins. The displacement is stored in the location following the ins opcode. • Example – MOV CL, [9823H] – this ins will move the contents of the memory location at a displacement of 9823H(offset) to CL reg.


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B. Register indirect addressing modes • In this mode the EA is specified in either a pointer register or an index reg. – The pointer reg can be either base reg BX or base pointer reg BP and index reg can be either source reg SI or destination reg DI . – The 20 bit physical address is computed using DS and EA.

• Example – MOV [DI],BX – the instruction copies the 16 bit contents of BX into DI


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C. Based addressing mode • EA is obtained by adding a displacement value to the contents of BP or BX • Segment registers used are DS and SS • When memory is accessed Physical address is computed from BX and DS • When stack is accessed physical address is accessed from BP and SS • Example: MOV AL, LAST[BX] – EA is obtained by adding LAST and BX – 20 bit PA is produced from DS and EA, content copied to AL IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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D. Indexed Addressing mode • The effective address is calculated by adding the unsigned 16 bit or signextended 8 bit displacement and the contents of SI or DI – Example MOV BH, LAST [SI] ; copies the contents of the 20 bit address computed from the displacement LAST , SI and DS IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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E. Based indexed addressing mode • EA is computed by adding a base register (BX or BP) an index register (SI or DI)and a displacement ( unsigned 16 bit or signed 8 bit) • Example: MOV TOT [SI] [BX], CL copies the contents of CL to 20 bit physical address obtained by adding value of TOT and the address of SI + DS+ BX IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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G. String addressing mode • This mode uses index reg. • The string ins automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand. • Contents of SI and DI are automatically incremented (DF=0) or decremented to point to the next byte or word ( DF=1) • The segment register for the source is i s DS. The segment register for the destination must be ES. • Example: MOVS BYTE if DF=0 SI&DI incremented IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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3.

ress ng mo es or access ng I/O ports

• Two types of port addressing modes: A. Direct po port mo mode B. Ind ndir irec ectt po port rt mo mode de

A. Direct port mode: – Port number is an 8 bit immediate operand – This allows fixed access to ports numbered 0 to 255 – Example: OUT 05H, AL ; sends the contents of AL to 8 bit I/O port

80H;; copies 16 bit content – Example2: IN AX, 80H of port 80H to AX IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1 62

B. Indirect port mode: – Port number is taken from allowing 64k 8 bit ports or 32k 16 bit ports – Example:

if DX=7890H copies 8 bit – IN AL,DX ; content of port 7890H into AL copies 8 bit content of – IN AX,DX ; ports 7890H and 7891H into AL and AH


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4. Relative addressing mode • In this mode, the operand is a signed 8 bit displacement relative to PC. • Example: – JNZ BACK

;

JNZ is jump if not zero

5. Implied addressing mode 

Instructions using this mode have no operands ; sets the carry flag to one Example : STC IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Control transfer instructions • The addressing modes depend upon whether the destination location is within the same segment or in a different one. • It also depends upon the method of passing the destination address to the processor. • There are two addressing modes for the control transfer instructions, intersegment and intrasegment addressing modes. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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INTRASEGMENT MODE • If the location to which the control is to be transferred lies in the same segment, the mode is called intrasegment mode • Intrasegment Direct: Destination location is in same segment and appears directly in the instruction as an immediate displacement value.The effective address is sum of 8 or 16 bit displacement and current content of IP. JMP SHORT label; Label lies within -128 to +127 from the current IP content. • Intrasegment Indirect mode: Destination location is in same segment but it is passed to the instruction indirectly. The branch address is found as the content of a register or a memory location. JMP[BX];Jump to effective address stored in BX IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Intersegment addressing mode • If the location to which the control is to be transferred lies in a different segment other than the current one the mode is called intersegment mode. • Intersegment direct:The CS and IP of the destination address are specified directly in the instruction. JMP 5000H : 2000H- Jump to EA 2000H in segment 5000H. • Intersegment Indirect: Destination address is passed to the instruction indirectly. JMP [2000H]; Jump to an address in the other segment specified at EA 2000H in DS, that points to the memory block . IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Instruction Set and Assembler Directives • Introduction • The 8086 ins set includes equivalents of the 8085 ins plus many new ones. The new ins contains operations such as signed/unsigned multiplication and division, bit manipulation ins. String ins, and interrupt ins. • The 8086 app have 117 different ins with about 300 opcodes. The 8086 ins set contains no operand, single operand and two operand ins. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Types of Instructions The instructions supported by 8086 are • • • • • • • • • •

Data transfer instructions Addition, subtraction and comparison instructions Multiplication and Division instructions BCD and ASCII arithmetic instructions Logical instructions Shift compare instructions String compare instructions Jump instructions Machine control and miscellaneous instructions Interrupt instructions IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Data Transfer instructions • General purpose byte or word transfer • Special address transfer • Flag transfer • Simple input and output port transfer

A )General purpose byte or word transfer instructions • The instructions can be classified as – MOV – PUSH – POP – XCHG – XLAT


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MOV instruction • MOV destination, source • MOV ins copies a word or a byte of data from some source to a destination. The destination can be a register or a memory location. The source can be a register, a memory location, or an immediate number. The source and destination in a MOV ins must be of same type. • MOV ins does not effect any flags. Example MOV BX,592FH MOV CL [357A] IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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PUSH instructions • PUSH source • Push ins decrement stack pointer by 2 and copies a word from some source to the location in the stack pointer points. • Here the source must be a word. • The source of the word can be a general purpose reg, a segment reg or memory • Example: PUSH CX; Decrement SP by 2 , copy CX to stack IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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POP instructions • POP destination • It copies a word from the stack location pointed by the stack pointer to the destination • Destination can be general purpose register, segment register or memory location • After a word is copied to the specified location, the stack pointer is incremented by 2 • Example: POP CX ; copy a word from top of stack to CX and increment SP by 2

XCHG • XCHG destination , source • Exchanges the contents of a register with the contents of another register • Or the contents of the register with the contents of a memory location • Instruction cannot exchange the contents of the two memory location • Example: XCHG BX, CX ; ;exchange word in BX with word in CX

XLAT • Translate a byte in AL • Replaces a byte in the AL register with a byte from a lookup table in memory

b) Special address transfer • LEA • LDA • LES

Load effective address • This ins determines the offset of the variable or memory location named as the source and loads this address in the specified 16 bit reg, flags are not affected by LEA. • EG: LEA CX, TOTAL – LOAD CX WITH OFFSET OF TOTAL IN DS


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LDS • Load register and DS with words from memory • This ins copies a word from two memory locations into the register specified in the ins. It then copies a word from the next memory location. Into the DS. • Example: – LDS CX, [391AH] copy contents of memory at displacement of 391AH and 391BH to CX, then copy contents at displacement of 391CH and 391DH into ds.

LES • LES ins- load register and ES with words from memory. • This ins loads new values into the specified reg and into the ES reg from four successive memory location. The word from the first two memory location is copied into the specified reg and the word from the next two memory location is copied into the ES reg. • Eg: LES CX,[3483H]- copy the contents of memory at displacement of 3483h in ds to cl, contents of 3484h in ds to ch and copy the contents of memory displacement of 3485h and 3486h in ds to es register. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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c) Flag transfer • LAHF- load lower byte of flag register in AH • SAHF- copy AH register to low byte of flag register • PUSHF- push flag register on the stack • POPF- pop word from top of stack to flag register

d) Simple input and o/p port transfer • IN – Input a byte or word from port

• OUT – Send a byte or word to a port

Addressing modes for accessing I/O ports • Standard I/O devices uses port addressing modes. For memory mapped I/O memory addressing modes are used. • There are two types of port addressing modes they are – Direct and – Indirect


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Addressing modes for accessing I/O ports • In direct port mode, the port number is an 8 bit immediate operand. This allows fixed access to ports numbered 0 to 255.  

Eg: OUT 05H, AL – SENDS THE CONTENTS OF AL TO 8 BIT PORT 05H. IN AX, 80H – COPIES 16 BIT CONTENTS OF PORT 80H IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Addressing modes for accessing I/O ports • In indirect port mode, the port number is taken from DX allowing 64K 8 bit ports or 32K 16 bit ports. Eg:  IN AL, DX – IF [DX] = 7890H, THEN IT COPIES 8 BIT CONTENT OF PORT 7890 INTO AL.  IN AX,DX – COPIES THE 8 BIT CONTENTS OF PORTS 7890H AND 7891H INTO AL AND AH. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Arithmetic instructions • Addition instructions – (ADD,ADC,INC,AAA,DAA) • Subtraction instructions- (SUB, SBB ,DEC, NEG , CMP , AAS ,DAS) • Multiplication instructions- MUL, IMUL, AAM • Bit manipulation instructions – NOT, AND, OR, XOR, TEST • Shift instructions- SAL/ SHL , SHR, SAR

Arithmetic instructions • ADD – This instructions add a number from source to a number from destination and put the result in the destination – Example: ADD AL, OF0H ; – Add immediate number OF0H to contents of AL

• ADC – Adds the status of the carry flag into the result – Example: ADC DL,CL ; Dl <- DL+CL+CY

• NOTE: Flags affected: AF, CF, OF, PF, SF, ZF

INC • Increment destination • This instruc adds 1 to the specified destination. • Destination may be register or memory location • Example: – INC AL

; Adds 1 to contents of AL

• Flags affected AF,OF, PF,SF and ZF

• AAA – ASCII adjust for addition – Mask upper nibble (3) from the code before addition

• DAA – Decimal adjust accumulator – If the value of the low-order bits (D0-D3) in the AL is >9 add 6 to the low – order 4 bits – If the value of the high-order bits (D7-D4) in the AL is >9 add 6 to the high – order 4 bits

• SUB –

SUBTRACTION

– This ins subtract the number in the source from the number in the destination and put result in the destination. – EG: SUB AL, 0F0H ; subtract immediate number OF0H from contents of AL and stores result in AL

• SBB – The SBB instruction also sub the status of carry flag from the result. – EG : SBB DL,CL ; DL <- DL-CL- CY

• Note - Flags affected are AF, CF,OF,PF,SF and ZF IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• DEC instruction – decrement destination – This instruction subtract 1 from the specified destination. – The destination may be a register or a memory location. – The AF,OF,PF,SF and ZF flags are affected.

• Eg:

DEC AL ;Subtracts 1 from the contents of AL NOTE: The carry flag is not affected. AF, OF,PF, SF,ZF flags affected IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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NEG • This replaces the number in a destination with the 2’s complement of that number • AF ,CF , SF, PF, ZF affected • EXAMPLE: – NEG AL ; Replaces the number in AL with its 2’s complement – AL = 0011 0101 35H – 2’s = 1100 1011 CBH

COMPARISON • The comparison ins (CMP) compares a byte/word from the specified source with a byte/word from the specified destination. The source and destination both must be byte or word not a memory locations • The flags are updated by the CMP instruction they are AF,SF,ZF,OF,PF • EG: CMP BL,01H ; Compare immediate number 01H with byte in BL. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• AAS – ASCII adjust after subtraction – Mask upper nibble (3) from the code before subtraction

• DAS – Decimal adjust after subtraction – If the value of the low-order bits (D0-D3) in the AL is >9 , subtract 6 to the low – order 4 bits – If the value of the high-order bits (D7-D4) in the AL is >9 subtract 6 to the high – order 4 bits

MUL MUL – unsigned multiplication • This ins multiplies an unsigned byte from source and unsigned byte in AL or unsigned word from source and unsigned word in AX register. • Flags: MUL ins affect AF,PF,SF and ZF flags. • Example: MUL BL ; AL * BL result in AX MUL BX ; AX * BX result high word in DX low word in AX IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• IMUL – this ins multiplies a signed byte from some source and a signed byte in AL, – or a signed word from some source and a signed word in AX. – If the upper byte of a 16 bit result or the upper word of 32 bit result contains only copies of the sign bit , then the CF and the OF flags will both be 0’s. – The AF,PF,SF and ZF flags are undefined after IMUL.

• EG:IMUL BL – AL * BL RESULT IN AX IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• AAM – ASCII adjust after multiply – Adjust the product to 2 unpacked BCD digits in AX

Division instructions • DIV ins : DIV source • This ins is used to divide an unsigned word by a byte or to divide an unsigned double word by a word. • When dividing a word by a byte, the word must be in AX reg. • After the division AL will contain an 8 bit quotient and AH will contain an 8 bit remainder.


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Multiplication and division instruction • To divide a byte by a byte it is necessary to put the dividend byte in AL and fill AH with all 0. similarly to divide a word by a word, it is necessary to put the dividend word in AX and fill DX with all 0. • Flags: all flags are undefined after a DIV ins. • Eg: DIV CL – word in AX /byte in CL, Quotient in AL, Remainder in AH. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• IDIV instruction – IDIV source – This instruction is used to divide a signed word by a signed byte, – Or to divide a signed double word by a signed word

• AAD – Binary adjust before division

-- AAD converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. Done before division.

Sign extension • They are – CBW – CWD

• CBW – Copies the sign of a byte in AL to all bits in AH

• CWD – Copies the sign bit of a word in AX to all the bits of the DX register – Note: both CBW & CWD affects no flag

Logical instructions • The basic logic instruction include – NOT – AND – OR – EXCLUSIVE – OR, (XOR) and – TEST


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NOT • This inverts each bit of a byte or a word • Affects no flag • Example NOT AL ;

AL= 0010 1010 then AL= 1101 0101

AND • AND instuction : AND destination, source – Logically ANDs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination – AND operation with two inputs produces logic 1 only when both the inputs are logic 1 that is Y = A.B – The CF and OF flags are both 0 after AND. The PF, SF and ZF are affected, AF is undefined.

• OR instruction – OR destination, source – Or operation with two inputs produces result logic 1 when any one or both inputs are logic 1, that is Y = A+B. – This ins logically OR each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination. – The CF and OF are both 0 after OR.


• XOR ins – XOR destination, source – This ins logically XOR bit of the source byte or word with the corresponding bit in the destination. – Same bits 0, different bit 1

• TEST instruction- TEST destination, source – This instruction ANDs the contents of a source byte or word with the contents of the specified destination – SF , ZF affected – Eg: TEST AL, CL

; AND CL with AL


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Shift instructions • SAL/SHL – SAL/SHL destination, count s pecified destination to the left – Shfts each bit in the specified and 0 is stored at LSB position – MSB is shifted into the carry flag – eg: SAL CX,1

• SHR – SHR destination, count s pecified destination to the left – Shfts each bit in the specified and 0 is stored at MSB position – LSB is shifted into the carry flag – Eg: SHR CX,1

• SAR – SAR destination, count – Shifts the bits to right – Copy of the old MSB is put in the new MSB – LSB will be shifted into CF – EG: SAR CX,1

Rotate instructions • ROL • ROR • RCL • RCR

• ROL instr: – ROL destination , count – Rotates bits to left – Old MSB is placed as a new LSB and CF – Eg: ROL CX,1

• ROR instr : – ROR destination , count – Rotates bits to right – Old LSB is placed as a new MSB and new CF – Eg: ROR CX,1

• RCL instruc: – RCL destination , count – Rotates all the bits in left along with the carry flag – MSB is placed as a new carry and previous carry is placed as new LSB – EG: RCL CX,1

• RCR instruc – RCR destination , count – Rotates all the bits in right along with the carry flag – LSB is placed as a new carry and previous carry is placed as new MSB – EG: RCR CX,1

Program execution transfer • CALL- call the procedure or program • RET- returns the control from procedure • JMP-control transferred to the location • J cond

J cond • These instructions will cause a jump to label given in the instruction if the desired condition(s) occurs in the program before the execution of the instruction • Destination range -128 bytes to +127 bytes


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DESCRIPTION INSTRUCTIO N CODE

CONDITION FOR JUMP

JA / JNBE

Jump if above/ jump if not CF=0 & ZF=0 below or equal

JAE/ JNB

Jump if above or equal / jump if not below

CF=0 & ZF=1

JB/ JNAE/JC Jump if below/ jump if not CF=1 & ZF=0 above or equal JBE / JNA

Jump if below or equal / CF=1 & ZF=1 jump if not above


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INSTRUCTION DESCRIPTION CODE

CONDITION FOR JUMP

JE / JZ

Jump if equal / jump if Zero flag

ZF= 1

JG / JNLE

Jump if greater / jump if not less than or equal

ZF=0 & CF=0

JGE / JNL

Jump if greater than or equal / jump if not less than

SF=0

JL / JNGE

Jump if less than/ jump SF≠ 0 if not greater than or IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1 equal

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CONDITION FOR JUMP

JLE / JNG

Jump if less than or equal / jump if not greater

ZF= 1 or SF ≠ 0

JNC

Jump if no carry

CF=0

JNE / JNZ

Jump if not equal / jump ZF=0 if not zero

JNO

Jump if no overflow

JNP / JPO

Jump if not parity / jump PF=0 if parity odd

OF=0


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CONDITION FOR JUMP

JNS

Jump if not sign or jump SF=0 if positive

JO

Jump if overflow flag=1

OF=1

JP / JPE

Jump if parity / jump if parity even

PF=1

JS

Jump if sign flag=1 or jump if negative

SF=1

JCXZ

Jump if CX is zero

CX=0


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Iteration control instructions • This instruc are used to execute a series of instruc some number of times • Number is specified in CX register • CX register is automatically decremented by one, each time after exec of LOOP instruction • Until CX=0 execution will jump to a destination specified in the instruction IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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CONDITION FOR JUMP

LOOP

loop through a sequence of instrc

CX=0

LOOPE/ LOOPZ


CX=0 or ZF=0

LOOPNE/ LOOPNZ


CX=0 or Zf=1


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Machine control and miscellaneous • STC- sets the carry flag, does not affect any flag • CLC- resets the carry flag to 0 • CMC- complements the carry flag • STD – set the direction flag to one, SI& DI decrementd • CLD- reset the direction flag to zero, SI & DI incrmentd IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• STI- Sets the interrupt flag to one, enable interrupt • CLI- resets the interrupt flag to zero, no interrupt • HLT- strop fetching and executing instructions • WAIT- enters idle condition, no processing


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• ESC instruction: – Used to pass instructions to a coprocessor such as the 8087 math coprocessor which shares the address and data bus with an 8086 – Instruc represented as 6 bit code embedded in esc instruc – Coprocessor decodes the instruc and carries out the action specified by the 6 bit code IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• LOCK – Used in multiprocessor systems – This allows a microprocessor to make sure that another processor does not take control of the system bus while it currently executing an critical instruction

• NOP – At the time of execution of NOP instruc, no operation is performed except fetch and decode


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Interrupt instructions • INT, INTO, IRET • INT – General Format : INT type – This instruc causes the 8086 to call a far procedure. – Type refers to a number between 0-255 which identifies the interrupt – Address of the procedure is taken from the memory whose address is four times the type number IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• INTO – If the overflow flag is set, this instruc will cause the 8086 to do an indirect far call to a procedure you write to handle overflow condition

• IRET – Used at the end of the ISR to return execution to the interrupted program


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String data transfer instruction MOVS/MOVSB/MOVSW

• These ins copy a byte from a location in the data segment to a location in the extra segment. The offset of the source byte in the DS must be in the SI reg. the offset of destination in the extra segment must be contained in the DI register. Eg: • CLD – clear direction flag to auto increment SI and DI • MOV DS,AX – initialize data segment register to 0 • MOV SI,2000H – Load offset of start of source string into SI IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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String data transfer instruction • REP/REPE/REPZ/REPNE/REPNZ • REP is a prefix which is written before one of the string ins. These ins repeat until specified condition exists. • Eg: REPZ CMP SB – COMPARE STRING BYTES UNTIL CX=0 OR UNTIL STRING BYTES NOT EQUAL.


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Instruction code

condition for exit

REP

CX= 0

REPE / REPZ CX=0 or ZF=0 REPNE / REPNZ

CX=0 or ZF=1


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String data transfer instruction • LODS/LODSB/LODSW – This ins copies a byte from a string location pointed by SI to AL or a word from the string location pointed to by SI to AX . – LODS does not affect any flags. LODSB copies byte and LODSW copies a word.

• STOS/STOSB/STOSW – The STOS ins copies a byte from AL or a word to DI, STOS does not affect the flag, STOSB – copies byte, and STOSW copies a word. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives •

• • •

Assembler directives There are some instructions in the assembly level language program which are not a part of processor ins set. The instructions are instructions to the assembler, linker and loader. These are referred to as pseudo-operations or as assembler directives. The assembler directives enable to control the way in which a pgm assembles and lists. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives • There are many specialized assembler directives. They are • Align – Align directive forces the assembler to align the next segment at an address divisible by specified divisor.

• The general format for this number is

ALIGN number • Where the number can be 2,4,8 or 16 IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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• Assume – The 8086 at any time can directly address four physical segments which include a code segment, DS, SS and ES. – The 8086 may contain a number of logical segments. – ASSUME CS:code, DS:Data, SS:Stack

• CODE – This directive provides shortcut in def of the CS. – General format for this directive is code [name] – The name is optional IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives • DATA – this directive provides shortcut in definition of the data segment. DB – DEFINE BYTE DW – DEFINE WORD DD – DEFINE DOUBLEWORD DQ – DEFINE QUADWORD DT – DEFINE TEN BYTES


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DUP –This DUP directive can be used to initialize several locations and to assign values to these locations – Format name data _ type num DUP (value)


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Assembler directives • END – the END directive is put after the last statement of a pgm to tell the assembler that this is the end of the pgm module. • EQU – this EQU directive is used to redefine a data name or variable with another data name, variable. • EVEN- EVEN tells the assembler to advance the location counter if necessary so that the next defined data item or label is aligned on an even storage boundary IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives • EXTRN – the EXTRN directive is used to inform assembler that the names or labels following the directive are in some other assembly module. • GROUP – a pgm may contain several segments of the same type. The purpose of the group is to collect them all under one name, so that they reside within one segment usually a data segment


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Assembler directives • LABEL – assembler uses a location counter to keep track of how many bytes it is from the start of a segment at any time. The LABEL directive is used to give a name to the current value in the location counter. • LENGTH – it is an operator which tells the assembler to determine the number of elements in some named data item such as a string or array. • TITLE – this directive help to control the format of a listing of an assembled pf. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives • MACRO and ENDM – the macros in the pgm can be defined by MACRO directive. ENDM directive is used along with the MACRO directive. ENDM defines the end of the macro. • MODEL – it is available in MASM version 5.0 and above. This directive provides shortcut in defining segments. ( small , medium, compact, large) • SHORT – a short is a operator. It is used to tell the assembler that the only 1 byte displacement is needed to code a jump ins. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives • NAME – the name directive is used at the start of a source pgm to give specific names to each assembly module. • OFFSET – it is an operator which tells the assembler to determine the offset or displacement of a named data item from the start of the segment which contains it. • ORG – the assembler uses a location counter to account for its relative position in a data or code segment. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives • PTR – it is used to assign a specific type to a variable or to a label. It is used to override the declared type of variable. • PAGE – this directive help to control the format of a listing of an assembled pgm. At the start of a pgm the PAGE specifies the max number. • PROC and ENDP – the procedure in the pgm can be defined by PROC directive. This directive is used along with PROC directive . ENDP defines the end of the procedure. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembler directives • PUBLIC – large pgm are usually written as several separate modules. Each module is individually assembled, tested and debugged. • SEGMENT and ENDS – an assembly pgm in .EXE format consists of one or more segments. The start of these segment are defined by SEGMENT directive and the ENDS statement indicates the end of the segment. • STACK – this directive provides shortcut in definition of the stack segment. • TYPE – it is an operator which tells assembler to determine the type of specified variable. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembly language programming • A program is set of instructions arranged in the specific sequence to do the specific task. • Steps involved in programming  Specifying the problem  Designing the problem solution  Coding  Debugging  To write the program the programmer should know  How to develop program logic  How to tell the program to the processor  How to code the program  How to test the program IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Assembly language programming • Flow chart To develop the programming logic programmer has to write down various action which are to be performed. • Symbols used are  Oval – it indicates start or stop operation  Arrow – it indicates flow with direction  Parallelogram – input/output operation  Rectangle - process operation  Diamond – decision making operation  Double sided rectangle – predefined process  Circle with alphabet - continuation IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Languages used for programming • In any MP the system understands the ins in the binary form. The three languages levels that can be used to write a program are • Machine level programs – language consist of binary codes • Assembly level programs – language consists of mnemonics • High level programs – language consists of English like statements IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Example .To write an assembly language program

in 8086 to sort the array stored at location 1100 in ascending order. • ALGORITHM: • Start program. • Get the source. • Move CL and [SI] & decrement CL. • Move [SI] to CH and decrement CH and increment SI. • Compare AL,SI if no carry exchange AL & SI and AL & [SI-1]. • If carry, decrement CH and check for zero and repeat the steps. • Stop the program. IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Flowchart

START Get the source address Move the [SI] & CL. Decrement CL Move 1100 to SI. Decrement CH, Increment SI Move source to AL. Increment SI Compare AL & SI

no

Check for carry

yes Exchange AL & [SI] * also AL & [SI-1]

Check for 0

yes Decrement CL

Check for 0

no

IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232yes /Unit I / PPT/ Version 1.1

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PROGRAM: START

REPEAT

REPCOM

AHEAD

ORG MOV MOV DEC MOV MOV DEC INC MOV INC CMP JC XCHG XCHG DEC JNZ DEC JNZ HLT

1000H SI, 1100H CL, [SI] CL SI, 1100H CH, [SI] CH SI AL, [SI] SI AL, [SI] AHEAD AL, [SI] AL, [SI-1] CH REPCOM CL REPEAT


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Interrupts and interrupt service routines • Interrupts alter a program’s flow of control – Behavior is similar to a procedure call • Some significant differences between the two

• Interrupt causes transfer of control to an interrupt service routine (ISR) • ISR is also called a handler

• When the ISR is completed, the original program resumes execution • Interrupts provide an efficient way to handle unanticipated events IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Interrupts versus Procedures Interrupts • Initiated by both software and hardware • Can handle anticipated and unanticipated internal as well as external events • ISRs or interrupt handlers are memory resident • Use numbers to identify an interrupt service • (E)FLAGS register is saved automatically

Procedures • Can only be initiated by software • Can handle anticipated events that are coded into the program • Typically loaded along with the program • Use meaningful names to indicate their function • Do not save the (E)FLAGS register


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A Taxonomy of Pentium Interrupts


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Various Ways of Interacting with I/O Devices


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Interrupt Processing in Real Mode • Uses an interrupt vector table that stores pointers to the associated interrupt handlers. – This table is located at base address zero.

• Each entry in this table consists of a CS:IP pointer to the associated ISRs – Each entry or vector requires four bytes: • Two bytes for specifying CS • Two bytes for the offset

• Up to 256 interrupts are supported (0 to 255). IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Interrupt Vector Table


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Interrupt Number to Vector Translation • Interrupt numbers range from 0 to 255

Example

• Interrupt number acts as an index into the interrupt vector table

2 * 4 = 8H • The first two bytes at 8H are taken as the offset value • The next two bytes (i.e., at address AH) are used as the CS value

• Since each vector takes 4 bytes, interrupt number is multiplied by 4 to get the corresponding ISR pointer

• For interrupt 2, the memory address is


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A Typical ISR Structure • Just like procedures, ISRs should end with a return statement to return control back • The interrupt return (iret) is used of this purpose ;save the registers used in the ISR sti

;enable further interrupts

. . . ISR body . . . ;restore the saved registers iret ;return to interrupted program IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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What Happens When An Interrupt Occurs? • Push flags register onto the stack • Clear interrupt enable and trap flags – This disables further interrupts – Use sti to enable interrupts • Push CS and IP registers onto the stack • Load CS with the 16-bit data at memory address

interrupt-type * 4 + 2 • Load IP with the 16-bit data at memory address

interrupt-type

*

4


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Interrupt Enable Flag Instructions • Interrupt enable flag controls whether the processor should be interrupted or not • Clearing this flag disables all further interrupts until it is set – Use CLI (clear interrupt) instruction for this purpose – It is cleared as part interrupt processing • Unless there is special reason to block further interrupts, enable interrupts in your ISR – Use STI (set interrupt) instruction for this purpose


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Returning From An ISR • As in procedures, the last instruction in an ISR should be IRET • The actions taken on IRET are: – pop the 16-bit value on top of the stack into IP register – pop the 16-bit value on top of the stack into CS register – pop the 16-bit value on top of the stack into the flags register • As in procedures, make sure that your ISR does not leave any data on the stack – Match your push and pop operations within the ISR IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Dedicated Interrupts • Several Pentium predefined interrupts --called dedicated interrupts • These include the first five interrupts: interrupt type Purpose 0 Divide error 1 Single-step 2 Nonmaskable interrupt (MNI) 3 Breakpoint 4 Overflow IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Dedicated Interrupts (cont’d) • Divide Error Interrupt – CPU generates a type 0 interrupt whenever the div/idiv instructions result in a quotient that is larger than the destination specified

• Single-Step Interrupt – Useful in debugging – To single step, Trap Flag (TF) should be set – CPU automatically generates a type 1 interrupt after executing each instruction if TF is set – Type 1 ISR can be used to present the system state to the user IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Dedicated Interrupts (cont’d) • Breakpoint Interrupt – Useful in debugging – CPU generates a type 3 interrupt – Generated by executing a special single-byte version of int 3 instruction (opcode CCH) • Overflow Interrupt – Two ways of generating this type 4 interrupt 4 (unconditionally generates a type 4 interrupt)

•

int

•

into (interrupt is generated only if the overflow flag is set)

– We do not normally use into as we can use jo/jno conditional jumps to take care of overflow


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A Single-Step Interrupt Example • Objectives: – To demonstrate how ISRs can be defined and installed (i.e., user defined ISRs) – How trap flag can be manipulated • There are no instruction to set/clear the trap flag unlike the interrupt enable flag sti/cli

• We write our own type 1 ISR that displays the contents of AX and BX registers after each instruction has been executed IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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Hardware Interrupts • Software interrupts are synchronous events – Caused by executing the int instruction • Hardware interrupts are of hardware origin and asynchronous in nature – Typically caused by applying an electrical signal to the processor chip • Hardware interrupts can be – Maskable – Non-maskable • Causes a type 2 interrupt IFET CE/ MCA/ II yr/ III sem/ MuP/MC9232 /Unit I / PPT/ Version 1.1

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How Are Hardware Interrupts Triggered? • Non-maskable interrupt is triggered by applying an electrical signal to the MNI pin of Pentium – Processor always responds to this signal – Cannot be disabled under program control • Maskable interrupt is triggered by applying an electrical signal to the INTR (INTerrupt Request) pin of Pentium – Pentium recognizes this interrupt only if IF (interrupt enable flag) is set – Interrupts can be masked or disabled by clearing IF


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How Does the CPU Know the Interrupt Type? • Interrupt invocation process is common to all interrupts – Whether originated in software or hardware • For hardware interrupts, CPU initiates an interrupt acknowledge sequence – CPU sends out interrupt acknowledge (INTA) signal – In response, interrupting device places interrupt type number on the data bus – CPU uses this number to invoke the ISR that should service the device (as in software interrupts)


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microprocessor and its applications

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