Modeling of Spatially Distributed Microwave Circuits Michael Steer1 Andreas Cangellaris2 1
2
Department of Electrical and Computer Engineering North Carolina State University Raleigh, North Carolina USA, 27695
[email protected]
Department of Electrical and Computer Engineering University of Illinois, Urbana Champaign Urbana Champaign, Illinois USA, 61801
[email protected]
IMS2005
Outline
Why is it so difficult to design and model circuits with spatially distributed elements
Revisit circuit and network theory Revisit the concept of ground Circuit Theory for Spatially Distributed Systems
Research tools that address spatially distributed circuits Examples (throughout)
Opto Electronic Modeling On-Chip Supply/Ground Modeling
Workshop WFG: REDISCOVERING CIRCUIT DESIGN TECHNIQUES FOR MICROWAVE COMPONENTS, CIRCUITS AND SUBSYSTEMS: THE EFFICIENCY AND POWER OF EM/CIRCUIT CODESIGN
Motivation
Mixed Signal System Only really have good EDA solutions for digital. DIGITAL
ANALOG (feedback)
Many HARD modeling problems:
MICROWAVE (distributed)
RF (no feedback)
PACKAGE (distributed)
Reflector VCSEL Lens
Is there a common solution strategy?
VCSEL Modeling with Optical Feedback
YES! = Local Reference Terminals
RF design is difficult as EDA cannot be used EDA to determine the system performance measures.. To streamline design we must revolutionize our ability to predict system performance.
OPTICAL
MECHANICAL
S
G
Delay
D
Active Antennas
Courtesy Rockwell Science Center
Background Reading
Where is ground? A fundamental consideration in handling spatially distributed circuits. Circuits (conventionally) have a single ground.
Background Reading
Microstrip Model
In a Field Simulator Voltages Are Determined By Integrating The Electric Field Along a Path In Microstrip Problems the Field is Integrated Over The Paths Shown to Obtain V The Path of Integration Matters The Dashed Path Yields a Different Value of V2 V 1
V 2
Not the same point electrically.
Local reference terminal concept This avoids non-physical connections and therefore is fundamental for the analysis of spatially distributed circuits as well as for simultaneous thermal-electrical simulations.
Microstrip Model V2
V1 REF
V1
REF
V2
REF
V1
V2
REF Network Model:
REF
⎡ S11 ⎢S ⎣ 21
S12 ⎤ But a (SPICE) Circuit does not have two ⎥ reference terminals. S 22 ⎦
Modeling a Transformer
REF
LOCAL REFERENCE TERMINAL
How to extend this beyond two terminal ports?
Modeling Transformer Network
IDEAL TRANSFORMER
IN SPICE Or your Favorite simulator
IDEAL TRANSFORMERS
NO
BETTER
TWO LOCAL REFERENCE NODES
1 MΩ IN SPICE Or your Favorite simulator
=
OR
= 1 MΩ
Modeling Transformer Network Local Reference Group Concept Really need simulator support for multiple ‘grounds’ i.e. local reference terminals
Local reference node concept This avoids non-physical connections and therefore is fundamental for the analysis of spatially distributed circuits as well as for simultaneous thermal-electrical simulations.
V1 REF LOCAL REFERENCE TERMINAL Our common view of a port is that it has two terminals
=
V2 REF
i2
i1
1 i1
How to extend this beyond two terminal ports? Local Reference Terminal
Spatially Distributed Modeling
KEY CONCEPT: LOCAL REFERENCE TERMINAL
Kunisch and Wolff (preliminary concept)
Khalil and Steer (full concept)
KCL applies to this local reference group This is a multi terminal port!
Quasi-Optical Amplifier
2 i2
Nodal Admittance Matrix Determination Nodal Admittance Description Required in Microwave Circuit Simulators Process: Guess a node voltage and calculate node current.
Locally Reference Group (Single Local Reference Terminal)
LOCAL REFERENCE NODE
Using MOM model to develop model of spatially distributed system.
Grid Amplifier (Spatial Power Combiner) It is important to do circuit/field co-simulation More accurate. Uncover unexpected physics.
Things learnt when it is done right. Role of Symmetry
Comparison of measured and simulated results. BEAM CENTER
BEAM CENTER
Full linear + nonlinear simulation with integrated field solution
BEAM CENTER
Symmetry Broken
Things learnt when it is done right. Role of Symmetry
Symmetry Lessons Learnt
GRID SYMMETRY
CIRCUIT SYMMETRY
BEAM CENTER
HORIZONTAL AXIS OF LINEAR SYMMETRY
VERTICAL AXIS OF LINEAR SYMMETRY
NORMAL AXIS OF CIRCULAR SYMMETRY
The grid symmetry and circuit symmetry are fundamentally incompatible.
Symmetry Effects
Modeling Concept NO PLANE OF SYMMETRY
SPATIALLY DISTRIBUTED CIRCUIT
LINEAR CIRCUIT
NONLINEAR NETWORK
NO POINT OF SYMMETRY
LINEAR CIRCUIT
LINEAR NETWORK
+ Optoelectronic + Any other physics Incorporate using locally referenced groups.
THERMAL NETWORK
EM-PDK (Em-Aware Process Design Kit) Mixed Layout ElectricTM
Parasitic Extractor
Commercial MESHER
MESH GENERATION
UIUC2D
MACROMODEL NETLIST SIMULATION
fREEDA®
EM-PDK (Java) is both a stand alone program and integrated into Electric. STAND ALONE MODE: PARSES A LAYOUT FILE AND EXTRACTS EM FEATURES, EM_Aware, CREATES CIF OUTPUT. (METALS, DIELECTRICS THICKNESSES AND PROPERTIES ONLY). PASS TO EM SIMULATOR. ELECTRIC MODE IDENTIFIES LOCAL REFERENCE GROUPS AND ASSIGNS LOCAL REFERENCE TERMINALS. ASSIGNS TERMINAL NUMBERS. CREATES SPICE FILE + EM-Aware LAYOUT FILE
Electric (Editor)
S2IBIS R,L,C,G PRIME ⎛ a ai ⎞ ⎟G i Y( s) = G 0 + sC 0 + ∑ ⎜⎜ i + s − pi ⎟⎠ i ⎝ s − pi
+ -
f REEDA CIRCUIT SIMULATION
L L
EM-fREEDA-Spice Interface
Handles MOS-Bipolar Handles MOS-Bipolar Schematics, HDLs Common Layout-Schematic Interface Supports CIF, GDS II, VHDL, Verilog etc.. Custom IC layout tool.
Coupled Inductors
Step 1. Foster’s model fit to simulated or measured frequency data. GO TO fREEDA directly Step 2. Synthesize R, L, C, K subcircuit (many elements) GO TO Spice Why Foster’s model ? ¾ It is a convenient method that facilitates the direct synthesis of an equivalent circuit representation of the power distribution network.
NCSU MILESTONE Modifications made to include naming of nodes at points of connection between schematic and layout. Support for materials properties added. Modifications to be included in next release of Electric Editor.
G2M
DC2LIGHT
EM – Aware Technology file
Integrating Electric & EM-PDK
EM-PDK
SCHEMATIC
Layout
LAYOUT
ELECTRIC
¾ Further this method is guaranteed to be causal and circumvents the problem of implementing reduced order models with problems concerning stability (AWE method), aliasing (Convolution based on Impulse response) and series approximations problem (Numerical Inversion of Laplace Transform Technique).
• Layer Thickness.
Foster’s canonical representation :
• Loss Tangent.
H(s) = ∑
• Dielectric Constant.
m
kj j =1 s – pj
m +
∑ j =1
aj s – pj
+
aj* s – pj*
where kj /(s-pj) represents the real pole and aj/(s-pj) and aj*/(s-pj*) together represents the complex conjugate pair
Indicates LRT
EM-fREEDA Interface N-Port Foster Model PORT 1 LRG 1
Multigrid-Enhanced EM Modeling of the Power Grid On Chip Maxwell equation’s-based modeling
o
o PORT2
o
Finite Volume model
Key Attributes
LRG 2 o
Foster N – Terminal Network
The transfer function is given as,
I(s) = H(s)V(s)
PORT N LRG N
o o
FV-Based Modeling Methodology
Model developed directly from physical structure Cumbersome and error-prone extraction of [L] and [C] avoided Rigorous modeling of electromagnetic effects In addition to power switching noise analysis it enables prediction of power grid-induced EMI between different blocks on the chip
Implementation of Variable-Size Grid
Finite-volume discretization of Maxwell’s equations
K K K K d E ⋅ dl = − ∫∫ µ H ⋅ dS F dt SF K K d K K K K ⋅ = ε ⋅ + σ H dl E dS E ∫∫S A ⋅ dS v∫ C A dt ∫∫ S A Micron-size cross-sectional dimensions and regular layout of the grid exploited to contain model complexity
v∫ C
Grid size of the order of grid feature size Assignment of unknown electric & magnetic fields in space dictated by the electromagnetic effects that must be captured for accurate simulation
Ohmic loss in the wires Inductive effects during switching Capacitive coupling and common impedance coupling for grid-induced interference calculation
Ex
Ez
Hz
Ey
z Hy
(a) Grid Coarse
y
Fine Grid
The choice of grid coarseness is dependent on the simulation objective and the desired accuracy.
Switching noise simulation only: Coarse grid Power grid-induced interference: Finer grid
Compatibility with SPICE The state-space form of the discrete model, ⎡G ⎢D ⎣ e
“Cartoon” of the On-Chip Grid
Dh ⎤ ⎡ e ⎤ ⎡ C 0 ⎤ d ⎡ e ⎤ ⎡ i S ⎤ + = R ⎥⎦ ⎢⎣h ⎥⎦ ⎢⎣ 0 L ⎥⎦ dt ⎢⎣ h ⎥⎦ ⎢⎣ v S ⎥⎦
is of the same form with the MNA formalism used in SPICE Hence, it facilitates direct incorporation of lumped circuits and behavioral models for drivers and receivers
e , h : the discrete unknown fields G, R, L, C, Dh, De : sparse matrices (dependent on material and geometric properties of the structure) iS, vS : voltage & current sources connected to the grid
Top view of Metal-1 Layer
Additional Features of Solver
Inverter Model
Convenient interface to models for the offchip power grid
Si Substrate
Can be incorporated either in terms of SPICE net lists or in terms of a matrix rational function representation of their multi-port form
Modeling of the semiconductor substrate
Effected through position- and frequencydependent surface impedance relationships cast in terms of rational functions
Impact of semiconductor substrate on power grid switching response
Impact of semiconductor substrate… 1.6 Case0 Case1 Case2 Gate Input
1.4
SiO2
ε3 , µ3=µ 0 , σ3= 0
t2
p- epitaxy
ε2 , µ2=µ 0 , σ2≠ 0
t1
p+ bulk
ε1 , µ1=µ 0 , σ1≠ 0
z x
1.2 1
y
Voltage (V)
t3
0.8
Suppressed overshoot and oscillation
0.6 0.4 0.2
Case 0: Semiconductor substrate modeled as PEC Case 1: t1 = 198 µm, σ1 = 104 S/m, t2 = 2 µm, and σ2 = 10 S/m Case 2: t1 = 200 µm, σ1 = 104 S/m, t2 = 0 (no epi)
0 -0.2 -0.4 0
50
100
150
200
250
300
Time (ps)
Transient EM Modeling of Power Switching Visualization of on-chip supply voltage disturbance during simultaneous switching at all nodes
Transient EM Modeling of Power Switching Visualization of on-chip supply voltage disturbance during switching of drivers in central region only
Modeling of Substrate Noise Simulation
Volts
0
0
Summary
Experiment
Volts
Buffer -0.5 Output -1
-1.5
-1.8
-2
Millivolts
20 0 Sensor -20 Output -40 -60 -80 -100
-20 -40 -60 1.4
1
1.8 2.2 Time (µs)
2.6
Long interconnect from buffer output to pad: Its coupling to substrate critical for accurate prediction of substrate-induced noise
Millivolts
1.4
1.8 2.2 Time (µs)
Noise injector
Direct implementation of SPICE models for non-linear drivers, decoupling caps, etc… Supports convenient interfacing with models for the off-chip power distribution network
Supports both simultaneous switching noise and power grid-induced interference prediction
Noise sensor
VCSEL VCSEL
P-contact
VCSEL Feedback Results:
GaAs
AlA s
AlAs Oxide
Optical Component Feedback:
Distributed Noise Injector
Feedback Modeling:
3
2.6
Includes impact of semiconductor substrate
SPICE Compatible
Optoelectronic Modeling
Electromagnetic rigor Comprehensive modeling
1
3
On-Chip Power Grid Transient Simulator
Power and Wavelength degradation due to two components f1=12mm, R=0.04
In0.2Ga0.8As
Optical systems have reflective surfaces Small feedback can effect laser dynamics Optical component reflection study is important fREEDA enables component reflection modeling
Al0.8Ga0.2As
Detector
Vcsel Lens1
Modeling Approach:
VCSEL
Laser output sensitive to feedback phase
Detector
Lens2
z=12mm
N-contact
Calculate resultant field at each component Back propagate the resultant field to laser
f2=12mm, R=0.04
GaAs
Optical Power No feedback
z=12mm Output power degradation due to single and double lens feedback
L1 feedback
L1+L2 feedback
Wavelength
No feedback
L1 feedback
Output wavelength degradation due to single and double lens feedback
L1+L2 feedback
Nonlinear Electro-Thermal Element i i = f(x1,x2) v= g(x1,x2)
ELECTRICAL COMPONENT
T= x2
Nonlinear Electro-Thermal Element NONLINEAR ELECTRO-THERMAL ELEMENT
LINEAR ELECTRICAL NETWORK
v
i ELECTRICAL COMPONENT
v,i
i = f(x1,x2) v= g(x1,x2)
v
LINEAR ELECTRICAL NETWORK
T
THERMAL NETWORK
h THERMAL COMPONENT h(t)=h(v(t),i(t))
THERMAL NETWORK
T
T= x2
v,i h
THERMAL COMPONENT h(t)=h(v(t),i(t)) THERMAL GROUND (0 K)
THERMAL GROUND (0 K)
fREEDA Multiphysics Simulator
Time Delays Spice handles only short (< 3 time step) time delays.
4
10
Product: fREEDA
REQUIREMENTS FOR FIRST PASS DESIGNS: A Rapid development of models B 140 dB dynamic range required C Integration of tools. (new concepts for mixed digital/analog simulation; transmission lines in transient simulators) D Achieve 1 or 2 fab cycles (need exact emulation)
3
10 Observed delay (ns)
TWTA used to validated fREEDA’s ability to handle models with long time delays. Also implemented in many transistor models.
2
10
1
10
Validation in Progress
0
1
10
2
10 Specified delay (ns)
3
10
1 0.5 0 -0.5
Output Terminal Voltage (volts)
Input Terminal Voltage (volts)
10 0 10
-1 0
2000
4000
6000
8000 Time (ps)
10000
12000
14000
0
2000
4000
6000
8000 Time (ps)
10000
12000
14000
3 2 1 0 -1 -2 -3
Extracted amplitude and time-delay parameters for in-band linear and nonlinear (3,5,7th order) from 8510C measurements of an HP 495A TWTA. Created TWTA model using 4 instances of Vccsd with extracted parameters. Voltage gain ~10, transit time ~10.5 nsec reflect well in simulated results. (Sinusoidal input at 7.5 GHz.)
4
10
STATE-OF-THE-ART AT START OF PROGRAM: A Limited ability to model new devices B Inadequate dynamic range 40–60 dB C Many unconnected EDA tools D NRE for a mixed signal chip $50M + 2 years (Bluetooth/802.11 complexity, 8–20 fab cycles)
TECHNOLOGIES DEVELOPED A Rapid development of models (completed) (6 days versus 1 year in spice, e.g. BSIM3SOIv3 ) B 140 dB dynamic range required to determine actual performance (achieved 160 dB) C Proven distributed circuit concepts: True time delay for the first time; multiphysics/multiscale environment. D Experimental validation of precise simulations.
Major features
Accessibility
Feature
Initial State of The Art
Goal
Achieved
Dynamic Range Multi Physics Time Delay
40–60 dB SPICE > 120 dB ADS
140 dB
160 dB
Limited
Thermal / EM / Circuit Unlimited
Thermal / EM / Circuit Unlimited
2 or 3 time steps
fREEDA runs on all Linux and cygwin flavors Can be downloaded as a single executable on windows (16 MB) (Must first install cygwin) Improved Documentation (on line)
www.freeda.org
Transient Dynamic Range 0.05
Spice handles only short (< 4 time step) time delays.
SPICE (UCB) Algorithm
fREEDA has no limit
160 dB 0.03
Error
40 dB line 0.02
CONVENTIONAL
Result from Backward Euler
Error estimate
0.01 IDEAL RESULT
Result from trapezoidal
NEW
0 Tn-1 Tn
Tn+1
0
0.002 0.004 0.006 0.008 0.01
Tolerance
3
10 Observed delay (ns)
Primarily achieved through • better error estimation • better time point selection
TWTA used to validated fREEDA’s ability to handle models with long time delays. Also implemented in many transistor models. Input Terminal Voltage (volts)
X-band MMIC
4
10
2
10
1
1
10
0.5 0
10 0 10
0
1
10
2
10 Specified delay (ns)
-0.5
Output Terminal Voltage (volts)
(Defined as the detection of a small signal in the presence of a 0.04 large signal.)
Time Delays
-1 0
2000
4000
6000
8000 Time (ps)
10000
12000
14000
8000 Time (ps)
10000
12000
14000
3 2
1 ns
1 0 -1 -2 -3 0
2000
4000
6000
3
10
4
10
Conclusions New Circuit Concept
Products
Delivery of best in class software tools: (beta release)
fREEDA
High dynamic range multi physics circuit simulator Easy development of advanced device models Now available as single binary for Windows (16 MB)
S2IBIS3
EMPDK
Digital macromodeling tool
UIUC2D EM modeling tool for 2D geometries ICWAVE
PRIME
V1
Em-Aware physical design kit tool (JAVA) (Can also be run in conjunction with Electric Editor)
V2
REF
On chip, comprehensive, 3D EM modeling EM reduced Order Model macromodeler tool (Foster Model) Directly interfaces with fREEDA Synthesizes R, L, C, K models for Spice.
LOCAL REFERENCE TERMINAL Our common view of a port is that it has two terminals
REF
i2
i1
1 i1
All packages can be accessed through http://www.freeda.org PRIME and UIUC2D http://alpha1.ece.uiuc.edu/download For PRIME: username: prime pwd: fitting For UIUC2D: username: uiuc2d pwd: rlcgsyn For ICWAVE Contact Andreas Cangellaris
How to extend this beyond two terminal ports?
Acknowledgements
UIUC TEAM Integral Equation Solvers
FEM Solvers
V. Okhmatovski A. Rong J. Morsey V. Kourkoulos T. Yioultsis L. Proekt (Post-doc)
Model Order Reduction
T. Yioultsis J. Morsey
NCSU TEAM Simulator
C. Christofferson S. Luniya S. Wang S. Skaggs F. Hart M. Basel C.-R. Chang P. Heron W. Kanj G. Rhyne
EM-Circuit Integration
Sponsors: DARPA Army Research Office
M. Abdullah A. Khalil J. Patwardhan S. Nakazawa C. Hicks U. Mughal T. Nuteson M. Summers R. Mohan R. Bollapragada S. Uppathil B. Biswas
Modeling
N. Kriplani S. Velu H. Guiterrez W. Jang
2 i2
