Showing posts with label Interview Questions. Show all posts
7/21/13
Only-VLSI: Interview Questions switch.The line should keep moving unless any of the following conditions arise: (1) If the emergency switch is press ed (2) If the senor1 and sensor2 are activated at the same time. (3) If sensor 2 and sensor3 are activated at the same time. (4) If all the sensors are activated at the same time Suppose a combinational circuit for above case is to be implemented only with NAND Gates. H ow many minimum number of 2 input NAND gates are required? Answer 8. In a 4-bit Johnson counter How many unused states are present? Answer 9. Design a 3 input NAND gate using minimum number of 2 input NAND gates. Answer 10. How can you convert a JK flip-flop to a D flip-flop? Answer 11. What are the differences between a flip-flop and a latch? Answer 12. What i s the difference between Mealy and Moore FS M? Answer 13. What are v arious types of s tate encoding techniques? Explain them. Answer 14. Define Clock Skew , Negative Clock Skew, Positive Clock Skew. Answer 15. Give the transistor level circuit of a CM OS NAND g ate. Answer 16. Desig n a 4-bit comparator circuit. Answer 17. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)? Answer 18. Define M etastability. Answer 19. Compare and contrast between 1's complement and 2's complement notation. Answer 20. Give the transistor level circuit of CMOS, nMOS, pMOS, and TTL inverter gate. Answer 21. What are s et up time and hold time constraints? Answer 22. Give a circuit to divide frequency of clock cycle by two. Answer 23. Des ign a divide-by-3 s equential circuit with 50% duty circle. Answer 24. Explain different types of adder circuits. Answer 25. Give two ways of converting a two input NAND gate to an inverter. Answer 26. Draw a Transmission Gate-based D-Latch. Answer
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Only-VLSI: Interview Questions 27. Desig n a FSM which detects the sequence 10101 from a s erial line without overlapping. Answer 28. Desig n a FSM which detects the sequence 10101 from a s erial line with overlapping. Answer 29. Give the design of 8x 1 multiplexer using 2x1 multiplexers. Answer 30. Desig n a counter which counts from 1 to 10 ( R esets to 1, after 10 ). Answer 31. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate. Answer 32. Design a circuit which doubles the frequency of a given input clock signal. Answer 33. Implement a D-latch using 2x1 multiplexer(s). Answer 34. Give the excitation table of a JK flip-flop. Answer 35. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14. Answer 36. What is race condition? Answer 37. Give 1's and 2's complement of 19. Answer 38. Design a 3:6 decoder. Answer 39. If A*B=C and C*A =B then, what is the Boolean operator * ? Answer 40. Design a 3 bit Gray Counter. Answer 41. Expand the following: PLA, PAL , CPLD, FPGA. Answer 42. Implement the functions: X = A'BC + A BC + A'B'C' and Y = ABC + AB'C us ing a PLA. Answer 43. W hat are PLA and PAL ? Giv e the differences between them. Answer 44. What is LUT? Answer 45. What i s the si gnificance of FPGAs i n modern day electronics? (Applications of FPGA.) Answer 46. W hat are the differences between CPLD and FPGA. Answer 47. Compare and contrast FPGA and ASIC digital designing. Answer 48. Give True or False. (a) CPLD consumes less power per gate when compared to FPGA. (b) CPLD has more complexity than FPGA
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Only-VLSI: Interview Questions (d) FPGA can be used to verify the design before making a ASIC. (e) PALs have programmable OR plane. (f) FPGA designs are cheaper than corresponding ASIC, irrespective of design complexity. Answer 49. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL. Answer 50. Giv e the FPGA dig ital design cycle. Answer 51. What is DeMorgan's theorem? Answer 52. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form. Answer 53. How many s quares/cells will be present in the k- map of F( A, B, C )? Answer 54. Simplify F(A, B, C, D) = S ( 0, 1, 4, 5, 7, 8, 9, 12, 13) Answer 55. Simplify F(A, B, C) = S (0, 2, 4, 5, 6) into Product of Sums. Answer 56. The simplified expression obtained by using k-map method is unique. True or False. Ex plain your answer. Answer 57. Give the characteristic tables of R S, JK, D and T flip-flops. Answer 58. Give excitation tables of RS, JK, D and T flip-flops. Answer 59. Design a BCD counter with JK flip-flops Answer 60. Desig n a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops. Answer 44 Comments Labels: Interview Questions
Digital Design Interview Questions - 6 1. What is DeMorgan's theorem? Answer 2. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form. Answer 3. How many s quares/cells will be present in the k -map of F( A, B, C )? Answer 4. Simplify F(A, B, C, D) = Σ ( 0, 1, 4, 5, 7, 8, 9, 12, 13) Answer 5. Simplify F(A, B, C) = Σ (0, 2, 4, 5, 6) into Product of Sums. Answer 6. The simplified expression obtained by using k-map method is unique. True or False. Ex plain your answer. Answer 7. Giv e the characteristic tables of R S, JK, D and T flip-flops.
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Only-VLSI: Interview Questions 8. Give excitation tables of RS, JK, D and T flip-flops. Answer 9. Design a BCD counter with JK flip-flops Answer 10. Desig n a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops. Answer 1 Comments Labels: Interview Questions
Microprocessor Interview Questions - 5 1. Why are program counter and stack pointer 16-bit regis ters? Answer 2. What happens during DMA transfer? Answer 3. Define ISR. Answer 4. Define PSW. Answer 5. What are the execution modes available in x86 processors ? Answer 6. What i s meant real mode? Answer 7. What i s protected mode? Answer 8. What is virtual 8086 mode? Answer 9. What i s unreal mode? Answer 10. W hat is the difference between ISR and a function call? Answer 1 Comments Labels: Interview Questions
VLSI Interview Questions - 6 1. Why is NAND gate preferred over NOR gate for fabrication? Answer 2. Which transistor has higher gain: BJT or MOSFET and why? Answer 3. Why PMOS and NMOS are sized equally in a transmission gates? Answer 4. What is SCR? Answer 5. In CMOS digital design, why is the size of PMOS is generally higher than that of the NMOS? Answer 6. What is slack? Answer
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Only-VLSI: Interview Questions 7. What i s latch up? Answer 8. Why is the size of inverters in buffer design gradually increased? Why not give the output of a circuit to one large inverter? Answer 9. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus? Answer 10. W hat happens to delay if load capacitance is i ncreased? Answer 3 Comments Labels: Interview Questions
Microprocessor Interview Questions - 4 1. What is the size of flag register of 8086 processor? Answer 2. How many pin IC 8086 is? Answer 3. What i s the Max imum clock frequency of 8086? Answer 4. What is meant by instruction cycle? Answer 5. W hat is Von Neumann architecture? Answer 6. W hat is the main difference between 8086 and 8085? Answer 7. What does EAX mean? Answer 8. What type of ins tructions are av ailable in ins truction set of 8086? Answer 9. How is Stack Pointer affected when a PUSH and POP operations are performed? Answer 10. What are SIM and RIM instructions? Answer 1 Comments Labels: Interview Questions
Microprocessor Interview Questions - 3 1. How many bits processor is 8086? Answer 2. What are the sizes of data bus and address bus in 8086? Answer 3. What is the maximum addressable memory of 8086? Answer 4. How are 32-bit addresses stored in 8086? Answer 5. What are the 16-bit regi sters that are available in 8086? Answer
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Only-VLSI: Interview Questions 6. What are the different types of address modes available in 8086? Answer 7. How many flags are avai lable in flag regis ter? What are they? Answer 8. Explain the functioning of I P (instruction pointer). Answer 9. What are the vari ous types of interrupts present in 8086? Answer 10. How many segments are present in 8086? What are they? Answer 0 Comments Labels: Interview Questions
Digital Design Interview Questions - 5 1. Expand the following: PLA, PAL , CPLD, FPGA. Answer 2. Implement the functions: X = A'BC + A BC + A'B'C' and Y = ABC + A B'C using a PLA. Answer 3. W hat are PLA and PAL ? Giv e the differences between them. Answer 4. What is LUT? Answer 5. What i s the si gnificance of FPGAs in modern day electronics? (Applications of FPGA.) Answer 6. W hat are the differences between CPLD and FPGA. Answer 7. Compare and contrast FPGA and ASIC digital designing. Answer 8. Give True or False. (a) CPLD consumes less power per gate when compared to FPGA. (b) CPLD has more complexity than FPGA (c) FPGA design is slower than corresponding ASIC design. (d) FPGA can be used to verify the design before making a ASIC. (e) PALs have programmable OR plane. (f) FPGA designs are cheaper than corresponding ASIC, irrespective of design complexity. Answer 9. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL. Answer 10. Giv e the FPGA dig ital design cycle. Answer 2 Comments Labels: Interview Questions
Digital Design Interview Questions - 4 1. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate. Answer 2. Desi gn a circuit which doubles the frequency of a gi ven input clock s ignal.
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Only-VLSI: Interview Questions 3. Implement a D-latch using 2x1 multiplexer(s). Answer 4. Give the excitation table of a JK flip-flop. Answer 5. Giv e the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14. Answer 6. What is race condition? Answer 7. Giv e 1's and 2's complement of 19. Answer 8. Design a 3:6 decoder. Answer 9. If A*B=C and C*A =B then, what is the Boolean operator * ? Answer 10. Design a 3 bit Gray Counter. Answer 4 Comments Labels: Interview Questions
Verilog Interview Questions - 3 1. How are blocking and non-blocking s tatements ex ecuted? Answer 2. How do you model a s ynchronous and asynchronous reset in Verilog? Answer 3. What happens if there is connecting wires width mismatch? Answer 4. W hat are different options that can be used with $dis play statement in Verilog? Answer 5. Give the precedence order of the operators in Verilog. Answer 6. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason. Answer 7. Giv e 10 commonly used Verilog k eywords. Answer 8. Is it poss ible to optimize a Verilog code such that we can achieve low power design? Answer 9. How does the following code work? wire [3:0] a; always @(*) begin case (1'b1) a[0]: $display("Its a[0]"); a[1]: $display("Its a[1]"); a[2]: $display("Its a[2]"); a[3]: $display("Its a[3]"); default: $display("Its default") endcase end
7/21/13
Only-VLSI: Interview Questions 10. Which is updated first: signal or variable? Answer 7 Comments Labels: Interview Questions
VLSI Interview Questions - 5 This sections contains interview questions related to LOW POWER VLSI DESIGN. 1. What are the important aspects of VLSI optimization? Answer 2. What are the sources of power dissipation? Answer 3. W hat is the need for power reduction? Answer 4. Giv e some low power design techniques. Answer 5. Giv e a dis advantage of v oltage scaling technique for power reduction. Answer 6. Give an expression for switching power dissipation. Answer 7. W ill glitches in a logic circuit cause power wastage? Answer 8. What is the major source of power wastage in SRAM? Answer 9. W hat is the major problem associated with caches w.r.t low power design? Gi ve techniques to ov ercome it. Answer 10. Does software play any role in low power design? Answer 1 Comments Labels: Interview Questions
Digital Design Interview Questions - 1 1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What i s a multiplexer? Answer 4. What is a ring counter? Answer 5. Compare and C ontrast Synchronous and Asynchronous reset. Answer 6. What i s a Johnson counter? Answer 7. An as sembly line has 3 fail safe s ensors and one emergency shutdown switch.The line should keep moving unless any of the following conditions
7/21/13
Only-VLSI: Interview Questions (1) If the emergency switch is press ed (2) If the senor1 and sensor2 are activated at the same time. (3) If sensor 2 and sensor3 are activated at the same time. (4) If all the sensors are activated at the same time Suppose a combinational circuit for above case is to be implemented only with NAND Gates. H ow many minimum number of 2 input NAND gates are required? Answer 8. In a 4-bit Johnson counter How many unused states are present? Answer 9. Design a 3 input NAND gate using minimum number of 2 input NAND gates. Answer 10. How can you convert a JK flip-flop to a D flip-flop? Answer 13 Comments Labels: Interview Questions
VLSI Interview Questions - 4 1. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four? Answer 2. What are s tatic and dynamic power dissipation w.r.t to CMOS gate? Answer 3. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) considering Channel Length Modulation. Answer 4. Which is fastest among the following technologies: CMOS, BiCMOS, TTL, ECL? Answer 5. What is a transmission gate, and what is its typical use in VLSI? Answer 6. Draw the cross section of nMOS or pMOS. Answer 7. What s hould be done to the size of a pMOS transistor inorder to increase its threshold voltage? Answer 8. Explain the various MOSFET Capacitances and their significance. Answer 9. On what factors does the resistance of metal depend on? Answer 10. Draw the layout a CM OS NAND gate. Answer 1 Comments Labels: Interview Questions
VLSI Interview Questions - 3 1. Explain the voltage transfer characteristics of a CMOS Inverter. Answer 2. What should be done to the size of a nMOS transistor in order to increase its threshold voltage? Answer
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Only-VLSI: Interview Questions 3. What are the advantages of CMO S technology? Answer 4. Give the expression for CMOS switching power dissipation. Answer 5. Why is static power dissipation very low in CMOS technology when compared to others? Answer 6. What is velocity saturation? What are its effects? Answer 7. Why are pMOS transistor networks generally used to produce high s ignals, while nMOS networks are used to product low signals? Answer 8. Expand: DTL, RTL, ECL, TTL, CM OS, BiCMOS. Answer 9. On I C s chematics, transistors are usually labeled with two, or sometimes one number(s). What do each of those numbers mean? Answer 10. How do you calculate the delay in a CMOS circuit? Answer 2 Comments Labels: Interview Questions
VLSI Interview Questions - 2 1. Explain the various MOSFET capacitance and give their significance. Answer 2. W hat is the fundamental difference between a M OSFET and BJT ? Answer 3. What is meant by scaling in VLSI design? Describe various effects of scaling. Answer 4. What i s early effect? Answer 5. Compare and contrast analog and dig ital design. Answer 6. What are v arious types of the number notations? Explain them. Answer 7. W hy are most i nterrupts active low? Answer 8. Whi ch is better: synchronous res et or asynchronous reset s ignal? Answer 9. W hat is meant by 90nm technology? Answer 10. Compare enhancement and depletion mode devices. Answer 0 Comments Labels: Interview Questions
Digital Design Interview Questions - 2 1. What are the differences between a flip-flop and a latch?
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Only-VLSI: Interview Questions 2. What i s the difference between Mealy and Moore FS M? Answer 3. What are v arious types of s tate encoding techniques? Explain them. Answer 4. Define Clock Skew , Negative Clock Skew, Positive Clock Skew. Answer 5. Giv e the transistor level circuit of a CM OS NAND g ate. Answer 6. Desig n a 4-bit comparator circuit. Answer 7. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)? Answer 8. Define M etastability. Answer 9. Compare and contrast between 1's complement and 2's complement notation. Answer 10. Give the transistor level circuit of CMOS, nMOS, pMOS, and TTL inverter gate. Answer 1 Comments Labels: Interview Questions
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