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Experiment 1 Parity bit generator and checker Objectives: To implement the parity bit (even and odd) generator and checker.
Background Information: The most common error detection code used is the parity bit. A parity bit is an extra bit included with a binary message to make the total number of 1's either odd or even. In case of even parity, the parity bit is chosen so that the total number of 1's in the coded message is even. Alternatively, odd parity can be used in which the total number of 1's in the coded message is made odd. During transfer of information, the message at the sending-end is applied to a parity generator where the parity pit is generated. At the receiving-end a parity checker is used to detect single bit error in the transmitted data word by regenerate the parity bit in the same fashion as the generator and then compare with the parity bit transmitted.
Even parity bit generator and checker: This XOR gate is used to produce an error
Source
Destination
x y z P
Transmission Channel
P C Parity Generator
Parity Error Check Parity Checker
Figure 1-1 : Circuit diagram of the even parity bit generator and checker
Equipments: 1.
6 XOR logic gates (2 x 7486 TTL chip).
2.
Logic Lab Trainer.
3.
Interconnection leads.
Procedures: 1.
Derive the wiring diagram for the circuit in Figure 1-1.
2.
Collect all IC chips necessary to build the circuit from the IC drawers.
3.
Bring some connection wires with varying lengths.
4.
Insure that the power switch of the IC trainer is turned off.
5.
Plug the IC chips into the proper sockets.
6.
Connect the voltage supply and ground lines to the chips.
7.
Starting from left to right connect the outputs of one IC to the input of another ICs according to your wiring diagram.
8.
Once all connections have been done, turn on the power switch of the IC trainer.
9.
Produce a single-bit error and verify the correct functioning of the Parity Checker circuit.
10. After finishing the experiment, turn off the power switch and disconnect the wires and take out all IC chips from the trainer.
Odd parity bit generator and checker: This XOR gate is used to produc e an error
Source
Destination
x y z P
Transmis sio n Channel
P Parity Generator
Parity Check er
Figure 1-2 : Circuit diagram of the odd parity bit generator and checker
Equipments: 1.
6 XOR logic gates (7486 TTL–IC).
2.
2 Inverter gates (7404 TTL-IC)
3.
Logic Lab Trainer.
4.
Interconnection leads.
Procedures: 1.
Derive the wiring diagram for the circuit in Figure 1-2.
C Parity Error Chec k
2.
Collect all IC chips necessary to build this circuit
3.
Insure that the power switch of the IC trainer is turned off.
4.
Plug every IC chip into the proper socket.
5.
Connect the supply voltage and ground lines to the chips.
6.
Starting from left to right connect the outputs of one IC to the input of another ICs according to your wiring diagram.
7.
Once all connections have been done, turn on the power switch of the IC trainer.
8.
Produce a single-bit error and verify the correct functioning of the parity checker circuit.
9.
After finishing the experiment, turn off the power switch, disconnect the wires, take out all IC chips from the trainer, put back everything you have used, close IC trainer and clean your table.
Questions: 1.
According to the circuit you have done, find the truth table for the odd-parity checker.
2.
Considering 4-bit message to be transmitted, derive the parity circuit using odd parity bit.
