Rangkaian Elektronika - Chapter 07 2013

RANGKAIAN ELEKTRONIKA (ELECTRONIC CIRCUITS) oleh: Dr. Ir. Retno Wigajatri Purnamaningsih, Purnamaningsih, MT Tomy Abuzairi, ST, MT, M.Sc

Reference Books: 1. Robe Robert rt L. Boyl Boyles esta tad d and and Loui Louiss Nas Nashe hels lsky ky,, Ele Elect ctro roni nic c Dev Devic ices es and and Circuit Theory, Pearson Education, Inc., Uppersaddle River, New Jersey 07458, USA, 2006. 2.

Paul Paul R. Gray Gray,, Paul Paul J. Hurs Hurst, t, Step Stephe hen n H. H. Lew Lewis is,, and and Rob Rober ertt G. G. Mey Meyer er,, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc., Singapore, 2003.

ELECTRONIC CIRCUIT •

CHAPTER 1.

Semiconductor Diodes

•

CHAPTER 2. 2.

Diode Ap Applications

CHAPTER 3. CHAPTER 4.

Bipolar Junction Transistors DC Biasing - BJTs

•

CHAPTER 5. CHAPTER 6. CHAPTER 7.

BJT AC Analysis Field-Effect Transistors FET Biasing

•

CHAPTER 8.

FET Amplifier

•

CHAPTER 9.

BJT and JFET Frequency Response

CHA CHAPTER TER 10 10.. CHA CHAPTER TER 11 11..

Operat eratiional onal Am Amp plif lifier ier Op-Amp -Amp Applic plicat atio ions ns

•

•

•

•

•

•

ELECTRONIC CIRCUIT •

CHAPTER 1.

Semiconductor Diodes

•

CHAPTER 2. 2.

Diode Ap Applications

CHAPTER 3. CHAPTER 4.

Bipolar Junctio Junction n Transistors DC Biasing - BJTs

•

CHAPTER 5. CHAPTER 6. CHAPTER 7.

BJT AC Analysis Field-Effect Field-Ef fect Transistors FET Biasing

•

CHAPTER 8.

FET Amplifier

•

CHAPTER 9.

BJT and JF JFET Frequency Re Response

CHAPTE CHA TER R 10. 10. CHA CH APTE TER R 11 11..

Oper erat atio iona nall Am Amp pli lifi fier er Op-A -Amp mp Ap App pli lica cati tion onss

•

•

•

•

•

•

ELECTRONIC CIRCUIT CHAPTER 7. FET Biasing

1)

Introduction

404

2)

Fixed-Bias Configuration

405

3)

Self-Bias Configuration

409

4)

Voltage-Divider Biasing

415

5)

Depletion-Type MOSFETs

420

6)

Enhancement-Type MOSFETs

425

7)

Summary Table

430

8)

Combination Networks

430

9)

Design

434

10)

Troubleshooting

436

11)

p-Channel FETs

437

12)

Universal JFET Bias Curve

439

13)

Practical Applications

442

14)

Summary

453

15)

Computer Analysis

454

ELECTRONIC CIRCUIT CHAPTER 6. FIELD-EFFECT TRANSISTORS SUMMARY TABLE



ELECTRONIC CIRCUIT CHAPTER 6. FIELD-EFFECT TRANSISTORS SUMMARY

For the FET, the relationship between input and output quantities is NONLINEAR due to the squared term in Shockley’s Equation.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.1. Introduction

Linear relationships result in straight lines when plotted on a graph of one variable versus the other, whereas nonlinear functions result in curves as obtained for the transfer characteristics of a JFET. The nonlinear relationship between I D vs V GS can complicate the mathematical approach to the dc analysis of FET configurations. THE INPUT CONTROLLING VARIABLE FOR A BJT TRANSISTOR IS A CURRENT LEVEL, WHEREAS FOR THE FET A VOLTAGE IS THE CONTROLLING VARIABLE. The general relationships that can be applied to the dc analysis of all FET amplifiers are

For JFETs and depletion-type MOSFETs and MESFETs, Shockley’s equation is applied to relate the input and output quantities:

For enhancement-type MOSFETs and MESFETs, the following equations is applicable:

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.2. FIXED-BIAS CONFIGURATION

The simplest of biasing arrangements for the n-channel JFET appears in FIG. 7.1. Referred to as the fixedbias configuration, it is one of the few FET configurations that can be solved just as directly using either a mathematical or a graphical approach. The configuration of FIG. 7.1 includes the ac levels V i and V o and the coupling capacitors (C 1 and C 2 ).

Recall the coupling capacitors are OPEN CIRCUIT for the dc analysis and low impedances (essentially short circuits) f or the ac analysis. The resistor R G is present to ensure that V i appears at the input to the FET amplifier for the ac amplifier. For the dc analysis,


The zero-drop across R G permits replacing R G by a shortcircuit equivalent,as appearing in the network of FIG. 7.2, specifically redrawn for the dc analysis.

The fact that the negative terminal of the battery is connected directly to the defined positive potential of V GS clearly reveals that the polarity of V GS is directly opposite to that of V GG.


Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop of FIG. 7.2 results in

Since V GG is a fixed dc supply, the voltage V GS is fixed in magnitude, resulting in the designation FIXED-BIAS CONFIGURATION. The resulting level of drain current I D is now controlled by Shockley’s equation:

Since V GS is a fixed quantity for this configuration, its magnitude and sign can simply be substituted into Shockley’s equation and the resulting level of I D calculated.

(See FIG. 7.3) Recall that choosing V GS = V P /2 will result in a drain current of I DSS/4 when plotting the equation. For the analysis of this chapter, the three points defined by I DSS, V P , and the intersection just described will be sufficient for plotting the curve.


In FIG. 7.4, the fixed level of V GS has been superimposed as a vertical line at V GS = -V GG. At any point on the vertical line, the level of V GS is –V GG – the level of I D must simply be determined on this vertical line.

The point where the two curves intersect is the common solution to the configuration – commonly referred to as the quiescent or operating point.


It is important to realize that once the network of FIG. 7.1 is constructed and operating, the dc levels of I D and V GS that will be measured by the meters of FIG. 7.5 are the quiescent values defined by FIG. 7.4. The drain-to-source voltage of the output section can be determined by applying Kirchhof’s voltage law as follows:



The self-bias configuration eliminates the need for two dc supplies. The controlling gate-to-source voltage is now determined by the voltage across a resistor R S introduced in the source leg of the configuration a shown in FIG. 7.8.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.3. SELF-BIAS CONFIGURATION

For the dc analysis, the capacitor can again be replaced by OPEN CIRCUIT and the resistor R G replaced by a short-circuit equivalent since I G = 0 A. The current through R S is the source current I SS = I D and

For the indicated closed loop of FIG.7.9, we f ind that

In this case that V GS is a function of the output current I D and not fixed in magnitude as occurred for the fixed-bias configuration.

A mathematical solution could be obtained simply by substituting Eq. (7.10) into Shockley’s equation as follows


Let us now identify two points on the graph that are on the line and simply draw a straight line between the two points. The most obvious condition to apply is I D = 0 A since it results in V GS = -I DR S = (0 A)R S = 0 V.

For Eq. (7.10), therefore, one point on the straight line is defined by I D = 0 A and V GS = 0 V, as appearing on FIG 7.10. The second point for Eq. (7.10) requires t hat a level of V GS or I D be chosen and the corresponding level of the ot her quantity be determined suing Eq. (7.10). Suppose, for example, that we choose a level of I D equal to one-half the saturation level. That is,

(See FIG. 7.11) The straight line as defined by Eq. (7.10) is then drawn and the quiescent point obtained at the intersection of the straight-line plot and the device characteristic curve. The level of V DS can be determined by applying Kirchhoff’s voltage law to the output circuit, with the result that


KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI

25/89


The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to FET amplifiers as demonstrated by FIG. 7.21. The network of FIG. 7.21 is redrawn as shown in FIG. 7.22 for DC analysis. All the capacitors, including the bypass capacitor C S, has been replaced by an OPEN CIRCUIT equivalent. The source V DD was separated into two equivalent sources to permit a further separation of the input and output regions of the network.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.4. VOLTAGE-DIVIDER CONFIGURATION Since IG = 0 A, Kirchhoff’s current low requires that I R1 = I R2 , and the series equivalent circuit appearing to the left of the figure can be used to find the level of V G.

Applying Kirchhogg’s voltage law in clockwise direction to indicate loop of FIG. 7.22 result in

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.4. VOLTAGE-DIVIDER CONFIGURATION

Substituting





ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.5. DEPLETION-TYPE MOSFETs

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.5. DEPLETION-TYPE MOSFETs

For the n-channel enhancement-type MOSFET, the drain current is ZERO for levels of gate-to-source voltage less than the threshold level V GS(Th), as shown in FIG. 7.36. For levels V GS greater than V GS(Th), the drain current is defined by

Since specification sheets typically provide the threshold voltage and a level of drain current (I D(on)) and its corresponding level of V GS(on), two points are defined immediately as shown in FIG. 7.36.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.6. ENHANCEMENT-TYPE MOSFETs

Feedback Biasing Arrangement Arrangement A popular popular biasing arrangement arrangement for enhancement-type MOSFETs is provided in FIG. 7.37. The resistor R G brings a suitably large voltage to the gate to drive the MOSFET ‘ON’. Since I G = 0 mA and V RG = 0 V, the DC equivalent network appears as shown in FIG. 7.38.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.6. ENHANCEMENT-TYPE MOSFETs For the output circuit,

Feedback Biasing Arrangement Arrangement (cont’d) Since Eq. (7.28) is that of a straight line, the same procedure described earlier earlier can be employed employed to determine the two points that will define the plot on the graph ( I D = 0 mA an V GS = 0 V)




Voltage-Divider Biasing Arrangement A second popular biasing arrangement for the enhancementtype MOSFET appears in FIG. 7.43. The fact that I G = 0 mA results in the following equation for V GG as derived from an application of the voltage-divider rule:

Applying Kirchhoff’s voltage law around the indicated loop of FIG. 7.43 results in

For output section





ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.7. SUMMARY TABLE

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.8. COMBINATION NETWORK





The design process is not limited solely to DC applications. The area of application, level of amplification desired, signal strength, and operating conditions are just a few of the conditions that enter into the total design process. For example, if the levels of V D and I D are specified for the network of FIG. 7.50, the level of V GSQ can be determined from a plot of the transfer curve and R S can then be calculated from

If V DD is specified, the level of R D can then be calculated from

The values of R S and R D may not be standard commercial values, requiring that the nearest commercial values be employed. However, with the tolerance (range of values) normally specified for the parameters of a network, with slight variation due to the choice of standard values will seldom cause a real concern in the design process. In general, it is good design practice for linear amplifier to choose operating points that do not crowd the saturation level (I DSS) or cutoff (V P ) region. Level of V GSQ close to V P /2 or level of I DQ near I DSS/2 are certainly reasonable starting points in the design.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.9. DESIGN




For the n-channel JFET amplifier, it is clearly underst ood that the quiescent value of V GSQ is limited to 0 V or a negative voltage.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.10. TROUBLESHOOTING

For the network of FIG. 7.55, V GSQ is limited to negative values in the range 0 V to V P . If a meter is hookep up as shown in FIG. 7.55, with the positive lead (normally red) to t he gate and the negative lead (usually black) to the source, the resulting reading should have a negative sign in a magnitude of a few volt. The level of V DS is typically between 25% to 75% of V DD. A reading of 0 V for V DS clearly indicates that either the output circuit has an OPEN or the JFET is internally short-circuited between drain and source. IfV D is V DD volts, there is obviously no drop across R D, due to the lack of the current through R D, and the connections should be checked for continuity. If the level of V DS seems inappropriate, the continuity of the output circuit can easily be checked by grounding the negative lead of the voltmeter and measuring the voltage levels from V DD to ground using the positive lead. If V S = V DD, the device is not open between drain and source, but it is also not ON. In this case, it is possible that there is a poor ground that may not be obvious. The internal connection between the wire of the lead and the terminal connector may have separated. Other possibilities also exist, such as shorted device from drain t o source. The continuity of a network can also be checked simply by measuring the voltage across any resistor of the network (except R G in the JFET configuration). An indication of 0 V immediately reveals the lack of current through the element due to an open circuit in the network.

For p-channel FETs, a mirror image of the transfer curves is employed, and the defined current directions are reversed as shown in FIG. 7.56 for the various types of FETs.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.11. p-CHANNEL FETs

KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI

73/89

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.11. p-CHANNEL FETs

Since the DC solution of a FET configuration requires drawing the transfer curve for each analysis, a universal curve was developed that can be used for any level of I DSS and V P . The unversal curve for an n-channel JFET or depletion-type MOSFET (for negative values of VGSQ) is provided in FIG. 7.59. Note that the horizontal axis is not that of V GS but of a normalized level defined by V GS/|V P |, the |VP| indicating that only the magnitude of V P is to be employed, not its sign. For the vertical axis, the scale is also normalized level of I D/I DSS. The additional two scales are m and M . The vertical scale labeled m can in itself be used to find the solution to fixed-bias configurations. The other scale, labeled M, is employed along with the m scale to find the solution to voltage-divider configurations.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.12. UNIVERSAL JFET BIAS CURVE





Voltage-Controlled Resistor (Noninverting Amplifier) One of the most common applications of the JFET is as a variable resistor whose resistance value is controlled by the applied DC voltage at the gate terminal.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.13. PRACTICAL APPLICATIONS

The plot of a fixed resistor is nothing more than a straight line with its origin at the intersection of the axes. For an I-V plot where the current is the vertical axis and the voltage the horizontal axis, the steeper the slope, the less is the resistance; and the more horizontal the curve, the greater the resistance. The linear region of a JFET is defined by V DS « V DSmax and |V GS | «|V P |.

The drain-to-source resistance increases as the gate-to-source voltage approaches the pinch-off value.

ELECTRONIC CIRCUIT CHAPTER 7. FET BIASING 7.13. PRACTICAL APPLICATIONS

Rangkaian Elektronika - Chapter 07 2013

Recommend Documents