VLSI DESIGN BOOK for final year Engg studentsFull description
Full description
syllabus for ME vlsi
VLSI interview questiuons
VLSI Interview Questions and Answers, VLSI FAQs
VLSI interview questiuons
VLSI Interview questions
short doc on vlsi questions. Good for a last minute review. Not my work..Full description
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VLSI Design
Vlsi design flow
What are the steps required to solve setup and Hold violations in VLSI? There are few steps that has to be performed to solved the setup and hold violations in VLSI. The steps are as follows: the optimization and restruturin! of the lo!i between the flops are arried wa". This wa" the lo!is are ombined and it helps in solvin! this problem. There is wa" to modif" the flip#flops that offer lesser setup dela" and provide faster servies to setup a devie. $odif"in! the launh#flop to have a better hold on the lo% pin& whih provides '(#)* that ma%es the launh#flop to be fast and helps in fi+in! the setup violations. The networ% of the lo% an be modified to redue the dela" or slowin! down of the lo% that aptures the ation of the flip#flop. There an be added dela",buffer that allows less dela" to the funtion that is used. What are the different wa"s in whih antenna violation an be prevented? -ntenna violation ours durin! the proess of plasma ethin! in whih the har!es !eneratin! from one metal strip to another !ets aumlated at a sin!le plae. The lon!er the strip the more the har!es !ets aumulated. The prevention an be done b" followin! method: 'reatin! a o!!in! the metal line& that onsists of atleas one metal above the proteted la"er. There is a requirement to o! the metal that is above the metal !ettin! the ethin! effet. This is due to the fat that if a metal !ets the ethin! then the other metal !ets disonneted if the prevention measures are not ta%en. There is a wa" to prevent it b" addin! the reverse /iodes at the !ates that are used in the iruits. What is the funiton of tie#hi!h and tie#low ells? Tie#hi!h and tie#low are used to onnet the transistors of the !ate b" usin! either the power or the !round. The !ates are onneted usin! the power or !round then it an be turned off and on due to the power boune from the !round. The ells are used to stop the bounin! and eas" from of the urrent from one ell to another. These ells are required Vdd that onnets to the tie#hi!h ell as there is a power suppl" that is hi!h and tie# low !ets onneted to Vss. This onnetion !ets established and the
transistors funtion properl" without the need of an" !round boune ourin! in an" ell. What is the main funtion of metastabilit" in VS/L? $etastabilit" is an un%nown state that is !iven as neither one or zero. It is used in desi!nin! the s"stem that violates the setup or hole time requirements. The setup time requirement need the data to be stable before the lo%#ed!e and the hold time requires the data to be stable after the lo% ed!e has passed. There are potential violation that an lead to setup and hold violations as well. The data that is produed in this is totall" as"nhronous and lo%ed s"nhronous. This provide a wa" to setup the state throu!h whih it an be %nown that the violations that are ourin! in the s"stem and a proper desi!n an be provided b" the use of several other funtions. What are the steps involved in preventin! the metastabilit"? $etastabilit" is the un%nown state and it prevents the violations usin! the followin! steps: proper s"nhronizers are used that an be two sta!e or three sta!e whenever the data omes from the as"nhronous domain. This helps in reoverin! the metastable state event. The s"nhronizers are used in between ross#lo%in! domains. This redues the metastabilit" b" removin! the dela" that is aused b" the data element that are omin! and ta%in! time to !et removed from the surfae of metal. 0se of faster flip#flops that allow the transation to be more faster and it removes the dela" time between the one omponent to another omponent. It uses a narrower metastable window that ma%es the dela" happen but faster flip#flops help in ma%in! the proess faster and redue the time dela" as well. What are the different de!ins onstraints our in the S"nthesis phase? The steps that are involved in whih the desi!n onstraint ours are: first the reation of the lo% with the frequen" and the dut" "le !ets reated. This lo% helps in maintainin! the flow and s"nhronizin! various devies that are used. /efine the transition time aordin! the requirement on the input ports. The load values are speified for the output ports that are mapped with the input ports.
Settin! of the dela" values for both the input and output ports. The dela" inludes the input and output dela". Speif" the ase#settin!s to report the orret time that are mathed with the speifi paths. The lo% unertainit" values are setup and hold to show the violations that are ourin!. What are the different t"pes of s%ews used in VLSI? There are three t"pes of s%ew that are used in VLSI. The s%ew are used in lo% to redue the dela" or to understand the proess aordin!l". The s%ew are as follows: Loal s%ew: this ontain the differene between the launhin! flip#flop and the destination flip#flop. This defines a time path between the two. 1lobal s%ew: defines the differene between the earliest omponent reahin! the flip flow and the the latest arrivin! at the flip flow with the same lo% domain. In this dela"s are not measured and the lo% is provided the same. 0seful s%ew: defines the dela" in apturin! a flip flop paths that helps in settin! up the environment with speifi requirement for the launh and apture of the timin! path. The hold requirement in this ase has to be met for the desi!n purpose. What are the han!es that are provided to meet desi!n power tar!ets? To meet the desi!n power tar!et there should be a proess to desi!n with $ulti#V// desi!ns& this area requires hi!h performane& and also the hi!h V// that requires low#performane. This is used to reate the volta!e !roup that allow the appropriate level#shifter to shift and plaed in ross# volta!e domains. There is a desi!n with the multiple threshold volta!es that require hi!h perfomane when the Vt beomes low. This have lots of urrent lea%a!e that ma%es the Vt ell to lower the performane. The redution an be performed in the lea%a!e power as the lo% in this onsume more power& so plain! of an optimal lo% ontrols the module and allow it to be !iven more power. 'lo% tree allow the swithin! to ta%e plae when the lo% buffers are used b" the lo% !atin! ells and redue the swithin! b" the power redution. What are the different measures that are required to ahieve the desi!n for better "ield?
To ahieve better "eild then there should be redution in maufaturabilit" flaws. The iruit perfomane has to be hi!h that redues the parametri "ield. This redution is due to proess variations The measures that an be ta%en are: 'reation of powerful runset files that onsists of spain! and shortin! rules. This also onsists of all the permissions that has to be !iven to the user. 'he% the areas where the desi!n is havin! litho!raphi issues& that onsists of sharp uts. 0se of redundant vias to redue the brea%a!e of the urrent and the barrier. 2ptimal plain! of the de#ouplin! apaitanes an be done so that there is a redution in power#sur!es. What is the differene between the meal" and moore state mahine? $oore model onsists of the mahine that have an entr" ation and the output depends onl" on the state of the mahine& whereas meal" model onl" uses Input -tions and the output depends on the state and also on the previous inputs that are provided durin! the pro!ram. $oore models are used to desi!n the hardware s"stems& whereas both hardware and software s"stems an be desi!ned usin! the meal" model. $eal" mahine3s output depend on the state and input& whereas the output of the moore mahine depends onl" on the state as the pro!ram is written in the state onl". $eal" mahine is havin! the output b" the ombination of both input and the state and the han!e the state of state variables also have some dela" when the han!e in the si!nal ta%es plae& whereas in $oore mahine doesn3t have !lithes and its ouput is dependent onl" on states not on the input si!nal level. What is the differene between S"nhronous and -s"nhronous reset.? S"nhronous reset is the lo!i that will s"nthesize to smaller flip#flops. In this the lo% wor%s as a filter providin! the small reset !lithes but the !lithes our on the ative lo% ed!e& whereas the as"nhronous reset is also %nown as reset release or reset removal. The desi!ner is responsible of added the reset to the data paths. The s"nhronous reset is used for all the t"pes of desi!n that are used to filter the lo!i !lithes provided between the lo%s. Whereas& the iruit an be reset with or without the lo% present.
S"nhronous reset doesn3t allow the s"nthesis tool to be used easil" and it distin!uishes the reset si!nal from other data si!nal. The release of the reset an our onl" when the lo% is havin! its initial period. If the release happens near the lo% ed!e then the flip#flops an be metastable. What are the different desi!n tehniques required to reate a La"out for /i!ital 'iruits? The different desi!n tehniques to reate the La"out for di!ital iruits are as follows: /i!ital desi!n onsists of the standard ells and represent the hei!ht that is required for the la"out. The la"out depends on the size of the transistor. It also onsists of the speifiation for Vdd and 14/ metal paths that has to be maintained uniforml". 0se of metal in one direton onl" to appl" the metal diretl". The metal an be used and displa"ed in an" diretion. 5lain! of the substrate that plae where it shows all the empt" spaes of the la"out where there is resistanes. 0se of fin!ered transistors allows the desi!n to be more eas" and it is eas" to maintain a s"mmetr" as well. Write a pro!ram to e+plain the omparator? To ma%e a omparator there is a requirement to use multiple+er that is havin! one input and man" outputs. This allows the hoosin! of the ma+imum numbers that are required to desi!n the omparator. The implementation of the 6 bit omparator an be done usin! the law of ti!otom" that states that - ) 7& - 8 7& - 9 7 Law of tri!otom";. The omparator an be implemented usin!: ombinational lo!i iruits or multiple+ers that uses the H/L lan!ua!e to write the shemati at &"6&"&a&b;@ input A>:=B a&b@ output ">&"6&"@ wire ">&"6&"@ assi!n ">9 a )b;? >:=@ assi!n "69 b )a;? >:=@ assi!n "9 a99b;? >:=@ endmodule
What is the funtion of hain reorderin!? The optimization tehnique that is used ma%es it diffiult for the hain orderin! s"stem to route due to the on!estion aused b" the plaement of the ells. There are tool available that automate the reorderin! of the hain to redue the on!estion that is produed at the first sta!e. It inreases the problem of the hain s"stem and this also allow the overomin! of the buffers that have to be inserted into the san path. The inrease of the hold time in the hain reorderin! an ause !reat amount of dela". 'hain reorderin! allows the ell to be ome in the ordered format while usin! the different lo% domains. It is used to redue the time dela" aused b" random !eneartion of the elment and the plaement of it. What are the steps involved in desi!nin! an optimal pad rin!? To ma%e the desi!n for an optimal pad rin! there is a requirement for th orner#pads that omes aross all the orners of the pad#rin!. It is used to !ive power ontinuit" and %eep the resistane low. It requires the pad rin! that is to fullfill the power domains that is ommon for all the !round aross all the domains. It requires the pad rin! to ontain simultaneous swithin! noise s"stem that plae the transfer ell pads in ross power domains for different pad len!th. /rive stren!th is been seen to he% the urrent requirements and the timin!s to ma%e the power pads. 'hoose a no#onnetion pad that is used to fill the pad#frame when there is no requirement for the inputs to be !iven. This onsumes less power when there is no input !iven at a partiular time. 'he%in! of the osillators pads ta%e plae that uses the s"nhronous iruit
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What is the funtion of enhanement mode transistor? The enhanement mode transistors are also alled as field effet transistors as the" rel" on the eletri filed to ontrol the shape and ondutivit" of the hannel. This onsists of one t"pe of har!e arrier in a semiondutor material environment. This also uses the unipolar transistors to differentiate themselves with the sin!le#arrier t"pe operation transistors that onsists of the bipolar untion transistor. The uses of field effet transistor is to ph"sial implmementation of the semiondutor materials that is ompared with the bipolar transistors. It provides with the maorit" of the har!e arrier devies. The devies that onsists of ative hannels to ma%e the har!e arriers pass throu!h. It onsists of the onept of drain and the soure. What is the purpose of havin! /epletion mode /evie? /epletion modes are used in $2SCDT it is a devie that remains 24 at zero !ate#soure volta!e. This devie onsists of load resistors that are used in the lo!i iruits. This t"pes are used in 4#t"pe depletion#load devies that allow the threshold volta!es to be ta%en and use of # V to EV is done. The drain is more positive in this omparison of 5$2S where the
polarities !ets reversed. The mode is usuall" determined b" the si!n of threshold volta!e for 4#t"pe hannel. /epletion mode is the positive one and used in man" tehnolo!ies to represent the atual lo!i iruit. It defines the lo!i famil" that is dependent on the silion VLSI. This onsists of pull#down swithes and loads for pull#ups. What is the differene between 4$2S and 5$2S tehnolo!ies? 5$2S onsists of metal o+ide semiondutor that is made on the n#t"pe substrates and onsists of ative areers named as holes. These holes are used for mi!ration purpose of the har!es between the p#t"pe and the drain. Whereas& 4$2S onsists of the metal o+ide semiondutor and the" are made on p#t"pe substrates. It onsists of eletrons as their arriers and mi!ration happens between the n#t"pe soure and drain. 2n appl"in! the hi!h volta!e on the lo!i !ates 4$2S will be onduted and will !et ativated& whereas 5$2S require low volta!e to be ativated. 4$2S are faster than 5$2S as the arriers that 4$2S uses are eletrons that travels faster than holes. The speed is twie as fast as holes. 5$2S are more immune to noie than 4$2S. What is the differene between '$2S and 7ipolar tehnolo!ies? '$2S tehnolo!" allows the power dissipation to be low and it !ives more power output& whereas bipolar ta%es lots of power to run the s"stem and the iriutar" require lots of power to !et ativated. '$2S tehnolo!" provides hi!h input impedane that is low drive urrent that allow more urrent to be flown in the iruit and %eep the iruit in a !ood position& whereas it provides hi!h drive urrent means more input impedane. '$2S tehnolo!" provides salable threshold volta!e more in omparison to the 7ipolar tehnolo!" that provides low threshold volta!e. '$2S tehnolo!" provides hi!h noise mar!in& pa%in! densit" whereas 7ipolor" tehnolo!" allows to have low noise mar!in so that to redue the hi!h volues and !ive low pa%in! densit" of the omponents. What are the different lassifiation of the timin! ontrol? There are different lassifiation in whih the timin! ontrol data is divided and the" are: /ela" based timin! ontrol: this is based on timin! ontrol that allows to mana!e the omponent suh that the dela" an be notified and wherever it is required it an be !iven. The dela"s that are based on this are as:
level that is bein! !iven or shown and the data is bein! modified aordin! the levels that are bein! set. When a level han!es the timin! ontrol also han!es.