6645530 Allen and Holberg Homework Solution(2)

ECE 6412 - Spring 2006

Prof. Ayazi

EXAMINATION NO. 2 SOLUTIONS Problem 1 - (35 points)

The op amps below have identical DC currents and W/L values for transistors with the same number. Find parametric expressions for entries in the table in terms of bias currents I 5 and I7, Kn’, Kp’, λN, λP, VTN, |VTP|, S=W/L ratios, VDD, V SS, Cc, CL, and identify which is larger in magnitude for the two circuits. Assume K’ n>K’p, VTN= -VTP, λN<λP, (W/L) 1= (W/L)2, VDD=VSS. The threshold voltage is larger than the ON (saturation) voltage. Ignore body effect. USE THE LAST SHEET TO DO YOUR WORK AND THEN WRITE YOUR FINAL ANSWER/EXPRESSION IN THE TABLE. NO PARTIAL CREDIT.

N-channel Input Op Amp

P-channel Input Op Amp

Characteristic

N-channel Input Op Amp

<,=,>

P-channel Input Op Amp

Small-signal output resistance

( I 7 (λ6 + λ 7 ))−1

=

( I 7 (λ6 + λ 7 ))−1

Small-signal voltage gain

8K N′ K P′ S1S6

=

8 K N′ K P′ S1S6

I 5 I 7 (λ2 + λ4 )(λ6 + λ7 )

Gainbandwidth Upper input common mode voltage

I 5 I 7 (λ2 + λ4 )(λ6 + λ7 )

>

′ S1I 5 K N

K P′ S1I 5

C c V

DD−

V

TP+

V TN−

C c

>

I 5 K P′ S3

Slew rate(due to Cc)

I 5

Positive (VDD) PSRR

no expression needed

=

C c

V

DD−

V TP−

2 I 5 K P′ S5

−

I 5 K P′ S1

I 5 C c

<

1


Negative (VSS) PSRR Phase Margin


90

o

− tan

−1

(

K N′ S1I 5 C L

2 K P′ S 6 I 7 C C

−

) − tan 1 (

> ′ S1 I 5 K N ) 2K P′ S 6 I 7

(EXTRA CREDIT)

2

<


90

o

− tan

−1

(

K P′ S1I 5 C L

2 K N′ S 6 I 7 C C

) − tan −1 (

K P′ S1I 5 ) ′ S6I 7 2K N

Problem 2 - (35 points)

The device parameters for the operational amplifier shown below are given in the table. Ignore the body effect of the MOS transistor and the internal capacitances of all the transistors. a. What resistance R in the emitter of Q9 is required to set the first stage bias currents in the emitters of Q3 and Q4 at 10µA each? b. Calculate the overall voltage gain of the amplifier, by calculating the effective nd transconductances of the differential input stage and the 2 gain stage, and their effective output resistances. c. Calculate the value of the miller capacitance Cc required to obtain a gain-bandwidth of 2MHz for this op-amp. d. Calculate the phase margin of this op-amp.

Parameter

NPN 200 130V 0.7V

Beta Early voltage VBE(on) Vt

PNP 50 50V 0.7V

25mV MOS 0.01V-1 100µA/V2 0.7V

lambda µCox VTO

a) RI C9=V t ln(I C8 /I C9)

0.372mA I C8=(20V-1.4V)/50k Ω= I C9=20µ A  R=3.65k Ω

b) GmI R

g m1

=

1 + g m1re3

I= r07

=

AvI

R3 IC13

=

GmI

RI

=II =

=

r 2e) = r07 || 2 r04 Anpn

A

note that : re3 =

V

=

1 + g mm1 R2

and

=

r04

(1

1dsm +

×

V I C 4

=

g m3

1 g m1

=

Apnp

5M Ω

g

0.663 × 10−3

× 1mm

A V

R2 ) || r013 (1 + g

A

note that : gmm1 = 2µ Cox ( × 13 m

AvII

≅

W )mm1 I mm 1 L

561,610

3

−3

= 1.414 × 10

R3 ) = 2.13 MΩ ||1.16 MΩ = 0.749 MΩ

GmII RII = 497 AvI

1

= 5.65 M Ω

⇒ IC 13 = 100 µ

)

g mm1

r

200 × 10−6

= 1130

I C 13

AvII Av

×

=

= 13M Ω

I C 7 I C 10

R

4m×

V

= V t ln(

GmII =

g m1

2

|| r04 (1 + g

because : r07 

=

A V

c) GBW

=

GmI

⇒

CC =

200 ×10−6

2π × 2 × 10−6 2 MHz −1 2 MHz d) Φ M = 90o − tan−1 ( ) − tan ( ) p2 z 2

=

=

C C

GmII C L

GmII C C

⇒

=

=

0.663 ×10 p − 5 ×10 12

−3

0.663 ×10−3 z 15.9 ×10−12

Φ M = 90 − tan o

−1

(

= 132 × 10

=

2 21

rad = 21.1 sec

6

MHz

rad = 6.64 sec

41.69 × 106 ) − tan −1 (

= 15.9 pF

2 6.64

) = 90

4

o

MHz

− 5.41 − 16.76 = o

o

67.82

o


In this problem, you are not asked to provide any numerical calculations. You are only required to provide expressions . Make sure that your final expression for each section is clearly identified and legible. For the cascoded two-stage CMOS Op-Amp shown below: VDD

4 M3

M6

M4

3

1 CC

VBP

VOUT

2

M2

M1

M7

V−

V+

CL VBN

M8

M5 VBIAS

M9

VSS

a. Show an expression for the overall voltage gain of this amplifier as a function of transistor transconductances and output resistances.

Av

=

gm1 ( rds 4 || rds 2 ) × gm 6 [( gm 7 rds 6 rds 7 ) || ( g m8rds 8rds 9 )] 14444244443 R II

b. Show the expressions for the poles associated with the two capacitors C C and CL, as a function of the two capacitance values, transistor transconductances and output resistances. Assume that C C and CL include the transistor internal capacitances at their respective nodes. 1

=p

1

( rds 4 || rds 2 )Cc

and

2

=p

1

RII CL

c. If CL>>CC, provide an expression for the unity gain frequency (GB) of the amplifier.

GBW =

g m1 gm 6 (rds 4 || rds 2 ) C L

5

d. Show an expression for the pole associated with node 3, in terms of transistors internal capacitances, transconductances and output resistances. Identify all the components of the internal capacitances.

1

p3

=

C3

= Cgs7 + Csb 7 + Cgd 6 + Cdb 6

R3

=

( rds 6 || R3 )C 3 rds 7 + gm8 rds 8rds 9

1 + gm 7 rds 7

1

≅

+

gm 8rds 8rds 9

gm 7

gm 7 rds 7

e. Is there a right half plane zero in this amplifier that would affect the phase margin? If there is, provide an expression for the position of this zero.

No, because a miller configuration is not used  there is no RHZ that would affect the phase margin

f.

(EXTRA CREDIT) Show expressions for any pole or zero associated with node 4. Identify all the components of the internal capacitances.

− g m3

p4

=

C

x=

C

z4

=

−2 g m 3

C x gs 3+

C

gs 4+

C

db 3 +

C

db 1+

C gd1

C x

6

ECE 6412- Spring 200 6

Page 1 Homework No. 1 - Solutions


n+

A top view of a MOS transistor is shown. (a) Identify the type of transistor (NMOS or PMOS) and its value of W and L. (b.) Draw the cross-section approximately to scale.

A-A’

p+ A

A' Metal

(c) Assume that dc voltage of terminal 1 is 5V, terminal 2 is 3V and terminal 3 is 0V. Find the numerical value of the capacitance between terminals 1 and 2, 2 and 3, and 1 and and 3. Assume that the dc value of the output voltage is 2.5V and that the voltage dependence for pn junction capacitances is for both transistors is -0.5 (this is called MJ in SPICE).

Poly

p-well 3

(b.) The approximate approximate cross-section is shown (vertical scale is magnified by 4 times).

IOX

IOX IOX

F O X

F O X

p+

(c.)With V DS = 5V, V GS = 3V and V T = 0.75V, the transistor is in saturation. Therefore, the capacitors are:

n+

n+

p-well

1µm

2

S00PES1

C 12 = C GD = LD(NMOS)xW xC ox

= 0.45µm·26 0.45µm·26µm·0.7fF/µm2 µm·0.7fF/µm2 =

1 n-substrate

Solution

(a.) This transistor is an NMOS transistor with the drain as terminal 1, the gate as terminal 2, and the bulk and source connected together to terminal 3. The W = 26µm and L = 4µm .

2

8.19fF

C 23 = C GS = LD(NMOS)xW xC ox + 0.67(W x L)X C ox = 8.19fF + 48.776fF 48.776fF

= 56.966fF 56.966fF C 13 requires the area of the drain (AD) and the perimeter perimeter of the drain (PD). These values

are AD = 26µmx10µm = 260µm2 and PD = 2(10+26) = 72µm. 2 2 2 µ m +PD·0.9fF/µm] [260µm ·0.33fF/ µ µ m +72µm·0.9fF/µm] [AD·0.33fF/ µ C 13 = CBD = = 5 5 1 + 0.6 1 + 0. 6 0.6 0. 6

=

49.29fF


Page 2

Problem 2 - (10 points) +2.5V

Find the numerical values of I 1, I 2,V D , V E , and V C to within ±5% accuracy.

100µm 1µm M2 V C C Q1 I 2

Solution

First find I 1 . This is done by solving the the equations equations I 1 = K ’ W 2 2 L (V GS 4-V T )

V E

and 5V = I 1100k Ω + V GS4

50µm 1µm

Solving quadratically gives 1  5  V GS 42 - V GS 4 2 V T - 12 + V T 2 - 12 = 0    

M3 M4

S00PEP1

100k Ω I 1 V D

10µm 1µm

-2.5V

V GS2 - 1.41667V GS + 0.145833 = 0

This gives V GS = 0.708335 ± 0.5965 = 1.305V This value of V GS gives I 1 =

5-1.195 100k Ω

∴ V D = -2.5+1.305 = -1.195V

= 36.95µA

Neglecting the lambda effects, let I 2 = 5 I 1 = 184.75µA The base-emitter voltage of Q1 is found as

 I 2 184.75µA = -0.614V V -V V   = = ln = -0.026ln E BE 1 T I s  10fA    Finally, the value of V GS2 =

2 I 2 K ’W 2 / L 2 + V T =

∴ V C = 2.5V - 1.43V = +1.070V

2x184. 7 5 800 + 0.75 = 1.43V


Page 3

Problem 3 Find the numerical values of all roots and the midband gain of the transfer function vout / vin of the differential amplifier shown. Assume that K N ’ =

V DD R L= 10k Ω C L =1pF

100µA/V2, V TN = 0.7V, and λ N = 0.04V-1. The values of C gs = 0.2pF and C gd = 20fF.

C L =1pF

- vout +

M2

M1

Solution

R L= 10k Ω

100/1 100/1

A small-signal model appropriate for this circuit is vin shown. vin 2

C gs gs

C gd gd gm1vgs1

r ds ds1

R L

C L

1mA

+ vout 2 -

S03E1P4

Fig. S03E1S4

Summing the currents at the output nodes gives, gm1vgs1 + sC gd (vout -vin) + (gds1 + G L)vout + sC L vout = 0

(Note: we are ignoring the fact that vout and vin should be divided by two since it makes no difference in the results and is easier to write.) Replacing vgs1 by vin gives -(gm1 - sC gd )vin = [(gds1 + G L) + sC L + sC gd ] vout

 1 - s C g d  vout -( g m 1 - sC gd ) gm  - gm 1  = = v in s ( C L + C gd ) + ( g ds 1 + G L ) g ds 1 + G L   C L + C g d  1 + s g ds 1 + G L  ∴

gm MGB = - gm1(r ds|| R R L), Zero = C

gd

gm =

∴

2·100·100·500 = 3162.3µS and

and

g ds + G L Pole = - C + C gd L rds =

1 λ I D

25 = 500µA = 50 k Ω

MGB = -3.162mS·(10k Ω||50k Ω) = -26.35 V/V Zero = Pole =

3.162x10-3 20x10-15

= 1.581x1011 radians/sec.

-1 1.02x10-12(10k Ω||50k Ω)

= -1.1176x108 radians/sec.


Page 4

Problem 4 Find the voltage transfer function of the common-gate amplifier shown. Identify the numerical values of the small-signal voltage gain, vout / v in , and the poles and zeros. Assume that 2 I D =250µA, K N ’ = 100µA/V , V TN = 0.5, -1 λ ≈ 0V , C gs = 0.5pF and C gd = 0.1pF.

V DD R D = 10k Ω 20

Solution V Bias

The small signal transconductance is, gm =

2·K N ·(W/L) I D =

2·100·20·250 = 1mS vin

r ds = ∞

The small model is,

RS = 1k Ω

gmvgs

Rs

signal

S04E1P3

+

vin

vgs

C gs

C gd R L

+

vout

-

S04E1S3

The voltage gain can be expressed as follows, V out  V out   V gs  V in =  V gs   V in  ,

V out R L(1/ sC gd )   V gs = -gm  R L+(1/ sC gd )

Sum currents at the source to get, V in + V g s + gmV gs + sC gsV gs = 0 R s

∴

→

V gs -G s = V in G s + g m + s C g s

V out  g m R L  1 1    = V in 1+ g m R L  sC gd R L+1  sC gs  + 1  gm +G s 

The various values are, g m R L 1·10 Voltage gain = 1+ g R = 1+1 = 5V/V m L

-1 p1 = C R = gd L

-1 10-13·10

9 = -10 radians/sec. 4

-(gm+Gs) -10-3+10-3 p2 = = = -4x109 radians/sec. C gs -12 0.5x10

+

1 vout I D -


Page 5

Problem 5 Draw the electrical schematic using the proper symbols for the transistors. Identify on your schematic the terminals which are +5V, ground, input, and output. Label the transistors on the layout as M1, M2, etc. and determine their W/L values.

Assume each square in the

layout is 1 micron by 1 micron. Find the area in square microns and periphery in microns for the source and drain of each transistor.

n+

Metal

p+

p-well

Poly

Contact Ground

M1

M2

Output +5V Input

N-Substrate +5Volts D1 B1 G1 M1 Input

S1 S2 G2 M2

W1 = 10 L1

AS1 = AD1 = 40x8 = 320µm2 PS1 = PD1 = 8+8+40+40 = 48µm

Output B2

D2 Ground

W2 = 20 L2

AS2 = 2AS1 = 640 µm2 AD2 = AD1 = 320µm2 PS2 = 2PS1 =192µm PD2 = PD1 = 96µm S01PES1


Page 1

Homework Assignment No. 4 - Solutions

Problem 1 Find the midband voltage gain and the –3dB frequency in Hertz for the circuit shown. C 2=1pF R1=1k Ω R2= 10k Ω

C 1= 10pF

V in

+ V 1 -

V 1

100

R3= 20k Ω

C 3= 10pF

+ V out -

S02E1P3

Solution

The midband gain is given as, V out  20k Ω  10k Ω =  100  11k Ω = -181.82V/V V in

To find the –3dB frequency requires finding the 3 open-circuit time constants. RC 10: RC 10 = 1k Ω||10k Ω = 0.9091k Ω

→

RC 10C = 0.9091x10ns

=9.09ns

RC 20:

it vt = it RC 10 + R3(it +0.01V 1)

S02E1S3

= it ( RC 10 + R3 + 0.01 RC 10 R3)

+ v t

∴ RC 20 = RC 10 + R3 + 0.01 RC 10 R3

+ V 1 V 1 100

Rc10

=0.9091+ 20x (1+0.01·909.1)k Ω RC 20C 2 =

=

202.72k Ω

202.72x1ns

R3

=202.72ns

RC 30: RC 30 = 20k Ω

→

RC 30C 3 =

ΣT 0 = (9.091 + 202.72 + 200)ns=411.82n f -3dB =

2.43x106

2π

= 386.5kHz

20x10ns

→

=

200ns

-3dB =

ω

1

Σ T 0

= 2.43x106 rad/s


Page 2

Problem 2 – (10 points) Find the midband voltage gain and the exact value of the two poles of the voltage transfer function for the circuit shown. Assume that R I = 3k Ω, R L = 9KΩ, gm = 1mS, C gs = 4.5pF and C gd = 1pF. Ignore r ds. R I

+

V in

R L

V out

-

S02E1P4

Solution

The best approach to this problem is a direct analysis. Small-signal model: gmV gs

R I

V in

+

V gs +

C gs

gmV s

R I

C gd

R L V out

V in

+

+ V s

C gs

C gd

R L V out

-

-

S02E1S4

V out = gm Z LV s

where

1 = Z L sR LC gd +1

and

V in-V s R I

= gm V s +

sC gs V s

Solving for V s from the second equation gives, V in V s = 1+ g R +sC R m I gs I

Substituting V s in the first equation gives, V in V out 1 1 V out = gm Z L 1+ g R +sC R → V = gm sR C +1 1+ g R +sC R  m I gs I in  L gd   m I gs I  g m R L  1 1   = MBG 1   1  = 1+ g R  sR C +1  sC R  m I  L gd   gd I 1 - s  1 - s   + 1  p1  p2 1+ gm R I  g m R L 1x9 ∴ MBG = 1+ g R  = 1+1 x3 = 2.25V/V m I

1 1 p1 = - R C = - 9x 1ns L gd

= 1.1e8 rad/s

1+gm R I 1+3 and p2 =- R C = - 3x4.5 ns = -2.9x108 rad/s I gs


Page 1


Problem 1 - (10 points) For the CMOS op amp shown, find the following quantities. 1.) Slew rate (V/sec.)

V DD=2.5V

10/1

2.) Positive and negative output voltage limits (all transistors remain in saturation)

M8

M5

+ vin

M2

M1

-

3.) Positive and negative input common voltage limits (all transistors remain in saturation and use nominal parameter values)

60 /1

10/1

10/1

10/1

60 /1

10/1

10/1 V SS=-2.5V

4.) Small signal voltage gain

vout

M6

M4

M3 40µA

M7 C c=3pF

S99E2P4

5.) Unity-gainbandwidth (MHz) and 6.) Power dissipation (mW). Solution I 5 40µA 1.) SR = C = 3pF = 1.1x107V/second c

2.)

∴

V SD7 =

2 I 7 K P(W L) = /

⇒

S R = 1.1x 10 7V/sec 480µA

480µA

50· 60 = 0.4V and V DS 6 =

V ou t (max) = 2.5-0.4 = 2. 1 V

110·60 = 0.2697 V

&

V out (min) = -2.5V+ 0.2697 V = -2. 23 0 V

3.) ICM (min) = -2.5V+V GS 3 -|V TP| = -2.5V+

∴ ICM (min) = -2.5+0.191 = -2.309V

2·2 0 110·10 +0.7V-0.7V ⇒ ICM ( min) = -2. 30 9 V

2· 40 and V SG1 = 50·10 = 0.4V ∴ ICM (max) = 2.5 -V SD5(sat) -V SG1 = 2.5-0.4-0.983 = 1.117V

ICM (max) = ?

ICM ( max) =

V SD5(sat) =

0.983V

1.1171 V

gm1gm6 2K PW 1 I 1 4.) A v = (g +g )(g +g ) gm1 = = L1 sd 2 ds4 ds6 sd 7 2K PW 6 I 6 gm6 = = 2·110·60·240 = 1779µS L6 G II = 0.09·240µA = 21.6µS and

∴

2·2 0 50·10 + 0.7 =

2·50·10·20 =

G I = 0.09·20µA =

141x1779

Av = 1.8x21.6 = 6,452V

A v =

gm1 141µS 5.) GB = C = 3pF = 47Mrads/sec c

⇒

6.) Pdiss = 5x320µA = 1.6mW

⇒

6 , 4 5 2 V/V

GB =

141 µS

7 . 4 8 MHz

P diss = 1. 6 mW

1.8µS


Page 2

Problem 2 - (10 points) Bias current calculation: . S = V dd − V ss or, V T 8 + V ON 8 + I 8 R

T 8

+

2. I 8 3. K p/

= 5 − I 8 .R s .

(1)

Solving for I 8 quadratically would give, I 8 __ 36µA , I 5 __ 36µA , and I 7 __ 60µA Using the formula, g m =

2. K /

g m 2 = 60 µ S , g ds 2

W

. I and g ds = λ I we get, L = 0.9µ S , g ds 4 = 0.72µ S

g m 6 = 363µ S , g ds 6 = 3µ S , g ds 7 = 2.4µ S

(2) (3)

Small-signal open-loop gain: AV 1

The small-signal voltage gain can be expressed as, − g m2 − g m6 = = − 37 and AV 2 = = −67 ( g ds 2 + g ds 4 ) ( g ds 6 + g ds 7 )

Thus, total open-loop gain is, A v = A v1· A v2 = 2489V/V

(3)

Output resistance: Rout =

1 ( g ds 6 + g ds 7 )

= 185K Ω

(5)

Power dissipation: Pdiss = 5(36 + 36 + 60)µ W = 660µ W

(6)

V in ,max = 2.5 − V T 1 − V ON 1 − V ON 5 = 0.51V

(7)

V in ,min = − 2.5 − V T 1 + V T 3 + V ON 3 = −2.21V

(8)

ICMR:

Output voltage swing: V 0,max = 2.5 − V ON 7 = 1.81V Slew Rate: Slew rate under no load condition can be given as, I SR = 5 = 6V / µ s C C In presence of a load capacitor of 20 pF, slew rate would be,  I 5 I 7  SR = min C , C  c L

(9)


Page 3

Problem 6.3-7 - Continued CMRR: Under perfectly balanced condition where I 1 = I 2 , if a small signal common-mode variation occurs at the two input terminals, the small signal currents i1 = i 2 = i 3 = i 4 and the differential output current at node (7) is zero. So, ideally, common-mode gain would be zero and the value for CMRR would be infinity. GBW: Let us design M9 and M10 first. Both these transistors would operate in triode region and will carry zero dc current. Thus, V ds9 = V ds10 ≅ 0 . The equation of drain current in triode region is given as, W I D ≅ K / (V GS − V T ).V DS . L The on resistance of the MOS transistor in triode region of operation would be, W RON = K / (V GS − V T ) . L 1 It is intended to make the effective resistance of M9 and M10 equal to . g m6 So, Thus,

 W 9   W 10  (V K’ 9 L (V GS 9-V T 9) + K’ 10 L  9  10  GS10 -V T 10) = gm6 V D 4 = V D 3 = − 2.5 + V T 3 + V ON 3 = − 1.51V

(11)

V GS 9 ≅ 4V

and V GS 10 ≅ −1V . Putting the appropriate values in (11), we can solve for the aspect ratios of M9 and M10. One of the solutions could be,

 W 9 = 1 and K’  W 10  = very small K’ 9 L 10 L10   9 1 The dominant pole could be calculated as,

( g 4 g 2 ) p1 = − ds + ds 2.π . AV 2 .C C And the load pole would be, − g m 6 p2 = = −2.8MHz. 2.π .C L

=640HZ

(12)

.

for a 20 pF load.

It can be noted that in this problem, the product of the open-loop gain and the dominant pole is approximately equal to the load pole. Thus, the gain bandwidth is approximately equal to 2.8 MHz and the phase margin would be close to 45 degrees.


Page 4

Problem 6.3-7 - Continued PSRR: If a small ripple v S is applied at the V dd terminal, then the gain of this ripple from this terminal to the output can be expressed as, 1- R S g R g +(1/ ) vo  S m8  m 7 = 2.8V/V vs = gds6+gds7 Thus, PSRR due to variations in V dd would be, AV 2.8 = 2489 / 2.8 = 889 .

SPICE file: .model

nmos nmos vto=0.7 lambda=0.04 kp=110u .model pmos pmos vto=-0.8 lambda=0.05 kp=50u vdd 1 0 dc 2.5 ac 0 vss 10 0 dc -2.5 ac 0 vinp 5 0 dc 0 ac 1 *vinn 4 0 dc 0 ac 0 m8 2 2 1 1 pmos w=3u l=1u rs 2 10 100k m5 3 2 1 1 pmos w=3u l=1u m1 6 8 3 3 pmos w=2u l=1u m2 7 5 3 3 pmos w=2u l=1u m3 6 6 10 10 nmos w=4u l=1u m4 7 6 10 10 nmos w=4u l=1u m7 8 2 1 1 pmos w=5u l=1u m6 8 7 10 10 nmos w=10u l=1u cc 7 9 6p cl 8 0 20p m9 8 1 9 9 nmos w=1u l=1u m10 8 10 9 9 pmos w=1u l=100u .op .ac dec 10 1 100meg .option post .end

Operating points: **** mosfets

subckt element 0:m8 0:m5 0:m1 0:m2 0:m3 0:m4 model 0:pmos 0:pmos 0:pmos 0:pmos 0:nmos 0:nmos region Cutoff Cutoff Cutoff Cutoff Saturati Saturati id -35.3708u -34.8506u -17.4107u -17.4399u 17.4107u 17.4399u ibs 0. 0. 0. 0. 0. 0. ibd 14.6292f 11.4726f 28.7676f 28.3314f -9.7598f -10.1959f


Page 5

Problem 6.3-7 - Continued vgs -1.4629 -1.4629 -1.3517 -1.3527 975.9818m 975.9818m vds -1.4629 -1.1473 -2.8768 -2.8331 975.9818m 1.0196 vbs 0. 0. 0. 0. 0. 0. vth -800.0000m -800.0000m -800.0000m -800.0000m 700.0000m 700.0000m vdsat -662.9217m -662.9217m -551.7476m -552.7377m 275.9818m 275.9818m beta 160.9719u 158.6045u 114.3838u 114.1657u 457.1773u 457.9449u gam eff 527.6252m 527.6252m 527.6252m 527.6252m 527.6252m 527.6252m gm 106.7118u 105.1423u 63.1110u 63.1037u 126.1726u 126.3844u gds 1.6480u 1.6480u 761.0636n 763.7975n 670.2604n 670.2604n gmb 36.9704u 36.4266u 21.8648u 21.8623u 43.7126u 43.7860u cdtot 2.021e-18 1.585e-18 2.649e-18 2.609e-18 1.797e-18 1.878e-18 cgtot 7.005e-16 7.000e-16 4.693e-16 4.692e-16 9.467e-16 9.467e-16 cstot 6.906e-16 6.906e-16 4.604e-16 4.604e-16 9.208e-16 9.208e-16 cbtot 7.806e-18 7.806e-18 6.216e-18 6.205e-18 2.402e-17 2.402e-17 cgs 6.906e-16 6.906e-16 4.604e-16 4.604e-16 9.208e-16 9.208e-16 cgd 2.021e-18 1.585e-18 2.649e-18 2.609e-18 1.797e-18 1.878e-18

subckt element 0:m7 0:m6 0:m9 0:m10 model 0:pmos 0:nmos 0:nmos 0:pmos region Cutoff Saturati Linear Cutoff id -61.7971u 61.7971u 0. 0. ibs 0. 0. 0. 0. ibd 24.9901f -25.0099f 0. 0. vgs -1.4629 1.0196 2.4990 -2.5010 vds -2.4990 2.5010 0. 0. vbs 0. 0. 0. 0. vth -800.0000m 700.0000m 700.0000m -800.0000m vdsat -662.9217m 319.5939m 0. 0. beta 281.2376u 1.2100m 110.0000u 500.0000n gam eff 527.6252m 527.6252m 527.6252m 527.6252m gm 186.4385u 386.7225u 0. 0. gds 2.7467u 2.2471u 197.8911u 850.4951n gmb 64.5917u 133.9802u 0. 0. cdtot 5.753e-18 1.152e-17 1.727e-16 17.2658f cgtot 1.1698f 2.3660f 3.463e-16 34.6349f cstot 1.1511f 2.3021f 1.727e-16 17.2658f cbtot 1.301e-17 5.233e-17 9.769e-19 1.033e-16 cgs 1.1511f 2.3021f 1.727e-16 17.2658f cgd 5.753e-18 1.152e-17 1.727e-16 17.2658f

Results from SPICE simulation: i.

Unloaded output (load capacitor = 0) GBW = 1.5 MHz., Phase Margin = 90 deg, 1% settling time = 0.39 us.

ii.

Loaded output (load capacitor = 20 pF) GBW = 1.5 MHz., Phase Margin = 65 deg, 1% settling time = 0.48 us.


Problem 6.3-7 - Continued

Page 6


Problem 6.3-7 - Continued

Page 7


Page 8


+5V

Small signal differential voltage gain: 2/1

By intuitive analysis methods, vo1 -0.5gm1 = vin g ds1 + gds 3 and vout -gm4 = vo1 g ds4 + gds 5

∴

M8

1/1

vout 0.5gm1 gm4 = vin (gds1+gds3)(gds4+gds5) 2KNW1ID1 = L1

gm1 =

2KPW4ID4 = L4

M2 10µA5pF 100µA 4/1

M6

M5 1/1

-5V

gds3 = λPID3 = 0.02·10µA = 0.2µS

2·8·10·100 x10-6 = 126.5µS

gds4 = λPID4 = 0.02·100µA = 2µS,

∴

4/1

v out

24·2·4·10 x10-6 = 43.82µS

gds1 = λNID1 = 0.01·10µA = 0.1µS,

gm4 =

M3 M1 10µA

M7

gds5 = λNID5 = 0.01·100µA = 1µS

v ou t 0.5·43.82·126.5 vin = (0.1+0.2)(1+2) = 3,079V/V

Output resistance: 1 106 R o u t = g +g = 1+2 = 333k Ω ds4 ds5 Dominant pole, p1: 1 1 106 |p1| = R C where R1 = g +g = 0.1+0.2 = 3.33MΩ 1 1 ds1 ds3 and gm4    126.5 = 215.8pF C1 = Cc(1+|Av2|) = 5pF 1 + g +g = 5 1+ 3  ds4 ds5   106 ∴ |p1| = 3.33·2.15.8 = 1,391 rads/sec → |p 1 | = 1,391 rads/sec = 221Hz 0.5·gm1 0.5·43.82x10-6 GB = C = = 4.382Mrads/sec c 5x10-12 GB = 4.382 Mrads/sec = 0.697MHz ID 6 1 0 µ A SR = C = 5pF = 2V/µs c

10/1

vo1

+ v in -

20µA

M4

1/1

P diss = 10V(140µA) = 1.4mW

5/1


Problem 4 - Design Problem 2 (50 points)

Page 9


Page 1


Problem 1 - (10 points) This problem deals +3V with the op amp M3 M4 shown in Fig. M14 P6.5-15. All 1.5I 1.5I device lengths are 1µm, the slew rate M15 M6 M7 is ±8V/µs, the GB is 8MHz, the 0.5I 0.5I I I maximum output I v1 M1 voltage is +2V, the M8 M9 minimum output I v2 M2 voltage is -2V, and the input common I I mode range is from M13 M10 M12 M5 M11 -1V to +2V. Design all W values of all transistors in -3V this op amp. Your Figure P6.5-15 design must meet or exceed the specifications. When calculating the maximum or minimum output voltages, divide the voltage drop across series transistors equally. Ignore bulk effects in this problem. When you have completed your design, find the value of the small signal differential voltage gain, A vd = vout /vid, where vid = v1-v2 and the small signal output resistance, Rout. Solution

1.) The slew rate will specify I .

∴

I = C ·SR = 10-11x8x106 = 10-4 =

80µA.

2.) Use GB to define W 1 and W 2. gm 1 GB = C gm1 = GB·C = 2πx8x 106·10 -11 = 502.4µS → g m 12 (502.4)2 ∴ W 1 = 2K (0.5 I ) = 2·110· 40 = 28.68 ⇒ W 1 = W 2 = 29µm N 3.) Design W 15 to give V T +2V ON bias for M6 and M7. V ON = 0.5V will meet the desired maximum output voltage specification. Therefore, 2 I → V ON 15 = 1V = V SG15 = V ON 15 + |V T | = 2(0.5V) + |V T | K P W 15 2 I 2·80 ∴ W 15 = ⇒ = = 3.2µm W 15 = 4µm K PV ON 15 2 50·12 4.) Design W 3, W 4, W 6 and W 7 to have a saturation voltage of 0.5V with 1.5I current. W 3 =W 4 = W 6 = W 7 =

2(1.5 I )

2·1 20 = = 19.2µm ⇒ W 3=W 4 =W 6 =W 7 = 20µm K PV ON 2 50·0.52

vout 10pF


Page 2

Problem 6.5-15 – Continued 5.) Next design W 8, W 9, W 10 and W 11 to meet the minimum output voltage specification. Note that we have not taken advantage of smallest minimum output voltage because a normal cascode current mirror is used which has a minimum voltage across it of V T + 2V ON . Therefore, setting V T + 2V ON = 1V gives V ON = 0.15V. Using worst case current, we choose 1.5 I . Therefore, 2(1.5 I ) 2·1 20 W 8 = W 9 = W 10 =W 11 = = = 96.8µm ⇒ W 8 =W 9 =W 10 =W 11 = K N V ON 2 110·0.15 2 97µm 6.) Check the maximum ICM voltage. V ic(max) = V DD + V SD3(sat) + V TN = 3V – 0.5 + 0.7 = 3.2V which exceeds spec.

7.) Use the minimum ICM voltage to design W 5.

∴

2· 40   V ic(min) = V SS + V DS5(sat) + V GS1 = -3 + V DS5(sat) +  110·29+0.7 = -1V 2 I V DS5(sat) = 1.142 → W 5 = = 1.11µm = 1.2µm K N V DS 5 (sat)2 Also, let W 12 =W 13 =W 5

⇒

W 12 =W 13 =W 5 = 1.2µm

8.) W 14 is designed as I 14 I W 14 = W 3 I = 20µm 1.5 I = 13.3µm 3

⇒

W 14 = 14µm

Now, calculate the op amp small-signal performance. Rout ≈ r ds11gm9r ds9||gm7r ds7(r ds2||r ds4) 25V 2K N ·I·W 9 = 1306µS, r ds9 = r ds11 = 80µA = 0.312MΩ, 20V 25V gm7 = 2K P·I·W 7 = 400µS, r ds7 = 80µA = 0.25MΩ, r d 2 = 40µA = 0.625MΩ 20V r ds4 = 120µA = 0.1667MΩ ∴ R out ≈ 127ΜΩ||13.16ΜΩ = 11.92ΜΩ gm9 =

Avd =gm1 Rout

∴

Avd = (505µS)(11.92MΩ) = 6,022V/V

gm 1 = K N ·I·W 1 =

505 µS

⇒ A vd = 6,022V/V

1.5X as much

3.6

14.25 uA

3.6

14.25e3 9.12 14.25e3

0.54 7.2M

1.54

9.12

4.75

1.8

4.75

3.6

4.75

=2.59 2590 3.6

401,000

719

is changed to 50ohm

+

x50ohm=11.8+251x0.05=24.35k 16.37 Req

377

16.37

4.487

1

1+REgm17

97ohm

(1+REgm17)

79.14 79.1

4.487

97 2703

78.4K 0.097K

404,610

79.14

78.4K


Page 5

Problem 5 – (10 points) A two-stage, BiCMOS op amp is shown. For the PMOS transistors, the model parameters are K P’=50µA/V2, V TP = -0.7V and λ P = 0.05V-1. For the NPN BJTs, the model parameters are β F = 100, V CE (sat) = 0.2V, V A = 25V, V t = 26mV, I s = 10fA and n=1. (a.) Identify which input is positive and which input is negative. (b.) Find the numerical values of differential voltage gain magnitude, | Av(0)|, GB (in Hertz), the slew rate, SR , and the location of the RHP zero. (c.) Find the numerical value of the maximum and minimum input common mode voltages.

1.2V 20/1

M8

M5

25µA

v1

20 /1

-

M1

20/1 25µA

20 /1

12.5µA

W/L ratios in microns

M7 50µA vout v2 C c= 5pF + Q6

Q4

Q3

-1.2V

S01E2P1

Solution

M2

40/1

(a.) The plus and minus signs on the schematic show which input is positive and negative. (b.) The differential voltage gain, Av(0), is given as g m1 gm 6 Av(0) = g +g +g ·g +g ds2 o4 π 6 ds7 o6 r ds2 =

1 λ P I D

20 = 12.5µA =

β F r π 6 = g = 52k Ω m6

∴

gm1 = gm2 = V A

1.6MΩ,r o4= I

C

50·25·20 = 158.1µS

I C 50µA 25V = 12.5µA2=MΩ, gm6 = V = 26mV =1923µS t

V A 1 20 25V r ds7 = = 50µA = 0.4MΩ and r o6 = I = 50µA = 0.5MΩ C λ P I D

|Av(0)| = [158.1(1.6||2||0.052)][1923(0.4||0.5)] =

3319.3V/V

gm1 158.1µS GB = C = 5pF = 31.62x106 rads/sec → GB = 5.0325MHz c 25µA SR = 5pF =

5V/µs

g m6 1.923 mS RHP zero = C = 5pF = c

384.6x106

rads/sec=61MHz

(c.) The maximum input common mode voltage is given as vicm + = V CC -V DS 5(sat) - V SG 1 = 1.2 -

∴

2· 25 50· 20 - 0.7 -

2x1 2. 5 50· 20 = 0. 5 - 0. 224-0.158 =

vicm + = 0.118V

 12.5µA  vicm - = -1.2 + V BE 3 - V T 1 = -1.2 + V t ln 10fA - 0.7 = -1.9 + 0.545 = -1.3554V  


Page 1

Homework Assignment No. 9 Solutions

Problem 1 – (10 points)








Problem 9– (10 points)

Problem 10– (10 points)


Problem 4

Problem 6– P7.2-4

Use the technique of Ex. 7.2-2 to extend the GB of the cascode op amp of Ex. 6.5-2 as much as possible that will maintain 60° phase margin. What is the minimum value of C L for the maximum GB? Solution

Assuming all channel lengths to be 1 or,

C 7

=

C gs 7

C 7

=

75 + 51 + 9 + 51 = 186

g m7

=

+

C bd 7

+

C gd 6

+

µ m

, the total capacitance at the source of M7 is

C bd 6

fF

707 µ S

Thus, the pole at the source of M7 is g p S 7 ! m7 !605 MHz. C 7 =

=

The total capacitance at the source of M12 is C 12 = C gs12 + C bd 12 + C gd 11 + C bd 11 or,

C 12

=

g m12

34 + 29 + 4 + 29 =

=

96

fF

707 µ S

Thus, the pole at the source of M12 is g p S 12 ! m12 !1170 MHz. C 12 =

=

The total capacitance at the drain of M4 is C 4 = C gs 4 + C gs 6 + C bd 4 + C gd 2 + C bd 2 or,

C 4

=

g m 4

43 + 75 + 21 + 3 + 19 =

283 µ S

=

161

fF


Problem

6

Page 11

- Continued

Thus, the pole at the drain of M4 is g p D 4 ! m 4 !280 MHz. C 4 =

=

The total capacitance at the drain of M8 is C 8 = C gd 8 + C bd 8 + C gs10 + C gs12 or,

C 8

=

R2

+

9 + 51 + 34 + 34

1 =

g m10

=

128 fF

3.4 K !

Thus, the pole at the drain of M8 is p D 8

=

"

1

#% R $

1

2

+

gm10

&( C '

=

" 366 MHz.

8

o

For a phase margin of 60 , we have PM = 180

/ ) "1 # GB & # # # ,2 "1% GB & "1% GB & "1 % GB & % ( ( ( ( " 190 " *tan + tan + tan + tan -4 p p p p $ ' $ ' $ ' $ ' + S 7 S 12 D4 D 8 .3 0

o

o

Solving the above equation GB

And,

Av

Thus,

p1

!

=

=

65

MHz.

6925

9.39

V/V KHz, and

C L " 1.54

pF


Page 1



Problem 2 – (10 points) Common mode half circuit: Vo1 = Vo 2 = VDD − VGS 3

2 I D + VTP = Vov + VTP = 0.8V ' w k p L ⇒ Vo1 = Vo 2 = 2.5 − 0.8 = 1.7V VGS 3 =

adm = − g m1 ( ro1 ro3 20 K ) = −1(100 200 20) = −15.38, where : g m1 =

w

2k n '

L

I D = k n'

w L

vo v = 5000 × 0.2 = 1mS

⎧ ' ⎛ w⎞ ⎪ k p ⎜ L ⎟ = 5000 µ 2 I D 3 2 ×100 µ ⎪ ⎝ ⎠3 ⇒ 0.2 = ⇒⎨ vov = ' ⎛ w ⎞ ' ⎛ w ⎞ ⎪ k ' ⎛ w ⎞ = 5000 µ k p ⎜ ⎟ k p ⎜ ⎟ ⎪⎩ n ⎜⎝ L ⎟⎠1 ⎝ L ⎠3 ⎝ L ⎠3 ro1 = 100 K , ro 3 = 200 K acm = −

g m1

1 + 2 g m1ro 5

(ro1 (1 + 2 g m1ro5 ) ro3

1 1 = 0.01, where : )= g m3 1 + 2 m × 50 K

g m 3 = 5000 × 0.2 = 1mS ro5 = 50 K

Because of adding the 20Kresistors, the a dm becomes smaller but a cm becomes much smaller. The effective impedance of M 3 and M4 is now 1/gm, which is much smaller than ro adm /acm=1538 which is much higher than 100 in 12.4.1

Problem 3 – (10 points) Without Ccs: 1

( Rcs vcms = (vov1 + vov 2 )

( Rcs voc = vcms voc

C1s

1 C1s

)

) + Rcs

vov1 + vov 2

=2

2 Rcs Rcs + Rcs ( Rcs C1s + 1)

⇒ acms =

1+

1 RcsC1 s 2

Gain starts to drop at frequencies higher than the pole. In Other words the CM detector cannot follow the signal at the same rate. With Ccs: 1

( Rcs vcms = (vov1 + vov 2 )

( Rcs voc = vcms voc

(Ccs + C1 ) s 1

(Ccs + C1 ) s

)

) + ( Rcs

1 Ccs s

)

vov1 + vov 2

2

=2

Rcs Ccs s + 1 Rcs Ccs s + 1 + 1 + Rcs (C1 s + Ccs s)

If C cs >>

C 1

2



⇒ acms =

1 + RcsCcs s C 1 + Rcs ( Ccs + 1 ) s 2

gain stays constant over the entire frequency range.

Problem 4 – (10 points) w ( )12 20 w L = ⇒ ( )12 = 19.2 ⇒ w12 = 19.2 µ m w L 100 ( )11 L I D 51 = 120µ w ( )51 120 w 16 L = ⇒ ( )51 = 1.2 × × 0.8 = 19.2 ⇒ w51 = 19.2 µ m w 100 L 0.8 ( )14 L SR =

100µ A 4 pF

= 25 V

µ sec

vo1 min = max( −1.65 + vov 51 + vov1 + vov1C , vi − vt + vov1C ) vo1 max = 1.65 − vov 27 − vgs 24

Problem 5 – (10 points) v v

+ o

= vDD − vds 3 − v gs1

o

= vDD − vds 6 − vgs 2

−

k n ' = µnCox = 126, k p ' = µ p Cox = 57 vov 6 = vov3 =

20 µ k n ' (25)

20µ k p ' (50)

= 0.079V = 0.083V

Vtn = Vt 0 + 0.16( 3.5 + 0.65 − 0.65) = 0.897V

⇒ vgs1 = 2.5 −1 − 0.083 = 1.41V 2 ×1mA ⎛w⎞ ⎛w⎞ ⇒⎜ ⎟ = = 60, ⎜ L ⎟ = 0.1× 60 = 6 2 ⎝ L ⎠1 126 µ × (1.41 − 0.897) ⎝ ⎠4 Vtp = Vt 0 − 0.44( 3.5 + 0.65 − 0.65) = −1.242V

⇒ vgs 2 = −2.5 + 1 + 0.079 = 1.421V 2 ×1mA ⎛w⎞ ⎛w⎞ ⇒⎜ ⎟ = = 1095, ⎜ ⎟ = 0.1×1095 = 109.5 2 × − µ L 57 (1.421 1.242) ⎝ ⎠2 ⎝ L ⎠4


Page 1



Problem 2 – (10 points) Applying the half-circuit principle, it can be seen that each ½ circuit consists of a cascade of two common-source (CS) stages – the first with a diode connected PMOS load and the other with an NMOS load. The half circuit representation is shown along-side. The gain of the first stage is:

Av1 = Gm Rout =

g m1 g m3

In general for a CS stage with an active load, the primary noise contributors can be represented as shown below (for the second CS stage in the problem). From the figure along-side, we have:

i

2 n5

i

2 n7

2

K P g m 5 ⎛ 2 ⎞ = 4kT ⎜ ⎟ g m5 + C OX (WL )5 f ⎝ 3 ⎠ 2

K N g m 7 ⎛ 2 ⎞ = 4kT ⎜ ⎟ g m 7 + C OX (WL )7 f ⎝ 3 ⎠

Therefore the input referred noise at the gate of M5 is given by:

v

2 o1

in 5 + in 7 2

=

2

2

g m5

Similarly, the noise at the gate of M1 due to M1 and diode connected M3 can be expressed as:

v

2 in (1, 3)

in1 + in3 2

=

2

2

g m1 2

2

2 K N g m1 K P g m 3 ⎛ 2 ⎞ ⎛ 2 ⎞ Where, i = 4kT ⎜ ⎟ g m1 + and i n 3 = 4kT ⎜ ⎟ g m 3 + C OX (WL )1 f C OX (WL )3 f ⎝ 3 ⎠ ⎝ 3 ⎠ 2 n1

Therefore the total noise referred to the input (gate of M1) is: 2 in

v =v 2 in

v =

2 in (1, 3)

+

(

vo21 Av21

(i =

2 n1

+ in23 )

g m2 1

) (

(i +

+ in27 )× g m2 3 . Therefore for one half-circuit, g m2 5 × g m2 1

2 n5

)

g m2 5 × in21 + in23 + in25 + in27 × g m2 3 g m2 5 × g m2 1

Considering only the thermal noise, the total input referred noise is:

2

v in (THERMAL ) = 2 ×

⎡ ⎤ ⎡ ⎤ ⎛ 2 ⎞ ⎛ 2 ⎞ g m2 5 ⎢4kT ⎜ ⎟( g m1 + g m 3 )⎥ + g m2 3 ⎢4kT ⎜ ⎟(g m 5 + g m 7 )⎥ ⎝ 3 ⎠ ⎝ 3 ⎠ ⎣ ⎦ ⎣ ⎦ g m 5 × g m1 2

2

Considering only the flicker noise, the total input referred noise is: 2 2 2 ⎡ K N g m2 1 K P g m 3 ⎤ K P g m 5 K N g m 7 ⎤ 2 ⎡ + + g ⎢ ⎥ + g m3 ⎢ ⎥ C WL f C WL f C WL f C OX (WL )7 f ⎦ ( ) ( ) ( ) OX OX OX 1 3 5 ⎣ ⎦ ⎣ = 2× 2 2 g m 5 × g m1 2 m5

2

v in ( FLICKER )

Equating the thermal noise and flicker noise to find the flicker noise corner frequency ( f C), we have: 2 2 2 ⎧⎪ 2 ⎡ K N g m2 1 K P g m3 ⎤ K N g m 7 ⎤ ⎫ ⎪ 1 2 ⎡ K P g m 5 + + + = g ⎨ g m5 ⎢ m3 ⎢ ⎥ ⎥⎬ C WL C WL f ( ) ( ) ⎪⎩ ⎣ C OX (WL )1 C OX (WL )3 ⎦ ⎪ OX OX C 5 7 ⎣ ⎦⎭

⎡ ⎤ ⎡ ⎤ ⎛ 2 ⎞ ⎛ 2 ⎞ g m2 5 ⎢4kT ⎜ ⎟( g m1 + g m 3 )⎥ + g m2 3 ⎢4kT ⎜ ⎟(g m 5 + g m 7 )⎥ ⎝ 3 ⎠ ⎝ 3 ⎠ ⎣ ⎦ ⎣ ⎦ Numerical Calculations: All transistors in saturation, (W/L)1,2 = 50/0.6, (W/L)3,4 = 10/0.6, (W/L)5,6 = 20/0.6 and (W/L)7,8 = 56/0.6 2 µ nCOX = 75 µA/V2 and µ pCOX = 30 µA/V and ISS = 0.5 mA Therefore  I1 = I2 = I3 = I4 = 0.25 mA and I5 = I6 = I7 = I8 = 0.5mA

Using g m

⎛ W ⎞ = 2 µ C OX ⎜ ⎟ I D , we obtain: ⎝ L ⎠

gm1 = gm2 = 1.768 mS gm3 = gm4 = 0.5 mS gm5 = gm6 = 1 mS gm7 = gm8 = 2.646 mS Using the above, we obtain, the following values for the thermal and flicker noise powers 2

v in (THERMAL ) = 2.247 ×10

−17 V 2

Hz

Assuming tox= 100A°, we obtain COX = 34.53 x 10 . Therefore the total flicker noise is given by: -4

v

2 in ( FLICKER)

3.2417 ×10 −8 V 2 = Hz f

Equating the noise powers to find the flicker noise corner frequency, we obtain: f C = 1.44 GHz.

Problem 3 – (10 points) Assumptions: • VOD = VGS – VTH • Only thermal noise of drain current considered Also, we know for a MOS transistor, we have:

gm =

2 I D

=

V GS − V TH

2 I D V OD

and

r o =

1 λ I D VDD

Dynamic range of the circuit is defined as:

DR =

V out −swing

M5

V b5

M4

V b4

V noise −out

where Vout-swing is the maximum output voltage swing of the amplifier and Vnoise-out is the total output referred voltage noise. We know for a folded cascode amplifier,

Gm = g m1

VDD v in

M1

v out M2

V b2

and

Rout = g m 4 r o 4 r 05 g m 2 r o 2 (r o1 r o 3 ) , M3

V b3

which on expansion, yields

Rout =

g m 2 g m 4 r o1r o 2 r o 3 r o 4 r o 5 g m 4 r o 4 r o5 (r o1 + r o 3 ) + g m 2 r o1r o 2 r o 3

Since from the above, we see that both Gm and Rout are dependent on the over-drive voltage, we need to consider the effect of variation of VOD on both. Substituting for g m and Rout in terms of VOD, we obtain the following expressions for Gm and Rout

Gm = g m1 = Rout =

2

×

2 I D V OD

1

5 V OD λ 2 I D

Expression for output swing in terms of the over-drive voltage: Output swing of a folded cascode amplifier:

V out − swing = V DD − 4V OD Expression for the output referred noise as a function of over-drive voltage: The major noise contributors in the folded cascode amplifier are: M1, M3 and M5. Therefore we first obtain the noise contributions of each of these noise sources at the output.

2

⎡

⎛ 2 ⎞⎤ 2 2 ⎟⎟⎥ × g m1 Rout g 3 ⎝ m1 ⎠⎦ ⎣ ⎡ ⎛ 2 ⎞⎤ 2 2 ⎟⎟⎥ × g m3 Rout = ⎢4kT ⎜⎜ 3 g ⎝ m3 ⎠⎦ ⎣ ⎡ ⎛ 2 ⎞ ⎤ 2 ⎟⎟ ⎥ × g m2 5 Rout = ⎢ 4 kT ⎜⎜ ⎝ 3 g m 5 ⎠ ⎦ ⎣

v n−out (1) = ⎢4kT ⎜⎜ 2

v n−out ( 3) 2

v n − out ( 5 )

Therefore taking the superposition of these noise sources, we have the output referred noise given by: 2 ⎛ 2 ⎞ 2 v n−out = 4kT ⎜ ⎟ × [g m1 + g m3 + g m5 ]× Rout ⎝ 3 ⎠

Therefore substituting expressions for g m and Rout into the above, we obtain the total output referred noise power as: 2 1 ⎛ 2 ⎞ ⎛ 32 ⎞ v n−out = 4kT × ⎜ ⎟ × ⎜ ⎟× 3 4 ⎝ 3 ⎠ ⎝ 25 ⎠ V OD λ I D

Therefore the output referred noise voltage can be expressed as a function of VOD as:

vn−out = B ×

1 3

(V OD ) 2

Dynamic Range calculations: Initial expression for the dynamic range (DR 1): 3

DR1 =

(V DD − 4V OD )(V OD ) 2 B

After the over-drive voltage changes to 75% of its original value, the new dynamic range (DR2) is given by:

3 (V DD − 3V OD )⎛ ⎜ V OD ⎞⎟ ⎝ 4 ⎠ DR2 =

3

2

B Therefore, finding the difference between the initial and final dynamic ranges, we can find the variation in the dynamic range caused by 25% reduction in VOD 3

∆ DR = DR1 − DR2

(V ) 2 ⎡V DD − 7V OD ⎤ = OD B

⎢ ⎣

4

⎥ ⎦

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Page 1

Homework Assignment No. 13 Solutions Problem 1 – (10 points)



6645530 Allen and Holberg Homework Solution(2)

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