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Backend (Physical Design) Interview Questions and Answers Below are the sequence sequence of questions asked for a physical design design engineer.
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ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers
Can you talk about low power techniques? How low power and latest 90nm/65nm technologies are related? Refer here and browse for different low power techniques. Do you know about input vector controlled method of leakage reduction? Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction. How can you reduce dynamic power?
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ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers
-Use multiple voltage domains-Multi vdd What are the vectors of dynamic power? Voltage and Current
Top Posts What is the difference between FPGA and ASIC? This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that the...
How will you do power planning? Refer here for power planning. If you have both IR drop and congestion how will you fix it ? -Spread macros -Spread standard cells -Increase strap width -Increase number of straps -Use proper blockage Is increasing power line width and providing more number of straps are the only solution to IR drop? -Spread macros -Spread standard cells -Use proper blockage In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why? (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must insert buffer !) Near to capture path. Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degarde. If all those paths have voilation then you may insert buffer nearer to launch flop provided it improves slack. How will you decide best floorplan? Refer here for floor planning. What is the most challenging task you handled? What is the most challenging job in P&R flow? -It may be power planning- because you found more IR drop -It may be low power target-because you had more dynamic and leakage power -It may be macro placement-because it had more connection with standard cells or macros
Companywise ASIC/VLSI Interview Questions Senior Physical design engineer position, Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Be... Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high s... Backend (Physical Design) Interview Questions and Answers Below are the sequence of questions asked for a physical design engineer. In which field are you interested? Answer to this question... Clock Gating Clock tree consume more than 50 % of dynamic power. The components of this power are: 1) Power consumed by combinatorial log... Clock Definitions lock Definitions: Rising and falling edge of the clock For a +ve edge triggered design +ve (or rising) edge is called ... Setup and hold slack 13. Setup and hold slack Slack Slack is defined as difference between actual or achieved time and the desired time for a timing ... Embedded System for Automatic Washing Machine using Microchip PIC18F Series Microcontroller The design uses the PIC18F series microcontroller. All the control functionalities of the system are built around this. Upgradeability is th...
ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers
How will you synthesize clock tree?
the same compani... Constraints: Clock, Logical DRC, Area, Power 14. Constraints: Clock, Logical DRC, Area, Power Design constraints are generally specified in “Synopsys Design Constraints”
-Single clock-normal synthesis and optimization -Multiple clocks-Synthesis each clock seperately -Multiple clocks with domain crossing-Synthesis each clock seperately and balance the skew How many clocks were there in this project?
...
-It is specific to your project -More the clocks more challenging ! Search
How did you handle all those clocks? -Multiple clocks-->synthesize seperately-->balance the skew-->optimize the clock tree Read More...
Are they come from seperate external resources or PLL? -If it is from seperate clock sources (i.e.asynchronous; from different pads or pins) then balancing skew between these clock sources becomes challenging. -If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy. Why buffers are used in clock tree? To balance skew (i.e. flop to flop delay) What is cross talk? Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This affect is known as cros talk. Cross talk may lead setup or hold voilation. How can you avoid cross talk? -Double spacing=>more spacing=>less capacitance=>less cross talk -Multiple vias=>less resistance=>less RC delay -Shielding=> constant cross coupling capacitance =>known value of crosstalk -Buffer insertion=>boost the victim strength How shielding avoids crosstalk problem? What exactly happens there? -High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to either VDD or VSS. Coupling capacitance remains constant with VDD or VSS. How spacing helps in reducing crosstalk noise? width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less
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ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers
any other signal. If any other signal switches fast then also we can use double space. Double spacing=>width is more=>capacitance is less=>less cross talk Multiple vias=>resistance in parellel=>less resistance=>less RC delay
How buffer can be used in victim to avoid crosstalk? Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to coupled signal from aggressor.
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1 comment: VARAHA NAGESWARARAO May 23, 2014 at 3:42 PM Good for knowledge Reply
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ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers
