Basic Cell

SRAM cell 6T **I used this netlist for simulate the cell (0.35u) in three modes (writehold read) in a transient** .include modn.mod .include mod!.mod *sources **su!!l" #dd $ 0 dc 0.% **access control #wl wl 0 !ulse(0 0.% &m $00u $00u &m 'm) **data #l $ 0 dc 0.% #lr R$ 0 !ulse(0 0.% 5m $00u $00u $5m $) **control #r+w r+w 0 !ulse(0 0.% 0 $u $u $0m $) *de#ices **switches , $  -R /($) r+w10 01$e&0 $m1$e&0 ,R R$ R -R /($) r+w10 01$e&0 $m1$e&0 **mos transistors  latch m$ 2 2R 0 0 modn w$u l0.35u m& 2 2R $ $ mod! w$u l0.35u m3 2R 2 0 0 modn w$u l0.35u m% 2R 2 $ $ mod! w$u l0.35u **mos transistors  data access m5  wl 2 0 modn w$0u l0.35u m6 R wl 2R modn w$0u l0.35u *anal"sis .tran $u $5m 0 .o!tion !ost .end *"ou could chan4e the mos tansistors models SRAM cell 6T **I used this netlist for simulate the cell (0.35u) in three modes (writehold read) in a transient** .include modn.mod .include mod!.mod *sources **su!!l" #dd $ 0 dc 0.% **access control #wl wl 0 !ulse(0 0.% &m $00u $00u &m 'm) **data #l $ 0 dc 0.%

#lr R$ 0 !ulse(0 0.% 5m $00u $00u $5m $) **control #r+w r+w 0 !ulse(0 0.% 0 $u $u $0m $) *de#ices **switches , $  -R /($) r+w10 01$e&0 $m1$e&0 ,R R$ R -R /($) r+w10 01$e&0 $m1$e&0 **mos transistors  latch m$ 2 2R 0 0 modn w$u l0.35u m& 2 2R $ $ mod! w$u l0.35u m3 2R 2 0 0 modn w$u l0.35u m% 2R 2 $ $ mod! w$u l0.35u **mos transistors  data access m5  wl 2 0 modn w$0u l0.35u m6 R wl 2R modn w$0u l0.35u *anal"sis .tran $u $5m 0 .o!tion !ost .end *"ou could chan4e the mos tansistors models SRAM cell 6T **I used this netlist for simulate the cell (0.35u) in three modes (writehold read) in a transient** .include modn.mod .include mod!.mod *sources **su!!l" #dd $ 0 dc 0.% **access control #wl wl 0 !ulse(0 0.% &m $00u $00u &m 'm) **data #l $ 0 dc 0.% #lr R$ 0 !ulse(0 0.% 5m $00u $00u $5m $) **control #r+w r+w 0 !ulse(0 0.% 0 $u $u $0m $) *de#ices **switches , $  -R /($) r+w10 01$e&0 $m1$e&0 ,R R$ R -R /($) r+w10 01$e&0 $m1$e&0 **mos transistors  latch m$ 2 2R 0 0 modn w$u l0.35u m& 2 2R $ $ mod! w$u l0.35u m3 2R 2 0 0 modn w$u l0.35u m% 2R 2 $ $ mod! w$u l0.35u

**mos transistors  data access m5  wl 2 0 modn w$0u l0.35u m6 R wl 2R modn w$0u l0.35u *anal"sis .tran $u $5m 0 .o!tion !ost .end *"ou could chan4e the mos tansistors models SRAM cell 6T **I used this netlist for simulate the cell (0.35u) in three modes (writehold read) in a transient** .include modn.mod .include mod!.mod *sources **su!!l" #dd $ 0 dc 0.% **access control #wl wl 0 !ulse(0 0.% &m $00u $00u &m 'm) **data #l $ 0 dc 0.% #lr R$ 0 !ulse(0 0.% 5m $00u $00u $5m $) **control #r+w r+w 0 !ulse(0 0.% 0 $u $u $0m $) *de#ices **switches , $  -R /($) r+w10 01$e&0 $m1$e&0 ,R R$ R -R /($) r+w10 01$e&0 $m1$e&0 **mos transistors  latch m$ 2 2R 0 0 modn w$u l0.35u m& 2 2R $ $ mod! w$u l0.35u m3 2R 2 0 0 modn w$u l0.35u m% 2R 2 $ $ mod! w$u l0.35u **mos transistors  data access m5  wl 2 0 modn w$0u l0.35u m6 R wl 2R modn w$0u l0.35u *anal"sis .tran $u $5m 0 .o!tion !ost .end *"ou could chan4e the mos tansistors models SRAM cell 6T **I used this netlist for simulate the cell (0.35u) in three modes (writehold read) in a transient** .include modn.mod

.include mod!.mod *sources **su!!l" #dd $ 0 dc 0.% **access control #wl wl 0 !ulse(0 0.% &m $00u $00u &m 'm) **data #l $ 0 dc 0.% #lr R$ 0 !ulse(0 0.% 5m $00u $00u $5m $) **control #r+w r+w 0 !ulse(0 0.% 0 $u $u $0m $) *de#ices **switches , $  -R /($) r+w10 01$e&0 $m1$e&0 ,R R$ R -R /($) r+w10 01$e&0 $m1$e&0 **mos transistors  latch m$ 2 2R 0 0 modn w$u l0.35u m& 2 2R $ $ mod! w$u l0.35u m3 2R 2 0 0 modn w$u l0.35u m% 2R 2 $ $ mod! w$u l0.35u **mos transistors  data access m5  wl 2 0 modn w$0u l0.35u m6 R wl 2R modn w$0u l0.35u *anal"sis .tran $u $5m 0 .o!tion !ost .end *"ou could chan4e the mos tansistors models