Radon is an invisible, odorless, and chemically inactive radioactive gas produced by the decay of uranium ore. Various types of equipment and components have been proposed for use in effective radon detection. In this paper, we describe a radon detec
Full description
Allen and Holberg - CMOS Analog Circuit Design
I. INT IN TRODU RO DUCT CTIO ION N Contents
I.1
I n t r o du c t i o n
I.2
Anal Analog og Inte Integr grat ated ed Circ Circui uitt Desi Design gn
I.3 I.3
Technology Ov Overview
I.4
Notation
I.5
Anal Analog og Circ Circui uitt Anal Analys ysis is Tech Techni niqu ques es
Page I.0-1
Allen and Holberg - CMOS Analog Circuit Design Organization
Chapter 10 D/A and A/D Converters
Chapter 11 Analog Systems
SYSTEMS
Chapter 7 CMOS Comparators
Chapter 8 Simple CMOS Opamps
Chapter 9 High Performance Opamps
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
Chapter 3 CMOS Device Modeling
DEVICES Introduction
Chapter 4 Device Characterization
Page I.0-2
Allen and Holberg - CMOS Analog Circuit Design
Page I.2-1
I.1 - INTRODUCTION
GLOBAL OBJECTIVES • Teach the analysis, modeling, simulation, and design of analog circuits implemented in CMOS technology. • Emphasis will be be on the the design methodology and a hierarchical hierarc hical approach to the subject. SPECIFIC OBJECTIVES 1. Present an overall, uniform viewpoint of CMOS analog circuit design. 2. Achieve an understanding of analog circuit design. • Hand calculations calculations using simple models • Emphasis on insight • Simulation to provide second-order design resolution 3. Present a hierarchical approach. • Sub-blocks → Blocks → Circuits → Systems 4. Examples to illustrate the concepts.
Allen and Holberg - CMOS Analog Circuit Design I.2
Page I.2-1
ANALOG INTEGRATED CIRCUIT DESIGN
ANALOG DESIGN TECHNIQUES VERSUS TIME
FILTERS
AMPLIFICATION
Passive RLC circuits
Open-loop amplifiers
1935-1950 Active-RC Filters Requires precise definition of time constants (RC products)
1978
Feedback Amplifiers Requires precise definition of passive components
Switched Capacitor Filters Requires precise C ratios and clock
Switched Capacitor Amplifiers Requires precise C ratios
1983 Continuous Time Filters Time constants are adjustable
Continuous Time Amplifiers Component ratios are adjustable
1992
?
Digitally assisted analog circuits
?
Allen and Holberg - CMOS Analog Circuit Design
Page I.2-2
DISCRETE VS. INTEGRATED ANALOG CIRCUIT DESIGN
Activity/Item
Discrete
Integrated
Component Accuracy Well known
Poor absolute accuracies
Breadboarding?
Yes
No (kit parts)
Fabrication
Independent
Very Dependent
Physical
PC layout
Layout, verification, and
Implementation Parasitics
extraction Not Important
Must be included in the design
Simulation
Testing
CAD
Components
Model parameters well
Model parameters vary
known
widely
Generally complete
Must be considered
testing is possible
before the design
Schematic capture,
Schematic capture,
simulation, PC board
simulation, extraction,
layout
LVS, layout and routing
All possible
Active devices, capacitors, and resistors
Allen and Holberg - CMOS Analog Circuit Design
Page I.2-3
THE ANALOG IC DESIGN PROCESS
Conception of the idea Definition of the design Comparison with design specifications
Signals are continuous in amplitude Signal are discontinuous in and can be continuous or discrete in amplitude and time - binary signals time have two amplitude states Designed at the circuit level
Designed at the systems level
Components must have a continuum Component have fixed values of values Customized
Standard
CAD CAD tool toolss are are diff diffic icul ultt to appl applyy
CAD tool toolss have have been een extr extrem emel elyy successful
Requires precision modeling
Timing models only
Performance optimized
Programmable by software
Ir r egu lar b lock
Regular blocks
Diff Diffiicul cult to to rou route au automati atically
Easy to to ro route au automatical cally
Dynamic range limited by power Dynamic range unlimited supplies and noise (and linearity)
Allen and Holberg - CMOS Analog Circuit Design I.3
Page I.3-1
TECHNOLOGY OVERVIEW
BANDWIDTHS OF SIGNALS USED IN SIGNAL PROCESSING APPLICATIONS Video Acoustic imaging
Seismic
Radar
Sonar Audio
AM-FM radio, TV Telecommunications
1
10
10 0
1k
10k
100 k 1 M 10 M 100 M Signal Frequency (Hz)
Microwave 1G
Signal frequency used in signal processing applications.
1 0G 1 0 0 G
Allen and Holberg - CMOS Analog Circuit Design
Page I.3-2
BANDWIDTHS THAT CAN BE PROCESSED BY PRESENTDAY TECHNOLOGIES
BiCMOS Bipolar analog Bipolar digital logic MOS digital logic MOS analo Optical GaAs 1
10
100
1k
10k
1 0 0 k 1 M 1 0 M 1 0 0 M 1G 1 0G 1 0 0 G Signal Frequency (Hz) Frequencies that can be processed by present-day technologies.
Allen and Holberg - CMOS Analog Circuit Design
Page I.3-3
CLASSIFICATION OF SILICON TECHNOLOGY
Silicon IC Technologies
Bipolar
Junction Isolated
Dielectric Isolated
Bipolar/MOS
CMOS
Aluminum gate
MOS
PMOS (Aluminum Gate)
Silicon gate
NMOS
Aluminum gate
Silicon gate
Allen and Holberg - CMOS Analog Circuit Design
Page I.3-4
BIPOLAR VS. MOS TRANSISTORS
CATEGORY
BIPOLAR
CMOS
Turn-on Voltage
0.5-0.6 V
0.8-1 V
Saturation Voltage gm at 100 µA
0.2-0.3 V
0.2-0.8 V
4 mS
0.4 mS (W=10L)
Analog Switch Implementation
Offsets, asymmetric
Good
Power Dissipation
Moderate to high
Low but can be large
Speed
Fas ter
Fast
Compatible Capacitors Voltage dependent
Good
AC Performance Dependence
DC variables only
DC variables and geometry
Number of Terminals
3
4
Noise (1/f)
Go o d
P o or
Noise Thermal
OK
OK
Offset Voltage
< 1 mV
5-10 mV
Allen and Holberg - CMOS Analog Circuit Design
Page I.3-5
WHY CMOS???
CMOS is nearly ideal for mixed-signal designs:
• Dense digital logic • High-performance analog
DIGITAL
ANALOG
MIXED-SIGNAL IC
Allen and Holberg - CMOS Analog Circuit Design I.4
NOTATION
SYMBOLS FOR TRANSISTORS
Drain Gate
Drain Bulk Gate
Source Source/bulk n-channel, enhance- n-channel, enhancement, bulk at most ment, VBS ≠ 0 negative supply Drain Gate
Drain Bulk Gate
Source Source/bulk p-channel, enhance- p-channel, enhancement, bulk at most ment, VBS ≠ 0 positive supply
Page I.4-1
Allen and Holberg - CMOS Analog Circuit Design SYMBOLS FOR CIRCUIT ELEMENTS
II.1 Basi Basicc Fabr Fabric icat atio ionn Proc Proces esse sess II.2 II.2 CMOS Technology II.3 PN Junction II.4 II.4 MOS Tr Transistor II.5 II.5 Pass Passiive Compo mponents II.6 II.6 Lat Latchu chup Pro Protec tectio tion II.7 II.7 ESD Pr Protection II.8 Geom Geomet etri rica call Cons Consid ider erat atio ions ns
Page II.0-1
Allen and Holberg - CMOS Analog Circuit Design Perspective
Chapter 10 D/A and A/D Converters
Chapter 11 Analog Systems
SYSTEMS
Chapter 7 CMOS Comparators
Chapter 8 Simple CMOS Opamps
Chapter 9 High Performance Opamps
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
DEVICES
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
Page II.0-2
Allen and Holberg - CMOS Analog Circuit Design
Page II.0-3
OBJECTIVE • Provide an understa understanding nding of CMOS CMOS technolog technologyy suffici sufficient ent to enhanc enhancee circuit design. • Characterize Characterize passive passive components components compatible compatible with basic technologi technologies. es. • Provide a background for modeling at the circuit level. • Understand the limits and constraints introduced by technology.
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-1
II.1 - BASIC FABRICATION PROCESSES
BASIC FABRTICATION PROCESSES
Basic Steps
• • • • •
Oxide growth Thermal diffusion Ion implantation Deposition Etching
Photolithography Means by which the above steps are applied to selected areas of the silicon wafer. Silicon wafer 0.5-0.8 mm 125-200 mm
n-type: 3-5
Ω -cm
p-type: 14-16
Ω -cm
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-2
Oxidation
The process of growing a layer of silicon dioxide (SiO 2)on the surface of a silicon wafer. Original Si surface
tox
SiO 2
0.44 tox
Si substrate
Uses:
• Provide isolation between two layers • Protect underlying material from contamination • Very thin oxides (100 to 1000 Å) are grown using dry-oxidation techniques. Thicker oxides (>1000 Å) are grown grow n using wet oxidation techniques.
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-3
Diffusion
Movement of impurity atoms at the surface of the silicon into the bulk of the silicon - from higher concentration to lower concentration.
High Concentration
Low Concentration
Diffusion typically done at high temperatures: 800 to 1400 °C. Infinite-source diffusion: N0
ERFC t1
N(x) NB
t1
t3
t2 Depth (x)
Finite-source diffusion: N0
Gaussian t1
N(x) NB
t1
t2 Depth (x)
t3
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-4
Ion Implantation
Ion implantation is the process by which impurity ions are accelerated to a high velocity and physically lodged into the target. Path of impurity atom
Fixed atoms
Impurity final resting place
• Anneal required to activate the impurity atoms and repair physical damage to the crystal lattice. This step is done at 500 to 800 °C. • Lower temperature process compared to diffusion. • Can implant through surface layers, thus it is useful for field-threshold adjustment.
• Unique doping provile available with buried concentration peak.
Concentration peak N(x)
NB 0
Depth (x)
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-5
Deposition
Deposition is the means by which various materials are deposited on the silicon wafer. Examples: • Silicon nitride (Si 3N4)
• Silicon dioxide (SiO 2) • Aluminum • Polysilicon There are various ways to deposit a meterial on a substrate:
Materials deposited using these techniques cover the entire wafer.
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-6
Etching
Etching is the process of selectively removing a layer of material. When etching is performed, the etchant may remove portions or all of:
• the desired material • the underlying layer • the masking layer Important considerations:
• Anisotropy of the etch lateraletchrate A = 1 - verticaletchrate
• Selectivity of the etch (film toomask, and film to substrate) filmetchrate Sfilm-mask = masketchrate
Desire perfect anisotropy (A=1) and invinite selectivity. There are basically two types of etches:
• Wet etch, uses chemicals • Dry etch, uses chemically active ionized gasses. a Mask Film
c b
Underlying layer
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-7
Photolithography
Components
• Photoresist material • Photomask • Material to be patterned (e.g., SiO 2) Positive photoresistAreas exposed to UV light are soluble in the developer Negative photoresistAreas not exposed to UV light are soluble in the developer Steps: 1. Apply photoresist 2. Soft bake 3. Expose the photoresist to UV light through photomask 4. Develop (remove unwanted photoresist) 5. Hard bake 6. Etch the exposed layer 7. Remove photoresist
Allen and Holberg - CMOS Analog Circuit Design
Photomask
UV Light Photomask
Photoresist
Polysilicon
Page II.1-8
Allen and Holberg - CMOS Analog Circuit Design
Page II.1-9
Polysilicon
Photoresist
Photoresist Polysilicon
Polysilicon
Positive Photoresist
Allen and Holberg - CMOS Analog Circuit Design
Page II.2-1
II.2 - CMOS TECHNOLOGY TWIN-WELL CMOS TECHNOLOGY
Features •
Two laye layers rs of of metal metal conn connect ectio ions, ns, both both of them them of of high high qual qualit ityy due due to a planarization step.
•
Opti Optimal mal thr thresh eshol oldd volt voltag ages es of of both both p-ch p-chan anne nell and and n-ch n-chan anne nell trans transis isto tors rs
•
Light Lightly ly doped doped drain drain (LDD) (LDD) tran transis sisto tors rs prev prevent ent hot-e hot-ele lectr ctron on effect effects. s.
•
Good la latchup protection
Allen and Holberg - CMOS Analog Circuit Design
Page II.2-2
n-well implant
SiO2
Photoresist
Photoresist
p- substrate
(a)
Si3N4
SiO2 n-well
p- substrate
(b) n- field implant
Photoresist
Photoresist
Si3N4
n-well p- substrate
(c)
p- field implant
Si3N4
Photoresist n-well
p- substrate
(d) Figure 2.1-5
The major CMOS process steps.
Pad oxide (SiO 2)
Allen and Holberg - CMOS Analog Circuit Design
Page II.2-3
Si3N4 FOX
FOX n-well
p- substrate
(e)
Polysilicon
FOX
FOX n-well
p- substrate
(f)
SiO2 spacer Polysilicon
Photoresist FOX
n-well
FOX
p- substrate
(g) n+ S/D implant
Polysilicon
Photoresist FOX
n-well
p- substrate
(h)
Figure 2.1-5
The major CMOS process steps (cont'd).
FOX
Allen and Holberg - CMOS Analog Circuit Design
Page II.2-4
n- S/D LDD implant
Polysilicon
Photoresist FOX
FOX
n-well
p- substrate
(i)
LDD Diffusion Polysilicon FOX
FOX n-well
p- substrate
(j)
p+ Diffusion
n+ Diffusion
Polysilicon
FOX
FOX n-well
p- substrate
(k)
n+ Diffusion
p+ Diffusion
Polysilicon BPSG
FOX
FOX n-well
p- substrate
(l)
Figure 2.1-5
The major CMOS process steps (cont'd).
Allen and Holberg - CMOS Analog Circuit Design CVD oxide, Spin-on glass (SOG)
Page II.2-5 Metal 1
BPSG FOX
FOX n-well
p- substrate
(m)
Metal 2
Metal 1
BPSG FOX
FOX n-well
p- substrate
(n)
Metal 2
Metal 1
Passivation protection layer
BPSG FOX
FOX n-well
p- substrate
(o)
Figure 2.1-5
The major CMOS process steps (cont'd).
Allen and Holberg - CMOS Analog Circuit Design
Page II.2-6
Silicide/Salicide
Purpose •
Reduce int interco rconnect resi resisstance,
Polysilicide
Metal
Polysilicide
Silicide
FOX
(a)
FOX
(b) Figure 2.1-6
(a) Polycice structure and (b) Salicide structure.
1. Doped atoms atoms near the metallurgical junction lose their free fr ee carr ca rrie iers rs by diffusion. 2. As these fixed atoms lose their free carriers carr iers,, they build build up an electric field which opposes the diffusion mechanism. 3. Equilibrium conditions are reached when: Current due to diffusion = Current due to electric field
Allen and Holberg - CMOS Analog Circuit Design
Page II.3-2
PN JUNCTION CHARACTERIZATION
xp
xd
xn
p-type semiconductor
n-type semiconductor
iD
+vD -
Impurity concentration ( cm-3 ) ND x
0 -NA Depletion charge concentration ( cm-3 ) xp
qND 0
xn
x
-qNA Electric Field (V/cm) x Eo Potential (V)
φo− v D
x
xd
Allen and Holberg - CMOS Analog Circuit Design
Page II.3-3
SUMMARY OF PN JUNCTION ANALYSIS
Barrier potentialN N
kT
N N
φ o = q ln nA 2 D = Vt ln nA 2 D i i Depletion region widthsxn = xp =
2εsi(φo-vD)NA qND(NA+ND) 2εsi(φo-vD)ND qND(NA+ND)
x ∝
Depletion capacitanceC j = A
εsiqNAND 2(NA+ND)
C j0 1 = φo-v D φo-v D
Breakdown voltage-
εsi(NA+ND) 2 BV = 2qN N Emax A D
1 N
Allen and Holberg - CMOS Analog Circuit Design
Page II.3-4
SUMMARY - CONTINUED
Current-Voltage Relationship vD iD = I sexpV - 1 t
Source Source/bulk n-channel, enhance- n-channel, enhancement, bulk at most ment, VBS ≠ 0 negative supply Drain Gate
Drain Bulk Gate
Source Source/bulk p-channel, enhance- p-channel, enhancement, bulk at most ment, VBS ≠ 0 positive supply
Polarity of vBULK Most negative Most negative Most positive Most positive
Allen and Holberg - CMOS Analog Circuit Design
II.5-1
II.5 - PASSIVE COMPONENTS CAPACITORS
εoxA C = tox Polysilicon-Oxide-Channel Capacitor and Polysilicon-Oxide-Polysilicon Capacitor Metal SiO2
Polysilicon top plate
Gate SiO2
FOX
FOX p+ bottom-plate implant
p- substrate (a)
Polysilicon top plate Polysilicon bottom plate
FOX Inter-poly SiO 2 p- substrate (b) Figure 2.4-1 MOS capacitors. (a) Polysilicon-oxide-channel. (b) Polysilicon-oxide-polysilicon.
Allen and Holberg - CMOS Analog Circuit Design
II.5-2
Metal-Metal and Metal-Metal-Poly Capacitors
M3
M2 B
T
M1
Poly
M1
M2 Poly
T
M2
T
M3
M2
B
T
M1
M1
B
B T
B
Figure 2.4-2 Various ways to implement capacitors using available interconnect layers. M1, M2, and M3 represent the first, second, and third metal layers respectively.
Top plate parasitic
C desired
Bottom plate parasitic
Figure 2.4-3 A model for the integrated capacitors showing top and bottom plate parasitics.
Allen and Holberg - CMOS Analog Circuit Design PROPER LAYOUT OF CAPACITORS
• Use “unit” capacitors • Use “common centroid” Want A=2*B Case (a) fails Case (b) succeeds!
(a)
A1
A2
B
(b)
A1
B
A2
x1
x2
x3
y
Components placed in the presence of a gradient, (a) without common- centroid layout and (b) with common-centroid layout.
Figure 2.6-2
II.5-3
Allen and Holberg - CMOS Analog Circuit Design NON-UNIFORM UNDERCUTTING EFFECTS
Random edge distortion
Large-scale distortion
Corner-rounding distortion
II.5-4
Allen and Holberg - CMOS Analog Circuit Design
II.5-5
VICINITY EFFECT
A
A
B
B
C
C
Figure 2.6-1 (a)Illustration of how matching of A and B is disturbed by the presence of C. (b) Improved matching achieved by matching surroundings surroundings of A and B
Allen and Holberg - CMOS Analog Circuit Design IMPROVED LAYOUT METHODS FOR CAPACITORS
Corner clipping: Clip corners
Street-effect compensation:
II.5-6
Allen and Holberg - CMOS Analog Circuit Design
II.5-7
ERRORS IN CAPACITOR RATIOS
Let C 1 be defined as C 1 = C 1A + C 1P
and C 2 be defined as C 2 = C 2A + C 2P
CXA is the bottom-plate capacitance capacitance CXP is the fringe (peripheral) capacitance capacitance CXA >> CXP The ratio of C 2 to C 1 can be expressed as C2P 1+ C 2 C 2A C 2A C2A 2A+C 2P 2P 2A = = C 1 C 1A C 1A C1P 1A+C 1P 1P 1A 1+ C 1A
C
C
C
2A 2P 2P 1P 1P ≅ C 2A 1+C -C - 1A 1A
C
2A 2A
C
1A 1A
(C 1P 1P)(C 2P 2P) C 1A 1AC 2A 2A
C
2A 2P 2P 1P 1P 1+C -C ≅ C 2A 1A 1A
2A 2A
1A 1A
Thus best matching is achieved when the area to periphery ratio remains constant.
Allen and Holberg - CMOS Analog Circuit Design
II.5-8
CAPACITOR PARASITICS
Top Plate
Top plate parasitic
Desired Capacitor
Bottom Plate
Bottom plate parasitic
Parasitic is dependent upon how the capacitor is constructed. Typical capacitor performance (0.8 µ m Technology)
Capacitor Type Poly/poly capacitor MOS MO S capacitor MOM MO M capacitor
Range nge of of Va Values ues 0.8-1.0 fF/ µ µm 2
Relative Temperature Accuracy Coefficient 0 .0 5 % 50 ppm/ °C
Component Rang Rangee of of Val Value uess Matc atching hing Temperature Type Accuracy Coefficient Poly/poly 0 .0 5 % 0.8-1.0 fF/ µ 50 ppm/ °C µm 2 capacitor MOS MO S 0 .0 5 % 2.2-2.5 fF/ µ 50 ppm/ °C µm 2 capacitor MOM MO M 1.5 % 0.02-0.03 fF/ µ µm 2 capacitor Diffused 0.4% 20-150 Ω /sq. 1500 ppm/ °C resistor Polysilicide R 2-15 Ω /sq. Poly resistor 0.4% 20-40 Ω /sq. 1500 ppm/ °C N-well 0.4% 1-2k Ω /sq. 8000 ppm/ °C resistor
Voltage Coefficient 50ppm/V
Absolute Accuracy ±10%
50ppm/V
±10% ±10%
200ppm/V
±35%
100ppm/V 10k ppm/V
±30% ±40%
Allen and Holberg - CMOS Analog Circuit Design
II.5-11
BIPOLARS IN CMOS TECHNOLOGY Metal
Emitter (p+)
Base (n+)
FOX
FOX
FOX W B
n- well Collector (p- substrate)
Figure 2.5-1 Substrate BJT available from a bulk CMOS process. process.
Depletion regions p Emitter
n Base
p Collector
Carrier concentration
p pE
nn( x x)
p pC
pn(0) N A
n pE (0)
N D
N A pn( x x)
n pE
p pC
pn(w B) x=0
x=w B
Figure 2.5-2 Minority carrier concentrations for a bipolar bipolar junction transistor.
x
Allen and Holberg - CMOS Analog Circuit Design
II.6-1
II.6 - LATCHUP
S
G
D=B
S
G
Well tie
Substrate tie p+
FOX n+
n+
FOX
p+
Q2
Q1
p-substrate
V DD
D=A
p+ FOX
n+
R N -
n-well
RP-
(a) V DD
R N -
Q2 A
Q1 B
RP-
(b) Figure 2.5-3 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS integrated circuits. (b) Equivalent circuit of the SCR formed formed from the parasitic bipolar transistors.
Allen and Holberg - CMOS Analog Circuit Design
II.6-2
PREVENTING LATCHUP p-channel transistor
n-channel transistor
n+ guard bars
p+ guard bars
V DD
V SS
FOX n-well p- substrate
Figure 2.5-4 Preventing latch-up using guard guard bars in an n-well technology
Active Area (AA) 2A. 2A. widt widthh ..................... .......... ....................... ....................... ....................... ....................... ................. ......44 Spacing to Well 2B. 2B. AA-n AA-n con conta tain ined ed in in n-We n-Well.......... ll........................ ............................ .....................1 .......1 2C. 2C. AA-n AA-n exte extern rnal al to n-We n-Well.......... ll........................ ............................ ..................... ....... 10 2D. AA-p AA-p cont contai aine nedd in n-We n-Well.......... ll........................ ............................ .....................3 .......3 2E. AA-p AA-p exte extern rnal al to n-We n-Well........... ll........................ ........................... .......................4 .........4 Spacing to other AA (inside or outside well) 2F. AA to AA (p or n)........................ n)..................................... ........................... ..................3 ....3
3.
Polysi Polysili lico conn Gate Gate (Cap (Capaci acito torr bot botto tom m pla plate te)) 3A. widt width..................... h................................. ......................... .......................... ......................... ...............2 ...2 3B. 3B. spac spacin ingg .......................... ....................................... ......................... ......................... ....................3 .......3 3C. 3C. spac spacin ingg of poly polysil silic icon on to AA (ov (over er fie field ld).............. )....................... ..........1 .1 3D. exte extensi nsion on of of gate gate beyo beyond nd AA AA (trans (transist istor or widt widthh dir.) dir.) ........2 ...... ..2 3E. spaci spacing ng of of gate gate to to edge edge of of AA (tra (transi nsisto storr leng length th dir. dir.)) ......4 ..... .4
4. Poly Polysi sili lico conn Cap Capac acit itor or top top pla plate te 4A. widt width..................... h................................. ......................... .......................... ......................... ...............2 ...2 4B. 4B. spac spacin ingg .......................... ....................................... ......................... ......................... ....................2 .......2 4C. spacin spacingg to to insi inside de of polysi polysilic licon on gate gate (bott (bottom om plate)... plate)...... ...... ....2 .2 5.
Contacts
Allen and Holberg - CMOS Analog Circuit Design
II.8-2
5A. 5A. size ........ ............ ........ ........ ........ ........ ........ ......... ......... ........ ........ ........ ......... ......... ........ ........ ...... 2x2 5B. 5B. spac spacin ingg .......................... ...................................... ......................... .......................... ....................4 .......4 5C. 5C. spac spacin ingg to pol polys ysil ilic icon on gat gatee ............................ .......................................... ................2 ..2 5D. spac spacin ingg poly polysi sili lico conn cont contac actt to AA .................... .......... .................... .............. ....22 5E. meta metall over overla lapp of cont contac actt .......................... ........................................ .....................1 .......1 5F. AA over overla lapp of cont contac actt ........................... ........................................ .......................2 ..........2 5G. poly polysil silic icon on overl overlap ap of cont contac act................. t........................... ..................... .............2 ..2 5H. capa capaci cito torr top top plat platee ove overla rlapp of of con conta tact......... ct................... ................... ..........2 .2 6.
Via 7A. 7A. size ........ ............ ........ ........ ........ ........ ........ ......... ......... ........ ........ ........ ......... ......... ........ ........ ...... 3x3 7B. 7B. spac spacin ingg .......................... ...................................... ......................... .......................... ....................4 .......4 7C. 7C. encl enclos osur uree by Met Metal al-1............ -1......................... .......................... .......................... ..............1 .1 7D. encl enclos osur uree by Meta Metall-2.................. 2................................ ........................... ....................1 .......1
8.
Metal-2 8A. widt width..................... h................................. ......................... .......................... ......................... ...............4 ...4 8B. 8B. spac spacin ingg .......................... ....................................... ......................... ......................... ....................3 .......3 Bonding Pad 8C. 8C. spac spacin ingg to AA............ AA......................... .......................... .......................... ...................... ......... 24 8D. spac spacin ingg to to meta metall cir circu cuit itry ry ........................... ......................................... .................. 24 8E. spac spacin ingg to poly polysi sili lico conn gat gatee ............................ ..........................................24 ..............24
Allen and Holberg - CMOS Analog Circuit Design
II.8-3
9. Pass Passiv ivat atio ionn Ope Openning ing (Pa (Pad) d) 9A. bond bondin ingg-pa padd open openin ingg ............................ ..............................10 ..1000 µ m x 100 µ m 9B. 9B. bond bondin ingg-pa padd open openin ingg encl enclos osed ed by Meta Metall-22 .................. ......... ............. ....88 9C. 9C. bond bondin ingg-pa padd ope openi ning ng to pad pad ope openi ning ng spac spacee ................. ........ ............. 40 Note: For a P-Well process, exchange p and n in all instances.
Allen and Holberg - CMOS Analog Circuit Design
II.8-4
1B
1A
2E 2B 2A 2F
2C
2D
3C
3A
3E
3D
3B
Figure 2.6-8(a)
Illustration of the design rules 1-3 of Table 2.6-1.
Allen and Holberg - CMOS Analog Circuit Design
4C
II.8-5
4B
4A
5C 5A 5B
5D
5E
5F
Figure 2.6-8(b)
5G
5H
Illustration of the design rules 4-5 of Table 2.6-1.
Allen and Holberg - CMOS Analog Circuit Design
II.8-6
7A
7B 6B
7C
6A 7D
8A 8B
9B
9A
9C
N-WELL
N-AA
P-AA
POLYSILICON CAPACITOR
POLYSILICON GATE
METAL-1
METAL-2
PASSIVATION
Figure 2.6-8(c)
CONTACT
Illustration of the design rules 6-9 of Table 2.6-1.
VIA
Allen and Holberg - CMOS Analog Circuit Design
II.8-7
Transistor Layout Metal FOX
Active area drain/source
FOX
Polysilicon gate L
Contact Cut W
Active area drain/source Metal 1
Example layout of an MOS transistor showing top view and side view at the cut line indicated.
Figure 2.6-3
Allen and Holberg - CMOS Analog Circuit Design
II.8-8
SYMMETRIC VERSUS PHOTOLITHOGRAPHIC INVARIANT
(a)
(b)
Example layout of MOS transistors using (a) mirror mirror symmetry, and (b) photolithographic invariance.
Figure 2.6-4
PLI IS BETTER
Allen and Holberg - CMOS Analog Circuit Design
II.8-9
Resistor Layout Metal FOX
FOX Substrate Active area (diffusion)
Contact
Active area or Polysilicon
W
Cut
L
Metal 1
(a) Diffusion or polysilicon resistor
Metal FOX
FOX
FOX
Substrate Active area (diffusion) Active area
Well diffusion
Well diffusion
W
Contact
Cut
L
Metal 1
(b) Well resistor
Example layout of (a) diffusion or polysilicon resistor and (b) Well resistor along with their respective side views at the cut line indicated.
Figure 2.6-5
Allen and Holberg - CMOS Analog Circuit Design
II.8-10
Capacitor Layout Polysilicon 2
Metal
FOX Substrate Polysilicon gate
Polysilicon gate Polysilicon 2
Cut
Metal 1
(a)
Metal 3
Metal 2
Metal 1
FOX Substrate
Metal 3
Metal 2
Metal 1
Metal 3 Via 2
Via 2 Metal 2
Cut
Via 1
Metal 1
Allen and Holberg - CMOS Analog Circuit Design
III. CMOS MODELS Contents
III.1 III.1 Simp Simple le MOS MOS lar large ge-s -sig igna nall mode modell Strong inversion Weak inversion III. III.22 Capa Capaci cita tanc ncee mod model el III. III.33 Smal Smalll-si sign gnal al MOS MOS mode modell III. III.44 SP SPIC ICE E Lev Level el-3 -3 mode modell Perspective
SYSTEMS
Chapter 10 D/A and A/D Converters
Chapter 7 CMOS Comparators
Chapter 11 Analog Systems
Chapter 8 Simple CMOS OP AMPS
Chapter 9 High Performance OTA's
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
DEVICES
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
Page III.0-1
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-1
III.1 - MODELING OF CMOS ANALOG CIRCUITS Objective
1. Hand calculations and design of of analog CMOS circuits. circuits. 2. Efficiently and accurately simulate simulate analog CMOS circuits. Large Signal Model
The large signal model is nonlinear and is used to solve for the dc values of the device currents given the device voltages. The large signal models for SPICE: Basic drain current models 1. Level 1 - Shichman-Hodges (V T, K', γ , λ, φ, and NSUB) 2. Level 2 - Geometry-based analytical model. Takes into into account account second-order effects (varying channel charge, short-channel, weak inversion, varying surface mobility, etc.) 3. Level 3 - Semi-empirical short-channel model model 4. Level 4 - BSIM model. Based on on automatically automatically generated parameters from a process characterization. Good weak-strong inversion transition. Basic model auxilliary parameters include capacitance [Meyer and Ward-Dutton (charge-conservative)], bulk resistances, depletion regions, etc.. Small Signal Model
Based on the linearization of any of the above large signal models. Simulator Software
SPICE2 - Generic SPICE available from UC Berkeley (FORTRAN) SPICE3 - Generic SPICE available from UC Berkeley (C) *SPICE*- Every other SPICE simulator!
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-2
Transconductance Characteristics of NMOS when V DS = 0.1V
Derivation• Let the charge per unit area in in the channel inversion layer be QI(y) = C ox[vGS − v(y) − V T] (coulombs/cm2) • Define sheet conductivity conductivity of the inversion layer per per square as 1 cm2 coulombs amps σS = µoQI(y) v·s cm2 = volt = Ω /sq. • Ohm's Law for current in a sheet is iD dv JS = W = σSE y = σS dy . Rewriting Ohm's Law gives, iD iDdy dv = σ W dy = µ Q (y)W S o I where dv is the voltage drop along the channel in the direction of y. Rewriting as iD dy = WµoQI(y)dv and integrating along the channel for 0 to L gives L
After integrating and evaluating the limits 2 vDS WµoCox iD= L (vGS−VT)vDS − 2
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-7
ILLUSTRATION OF THE SAH EQUATION Plotting the Sah equation as i D vs. vDS results in iD vDS = vGS - VT Non-Sat Region
Saturation Region
Increasing values of vGS vDS
Define v DS(sat) = vGS − VT Regions of Operation of the MOS Transistor 1.) Cutoff Region: iD = 0, vGS − VT < 0 (Ignores subthreshold currents) 2.) Non-saturation Region
µCoxW
iD = 2L
2(vGS −VT)−v DS vDS , 0 < v DS < vGS − VT
3.) Saturation Region
µCoxW
iD = 2L
2 (vGS −VT) , 0 < v GS − VT < vDS
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-8
SAH MODEL ADJUSTMENT TO INCLUDE EFFECTS OF VDS ON VT From the previous derivation: vDS
Assume that the threshld voltage varies across the channel in the following way: VT(y) = VT + ∆v(y) where V T is the value of the threshold voltage at the source end of the channel. Integrating the above gives, WµoCox v2(y)vDS iD = L (vGS−VT)v(y)−(1+∆) 2 0 or WµoCox v2DS iD = L (vGS−VT)vDS −(1+∆) 2 To find v DS(sat), set the derivative of i D with respect to v DS equal to zero and solve for v DS = vDS(sat) to get, vGS −VT vDS(sat) = 1+∆ Therefore, in the saturation region, the drain current is WµoCox 2 iD = 2(1+ ∆)L vGS −VT
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-9
EFFECTS OF BACK GATE (BULK-SOURCE) Bulk-Source (v BS) influence on the transconductance characteristicsiD
Decreasing values of bulk-source voltage VBS = 0 vDS ≥ vGS - VT
VT0
VT1
VT2
VT3
vGS
In general, the simple model incorporates the bulk effect into V T by the following empirically developed equationVT(V ) =V T0 + γ 2|φf |+|v |+|vBS| − γ 2|φf || BS
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-10
EFFECTS OF THE BACK GATE - CONTINUED IllustrationVSB0 = 0V:
VSB0=0V +
Gate VGS>VT
Source
Bulk
p-
Poly
n+
p+
Drain VDS>0 n+
Substrate/Bulk
VSB1>0V: VSB1 +
Gate VGS>VT
Source
Bulk
n+
Substrate/Bulk
VSB2 > VSB1: -
VSB2
Gate VGS>VT
+
Source
Bulk p+ p-
Poly
n+
p+ p-
Drain VDS>0
Substrate/Bulk
Drain VDS>0
Poly
n+
n+
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-11
SAH MODEL INCLUDING CHANNEL LENGTH MODULATION N-channel reference convention:
D iD
G
+
vGS
+ +
B vDS
vBS - -S
Non-saturationWµoCox vDS2 iD = L (vGS −VT)vDS − 2 SaturationWµoCox vDS(sat)2 iD = L (vGS −VT)vDS(sat)− 2 (1 + λvDS) WµoCox 2 = 2L (vGS − VT) (1 + λvDS) where:
µo = zero field mobility (cm 2 /volt·sec) Cox = gate oxide capacitance per unit area (F/cm (F /cm 2)
γ = bulk threshold parameter (volts 1/2) 2|φf | = strong inversion surface potential (volts) When solving for p-channel devices, negate all voltages and use the nchannel model with p-channel parameters parameters and negate the current. Also negate VT0 of the p device.
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-12
OUTPUT CHARACTERISTICS OF THE MOS TRANSISTOR
iD / ID0 1.0
vDS = vGS - VT Non-Sat Region
0.75
Saturation Region Channel modulation effects
0.5 0.25 Cutoff Region 0
0
0 .5
1 .0
1 .5
Notation: W W ß = K' L = (µoCox) L Note:
Allen and Holberg - CMOS Analog Circuit Design GRAPHICAL INTERPRETATION OF
Page III.1-13
λ
Assume the MOS is transistor is saturated-
µCoxW
∴ iD = 2L (vGS − VT) 2(1 + λvDS) Define iD(0) = iD when vDS = 0V.
µCoxW
∴ iD(0) = 2L (vGS − VT)2 Now, iD = iD(0) [1+λvDS] = iD(0) + λiD(0) vDS or
1 1 vDS = λi (0) iD − λ D
Matching with y = mx + b gives vDS 1 1 λiD(0) iD iD(0) -1
λ
or
iD iD3(0) iD2(0) iD1(0) -1
λ
VGS3 VGS2 VGS1 vDS
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-14
SPICE LEVEL 1 MODEL PARAMETERS FOR A TYPICAL BULK CMOS PROCESS (0.8µm) Typical Parameter Value NMOS PMOS
Model Parameter
Parameter Description
VT0
ThresholdVoltage forVBS = 0V
0.75±0.15
−0.85±0.15
Volts
Transconductance Parameter
110±10%
50±10%
µA/V2
0. 4
0.5 7
V
0.04 (L=1 µ m) m) 0.01 (L=2 µ m) m)
0.05 (L = 1 µ m) m) 0.01 (L = 2 µ m) m)
V-1
0. 7
0 .8
Volts
K'
Units
(sat.)
γ
Bulk Threshold Parameter
λ
Channel Length Modulation Parameter
φ = 2φF
Surfa urfacce pot poteenti ntial at stro strong ng inversion
These values are based on a 0.8 µm silicon-gate bulk CMOS n-well process.
Allen and Holberg - CMOS Analog Circuit Design
Page III.1-15
WEAK INVERSION MODEL (Simple)
i D (nA)
Weak inversion region
1000.0
i D
100.0
Strong inversion region
10.0 1.0 0
V T V ON
vGS
0
V T V ON
vGS
This model is appropriate for hand calculations but it does not accommodate a smooth transition into the strong-inversion region. qvGS W exp i D ≅ I L DO nkT
The transition point where this relationship is valid occurs at approximately vgs < V T + n
kT q
Weak-Moderate-Strong Inversion Approximation Moderate inversion region
i D (nA)
Weak inversion region
1000.0 100.0
Strong inversion region
10.0 1.0 0
vGS
Allen and Holberg - CMOS Analog Circuit Design
Page III.2-1
INTRINSIC CAPACITORS OF THE MOSFET
Types of MOS Capacitors 1. Depletion capacitance ( C BD and C BS) 2. Gate capacitances ( C GS GS, C GD GD, and C GB GB)
SiO2
Gate Source C 1
Drain C 2
C 3
C 4 C BD
C BS
Bulk
Figure 3.2-4
Large-signal, charge-storage capacitors of the MOS device.
Allen and Holberg - CMOS Analog Circuit Design
Page III.2-2
Depletion Capacitors Bulk-drain pn junction -
CBD
Capacitance approximation for strong forward bias
CBD0xArea (FC).φ B Reverse Bias C BD =
C A BD BD0 A
v BD MJ 1 − B φ B
Forward φ B Bias
and C BS =
VBD
C A BS BS0 A
v BS MJ 1 − B φ B
where, A BD ( A A BS) = area of the bulk-drain (bulk-source)
For strong forward bias, approximate the behavior by the tangent to the above C BD or C BS curve at v BD or v BS equal to ( FC )· )·φ B B. v BD 1 −(1+ MJ )FC + +FC φ , v BD > ( FC )· )·φ B C BD = B (1+FC )1+ MJ B C BD0 A BD
and
C BD =
v BS 1 (1+ ) + + )·φ B − MJ FC FC , v > (FC )· B (1+FC )1+ MJ φ B BS C BS0 A BS
where AX = area of the source ( X = S) or drain ( X = D) PX = perimeter of the source ( X = S) or drain ( X = D) CJSW = zero-bias, bulk-source/drain sidewall capacitance MJSW = bulk-source/drain sidewall grading coefficient
Allen and Holberg - CMOS Analog Circuit Design
Page III.2-4
Overlap Capacitance Mask L
Oxide encroachment
Actual L ( L Leff )
Mask W
LD
Actual W (W eff )
Gate
Source-gate overlap capacitance C GS (C 1) FOX
Drain-gate overlap capacitance C GD (C 3)
Gate
Source
Drain Bulk
C 1 = C 3 ≅ ( LD LD)(W eff ) C ox = (CGXO)W eff
FOX
Allen and Holberg - CMOS Analog Circuit Design
Page III.2-5
Gate to Bulk Overlap Capacitance Overlap
FOX
C 5
Overlap
Gate
C 5
Source/Drain
FOX
Bulk
On a per-transistor basis, this is generally quite small Channel Capacitance C 2 = W eff ( L L
− 2 LD)C ox = W eff ( L Leff ) C ox
Drain and source portions depend upon operating condition of transistor.
Allen and Holberg - CMOS Analog Circuit Design
Page III.2-6
MOSFET Gate Capacitance Summary:
Capacitance C 2 + 2C 5 C GS
C 1 + 2_3 C 2
C GS, C GD
C 1 + 1_2 C 2
C GS, C GD
C 1, C 3
v DS = constant v BS = 0
C GD C GB
2C 5 0 Off
Saturation V T
iD
v DS +V T
Non- Saturation
vGS
v DS = vGS - VT
Non-Sat Region
Saturation Region Cutoff Region 0 0
0.5
1.0
vDS = constant
1.5
2.0
2.5
Allen and Holberg - CMOS Analog Circuit Design C GS, C GD, and C GB
Off C GB
)( L = C 2 + 2 C 5 = C ox(W eff )( Leff ) + CGBO( L Leff )
C GS = C 1 ≅ C ox( LD LD)(W eff ) = CGSO(W eff ) C GD = C 3 ≅ C ox( LD LD)(W eff ) = CGDO(W eff ) Saturation C GB
= 2C 5 = CGBO ( L Leff )
C GS = C 1 +
(2/3)C 2 = C ox( LD )(W eff ) LD + 0.67 Leff )(
)( L = CGSO(W eff ) + 0.67C ox(W eff )( Leff ) C GD = C 3 ≅ C ox( LD LD)(W eff ) = CGDO(W eff ) Nonsaturated C GB
= 2C 5 = CGBO ( L Leff )
C GS = C 1 +
0.5C 2 = C ox( LD )(W eff ) LD + 0.5 Leff )(
= (CGSO + 0.5C ox Leff )W eff C GD = C 3 +
0.5C 2 = C ox( LD )(W eff ) LD + 0.5 Leff )(
= (CGDO + 0.5C ox Leff )W eff
Page III.2-7
Allen and Holberg - CMOS Analog Circuit Design
Page III.3-1
Small-Signal Model for the MOS Transistor D
r D C bd
inrD C gd
G
gbd
gds
gmvgs
B
inD C gs
gmbsvbs
gbs
inrS
C gb
C bs
r S
S
Figure 3.3-1
Small-signal model of the MOS transistor.
gbd =
∂ I BD (at the quiescent point) ≅ 0 ∂V BD
gbs =
∂ I BS (at the quiescent point) ≅ 0 ∂V BS
and
The channel conductances, gm , gmbs , and gds are defined as
−∂ I D ∂ I D ∂V T = − ∂V SB ∂V T ∂V SB
Noting that
∂ I D −∂ I D , we get = ∂V T ∂V GS
gmbs = gm
gds = go =
γ
2(2|φ F | + V SB)1/2
I D λ V 1+ λ V DS
= η gm
≅ I D λ
Relationships of the Small Signal Model Parameters upon the DC Values of Voltage and Current in the Saturation Region.
Small Signal Model Parameters gm
DC Current ≅ (2K' I DW/L)1/2
gmbs gds
≅
λ I D
DC Current and Voltage _ γ (2 (2 I Dβ )1/2 2(2|φ F |+ V SB)1/2
DC Voltage ≅ 2K'W (V GS -V T ) L γ ( β (V GS−V T )) 2(2|φ F |+V SB)1/2
Allen and Holberg - CMOS Analog Circuit Design
Page III.3-3
Nonsatu ons aturat ration ion region regio n gm =
∂ I d d = β V DS ∂V GS
gmbs
=
V DS ∂ I D βγ V = ∂V BS 2(2|φ F| +VSB)1/2
and gds = β (V GS − V T − V DS)
Relationships of the Small-Signal Model Parameters upon the DC Values of Voltage and Current in the Nonsaturation Region. Small Signal DC Voltage and/or Current Model Parameters Dependence = β V DS gm β γ β γ V V gmbs DS 2(2|φ F |+ V SB)1/2
= β (V GS −V T −V DS)
gds
Noise 2
i nrD =
2
i nrS =
4kT ∆ f r D
(A2)
4kT ∆ f r S
(A2)
and 2
i nD =
kT g gm(1+η) (KF)I 8kT D + ∆ f 2 3 fC L ox
(A2)
Allen and Holberg - CMOS Analog Circuit Design
Page III.4-1
SPICE Level 3 Model The large-signal model of the MOS device previously discussed neglects many important second-order effects. effects. Most of these second-order effects are due to narrow or short channel dimensions (less than about 3µ m). m). We shall also consider the effects of temperature upon the parameters of the MOS large signal model. We first consider second-order effects due to small geometries. When vGS is greater than V T , the drain current for a small device can be given as Drain Current
1+ f b i DS = BETA vGS − V T − 2 v DE ⋅ v DE W eff
BETA = KP L L eff = L
eff
= µ eff COX
W eff Leff
− 2(LD)
(1)
(2) (3)
W eff = W − 2(WD)
(4)
v DE = min(v DS , v DS (sat))
(5)
f b = f n +
GAMMA⋅ f s 4(PHI + vSB)1/2
(6)
Note that PHI is the SPICE model term for the quantity 2 φ f . Also be aware that that PHI is always positive in SPICE regardless of the transistor type (p- or n-channel). f n =
DELTA πε si si W eff 2⋅COX
21/2 LD+ wc wp LD f s = 1 − x 1− − x L eff x wp + j j j
x j
wp = xd (PHI + vSB )1/2
2⋅ε si 1/2 xd = q ⋅ NSUB
(7)
(8)
(9)
(10)
Allen and Holberg - CMOS Analog Circuit Design 2 wp wp wc = x j k 1 +k 2 − k 3 x j x j
Page III.4-2
(11)
k 1 = 0.0631353 , k 2 = 0.08013292 , k 3 = 0.01110777
Thresh Thr eshold old V oltage olta ge
ETA⋅8.15-22 v DS + GAMMA ⋅ f s( PHI + vSB)1/2 + f n( PHI + vSB) V T = V bi − 3 C ox Leff vbi = v fb + PHI
(12)
(13)
or vbi = VTO
− GAMMA ⋅
PHI
(14)
Saturation Voltage vgs − V T
vsat =
v DS(sat) = vsat + vC −
vC
=
(15)
1+ f b
2 vsat
1/2
+ 2 vC
VMAX⋅ L eff
(16)
(17)
µ s
If VMAX is not given, then v DS(sat) = vsat Effective Mobility
µ s =
U0 1+ THETA(vGS −V T )
µ eff =
µ s 1+
v DE
when VMAX > 0; otherwise µ eff = µ s
vC
Channel-Length Modulation
When VMAX = 0
when VMAX = 0
(18)
(19)
Allen and Holberg - CMOS Analog Circuit Design
Page III.4-3
1/2 ∆ L = xd KAPPA (v DS − v DS(sat))
(20)
when VMAX > 0
∆ L = −
⋅
ep xd2 2
1/2
ep ⋅xd2 2 2 + 2 +KAPPA ⋅ xd ⋅ (v DS − v DS(sat))
(21)
where ep =
i DS =
vC (vC +v DS(sat)) L eff v DS(sat) i DS
1− ∆ L
(22)
(21)
Weak Inversion Model (Level 3)
In the SPICE Level 3 model, the transition point from the region of strong inversion to the weak inversion characteristic of the MOS device is designated as von and is greater than V T . von is given by von = V T + fast
(1)
where 1/2 f (PHI+v ) n q ⋅NFS GAMMA⋅f s(PHI+vSB) + f kT SB fast = 1+ + q COX 2(PHI+vSB)
(2)
N F S is a parameter used in the evaluation of v o n and can be extracted from measurements. The drain current in the weak inversion region, vGS less than von , is given as
i DS DS =
vGS-von fast i DS (von , v DE , vSB) e
(3)
where i DS is given as (from Eq. (1), Sec. 3.4 with vGS replaced with von)
1+ f b i DS = BETA von − V T − 2 v DE ⋅ v DE
(4)
Allen and Holberg - CMOS Analog Circuit Design
Page III.4-4
Typical Model Parameters Suitable for SPICE Simulations Using Level-3 Model (Extended Model). These Values Are Based upon a 0.8µm Si-Gate Bulk CMOS nWell Process
Parameter Parameter Symbol Description VTO Threshold UO mobility DELT DELTA A Narr Narrowow-wi widt dthh thre thresh shol oldd adjust factor ETA Static-feedback threshold adjust factor KAPP KAPPA A Satu Satura rati tion on fie field ld fac facto torr in channel-length modulation THETA Mobility degradation factor NSUB Substrate do doping TOX Oxide thickness XJ Mettallurgical ju junction depth WD Delta width LD Lateral diffusion NFS Parameter for weak inversion modeling CGSO CGDO CGBO CJ CJSW MJ MJSW NFS Parameter for weak inversion modeling
Typical Parameter Value N-Channel P-Channel Units V 0.7 ± 0.15 −0.7 ± 0.15 660 210 cm2 /V-s 2. 4 1 .2 5 0. 1
Temperature Dependence The temperature-dependent variables variables in the models developed so far include the: Fermi potential, PHI, EG, bulk junction potential of the source-bulk and drain-bulk junctions, PB, the reverse currents of the pn junctions, I S, and the dependence of mobility upon temperature. The temperature dependence of most of these variables is found in the equations given previously or from well-known expressions. The dependence of mobility upon temperature is given as T BEX UO(T ) = UO(T 0) T 0
where BEX is the temperature exponent for mobility and is typically -1.5. vtherm(T ) =
T T 1 ⋅ T ⋅ expEG⋅ T − 1 ⋅ 0 0 2⋅ vtherm(T 0)
For drain and source junction diodes, the following relationships apply. EG(T 0) T T EG(T ) PB(T ) = PB ⋅ − vtherm(T ) 3⋅ln + − T 0 T 0 vtherm(T 0) vtherm(T ) I S(T ) =
I S(T 0)
N
T EG(T 0) EG(T ) ⋅ exp v + − 3⋅ln T 0 therm(T 0) vtherm(T )
where N is diode emission coefficient. The nominal temperature, T 0, is 300 K.
Allen and Holberg - CMOS Analog Circuit Design
Page III.3-1
SPICE Simulation of MOS Circuits
Minimum required terms for a transistor instance follows: M1 3 6 7 0 NCH W=100U L=1U “M,” tells SPICE that the instance is an MOS transistor (just like “R” tells SPICE that an instance is a resistor). The “1” makes this instance unique (different from M2, M99, etc.) The four numbers following”M1” specify the nets (or nodes) to which the drain, gate, source, and substrate (bulk) are connected. These nets have a specific order as indicated below:
M ... Following the net numbers, is the model name governing the character of the particular instance. In the example given above, the model name is “NCH.” There must be a model description of “NCH.” The transistor width and length are specified for the instance by the “W=100U” and “L=1U” expressions. The default units for width and length are meters so the “U” following the number 100 is a multiplier of 10 -6. [Recall that the following following multipliers multipliers can be used in SPICE: M, U, N, P, F, for 10 -3, 10-6, 10-9, 10-12 , 10 -15 , respectively.] Additional information information can be specified specified for each instance. instance. Some of these are Drain area and periphery (AD and PD) ← calc depl cap and leakage Source area and periphery (AS and PS) ← calc depl cap and leakage Drain and source resistance in squares (NRD and NRS) Multiplier designating how many devices are in parallel (M) Initial conditions (for initial transient analysis) The number of squares of resistance in the drain and source (NRD and NRS) are used to calculate the drain and source resistance for the transistor.
Allen and Holberg - CMOS Analog Circuit Design
Page III.3-2
Geometric Multiplier: M
To apply the “unit-matching” principle, use the geometric multiplier feature rather than scale W/L. This: M1 3 2 1 0 NCH W=20U L=1U
is not the same as this: M1 3 2 1 0 NCH W=10U L=1U M=2
The following dual instantiation is equivalent to using a multiplier M1A 3 2 1 0 NCH W=10U L=1U M1B 3 2 1 0 NCH W=10U L=1U
A SPICE simulation file for an MOS circuit is incomplete without a description of the model to be used to characterize the MOS transistors used in the circuit. A model is described by placing placing a line in the simulation simulation file using the following format. .MODEL
MODEL NAME e.g., “NCH” MODEL TYPE either “PMOS” “PMOS” or “NMOS.” MODEL PARAMETERS : LEVEL=1 VTO=1 KP=50U GAMMA=0.5 LAMBDA=0.01
SPICE can calculate what you do not specify You must specify the following • surface state density, NSS, in cm -2 • oxide thickness, TOX, in meters • surface mobility, UO, in cm 2 /V-s, • substrate doping, NSUB, in cm -3 The equations used to calculate the electrical parameters are 1/2 (2q ⋅ ε si q(NSS) si ⋅NSUB⋅ PHI) + + PHI VTO = φ MS − (ε ox /TOX)
KP = UO
(ε ox /TOX)
ε ox ox TOX
GAMMA =
1/2 (2q ⋅ ε si si ⋅NSUB)
(ε ox /TOX)
and PHI = 2φ F =
2kT NSUB ln q ni
LAMBDA is not calculated from the process parameters for the LEVEL 1 model.
Allen and Holberg - CMOS Analog Circuit Design
Page III.3-4
Other parameters:
IS: Reverse current of the the drain-bulk or source-bulk junctions junctions in Amps JS: Reverse-current density in A/m 2 JS requires the specification of AS and AD on the model line. If IS is specified, it overrides JS. The default value of IS is usually 10 -14 A. RD: Drain ohmic resistance in ohms RS: Source ohmic resistance in ohms RSH: Sheet resistance in ohms/square. RSH is overridden overridden if RD or RS are entered. To use RSH, the values of NRD and NRS must be entered on the model m odel line. The drain-bulk and source-bulk depletion capacitors CJ: Bulk bottom plate junction capacitance MJ: Bottom plate junction grading coefficient CJSW: Bulk sidewall junction capacitance MJSW: Sidewall junction grading coefficient If CJ is entered as a model parameter it overrides the calculation of CJ using NSUB, otherwise, CJ is calculated using NSUB. If CBD and CBS are entered, these values override CJ and NSUB calculations. In order for CJ to result in an actual circuit capacitance, the transistor instance must include AD and AS. In order for CJSW to result in an actual circuit capacitance capacitance,, the transistor instance must include PD and PS. CGSO CGSO:: CGDO:
Gate Gate-S -Sour ource ce over overla lapp capa capaci cita tanc ncee (at (at zero zero bias bias)) Gate Gate-D -Dra rain in overl overlap ap capa capaci cita tanc ncee (at (at zer zeroo bia bias) s)
AF: KF:
Flicker noise exponent Flicker noise coefficient
TPG: Indicates type of gate material relative relative to the substrate substrate TPG=1 > gate material is opposite of the substrate TPG=-1 > gate material is the same as the substrate TPG=0 > gate material is aluminum XQC: Channel charge flag and fraction fraction of channel charge charge attributed to the drain
Allen and Holberg - CMOS Analog Circuit Design
Page IV.0-1
IV. CMOS PROCESS CHARACTERIZATION Contents
IV.1 IV.2 IV.3 IV.4 IV.5
Measur Measuremen ementt of basi basicc MOS leve levell 1 parame parameter terss Charac Characteri terizat zation ion of the the extend extended ed MOS MOS model model Characterization other active components Characterization of resistance Characterization of capacitance
Organization Chapter 10 D/A and A/D Converters
Chapter 11 Analog Systems
SYSTEMS
Chapter 7 CMOS Comparators
Chapter 8 Simple CMOS Opamps
Chapter 9 High Performance Opamps
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
DEVICES
1
Allen and Holberg - CMOS Analog Circuit Design I.
Page IV.1-1
Characterization of the Simple Transistor Model
Determine V T 0(V SB = 0), K', γ , and λ. Terminology: K' S for the saturation region K' L for the nonsaturation region W eff ef f (vGS - V T ) 2 (1 + λ v DS ) i D = K' S 2 L ef f eff
( 1)
2 v W eff ef f DS ( v G S - V T ) v D S - i D = K' L 2 L eff ef f
(2)
V T T = V T 0
+ γ
2 | φ F |+ v S B -
2 | φ F |
( 3)
Assume that v DS is chosen such that the λ v DS << 1 vSB =0 -> V T = V T 0 . Therefore, Eq. (1) simplifies to W eff ef f (v GS - V T 0 )2 i D = K’ S 2 Leff
(4)
This equation can be manipulated algebraically to obtain the following K ' S W e f f 1/2 K ' S W ef f 1/2 vGS - V T 0 i D = 2 2 L L eff eff which has the form 1/2
(5)
y
= mx + b
y
= i D
(7)
x
= vG S
(8)
1/2
(6)
1
Allen and Holberg - CMOS Analog Circuit Design K ' S W e f f 1/2 m= 2 L eff ef f
Page IV.1-2 (9)
and K ' S W e f f 1/2 V T 0 b = − ef f 2 Leff
Plot
1/2
i D
1/2
versus vGS and measure slope. to get
(10) K' S
When i D = 0 the x intercept ( b') is V T 0.
2
Allen and Holberg - CMOS Analog Circuit Design
Page IV.1-3
Mobility degradation region
v DS
(i D )
> V DSAT
1/2
Weak inversion region
1/2
K S′ W eff m= 2 L eff
b ′ = V T 0
v GS
(a)
v DS
= 0 . 1 V
i D m=
K L′ W eff v L eff DS
vGS
(b) Figure B.1-1 (a) i D1/2 versus v GS plot used to determine V T 0 and K' S. (b) i D versus vGS plot to determine K' L.
Extract the parameter
K' L
for the nonsaturation region:
W eff W eff v D S ef f ef f (11) i D = K' L v DS v GS - K' L v DS V T + 2 L L ef f ef f eff eff Plot i D versus vGS as shown in Fig. B.1-1(b), the slope is seen to be
3
Allen and Holberg - CMOS Analog Circuit Design
Page IV.1-4
∆i D W eff ef f m= ∆vGS = K ' L Leff ef f v D S Knowing the slope, the term
K' L
is easily determined to be
L eff ef f 1 K' L = m W ef f v DS D S eff W eff , Leff , and v DS
(12)
(13)
must be known.
The approximate value µ o can be extracted from the value of K' L At this point, γ is unknown. Write Eq. (3) in the linear form where y
= V T
(14)
x
= 2| φ F |+ v S B − 2| φ F |
(15)
m
= γ
(16)
b
= V T 0
(17)
2|φ F| normally in the range of 0.6 to 0.7 volts. Determine V T at various values of vSB Plot V T versus x and measure the slope to extract γ Slope m, measured from the best fit line, is the parameter γ .
4
Allen and Holberg - CMOS Analog Circuit Design
( i D )
Page IV.1-5
1/2
V T 0
V T 1
V T 2
V T 3
v GS
Figure B.1-2 i D1/2 versus vGS plot at different vSB values to determine γ .
V SB = 3 V V SB = 2 V V T
V SB = 1 V
m = γ
V SB = 0 V
0.5
( vSB + 2 φ F )
0.5
− ( 2 φ F )
Figure B.1-3 Plot of VT versus f( vSB) to determine γ .
We still need to find λ , ∆ L, and ∆W . λ should be determined for all device lengths that might be used. Rewrite Eq. (1) is as i D
= i' D λ v DS + i' D
(18)
5
Allen and Holberg - CMOS Analog Circuit Design which is in the familiar linear form where y = i D (Eq. (1))
Page IV.1-6
( 19)
= v D S
(20)
m
= λ i' D
(21)
b
= i' D (Eq. (4) with λ = 0)
( 22)
x
Plot i D versus v DS , and measure the slope of the data in the saturation region, and divide that value by the y-intercept to get λ .
Saturation region Nonsaturation region i D i' D
m = λ i' D
v DS
Figure B.1-4 Plot of i D versus v DS to determine λ.
Calculating ∆L and ∆W. Consider two transistors, with the same widths but different lengths, operating in the nonsaturation region with the same v DS. The widths of the transistors are assumed to be very large so that W ≅ W eff . The large-signal model is given as v2 K' L W eff ef f DS ( ) (23) i D = v V v T 0 D S 2 L eff ef f G S 6
Allen and Holberg - CMOS Analog Circuit Design
Page IV.1-7
and
∂ I D K ' L W e f f V D S ∂V G S = gm = Leff ef f
(24)
The aspect ratios ( W / L) for the two transistors are W 1 L 1
(25)
+ ∆ L
and W 2 L 2
(26)
+ ∆ L
Implicit in Eqs. (25) and (26) is that ∆ L is assumed to be the same for both transistors. Combining Eq. (24) with Eqs. (25) and (26) gives gm1
K ' L W
= L + ∆ L 1
v D S
(27)
and K ' L W
(28) = L + ∆ L v D S 2 where W 1 = W 2 = W (and are assumed to equal the effective width). With gm2
further algebraic manipulation of Eqs. (27) and (28), one can show that, gm1 L 2 + ∆ L (29) = L - L g m 1 - g m 2 2 1
which further yields ( L 2 - L 1 ) g m 1 L 2 + ∆ L = L eff ef f = g - g m1 m2 L2 and L1 known gm1 and gm2 can be Similarly for W eff :
(30)
measured
( W 1 - W 2 ) g m 2 W 2 + ∆ W = W eff ef f = g m 1 - g m 2
(31)
Equation (31) is valid when two transistors have the same length but different widths.
7
Allen and Holberg - CMOS Analog Circuit Design
Page IV.1-8
One must be careful in determining ∆ L (or ∆W ) to make the lengths (or widths) sufficiently different in order to avoid the numerical error due to subtracting large numbers, and small enough that the transistor model chosen is still valid for both transistors.
8
Allen and Holberg - CMOS Analog Circuit Design II.
Page IV.3-1
Transistor Characterization for the Extended Model
Equations (1) and (2) represent a simplified version of the extended model for a relatively wide MOS transistor operating in the nonsaturation, stronginversion region with V SB = 0. i D
=
µ sC oxW L
(v G S - V T ) v D S
v2 DS - 2 + γ v DS
2| φ F |
2γ (1) where W and L are effective electrical equivalents (dropping the subscript, “eff”, for convenience).
[ ( v D S +2| φ F |) 1. 5 -(2| φ F |)] |) ] 1 . 5 − 3 [(
(UCRIT)ε si UEXP (2) µ s = µ o [ -(UTRA) -(UTRA) ] C o x v V v G S T T DS D S Eq. (2) holds when the denominator term in the brackets is less than unity. Otherwise, µ o = µ s. To develop a procedure for extracting µ o, consider the case where mobility degradation effects are not being experienced, i.e., µ s = µ o, Eq. (1) can be rewritten in general as i D
= µ o f (C ox , W , L , vGS , V T , v DS , γ , 2|φ F |)
( 3)
This equation is a linear function of vGS and is in the familiar form of
= mx + b where b = 0.
(4)
y
Plot i D versus the function, f (C (C ox , measure the slope = µ o.
W , L , vGS , V T , v DS , γ ,
2 |φ F|) and
• The data are limited to the nonsaturation region (small v DS). • The transistor must be in the strong-inversion region ( vGS > V T ). • The transistor must operate below the critical-mobility point. Keep vGS as low as possible without encroaching on the weak-inversion region of operation.
1
Allen and Holberg - CMOS Analog Circuit Design
Page IV.3-2
Region of variable mobility
i
D
Region of constant mobility
Weak-inversion region
v GS
Figure B.2-1 Plot of i D versus vGS in the nonsaturation region.
Once µ o is determined, there is ample information to determine UCRIT and UEXP. Consider Eqs. (1) and (2) rewritten and combined as follows. (5) i D = µ o[(UCRIT) f f 2]UEXP f 1 where 2 v C ox ox W DS + γ v ( ) f 1 = v V v T D S D S 2| φ F | GS 2 L
2γ
1 .5 -(2| φ |)] 1 . 5 (1) − 3 [( [ ( v DS +2| |) |) ] φ F F D S
and
2
Allen and Holberg - CMOS Analog Circuit Design f 2
ε s i
= [v - V -(UTRA) v ] C T DS D S ox GS
Page IV.3-3 (7)
The units of f 1 and f 2 are FV2 /cm2 and cm/V respectively. Notice that f 2 includes the parameter UTRA, which is an unknown. UTRA is disabled in most SPICE models. Equation (5) can be manipulated algebraically to yield i D log f = log( µ o) + UEXP[log(UCRIT)] + UEXP[log( f f 2)] (8) 1 This is in the familiar form of Eq. (4) with ( 9) x = log( f 2) i D y = log f 1
( 10)
= UEXP
( 11)
m
b = log( µ o) +
UEXP[log(UCRIT)]
( 12)
By plotting Eq. (8) and measuring the slope, UEXP can be determined. The y-intercept can be extracted from the plot and UCRIT can be determined by back calculation given UEXP, µ o, and the intercept, b.
3
Allen and Holberg - CMOS Analog Circuit Design III.
Page IV.4-1
Characterization of Substrate Bipolar
Parameters of interest are: β dc, and J S. For
v BE
>> kT/q,
v BE =
k T q
iC ln J A S E
(1)
and β dc A E is
=
i E i B
−1
( 2)
the cross-sectional area of the emitter-base junction of the BJT. i E = i B(β dc
+ 1)
( 3)
Plot i B as a function of i E and measure the slope to determine β dc. Once β dc is known, then Eq. (1) can be rearranged and modified as follows. k T i E β d c k T k T k T − ln ln( ln( α dci E ) − v BE = J S A E ) = q q q q 1+ β d c ln( J S A E ) Plotting ln[ i E β dc /(1 + β dc)] versus v BE results in a graph where m
= slope =
k T q
(5)
and k T Since the emitter area is known, J S can be determined directly. b = y-intercept
= − q ln( J J S A E )
( 6)
1
Allen and Holberg - CMOS Analog Circuit Design IV.
Page IV.5-1
Characterization of Resistive Components
• Resistors • Contact resistance Characterize the resistor geometry exactly as it will be implemented in a design. Because
• sheet resistance is not constant across the width of a resistor • the effects of bends result in inaccuracies • termination effects are not accurately predictable Figure B.5-1 illustrates a structure that can be used to determine sheet resistance, and geometry width variation (bias). Force a current into node A with node F grounded while measuring the voltage drops across BC (V n) and DE (V w), the resistors Rn and Rw can be determined as follows R n
=
V n I
(1)
=
V w I
(2)
R w
The sheet resistance can be determined from these to be W n -Bias RS = R n L n W w -Bias R S = R w L w where Rn = resistance of narrow resistor ( Ω )
Ω /square) Ln
(3)
= resistance of wide resistor ( Ω)
Rw RS
(3)
= sheet resistance of material (polysilicon, diffusion etc.
= drawn length of narrow resistor 1
Allen and Holberg - CMOS Analog Circuit Design Lw
= drawn length of wide resistor
W n
= drawn width of narrow resistor
W w
= drawn width of wide resistor
Page IV.5-2
Bias = difference between drawn width and actual device width Rw Rn A
W n
Ln
B
F
W w
Lw C
Figure B.5-1
D
E
Sheet resistance and bias monitor.
Solving equations (3) and (4) yields Bias =
W n - k W w 1- k
(5)
where k =
R w L n R n L w
(6)
and W n -Bias W w -Bias = R w RS = R n L n L w
(7)
2
Allen and Holberg - CMOS Analog Circuit Design
Page IV.5-3
Determining sheet resistance and contact resistance
10 squares
R A=220 Ω
20 squares
R B=420 Ω
Figure B.5-2
R A
= R1 + 2 Rc;
Two resistors used to determine RS and RC .
R 1 = N 1 R S
(8)
R2 = N 2 R S
(9)
and R B = R 2
+ 2 Rc;
N 1 is the number of squares for R1 RS is the sheet resistivity in Ω /square Rc is the contact resistance. R B - R A R S = N 2 - N 1
Back bias (volts) Figure B.5-4 N-well resistance as a function of back-bias voltage
4
Allen and Holberg - CMOS Analog Circuit Design
Page IV.5-5
Contact Resistance Pad 1
Metal pads
Diffusion or polysilicon
Pad 3
Pad 4
Metal pads
Pad 2
Pad 1
RC
R RC
Pad 4 R RC
Pad 3 R M R M
Pad 2
5
Allen and Holberg - CMOS Analog Circuit Design V.
Page IV.5-1
Characterization of Capacitance
MOS capacitors C GS, C GD, and C GB Depletion capacitors C DB and C SB Interconnect capacitances C poly-field , C metal-field, and C metal-poly (and perhaps multi-metal capacitors SPICE capacitor models C GS 0, C GD 0, and C GB 0 (at V GS = V GB = 0). Normally SPICE calculates C DB and C SB using the areas of the drain and source and the junction (depletion) capacitance, C J (zero-bias value), that it calculates internally from other model parameters. Two of these model parameters, MJ and MJSW , are used to calculate the depletion capacitance as a function of voltage across the capacitor.
1
Allen and Holberg - CMOS Analog Circuit Design
Page IV.5-2
C GS 0 , C GD 0 , and C GB 0 C GS0 and C GD0,
are modeled in SPICE as a function of the device width, while the capacitor C GB0 is per length of the device Measure the C GS of a very wide transistor and divide the result by the width in order to get C GS 0 (per unit width).
Source
Drain
Source
Gate Figure B.6-1
C meas
Structure for determining C GS and C GD.
= W (n)(C GS0 + C GD0)
( 1)
where C meas = total measured capacitance W = n=
total width of one of the transistors
total number of transistors
2
Allen and Holberg - CMOS Analog Circuit Design
Page IV.5-3
For very narrow transistors, the capacitance determined using the previous technique will not be very accurate because of fringe field and other edge effects at the edge of the transistor. In order to characterize C GS0 and C GD 0 for these narrow devices, a structure similar to that given in Fig. B.6-1 can be used, substituting different device sizes. Such a structure is given in Fig. B.6-3. The equations used to calculate the parasitic capacitances are the same as those given in Eq. (1).
Metal drain interconnect
Drain
Source
Metal source interconnect
Drain
Polysilicon gate
Source
Figure B.6-3 Structure for measuring C GS and C GD, including fringing effects, for transistors having small L.
3
Allen and Holberg - CMOS Analog Circuit Design
Page IV.5-4
C GB0 GB 0
Drain
Gate overhang Gate Source FOX
Diffusion source
FOX
C GB
C poly-field
Figure B.6-4 Illustration of gate-to-bulk and poly-field capacitance.
This capacitance is approximated from the interconnect capacitance C poly-field (overhang capacitor is not a true parallel-plate capacitor) C poly-field
C meas
= L
R W R
(F/m2 )
(2)
where C meas = C meas L R
= measured value of the polysilicon strip
= length of the centerline of the polysilicon strip
W R =
width of the polysilicon strip (usually chosen as device length)
Having determined C poly-field , C GB0 can be approximated as C GB 0 ≅ 2 ( C poly-field )(d overhang ) = 2C 5
(F/m)
( 3)
where d overhang =
overhang dimension (see Rule 3D, Table 2.6-1)
4
Allen and Holberg - CMOS Analog Circuit Design
Page IV.5-5
C BD and C BS B S
- MJ - MJSW MJ MJSW V V J J + PC JSW (0) 1 + PB C (4) J (V J ) = AC J (0) 1 + PB where V J =
the reverse bias voltage across the junction
C J (V J ) =
bottom junction capacitance at
C JSW (V J ) =
V J
junction capacitance of sidewall at
A
= area of the (bottom) of the capacitor
P
= perimeter of the capacitor
V J
PB =
bulk junction potential The constants C J and MJ can be determined by measuring a large rectangular capacitor structure where the contribution from the sidewall capacitance is minimal. For such a structure, C J (V J ) can be approximated as MJ - MJ V J (5) C J (V J ) = AC J (0) 1 + PB This equation can be rewritten in a way that is convenient for linear regression. V J log[C J (V J )] = (− MJ )log )log 1 + PB + log[ AC J (0)] ( 6) Plotting log[C J (V J )] versus log[1 + and the
Y
intercept (where
Y
/ PB V PB] J
and determine the slope, − MJ ,
is the term on the left), Log[ AC J (0)].
Knowing the area of the capacitor, the calculation of the bottom junction capacitance is straightforward.
5
Allen and Holberg - CMOS Analog Circuit Design
Page V.0-1
V. CMOS SUBCIRCUITS Contents
V .1 V .2 V.3 V.3 V.4 V.4 V.5 V.5
MOS Switch MOS Diode MOS MOS Cur Curre rent nt Sour Source ce/S /Sin inks ks Curr Curren entt Mi Mirr rror ors/ s/Am Ampl plif ifie iers rs Refe Refere rennce Cir Circui cuits V.5-1 Power Supply Dependence V.5-2 Temperature Dependence V.6 Summary
Organization Chapter 10 D/A and A/D
Chapter 11 Analo S stems
SYSTEMS
Chapter 7 CMOS Com Com arat arator orss
Chapter 8 Simple CMOS O am s
Chapter 9 High Performance O am s
COMPLEX
CIRCUITS
SIMPLE
Chapter 5 CMOS Subcircuits
Chapter 2 CMOS Technology
DEVICES
Chapter 6 CMOS Amplifiers
Chapter 3 CMOS Device Modelin
Chapter 4 Device Characterization
Allen and Holberg - CMOS Analog Circuit Design
Page V.0-2
WHAT IS A SUBCIRCUIT?
A subcircuit is a circuit which consists of one or more transistors and generally perfoms only one function. A subcircuit is generally not used by itself but in conjunction with other subcircuits. Example Design hierarchy of analog circuits illustrated by an op amp.
Current Source Current Inverter Sink Sink Follower Load Load
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-1
V.1 - MOS SWITCH SWITCH PROPERTIES
Ideal Switch A
RAB(on) = 0Ω
B
RAB(off) = ∞
Nonideal Switch CAB IOFF ROFF VOFF
RON
+
A CAC
+
RA VControl
-
C
-
B
CBC RB
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-2
MOS TRANSISTOR AS A SWITCH
Symbol Bulk A
A (S/D)
B
B (D/S) C (G)
On Characteristics of A MOS Switch Assume operation in non-saturation region (v DS < vGS - V T). v D S K’W iD = L ( v G S -V T )- 2 vDS
∂iD K’W ∂vDS = L v G S − V T − v D S Thus,
∂vDS RON = ∂i = K’W K’W D
1
L (vG S − V T − vD S )
OFF Characteristics of A MOS Switch If v GS < V T, then i D = I OFF = 0 when vDS ≈ 0V. If v DS > 0, then 1 1 ROFF ≈ i λ = I λ ≈ ∞ DS OFF
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-3
MOS SWITCH VOLTAGE RANGES
Assume the MOS switch connects to circuits and the analog signal can vary from 0 to 5V. What are the voltages required at the terminals of the MOS switch to make it work properly? Bulk (0 to 5V) (S/D) Circuit 1
(0 to 5V) (D/S) Circuit 2 G
• The bulk voltage must be less less than or equal to zero to insure that the bulk-source and bulk-drain are reverse biased. • The gate voltage must be greater than 5 + V T in order to turn the switch on. Therefore, VBulk ≤ 0V VG ≥ 5 + V T (Remember that the larger the value of V SB, the larger V T)
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-4
I-V CHARACTERISTICS OF THE MOS SWITCH
SPICE ON Characteristics of the MOS Switch 100µA V1
V1 =10V V1=9V
Id
60µA V2
20µA
V1 =8V V1 =7V -5
Id -20µA
V1=2V V1=3V V1=4V
-60µA -100µA - 1V
V1 =5V V1 =6V -0.6V
- 0 .2 V
0.2 V V2
SPICE Input File: MOS Switch On Characteristics M1 1 2 0 3 MNMOS W=3U L=3U .MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, GAMMA=0.8 PHI=0.6 V2 1 0 DC 0.0 V1 2 0 DC 0.0 V3 3 0 DC -5.0 .DC V2 -1 1 0.1 V1 2 10 1 .PRINT DC ID(M1) .PROBE .END
0 .6V
1V
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-5
MOS SWITCH ON RESISTANCE AS A FUNCTION OF V G S
SPICE ON Resistance of the MOS Switch 100kΩ
W/L = 3µm/3µm
e c n a 10kΩ t s i s e R n O h c t i w S S 1kΩ O M
W/L = 15µm/3µm W/L = 30µm/3µm
W/L = 150µm/3µm
100Ω 1 .0 V
SPICE Input File:
1.5V
2. 0 V
2.5 V 3 .0V 3 .5 V Gate-Source Voltage
4 .0V
4 .5 V
5 .0 V
MOS Switch On Resistance as a f(W/L) M1 1 2 0 0 MNMOS W=3U L=3U M2 1 2 0 0 MNMOS W=15U L=3U M3 1 2 0 0 MNMOS W=30U L=3U M4 1 2 0 0 MNMOS W=150U L=3U .MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8 PHI=0.6 VDS 1 0 DC 0.001V VGS 2 0 DC 0.0 .DC VGS 1 5 0.1 .PRINT DC ID(M1) ID(M2) ID(M3) ID(M4) .PROBE .END
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-6
INFLUENCE OF SWITCH IMPERFECTIONS ON PERFORMANCE
Finite ON Resistance Non-zero charging and discharging rate. φ1
RON + VIN -
VSS
C1
+
+ vC1 -
C1
VIN -
+ vC1 -
Finite OFF Current φ1
φ1
C2 + vIN VSS CHold -
+ vOUT -
+ VSS
vOUT -
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-7
EXAMPLES
1.
What is the on resistance of an enhancement MOS switch if V S = 0V, V G = 10V, W/L = 1, V TO = 1V, and K' = 25 µA/V2? Assume that v DS ≈ 0V. Therefore, vDS L/W RON ≈ i = K'(V -V -V ) D G S T 106 RON = 25(10-1) = 4444 Ω VG
2.
If V G=10V at t=0, what is the W/L value necessary to discharge C 1 to with 5% of its intial charge at + t=0.1 µS? Assume K'=25 K'= 25 µA/V 2 5V - C1=20pF and V TO = 1V. → v(t) = 5exp(-t/RC) 10-7 10-7 exp RC = 20 → RC = ln(20) 10 Therefore, R = 6 x 10 3Ω 10x10 3 L/W L/W Thus, = = 6 K'(VG-V S-V T) (2.5x10-5)(9) W Gives L = 2.67
C2=10pF + -
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-8
INFLUENCE OF PARASITIC CAPACITANCES MOSFET Model for Charge Feedthrough Analysis
Case 1 - Slow Fall Time: • Gate is inverted as v G goes negative . • Channel time constant small enough so that the charge on C Hold is absorbed by v IN. • When gate voltage reaches v IN+VT, the device turns off and feedthru occurs via the overlap capacitance. Case 2 - Fast Fall Time: • Gate is inverted as v G goes negative. • Fall rate is faster than the channel time constant so that feedthru occurs via the channel capacitance onto C Hold which is not absorbed by v IN. • Feedthru continues when v G reaches v IN+VT. • Total feedthru consists of that due to both the channel capacitance and the overlap capacitances. Other Considerations: • Source resistance effects the amount of charge shared between the drain and the source. • The maximum gate voltage before negative transition effects the amount of charge injected.
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-10
Intuition about Fast and Slow Regimes
To develop some intuition about the fast and slow cases, it is useful to model the gave voltage as a piecewise constant waveform (a quantized waveform) and consider the charge flow at each transition as illustrated below. In this figure, the range of voltage at C L illustrated represent the period while the transistor is on. In both cases, the quantized voltage step is the same, but the time between steps is different. differ ent. The voltage accross C L is observed to be an exponential whose time constant is due to the channel resistance and channel capacitance and does not change from fast case to slow case. vCL
∆V vGATE
Voltage
Time (d)
∆V Voltage
Time (e)
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-11
Illustration of Parasitic Capacitances φ1
CGS + VIN -
CBS
CGD VSS
CBD
C1
+ -
vC1
CGS and CGD result in clock feedthrough CBS and CBD cause loading on the desired capacitances Clock Feedthrough Assume slow fall and rise times φ1 ∆φ1
Switch ON Switch OFF
φ1
CGS + VIN -
CBS
Clock signal couples through through CGD on the the rising part of signal when switch is off, but VIN charges C1 to the right value regardless. Clock signal couples through CGD on the falling part of the signal when the switch is off.
CGD VSS
CGD
C1
+ vC1 -
CGD
CGD
∆vC1 = -C +C ∆φ 1 ≈ - C ∆φ 1 = - C (v in + VT) 1 GD 1 1
Allen and Holberg - CMOS Analog Circuit Design EXAMPLE regime)
Switched
Capacitor
Page V.1-12 Integrator
(slow
clock
edge
φ1
Switch ON Switch OFF
vIN+VT
φ2
Switch ON Switch OFF
VT T t1 t 2
φ1
t3
t4
φ2
M1
M2
+
+ VIN -
assuming:
C2
VSS
C1
VSS
vOUT -
CGS1=CGS2=CGD1=CGD2 = CG
Net feedthrough on C 1 at t2: C
G ∆VC1 = − C +C (V + V T) G 1 IN
CG CG VC1 = VIN 1 − C +C −V T C +C 1 G G 1 At t 3, additional charge has been added due to C GS overlap of M2 as φ2 goes positive. Note that M2 has not turned on yet. CG
∆VC1 (t2-t3) = C +C VT G 1
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-13
Giving at the end of t 3 (before M2 turns on): CG VC1 = VIN 1−C +C 1 G + Once M2 turns on (at t 3 ), all of the charge on C 1 is transferred to C 2. CG C1 C1 ∆VO = −VC1C = −VINC 1 − C +C 2 2 1 G + Between times at t 3 and t4 additional charge is transferred to C1 from the channel capacitance of M2. Cch
∆VO (t3-t4)= − C (Vclk −VT) 2 The final change in Vout is: CG Cch C1 ∆VO = −VINC 1−C +C − C (Vclk − VT) 2 1 G 2 C1 Ideally the output voltage change is −VINC so the error due to charge 2 feedthrough is: C C
Cch
G ∆ V O (error) = VIN C1 C +C − (V − V T) 2 1 G C2 clk
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-14
Rigorous Quantitative Analysis of Fast and Slow Regimes
Consider the gate voltage traversing from V H to V L (e.g., 5.0 volts to 0.0 volts, respectively) described in the time domain as vG
= V H − Ut
(3)
When operating in the slow regime defined by the relationship 2 β V HT
2C L where
V HT
>>
(4)
U
is defined as
V HT = V H − V S
− V T
the error err or (the difference between the desired voltage V C L) due to charge injection can be described as
(5) V S
and the actual voltage,
Allen and Holberg - CMOS Analog Circuit Design
W· C G D 0 + C c h 2 V error = C L
π UC UC L 2β
Page V.1-15
+
W· C G D 0 (V S C L
+ V T − V L ) (6)
In the fast swithing regime defined by the relationship 2 β V HT
2C L
<<
(7)
U
the error voltage is given in Eq. (8) below as
W· CGD0 + C c h 2 V error = V H T C L
3 β V HT W· CGD0
− 6 U C + L
C L
( V S + V T T − V L )
(8)
The following example illustrates the application of the charge-feedthrough model given by Eq’s. (3) through (8). Example 4.1-1 Calculation of charge feedthrough error Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.1-9 where V s = 1.0 volts, C illustrated below. Use model L = 200 fF, W/L = 0.8µm/0.8µm, and V G is given for two cases illustrated parameters parameters from Tables Tables 3.1-2 and 3.2-1. Neglect ∆L and ∆W effects.
5
Case 2
vG
Case 1 0 0.2 ns 10 ns Time
Case 1: The first step is to determine the value of U in the expression vG = V H - Ut For a transition from 5 volts to 0 volts in 0.2 ns, U = 25 × 109 In order to determine operating regime, the following relationship must be tested.
Allen and Holberg - CMOS Analog Circuit Design 2
β V HT
Page V.1-16
2
β V HT
2C L >> U for slow or 2C L << U for fast Observin g that there is a backbias on the transistor switch effecting V T , V HT is V HT = V H - V S - V T T = 5 - 1 - 0.887 = 3.113 giving 2 β V HT 110×10-6×3.1132 = 2.66 × 109 << 25 × 109 thus fast regime. 2C L = 2×200f Applying Eq. (8) for the fast regime yields 1.58×10-15 -18 176×10 + 3.32×10-3 176×10-18 2 V error (5 + 0.887 - 0) 3.113- + error = 200×10-15 30×10-3 200×10-15 V error error = 19.7 mV
Case 2: The first step is to determine the value of U in the expression v G = V H - Ut
For a transition from 5 volts to 0 volts in 10 ns, U = 5 × 108 thus indicating the slow regime according to the following test 2.66 × 109 >> 5 × 108 1.58×10-15 -18 176×10 + 2 V error error = 200×10-15 V error error =
1.) Dummy Dummy trans transist istor or (MD) (MD) φ
φ
W1 L1
WD = W1 LD 2L1
M1
MD
VSS
VSS
Complete cancellation is difficult. Requires a complementary clock. 2.) Limit the clock swing when one one terminal of the switch is at a define definedd potential. vG
0V C
+
+
vin > 0 -
vout -
VSS
vG 3VT 2VT VT ON
OF F
ON
t
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-18
CMOS SWITCHES
"Transmission Gate"
φ
A
VSS
VDD
φ Advantages 1.) Larger dynamic range. 2.) Lower ON resistance. resistance. Disadvantages 1.) Requires complementary clock. 2.) Requires more area.
B
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-19
DYNAMIC RANGE LIMITATIONS OF SWITCHES
Must have sufficient v GS to give a sufficiently low on resistance Example: VDD 50µ 2µ A VAB
B VDD
+
1 µA
50µ 2µ
3kΩ e c 2.5kΩ n a t s 2kΩ i s e R 1.5kΩ n O h c 1kΩ t i w S 0.5kΩ
0kΩ
SPICE File:
VDD = 4V VDD = 4.5V VDD = 5V
0V
1V
2V
VAB
3V
4V
5V
Simulation of the resistance of a CMOS transmission switch M1 1 3 2 0 MNMOS L=2U W=50U M2 1 0 2 3 MPMOS L=2U W=50U .MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5 .MODEL MPMOS PMOS VTO=-0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5 VDD 3 0 VAB 1 0 IA 2 0 DC 1U .DC VAB 0 5 0.02 VDD 4 5 0.5 .PRINT DC V(1,2) .END
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-20
“Brooklyn Bridge” Effect
If N-channel and P-channel devices are “resistively” scaled (i.e., sized to have the same conductance at equivalent terminal conditions) the resistance versus voltage (common mode) will appear as shown below.
Nch on Pch off
Nch on; Pch on
Pch on Nch off
280 270
5v
260
R
Id
250
5v 240
V
230
0.1
220 210 0
1
2
3
V
4
5
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-21
VOLTAGE DOUBLER USE TO PROVIDE GATE OVERDRIVE Example
VDD M1
φA
φA
CPump
M6 M4
M2
φA
M7
+
M8
φB
CHold
M3 M5
φB
φA
φB
VSS φA φB Operation:
1. φA low, φB high - C Pump is charged to V DD -V SS . 2. φA high, φB low - C Pump transfers negative charge to C Hold VDBL ≈ -0.5 V D D -V S S 3. Eventually, V DBL approaches the voltage of -V DD + VSS. If VDD = - VSS , then V DBL ≈ - 2V DD .
VDBL -
Allen and Holberg - CMOS Analog Circuit Design
Page V.1-22
SUMMARY OF MOS SWITCHES
• Symmetrical switching characteristics • High OFF resistance • Moderate ON resistance (OK for most applications) • Clock feedthrough is proportional to size of switch (W) and inversely proportional to switching capacitors. • Complementary switches help increase dynamic range. • As power supply reduces, switches become more difficult difficult to fully turn on. • Switches contribute a kT/C noise which folds back into the baseband.
Allen and Holberg - CMOS Analog Circuit Design
Page V.2-1
V.2 - DIODES AND ACTIVE RESISTORS MOS ACTIVE RESISTORS
Realizations +
i
i
i
+
v
v
-
-
When the drain is connected to the gate, the transistor is always saturated. vDS ≥ vGS - V T vD - v S ≥ v G - v S - V T ∴ vDG ≥ -VT where V T > 0 Large Signal
I-V Characteristics AC DC
K 'W i = iD = ( 2L ) [ v GS - VT ]2
β
= 2 ( v GS - V T ) 2 , ignore or
v
v = v DS = vGS = V T +
Small signal i G
S
+ v
D gm v
gmbs vbs
rds
-
S
v If VBS = 0 , then R OUT = OU T i If V BS ≠ 0? Note:
λ
1 1 = g +g ≈ g M DS M
Generally, gm ≈ 10 g mbs ≈ 100 g ds
2iD
β
Allen and Holberg - CMOS Analog Circuit Design
Page V.2-2
VOLTAGE DIVISION USING ACTIVE RESISTORS
Objective : Derive a voltage Vout from V SS and VDD VDD M2 Vout M1 VSS
Equating i D1 to i D2 results in : vDS1 = where
vGS1 = v DS1
β2 β1 v D S2 -V T 2 + VT1 and
v GS2 = vDS2 DS 2
Example : If VDD = -V SS = 5 volts, Vout = 1 volt, and I D1 = ID2 = 50 µamps, then use the model parameters of Table 3.1-2 to find W/L ratios.
β
iD1 = 2 ( v GS - V T ) 2 β1 = 4.0 µA/V2 β2 = 11.1 µA/V2 K' n = 17 µA/V2 K'p = 8 µA/V2 1 then ( W/L )1 = 4.25
and ( W/L )2 = 1.34
Allen and Holberg - CMOS Analog Circuit Design
Page V.2-3
EXTENDED DYNAMIC RANGE OF ACTIVE RESISTORS
Concept: I VC +
I1 M1
+ vDS -
I I2 M2
+ VC -
Consider : Assume both devices are non-saturated 2 v DS I1 = β1 ( v D S +V C -V T ) v D S - 2
R
2 v DS I2 = β2 ( V C -V T ) v D S - 2 2 2 v v DS DS I = I1 + I 2 = β v D S 2 +(V C -V T ) v D S - 2 +(V C - V T ) v D S - 2 1 I = 2 β(VC - V T)vDS R = 2 β ( V -V ) C T
Allen and Holberg - CMOS Analog Circuit Design
Page V.2-4
Implementation : VDD + V - C
M3A
S
M1
+ VGS
M2A
G-
M3B
D
S M2 - vDS +
i
+
R VSS
i
VGS S
G
M2B
Allen and Holberg - CMOS Analog Circuit Design
NMOS Parallel Transistor Realization : + i D2 D1 i2 i1 VC + G1 M1 v VSS M2 S1
Single MOSFET Parallel MOSFET Single-MOSFET, differential resistor
P oo r
How How Controlled VGS or W/L
vBULK < Min (v S, vD)
Good
VC or W/L
v ≤ (VC - V T)
V C or W/L
|v1| < V C - VT vBULK < -v 1 Differential around v 1
Good
Double-MOSFET, Very Good VC1 - V C2 or W/L differential resistor
Restrictions
v1, v2 < min(VC1-VT, VC2-VT) vBULK < min(v1,v2) Transresistance only
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-1
V.3 - CURRENT SINKS & SOURCES CHARACTERIZATION OF SOURCES & SINKS
1). Minimum voltage (v MIN ) across sink or source for which the current is no longer constant. 2). Output resistance which is a measure of the "flatness" of the current sink or source. CMOS Current Sinks & Sources VDD iD VGG
VG = V GG
iD + v
-
vMIN
v
0
iD
VDD
VG = V GG
VGG iD
+
v
1 rOUT = OU T λID vMIN = vDS(SAT.) = v ON
0 0
vMIN VDD
where vON = vGS - V T
v
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-2
SMALL SIGNAL MODEL FOR THE MOSFET
D G
B S
gm =
2K'WI D L
gmγ gmbs = 2 2 φ F +|V B S | 1 1 r ds ≈ g = λI ds D
G +
B +
vgs
vbs
S
-
D gmvgs
gmbsvbs
rds S
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-3
INCREASING THE R OUT OU T OF A CURRENT SOURCE
MOS MOS Circuit
Small-Signal Model i OUT
+ iout +
M2 r ds2 g
2 vgs2
vOUT
+ -
r
g
bs2 vbs2
+
VGG
-
v S2 -
r
Loop equation: vout = [iout - (g m2vgs2 + gmbs2vbs2)]r ds2 + iout r But, v gs2 = -v s2 and v bs2 = - v s2. vout = [i out + gm2vs2 + g mbs2vs2]rds2 + iout r Replace vs2 by i outrvout = iout [ r ds2 + gm2 rds2 r + gmbs2rds2 r + r ] Therefore, rout = rds2 + r [1 + g m2 rds2 + g mbs2rds2 ] MOS Small Signal Simplifications Simplifications Normally, g m ≈ 10g m b s ≈ 100g d s Continuing rout ou t ≅ rgm2 rds2 ds 2 rout
≈
r x (voltage gain of M2 from source to drain)
vout -
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-4
CASCODE CURRENT SINK
MOS MOS
Circuit
iOUT
IREF
iout
+
M2
M4
Small-Signal Model
+
vOUT M3 M1
gmbs2vbs2
r ds2
gm2vgs2
-
vout
+ vS2 -
r ds1 gm1vgs1
-
vout = [iout - (g m2vgs2 + gmbs2vbs2)]rds2 + ioutrds1 vout = iout [rds2 + g m2 rds2 r(1 + η2) + r ds1 ] rout = rds2 + r[1 + g m2 rds2 (1 + η2)] ≅ r ds1 gm2 rds2 (1 + η2) Note : v MIN = VT + 2VON ≅ 0.75 + 1.5 = 2.25 (assuming VON ≈ VT) NMOS Cascode1mA Slope = 1/R o 0.75mA + vGS2 -
iO 0.5mA 0.25mA 0mA 0V
2V
4V
vO
VMIN 6V
iO + vO
+ vGS1 - 8V
1 0V
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-5
Gate-Source Matching Principle iD2
iD1
iD2 +
M1 -
+
vGS1
vGS2
+
vGS2
-
M2
iD1
-
S = W/L
M2
+
vGS1
-
M1
Assume that M1 and M2 are matched but may not have the same W/L ratios. 1). If v GS1 = vGS2 , then i D1 = (S 1 /S2)iD2 a). v GS1 may be physically connected together , or b). v GS1 may be equal to v GS2 by some other means. 2). If i D1 = i D2 , then a). v GS1 = V T + S2 /S1(vGS2 - V T) , or b). If S 1 = S 2 and V S1 ≈ V S2 then vGS1 = v GS2 GS 2 Strictly speaking, absolute matching requires that v DS be equal for two matched devices.
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-6
Reduction of VMIN or VO U T (sat) High-Swing Cascode
Method 1 for Reducing the Value of v OUT(sat) IREF
IOUT
2VT + 2VON
IOUT VOUT(sat)
M4
M3
+ VT + VON -
+
M2 M1
VOUT + VT + VON
+ VT + VON -
-
0
VOUT
VT + 2VON
Standard Cascode Sink : vGS = VON + V T =
Partofv G S toachieve draincurrent
Partofv G S t o + enhancethechannel
∴ vDS(sat) = v GS - V T = (VON + VT) - V T = VON iD
ID
VT
VT+VON
Above is based on the Gate-Source matching principle.
vGS
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-7
Circuit Circ uit Whic W hich Reduces the Value of Vout(sat) Vout (sat) of the Cascode Curren Cur rentt Sink
iREF
iREF
M6
M4 1/4
+ -
+ 1/1
+
VT + 2VON
iOUT
+ VT + VON -
M2
+
-
M3 1/1
1/1
VT + VON
2VT + 3VON
M5
iout
vOUT
VT + VON VT + 2VON
M1
+
VON
1/1 1/1
iD vOUT(sat)
-
-
W=1 L 1
W =1 L 4
VT + VON
VT + 2VON
ID
0
2VON
K 'W iD = 2 L (vGS - VT ) 2
vOUT
0
K 'W = 2 L (VO N ) 2
vGS VT
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-8
Method 2 for Reducing V MIN for MOS Cascode Cascode Sink/Source
iREF
iREF
iO
M5
1
M4
+ 1/4
M1 1
VT + VON
M2
+ VT + VON -
+
VON 1
-
Assume (W/L)1 = (W/L)2 = (W/L)4 = 4(W/L)5 values are identical and ignore bulk effects. Let I REF = IO RE F VGS1 =
2I REF RE F + V T = V ON + VT W1 K ’ L 1
and VGS5 =
2IREF RE F +V W5 T K ’ L 5
Since (W/L)1 = 4(W/L)5 VGS5 =
2I REF RE F + VT = 2 W1 K ’ 4L 1
2I REF RE F + V = 2 V ON + VT W1 T K ’ L 1
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-9
Since V GS3 = VGS4 = VON +VT VDS1 = V DS2 = V ON which gives gives a minimum output voltage voltage while keeping all devices in saturation of of v M I N =2V O N Output Plot: 1000µA 750µA ) 4 M ( 500µA D I
250µA 0µA 0V
1V
2V 3V VOUT
4V
5V
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-10
Matching Improved by Adding M3
iREF
iREF
VT
+ M3 1
+
V T + VON
-
1
M4
+ 1/4
M1
VON
1
M5
+
-
iO
V T + 2VON
+ V T + VON -
VT + VON
M2
+
V ON 1
-
What is the purpose of M3? The presence of M3 forces the V DS1 = VDS2 which is necessary to guarantee that M1 and M2 act alike (e.g., both will have the same V T).
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-11
CMOS REGULATED CASCODE CURRENT SOURCE
Circuit Diagram VDD
VDD IB2
iOUT RB2 M3
iD3 +
vGS3
IB1 M4
vOUT
Iout
M2
M1
-
VDS3(min) VDS3(sat)
vDS3
Principle of operation: As v OUT decreases, M3 will enter the non-saturation region and iOUT will begin to decrease. However, this causes a decrease in the gatesource voltage of M4 which causes an increase in the gate voltage of M3. The minimum value of v OUT is determined by the gate-source voltage of M4 and Vdsat of M3. Assume that all devices are in saturation. vOUT (min) =
2IB2 K'(W/L) 4 +
2Iout K'(W/L) 3 + V T4
Allen and Holberg - CMOS Analog Circuit Design
Page V.3-12
CMOS REGULATED CASCODE CURRENT SOURCE - CONT.
Small Signal Model
r ds3 iout
+ vgs3 +
RB2
r ds4
gm4vgs4
vgs4
gm3vgs3 r ds2
-
+
vout -
(Ignore bulk effects)
iout = gm3vgs3 + g ds3(vout - v gs4) vgs4 = ioutrds2 vgs3 = v g3 - v s3 = -g m4 (rds4 ||R B2)v gs4 - v gs4 = -r ds2 [1 + g m4 (r ds4 ||R B2 )]i out
∴
iout = -g m3rds2[1 + g m4(rds4||RB2)]iout + g ds3vout - g ds3rds2 iout
Solving for v out, vout = r ds3 [1 + g m3 rds2 + g ds3 rds2 + g m3 rds2 gm4 (r ds4 ||R B2 )]i out ou t vout rout = i = r ds3 [1 + g m3 rds2 + g ds3 rds2 + g m3 rds2 gm4 (r ds4 ||R B2 )] out g m 2r3 r out=r = r ds3 || R B2 )= 2 ds 3 g m3 rds2 ds 2 g m4 (r ds4 ds 4 ||R Example K' N = 25 µA/V 2, λ = 0.01, I B1 = IB2 = 100 µA, all transistors with minimum geometry (W = 3 µm, L=3µm), and R B2 = r ds, we get rds = 1M Ω and g m = 70.7µmho rout≈ (1M Ω)(70.7µmho)((1MΩ)(70.7µmho)(1MΩ||1MΩ)= 2.5GΩ!!!
If the devices are matched, iO W2L1 1+λvDS2 iI = W1L2 1+λvDS1 If v DS1 = vDS2 , iO W 2L 1 iI = W1L2 Therefore the sources of error are: 1). v DS1 ≠ vDS2 DS 2 2). M1 and M2 not matched ( ∆β and ∆VT)
+ vGS -
M2
vDS2 -
Allen and Holberg - CMOS Analog Circuit Design
Page V.4-3
Simple Current Mirror With λ ≠ 0 Circuit -
iO
iI + vDS1 -
% 0 0 1 x ) 1 -
M1
M2
+ vGS -
+
10
λ = 0.02 8
1 2 S S D D
λ = 0.015 6
v v
λ λ
v DS2 + + 4 1 1 (
v SS
r o r r E o i t a R
λ = 0.01
2 0 0V
1V
2V 3V VDS1-VDS2
Ratio error (%) versus drain voltage difference Used to measure λ iO 1 + λ v D S 2 S1 iI = 1 + λ v D S 1 S2 If S 1 = S 2, v DS2 = 10V, v DS1 = 1V, and i O /iI = 1.501, then iO 1+10λ ∴ i = 1.501 = 1 + λ I
0.5 0. 5 ---> λ = 8.5 = 0.059
4V
5V
Allen and Holberg - CMOS Analog Circuit Design
Page V.4-4
Matching Matching Accuracy Accuracy of MOS Current Mirro Mir rors rs Neglect λ effects
iD1
iD2 +
M1 Define:
+
vGS1
vGS2
iO = iD2 = β2(vGS2-VT2)2 iI iD1 β1(vGS1-VT1)2
M2
(vDS2 > vGS2 - VT1)
-
∆β = β2 - β1
and
∆β
∆β
β=
β 1 + β 2
2 VT1+VT2 ∆VT = VT2 - VT1 and VT = 2
∆VT
∴ β 1 = β - 2 , β 2 = β + 2 , VT1 = VT - 2 ∆ VT and V T2 = V T + 2
Example of Small Signal Output Resistance Calculation ii io + v3 -
rds3
gm3 v3 v1=v3 =0
+ v1 -
rds1
gm1 v1
+ v4 + v2 -
+ rds4
gm4(v3+v1 -v2 ) io
rds2
gm2 v1
gmbs v2 vo -
1). v o = v 4 + v 2 = rds4 [i o - g m4 (v3 + v 1 - v 2) + gmbs4v2] + rds2 (io - gm2 v1) 2). v 2 = i ords2 ds 2 3). v o = i o [rds4 + (g m4 rds2 )r ds4 + (r ds2 gmbs4)r ds4 + r ds2 ] vo 4). r out = i = r ds4 + r ds2 + r ds2 rds4 (g m4 + g mbs4) o
Allen and Holberg - CMOS Analog Circuit Design
Page V.4-9
Wilson Current Mirror Circuit and PerformanceIin = 80uA
Principle of Operation: Series negative feedback increase output resistance 1. Assume input current is constant and that there is high resistance to ground from the gate of M3 or drain of M1. 2. A positive increase in output current causes an increase in v GS2. 3. The increase in v GS2 causes an increase in v GS1. 4. The increase in v GS1 causes an increase in i D1. 5. If the input current is constant, then the current through the resistance to ground from the gate of M3 or the drain of M1 decreases resulting in a decrease in v GS3 . 6. A decrease in v GS3 causes a decrease in the output current opposing the assumed increase in step 2.
Allen and Holberg - CMOS Analog Circuit Design
Page V.4-10
Output Impedance of the Wilson Current Source iout +
iin=0
v3 -
gm1v2
rds1
+ v1 -
+ rds3
gm2v2
gm3(v1-v2)
rds2
+ v2 -
gmbs3v2 vout -
vout = rds3 [iout - g m3v1 + g m3v2 + gmbs3v2] + v 2 vout = r ds3 iout - g m3 rds3 (-g m1 rds1 v2) + gm3 rds3 v 2 + g mbs3rds3 v2 + v 2 rds 2 v2 = iout 1+g m 2 r d s 2 vout = iout rds3 + [g m3 rds3 + g mbs3rds3 + g m1 rds1 gm3 rds3 ]v 2 + v 2 + g m 1 r ds1 ds 3 +g mbs3 r ds3 +g ds 1 g m 3 r d s 3 1+g m 3 r ds3 rout = r + r ou t ds3 ds 3 ds2 ds 2 1+g m2 rds2 r ds2 ds 2 g m 1 r d s1 g m 3 r d s 3 r ou t ≈ ≈ r d s 1 × ( g m 3 r d s 3 )ifg m 1 =g m 2 gm2 rds2 ds 2
Allen and Holberg - CMOS Analog Circuit Design
Page V.4-11
Improved Improved Wilson Wilson Current Mir M irro rorr
Iout
Iin
M1
M4
M3
Additional diode-connected transistor equalizes the drain-source voltage drops of transistors M2 and M3
Regulated Regulated Cascod Cascodee Current Mi Mirr rror or VDD
iOUT IB
M4
+
IIN M3
vOUT
+ vGS4 -
M1
M2
-
VSS
Small Signal Equivalent Model (g mbs effects ignored) iout + rds4
gm4v
v4 + g m3 v3
rds3
rds2
s4
vout
v3 -
-
vout = (i out - g m4vgs4 )rds4 + iout rds2 vgs4 = v 4 - v 3 v3 = iout rds2 v4 = -g m3 v3rds3 vout = iout rds4 - g m4 (-g m3 iout rds2 rds3 - i out rds2 )r ds4 + i out rds2 rout = r ds4 + g m4 gm3 r ds2 rds3 rds4 + r ds2 + g m4 rds2 rds4 ds 4 2IB 2Iout vOUT (min) = K'(W/L) 4 + K'(W/L) 3 + V T4
Allen and Holberg - CMOS Analog Circuit Design
Page V.4-13
SUMMARY OF CURRENT MIRRORS
Simple
Poor (Lambda)
Output Resistance rd s
Cascode
Excellent
g m rds 2
VT + 2V ON
Wilson
Excellent
g m rds 2
2VON
Good
gm 2rds 3
VT + 2VON
C ur r e n t M i r r o r
Regulated Cascode
Accuracy
Minimum Voltage VON
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-1
V.5 - REFERENCE CIRCUITS Introduction
What is a Reference Circuit? A reference circuit is an independent voltage or current source which has a high degree of precision and stability. Requirements for a Reference Circuit 1.) Output Output voltag voltage/c e/curre urrent nt should should be inde indepen penden dentt of power power supply. supply. 2.) Output Output voltage voltage/cur /current rent shoul shouldd be indepen independen dentt of temperat temperature. ure. 3.) Output voltage/curren voltage/currentt should should be indepen independent dent of processin processingg variatio variations. ns. V-I Characteristics of an Ideal Reference i
Voltage Reference
Iref Current Reference
Vref
v
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-2
Concept of Sensitivity
Definition Sensitivity is a measure of dependence of V ref (Iref ) upon a parameter or variable x which influences V ref (Iref ). Vref
∂Vref
Vref x ∂Vref = ∂x = V ∂x ref x x
S
where x = VDD or temperature Application of Sensitivity
∂Vref Vref
Vref ∂x = S x x
For example, if the sensitivity is 1, then a 10% change in x will cause a 10% change in V ref . Vref Ideally,
S x
→0
Allen and Holberg - CMOS Analog Circuit Design V.5-1 - SIMPLE REFERENCES
Objective is to minimize,
∂ V r e f
Vref
S
VDD
=
Vref ∂VD D VDD
Types of references include, 1. Voltage dividers - passive and active. 2. MOS diode reference. 3. PN junction diode reference. 4. Gate-source threshold referenced circuit. 5. Base-emitter referenced circuit.
Page V.5-3
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-4
Passive Divider Accuracy is approximately equivalent to 6 bits (1/64). VDD
RA V1 I
RB V2 RC
VSS
Active Dividers I V3 M3
VDD
VDD
V2 M2 V1 M1
M2
M2
+ M1 Vref -
+ M1 Vref -
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-5
PN Junction Voltage References Refere nces VCC kT I I VREF = V BE = q ln I = V t ln I s s
I
R
V C C -V B E VCC If I = ≈ R R
+
VREF
VCC V REF ≈ V t ln RI s
-
Sensitivity:
VREF
S
=
VCC
1 VCC ln RI s
VREF
If V CC = 10V, R = 10 k Ω, and I s = 10 -15A, then Modifying the Value of V REF RE F VCC
R IR1
R1
= 0.0362.
VCC
If β >> 1, then V REF ≈ IR1(R 1+R 2) I +
VREF R2
S
-
VBE replacing I R1by R gives, 1 + R2 R 1+R VREF ≈ R V BE 1 or R1+R2 VCC VREF Vt ln RI RE F ≈ R 1 s
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-6
Gate-Source Referenced Circuits (MOS equivalent of the pn junction referenced circuit) VDD VREF = V GS = V T + I
R
1 V R E F =V T − βR +
+
2(V DD-V REF ) βR 2(VDD-VT) 1 + βR β2R2
VREF Sensitivity:
-
V RE F
S
VDD
VDD 1 = V 1+ β R ( V REF R E F -V T )
If V DD = 10V, W/L = 10, R = 100k Ω and using the results of Table 3.1-2 gives VREF
VREF = 1.97V.and
S
= 0.29.
VDD
Modifying the Value of V REF RE F V DD
R IR1
R1
+ R2 R 1+R VREF ≈ R V GS 2
I +
V REF R2 -
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-7
Bootstrapped Current Source VDD M4 M5
M3
RB
ID1 = I1
iOUT
ID2 = I2
M6 M2 M8
M1 R
Principle:
I2
If M3 = M4, then I1 = I 2
(1)
also, VGS1 = V T1 +
2I1 KNS1 = I2R
therefore, VT1 1 I2 = R + R
2I1 KNS1
Des ope poi
Eq. (2)
Eq. (1)
(2) Undesired operating point
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-8
Bootstrapped Current Sink/Source - Continued An examination of the second-order effects of this circuitThe relationship between M1 and R can be expressed as, I2R = V T1 +
2I1
β1
Instead of assuming that I 1 = I2 because because of the current curre nt mirror mir ror,, M3-M4, let us consider the effects of the channel modulation which gives 1+ λ P V G S 4 I2 = I 1 1+ λ ( V -V ) P DD DS1 Solving for I 1 from the above two expressions gives I1R(1 + λPVGS4) = [1 + λP(VDD-VDS1)]
2I1
β1
Differentiating with respect to V DD and assuming the V DS1 and V GS4 are ar e constant gives (I OUT = I 1), IOUT
S
VDD
2I1 20V DDλPV T 1 + β1 = 1+ λ P ( V D D -V D S 1 ) IOUTR(1+ λ P V G S 4 )- 2β 1I 1
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-9
Bootstrapped Current Sink/Source - Continued Assume that V DD=5V, K N ' = 23.6 µA/V 2, VTN=0.79V, γ N=0.53V 0.5, φ P = 0.590V, λN=0.02V-1, K P ' = 5.8 µA/V 2, VTP=-0.52V, γ P=0.67V0.5, φ P = 0.6V, λN=0.012V-1. Therefore, VGS4 = 1.50V, V T2 = 1.085V, V GS2 = 1.545V, and V DS1 = 2.795V which gives
IOUT
S
VDD
∆IOUT /IOUT OU T = 0.08 = ∆V /V DD DD
∆VD D = 3.2µA If ∆VDD = 6V - 4V = 2V, then ∆IOUT = 0.08 I OUT V DD SPICE Results: 120µA 100µA
∆ IOUT OUT ≈ 2.8µA for ∆ VDD 4V →6V
80µA
IOUT
60µA 40µA 20µA 0µA 0V
2V
4V
VDD
6V
8V
1 0V
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-10
Base-Emitter Voltage Referenced Circuit VDD M4 M5
M3
RB
ID1 = I1
ID2 = I2
M6 M1 M8
VBE1 BE 1 I2 ≈ R = I 5 V = I2R ≈ VBE1
Q1
M2 R
iOUT
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-11
V.5-2 - TEMPERATURE DEPENDENCE
Objective Minimize the fractional temperature coefficient which is defined as 1 ∂Vref TCF = V ∂ T parts per million per °C or ppm/ °C ref Temperature Variation of References PN Junction:
v i ≈ I s e x p V t -V GO 3 I s =KT exp ex p V t
dvBE V B E -V G O = -2mV/ °C at room temperature dT ≈ T (VGO = 1.205 V and is called the bandgap voltage) Gate-Source Voltage with constant current (Strong Inversion): dVGS dVT dT = dT +
2L d WCox dT
ID µo
µo = KT -1.5 ; VT = V T0 - αT or V T(T) = VT(T o) - α(T-To) dV G S 3 V G S -V T dT =- α + 4 T
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-12
PN Junction Voltage Reference VDD
R
I
+ VREF = VBE = kT ln I = Vt ln I q Is Is -
V D D -v B E VD D I= ≈ R R
------->
VDD V R E F =V tln l n RI s
Vt dR dVREF V R E F -V G O TC F = V = TV - V RdT REF dT REF RE F REF 1
Assume VREF = 0.6 volts and that R is a polysilicon resistor dR RdT=+1500ppm/ ° C gives a 0.6-1.205 0.026 T C F = (300 K)(0.6) - 0.6 (0.0015) = -0.003361 - 0.000065 = -3426 ppm/ °C
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-13
Gate - Source Referenced Circuits MOS Equivalent of the PN Junction Referenced Circuit VDD R
I +
VREF -
1 V REF =V T − βR +
1 dVR EF TCF = V = dT REF
2(VDD−VT) 1 + βR β2R2
1 VREF
V D D − V R E F 1.5 1 d R − R dT 2βR T 1 1 + 2 β R(V D D − V RE F )
−α +
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-14
Example
W = 2L, VDD = 5V, R = 100 KΩ , K’=110 µ, VT = 0.7, T = 300 K, α = 2.3 mV/ °C Solving for V REF gives VREF = 1.281 V dR RdT = +1500 ppm/ °C
2ID1L VGS1 K'W K' W +V T V O N +V T ID2 = R = = = I D1 = I OUT OU T R R Assuming that V ON is constant as a function of temperature because of the bootstrapped current reference, then 1 dVT 1 dR -α 1 dR ∴ TCF = V dT - R dT = V - R dT T T If R is a polysilicon resistor, then -2.3x10 - 3 TCF = - 1.5x10 -3 = -3800 ppm/ °C 1 If R is an implanted resistor, then -2.3x10 - 3 TCF = - 0.4x10 -3 = -2700 ppm/ °C 1
Allen and Holberg - CMOS Analog Circuit Design
Page V.5-16
Base-Emitter Voltage - Referenced Circuit VDD M4 M5
M3
RB
ID1 = I1
ID2 = I2
iOUT
M6 M1 M8
Q1
vBE1 BE 1 I2 ≈ R
M2 R
1 dv BE 1 dR -----> TCF = v - R dT dT BE
Assuming VBE = 0.6 volts and a polysilicon resistor gives 1 TC F = 0.6 (-2x10-3) - (1.5x10 -3) = -4833 ppm/ °C
Allen and Holberg - CMOS Analog Circuit Design
Page V.6-1
V.6 - SUMMARY • The circuits in this chapter represent the first level of building blocks in analog circuit design. • The MOS MOS transistor transistor makes a good switch and a variable variable resistor resistor with with reasonable ranges of linearity in certain applications. • Primary switch imperfection imperfection is clock feedthrough. feedthrough. In order for switches to be used with lower power supplies, V T must be decreased. • The primary primary charac characteri teristic sticss defining defining a current current sink sink or source source are V MIN and Rout. V MIN → 0 and R out → ∞. Typically the product of V MIN times Rout is a constant in most designs. • Curren Currentt mirror mirrorss are charac character terize izedd by: by: Gain accuracy Gain linearity VMIN on output Rout Rin • Reasonably Reasonably good good power power supply supply independen independentt and temperat temperature ure independe independent nt voltage and current references are possible. These references do not satisfy very stable reference requirements.
Allen and Holberg - CMOS Analog Circuit Design
VI.
Page VI.0-1
CMOS AMPLIFIERS
Contents
VI.1 VI.2 VI.2 VI.3 VI.3 VI.4 VI.4 VI.5
Simple Simple Invert Inverting ing Ampli Amplifie fierr Diff Differ eren enti tial al Ampl Amplif ifie iers rs Casc Cascod odee Ampl Amplif ifie ierr Outp Output ut Ampl Amplif ifie iers rs S um m a r y
Organization
SYSTEMS
Chapter 10 D/A and A/D Converters
Chapter 7 CMOS Comparators
Chapter 11 Analog Systems
Chapter 8 Simple CMOS OTA's
Chapter 9 High Performance OTA's
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
DEVICES
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-1
VI.1 SIMPLE INVERTING AMPLIFIERS CHARACTERIZATION OF AMPLIFIERS
We shall characterize the amplifiers of this Chapter by the following aspects: • Large Signal Voltage Transfer Characteristics • Maximum Signal Swing Limits Limits • Small Signal Midband Performance Gain Input resistance Output resistance • Small Signal Frequency Response • Other Considerations Noise Power Etc.
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-2
VI.1.1 - CMOS INVERTERS
Types
VDD VGG2 M2
M2
+ M1
+ vIN -
M2
+ M1
vOUT + vIN - Active Current Load Source Inverter Inverter
+
vOUT vIN -
+ M1
vOUT
-
Push-pull inverter
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-3
ACTIVE LOAD INVERTER - VOLTAGE TRANSFER CURVE CMOS Active Load Inverter VDD 3 0 DC 5.0 5V 1.2 v IN=5V
= 2 (vOUT−VSS)−(VDD−VSS−VT)2 Define vOUT ' = v OUT − V SS and V X = V DD − V SS − V T (v OUT')2 (M1) ∴ iD = β1 V XvOUT OU T'− 2
β2
iD = 2 v O U T ' − V X 2 Equate currents -
(M2)
v O U T '2 2 2 V v 2 = β V v X O UT '+V X 1 X O U T ' − 2 v OU T ' − 2V 2
β2
or
β2 2 2 V v 2 = 2V v 2 X O UT '+V X X OUT ' − v OUT OU T' β1 v OU T ' − 2V β 2 β 2 β2 2 2 1+ β vOUT OU T' − 2VX1+ β vOUT OU T' + β V X = 0 1 1 1 β2 / β1 2 2 vOUT OU T' − 2VXvOUT OU T' + 1+β / β VX = 0 2 1
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-5
β2 / β1 1 1 − 1+β2 / β1 = VX 1 − ∴ 1+ β 2 / β 1 V D D − VSS − VT v O U T (min.)=V D D − V T − 1+ β 2 / β 1 vOUT OU T' = V X1 ±
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-6
Interpretation of v OUT(min.) vOUT(min.) = (V DD − VSS − V T)1 −
1
β2 1+ β 1
+ V SS
VDD = −VSS = 5V VT = 1V vOUT 5
3
v
MAX
1 0
0.1
1
10
-1 v -3
-5
Gain ~
β1 β2
MIN
β1 β2
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-7
Active Load Inverters
Small Signal Characteristics Model: 5V S2=B2 gm2vgs2
M2
+
M1
v OUT + vIN -
rds2
D1=D2=G2 G1 + v in gm1 vin
rds1
v in g m1v in
v out
r ds1
g m2v out
rds2
v out -
-
-
-
+
+
+
S1=B1
-
Small Signal Voltage Gain vout = − g m1 v in +g m2 v out ou t r d s 1 ||r d s 2
−gm1 −gm 1 vout vin = g d s 1 +g d s 2 +g m 2 ≈ gm2 = − vout vin = −
W1 2KN L I1 1 = − W2 2KP L I2 2
µNO W1L2 µPO W2L1
K N ' W1L2 = − K P ' W2L1
W 1 /L 1 vout If W /L = 20, then v = −6.67 using the parameters of Table 3.1-2 2 2 in Small Signal Output Resistance rout = g
1
d s 1 +g d s2 +g m 2
≈g
1 m2
β1 β2
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-8
High Gain CMOS Inverters VDD VGG
VDD
M2 I
M2 I
vIN
vOUT OUT vIN
vOUT
M1
M1
V SS
V SS
Inverter with current source load
Push-pull, inverter I
M2 vIN = V SS
M1 vIN = VDD
.8V SS .8V DD .6V SS
.6V DD
.4VSS
.4V DD I
.2VSS
.2VDD
J K
0
H
G
F=F'
0
.2VDD .4VDD VSS
D'
E' E D K'
J' I' H' G'
.5VSS
0
.5VDD
.2V SS C=C' B=B'.4V SS .6V SS A=A' V DD
vOUT
Large signal transfer characteristics of inverter with a current source and push pull inverter
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-9
High Gain, CMOS Inverter Large Signal Signal Transfer Characteristics Characteristics vOUT C' A=A'
B ≅ B'
C
E'
D VSD2 > VSG2 -VT2 VDD - vOUT > VDD - VGG - VT2 v OUT < VGG + VT2
M1 sat. M2 non-sat.
.8VDD
M1 non-sat. M2 sat.
.4VDD
vout = VGG + VT2 VGG = 0
.2V DD F=F' 0
.8VSS .6VSS .4VSS .2VSS .2VSS
.2VDD .4VDD .6VDD .8VDD VDD
.4VSS
.8VSS VSS
v IN
G H
.6VSS
VDS1 > VGS1 - VT1 v OUT - VSS > vIN - VSS - VT1 v OUT > v IN - VT1
vOUT =vin - VT1
M1 & M2 saturated
.6VDD
E
M2 non-sat. M2 sat.
VSS
vOUT =vin + VT2
VDD
D'
I
J
K
G' H' I'
J'
K'
Advantages: 1. High gain. 2. Large output signal swing. 3. Large current sink and source capability in push pull inverter.
High Gain, CMOS Inverters Small Signal Characteristics Model +
+
vin
gm1vin
r ds1
gm2vin
r ds2
vout
-
-
Small Signal Voltage Gain: vOUT = − gm1 v in +g m2 v in r ds1||r d s 2 OR
− vout − g m 1 +g m 2 vin = g ds 1 +g d s 2 =
2 ID
W1 KN' L + 1 λ1 + λ2
W2 KP' L 2
=
K !!! !! ! ID
Set g m2 = 0 for the current source inverter W1 W2 Assume that i D = 1 µA and L = L , using the values of Table 1 2 3.1-2 gives vOUT vin = − 328 = −194 194
for the push-pull inverter (L=10 µm) for the current source inverter (L=10 µm )
Small Signal Output Resistance: rout = g
1 ds 1 +g d s 2
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-13
High Gain, CMOS Inverters Dependence of Gain upon Bias Current log AV
1000
100 weak inversion strong inversion
10
1
0.1µA
1µA
10µA
100µA
1000µA
ID
Limit is the subthreshold current where square law characteristic turns into an exponential characteristic. Assume that the level where subthreshold effects begin is approximately 0.1 µA, the maximum gains of the CMOS inverters become: The CMOS inverters become: Push-Pull: -1036 Curr Curren ent tso souurce rceloa load: d: -615 Currentsinkload:-422
W L = 1, L=10 µm
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-14
Frequency Response of CMOS Inverters General Configuration
gm1)
X = vOUT ; Active Load CMOS Inverter (g m = gm1) X = V GG ; CMOS Inverter with a Current Source Load (g m = X = v IN ;
CMOS Push Pull Inverter (g m = gm1 + gm2) VDD
C GS2
C GD1
X C GD2
M2 C BD2
+
vin CGD1
vin
C BD1
CL
+ g m vin
R
CT
-
v out -
M1
VSS (b)
(a)
(a) General configuration of an inverter illustrating parasitic capacitances. (b) Small signal model of (a) CGD1 and CGD2 are overlap capacitances CBD1 and C BD2 are the bulk-drain capacitances CL is the load capacitance seen by the inverter Frequency Response vOUT −g m R ω 1(1 −s/z) , vIN = s+ ω 1 R=g
1
ds1+gds2+gm2
gm 1 ω 1 = RC and z = C GD1
(gm2 = 0 for push pu sh pull and current source inverters)
C ≈ CGD1+CGS2+CBD1+CBD2+CL (Active load inverter) C ≈ CGD1+CGD2+CBD1+CBD2+CL (Current source & push-pull inverter) if g mR >> 1
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-15
Frequency Response of CMOS Inverters Dependence of Frequency Response on Bias Current When g m2 ≠ 0
(active load inverter): W 2K' 1 L ID R≈g or ω -3dB = ~ ID C m2 When g m2 = 0 (pu (push pull and and cu curren rrentt so source rce in invert erter): er): ( λ 1 + λ 2 )I ) I D 1 R = (λ + λ ) I or ω -3dB = ~ ID C 1 2 D Example: Find the −3dB frequency for the CMOS inverter using a current source load and the CMOS push pull inverter assuming that i D = 1µA, CGD1=CGD2=0.2pF and C BD1=CBD2=0.5pF W1 W2 Using the parameters of Table 3.1-2 and assuming that L = =1 1 L2 Gives, For the active load CMOS inverter, gm2 ω-3dB = C = 3.124x10 -6 rads/sec or 512KHz For the push pull or current source CMOS inverter, g gd1 gd 1+g ds 2 = 14.3x10 3 rads/sec or 2.27 KHz ω -3dB = C gm1 z=C = 29.155 Mrads/sec or 4.64 MHz GD1 The reason for the difference is the higher output resistance of the push pull or current source CMOS inverters
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-16
NOISE IN MOS INVERTERS
Noise Calculation
RL RS
i2d
v IN +
RL
iL2
RS
-
2
We wish to determine the equivalent input noise voltage, v n as shown below:
RL v2n RS
2 8 id = KTg m (A2 /Hz) 3 4K T 2 2 4KT iL = RL (A /Hz)
Comments: 1.) 1/f noise has has been ignored. 2.) Resistors are noise-free, they are used to show topological aspects. aspects. Can repeat the noise analysis for the resistors if desired.
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-17
Noise in an Active Load Load Invert Inv erter er VDD 2 en2
1+ KP' BP L1 2 K N' BN L2 2 = en1 KP' W2L1 2 1 + K N' W1L2
To minimize minimize noise - Reduce e n1 and en2 .
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-20
SUMMARY OF MOS INVERTERS
Inverter Type AC Voltage Gain
AC Output Resistance
Bandwidth (CGB=0)
Equivalent, input-referred,meansquare noise voltage
p-channel active load sinking inverter
-gm1 gm2
1 gm2
gm2 CBD1 +CGS1 +CGS2+CBD2
g 2 v2n1 gm1 +v2n2
n-channel active load sinking inverter
-gm1
gm2+gmb2
1 gm2 +gmb2
gm2+gmb2 CBD1+CGD1+CGS2+CBD2
g 2 v2n1 gm1 +v2n2
Current source load sinking inverter
-gm1 gds1+gds2
1 gds1+gds2
gds1+gds2 CBD1+CGD1+CGS2+CBD2
g 2 v2n1 gm1 +v2n2
Push-Pull inverter
-(gm1+gm2) gds1+gds2
1 gds1+gds2
gds1+gds2 CBD1+CGD1+CGS2+CBD2
v2n1 gm1 v2n2 gm2 gm1+gm2 + gm1+gm2
m2
m2
m2
2
2
Allen and Holberg - CMOS Analog Circuit Design
Page VI.1-21
KEY MOSFET RELATIONSHIP USEFUL FOR DESIGN
Assume MOSFET is in saturation. 1. )
2.)
3. )
KW iD = 2L (vGS − VT) 2 or vDS(sat) = gm =
2iD KW/L
2IDKW L
v GS =
2iD KW/L − VT
or
KW iD(sat) = 2L vDS(sat)2
or
KW gm = L (VGS − V T)
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-1
VI.2 - DIFFERENTIAL AMPLIFIERS Definition of a Differential Amplifier
v1 v2
+
Differential Amplifier
vOUT
-
v 1 +v 2 vOUT = A VD(v1 − v2) ± AVC 2
Differential voltage gain = A VD (100) Common mode voltage gain = A VC (1) AVD Common mode rejection ratio = A (1000) VC VOS(out) Inpu Inputt offs offset et volt voltag agee = VOS(in) = A (2-10mV) VD Common mode input range = V ICMR (VSS+2V
Allen and Holberg - CMOS Analog Circuit Design
P-Channel P-Channel Input Input Pair Differential Amplifier Amplifie r
VDD IDD
vGS1 vG1
-
+
+ M1
iD1=iD3
M2
iD2
vGS2 -
iOUT
iD4 M3
M4
VSS
vG2 vOUT
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-4
Large Signal Analysis of CMOS Differential Amplifiers iD1
iD2
M1
+
vGS1
M2
-
ISS 2iD1
(1). vID = v GS1 − vGS2 = (2). ISS = i D1 + i D 2 Solving for i D1 and iD2 gives, ISS (3). iD1 = 2 +
β −
ISS 2 vID
+ -
vGS2
2iD2
β
β
β 2 v 2ID
β
β 2 v 2ID
ISS − 4ISS2
And ISS ISS (4). iD2 = 2 − 2 vID
Where vID < 2
ISS − 4ISS2 ∂ iD 1 βISS g m = ∂v = 4 ID
IS S
β
I
ISS 1
iD2
.8 .6 .4
iD1 .2 -2
- 2
2
2
vID ISS ß
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-5
Transconductance Characteristics of the Differential Amplifier Circuit VDD = 5V 9u/3u
9u/3u iD1 3u/3u
+ v+
iD2 3u/3u
vOUT 50K v-
3u/3u
3u/3u
VSS = -5V Simulation Results 140uA 120uA 100uA
iD1
80uA 60uA 40uA 20uA 0uA -5V
i D2 - 3V
- 1V
v+
1V
3V
5V
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-6
Voltage Transfer Curve of n-channel Differential Amplifier VDD 9u/3u
9u/3u
50kΩ
vOUT v+
3u/3u
3u/3u
v-
3u/3u
3u/3u
VSS
5 v- = 0V
3
v- = -1V
v- = 1V e g a t l 1 o V t u p t u -1 O
v- = -1V v- = 1V
-3
v- = 0V
-5 -5
-3
-1
1
Positive Input Voltage
3
5
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-7
Voltage Transfer Curve for a p-channel Differential Amplifier VDD 9u/3u
v+
9u/3u
v-
9u/3u
9u/3u
vOUT 3u/3u
3u/3u
50kΩ
VSS 5
v- = 1V
3
v- = 0V e g a t l 1 o V t u p t u -1 O
v- = -1V
v- = 1V
-3
v- = 0V v- = -1V
-5
-5
-3
-1
1
Positive Input Voltage
3
5
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-8
COMMON MODE INPUT RANGE P-Channel P-Channel Input Input Pair Differential Amplifier Amplifie r VDD + M5 vSD5 +
vG1
-
vSG1 M1
+
+
vSG2
vSD1
M2
-
vG2
-
vOUT M3
M4
+
vGS3 -
VSS
Lowest common mode input voltage at gate of M1(M2) vG1(min) = V SS + v GS3 + v SD1 − vSG1 for saturation, the minimum value of v SD1 = v SG1 − |V T1| Therefore, v G1(min) = V SS + v GS3 − |V T1| or, v G1(min) = VSS +
ISS
β + VTO3 − |VT1|
vG1(max) = V DD − vSD5 − vSG1 = V DD − vSD5 −
2ID1
β1 − |V T1|
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-9
COMMON MODE RANGE-CONT'D Example Assume that VDD varies from 8 to 12 volts and that V SS = 0. Using the values of Table 3.1-2, find the common mode range for worst case conditions. Assume that I SS = 100 µA, W1 /L1 = W2 /L2 = 5, W 3 /L3 = W4 /L4 = 1, and v SD5 = 0.2V. Include the worst case value of K' in the calculations. If V DD varies 10 ± 2V, then we get vG1(max)
= VDD − v SD5 − = 8 − 0.2 −
vG1(min)
= V SS + =0+
ISS
β1 − |V T1|
100 5x7.2 − 1.2 = 6.6 − 1.67 = 4.99V ISS
β3 + VTO3 − |V T1|
100 1x18.7 + 1.2 − 0.8 = 0.4 + 2.31 = 2.71V
Therefore, the input common mode range of the p-channel input differential amplifier is from 2.71V to 4.99V
Allen and Holberg - CMOS Analog Circuit Design 8V
4.99V Input Common Mode Range ≈ 2.22V 2.71V
0V
Page VI.2-10
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-11
CMOS CMOS DIFFERENTIAL AMPLIFIER Small Signal Differential Mode Gain N-Channel input differential amplifier VDD M3
M4
vOUT M1
vG1
M2
VGG
vG2
M5
VSS Exact small signal model rds1
D1=G3=D3=G4 G1 +v -G2 id + + vg1 _
1 v g2 g m3 _
rds2
g m1v gs1
+ v gs4
rds3
S1=S2 + rds5
_
D2=D4
gm2v gs2
vs1 =vs2 ≈ 0 _
vout
rds4
g m4vgs4
v gs1 = -v gs2 ⇒ v s1 ≈ vs2 ≈ 0
S3
+
S4
Simplified small signal model using symmetry D1=G3=D3=G4 D2=D4
G1 G2 +v id + + vg1 _
1 v g2 g m3 _
+
gm1v gs1
g m2vgs2
_
vgs1 = 0.5vid and v gs2 = −0.5vid
+
gm4v gs4
vout
v gs4 rds3
rds2
i'out
r ds1 S1=S2=S3=S4
r ds4 -
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-12
CMOS CMOS DIFFERENTIAL AMPLIFIER Unloaded Differential Transconductance Gain (RL =0) g m 1 g m 4 (r ds 1 ||r ds3 ds 3 ) iout ' = −gm4 vgs4 − gm2 vgs2 = 1+g ( r ||r ) vgs1 − gm2 vgs2 m 3 d s1 d s3 If gm3 (r ds1 || r ds3 ) >> 1, gm3 = g m4 , and g m1 = g m2 = g md , then iout ' ≈ gm1 vgs1 − gm2vgs2 = g md(v gs1 − vgs2 ) = gmdvid or io u t' ≈ gm d v id =
KN'WI SS vi d L
Unloaded Differential Voltage Gain (RL = ∞) gmd 2 v o u t ≈ g +g v i d = (λ + λ ) ds 2 ds4 N P
KN'W ISS L v i d
Example If all W/L ratios are 3 µm/3 µm and I SS = 10 µA, then gmd(N-channel) = (17x10 -6)(10x10-6) = 13 µA/V gmd(P-channel) (P-channel) = (8x10 -6)(10x10 -6) = 8.9 µA/V and
vout 2(13x10 -6) vid (N-channel) = (0.01+0.02)10x10-6 = 86.67 vout 2(8.9x10-6) vid (P-channel) = (0.01+0.02)10x10 -6 = 59.33
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-13
INTUITIVE SMALL SIGNAL ANALYSIS OF MOSFET CIRCUITS Principle: Consider only small changes superimposed on the dc conditions. conditions. Technique: Identify the transistor(s) that convert input voltage to current (these transistors transistor s are called the active devices). Trace the currents to where they flow into the resistance seen from a given node and multiply this resistance times the currents to find the voltage at this node. Example - Differential Amplifier
VDD
gm1vin 2
gm1vin 2
M3
M4
gm1vin 2 +
gm2vin 2
M1 vin 2 -
VGG
Rout
M2 v + in -
vOUT
vin + 2
M5
VSS Current flowing into the output node (drains of M2 and M4) is gm1vin gm2vin iout = 2 + 2 Output resistance, R out, seen at this node is 1 R out = r ds2 ||r ds4 = g +g ds2 ds4 Therefore, the open circuit voltage gain is vout gm1+gm2 gm1 gm2 vin = 2(gds2+gds4) = gds2+gds4 = gds2+gds4
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-14
CMOS CMOS DIFFERENTIAL AMPLIFIER Common Mode Gain The differential amplifier that uses a current mirror load should theoretically have zero common mode gain. For example:
Therefore, the common mode gain will approach zero and is nonzero because of mismatches in the gain between the two paths.
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-15
CMOS CMOS DIFFERENTIAL AMPLIFIER Consider the following differential amplifier VDD M3
M4
vO1
vO2
vIC
M1
VGG5
vIC
M2
M5
VSS Use of symmetry to simplify gain calculations VDD M3
M4
vO1
vO2
vIC
M1
VGG
1 xM5 2
M2
1 xM5 2
VSS
vIC
VGG
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-16
CMOS CMOS DIFFERENTIAL AMPLIFIER Small signal model gmbs1vbs1
+ vIC=vg1 -
rds1
+ vs1 -
2rds5
+
gm1 vgs1
rds3
gm3 vo1
vo1 -
gm1 +gmbs1 vs1
gm1 vg1
rds1
r ds1
+ vIC=vg1 2rds5 -
+ vs1 -
+
gm1+gmbs1 vs1 1 gm1 +gmbs1
r ds3
1 gm3
gm1vg1
vo1 -
Writing nodal equations 0.5g ds +g d s1 +g mbs1 vs1 − gds1 vo1 = gm1vIC + g ds3 −g d s 1 +g m 1 +g mbs1 vo1 + g ds1 +g ds 3 +g m 3 vo1 = −gm1 vIC
vo1 Solving for v gives, IC vo1 −0.5gm1gds5 vIC = gds3+gm3 0.5g d s +g m 1 +g mbs1+ g d s 1+0.5g ds1 ds 1 g d s 5 or
vo1 −0.5gm1gds5 −gds5 ds 5 ≈ ≈ vIC gm3 g m 1 +g mbs1 2gm3
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-17
COMMON COMMON MODE REJECTION RATIO (CMRR) (CMRR) Differentialmodegain Avd CMRR = Commonmodegain = A vc For the previous example, gm1 gm3
2(g 2( g m1 +g mbs1) 2g m1 |CMRR| = = ≈g gds5 gm1gds5 ds5 2g g +g mbs1 m3 m 1 Therefore, current sinks/sources with a larger output resistance(r ds5 ) will increase the CMRR. Example Let all W/L ratios be unity, I SS = 100 µA, and use the values of Table 3.1-2 to find the CMRR of a CMOS differential amplifier. gm1 = 2x17( µA/V2)x100µA = 58.3µS gds5 = 0.01V-1 x 100 µA =1µS Therefore, |CMRR| = 116
VSS CT = tail capacitor (common mode only) CM = mirror capacitor = C dg1 + C db1 + C gs3 + Cgs4 + Cdb3 COUT = output capacitor ≈ Cbd4 + Cbd2 + Cgd2 + CL Small Signal Model +
+
g m1vgs1
v gs1 = vgs2 = vid /2 -v id /2 -
-
+
+
r ds3
v gs3
C gd4 rds2
rds1
1 g m3
-
CM
gm4v gs3 g m2v gs2
r ds4
C OUT
v out -
We will examine the frequency response of the differential amplifier in more detail later.
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-19
SLEW RATE Slew rate is defined as an output voltage rate limit usually caused by the current necessary to charge a capacitance. dV i.e. i = CdT For the CMOS differential amplifier shown,
VDD M3
M4 CL
+
M1
+ v - O
M2
vIN ISS
VSS ISS Slew rate = C L where C L is the total capacitance seen from the output node to ground. If C L = 5pF and I SS = 10 µA, then the SR = 2V/ µS
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-20
CMOS DIFFERENTIAL AMPLIFIERS NOISE Assumption: Neglect thermal noise(low frequency) and ignore the thermal noise sources of r d and r s . Therefore: KF AF 2 ind = iD (AF = 0.8 and KF = 10 -28) 2 fCoxL or 2
ind
KF 2 vnd = g 2 = 2f µ C 2WL iD(AF-1) o ox m
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-21
VDD IDD
2 veq1
2 veq2
M1
M2
i2o M3
M4 2 veq3
2 veq4
+ -
vOUT VSS
Allen and Holberg - CMOS Analog Circuit Design
Page VI.2-22
CMOS DIFFERENTIAL AMPLIFIERS NOISE Total output noise current is found as, 2
2
2
2
2
iod = g m1 2 v1 + g m22 v2 + g m32 v3 + g m42 v4 2
Define vneq as the equivalent input noise voltage of the differential amplifier. Therefore, 2
It is desirable to increase the transconductance of M1 and M2 and decrease the transconductance of M3 and M4. (Empirical studies suggest p-channel devices have less noise)
In terms of voltage spectral-noise densities we get, gm3 2 2 2 2 2 2 eeq = en1 + en2 + g en3 + en4 m1
1/f noise Let
KF B 2 en = 2fC WLK' = fWL ox 2
2
assume en1 = en2
∴
2
2
and en3 = en4
K N ' B N L1 2 2BP 2 eeq (1/f) = fW L 1+ K 'B L P P 3 1 1 1) Since B N ≈ 5BP use PMOS for M1 and M2 with large area. L1 K P'B P 1 2 2) Make L < K 'B ≈ 12.5 so that eeq (1/f) ≈ 3 N N
Thermal Noise
W3 K N ' L 16KT(1+η1) 2 1+ 3 eeq (th) = W1 W1 K P ' L 3 2K P'I 1 L 1 1
Objective Prevent Cgd of the inverter invert er from f rom loading the previous stage. Gives very high gain. Cascode Amplifier Circuit V DD
V GG2
Miller effect:
M3 vout
VGG1
M2
Cgd1 + vin
M1 v 1 VSS
Large Signal Characteristics When V GG1 designed properly, vout(min) = V on1 + Von2
Inverter Cin ≈ Gain x C gd1 Cascode Cin ≈ 3Cgd1 v1 v ≈ 2 in
Page VI.3-2
Allen and Holberg - CMOS Analog Circuit Design
CASCODE AMPLIFIER-CONTINUED Small Signal Model
gm2 v1
+
rds2
gmbs2 v1
+
+ vin
-
rds1
v1
gm1 vin
vout
rds3
-
(gm2 +gmbs2 )v1
C1
rds2
+ vin
+ C2 gm1vin
-
rds1
v1
-
1 gm2 (1+η2 )
+ C3
rds3
gm2(1+ η2 )v1
vout
-
Nodal Equations: (gm1 − sC1)vin + (g m2 + g mbs2 + g ds1 + g ds2 + sC 1 + sC 2)v1 − (gds2)vout = 0
−(gds2 + gm2 + gmbs2)v1 + (g ds2 + gds3 + sC 3)vout = 0 Solving for v out /vin gives (sC1-gm1)gm2(1+η) ≅ 2 s (C3C1+C3C2)+s(C1+C 2)(g ds2 +gds3)+C3gm2(1+ η)+gds3gm2(1+η)
Page VI.3-3
Allen and Holberg - CMOS Analog Circuit Design
Small Signal Characteristics Low-frequency Gains:
− g m 1 ( g ds2 vout ds 2 +g m 2 +g mbs2 ) vin = g d s1 g ds 2 +g d s3 ( g m 2 +g mbs2 +g d s1 +g d s2 ) −gm 1
2K'(W1 /L 1)ID1 ≈ g = λ3ID3 ds3 Also (see next page), v1 −2gm1 vin = g m 2 (1+η 2 ) Gain Enhancement: VDD VGG2
M4
M3
vout VGG1
M2 I4
I2 I1 vin
M1
vout −g m 1 vin ≈ gds3 2K'W1 I1 vout L1 vin ≈ λI 2 But I 1 = I2 + I4
VSS
I4 = 24I2 ⇒ x5 Gain enhancement
Page VI.3-4
Allen and Holberg - CMOS Analog Circuit Design
Voltage Gain of M1: v1 − g m 1 vin = gm2 ? What is the small signal resistance looking into the source of M2? Consider the model below: i1 + v1 = vs2
gm2 vgs2 r ds2
r ds3
-
vs2 = (i 1 + g m2 vgs2 )r ds2 + i 1rds3 = r ds2 i1 + g m2 (−vs2 )r ds2 + i 1rds3 ds 3 or
vs2 (1 + g m2 rds2 ) = i1(r ds2 + r ds3 )
Therefore, vs2 r ds 2 + r d s 3 r d s 2 +r d s 3 1 r d s 3 R = i = 1+g r = g 1+ r ≈ g r 1 m2 ds2 m2 ds2 ds 2 m2 ds 2 Some limiting cases: 1 rds3 = 0 ⇒ R = g m2 2 rds3 = r ds2 ⇒ R = g m2 and rds 3 rds3 >> r ds2 ⇒ R = g r m2 ds2 ds 2 Therefore, the gain v in to v 1 is v1 − g m1 (g ds2 −2gm1 −2g m1 ds 2 +g ds3 ds 3 ) vin ≈ (g m2 +gmbs2 )g d s3 ≈ g m 2 +g mbs2 ≈ gm2
Page VI.3-5
Allen and Holberg - CMOS Analog Circuit Design
CASCODE AMPLIFIER-CONTINUED High Resistance Driver for the Inverter M1-M2
−gm1 gm1 1 s − G1G3 C2 1+R (C +C )+R (C +C )+g R R C s+(C C +C C +C C )R R s2 1 1 3 3 2 3 m1 1 3 2 1 2 1 3 2 3 1 3
Page VI.3-6
Allen and Holberg - CMOS Analog Circuit Design
Note:
s s 1 1 s2 d(s) = 1 + as + bs 2 = 1 − p 1 − p = 1 − s p + p + p p 1 2 2 1 2 1 If |p2| >> |p 1| , then s s2 d(s) ≈ 1 − p + p p 1 1 2
or
1 p 1 = − a
and
a p 2 = − b
Using this technique we get,
−1 −1 p1 ≈ R1(C1+C3)+R3(C2+C3)+gm1R1R3C2 ≈ g R R C m1 1 3 2 (Miller effect on C 2 causes p 1 to be dominant; C M ≈ gm1R2Cgd1)
−gm1C2
p2 ≈ C C +C C +C C 1 2 1 3 2 3
Page VI.3-7
Allen and Holberg - CMOS Analog Circuit Design
CASCODE AMPLIFIER - CONTINUED How does the Cascode Amplifier solve this problem? VDD M5 VGG5 M2 VGG2
M4 1 ro =g +g ds3 ds4
vout
Cgd1 iin M1
M3 VSS Cgd1 iin
r1
+ v1 -
rds2 C2 gmv1
+ v2 r2 - gm2(1+η)v2
+ C3 r 3
r1 = r o = (g ds3 + g ds4 )-1 C2 = Cgs2 + Csb2 + Cdb1 + Cgd1
1 r 2 = g d s 1 +g m 2 (1+ η ) -1 ≈ g m2 C3 = Cgd2 + Cdb2 + Cgd5 + Cdb5 + CL gm2 -1 1 r 3 ≈ g g +g d s 5 ≈ g ds5 d s1 d s 2
vout -
Page VI.3-8
Allen and Holberg - CMOS Analog Circuit Design
Cascode amplifier with higher gain and output resistance
VDD
io
VGG4 M4 VGG3 M3 VGG2
gm2 v1 Vout
r ds2
gmbs2 v1
G1 M2
Vin VSS
-
g m3 v4
gmbs3 v4
r ds3
vout
D1=S2
+
+ vin
M1
+
D2
gm1 v in
v1
-
+ r ds1
r ds4
v4 -
' =rds3
-
Allen and Holberg - CMOS Analog Circuit Design
Page VI.4-1
VI.4 - OUTPUT AMPLIFIERS Requirements 1. Provide sufficient output power in the form of voltage or current. 2. Avoid signal distortion for large signal swings. 3. Be efficient. 4. Provide protection from abnormal conditions. Types of Output Stages 1. Class A amplifier. 2. Source follower. 3. Push-Pull amplifier ( inverting and follower). 4. Substrate BJT. 5. Negative feedback (OP amp and resistive).
Page VI.4-2
Allen and Holberg - CMOS Analog Circuit Design
CLASS A AMPLIFIER VDD VGG2
M2 IQ
Vin
Iout
M1
Vout
CL
RL
VSS
KnW1 2−I Iout (V V V ) − − DD SS T1 Q 2L1 KpW2 Iout = 2L (VDD − VGG2 − |VT2|) 2 < Iout + 2 +=
|Iout| determined by: dvout 1. |I out| = C L dt = C L (slew rate) vout(peak) 2. |I out| = RL Vout(peak) 2 Efficiency = P = ( V +V ) ≤ 25% supply D D SS
PRL
rout = g
1 1 = d s1 +g d s 2 2λID
(typically large)
Page VI.4-3
Allen and Holberg - CMOS Analog Circuit Design
SOURCE FOLLOWER N-Channel
Push Pull VDD
vIN
M1
M1 vOUT
VGG
VDD
vIN
M2 VSS
Large Signal Characteristics vOUT = v IN − vGS1 Maximum Output Swing Limits vOUT(MAX) = V DD − VT1 (VT1 greater than V T0 because of v BS) Single Channel Follower: vOUT(MIN) = V SS Push Pull Follower: vOUT(MIN) = VSS + |VT2| (VT2 greater than V T0 because of v BS)
vOUT
M2 VSS
Page VI.4-4
Allen and Holberg - CMOS Analog Circuit Design
SOURCE FOLLOWERS Small Signal Characteristics Single Channel Follower (Current source and active load): C1
+
+
gm1 vin
vin
gm1 vout
-
gmbs1 vout
rds1
rds2
C2
gm2vgs2
vout
-
Small Signal Voltage Transfer Function: vout gm1 vin = gds1+gds2+gm1+gmbs1+gm2whereg m 2 =0ifv GS2 = V G G Example:
W 10 µ m If V DD= −VSS =5V, vOUT = 0V, i D = 100µA, and L =10 µ m ,
then;
vout 41.23 = vin 1+1+41.23(1+0.2723)+41.23 = 0.4309 when v GS2 = vOUT vout 41.23 = vin 1+1+41.23(1+0.2723) = 0.751 when v GS2 = VGG vout Approximation gives v ≈ 0.786 (g ds1 = g ds2 ≈ 0) in
Output Resistance: 1 r out= g +g +g +g whereg m 2 =0ifv G S 2 = V G G ds1 ds2 m1 mbs1+gm2 rout = 10.5 KΩ (vGS2 = v OUT ) and r out = 18.4 KΩ (vGS2 = V GG)
Small Signal Voltage Transfer Function: vout g m 1 +g m 2 vin = g d s1 +g d s2 + g m 1 +g mbs1 +g m 2 +g mbs2 Example: W 10µm If V DD = −VSS = 5V, v OUT = 0V, i D = 100 µA, and L = 10µm then, vout 41.23+28.28 = vin 1+0.5+41.23(1+0.2723)+28.28(1+0.1268) = 0.81 Output Resistance: 1 r o u t = g +g +g +g =11.7K Ω ds1 ds2 m1 mbs1 +g m 2 +g m b s 2
Page VI.4-6
Allen and Holberg - CMOS Analog Circuit Design
PUSH-PULL INVERTERING CMOS AMPLIFIER ConceptVDD
VTR2 vIN VTR1
M2
+ + -
Iout
Vout
M1
CL
RL
VSS
ImplementationVDD
M5
M6
M1
M3
VGG3
M2
M4
VGG4
Iout
Vout
vIN
M7 VSS
CL
M8
RL
Page VI.4-7
Allen and Holberg - CMOS Analog Circuit Design
PUSH-PULL SOURCE FOLLOWER VDD M2
Iout
VTR
Vout
vIN
CL
M1
RL
VSS VDD VGG6
M6 M2 M5
Iout
Vout
M4 M1
vIN
M3
VSS
CL
RL
Page VI.4-8
Allen and Holberg - CMOS Analog Circuit Design
USE OF NEGATIVE FEEDBACK TO REDUCE ROUT VDD
error amplifier
M2 - +
vIN
Iout
Vout
- + CL
M1
RL
VSS
Use of negative feedback to reduce the output resistance of Fig. 6.3-4. VDD M2 R1 vIN
R2
Iout
M1
Vout
CL
RL
VSS
Use of resistive feedback to decrease the output resistance of Fig.6.3-4.
Allen and Holberg - CMOS Analog Circuit Design
VI.5 - SUMMARY • Analog Amplifier Building Blocks Inverters - Class A Push-Pull - Class AB or B Cascode - Increased bandwidth Differential - Common mode rejection, good input stage Output - Low output resistance with minimum distortion
Page VI.5-1
Allen and Holberg - CMOS Analog Circuit Design
SECTION 7 - COMPARATORS
Page VII.0-1
Allen and Holberg - CMOS Analog Circuit Design
Page VII.0-1
VII. COMPARATORS Contents
VI.1 VI.2 VI.3 VI.4 VI.5
Compa Comparat rators ors Mod Model elss and Perfo Performa rmanc ncee Devel Develop opmen mentt of a CMOS CMOS Comp Compara arato torr Design Design of a Two-S Two-Stag tagee CMOS CMOS Compara Comparator tor Other Other Types Types of Compa Comparat rators ors Improv Improveme ement nt in Compar Comparato atorr Perform Performanc ancee A. Hysteresis B. Autozeroing VI.6 High Speed Comparators Organization Chapter 10 D/A and A/D Converters
Chapter 11 Analog Systems
SYSTEMS
Chapter 7 CMOS Comparators
Chapter 8 Simple CMOS OTA's
Chapter 9 High Performance OTA's
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
DEVICES
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
Allen and Holberg - CMOS Analog Circuit Design
Page VII.1-1
VII.1 - CHARACTERIZATION OF COMPARATORS What is a Comparator? A comparator is a circuit which compares two analog signals and outputs a binary signal based on the comparsion. (It can be an op amp without frequency compensation.) Characterization Characterization of Comparators Compar ators We shall characterize the comparator by the following aspects: • Resolving capability • Speed or or propagation propagation time delay • Maximum signal swing limits • Input offset voltage • Other Considerations Noise Power Etc.
Allen and Holberg - CMOS Analog Circuit Design
Page VII.1-2
VOLTAGE COMPARATORS
Definition Definition of a Comparator Compar ator VA
+
VB
-
Noninverting
VOUT
VOUT VOH
V O H whenV A ≥ V B VOUT = V OLwhenVA <V B
VA - VB VOL
Inverting VOUT
V O L whenV A ≥ V B VOUT = V OHwhenV A ≤ V B
VOH
VA - VB VOL
Allen and Holberg - CMOS Analog Circuit Design
Page VII.1-3
COMPARATOR PERFORMANCE
1. Speed or propagation time delay. The amount of time between the time when V A - V B = 0 and the output is 50% between initial and final value. 2. Resolving capability. The input change necessary to cause the output to make a transition between its two stable states. 3. Input common mode range. The input voltage range over which the comparator can detect V A = V B. 4. Output voltage swing (typically binary). 5. Input offset voltage. The value of V OUT reflected back to the input when V A is physically connected to V B.
Allen and Holberg - CMOS Analog Circuit Design
Page VII.1-4
APPROACHES TO THE DESIGN OF VOLTAGE COMPARATORS
Open Loop Use of a high-gain differential amplifier. V O H -V O L Gain = resolutionofthecomparator Regenerative Use of positive feedback to detect small differences between two voltages, V A and VB. I.e., sense amplifiers in digital memories. Open Loop - Regenerative Use of low gain, high speed comparator cascaded with a latch. Results in comparators with very low propagation time delay. Charge Balancing Differential charging of a capacitor. Compatible with switched capacitor circuit techniques. Type
Offset Voltage (Power supply)
Resolution
Speed (8 bit)
Open-loop
1-10 mV
300 µV (±5V)
10 MHz
Regenerative Charge Balancing
0.1 mV
50 µV (±5V)
50 MHz
0.1 mV
5 m V ( 5V )
30 MHz
Allen and Holberg - CMOS Analog Circuit Design
Page VII.1-5
COMPARATOR MODELS - OPEN LOOP
Zero Order Model VOUT VOH +
-
VP - VN
VOL
Model VP +
+
+
f o VP - VN VN
-
VO
-
V O H for ( V P -V N ) f o( o( V P -V N ) = V OLfor( V P -V N )
-
≥ 0 ≤ 0
Allen and Holberg - CMOS Analog Circuit Design
Page VII.1-6
COMPARATOR MODELS - CONT'D
First Order Model Transfer Curve VOUT VOH VIL
VP - VN
VIH VOL
Model VP +
+
+
f 1 VP - VN VN
-
VO
-
V O H for ( V P -V N ) ≥ V IH
f 1( 1( V P -V N ) = AV( V P -V N ) forV I L ≤ ( V P -V N ) ≤ V I H VOLfor( V P -VN ) ≤V IL
Allen and Holberg - CMOS Analog Circuit Design
Page VII.1-7
COMPARATOR MODELS - CONT'D
First Order Model with Offset Transfer Curve
VOUT VOH
VOS VIL
VP - VN
VIH VOL First Order Model with Offset
VP
+
+- VOS
-
VP' +
+
+
f 1 VP' - VN' -
VN
-
VN'
Time Response of Noninverting, first order model VOH v = VOH + VOL 2
VOUT VOL VIH VP - VN
v = VIH + VIL 2
tP VIL
VO
Time
Allen and Holberg - CMOS Analog Circuit Design
Page VII.2-1
VII.2 - DEVELOPMENT OF A CMOS COMPARATOR SIMPLE INVERTING COMPARATOR
VDD vN
M2 I2 IB M1
VBIAS
vO
VSS Fig. 7.2-1 Simple inverting comparator
∆VIN
VDD
vO
vN
VTRP
Fig. 7.2-2 DC transfer curve of a simple comparator Low gain ⇒ Poor resolution VTRP = f V D D + process parameters
Allen and Holberg - CMOS Analog Circuit Design
Page VII.2-2
CALCULATION OF THE TRIP POINT, V T R P
vO VDD
VDD VIN
c t. vO = V IN + VT2 a 2 M s a t. 2 M
M2 vO
VBIAS
M1
M1 sat. M1 act.
VBIAS - VT1
VSS Operating RegionsvDS1 ≥ vGS1 - V T vSD2 ≥ vSG2 - VT2
VSS VSS
vN
VTRP
VDD
VIN
‘ vO - V SS ≥ VBIAS - V SS - V T1 v O ≥ V BIAS -V T 1 ‘
VDD - v O ≥ VDD - v IN - VT2 v O ≤ v I N + VT2
Trip PointAssume both M1 and M2 are saturated, solve and equate drain currents for V TRP . Assume λ ≈ 0. KN W1 2 iD1 = 2 L V BIAS - V S S -V T 1 1 K P W2 2 iD2 = 2 L V D D -v I N - VT2 2 iD1=iD2 ‘
vIN = VTRP = V DD- VT2 -
KN( W1 /L1) KP( W2 /L2) ( V BIAS -V S S -V T 1)
W1 W2 I.e. V DD = -V SS = 5V, V BIAS = -2V and KN L = KP L 1 2 VTRP = 5-1-(-2+5-1) = 4-2 = 2V
Allen and Holberg - CMOS Analog Circuit Design
Page VII.2-3
COMPARATOR USING A DIFFERENTIAL AMPLIFIER
VDD
M3
M4 vO M1
vP
M2
VBIAS
vN
M5
vO VOH = VDD VOH' M1 & M2 in saturation VOL' VOL VSS -1
+1
Gain is still low for a comparator
vP - vN Av
Allen and Holberg - CMOS Analog Circuit Design
Page VII.2-4
DERIVATION OF OUTPUT SWING LIMITS
VDD
v P >v N
M3 I1 vP
M4 M1
M2
I2
vO vN
ISS
VBIAS
M5 VSS
v P <v N
1. Current in M1 increases and current in M2 decreases. 2. Mirroring of M3-M4 will cause v O to approach V DD . 3. V OH' = V DD - VDS4 (sat) I4 ' VOH = V DD β 4
VOH ' = V DD V O H '=V D D -
I5 Kp'( W4 /L4) I5 Kp'( W3 /L3)
Assume vN is a fixed DC voltage 1. v O starts to decrease, M3-M4 mirror is valid so that I 1 = I 2 = I SS /2 . 2. V OL ' = v N - V GS2 + V DS2 when M2 becomes non-sat. we have VDS2(sat) = VGS2 - V T so that
4. Finally, v O ‘ V DD causing the mirror M3-M4 to no longer be valid and V OH ≈V DD . (I 2 = I 4 = 0 , I 3 = I 1 = I 5)
V O L '=v N -V T 2 3. For further decrease in v O, M2 is nonsat and therefore the V GS2 can increase allowing the sources of M1 and M2 to fall(as v P falls). 4. Eventually M5 becomes non-sat and I 5 starts to decrease to zero. M2 becomes a switch and v O tracks V S2(VDS5) all the way to V SS .
∴ V O L =V SS .
I1 still equals I2 due to mirror
Allen and Holberg - CMOS Analog Circuit Design
Page VII.2-5
TWO-STAGE COMPARATOR
Combine the differential amplifier stage with the inverter stage.
• Sufficient gain. • Good signal swing.
VDD M3
M4 M6
I8
M8
vN
M1
M2
M5 VSS
vP
vO
M7
Allen and Holberg - CMOS Analog Circuit Design
Page VI.3-1
VII.3 - DESIGN OF A TWO-STAGE CMOS COMPARATOR DC BALANCE CONDITIONS FOR TWO-STAGE COMPARATOR
• Try to keep all devices in saturation - more gain and wider signal swings.
• Based on gate-source and DC current relationship. I.e. if M1 and M2
are two matched devices and if V GS1 = V GS2, then I D1 = I D2 or vice versa. W1 Let S1 = L , 1 M1 and M2 matched gives S 1 = S2. M3 and M4 matched gives S 3 = S4. also, I 1 = I 2 = 0.5I5. From gate-source matching, we have S7 S6 VGS5 = V GS7 ‘ I 7 = I 5 S and I 6 = I 4 S ← Assume 5 4 VGS4 =VGS6 GS 6 For balance conditions, I 6 must be equal to I 7, thus I5 S7 S6 . I4 S5 = S4 I5 Since I = 2, then DC balance is achieved under the following: 4 S6 S . 7 ‘ VDG4 = 0 ‘ M4 is saturated. =2 S4 S5
(1) Find the the mismatch between i6 and i 7 i7 1+ λ N v D S 7 W7 /L7 1+(0.015)(5) i5 = 1+ λ N v D S 5 W5 /L5 = 1+(0.015)(3) (1) = 1.029 i6 1+ λ P v D S 6 W6 /L6 1+(0.02)(5) i4 = 1+ λ P v D S 4 W4 /L4 = 1+(0.02)(2) (2) = 2.115 i5 = 2i 4 ∴ i7 = (1.029)(2)i4 = 2.057i 4 and i6 = 2.115i 4 (2) Find how much v GS6 must be reduced to make i 6 = i7 ∆vGS6 = vGS6(2.115i 4) - v GS6 (2.057i 4) 2L ∆vGS6 = K W6 i 4 2.115- 2.057 = 14.11 mV P 6 (3) Reflecting ∆vGS6 into the input 2 KN( W2 /L2) A v(diff) = λ + λ = 89.9 I5 4 2 ∆vGS6 14.1mV ∴ VOS = A (diff) = 89.9 = 0.157 mV v
vO =5
i7
10 10 3V
VSS =0V
10
10 10
Allen and Holberg - CMOS Analog Circuit Design
Page VI.3-3
DESIGNING FOR COMMON MODE INPUT RANGE
VG1
VDD + VSG3 M3 + I5 /2 VDG1 + VDS1 + M1 VGS1 -
vG1(min) = VSS + V DS5 + V GS1 v G 1 (min)=V S S +V D S 5 +V T 1 (max)+ vG1(max) = VDD - VSG3 - V DG1 (sat) +
I5
VBIAS VSS
I5 2β 1
M5
v G 1 (max)=V D D -
VDS5 -
I5 2β3 - VT3(max) +VT1 (min)
where V DG1(sat) = -V T1
Example Design M1 through M4 for a CM input range 1.5 to 9 Volts when V DD = 10 V, I SS = 40µA, and V SS = 0V. Table 3.1-2 parameters with |V TN,P| = 0.4 to 1.0 Volts, I5 vG1(min) = VSS + V DS5 + β + VT1(max) 1
40 µA
β1 + 1 (assumed VDS5 ≈ 0.1V- it probably more reasonable to assume β1 is already defined and find β5) 1.5 = 0 + 0.1 +
KNW1 β1 = L = 250 µA/V2 ‘ 1 vG1(max) = VDD K W
W1 W2 L1 = L2 = 14.70
I5
β3 - |VT3(max)| + VT1(min)
β3 = PL 3 = 250 µA/V2 ‘ 3
W3 W4 L3 = L4 = 31.25
Allen and Holberg - CMOS Analog Circuit Design
Page VI.3-4
GAIN OF THE TWO-STAGE COMPARATOR
gm1vid
r ds2
r ds4
+ v1 gm6v1 -
+ r ds6
r ds7
vid = v P - vN gm1 gm6 A v = g +g g +g d s 4 ds 6 d s 7 ds 2 W1 W6 KNKP L L 1 6 Av = ( λ 2 + λ 4 ) ( λ 6 + λ 7 ) I1 I 6
2
W1 W6 Using L = 5, L = 5, λN = 0.015V -1, λP = 0.02V-1 1 6 and Table 3.1-2 values; 2 (17)(8)(5 )(5)(5) . -6 95199.10-6 Av = 10 = 2 (0.015+0.02) I1I6 I 1I 6 Assume I1 = 10 µA and I 6 = 100 µA Av = 3010 V OH -V - VO L = Resolution = 5 mV (assume) Av 5 then V OH - V OL = 1000 . 3000 = 15 Volts
vout -
Allen and Holberg - CMOS Analog Circuit Design
Page VI.3-5
PROPAGATION DELAY OF THE TWO-STAGE COMPARATOR
VDD signal swing less than the M4 output
M3 vN
VGS6 + -
M1
VBIAS
vP
M2
CL1
M6 i6 key node vO i7 CL2
M5
M7
i5 VSS VGS6 = V DD - v P +V D G 2
dv iC = C dt , ∆t = ∆v CI
∆ t2+
VTRP3
V VDD SS
VTRP3 ∆ t-2
∆t2+ = CL2 K W P 6 2 L6
V TRP3 -V S S
( V D D -v P -V D G 2 -|V T 6 |) 2 -I 7
V D D -V TRP3
∆t2- = C L2 W L 7 5
i L7 W5 5
Slew rate =
isource/sink CLi
Allen and Holberg - CMOS Analog Circuit Design
Page VI.3-6
CALCULATION OF COMPARATOR PROPAGATION DELAY
Find the total propagation delay of the comparator shown when the input vP goes from -1 to +1 in 2ns. Assume the trip point of the output(next stage) is zero. Total delay = 1st stage + 2nd stage delay delay
+5V 10 10
M3
vDO
vN
M1
40 10 C L1=0.3pF
M4
20 10
M2
vP
( v DO (t 0 )-V TRP2) CL1 , ∆t1 = I5 vDO(t0) = 5 because v P = -1V
VTRP2 = V DD - VGS6 , VGS6 = |V T6| +
CL2= 10pF
I7 =40µA
I5=20µA
∆t = ∆t1 + ∆t2
M6 I6
-5V
2I7 KP'( W6 /L6)
2.40 = 2.58 V ‘ V TRP2 = 5 - 2.58 = 2.42 V 8.4 0.3pF ∴ ∆t1 = (5 - 2.42)20 µA = 38.7ns CL2 CL2 ∆t2 = v O (t 0 )-0 I -I = 5 I -I 6 7 6 7 KP6' W6 I6 = 2 L V D D -V D O (min) (min)- VT6 2 6 [VDO(min) is an optimistic assumption based on v DS2 ≈ 0] VGS6 = 1 +
i D = 2 ( v G S -V T ) 2 or v D S (sat)= Also, gm = where
KW
β= L
2 β ID
2iD(sat)
β
β ⇒ iD(sat) = 2 [vDS(sat)]2
Allen and Holberg - CMOS Analog Circuit Design
Page VI.3-10
COMPARATOR DESIGN PROCEDURE
1. Set the output current to meet the slew rate requirements. dV i = C dt 2. Determine the minimum sizes for M6 and M7 for the proper ouput voltage swing. vDS(sat) =
2ID
β
3. Knowing the second stage current and minimum device size for M6, calculate the second stage gain. A2 = g
-g m6 ds 6 +g d s 7
4. Calculate the required first stage gain from A 2 and gain specifications. 5. Determine the current in the first stage based upon proper mirroring and minimum values for M6 and M7. Verify that P diss is met. 6. Calculate the device size of M1 from A 1 and I DS1. -gm1 2K'W/L A1 = g +g and gm1 = IDS1 ds 1 ds3 7. Design minimum device size for M5 based on negative CMR requirement using the following (I DS1 = 0.5I DS5 ): vG1 (min) = VSS + V DS5 + where VDS5 =
IDS5
β1 + VT1(max)
2IDS5
β5 = VDS5(sat)
8. Increase either M5 or M7 for proper mirroring. 9. Design M4 for proper positive CMR using: vG1(max) = VDD -
IDS5
β3 - VTO3 (max) + VT1
10. Increase M3 or M6 for proper mirroring. 11. Simulate circuit.
Allen and Holberg - CMOS Analog Circuit Design
Page VI.3-11
DESIGN OF A TWO-STAGE COMPARATOR
Specifications: Lambda = 0.05V -1 (L = 5 µm)
Avo > 66 dB Pdiss < 10 mW
VDD = 10 V
C L = 2 pF
VSS = 0 V
K'W Recall that β = L
tprop < 1 µs
CMR = 4-6 V Output swing is V DD - 2V and V SS + 2V 1). For t prop << 1 µs choose slew rate at 100 V/ µs dvOUT ∴ I7 = CL dt = ( 2.10-12) ( 100.10-6) = 200 µA 2). Size M6 and M7 to get proper output swing, M7: 2V > vDS7(sat) =
2I7
β7
W7 2(200µA) → L7 >5.88 17.0µA/V2( W7 /L7)
=
M6: 2V > vDS6(sat) =
2( IOUT+I7)
β6
=
-gm6 -1 3). A 2 = g +g = λ + λ ds 6 d s 7 N P
ω3 = r C out 3 Typical performanceW1 W2 W11 W13 ID1 = ID2 = 50µA and I D3= I D4 = 100µA, L = L = L = L 1 2 11 13 =1, assume C 3 ≈ 0.5pF, and using the values of Table 3.1-2 gives: gm1 = g m2 = g m11 =41.2 µS gds5 = g ds11 = 0.5µS
gm13 = 28.3µS
gds4 = g ds13 = 0.25µS
Therefore, rout = 121MΩ, ω3 = 16.553krps, and A VD0 = 4,978 resulting in a gain-bandwidth of 13.11MHz. C3∆V 0.5pFx10V Delay = ∆T = I = 100 µA = 50nS max
Allen and Holberg - CMOS Analog Circuit Design
Page VII.4-3
OPEN LOOP COMPARATOR - MC 14575
BIAS
M1
M6 M8
-
M2
vO
+
M3
M10
M9
M11
M7 M4
M5
Performance (ISET = 50 µA) Risetime Falltime = 100 ns into 50 pF Propagation delay = 1 µs Slew rate = 2.7 Volts/ µs Loop Gain = 32,000 Comments The inverter pair of M8-M9 and M10-M11 are for the purpose of providing an output drive capability and minimizing the propagation delay.
Allen and Holberg - CMOS Analog Circuit Design
Page VII.4-4
CLAMPED CMOS VOLTAGE COMPARATOR
VDD
VDD
M6
M8
BIAS
VPB
M1
-
+ M3
M2 M9
vO
M4
VNB
M5
M7
VSS
Drain of M2 and M3 clamped to the gate voltages of M4 and M5. M6 and M7 provide a current, push-pull output drive capability similiar to the current , push-pull CMOS OP amp. Comparator is really a voltage comparator with a current output.
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-1
VII.5 - COMPARATORS WITH HYSTERESIS HYSTERESIS
Why Hysteresis? Eliminates "chattering" when the input is noisy. Comparator with no Hysteresis vin
Comparator threshold
Time
Comparator output
Comparator with Hysteresis vin
vout
VTRP+ VTRPvin VTRP-
VTRP+ comparator output
Time
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-2
VOLTAGE COMPARATORS USING EXTERNAL FEEDBACK
Inverting vOUT
+
vB vA R1
VOH vOUT
VREFR2 R1 +R2 VOHR1 R1 +R2
R2 + V - REF
VOL
vB
VOLR1 R1+R2
Noninverting vOUT R2 vIN
R1
vA + vB + - VREF
VOH VREF R1 +R2 R2
vOUT
vIN R1 V R2 OL
VOL R1 V R2 OH
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-3
COMPARATORS WITH INTERNAL FEEDBACK
Cross-Coupled Bistable VDD M3
M10 M11
M4
M8
M6 M1
M2 vO
BIAS
M5
M9
M7 VSS
(1). Positive feedback gives hysteresis. (2). Also speeds up the propagation delay time.
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-4 m 0 0 6
m 0 0 4
S I S E R E T S Y H H T I W R O T A R A P M O C 1 4 . 7 E L P M A X E
m 0 0 2
m 0
m 0 0 2 -
m 0 0 4 -
V 0 . 6
V 0 . 5
V 0 . 4
V 0 . 3
V 0 . 2
m 0 0 V 6 0 . 1
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-5
AUTO ZEROING OF VOLTAGE COMPARATORS
Model of the Comparator Including Offset
-
+ IDEAL -
+ VOS
Auto Zero Scheme-First Half of Cycle
-
+
+ IDEAL -
CAZ
VOS
Auto Zero Scheme-Second Half of Cycle
VIN VOS
+
+ VOS
+ IDEAL -
+ 0V -
+ V - OS
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-6
GENERALIZED AUTO ZERO CONFIGURATION
φ1 φ2 vIN+ vIN-
+
φ1
φ2
VOS
+ CAZ
+
-
IDEAL
-
VOS
φ1
Good for inverting or noninverting when the other terminal is not on ground.
vOUT
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-7
Noninverting Auto-Zeroed Comparator
φ1 φ2 vOUT
φ1
vIN
+ CAZ
φ2
φ1
Inverting Auto-Zeroed Comparator
φ1 φ2 CAZ
vIN
vOUT
φ1
Use nonoverlapping, two-phase clock.
+
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-1
VII.6 - HIGH SPEED COMPARATORS Concept
Question: For a given input change, what combination of first-order openloop comparators and a latch gives minimum propagation delay?
+ vIN -
C1
C2
C3
Cn
Latch
Q Q
n first-order, open-loop comparators with identical gains, A Concept: voltage High Output Level
∆ = input voltage change
Latch vout = e t/ τ ∆
n tn-1 )e-t/ τ ] v out = A [1 - (1 + (n-1)! ∆
A5∆ A4∆ A3 ∆ A2∆ A∆
5 4 3 v out = A2[1 - (1 + t)e -t/ τ )] ∆ 2 -t/ τ out v = A(1-e )∆ n=1 t3
tL
Time
Propagation delay time = t 3 + t L for n=3 Answer: tp(min) occurs when n=6 and A=2.72=e Implementation: n=3 and A ≈6 gave nearly the same result with less area. [Ref: Doernberg et al., “A 10-bit 5 MSPS CMOS Two-Step FLASH ADC”JSSC April 1989 pp 241249]
Allen and Holberg - CMOS Analog Circuit Design
Page VII.6-2
HIGH SPEED COMPARATORS-CONT'D
Conceptual Implementation-
+ vIN -
+ -
+ -
+ -
- +
- +
- +
Latch
Q Q
VDD
Q FB
Reset Q FB
VB1
Offset and level shifting-
vIN
vIN-VOS + -
VOS
_ + -
+
LATCH VB2 VSS
Allen and Holberg - CMOS Analog Circuit Design
Page VII.7-1
VII.7 - COMPARATOR SUMMARY • Key Key perf perfor orma manc ncee para parame mete ters rs:: Propagation time delay Resolving capability Input common mode swing Input offset voltage • Ty Type pess of comp compar arat ator ors: s: Open loop Regenerative Open loop and regenerative Charge balancing • Open loop loop compa comparat rator or needs needs differ different ential ial inpu inputt and seco second nd stage stage • Systemat Systemative ive offset offset error error is offset offset (usin (usingg perfect perfectly ly matched matched transist transistors) ors) that is due to current mirror errors. • For fast fast compar comparato ators, rs, keep keep all all node node swing swingss at a minim minimum um excep exceptt for the the output (current comparators?). • Key Key de design sign equ equati ations: ons: KW iD = 2L (vGS -V T) 2,
vDS (sat) =
2iD K(W/L) , and gm =
2KWID L
• Positiv Positivee feedb feedback ack is used for regenera regenerative tive comparat comparators. ors. • Use autoze autozeroi roing ng to remove remove offse offsett voltage voltagess (charge (charge injec injectio tionn is limit). limit). • Fastest Fastest compa comparato rators rs using using low-ga low-gain, in, fast fast open open loop ampli amplifier fierss cascade cascadedd with a latch.
Allen and Holberg - CMOS Analog Circuit Design
Page VII.0-1
VIII. SIMPLE CMOS OPERATIONAL AMPLIFIERS (OP AMPS) AND OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTA'S) Contents
VI II .1 VI II .2 VI II .3
Design Principles OTA Compensation Two-Stage CMOS OTA Design
Organization
SYSTEMS
Chapter 10 D/A and A/D Converters
Chapter 7 CMOS Comparators
Chapter 11 Analog Systems
Chapter 8 Simple CMOS Op Amps
Chapter 9 High Performance OTA's
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
DEVICES
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
Allen and Holberg - CMOS Analog Circuit Design
Op Amp Characteristics Non-ideal model for an op amp V 1
R
I b2
icm CMRR
2
e V
n
R
2
2
V os
R
I n
C id
V
Ideal
id +
1
R icm
I b1
Boundary Conditions Process Specification Supply Voltage Supply Current Temperature Range Typical Specifications Gain Gainbandwidth Settling Time Slew Rate Input CMR CMRR PSRR Output Swing Output Resistance Offset Noise Layout Area
Requirement See Ta Tables 3.1 3.1-1 and 3.1-2 +5 V ±10% 100 µ A 0 to 70 °C
≥ 80 dB ≥ 10 MHz sec ≤ 0.1 µ sec µsec sec ≥ 2 V/ µ ≥ ±2 V ≥ 60 dB ≥ 60 dB ≥ 2 VP-P
Capacitive load only ≤ ± 5 mV 50nV// Hz at 1KHz ≤ 50nV ≤ 10,000 square µ m
out
Allen and Holberg - CMOS Analog Circuit Design Frequency Response
A v (s )
Av0
= s
s s (p − 1 ) (p − 1 ) (p − 1) . . . 1
2
3
-6dB/oct
Gain, dB
GB
ω2 ω3
0 dB
ω1
Frequency
180
Phase (degrees) 90
Phase margin 0 Frequency
-90
Allen and Holberg - CMOS Analog Circuit Design Power supply rejection ratio (PSRR):
vout ( vps = 0 ) Avd(s) vin (v ∆VDD PSRR = ∆v · A (s) = A (s) = v ps out OUT vd ( vin = 0 ) vps (v Common-mode input range (ICMR).
Maximum common mode signal range over which the differential voltage gain of the op amp remains constant. Maximum and minimum output voltage swing.
Allen and Holberg - CMOS Analog Circuit Design Settling Time 1.4 1.2
Upper tolerance
1
Vout(t)
Lower tolerance
0.8 0.6
Settling time
0.4 0.2 0
0
2
4
6
Time (sec)
8
10
12
14
Allen and Holberg - CMOS Analog Circuit Design Design Approach
Design
Specifications
Iterate
Analysis Simulation
Modify
Specifications:
• • • • • •
Gain Output voltage swing Settling time Power dissipation Supply voltage Silicon area
• • • • •
Bandwidth PSRR CMRR Noise Common-mode input range
Allen and Holberg - CMOS Analog Circuit Design Design Strategy
The design process involves two distinct activities: Architecture Design
• Find an architecture already available and adapt it to present requirements
• Create a new architecture that can meet requirements Component Design
• Design transistor sizes • Design compensation network If available architectures do not meet requirements, then an existing architecture must be modified, or a new one designed. Once a satisfactory architecture has been obtained, then devices and the compensation network must be designed.
Allen and Holberg - CMOS Analog Circuit Design Op Amp Architecture
VDD
M3
M4 M6
M1
M2
-
+
Compensation
IBias M5
M7
vOUT
Allen and Holberg - CMOS Analog Circuit Design
Compensation In virtually all op amp applications, feedback will be applied around the amplifier. Therefore, stable stable performance performance requires that that the amplifier amplifier be compensated. Essentially we desire that the loop gain be less than unity unity when the phase shift around the loop is greater than 135˚
β
IN
+
-
Σ
A
OUT
OUT
A =
IN
1 + Aβ
Goal: 1 + A β > 0 Rule of thumb: arg[A β] < 135˚ at mag[A β] = 1
Allen and Holberg - CMOS Analog Circuit Design
Graphical Illustration of Stability Requirements
β=1
|Aβ| (dB)
-6dB/oct
GB 0 dB
ω1
Frequency
180o Arg[Aβ] 90o
0o Frequency
ω2
-12dB/oct
Allen and Holberg - CMOS Analog Circuit Design
Step Response of Two-Pole System
Impact of placing ω2 at different locations:
stability Date/Time run: 04/08/97 19:45:36
Temperature: 27.0
1.5V
3 2 1 1.0V
ω1 = 1000 rps Case 1: ω2 = 1 x 106 rps
0.5V
Case 2: ω2 = 0.5 x 106 rps Case 3: ω2 = 0.25 x 106 rps 0V 0s
5us
10us
v(5) Time
15us
20us
Allen and Holberg - CMOS Analog Circuit Design
Types of Compensation 1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage. • Miller capacitor only • Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. • Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. 2. Self compensating - Load capacitor compensates the op amp (later). 3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.
Allen and Holberg - CMOS Analog Circuit Design
Miller Compensation VDD
M3
M4
CM
M1
M2
-
M6
Cc
+
v OUT
IBias
C1 CL
M7
M5
Small-signal model 1 gds2+g ds4
gm1
CM
-vin 2
r
ds1
+
gm4v 1
v1
1
-
gm3
1 gds6 +gds7
C c
+ v g m2 in 2
+
v2
C1
-
CL
gm6 v2
vout
-
Simplified small-signal model 1 gds2+gds4
+ vin
-
Cc
+ gm1vin
v2
-
1 gds6+gds7
+ C1 gm6v2
CL vout
-
Allen and Holberg - CMOS Analog Circuit Design
Analysis (gm I )(gmII )( R R I )( R R II )(1-sC c / gmII ) V o(s) = V in(s) 1+s[ R R I (C 1+C c)+ R R II (C R I R II C c]+s2 R I R II [C 1C L+C c)+gmII L+C c(C 1+C L)] p1 ≅
-1 gm II R I R II C c
-gm II C c p2 ≅ C 1C L+C LC c+C 1C c p2 ≅
z1 =
-gm II C L gm II C c
where gmI = gm1 = gm2
1
R I = gds2+gds4
gmII = gm6
1
R II = gds6+gds7
Allen and Holberg - CMOS Analog Circuit Design
Miller Compensation
β=1 |Aβ| (dB)
-6dB/oct Before compensation
GB
After compensation
ω1
Frequency
ω2
-12dB/oct
180o Before compensation Arg[Aβ] 90o
0o
After compensation Phase margin Frequency
Allen and Holberg - CMOS Analog Circuit Design
Conditions for Stability • Unity-gainbandwith is given as:
gmI 1 GB = Av(0)·|p 1| = ( gmIgmIIRIRII) · g R R C = C c mII I II c
• The requirement for 45 ° phase margin is:
ω ω ω Arg[Aß] = ±180° - tan-1 |p | - tan-1 |p | - tan-1 z = 45° 1 2 Let ω = GB and assume that z ≥ 10GB, therefore we get, GB GB GB ±180° - tan-1 |p | - tan-1 |p | - tan-1 z = 45° or
Parasitic pole, ω2, held constant while dominant pole, ω1, is moved.
Allen and Holberg - CMOS Analog Circuit Design
Eliminating RHP Zero M3
M4
M1
M6
Cc
M2 RZ
V OUT
CII
Vbias
M7 M5
RZ + vin
Cc
+ gmI vin
-
v2
+ RI
CI
-
gmI V in +
gmII v2
V I sC c sC I V I + + R I 1 + sC R c
(V − V ) = 0 I o z
V o sC c gmII V sC V + + + I R II o II 1+ sC R c
(V − V ) = 0 o I z
These equations can be solved to give V o(s) a{1− s[(C c / gmII )− R zC c]} = V in(s) 1+ bs + cs2 + ds3
where a = gmI gmII R I R II b = (C II + C c) R R II + (C I + C c) R R I + gmII R I R II C c + R zC c
RII
CII vout
-
Allen and Holberg - CMOS Analog Circuit Design c = [ R R I R II (C R I C I C II + C cC I + C cC II ) + R zC c( R I + R II C II )] d = R I R II R zC I C II C c R z is assumed to be less than R I or R II and the poles widely spaced, then the roots are If R p1 ≅
p2 ≅
p3 =
−1 (1+ gmII R II ) R R I C c
≅g
=
R II R I C c mII
−gmII C c −g ≅ C mII II C I C II + C cC I + C cC II −1 R zC I
and z1
−1
1 C c(1/ gmII − R z)
By setting R z = 1/ gmII
The RHP zero moves to infinity
Allen and Holberg - CMOS Analog Circuit Design
Implementing Compensation Resistor M3
M4
M1
M2
M6
MZ
Cc V OUT
CII
Vbias
M7 M5
Allen and Holberg - CMOS Analog Circuit Design Two-Stage Operational Amplifier Design
V DD
M6 M3
M4
C c vout
-
M1
M2
C L
vin + +
M7
M5
VBias -
V SS
Important relationships: gm1 = gm2 = gmI , gm6 = gmII , gds2 + gds4 = G I , and gds6 + gds7 = G II . I 5
Slew rate SR = C
(1)
c
First-stage gain Av1 =
gm1
2gm1
=
gds2 + gds4 I 5(λ 2
Second-stage gain Av2 =
gm6
=
+ λ 4) gm6
gds6 + gds7 I 6(λ 6 + λ 7)
gm1 Gain-bandwidth GB = C c
Output pole p2 = RHP zero z1 =
(3) (4)
−gm6
(5)
C L
gm6 C c
Positive CMR V in(max) = V DD −
(2)
(6) I 5
β 3
− |V T 03 03|(max) + V T 1(min) 1(min))
(7)
Allen and Holberg - CMOS Analog Circuit Design I 5
Negative CMR V in(min) = V SS + Saturation voltageV DS(sat) =
β 1
+ V T 1(max) 1(max) + V DS5(sat)
2 I DS
(8)
(9)
β
All transistors are in saturation for the above relationships. The following design procedure assumes that specifications for the following parameters are given. 1. Gain at dc, Av(0) 2. Gain-bandwidth, GB 3. Input common-mode range, ICMR 4. Load Capacitance, C L 5. Slew-rate, SR 6. Output voltage swing 7. Power dissipation, Pdiss Choose a device length to establish of the channel-length modulation parameter λ. Design the compensation capacitor C c. It was shown that placing the loading pole p2 2.2 times higher than the GB permitted a 60° phase margin (assuming that the RHP zero z1 is placed at or beyond ten times GB ). This results in the following requirement for the minimum value for C c. C c > (2.2/10) C L
Next, determine the minimum value for the tail current I 5, based upon slew-rate requirements. Using Eq. (1), the value for I 5 is determined to be I 5
= SR (C c)
If the slew-rate specification is not given, then one can choose a value based upon settlingtime requirements. Determine a value that is roughly ten times faster than the settling-time specification, assuming that the output slews approximately one-half of the supply rail. The value of I I 5 resulting from this calculation can be changed later if need be. The aspect ratio of M3 can now be determined by using the requirement for positive input common-mode range. The following design equation for (W / L)3 was derived from Eq.(7). S3 = (W / L)3 =
I 5
(K '3)[V DD − V in(max)− |V T 03 03|(max)+ V T 1(min)]2
If the value determined for (W / L)3 is less than one, then it should be increased to a value that minimizes the product of W and L. This minimizes the area of the gate region, which
Allen and Holberg - CMOS Analog Circuit Design in turn reduces the gate capacitance. This gate capacitance will affect a pole-zero pair which causes a small degradation in phase margin. Requirements for the transconductance of the input transistors can be determined from knowledge of C c and GB. The transconductance gm2 can be calculated using the following equation gm 1
= GB(C c)
The aspect ratio ( W / L)1 is directly obtainable from gm1 as shown below 2
gm1
S1 = (W / L)1 = (K ' )( I I ) 2
5
Enough information is now available to calculate the saturation voltage of transistor M5. Using the negative ICMR equation, calculate V DS5 using the following relationship derived from Eq. (8). I 5 1/2 V DS5 = V in(min) − V SS − − V T 1(max) β 1
If the value for V DS5 is less than about 100 mV then the possibility of a rather large ( W / L)5 may result. This may not be acceptable. If the value for V DS5 is less than zero, then the ICMR specification may be too stringent. To solve this problem, I 5 can be reduced or (W / L)1 increased. The effects of these changes must be accounted for in previous design steps. One must iterate until the desired result is achieved. With V DS5 determined, (W / L)5 can be extracted using Eq. (9) in the following way S5 = (W / L)5 =
I 5) 2( I 2 K '5(V DS5)
For a phase margin of 60°, the location of the loading pole was assumed to be | p2| in Eq. (5), placed at 2.2 times GB. Based upon this assumption and the relationship for p the transconductance gm6 can be determined using the following relationship gm6 = 2.2(gm2)(C Cc ) L / C
Since S3 is known as well as gm6 and gm3, assuming balanced conditions,
gm6 gm3
S6 = S3
can be calculated from the consideration of the “proper mirroring” of first-stage the current mirror load of Fig. 6.3-1. For accurate current mirroring, we want V SD3 to be equal to V SD4. This will occur if V SG4 is equal to V SG6. V SG4 will be equal to V SG6 if
I 6
Allen and Holberg - CMOS Analog Circuit Design I 6 =
(W / L)6 S6 I 1 = I1 (W / L)4 S4
Choose the larger of these two values for I 6 (Eq. 19 or Eq. 20). If the larger value is found in Eq (19), then (W / L)6 must be increased to satisfy Eq. (20). If the larger value is found in Eq. (20), then no other other adjustments must be made. One also should check the power dissipation requirements since I 6 will most likely determine the majority of the power dissipation. The device size of M7 can be determined from the balance equation given below
I 6 I6 S7 = (W / L)7 = (W / L)5 I = S5 I 5 5 The first-cut design of all W/L ratios are now complete. Fig. 6.3-2 illustrates the the above design procedure showing the various design relationships and where they apply in the two-stage CMOS op amp. Max. ICMR and/or p3 V SG SG4
V DD
+
+
V SG SG6
-
M3 GB =
vin +
Min. ICMR +
VBias -
-
M4
M6
C c
I 6
gm1 C c
I 5
gm6 or
Proper Mirroring V SG SG4=V SG SG6 vout
C c ≈ 0.2C L
M2
M1
V out out (max)
C L
(PM = 60°)
I 5 = SR·C c
M5
V out out (min)
M7 V SS
Figure 6.3-2 Illustration of the design relationships and the circuit for a two-stage CMOS op amp. At this point in the design procedure, the total amplifier gain must be checked against the specifications. (2)(gm2)(gm6) Av = I 5(λ 2 + λ 3) I I 6(λ 6 + λ 7) If the gain is too low, a number of things can be adjusted. The best way to do this is to use the table below, which shows the effects of various device sizes and currents on the
Allen and Holberg - CMOS Analog Circuit Design different parameters generally specified. Each adjustment may require another pass through this design procedure in order to insure that all specifications have been met. Table 6.3-2 summarizes the above design procedure. Dependencies of device performance on various parameters Drain Current I5 I7 DC (↓) 1/2 (↓) 1/2
Increase Gain Increase GB (↑) 1/2 Increase RHP Zero Increase Slew ↑ Rate Increase CL
(↑) 1/2
M1 and M2 W/L L (↑) 1/2 ↑
(↑) 1/2
M3 and M4 W L
↑
Inverter Inverter Comp. Load Cap.. W6 /L6 W 7 L7 C c ↑ (↑) 1/2
(↑) 1/2
↓ ↓ ↓ ↓
Allen and Holberg - CMOS Analog Circuit Design Design Procedure:
This design procedure assumes that the gain at dc ( Av), unity gain bandwidth (GB ), input common mode range (V in(min) and V in(max)), load capacitance ( C L), slew rate ( SR), settling time (T s), output voltage swing (V out (max) and V out (min)), and power dissipation (Pdiss) are given. 1.
Choose the smallest smallest device length length which will will keep keep the the channe channell modulation modulation paramete parameterr constant and give good matching for current mirrors. 2. From the the desire desiredd phase phase margin, margin, choose choose the the minimum value value for C c, i.e. for a 60 ° phase margin we use the following following relationship. relationship. This assumes that that z ≥ 10GB. C c
3.
> 0.22 C L
I 5) from the largest of the two Determ Determine ine the minimum valu valuee for for the the “tail “tail current” current” ( I values. I 5
= SR .C c V DD + |V SS| . 2 T s
I 5 ≅ 10
4.
Design for S3 from the maximum input voltage specification. S3 =
I 5 K '3[V DD − V in(max)− |V T 03 03|(max)+ V T 1(min)]2
≥1
5. Veri Verify fy tha that the the pole pole of M3 M3 due to C gs3 and C gs4 (=0.67W3L3C ox) will not be dominant by assuming it to be greater than 10 GB gm3 2C gs3
6.
> 10GB.
Design for S1 (S2) to achieve the desired GB. 2
gm2 gm1 = GB . C c ⇒ S2 = K '2 I 5 7.
Design for S5 from the minimum input voltage. First calculate V DS5(sat) then find S5. V DS5(sat) = V in(min) − V SS −
S5 =
2 I 5 2 K '5[V DS5(sat)]
I 5
β 1
− V T 1(max) ≥ 100 mV
Allen and Holberg - CMOS Analog Circuit Design 8.
Find gm6 and S6 by the relationship relating to phase margin, load, and compensation capacitors, and the balance condition. gm6 = 2.2gm2(C L / C Cc )
gm6 gm3
S6 = S3
9.
Calculate I 6 : I 6 = (S6 / S4) I I 4 = (S6 / S4)( I I 5 /2)
10. Design S7 to achieve the desired current ratios between I 5 and I 6. S7 = ( I I 6 / I 5)S5
11. Check gain and power power dissipation dissipation specificat specifications. ions. 2gm2gm6 Av = I 5(λ 2 + λ 3) I I 6(λ 6 + λ 7) Pdiss = ( I I 5 + I 6)(V DD + |V SS|)
12. If the gain specific specification ation is not met, met, then then the currents, currents, I 5 and I 6, can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they have been satisfied. If the power dissipation is too high, then one can only reduce the currents I 5 and I 6. Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings. 13. Simulate the circuit circuit to check to see that all all specifications specifications are met.
Allen and Holberg - CMOS Analog Circuit Design Example: Design of a Two-Stage Op Amp
Using the material and device parameters given in Tables 3.1-1 and 3.1-2, design an amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications. Assume the channel length is to be 1µm. Av > 3000V/V V V SS = -2.5V DD = 2.5V GB
= 5MHz
C L
V out range = ±2V
= 10pF
ICMR
= -1 to 2V
SR
> 10V/ µs
P diss
≤ 2mW
Solution
Calculate the minimum value of the compensation capacitor C c , C c > (2.2/10)(10 pF)
= 2.2 pF
Choose C c as 3pF. Using the slew-rate slew-rate specification and C c calculate I 5. I 5 = (3 × 10-12)(10 × 106) = 30
µA
Next calculate (W / L)3 using ICMR requirements. 30×10-6 (W / L)3 = = 15 (50×10-6)[2.5−2−.85+0.55]2 gm3 =
2×50x10-6x15x10-6 ×15 = 150µS
Therefore (W / L)3 = (W/ L) L)4 = 15 Check the value of the mirror pole, p3, to make sure that it is in fact greater than 10GB. Assume the C ox = 0.4fF/ µm2. The mirror mirror pole can be found found as -gm3 - 2K ’ pS3 I 3 9(rads/sec) p3 ≈ = = 15.75x10 2C gs3 2(0.667)W 3 L3C ox or 2.98 GHz. Thus, p3, is not of concern in this design because p3 >> 10GB. The next step in the design is to calculate gm1 gm1 = (5 × 106)(2π)(3 × 10-12) = 94.25µS
Therefore, (W / L)1 is gm12
(94.25)2 (W/L)1 = (W / L)2 = 2K’ I = 2·110·15 = 2.79 ≈ 3.0 N 1 Next calculate V DS5
Allen and Holberg - CMOS Analog Circuit Design 30×10-6 V DS5 = (−1) − (−2.5) − - .85 = 0.35V 110 × 10-6·3 Using V DS5 calculate (W / L)5 from Eq. (16) 2(30×10-6) = 4.49 ≈ 4.5 (50×10-6)(0.35)2 From Eq. (20) of Sec. 6.2, we know that gm6 ≥ 10gm1 ≥ 942.5µS (W / L)5 =
Assuming that gm6 = 942.5µS 942.5×10-6 = 94.25 150×10-6 Using the equations for proper mirroring, I 6 is determined to be (W / L)6 = 15
I 6 = (15 × 10-6)(94.25/15) = 94.25 µA
Finally, calculate ( W / L)7
94.25×10-6 ≈ 14.14 30×10-6
(W / L)7 = 4.5
Check the V out (min) specification although the W/L of M7 is so large that this is probably not necessary. The value of V out (min) is 2×94.25 = 0.348V 110×14.14 which is much less than required. At this point, the first-cut first-cut design desi gn is complete. Examining the results shows that the large value of M7 is due to the large value of M5 which in turn is due to a tight specification on the negative input common mode range. To reduce reduce these values the the specification specification should be loosened or a different architecture (i.e. p-channel input pair) examined. Now check to see that the gain specification has been met V min(out) = V DS7(sat) =
(2)(94.25×10-6)(942.5×10-6) = 19,240 30×10-6(.04+.05)38×10-6(.04+.05) which meets specifications.
Av
=
Allen and Holberg - CMOS Analog Circuit Design
IX. HIGH PERFORMANCE CMOS AMPLIFIERS Contents
IX.1 IX.2 IX.3 IX.4 IX.5 IX.5 IX.6 IX.7
Improv Improving ing The The Two-St Two-Stage age Arch Archite itectu cture re Two-st Two-stag agee Casco Cascode de Archi Archite tect ctur uree Folde Foldedd Casco Cascode de Arch Archit itec ectu ture re Differential Output Architecture (Class AB) Low Lo w powe powerr ampl amplif ifie iers rs Dyna Dynamic mical ally ly bias biased ed ampl amplif ifie iers rs
Organization
SYSTEMS
Chapter 10 D/A and A/D Converters
Chapter 7 CMOS Comparators
Chapter 11 Analog Systems
Chapter 8 Simple CMOS Op Amps
Chapter 9 High Performance OTA's
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
DEVICES
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
Allen and Holberg - CMOS Analog Circuit Design IX.1 IMPROVING THE TWO-STAGE ARCHITECTURE
Amplifiers Using an MOS Output Stage PUSH-PULL CMOS OTA This amplifier is a simple extension of the seven-transistor OTA studied in Section 8.
VDD
M9
VDD
M7
VDD vOUT
M1
-
VDD
M2
+
Cc CL
M8 M6 M4
M3
small-signal equivalent circuit: Cc
vout
+ gm1vi
C1
r1
where gm1 = g m2, r1 = g
v1 -
gm6 v1
CL
r2
1 1 , r = 2 g +g ds2 ds 2 +g d s 4 ds 6 ds7
gm1Ai v 2 i
Allen and Holberg - CMOS Analog Circuit Design
Amplifiers Using an MOS Output Stage - Continued Network equations: [g1 + s(C1 + CL)]v1 - sCcv2 = gm1vi
gm1AIvi [g5 + sCc]v1 + [g2 + s(Cc + CL)]v2 = 2 i7 AI is the current gain from M1 to M7: A I = i 1 -gm6 z= AI - 1 C 2 c -g1g2 p1 ≈ g C m6 c -gm6 p2 ≈ C L gm1gm6 AV ≈ g g 1 2 To guarantee that the zero stays in the left-half plane, A I > 2
Allen and Holberg - CMOS Analog Circuit Design
Amplifiers Using an MOS Output Stage - Continued Example: VDD
VDD
VDD
M9
-
M7
M1
VDD
M2
+
VDD
M9
VDD
M7
M1
-
Cc
+
M2
Cc CL
CL
M8 M6
M6
M3 M4
M3 M4
Push-Pull (AI ≈ 3)
Standard (AI = 0)
140 120 100 Gain(db)
80 Push-Pull phase
60
Standard gain 40 Push-Pull gain
20 Standard phase
0 -20 1
10
2
10
3
10
VDD
4
10
5
10
6
10
Frequency
7
10
8
10
9
10
Allen and Holberg - CMOS Analog Circuit Design IX.2 Two-Stage Cascode Architecture
Why Cascode Op Amps? • Control the frequency behavior • Increase PSRR • Simplifies design Where is the Cascode Technique Applied? • First stage Good noise performance Requires level translation to second stage Requires Miller compensation • Second stage Self compensating compensating Reduces the efficiency of the Miller compensation Increases PSRR
Allen and Holberg - CMOS Analog Circuit Design
Power Supply Rejection Ratio (PSRR) Definition: vdd + vin
+
+
-
-
+
-
vss
-
VDD vout
+
VSS
-
vout Av(vdd=0) vin (vdd=0) PSRR+ = A (v =0) = v dd in out vdd (vin=0) Calculation of PSRR: vdd
+
+
-
+ -
VDD
v1 vout
VSS
Addvdd
=>
v2
vout
Av(v1 -v2 )
K
vout = Addvdd + A v(v1-v2) = A ddvdd - A vvout vout(1 + Av) = A ddvdd vout Add Add 1 = = ≈ vdd 1+A v Av PSRR+
Extends bandwidth beyond GB
↓ vout KAdd Add vdd = 1+KAv ≈ Av
Allen and Holberg - CMOS Analog Circuit Design
Intuitive Interpretation of Positive PSRR for the Two-Stage OTA
vdd
+
VDD
-
-
M3
+
1.) The M7 current sink causes VGS6 to act like a battery. 2.) Therefore, vdd
M4
couples from the source
M6 M1
-
to gate of M6.
Cc
M2
vout
+
3.) The path to the output is through any capacitance
M7
M5
from gate to drain of M6.
+
VBias
VSS
+ -
4.) Resultant circuit
modelvdd
MustreduceC c!
+
vout Cc
Rout
-
Vout Vdd 1
0dB
-60 to -80dB
Rout Cc
ω
Other sources of PSRR beside C c
Allen and Holberg - CMOS Analog Circuit Design
Intuitive Interpretation of the Negative PSRR for the Two-Stage OTA +
Problems with the two-stage OTA: • Insu Insuff ffic icie ient nt gain gain • Poor stabili stability ty for for large large load load capacit capacitance ance • Poor PSRR These problems can be addressed using various cascode structures.
We will consider several approaches: • Casc Cascod odin ingg the the fir first st sta stage ge • Casco Cascodin dingg the the second second stage stage • Fol Folded ded cas casco codde
• Requires voltage translation to drive next stage • Requires additional biasing for cascode devices • Common-mode problem at drains of M1 and M2
Allen and Holberg - CMOS Analog Circuit Design
First Stage Cascode - Continued
Common-mode improvement: VDD
VDD
M3
M4 ICM MC2
VBP
MC3
VDD
VDD
MC1
M9
+
VO1
-
M1
M2
VBIAS VSS
Common-mode circuitry (M9) maintains V ds of M1 and M2 AV = g m1 ro1 ro1 ≈ (gmc2 rdsc2)r ds4 || (g mc1 rdsc1)r ds2 ds 2 -1 p1 ≈ C r L o1 gm1 GB ≈ AV|p1| ≈ C L Output range of this amplifier is poor when used by itself. It needs an output stage to be practical.
Allen and Holberg - CMOS Analog Circuit Design First Stage Cascode - Continued
Implementation of I CM VDD M4
M3 ICM
ICM VBP
VDD MC2 VSS VSS
VSS MC1
MC3 vin 2
-vin vin 2 2 VSS
VSS
VSS M2
M1
I5 +ICM
VSS
-vin 2
Allen and Holberg - CMOS Analog Circuit Design
Level Translator for First Stage Cascode
VDD M4 MT2 M6
MC2 MT1 MC1
Vo VSS M2 VBIAS
M5 VSS
M7
Allen and Holberg - CMOS Analog Circuit Design
Improved PSRR For Two-Stage OTA
Use cascode to reject C c feedforward VDD
M3
M6
M8
VB1
-
M4 Cc
M9
+
M2
M1
vOUT
M5 VB2
M7 VSS
+PSRR is reduced by M9
Disadvantage Miller pole is larger because R 1 ≈ g
1 m9
positive input common mode range is restricted
Allen and Holberg - CMOS Analog Circuit Design
Complete Two Stage Cascode
VDD M3
M4 MT2
VBP
M6
MC2 MT1
ICM MC3
MC1
Vo VSS
M9 M1
M2 M7
VBIAS M5 VSS
Allen and Holberg - CMOS Analog Circuit Design
Second Stage Cascode
VDD M3
M4
M6
VBP Comp
M1
M2
VBN
MC6 Vo
MC5
M7
VBIAS M5 VSS
Allen and Holberg - CMOS Analog Circuit Design
LOAD COMPENSATED CASCODE AMPLIFIER
VDD VDD
M9
M3
M4
VDD M6
VDD
MC2
MC3 VBP
VDD
VBP VDD
-
+ M2
M1 M5
I5
MC1 VBN
VSS
VBIAS M8
VDD
M7
VSS
gm 2 A V 1 = g gm2 m4 AV = 2(g m4) (gm6 + gm9) R o 1 A V 2 = 2(g ( g m 6 +g m 9 ) R o where Ro ≈ (g mc2 rdsc2)rds6 || (g mc1 rdsc1)rds7 and M7 = M8 Or, gm1+gm2 KR o AV = 2 where W6 /L6 W9 /L 9 K = W /L = W /L 4 4 3 3
CL
Allen and Holberg - CMOS Analog Circuit Design
Design Example
Pertinent design equations: iOUT SR = C L gm2 AV = 2(g ) (gm6 + g m7 ) r o m4 GB =
g m2 (g m6 +g m7 ) 2(gm4)CL
Vin(max) = V DD -
I5 ß3 - |VT3|(max) + V T1(min)
Vin(min) = VSS + VDS5 + Specifications: VDD = -V SS = 5V SR = 5V/ µs into C L = 50pf GB = 5 MHz AV > 5000 CMR = ±3V Output swing = ±3V
I5 ß1 + VT1(max)
Allen and Holberg - CMOS Analog Circuit Design
Design Procedure
1.) Design Design for maximu maximum m source/si source/sink nk current current Isource/sink = C L(SR) = 50pf(5V/ µs) = 250 µA 2.) Note Note that that S6 Max. I OUT (source) = S I5 4 Max. I OUT (Sink) = Max. I OUT (source) if S3 = S 4, S9 = S6 and S7 = S 8 3.) Choose I 5 =100 µ A
∴ S 9 =S 6 =2.5S 4 =2.5S 3 4.) Desi Design gn for for ± 3V output capability a.) Nega Negati tive ve peak peak Let VDSC1(sat.) = V DS7(sat.) = 1V under negative peak conditions, I C1 = I 7 = 250 µA Divide 2V equally,
∴ 2V =
2I7 + KN'S7
=29.4 ∴ S 7 =S C 1 =29.4
2IC1 =2 KN'SC1
2I7 KN'S7 = 2
-> S 8 =S 7 =29.4
500 µ A 17 µ A/V A/ V 2S 7
Allen and Holberg - CMOS Analog Circuit Design
b.) Positive Positive peak, peak, divide voltage voltage equally, equally, VSD6 = VSDC2 = 1V , --> 2V =
2I6 + KP'S6
2IC2 =2 KP'SC2
2I6 KP'S6
∴ S 6 =S C 2 =62.5 --> S 3 =S 4 =25 5.) Desi Design gn of V BP and V BN a.) VBN (Assume max. I OUT (sink) conditions) MC1 VBN
IOUT(sink) = 250 µA -3 -5V
VDSC1 = VGSC1 - V TC1 (ignoring bulk effects)
-4
1 = V GSC1 -1 --> VGSC1 = 2V ∴ V B N =-2V
M7 -5
b.) VBP (Assume max. IOUT (source) conditions) +5V
+4 VBP
VDSC2 = VGSC2 - |V TC2| (ignoring bulk effects) VSGC2 = 2V ∴ V B P =+2V
MC2 IOUT(source)= 250 µA +3V
Allen and Holberg - CMOS Analog Circuit Design
6.) Chec Checkk max max.. Vin influence on S 3 (S4) Vin (max) = VDD +3 = +5 S3 =
100 µ A = 4.88 (Use S 3 = S4 = 25) µA 8 2 (1.6V) 2 V
With S 3 = 25, V in (max) = 3.89V which exceeds the specification. 7.) 7.) Find gm1 (gm2 ) a.) AV specification gm1 g m 6 +g m 7 RII AV = g 2 m4 gm4 = 2I4Kp'S4 = 141.1 µs gm6 = 2I6KP'S6 = 353.5 µs gm7 = 2I7KN'S7 = 353.5 µs gmc1 = gm7 gmc2 = gm6
1 rds6 = r dsc2 = I λ = 0.4 M Ω 6 P 1 rds7 = r dsc1 = I λ = 0.8 M Ω 7 Ν RII ≈ (gmc1 rdsc1rds7 ) || (g mc2 rdsc2rds6 ) = 45.25 M Ω g
11.) Check on power dissipation Pdiss = 10(I 8 + I 5 + I 7) = 10(125 µA + 100µA + 125µA) = 3.5mW 12.) Design W's for lateral diffusion and simulate
Allen and Holberg - CMOS Analog Circuit Design
X.3 FOLDED CASCODE ARCHITECTURE
Principle VDD
1.5 I
1.5 I
VBP + vIN
M1 M2
M3
M4
I
vIN
vout=gm1Rout vin I
M5
M6
M7
M8
I
VSS
Currents in upper current sinks must be greater than I to avoid zero current in the cascode mirror (M5-M8). Advantages Good input CMR. Good frequency response. Self compensating.
Allen and Holberg - CMOS Analog Circuit Design
Folded Cascode OP Amp VDD VB3 M4
M3
+
-
VB3
M14
M2
M1
VOUT M9
M8
Cc M16
VB1
M5
M15 VB2
M11
M10
M13
M12 VSS
High gain, High speed, cascode amp GB ≈ 10 MHz, A VDC ≈ 100 dB
Allen and Holberg - CMOS Analog Circuit Design
XI. 4 DIFFERENTIAL OUTPUT OTA'S Implementation Using Two Differential-In, Singled-Ended Op Amps
+ +
R
+
R -
+
Conceptual Implementation of Differential In-Out OP Amp
VDD
VDD
+
VDD
Vin -
-
Vout
+
CL
CL Common mode feedback
VSS
VBIAS
Allen and Holberg - CMOS Analog Circuit Design
Schematic of a Fully Differential In-Out, FoldedCascode Op Amp
VDD = +5V MP1A VBIAS1
MP1
MP2A VDD
VDD
VBIAS2
MP2 vOUT +
CL + vIN
CL VSS
-
MN2A
VSS
VBIAS3
MN2 MN1 VSS
VSS
MN1A VSS
VBIAS4
MN3 MN3A VSS = -5V
Allen and Holberg - CMOS Analog Circuit Design
Evolution of Class AB Amplifier VDD
VDD
VB2
+ vIN
vIN
vOUT
vOUT
+ vIN
vIN
VB1 VSS
M12
M11
VB2
+ vIN
M1
M2
vIN
+ vIN
M3
M4
vIN
VB1
M10
M9
M17
M18
VSS
combine
M14
M13
Problem: DC levels of input voltages incompatible
Allen and Holberg - CMOS Analog Circuit Design
M17
M12
M14
M11
M5 + vOUT
M6
+ vIN
M7
M1
M2
M3
M4
vIN
vOUT
M8
I
I M18
M10
M13
M9
DC problem solved, but amplifier has low gain and requires CM feedback
M17
M12
M14
M11 VB3
VB1 M5 + vOUT
M6
+ vIN
M1
VB2 M7
M3
M4
VB4
M8
vOUT
M15
I
I M18
vIN
M2
M16
M10
Gain improved using cascode
M9
M13
Allen and Holberg - CMOS Analog Circuit Design IX.5 LOW POWER AMPLIFIERS
General Objective is to minimize the dc power dissipation. Typical applications are: 1. Battery powered circuits. 2. Biomedical instrumentation. 3. Low power analog "VLSI." Weak Inversion or Subthreshold Operation Drain current qvGS W iD = L I D exp nkT ( 1+lv D S)
Small signal parameters qiD g m = nkT ,
rds ≈ (λ iD )-1
Device characteristics iD
iD 100nA
square law
100nA weak inversion
vGS < VT
1
2
vDS
exponential
VT
vGS
Allen and Holberg - CMOS Analog Circuit Design
Op Amp Operating in Weak Inversion Consider the two-stage op amp with reduced currents and power supplieds, gm2gm6 1 AV = g +g = n2n6( kT/q) 2( l2+l4) ( l6+l7) ( ds2 ds4) ( gds6+gds7) where, gm1 ID1 GB = C = (n kT/q)C 1
2I D1 n1kT and SR = C = 2GB q
VDD M3
M4 M6 C
M1
M2
M7
M5
VSS
Allen and Holberg - CMOS Analog Circuit Design
Design Example Calculate the gain, unity-gain bandwidth, and slew rate of the previous previous two-stage op amp used in weak inversion if: ID5 = 200nA
n P = 1.5
λP = 0.02V -1
L = 10 µm
nN = 2.5
λN = 0.01V -1
C = 5pF
T = 27˚C
1 AV = (1.5)(2.5)(0.026)(2)(0.1+0.02)(0.01+0.02) = 5698 100.10-9 GB = = 307.69Krps or 48.97KHz (2.5)(0.026)(5 .10-12) SR = 2(153.85 .103)(2.5)(0.026) = 0.04V/ µs If V DD = -V SS = 2.5, the power dissipation is 0.2 µW assuming ID7 = I D5.
Allen and Holberg - CMOS Analog Circuit Design
Push-Pull Micropower Op Amp First stage clamped (low gain, low bias current)VDD M3
M4
M8
M6 M2
M1
CC VB
M5 M7
M9
VSS Gain enhancement for Push-Pull Micropower Op Amp M11 M3
M10
M12
M4
M8
M6 M2
M1
CC VB
M5
M13 M7
M9
VSS
Allen and Holberg - CMOS Analog Circuit Design
Push-Pull Cascode Micropower Op Amp VDD M3
M4
M8
M6 M1
M2
VB1
VDD M10
VB2 VB
M5
VSS M11 M7
M9
VSS 1 1 + nN n P AV = 2 2 ≈ 10,000 Vt ( λ P n P + λ N 2 n N 2 ) self-compensating Low power << 1 µW
CC
Allen and Holberg - CMOS Analog Circuit Design
Micropower Op Amp VDD M5
M9
M6
M7 M8
va v-1
vb M3
M4
M10 M16
M15
100nA
v2+
vo M17
M2
VBIAS
M18
M19
M14 M12
M11
120nA
20nA
20nA
VSS Pdiss = |V DD-V SS|(260nA) vo = v agm9 ro - v bgm10 ro ≈ gm9 ro(v a - v b) ; g m9 = gm10 m1 0 where ro ≈ (rds10gm18 m1 8rds18)||(rds12 gm19 m1 9rds19) and nP 1 + k (v a - v b) = va - v b = n 1 - k ( v 2 -v 1 ) N (See following pages)
Allen and Holberg - CMOS Analog Circuit Design
Small-Signal Analysis va
vb 1 gm5
gm3v1
gm8 vb
gm7va
1 gm6
gm3 gm 8 va = -v1 g - vb g m5 m5 gm4 gm 7 vb = -v2 g - va g m6 m6
v1ggm5m3 v2gm4 gm6
va =
=
gm3 v1g
gm8 -g
gm4 v2g
-1
-1
gm8 -g
gm7 -g
-1
m5 m6
m4
m5
m5
-1
gm8 -g m5
gm7 -g m4
-1
=
va vb
gm 3 gm4gm 8 -v - v 1 g +v 2 g g m5
m5 m6 gm7gm 8 1- g g m5 m6
gm4v2
Allen and Holberg - CMOS Analog Circuit Design
vb =
-1 gm7 -g m6 -1
gm3 v1g m5 gm4 v2g m6 gm8 -g m5
gm7 -g
m4
-1
=
gm 4 gm3gm 7 -v - v 2 g +v 1 g g m6
m5 m6 gm7gm 8 1- g g m5 m6
g m 4 g m 8 gm4 g m 3 g m 7 gm3 -v1g +v 2 g g - -v2g +v 1 g g m5 m6 m6 m5 m6 m5 va - v b = gm7gm 8 1- g g m5 m4 gm3 = gm4 = g mI ; gm5 = g m6 = g mII ; gm7 = g m8 = g mIII Then g mI g mIII gmI g mI g mIII gmI - -v +v 1 -v1g +v 2 gmII2 2gmII gmII2 mII va - v b = g mIII 2 1- gmII2 gmIII Define: g =k mII gmI ( 1 + k) ( v 2 -v 1 ) g mII va - v b = = ( v 2 -v 1 ) 1-k 2
gmI gmII 1-k
gmI 1 va - v b = g ( v 2 -v 1 ) mII 1 - k Consider dc currents under balanced condititions: I4 = I 6 + I 7 I3 = I 5 + I 8
I8 S 8 ⇒ in W.I. gm is proportional to I I6 = S6 I 8 S8 I7 S7 = = k; I6 S6 I5 = S5 = k Since under balanced conditions I3 = I 4 ; I4 = I 5 I4 = I 6 (1 + k) I3 = I 5 (1 + k) Again, since g m ∝ I in weak inversion, then gm4 ∝ I 6(1 + k) or gm4 =
I6 kT (1 + k) nN q
and gm3 ∝ I5(1 + k) since gm3 = g m4 = g mI
⇒ gmI =
Also gm4 = g mII =
I6 kT n N q
then gmI nP gmII = n N (1 + k)
I6 k T (1 + k) n N q
Allen and Holberg - CMOS Analog Circuit Design
finally: nP va - v b = n N
1 + k v -v 1 ) 1 - k ( 2
1+k
≈ 1 - k ( v 2 -v 1 ) Therefore, 1+k v o = g m9 ro 1-k vid
Allen and Holberg - CMOS Analog Circuit Design
OTA CURRENT OVERDRIVE Need large sinking and source currents without having to have large quiescent currents. One possible solution uses "tail current boosting" Assume that S 3 = S4 = S11 = S13, S18 = AS17, S15 = S16 = S17 = ..
M11
M13
M4
M3 I1 I2 -
M1
I1 I2
M2
+
I2 +I1 +A I2 -I1
I1 M15
I2
A I2 -I1
I10
M18 M9
M10 M19
I2 -I1
M16 M17
W18 = AW17 L18 L17
I19 ≈ 0
Allen and Holberg - CMOS Analog Circuit Design
Principle in Achieving Current Overdrive Differential amplifier transconductance characteristics iD I10 (overdrive)
I10 gm 1 8 gm 1 3 = gm 1 3 1- g 1- gm9 A m17 gm14
Allen and Holberg - CMOS Analog Circuit Design
A Dynamically Biased Micropower Op Amp VDD M12
M8
M13
M3 M4
M11
I1 -
M1
M14
M5A
I2 M2
+
VBP
M5B
vOUT
VBN
M6B
I10 M7
M15
M16 M17
M18 M9
M10 M19
M20 M21
M22
M6A VSS
Allen and Holberg - CMOS Analog Circuit Design
Parametric Overdrive Curves for Dynamically Biased Op Amp 2
A=2
A = 1.5 IOUT 1 I10
A=1 A = 0.3 A=0
0
0
1 vIN / nV nVt
2
Allen and Holberg - CMOS Analog Circuit Design
IX.7 - DYNAMICALLY BIASED AMPLIFIERS Dynamic circuits take advantage of the fact that many applications are synchronously clocked resulting in periods of time where the circuits is not functioning. Will examine: - Dynamic or switched resistors - Dynamically biased amplifiers - Dynamically biased, push-pull, cascode op amp Two Phase Clock φ1 φ1 switches on
φ1 switches off
0
1
2
3
4
5
t/T
1
2
3
4
5
t/T
φ2 φ2 switches on
φ2 switches off
0
A Switched Resistance Realization φ2
φ1 D
Pretune circuit
φ2
G
φ2
CG
VSS S
Switched resistor
RFET
φ1
Allen and Holberg - CMOS Analog Circuit Design
A Continuous Time Resistor Realization with Increased Signal Swing i + D VC
G1
+ D2 G2
M2
VSS
+ -
S2
D1 M1
VSS vDS
S1
RFET
VC - S
Implementation of the Continuous Time Switched Resistor Realization using Dynamic Techniques
φ2 φ2
φ1 CG VSS M2
Pretune circuit
RFET
φ2 φ2
VSS CG
M1
Switched resistor
φ1
Allen and Holberg - CMOS Analog Circuit Design
Dynamically Biased Inverter VDD CB M2
φ2
vOUT
M1
+ -
iD
COS
φ1 vIN
φ2
φ2
VSS
During phase 2 the offset and bias of the inverter is sampled and applied to C OS and C B. During phase 1 C OS is connected in series with the input and provides offset cancelling plus bias for M1. C B provides the bias for M2.
Allen and Holberg - CMOS Analog Circuit Design Dynamic, Push-pull, Cascode Op Amp Simplified schematic -
VDD
M8
VDD
+ VB2 -
φ1
φ2 M4
M7
M3 C2
φ2
IB
vIN
φ1
VDD
vOUT
+ vIN
C1 VSS
M2
M6
φ1 M5
φ2 M1
+ VB1 VSS
VSS
Allen and Holberg - CMOS Analog Circuit Design Dynamic, Push-pull, Cascode Op Amp - Cont'd
Phase 1 Clock Period VDD M8 M7
VDD
+ C2 -
IB
+ VDD - V B2 - v IN + vIN
C1 + -V -V vIN SS B1
VSS
M6
M5 VSS
Phase 2 Clock Period VDD M4
+ vIN - v IN + VDD - V B2
M3
VDD
+ - C2
+ VDD - V B2 - v IN vIN + -V -V vIN SS B1
vOUT C1 M2
- - v+ + V + V vIN IN SS B1
VSS
M1 VSS
Allen and Holberg - CMOS Analog Circuit Design
A Dynamic Op Amp which Operates on Both Clock Phases VDD
φ2 M8
VDD
φ1
M4
φ2
M7
M3 C2
RB
vIN
φ2
φ1
C4
φ1
vOUT
C3 M2
M6
φ2 M5
φ1
VDD
φ2 + vIN
C1 VSS
φ1
VSS
φ1 M1
φ2
VSS
1.6 mW dissipation
Set Settling time = 10 ns into 5 pF
GB ≈ 130 MHz with C L = 2.2 pF
1.5 µm technology
Used with a 28.6 MHz clock to realize a 5th order switched capacitor filter with a cutoff frequency of 3.5 MHz.
Chara Charact cteri erizat zatio ionn and defi defini nitio tionn of D/A D/A conver converter terss Volt Voltag agee sca scali ling ng D/A D/A con conve vert rter erss Char Charge ge scal scalin ingg D/A D/A con conve vert rter erss Volta Voltage ge and and cha charg rgee scal scalin ingg D/A D/A conv convert erters ers Othe Otherr type typess of of D/A D/A con conve vert rter ers, s, Chara Charact cteri erizat zatio ionn and defi defini nitio tionn of A/D A/D conver converter terss Seri Serial al A/D A/D co convert verteers Medi Medium um-s -spe peed ed A/D A/D conv conver erte ters rs High-spe High-speed ed A/D convert converters ers (Flash, (Flash, two-ste two-step, p, multip multiple le pipe) pipe) Oversa Oversampl mpled ed A/D conv convert erters ers Example Exampless of A/D converte converters, rs, limits limits of A/D A/D converter converterss
Organization
Chapter 10 D/A and A/D Converters
Chapter 11 Analog Systems
SYSTEMS
Chapter 7 CMOS Comparators
Chapter 8 Simple CMOS OTA's
Chapter 9 High Performance OTA's
COMPLEX
CIRCUITS Chapter 5 CMOS Subcircuits
Chapter 6 CMOS Amplifiers
SIMPLE
Chapter 2 CMOS Technology
DEVICES
Chapter 3 CMOS Device Modeling
Chapter 4 Device Characterization
Allen and Holberg - CMOS Analog Circuit Design
Page X.0-2
Importance of Data Converters in Signal Processing
ANALOG SIGNAL (Speech, sensors, radar, etc.)
DIGITAL PROCESSOR (Microprocessor)
PRE-PROCESSING (Filtering and analog to digital conversion)
POST-PROCESSING (Digital to analog conversion and filtering)
CONTROL ANALOG
A/D
DIGITAL
D/A
ANALOG
ANALOG OUTPUT SIGNAL
Allen and Holberg - CMOS Analog Circuit Design
Page X.0-3
A/D and D/A Converters in Data Systems Analog computer Audio signals Video signals Power sources Chemical cells Synchros/resolvers Pressure cells Thermocouples Strain gages Bridges Photomultiplier Etc.
Multiplexer
Sample and Hold
Analog to Digital Converter
Digital System
Transmission links Magnetic tape recorders Computer memories Paper tape recorders Real-time processor Comparators System and process controls Numerical machine controls Minicomputers Miroprocessors Etc.
Reference
Transmission links Magnetic tape recorders Computer memories Paper tape recorders Real-time processor Comparators System and process controls Numerical machine controls Minicomputers Miroprocessors Etc.
Digital System
Digital to analog converter
Reference
Filter
Amplifier
Audio systems Controllers Actuators CRT displays Analog recorders Analog computers Hybrid computers Analog meters Transducers Servomotors X-Y plotters Modems Etc.
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-1
X.1 - CHARACTERIZATION AND DEFINITION OF CONVERTERS
General Concept of Digital-to-Analog (D/A) Converters Reference b0 b1 b2 b3
Digital-toAnalog Converter
vOUT or iOUT
bN-1
vOUT = KV K Vref D
or iOUT = KI ref D
where K = gain constant (independent of digital input) b0 b1 b2 bN-1 D = N + N-1 + N-2 + ···· + 1 = scaling factor 2 2 2 2 Vref (Iref ) = voltage (current) reference bN-1 = most significant bit (MSB) b0 = least significant bit (LSB) For example, b1 b2 b N - 1 b0 vOUT = KVref N + N-1 + N-2+····+ 1 2 2 2 2 N-1 1 = KVref N b j2 j 2 j=0
∑
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-2
Basic Architecture of a D/A Converter Continuous Time D/A ConverterVoltage References
Vref
DVref
Scaling Network
vOUT = KDVref
Output Amplifier
Binary Switches
b0 b1 b2
bN-1
Clocked D/A ConverterVref b0 b1 b2 Latch
Digital Vout to analog converter
bN-1 Clock
Sample and hold
* Vout
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-3
Classification of D/A Converters Done by how the converter is scaledD/A Converters
Serial Charge
Parallel Voltage
Charge
Voltage and Charge Slow
Fast
Current
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-4
Static Characterization of D/A Converters Ideal input-output D/A converter Static Characteristic 1.000 0.875 0.750 e u l a V t u p u O g o l a n A
1 LSB 0.625
Ideal analog output
0.500 0.375 0.250 0.125 0.000 0 00
001
010
01 1 100 101 Digital Input Code
Vref An ideal LSB change causes an analog change of N 2
11 0
1 11
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-5
Definitions is the smallest analog change resulting from a 1 LSB digital change (quantified in terms of N bits).
Resolution
is the inherent uncertainty in digitizing an anlog value with a finite resolution converter.
Quantization Noise
Infinite resolution analog output - finite resolution analog output 0.5LSB
0.5
VREF 2N
=
VREF 2 N+1
Digital Input Code -0.5LSB 00 0 Dynamic range (DR)
difference.
001
010
011
-0.5
VREF -VREF = N 2 2 N+1
is the ratio of FS to the smallest resolvable
2 N − 1 VREF FS 2N N DR = LSBchange = 1 =2 −1 VREF N 2 DR(dB) = 20 log 10( 2 N − 1) ≅ 6N dB
Signal to noise ratio (SNR) for a sawtooth waveform Approximating FS = LSB(2 N -1) ≅ LSB(2 N), 2N FullscaleRMSvalue 2 2 12 N SNR = RMSvalueofquantizationnoise = 1 = 2 2 2 12 6 SNR (dB) = 20 log 10 2 2 N
= 20 log 10 6 + 20 log 10(2N) 2
= 20 log 10(1.225) + 6.02N = 1.76 dB + 6.02N dB
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-6
Definitions - Continued is the the maximum DAC analog output value. It is one LSB less than V REF . Full scale (FS)
FS = VREF RE F
2 N −1 2N
A monotonic D/A (A/D) converter is one in which an increasing digital input code (analog input) produces a continuously increasing analog output value (digital output code). Offset error is
a constant shift of the actual finite resolution characteristic from the ideal infinite resolution characteristic.
Gain error is
a deviation between the actual finite resolution characteristic and the ideal infinite resolution characteristic which changes with the input .
Integral nonlinearity (INL) is
the maximum difference between the actual finite resolution characteristic and the infinite resolution characteristic.
Differential nonlinearity (DNL) is
the maximum deviation of any analog FS output changes caused by an input LSB change from its ideal change of N 2 .
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-7
3-BIT D/A CONVERTER ILLUSTRATION
VREF
Ideal D/A conversion
7 8 t u p t u o ) g F o l a E R n a V d o e t z i o l t a i a m r R o ( N
3 4
1 LSB
5 8 1 2
Ideal analog output
3 8 1 4 1 8 0 000 0
001 1 8
0 10 2 8
011 3 8
10 0 4 8
1 01 5 8
110 6 8
1 11 7 8
Digital input, code and fractional value Ideal relationship
8 8
Allen and Holberg - CMOS Analog Circuit Design
7 8
Page X.1-8
7 8 Gain Error
5 8
5 8
3 Offset 8
3 8
1 8 0
1 8 0
Error
000 001 010 011 100 10 1 110 111
Offset Error
7 8
000 001 010 011 100 1 01 110 111
Gain Error
7 8
Nonlinearity
5 8
5 8
3 8
3 8
1 8 0
1 8 0
000 00 1 0 10 0 11 100 101 11 0 1 11
Linearity Error
Nonmonotonicity
000 00 1 0 10 0 11 100 101 1 10 1 11
Nonmonotonicity (Due to Excessive Differential Nonlinearity)
Typical sources of errors
Allen and Holberg - CMOS Analog Circuit Design
Page X.1-9
Integral and Differential Linearity for a D/A Converter D/A Converter with ±1.5 LSB integral nonlinearity and ±0.5 LSB differential nonlinearity 10
0.5 LSB
9
) B 8 S L l 7 a e d I ( 6 t u p 5 t u o 4 g o l a n 3 A 2
3-BIT VOLTAGE SCALING D/A CONVERTER Assume that b0 = 1, b1 = 0, and b 2 = 1 MSB: b2 LSB: b0 +VREF
b0
b0
b1
b1
b2
b2
R/2 8 R 7 R 6 R 5 R
vOUT
4 R 3 R 2 R 1 R/2
vOUT =
VREF VREF 11 RE F D + 0 . 5 = 2D+1 2D +1 = 0.6 0 .687 875V 5V = ( ) ( ) REF 8 16 16 VREF
Allen and Holberg - CMOS Analog Circuit Design
Page X.2-2
3-BIT VOLTAGE SCALING D/A CONVERTER - CONT'D Input-Output Characteristics: VREF 7VREF 8 6VREF 8 5VREF T 8 U O 4VREF 8 3VREF 8 2VREF 8 VREF 8 000
001
010
011
100
101
110
Advantages: Inherent monotonicity Compatible with CMOS technology Small area if n < 8 bits Disadvantages: Large area if n > 8 bits Requires a high input impedance buffer at output Integral linearity depends on the resistor ratios
111
Input
Allen and Holberg - CMOS Analog Circuit Design
Page X.2-3
3-BIT VOLTAGE SCALING D/A CONVERTER WHICH MINIMIZES THE SWITCHES Require time for the logic to perform b0
b1
b2
+VREF R/2 8
3-to-8 Decoder
R 7 R 6 R 5 R 4 R 3 R 2 R 1 R/2
vOUT
Allen and Holberg - CMOS Analog Circuit Design
Page X.2-4
Accuracy Requirements of a Voltage Scaling D/A Find the accuracy requirements for the voltage scaling D/A converter as a function of the number of bits N if the resistor string is a 5 micron wide polysilicon strip. If the relative accuracy is 2%, what is the largest number of bits that can be resolved to within ±0.5 LSB? Assume that the ideal voltage to ground across k resistors is kR V k = N VREF 2 R RE F The worst case variation in V k is found by assuming all resistors above this point in the string are maximum and below this are minimum. Therefore, Vk' =
kRminVREF ( 2N-k) R max ma x +kR m in
The difference between the ideal and worst case voltages is, Vk Vk' kRmin kR = VREF VREF 2NR ( 2N-k) R max ma x +kR m i n Assuming that this difference should be less than 0.5 LSB gives, kRmin kR 0.5 0. 5 < 2NR ( 2N-k) R max 2N ma x +kR m i n Expressing Rmax as R+0.5 ∆R and R min as R-0.5 ∆R and assuming the worst case occurs midway in the resistor string where k=0.5 ( 2N) and assuming that 5 micron polysilicon has a 2% relative accuracy gives, 0.5(R-0.5 ∆R) 1∆R 1 0.5- 0.5(R+0.5 ∆ R)+0.5(R-0.5 ∆ R) = 4 R < 2 2-N
⇒
∆R
1 < R 2N-1
or
0.25(0. 0.25(0.02) 02) < 0.5 0.5 ( 2-N) ⇒ N = 6
Allen and Holberg - CMOS Analog Circuit Design
Page X.2-5
R-2R LADDER DAC's Configuration: R
A 2R
2R
R
B
2R
b0
R
C
R
2R
b1
2R
b2
2R
b N-1
bN
+ -
Equivalent circuit at A:
R
A
b0 VREF + 2 -
Equivalent circuit at B: R + -
b0 VREF 2
R
R
B 2R + b1 VREF -
+
= -
B
( b4 + b2 )V 0
1
REF
Finally, the equivalent circuit at Q: + -
Q
(
R b0 b1 b2 bN-1 VREF + + +...+ 2N 2N-1 2N-2 2
)
sign bit
+
R bN
+
VREF
R
vOUT
VREF
Allen and Holberg - CMOS Analog Circuit Design
Page X.3-1
X.3 CHARGE SCALING D/A CONVERTER
Binary weighted capacitor array: -
φ
C
C 2
C 4
SN-1
SN-2
SN-3
C N-2 2
C N-1 2
C 2
v OUT
N-1
+
1
φ
2
φ
2
S1
φ
S0
φ
2
2
φ
2
Terminating capacitor
VREF
Operation: 1.) During φ1, all capacitors are discharged. 2.) During φ 2 , capacitors with b i = 1 are connected to V REF and capacitors with b i = 0 are grounded. 3.) The resul resulti ting ng outp output ut vol volta tage ge is, is, bN-1C b N- 2 C / 2 b N- 3 C / 4 b 0 C / ( 2N-1) vOUT = VREF 2C + + +...+ 2C 2C 2 C
If Ceq. is defined as the sum of all capacitances connected to V REF, then Ceq. vOUT = 2C VREF RE F
+ VREF -
Ceq. 2C-Ceq.
vOUT
Allen and Holberg - CMOS Analog Circuit Design
Page X.3-2
Other Othe r Versions of the Charge Scaling D/A Convert Conve rter er Bipolar Operation: Charge all capacitors to V REF . If bi = 1, connect the capacitor to ground, if b i = 0, connect the capacitor to V REF . Will require an extra bit to decide whether to connect the capacitors initially to ground or to V REF . Four-Quadrant Operation: If VREF can have ±values, then a full, four quadrant DAC can be obtained. Multiplying DAC: If VREF is an analog signal (sampled and held), then the output is the product of a digital word and an analog signal and is called a multiplying DAC (MDAC).
Allen and Holberg - CMOS Analog Circuit Design
Page X.3-3
Influence of Capacitor Ratio Accurcy on No. of Bits Use the data of Fig.2.4-2 to estimate the number of bits possible for a charge scaling D/A converter assuming a worst case approach and the worst conditions occur at the midscale (1 = MSB). The ideal output of the charge scaling DA converter is, vOUT Ceq. VREF = 2C The worst case output of the charge scaling DA converter is, Ceq.(min) v'OUT VREF = 2C-C eq. + C eq. eq . eq .(min) (max)+C The difference between the ideal output and the worst case output is, vOUT v 'O U T Ceq.(min) 1 = VREF VREF 2 ( 2C-C eq. eq.) (max) ± C eq.(min) Assuming the worst case condition occurs at midscale, then C eq. = C vOUT v 'O U T C(min) 1 = 2 - C ∴ V - V (max) -C (min) REF REF If C(max) = C + 0.5 ∆C and C (min) = C - 0.5 ∆C, then setting the difference between the ideal and worst case to 0.5LSB gives,
or or
0.5 ( C (max) ±C (min)) -C (min) ≤ 0.5( 1/2N) C (max) +C(min) 1 C(max) - C (min) ≤ N ( C (max) +C(min)) 2
∆C ≤
1 2C ⇒ 2N
∆C
-N ⇒ 2 ≤ 2C
∆C
1
C ≤ 2N-1
A 50 µm x 50 µm unit capacitor gives a relative accuracy of 0.1% and N = 11 bits. It is more appropriate that the relative accuracy is a function of N. For example, if ∆C/C ≈ 0.001 + 0.0001N, then N=9 bits.
Allen and Holberg - CMOS Analog Circuit Design
Page X.3-4
Increasing the Number of Bits for a Charge Scaling D/A Converter Use a capacitive divider. For example, a 13-bit DACLSB Array
MSB Array +
1.016pF (Attenuating capacitor) 1pF
2pF
8pF
4pF
16pF
32pF 1pF
2pF
4pF
8pF
16pF 32pF
v OUT
64pF
1pF b0
b1 b0
b2 b1
b3 b2
b4 b3
b5 b4
b6 b6
b5
b8
b7
b9
b7
b8
b 11
b 10 b9
b 10
b12 b 11
b 12 +VREF
-VREF 5
VL =
∑ i=0
±bi Ci VREF ∑ 127 i=6 12
±b iCi VREF
VR =
64
An equivalent circuit1 1 64 + = 1 C = ⇒ 64 C 63 ≈ 1.016 + 64pF
Removal of the Amplifier Input Capacitance Effects Use the binary weighted capacitors as the input to a charge amplifier. Example of A Two-Stage Configuration:
VREF
φ
1
b0 b 0
φ
1
C 8
b1 b1 φ1 b2 b2 φ 1 b3 b 3 φ1 b4 b4 φ1 b5 b5 C 4
C 2
φ b b 1 6 6
φ b b 1 7 7
C 4
C 2
C 8
C
C 8
φ
1
2C
+
v OUT
C
Allen and Holberg - CMOS Analog Circuit Design
Page X.4-1
X.4 - VOLTAGE SCALING-CHARGE SCALING DAC'S VREF
R(2M-1) SF v OUT
R(2M-2)
Ck-1 R(2M-3)
k-1
2
C k-2 C
k-2
2
C1 2C
C0 C
C
C
M=4
k=8 SA R1 SB
A S(k-1)A
S(k-2) A
S1A
S0A
S(k-1)B
S(k-2) B
S1B
S0B
R0
B
Advantages:
• Resistor string is inherently monotonic so the first M bits are monotonic.
• Can remove voltage threshold offsets. • Switching both busses A and B removes switch imperfections. • Can make tradeoffs in performance between the resistors and capacitors.
•
Example with 4 MSB's voltage scaling and 8 LSB's charge scaling:
Allen and Holberg - CMOS Analog Circuit Design
Page X.4-2
Voltage Scaling, Charge Scaling DAC - Cont'd Operation: 1.) SF, SB, and S1B through Sk,B are closed discharging all capacitors. If the output of the DAC is applied to any circuit having a nonzero threshold, switch S B could be connected to this circuit to cancel this threshold effect. 2.) Switch SF is opened and buses A and B are connected across the resistor whose lower and upper voltage is V 'REF and V'REF + 2-MVREF respectively, where b1 b2 b M - 1 b0 V'REF = Vref M + M-1 + M-2+····+ 1 2 2 2 2 + 2k-1 C
2-MV
A
+ REF
' V REF
- B +
2k-2 C
2C
C
C
vOUT S k,A
S k-1,A
S 2A
SA
S k,B
S k-1,B
S 2B
SB
-
-
3.) Final Final step step is is to dete determin rminee whethe whetherr to connect connect the the bottom bottom plates plates of the capacitors to bus A (b i=1) or bus B (b i=0). Ceq. 2-MVREF
' V REF
+
+ + -
2KC - Ceq.
vOUT -
M+K-1 vOUT = bi2-(M+K-i)VREF i=0
∑
Allen and Holberg - CMOS Analog Circuit Design
Page X.4-3
Charge Scaling, Voltage Scaling DAC Use capacitors for MSB's and resistors for LSB's vOUT
2N-1C
2 N-2C
2 N-3C
VREF 4C
2C
C
C
R
VREF
Switch network
MSBs
R
R LSBs
R
R
•
Resistors must be trimmed for absolute accuracy.
•
LSB's are monotonic.
Allen and Holberg - CMOS Analog Circuit Design
Page X.5-1
X.5- OTHER TYPES OF D/A CONVERTERS
CHARGE REDISTRIBUTION SERIAL DAC VREF
Precharge to VREF if bi = "1" Redistribution switch S1 S4
Close S4: VC2 = 0 Start with LSB firstClose S2 (b0=1): VC1 = VREF VREF Close S1: VC1 = 2 = VC2 Close S3 (b1=0): VC1 = 0 VREF Close S1: VC1 = V C2 = 4 Close S2 (b2=1): VC1 = VREF 5 Close S1: VC1 = V C2 = 8 VREF RE F Close S2 (b3=1): VC1 = VREF 13 Close S1: VC1 = VC2 = 16 VREF RE F
Comments: • LSB must go first. • n cycles to make an n-bit D-A conversion. • Top plate parasitics add error. • Switch parasitics add error.
Allen and Holberg - CMOS Analog Circuit Design
Page X.5-2
ALGORITHMIC SERIAL DAC Pipeline Approach to Implementing a DAC: 1/2
1/2
0
∑
z-1
b0
1/2
1/2 ∑
z-1
b1
LSB
∑ bN-1
MSB
VREF
b 0 -N bN-1 -1 bN-2 - 2 vOUT(z) = 2 z + 4 z +....+ N z VREF RE F 2 where bi = 1 or 0 Approaches: 1.) Pipe Pipeli line ne wit withh N casc cascad aded ed sta stage ges. s. 2.) 2.) Alg Algorit rithmic mic. biz-1VREF vOUT(z) = 1-0.5z - 1
z-1
vOUT
Allen and Holberg - CMOS Analog Circuit Design
Page X.5-3
Example of an Algorithmic DAC Operation Realization using iterative techniques: +VREF 0
A (Bit "1") B
+ +
∑
Sample and hold
VOUT
(Bit "0") 1 2
Assume that the digital word is 11001 in the order of MSB to LSB. The steps in the conversion are: 1.)VOUT(0) is zeroed. 2.)LSB = 1, switch A closed, VOUT(1) = V REF. 3.) Next LSB = 0, switch switch B closed, closed, VOUT(2) = 0 + 0.5V REF VOUT(2) = 0.5V REF. 4.) Next LSB = 0, switch switch B closed, closed, VOUT(3) = 0 + 0.25V REF VOUT(3) = 0.25V REF. 5.) Next LSB = 1, switch switch A closed, closed, VOUT(4) = V REF + (1/8)V REF VOUT(4) = (9/8)VREF. 6.) Finally, Finally, the MSB is is 1, switch A is closed, and VOUT(5) = V REF + (9/16)VREF VOUT(5) = (25/16)V REF 7.)Finally, the MSB+1 is 0 (always last cycle), switch A is closed, and VOUT(6) = (25/32)V REF
Allen and Holberg - CMOS Analog Circuit Design
Page X.6-1
X.6 - CHARACTERIZATION OF ANALOG TO DIGITAL CONVERTERS
General A/D Converter Block Diagram
Digital Processor
x(t) Filtering
Sampling
A/D Converter Types 1.) 1.) Serial. 2.) 2.) Medium dium spe speeed. 3.) High High spee speedd and high high per perfor forman mance ce.. 4.) New New conver converte ters rs and and techni technique ques. s.
Quantization
Digital Coding
y(kTN)
Allen and Holberg - CMOS Analog Circuit Design
Page X.6-2
Characterization of A/D Converters Ideal Input-Output Characteristics for a 3-bit ADC
111
Ideal A/D conversion 110 r e b m u 101 n l a t i g i d 100 t u p t u O 011
Missed codes due to excessive differential nonlinearity
001 1 FS 4
1 FS 2
3 FS 4
FS
000
1 FS 4
1 FS 2
3 FS 4
Analog input value
Analog input value
Integral Nonlinearity
Differential Nonlinearity
FS
Allen and Holberg - CMOS Analog Circuit Design
Page X.6-4
Sampled Data Aspect of ADC's
S-H command
Sample Hold e d u t i l p m A
Hold ta
ts
Output valid for A/D conversion
S*
S(t) S* S(t) t
Tsample = ts + ta ta = acquisition time ts = settling time tADC = time for ADC to convert analog input to digital word. Conversion time = ts + ta + tADC. kT Noise = C V2 (rms)
Operation: 1.) Initia Initially lly vint = 0 and vin is sampled and held (Vin* > 0). 2.) Reset Reset by integr integrati ating ng until until vint(0) = Vth. 3.) Inte Integr grat atee Vin* for Nref clock cycles to get, Nref T * ⌠ * vint(t1) = vint (Nref T) = k ⌡Vindt+vint(0) = kNref TVin + Vth 0 * 4.) The Carry Output on the the counter counter is used to switch the integrato integratorr from Vin to -V REF . Integrate until v int is equal to Vth resulting in NoutT+t1 ⌠ ⌠-V REFdt = Vth vint(t1 + t2) = vint(t1) + k ⌡ t1 Nout * * ∴ kNref TVin + Vth - kVREFNoutT= Vth ⇒ VREF N =Vin ref
Allen and Holberg - CMOS Analog Circuit Design
Page X.7-3
Waveform of the Dual -Slope A/D Converter
vin V'''in Vin'' Vin' Vth 0
t
0 Reset
t1 = N ref T t0 (start)
t2' t2'' t'''2 t2 = N out T
• Very accurate method of A/D conversion. -2( 2N) T • Requires a long titime -2
Assume non-overlapping clocks φ1 and φ2. During φ1, C1 is charged to v1[ ( n-1) T] giving a charge of q1[ ( n-1) T] on C1. During φ2, the charge across C1 is added to the charge already on C2 which is q2[ ( n-1) T] resu result ltin ingg in a new new cha charg rgee acr across oss C2 designated as q2( nT) . The charge charge equatio equationn can be written written as, or
A Voltage-Charge Scaling Successive Approximation ADC Vref SF
R1 R2
_
R3
2K-1C
2C
C
+
A B
SA SB
R2 M-1
C
R2M
Capacitor switches
* Vin
Resistor switches
Clock
Successive approx. register and switch control logic (M + K) bit output of A/D
start
Operation: 1.) 1.) With SF closed, the bottom plates of all capacitors are connected through switch S B to Vin*. (Automatically accounts for voltage offsets). 2.) 2.) Afte Afterr SF is opened, a successive approximation search among the resistor string taps to find the resistor segment in which the stored sample lies. 3.) Buses A and B are are then then connected connected across across this segment and the capaci capacitor tor bottom plates plates are switched in a successive approximation sequence until the comparator input voltage converges back to the threshold voltage. Capable of 12-bit monotonic conversion with a DL of ±0.5LSB within 50µs.
Conversion Sequence: 1.) Assume Assume first first K MSB's MSB's have have been been deci decided ded so that that,, 1 1 1 Digital word = aM N + aN-1 N-1 + ... + aN-K+1 N-K+1 + . 2 2 2 2.) Assume Assume (K + 1)th 1)th MSB is is 1 and and compar comparee this this anal analog og outpu outputt with Vin* to determine aN-K. 3.)
Store aN-K in the DATA storage register and contiune.
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-4
CHARGE REDISTRIBUTION SERIAL DAC VREF
Precharge to VREF if bi = "1" Redistribution switch S1 S4
S2 S3
+ VC1 -
C1
Precharge C1 to ground if bi = "0"
C2
+ VC2 -
Conversion sequence: sequence:
Initially discharge S4
C1 = C2 b0 = LSB b1 = NLSB . . . bN = MSB
4 Bit D/A Converter INPUT WORD: 1101 1
13/16
3/4
VC1 /VREF 1/2 1/4 0
2
4
6
8
1
13/16
3/4
VC2 /VREF 1/2 1/4 0
2
4
6
8
Close S4: VC2 = 0 Store with LSB firstClose S2 (b0=1): VC1 = VREF VREF Close S1: VC1 = 2 = V C2 Close S3 (b1=0): VC1 = 0 VREF Close S1: VC1 = V C2 = 4 Close S2 (b2=1): VC1 = VREF 5 Close S1: VC1 = V C2 = 8 VREF RE F Close S2 (b3=1): VC1 = VREF 13 Close S1: VC1 = V C2 = 16 VREF RE F
Comments: • LSB must go first. • n cycles to make an n-bit D-A conversion. • Top plate parasitics add error. • Switch parasitics add error.
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-5
Serial Serial ADC Waveform for an Input of (13/16Vref ) 1 3 4
A 1-BIT/PIPE PIPELINE A/D CONVERTER Single Bit/Stage, N-Stage Pipeline Converter
• Converter in 1 clock cycle using storage registers • Requires N comparators • Dependent upon passive component linearity • Can use error correcting algorithms and self-calibration techniques Block Diagram of the 1-Bit/Pipe A/D Architecture MSB
bi
LSB
+ -
+ -
+ -
2
* Vin
∑
±1
vi-1
2
z-1
Vref
∑
±1 ith stage
bi=+1ifVi-1>0 Vi = 2Vi-1 - biVref where b =-1ifV <0 i i-1
where Ai and bi are the gain and bit value of the ith stage
vi
z-1
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-7
Graphical Examples illustrating operation Example 1 x2
-VREF VREF
1
1
1
3/4
3/4
3/4
1/2 1/4
1/2 1/4
1/2 1/4
0
0
0
0
-1/4
-1/4
-1/4
-1/4
-1/2
-1/2
-1/2
-1/2
-3/4 -1
-3/4 -1
-3/4 -1
-3/4 -1
B= 1
B=1
1 x2
-VR -VREF
3/4 1/2 1/4
x2
B=0
+VR +VREF
B=1
Example 2 1
1
1
3/4 1/2
3/4 1/2
3/4 1/2
1/4 0
1/4 0
-1/4
-VREF
x2 -VREF
1 3/4 1/2
1/4 0
1/4 0
-1/4
-1/4
-1/4
-1/2 -3/4
-1/2 -3/4
-1/2 -3/4
-1/2 -3/4
-1
-1
-1
-1
B= 0
x2
B=1
B=0
x2
+VREF
B=1
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-8
IDEAL STAGE PERFORMANCE Vi Vi-1 ith ith Stage Stage Plot Plot of: V = 2 V − bi ref ref Vi Vref 1 bi+1 =+1 -1
-.5
.5
0
1
bi+1 =-1
bi , bi+1
-1
bi =-1 [00]
[01]
bi =+1 [10]
[11]
1.) bi+1 must change at 0, and ±0.5Vref . (when Vi-1=0 and ±0.5Vre f ) 2.) bi must change at Vi=0. 3.) Vi cannot exceed Vref . 4.) Vi should not be less than Vref when Vi-1=±Vref .
Vi-1 Vref
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-9
IDEAL PERFORMANCE Example Assume V in* = 0.4V and Vref = 1V Input to the ith stage, V i-1
RESOLUTION LIMITS OF THE 1-BIT/STAGE PIPELINE ADC 1st-Order Errors of The 1-Bit/Stage Pipeline ADC
• Gain magnitude and gain matching (k1) • Offset of the X2 amplifier and the sample/hold (k2) • Comparator offset (k 3) • Summer magnitude and gain matching (k4) • Summer offset (k 5) Illustration: + -
±k2
±k3 Vi-1
bi Vref -
+ 2
+ ∑ +
±k5
+
+
∑
±k1
+ ∑ +
±k4
Vi=AiVi-1+VOSi-biAsiVref where
+1ifVi-1>±k3=±VOCi bi = -1ifV <±k =±V i-1 3 OCi
Ai = all gain related errors of the ith stage VOSi = system offset errors of the ith stage VOCi = the comparator offset of the ith stage Asi = the gain of the summing junction of the ith stage
+
∑
Vi
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-12
Generalization of the First-Order Errors Extending the ith stage first-order errors to N stages gives:
∆A 1 2N( ∆A/A) < 1 ⇒ N=10 ⇒ A < 1000 Illustration of gain errors Vi Vref
2∆A A 2∆A 1A 1+
1 bi+1 =+1 -1
0
1
bi+1 =-1
bi =-1
-1
bi =+1
Vi-1 Vref
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-14
Identification of Errors - Cont'd 2. System Offset Errors Vref VOS< N 2 For N=10 and Vref = 1V, VOS < 1mV
Illustration of system offset error Vi Vref 1+VOS
1
1+VOS bi+1 =+1 -1
0
1
bi+1 =-1
bi =-1
-1
bi =+1
Vi-1 Vref
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-15
Identification of Errors - Cont'd 3. Summing Gain Error
∆A s
1 < A s 2N
1 ∆A For N=10, A < 1024 Vi Vref 1+∆As /As 1-∆As /A /As
-1
-0.5
0.5
1
Vi-1 Vref
-1+∆As /A /As -1-∆As /As
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-16
Identification of Errors - Cont'd 4. Comparator Offset Error The comparator offset error is any nonzero value of the input to a stage where the stage bit is caused to change. It can be expressed as: Vi = 2Vi-1 - biVref where +1ifVi-1>VOCi bi = -1ifV <V i-1 OCi
Illustration of comparator offset error: Vi Vref
bi+1 =+1 -1-1
-0.5
0.5
bi+1 =-1
bi =-1
bi =+1 VOC = ?
1
Vi-1 Vref
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-17
SUMMARY
1.) The 1-bit/p 1-bit/pipe, ipe, pipel pipeline ine conver converter ter which uses standard standard components including including a sample and hold, an amplifier, and a comparator would be capable of realizing at most an 8 or 9 bit converter. 2.) The accur accuracy acy of the the gains and offset offset of the first first stage stage of an N-Bit converter converter must be within 0.5LSB. 3.) The accuracy accuracy of the the gains gains and offset of a stage diminishes with the remaining remaining number of stages to the output of the converter. 4.) Error correction correction and self-calibr self-calibrating ating techniques techniques are necessary in order to realize the potential resolution capability of the 1-bit/'stage pipeline ADC.
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-18
Cyclic Algorithmic A/D Converter The output of the ith stage of a pipeline A/D converter is Voi = (2Vo,i-1 - biVREF )z-1 If Voi is stored and feedback to the input, the same stage can be used for the conversion. The configuration is as follows: Comparator Voi
X2
+1
Sample and hold
∑
+Vref
+1
-Vref
Practical implementation: Comparator Va
X2
+Vref Sample and hold
Vb S1 Vin
+1
∑
-1
+ -
Vo Vo = "1" +Vref Vo = "0"
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-19
Algorithmic ADC - Example Assume that Vin* = 0.8VREF. The conversion proceeds as; 1.) 0.8 0.8VREF is sampled and applied to the X2 amplifier by S1. 2.) Va(0) is 1.6VREF (b1=1) which causes -V REF to be subtracted from Va(0) giving Vb(0) = 0.6VREF 3.) In the the next next cycl cycle, e, Va(1) is 1.2VREF (b2=1) and Vb(1) is 0.2VREF. 4.) The next next cycl cyclee gives gives Va(2) = 0.4VREF (b3=0) and Vb(2) is 0.4VREF. 5.) The next next cycl cyclee gives gives Va(3) = 0.8VREF (b4=0) and Vb(3) is 0.8VREF. 6.) 6.) Fina Finall lly, y, Va(4) = 1.6VREF (b5=1) and Vb(4) = 0.6VREF.
∴ The digital word is 11001. ⇒ Vanalog = 0.78125VREF. Va /V /VREF
Vb /VREF
2.0
2.0
1.6
1.6
1.2
1.2
0.8
0.8 0.6 0.4 0.2
0.4 0
0
1
2
3
4
5
t T
1
2
3
4
5
t T
Allen and Holberg - CMOS Analog Circuit Design Algorithmic A/D Converters-Practical Results
• Only one accurate gain-of-two amplifier required. • Small area requirements • Slow conversion time - nT. • Errors: Finite op amp gain, input offset voltage, charge injection, capacitance voltage dependence.
Practical Converter 12 Bits Differential linearity of 0.019% (0.8LSB) Integral linearity of 0.034% (1.5LSB) Sample rate of 4KHz.
Main ADC is an N-bit charge scaling array. Sub DAC is an M-bit voltage scaling array. Calibration DAC is an M+2 bit voltage scaling array. This is an voltage-sc voltage-scaling, aling, charge-scal charge-scaling ing A/D converter converter with with (N+M)(N+M)- bits resolution. resolution.
Allen and Holberg - CMOS Analog Circuit Design
Page X.8-22
Self-Calibration Procedure During calibration cycles, the nonlinearity factors caused by capacitor mismatching are calibrated and stored in the data register for use in the following normal conversion cycles. The calibration procedure begins from MSB by connecting C N to VREF and the remaining capacitors C NX to GND, then exchange the voltage connection as follows: VX
CN
VX
CNX
CN
VREF
CNX
VREF
where C NX = C1B + C1A + ... + CN-1 The final voltage VX after exchanging the voltage connections is CNX-CN VX = VREF C +C NX N If the capacitor ratio is accurate and C NX = CN ⇒ VX = 0, otherwise VX ≠ 0. This residual voltage VX is digitized by the calibration DAC. Other less significant bits are calibrated in the same manner. After all bits are calibrated, the normal successive-approximation conversion cycles occurs. The calibrated data stored in the data register is converted to an analog signal by calibration DAC and is fed to the main DAC by CCAL to compensate the capacitor mismatching error.
Allen and Holberg - CMOS Analog Circuit Design Self-Calibrating ADC Performance Supply voltage ± 5V Resolution of 16 bits Linearity of 16 bits Offset less than 0.25 LSB Conversion time for 0.5 LSB linearity: 12 µs for 12 Bits 80 µs for 16 Bits. RMS noise of 40 µV. Power dissipation of 20 mW (excludes logic) Area of 7.5 mm (excludes logic).
Page X.8-23
Allen and Holberg - CMOS Analog Circuit Design
X.9 - HIGH SPEED ADC's Conversion Time ≈ T (T = clock period)
• Flash or parallel • Time interleaving • Pipeline - Multiple Bits • Pipeline - Single Bit
Page X.9-1
Allen and Holberg - CMOS Analog Circuit Design
Page X.9-2
FLASH A/D CONVERTER VREF
* = 0.7 Vin 0.7 VREF
R 7 VREF 8
+ R
6 VREF 8
+ +
R
4 VREF 8
2 VREF 8
+ + R
0
+
0
+
R
0
-
R 1 VREF 8
0
-
R 3 VREF 8
1
-
R 5 VREF 8
1
-
• Fast conversion time, one clock cycle • Requires 2N-1 comparators • Maximum practical bits is 6 or less • 6 bits at 10 MHz is practical
0
Digital decoding network
Output digital word 101
Allen and Holberg - CMOS Analog Circuit Design
Page X.9-3
Time-Interleaved A/D Converter Array Use medium speed, high bit converters in parallel. T1 S/H
• Compromise between speed and area • 8-bit, 1M Hz. Gain = 2M +
* Vin
∑
* Vin
Vref
Vref +
+
-
-
+
+
-
-
+ -
Digital decoding network
+ -
+
+
-
-
Digital decoding network
D/A Converter
2M - 1 equal resistors and comparators
M MSB's
2M - 1 equal resistors and comparators
M LSB's
Allen and Holberg - CMOS Analog Circuit Design
Page X.9-6
Conversion of Digital back to Analog for Pipeline Architectures Use XOR gates to connect to the appropriate point in the resistor divider resulting in the analog output corresponding to the digital output.
Analog Out
Vref
* Vin
1
+ -
0 1
+ -
1
+ -
0 0
+
0
0
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-1
X.10 - OVERSAMPED ( ∆-∑) A/D CONVERTER NYQUIST VERSUS OVERSAMPLED A/D CONVERTERS Oversampling A/D converters use a sampling clock frequency(f S) much higher than the Nyquist rate(fN). Conventional Nyquist ADC Block Diagram: Digital Processor
The anti-aliasing filter at the input stage limits the bandwidth of the input signal and prevents the possible aliasing of the following sampling step. The modulator pushes the quantization noise to the higher frequency and leaves only a small fraction of noise energy in the signal band. A digital low pass filter cuts off the high frequency quantization noise. Therefore, the signal to noise ratio is increased.
y(kTN)
y(kTN)
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-2
ANTI-ALIASING FILTER The anti-aliasing filter of an oversampling ADC requires less effort than that of a conventional ADC. The frequency response of the anti-aliasing filter for the conventional ADC is sharper than the oversampling ADC. Conventional ADC's Anti-Aliasing Filter f B
f N/2
f
fS=f N
Oversampling Oversampling ADC's Anti-Aliasing Filter f B
f N/2
fN
f S/2
fS
f
f B : Sign Signaal Band Bandwi widt dthh f N : Nyqu Nyquis istt Freq Freque uenc ncy, y, f N = 2f B f S : Samp Sampli ling ng Freq Freque uenc ncyy and and usua usuall llyy f S >> f N f S M : Oversampling ratio, M = f N So the analog anti-aliasing filter of an oversampling ADC is less expensive than the conventional ADC. If M is sufficiently large, the analog anti-aliasing filter is simply an RC filter.
Allen and Holberg - CMOS Analog Circuit Design
Conventional ADC's Quantization
Page X.10-3
QUANTIZATION
The resolution of conventional ADCs is determined by the relative accuracy of their analog components. For a higher resolution, self-calibration technique can be adopted to enhance the matching accuracy. Multilevel Quantizer: output (y) 5 3
ideal curve -6
-4
-2
1 -1
2
-3
4
6
input (x)
y=Gx+e
-5
e 1
x -1
where,
The quantized signal y can be represented by y = Gx + e G = gain of ADC, normally = 1 e = quantization error
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-4
Conventional ADC's Quantization - Cont'd The mean square value of quantization error, e, is ∆ /2 2 1 ⌠ 2 ⌡e(x) dx = ∆12 e2rms = ∆ ⌠ -∆ /2 where
VREF ) 2N When a quantized signal is sampled at f S (= 1/ τ), all of its noise power folds into the frequency band from 0 to f S /2. If the noise power is white, then the spectral density of the
∆ = the quantization level of an ADC (typically
sampled noise is
where
2 E(f) = e rms f S
1/2
= erms 2τ
τ = 1/f S and f S = sampling frequency The inband noise energy no is f B 2 e 2f 2 ⌡ rm s ⌠E 2(f)df = e 2 (2f τ) = e2 B = rms no = ⌠ rms B rms f S M 0 erms no = M f S The oversampling ratio M = 2f B Therefore, each doubling of the sampling frequency decreases the in-band noise energy by 3 dB, and increases the resolution by 0.5 bit. This is not a very efficient method of reducing the inband noise.
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-5
OVERSAMPLING ADC f S
analog f B input
∑∆ MODULATOR
f D
DECIMATOR
LOW-PASS
2 f B
FILTER
digital PCM
Oversampling ADCs consist of a ∑∆ modulator, a decimator (down-sampler), and a digital low pass filter.
∑∆ modulator Also called the noise shaper because it can shape the quantization noise and push majority of the noise to high frequency band. It modulates the analog input signal to a simple digital code, normally is one bit, using a sampling rate much higher the Nyquist rate. Decimator Also called the down-sampler because it down samples the high frequency modulator output into a low frequency output. Low-pass filter Use digital low pass filter to cut off the high frequency quantization noise and preserve the input signal.
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-6
Sigma-Delta (∑∆) Modulator
First Order ∑∆ Modulator The open loop quantizer in a conventional ADC can be modified by adding a closed loop to become a ∑∆modulator. f S
x(t)
+
+
-
Integrator
yi
A/D
D/A Modulator Output
input signal modulator output
) V ( e d u t i l p m A
0
0.5 Time (ms)
1
Allen and Holberg - CMOS Analog Circuit Design First-Order ∑∆ Modulator + gn xn -
wn+1
Delay
Page X.10-7
wn
yn en Quantizer
Accumulator yn = wn + en (1)
wn+1 = gn + wn = xn - yn + wn = xn -(wn + en) + wn = xn - en (2) Therefore, wn = xn-1 - en-1, which when substituted into (1) gives yn = xn-1 + ( en-en-1) The output of ∑∆ modulator yn is the input signal delayed by one clock cycle x n-1, plus the quantization noise difference en - en-1. The modulation noise spectrum density of en - en-1 is
ωτ ωτ N(f) N(f) = E(f) E(f) 1-z 1-z-1 = E(f) E(f) 1- 1-ee-jωτ = 2E(f) sin 2 = 2e rms 2τ sin 2 Plot of Noise Spectrum 2 1.5 ) f ( E / ) f ( N
1
d n a b e s a b l a n g i s
N(f)
E(f)
0.5
0 0
f B
Frequency
f S 2
Allen and Holberg - CMOS Analog Circuit Design First Order ∑∆ Modulator-Cont’d The noise power in the signal band is f B
ωτ 2πf πf where sin 2 = sin 2f = sin f ≈ πf τ S S if f S >> f f B
2 2 e π (2τf B)3 2 2 rms 2 ⌠ ⌠ ⌡ no ≈ (2τ)3π2 erms rm s f df = 3 0 where , f S >> f B no = erms
π 3/2 π -3/2 2f = e M τ rms B 3 3
Each doubling of the oversampling ratio reduces the modulation noise by 9 dB and increase the resolution by 1.5 bits.
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-9
Oversampling Ratio Required for a First-Order ∆ Σ Modulator A block diagram for a first-order, sigma-delta modulator is shown in the z-domain. Find the magnitude of the output spectral noise with V IN(z) = 0 and determine the bandwidth of a 10-bit analog-to-digital ∆ = rms value of converter if the sampling frequency, f S, 12 quantization is 10 MHz. noise + Vin (z) + Vout(z) Solution + 1 1 z-1 Vout(z) = e rms + z-1 [Vin(z) Vout(z)] or z-1 Vout(z) = z erms if Vin(z) = 0 → Vout(z) = (1-z-1)erms
Σ
ωτ |N(f)| = E(f) 1-e-jωτ = 2E(f) sin 2 = 2 The noise power is found as f B
ωτ 2 e sin f S rms 2
f B
⌠ 2 2 ⌠ ⌠ ⌡ no(f) = |N(f)| df = 2 ⌡ 0 0 2πf τ Let sin 2 ≈ πf τ if f S >> f B. Therefore,
3/2 VREF f B 8 no(f) = 3 π·erms f ≤ 10 2 S Solving for f B /f S gives (using ∆ in erms term is equal to VREF) f B 12 3 1 2/3 = [0.659x10-3]2/3 = 0.007576 f S = 8π 210 f B = 0.007576·10MHz = 75.76kHz.
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-10
Decimator (down-sampling) The one-bit output from the ∑∆ modulator is at very high frequency, so we need a decimator (or down sampler) to reduce the frequency before going to the digital filter. f S
analog f B input
∑∆ MODULATOR
f D
DECIMATOR Removes the modulation noise
from modulator xn
LOW-PASS
2 f B
FILTER
digital PCM
Removes the out-of-band components of the signal to low-pass filter yn
+ REGISTER
f S f S 1 N yn = N xn , where N = f = down-sampling ratio D N=0 The transfer function of decimator is N-1 Y(z) 1 1 1-z-N -i H(z) = X(z) = N z = N 1-z-1 i=0 sinc(πfNτ) H(e jωτ) = sinc(πf τ)
∑
∑
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-11
Frequency Spectrum of the Decimator sinc(πfNτ) H(e jωτ) = sinc(πf τ) 10 0
) B d ( e d u t i n g a M
Quantization Noise Signal Bandwidth
-10 -20 -30 -40 -50
f D
Frequency
f S 2
f D = intermediate decimation frequency When the modulation noise is sampled at f D, its components in the vicinity of f D and the harmonics of f D fold into the signal band. Therefore, the zeros of the decimation filter must be placed at these frequencies.
Allen and Holberg - CMOS Analog Circuit Design Digital Lowpass Filter
analog f B input
f S
∑∆ MODULATOR
f D
DECIMATOR
FIR or IIR digital low pass filter 10
-20 ) B d ( e d -50 u t i n g a M
-80
-110
4000
Page X.10-12
Frequency (Hz)
LOW-PASS
2 f B
FILTER
digital PCM
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-13
After Digital Low Pass Filtering 0 signal ) -50 B d ( e d u t i n -150 g a M
-100
0
quantization noise
1000
Fre uenc (Hz
Bit resolution From the frequency response of above diagram, the signal-to-noise ratio (SNR) signal SNR = 10log 10 f (dB) B noise(f) f=0
∑
and
Bit resolution (B) ≈
SNR(db) 6dB
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-14
System block in time domain and frequency domain
l a t i M g C 2 i d P B f
y c n e u q e r F
S S R A E P - T W L I O F L D f
R O T A M I C E D S f
∆ ∑
R O T A L U D O M
B f g t o u l a p n n a i
e m i T
e m i T
y c n e u q e r F
y c n e u q e r F
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-15
Second-Order ∑∆ Modulator Second order ∑∆ modulator can be implemented by cascading two first order ∑∆ modulators. INTEGRATOR 2 INTEGRATOR 1 xn DELAY A/D + ∑ + ∑ + ∑ + ∑ + + DELAY D/A
yn = xn-1 + (en - 2en-1 + en-2)
QUANTIZER
The output of a second order ∑∆ modualtor yn is the input signal delayed by one clock cycle xn-1, plus the quantization noise difference en - 2en-1 + en-2. The modulation noise spectrum density of e n - 2en-1 + en-2 is ωτ 2 2 N(f) N(f) = E(f) E(f) 1-z 1-z-1 = E(f) E(f) 1- 1-ee-jωτ = 4E(f) sin 2 2 Noise Spectrum 4 d n a b e s a b l a n g i s
3 ) f ( 2 E / ) f ( N
2nd order N(f) first first order order N(f) N(f) E(f)
1
0
0
f B
Frequency
f S 2
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-16
Second-Order ∑∆ Modulator- Cond’d The noise power in the signal band is ∆2 π2 -5/2 ∆ π π2 -5/2 no = erms M = = ( M) -5/2 , f s >> f o 12 5 M 5 2 15 Each doubling of the oversampling ratio reduces the modulation noise by 15 dB and increase the resolution by 2.5 bits. Higher-Order Σ − ∆ Modulators Let L = the number of loops. The spectral density of the modulation can be written as ωτ L | NL(f)| = erms 2τ 2sin 2 The rms noise in the signal band is given approximately by πL no ≈ erms (2f Bτ) L+0.5 2L+1 This noise falls 3(2L+1) dB for every doubling of the sampling rate providing L+0.5 extra bits. Decimation Filter
sinc(πfNτ)L+1 A filter function of is close to being optimum for decimating the sinc(πf τ) signal from an Lth-order ∆−Σ modulator. Stability
For orders greater than 2, the loop can become unstable. Loop configuration must be used that provide stability for order greater than two.
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-17
The modulation noise spectral density of a second-order, 1-bit ∆ Σ modulator is given as |N(f)| =
4∆ 12
ωt 2 2 sin fs 4
where ∆ is the signal level out of the 1-bit quantizer and f s = (1/ τ) = the sampling frequency and is 10MHz. Find the signal bandwidth, bandwidth, fB, f B, in Hz if the modulator is to be used in an 18 bit oversampled ADC. Be sure to state any assumption you use in working this problem.
Allen and Holberg - CMOS Analog Circuit Design
Page X.10-18
Circuit Implementation of A Second Order ∑∆ Modulator
S1
S2 C1
C2
S3 S4
IN
- +
S1
S2 C1
S3 S4
+ S1
C1 S2
S4 S3
C2 - + + -
S1 C2
+ VREF VREF
C1 S2
OUT
S4 S3
C2 VREF + VREF
Fully differential, switched-capacitor switched-capacitor integrators can reduce charge injection effect. Circuit Tolerance of a Second Order ∑∆ Modulator 1. 20% variation of C1/C2 has only a minor impact on performance. 2. The Op Amp gain should be comparable to the oversampling ratio. 3. The unity-gain bandwidth of Op Amp should be at least an order of magnitude greater than the sampling rate.
Allen and Holberg - CMOS Analog Circuit Design SOURCES OF ERRORS IN Σ ∆ A/D CONVERTERS 1.
Quantization in time and ampli plitude Jitter and hysteresis
Comparison of the Various Examples Discussed Type of Converter Flash Two-Step Flash
No. of No. of Dependent ResoluCycles/ Compar on Passive tion Conver- ators Components sion 1 2N-1 Yes Low 2
1 after initial delay Oversampl64 ing Pipeline
Speed INL/DNL (LSB's) High
N/A
5 M s/ s
±3/ ±0.6
31
Yes
10 bits
3
Yes
13 bits 250ks/s ±1.5/ ±0.5
3
Yes
16 bits
24kHz
9 1 dB
Area
Power (mW)
Largest Largest 54k mils2 3600 mils2
350
75.3k mils2
110
15
Allen and Holberg - CMOS Analog Circuit Design
Page X.11-1
X.11 -FUNDAMENTAL LIMITS OF SAMPLING A/D CONVERTERS
kT/C Noise Assume that the ON resistance of a switch is R and the sampling capacitor is C and that the time to charge the capacitor fully is 1 T = f ≈ 10RC c
( 1)
V ref re f Set the value of the LSB = N equal to kT/C noise of the switch, 2
Vref = 2N
kT C
(2)
Solve for C of (1) and substitute into (2) to get Vref 2 = 10kTRf c ⇒ 2N
2N f c =
Vref 10kRT
(3)
Taking the log of both sides of (3) gives N = -1.67 log(f c) + 3.3 log(V ref ) - 1.67 log(10kRT) or N=32.2+3.33log(V ref ) -1.67log(Rf c ) re f )-1.67log(Rf (At room temperature) kT/C Noise Comparison of high-performance, monolithic A/D converters in terms of resolution versus sampling frequency with fundamental limits due to kT/C noise superimposed.
Allen and Holberg - CMOS Analog Circuit Design
Page X.11-2
Fundamental Limits of Sampling A/D Converters - Continued Maximum Sample Rate Assume that the maximum sample rate is determined by the time required for the amplifiers and/or sample-hold circuits to settle with the desired accuracy for high resolution. Further Furt her assume that the dynamics of these circuits can be modeled by a second-order system with a transfer function of ω n2 A(s) A(0) = s 2 +2 ζ ω n s+ ω n 2 If ω n ≈ GB of the circuit and if the system is underdamped, then the step response is given as e-ζGBt vo(t) 2 A(0) = 1 - 1-ζ2 sin 1 - ζ GB·t+ φ
This response looks like the following, 2
1.5 +ε 1 -ε 0.5 0
0
Settling Time 4
8
12
16
20
ωn t If we define the error ( ±ε) in v o settling to A(0) as the multiplier of the sinusoid, then an expression for the settling time can be derived as e-ζGBt 1 1 2πζGB ts = 2πζGB ln =t = ⇒ f sample s ample 1 s 1- ζ 2 ln ε 1-ζ2
For reasonable values of ζ, f sample sample can be approximated as πGB G B f sample s ample ≈ 10 = 3
Allen and Holberg - CMOS Analog Circuit Design
Page X.11-3
Aperature Uncertainty (Jitter) A problem in all clocked or sampled A/D converters. vin Clock
Analog In
Analog-todigital converter
∆V
Digital Out
∆T
dvin ∆V = slope x ∆T = dt ∆ T
Vref /2N ∆T = Aperature uncertainty = dV = dv /dt in in dt Assume that vin(t) = Vp sin ωt
∆V
dvin dt = ωV p max
Vref Vref 1 1 ∆ T = 2 N x ω V ≈ 2 Nω V = 2 N ω p ref Therefore, ∆ T =
X.12 - SUMMARY OF A/D CONVERTERS Typical Performance Characteristics
A/D Architecture
Typical Performance Characteristics
Serial
1-100 conversions/sec., 12-14 bit accuracy, requires no element-matching, a stable voltage reference is necessary
Successive Approximation 1 f c ≈ NT
10,000-100,000 conversions/sec., 8-10 bits of untrimmed or uncalibrated accuracy, 12-14 bits of trimmed or calibrated accuracy
1 N f c = 2 T
High Speed 1 T < f < NT c
1 to 40 megaconversions/sec., 7-9 bits of accuracy, 10-12 bits of accuracy with error correction and other techniques
Oversampling
8,000-600,000 conversions/sec., 12-16 bits accuracy, requires linear integrators but no precision passive components, minimizes noise and offsets
1 f c << T
Conclusions •
Thee best Th best A/D A/D con conve vert rter er dep depen ends ds upo uponn the the appl applic icat atio ionn
•
Both Both resolu resolutio tionn and and speed speed are ulti ultimate mately ly limit limited ed by by the the accura accuracy cy of of the process
•
High resolut resolution ion A/D's A/D's will will be more oriented oriented toward toward "sign "signal al averagi averaging" ng" type converters, particularly with shorter channel lengths
