DFT Interview Questions

DFT Interview Questions(100 most commonly asked DFT Interview Questions ): Scan Insertion: 1).E!lain scan insertion ste!s" #).w$at are t$e %asic t$in&s t$at needs to taken care 'or Scan Insertion" ).w$at are t$e D* +iolations t$at u $ave 'aced durin& Scan Insertion and $ow did you 'i t$ose " ,).w$at is test !oint Insertion" *an you tell and e!lain one Test-oint Insertion scenario" ).Some Questions on desi&n com!leity like w$at was t$e &ate and 'lo!s count o' yours recent !ro/ect" ).E!lain Decom!ression lo&ic" ).w$at is sdc 'ile and w$at does it contains" 2).w$at is t$e use o' clock &aters in desi&n" 3).Draw t$e internal dia&ram o' clock &atin& cell" 10).w$at is use o' latc$ in clock &atin& cell" 11).4ow &litc$es can %e remove t$rou&$ latc$" 1#).Draw t$e mued 'li! 'lo! and e!lain" 1).Take t$ree scan 'lo! and stitc$ it and e!lain t$e scan o!eration" 1,).4ow you will decide t$e num%er o' scan c$ains 'or your core" 1).w$at is locku! latc$ and w$y we use it" 1).w$at are 5anu'actured de'ects" 1).w$at is clock latency" 12).will latency e''ect data s$i'tin& in scan c$ain" 13).consider two 'lo! o' .#sec and 0. sec latency $ow do you connect t$e 'lo!s in scan c$ain" #0).write t$e T6 codin& 'or an async$ronous and a sync$ronous Fli!7'lo!" #1).Im!lement a # %y 1 5u t$rou&$ &ates" ##).4ow you will decide t$e com!ression ratio 'or t$e core" #).w$at all in'ormation you will ask 'rom desi&ner 'or smoot$ scan insertion" #,).w$at all ctls you read w$ile scan insertion" #).Draw and e!lain t$e Structure o' t$e com!ressor and decom!ressor circuit" #).w$y we don8t &o 'or $i&$er com!ression ratio like 3071009" #).4ow many scan clocks you $ad 'or your core" #2).w$ic$ one is %etter $avin& sin&le or multi!le scan clock" #3).w$at all t$in&s you need to take care w$ile%e'ore insertin& on c$i! clock controller circuit" 0).In w$ic$ !at$ we insert t$e lockku! latc$; data or clock !at$" 1).4ow you will resolve t$e com%inational 'eed%ack loo! issue in desi&n i' !resent" #).w$y we don8t connect t$e ca!ture 'lo!8s clock to t$e locku! latc$" ).w$y we use 'lo! trays in desi&n" ,).w$at is t$e !ur!ose o' DFT" ).w$y we need scan" or w$y we convert normal D 'li! 'lo!s to scan 'lo!s in desi&n" ).w$at work around you can do i' you don8t $ave scan e
 =T->:  =T ->: ).Did you worked on *overa&e =nalysis" 4ow did you im!roved your *overa&e" 2).w$at are t$e =T-> ?ntesta%le 'aults" 3).4ow muc$ test covera&e you &ot in your last !ro/ect" ,0).w$at are t$e in!ut 'iles re and w$at all out!ut 'iles we &et a'ter com!letin& scan insertion and =T->" ,1).w$at is Stuck at 'ault" ,#).4ow many 'aults sites are t$ere 'or a # in!ut =@D >ate" ,).w$at is t$e di''erence %etween transition and !at$ delay 'ault model" ,,).w$at t$e S-Ftest !rocedure 'ile contains" ,).w$at are t$e di''erent ty!es o' 'ault classes" ,).w$at is 'ault colla!sin& colla!sin&" " ,).For a &iven 'ault covera&e t$e num%er o' !atterns 'or TFT is more t$an t$e !atterns &enerated 'or Stuck7at7'aults. Stuck7at7'au lts. A$y A $y so" ,2).4ow t$e # !ulses are &enerated 'or transition 'aults"

,3).can you draw t$e on c$i! clock controller structure dia&ram" 0).w$at all D*s you 'aced durin& =T->" 1).w$at is t$e di''erence %etween launc$ on ca!ture(6B*) and launc$ on s$i't(6BS)" #).w$ic$ one is widely used in industry" w$ic$ one is %etter 6BS or 6B*" ).4ow you will im!rove transition 'aults test covera&e" ,).w$y we do IDDQ testin&" ).w$at is !seudorandom !attern and w$y it called !seudorandom" ).4ave you ever seen condition statements in s!' and $ow t$ey work" ).I' we $ave cover all transition 'aults alon& a !at$(critical) already t$en s$ould we c$eck t$e !at$ delay also 'or t$at !at$" 2).w$at is t$e test covera&e and 'ault covera&e" 3).w$at is redundant 'ault e!lain wit$ eam!le" 0).w$at are !arallel !atterns $ow t$ey work e!lain wit$ t$e $el! o' a scan c$ain" 1).w$at are t$e D*s t$at can result in low test covera&e" #).w$at are %locked and unused 'aults" ).4ow t$e test data valume and tester time reduction $a!!ens wit$ com!ression" ,).w$at are advanta&es o' modular at!&" ).4ow DFT vectors are di''erent 'rom Functional vectors" ).w$y we measure -B(!rimary out!ut) %e'ore ca!ture clock" ).4ow t$e IDDQ test vectors is di''erent 'rom stuck at test vectors" 2).4ow increasin& se
Simulation: 3).4ow you will timin& simulation de%u&&in& 'or uncom!essed and com!ressed c$ains" 0).Su!!ose i' you &et $old violation $ow you 'i t$at" 1).4ave you ever o!ened sd' and seen" #).w$at is setu! and $old" ).w$at violation will occur i' ste! and $old time not maintain !ro!erly" ,).write t$e setu! slack e
5iscellaneous: 2).w$y we do 5CIST Insertion and veri'ication" A$ic$ tool you are usin&" 3).w$at is -100 $ow it works and use'ul" 20).4ow wra!!er cell works draw its structure" 21).4ow you do etest usin& -100 and tell w$at $a!!ens in its wra!!er cell" 2#).Do you know 5CIST and $ow it works" 2).w$at are ty!ical memory 'aults" 2,).w$at is nei&$%or$ood and cou!lin& 'aults $ow t$ese 'aults are di''erent 'rom eac$ ot$er" 2).w$ic$ tool did you use 'or 5CIST insertion" 2).w$at c$ecks(rules) ET c$ecker do" 2).Draw Coundary scan cell and e!lain its 'unctionality" 23).E!lain Sam!le and -reload o!eration" 30).w$at is T=>" w$y it is used" 4ow IB testin& $a!!ens wit$ T=>" 31).w$at are t$e manadatory instructions in T=>" 3#).w$at are t$e de'ault values o' T=> si&nals(tms;trstn;tdi;tdo;tck)" 3).For an I@B?T !ort $ow many %oundary scan cells you re" 3).w$ic$ instruction is $avin& 'i o!code in T=>" 3).w$at is t$e si&ni'icance o' 8!ause8 state o' T=- state mac$ine" 32).4ow t$e 8mode8 si&nal('or %oundary scan cell) &ets &enerated in T=>" 33).E!lain 201 microcontroller" 100).4ow many Timers and memory sie o' 201"