Dftadvisor Tutorial

Mentor Graphics Tools for DFT DFTAdvisor, FastScan and FlexTest

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DFT Tools

Saturday, October 22, 2005

DFT Advisor •Synthesis tool capable of doing DRC, Scan Insertion and Test point Synthesis •Creates a do file and and a test procedure file after scan insertion •Supports identification and insertion of full scan, partial scan, partition scan and test points • Supports mux mux scan, clocked scan or LSSD • Supports both manual and automatic scan identifications • Accepts most of the gatelevel netlist formats

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DFT Tools


DFT Advisor •Synthesis tool capable of doing DRC, Scan Insertion and Test point Synthesis •Creates a do file and and a test procedure file after scan insertion •Supports identification and insertion of full scan, partial scan, partition scan and test points • Supports mux mux scan, clocked scan or LSSD • Supports both manual and automatic scan identifications • Accepts most of the gatelevel netlist formats

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DFT Tools


DFT Advisor – what it does?

• Design flattening • Circuit Learning & Testability Analysis • DFT Rules Check ( DRC ) • Scan structure identification and insertion • Generate output files (dofile and testprocedure file)

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DFT Tools


DFT Advisor – output files It generates 3 files: •

A new netlist with scan cells inserted

•

do_file, which provides circuit setup and scan circuitry information, used by fastscan /flextest for Automatic Test Pattern Generation

•

test_procedure file, which contains cycle based procedures and timing definitions , used by fastscan/flextest, to operate the scan structures within a design

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DFT Advisor Flow

DFT Advisor : 2.

Setup

3.

DRC

4.

Test Structure Identification

5.

Test Structure Insertion

6.

Write Results

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DFT Advisor commands for Full scan SETUP > add clocks 0 /CK SETUP > set system mode dft DFT >

setup scan identification full_scan

DFT >

setup test_point identification –control 0 –observe 0 –noverbose

DFT >

run

DFT >

insert test logic –scan on –test_point on –ram on

DFT >

report statistics

DFT >

write netlist /project/mtech/../s27_fs.v –verilog

DFT >

write atpg setup /project/mtech/../s27_fs.v –

procfile

Note: Exit of SETUP mode triggers three major operations : 1. Flattening of design model, 2. Performing learning analysis on the flattned model and

Performing DFT rules check.

3. If the design passes DRC, the system enters into ATPG mode

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DFT Tools


Fastscan • Fastscan is the full scan ATPG tool • Offers high fault coverage and good run time • Supports testing of stuckat faults, iddq, transition faults • Automatically generates test patterns • Runs patterns for good & fault simulations • Generates test reports • Uses random patterns for fault simulation and stops when a pattern fails to detect atleast 0.5% of remaining faults • And then uses deterministic patterns to detect remaining faults which have a very low chance of detection by random patterns

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DFT Tools


Fast Scan Flow

2.

Setup

3.

DRC

4.

Configuration ( use defaults )

5.

Pattern Generation

6.

Fault Simulation

7.

Good Simulation

8.

Analysis of results

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Fastscan – full scan commands SETUP >

add clocks 0 /CK

SETUP >

add scan groups grp1 /project/mtech/../s27_fs.v.testproc

SETUP >

add scan chains chain1 grp1 /scan_in1 /scan_out1

SETUP >

set system mode atpg

ATPG >

add faults –all

ATPG >

run

ATPG >

report statistics

ATPG >

save patterns /project/mtech/../s27_fs.v.pattern

ATPG >

set system mode fault

FAULT >

set pattern source external /project/../s27_fs.v.pattern ascii

FAULT >

run

FAULT >

report statistics

FAULT >

set system mode good

GOOD >

set pattern source external /project/../s27_fs.v.pattern ascii

GOOD >

run

GOOD >

exitdiscard

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DFT Tools


Flextest •Flextest is a nonscan to full scan tool • It is most suited for testing designs with few or no inserted test structures • Supports partial scan and partition scans ( partial scan is extremely useful in situations where the design cannot accomodate any extra delay added to the critical path , due to added scan elements delay; those flip flops in the critical path can be excluded in the partial scan ) • Automatically generates test patterns • Runs patterns for good & fault simulations • Generates fault analysis reports

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•Flextest has capabilities for inserting test logic circuitry on uncontrollable pins like set, reset, tristateenable and RAM read/write controls •Flextest uses a proprietory sequential ATPG algorithm called BACK

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DFT Advisor – commands for partial scan Insertion

SETUP > add clocks 0 /CK SETUP > set system mode dft DFT >

setup scan identification sequential atpg –internal –percent 90 –controllability 100 –observability 100

min_detection 0.01 –backtrack 30 –

cycle 16 –time 100 DFT >

setup test_point identification –control 0 –observe 0 –noverbose

DFT >

run

DFT >

insert test logic –scan on –test_point on –ram on

DFT >

write netlist /project/mtech/../s27_ps.v –verilog

DFT >

write atpg setup /project/mtech/../s27_ps.v –procfile

DFT >

exit discard

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Flextest – commands for partial scan testing

SETUP > add clocks 0 /CK SETUP > add scan groups grp1 /project/mtech/../s27_ps.v.testproc SETUP > add scan chains grp1 /scan_in1 /scan_out1 SETUP > set test cycle 2 SETUP > add pin constraints /CK SR0 1 1 1 SETUP > set system mode drc DRC >

set system mode atpg

ATPG > set fault type stuck ATPG > add faults –all ATPG > run ATPG > save patterns /project/mtech/s27_ps.v.pattern –profile –ascii cell_placement bottom –parallel –begin 0 –all_test ATPG > report statistics ATPG > set system mode fault FAULT > set pattern source external

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/project/mtech/../s27_ps.v.pattern ascii

DFT Tools


Flextest – commands for partial scan testing – contd.

FAULT >

run

FAULT >

report statistics

FAULT >

set system mode good

GOOD > set pattern source external

/

project/mtech/../s27_ps.v.pattern ascii GOOD > run GOOD > exit discard

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Dftadvisor Tutorial

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