Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of ...
Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization. You begin with an e…Full description
Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization. You begin with an e…Full description
embedded design by frank vahid for btech and mtesh students of ece and cse
Descrição: Solution Manual for Digital Logics Classes
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Lista de Exercícios - Circuitos Digitais - Resolução - Frank VahidDescrição completa
Arte: Lápis e tinta de Frank MillherDescrição completa
Politeknik Seberang PeraiFull description
questions
degital
questions
The digital logic design is a system in electrical and computer engineering that uses simple numerical values to produce input and output operations. As a digital design engineer, you may assist in developing cell phones, computers, and related perso
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Cheat Sheet by Frank kernFull description
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Digital Design
Preface To IIIv!alllily. Alii.". Eric. Kelsi, alld Mom: IlIId ' 0 ' hose ellgill eers II'ho applv ,hel l' sk ills 10 bll ild 'hillgs ,hll' illlp''O I'e 'h e 1111111011 colldll lOlI .
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TO STUDENTS ABOUT TO STUDY DIGITAL DESIGN Dig ilal ci rc u.its . ~hich form th e basis of general-purpose computers as well as peciaJ purpose devl~es h.k~ cell phones or video game consoles. are dramatically changing the worl d . S lUdymg d igItal design not only gives you the confidence Ihal comes" ith fundame ntall y unders tand ing how d igital circ uits work. but also introduce!' you 10 an e:tcitiof! a nd usefu l possible career direction. This statement appl ies regardless of "-hether )ou'; maj or is Electrica l Engineering. Computer Enginee ring. or even Computer Science (in fac!. the need for digita l designers with strong computer science skills continues to increase). J hope you find (hi subjeci to be as ime restin e:. excitin2. and useful as J do. Throughout lhi s book. J have tried not only to in~uce con~ep{S in the rna I inruilive and easy to learn manner. but I have al 0 tried (Q sho\\ ho" those concepb can be a ppli ed to real-world systems. such as pacemakers. ul trasound machine . pnmers. automobil es. and cell phones. Young and capable engineering ludems (including computer science students ) Some limes lea\ their major. clai ming the) " 'ant a job that is more: "peopl e oriented." Ye t we need those people-oriented rudenlS more than e\cr. 35 engineering j obs are increas ingly people-oriented. in scveraJ wa) s. First. engineers ~uaJI~ wo rk in ,ighTly-imegraled groups involving numerous other engineers (rather than "silting a lo ne in front of a compu le r all day" as many studen ts belic\'e). econd. engineers often wo rk direCily lI'ilh CUSTomers ( uch as busine people. doctors. la\\ ) ers. go\ cmment officials. etc.). a nd mu st therefore be able 10 connect with those non-engineer ClJ.)(Qmero. Th ird . a nd in my opinion mosl importantly. ellgineers build 'lrings tlral dramatically impo('l people's /in's. teedcd are engineers \\ ho combine the.ir e nthlbiasm. C'T'eati\i £) . a nd innm'alion wi th Iheir olid engineering skills to con ehe and buiJd ne" product., thai il11prme people's quality o f life.
I have included " Designer Profiles" at the e nd of most chaplen.. The de"lgnef't.. \\ hose experi ence le \els \ 'M) from j ust a ~ ear to . e\ eral dec:lde .. , and \\ho. l.'"Omparu mnge fm m 5111alli0 huge . , hare \\ ith ~ ou their e\perience~. in .. ighb. and ad\ Il.':e. h'IU \\i ll notice hO\\ co mmon I) the) disc uss the people aspects of wetr Job~. You m3~ 3ho notice thei r cOIhu li; ias m a nd p:bs iQn for their job .
TO INSTRUCTORS OF DIGITAL DESIGN TIlis book. brea k!o from the 19 (hJ19 Os. digiml d(!, ign \It:" empha:.llm~ 'Iu-hmlted dc\ igll, lI1 :--tc3d cmph 3!
iii
Preface
Preface
to a beller app rec iati on of modem computers 3nd other digi tal devices. but n more 3CCUr~HC unders tandin g of careers involving digi t31desig n. Such an accurate und crst:'lIlding is cri ti cal to atlr3C( co mputing majors 10 C3rcers involvi ng some 3mOUJl( of digital design. and to cre~lI e 3 ci.ldre of engineers wi th the comfort in both ··softw3re" and " h3rdware" nccessary in mode m embedded comput ing system design. The dis tinguishing of basic desig n fro m optimiznrion should not be interpreted as avo iding a bOllom-up 3pproac h or glossing over import,lIlt steps - th e book takes a concrcte bOllom-up 3pproac h, starting from transistors. and building incrementall y up through gates. flip -fl ops. registers. controllers. datapath components. etc. Rather, the disting uis hing enables th e stu de nt to initiall y develop a solid understanding of basic design. before considerin g the morc advan ced topic of optimizati on, akin to how a phys ics book introd uces Newton's Ja ws of Illotion initiall y ass uming fri cti onless surfaces and no wind rcsislJ.nce. Furthermore. optimi zation IOday invo lves more than j ust size minimi zati on. ins tead requiring a broader understanding of tradeoffs among size, perform ance. and power. and eve n of tradeoffs among custom digi tal ci rcuits and microprocessor soft ware. Aga in , coverage is kept conc rete and appropriate to an int rod uctory digital desig n course. Nevertheless. the book distinguishes basic design from optimiza tion in a way that cleanly provides an ins tructor max imum Hexibility to introduce optimi za ti on at the tim es and to the ex tent desi red by th e instructor. In pani cular. the optimiza ti on chapter's subsections (Chapter 6) eac h correspond directly to one earlier chapter. such that Secti on 6.2 can direct ly follow Cha pte r 2. Secti on 6.3 can fo llow Chapter 3. 6.4 can follow 4. and 6.5 can follow 5. Several additional features of the boo k include:
HDL cOl'erage flexibility. The book's organization cleanly allows instructors to cove r HDLs (hardware descri ption languages) intennixed with the introduction of desig n concepts. to cove r HDLs later. or 10 not cover HDLs at all. The HDL chapter's subsecti ons (Chapter 9) each correspond to an earlier chapter. sucb that Sec tion 9.2 can directly fo llow Chapter 2. 9.3 can follow 3. 9.4 can follow J , and 9.5 can follow 5. Funhennore. rather than the book choosing jUst one of the popular languages - VHD L. Veri log. and the relatively new SystemC - the book provides equ al coverage of all three of those HDLs. And we use our extensive ex perience in synthesis with commercial tools to create HDL descnptions well -s uited for synthesis. in addi ti on to being suitable for imulation. Accompanying HDL-introdlictiOIl books. InstruclOrs wishing to co\er HDLs to an
eve n greater extent can utili ze one of our HDL-introduclion books specifically designed to accompany this tex tbook. wriuen by the same author as this textbook. Our HDL-introducrion books follow the same chapter tructure as. and use examples from. this tex tbook. eliminating the common situation of students struggling to correlate their distinct. and sometimes contradicting. HDL book ilIld digital desig n book subjects. Our HD L-intmduction books discuss language. simulanon. and testing concepts in more depth. providing numerous HDL e."tamples. and are al 0 designed to be usable by themselves for HDL learrung or ,..,fereoc<:. The books emphasize use of the language for real design. clearl) distio_uishing HDL use for symhesis fro m HDL use for testing. and include e."tlensive examples and fi gures throughout to ill ustrate conceplS. Our HDL-introductioD ~ come "",ith complete Powe rPoi nt slides th at use graphic and animations lO sene as an ea:Syto- use tutori al on the HDL.
Extensil'e lise of applied examples alldfigures. Afte r desc ribing a new conce pt and providing basic examples. Ihe book provides exampl es th at ap pl y the co nce pt 10 appl icati ons recog ni zab le to a student. like a seal belt unfas tened warnin g sys tcm. a computerized checke rboard ga me. a color printer, or a di gital video camera. Furulermore. the end of mOst chapters include a product profi le. intend ed to give students an eve n broader view of the applicability of the concepts. and to introduce clever appl icati on-speci fi c conce pts the students may find ve ry interestinglike the idea of beamfoml ing in an ultrasound machine or of fi ltering in a cellular phone. The book exte nsive ly uses fig ures 10 illustrate conce pts. contai nin g over 600 figures.
Allthor-created graphical animated Pou'uPo;nt slides. A rich set of Po,,-erPoint
lides are available to in tructors. The slides were reated by the textbook' author. res ulting in consiste ncy of perspective and emphasis be(\\, een the tides and this book. The slides are designed to be a truly effective teaching tool for the instructor. Most slides are graphics based (avoiding sLides con isting of j\bl bulleted lists of tex.t). The lides make e:<. t en ~ i\'e us of animation \\ here appropmue to gradually uO\'eil concept or build-up circuits. ~et e\en nnimated sli~ can b! printout out and undersuxxi. 1early e\er) figure. oncepL and e"tampie from tlt.b book i included io the set of almo t 500 lides. from \\ hich instructors choose.
=
Learn ing through discovery. The boo k emphasizes understanding the need fo r
new concepLS. which not onl y helps stude nts learn and remembe r the concept~. but develops reaso ning skills that can apply the concepts to other do mains. For example. rat her than just defi ning a carry- lookahead adder, the book shows intuitive bu t inefficient approac hes to buil ding a fas ter adder. even tua ll y solving the inefficienc ies and leading to ("discovering") the carry-lookahead des ign. Introduction to FPGAs. The book incl udes a full y boltom-up int rod uction to FPGAs. show ing stude nts co ncretely how a ci rcuit ca n be co nvcrtcd into :1 bitstream Ihat prog rams th e indi vidual lookup tables. switch I11 tl tri cc!!. and olher pro~ grammab le co mponents in an FPGA. This co ncrete int rod ucti on cli mi nntcS the mystery of th e increasingly-common FPGA devices.
3 complete - luuons m3DuJl (about 200 pages) containing !!olutions to c\ ef) end-of-chapter execci..-..e In thho book. The manual e.\tensively utilizes figures to illu. tr..ne .;:oluoo05.
~
PLUS ·
11r,1,,'PLU lIebsi". Dicit.1 Design;' supported b) \\'jle)PLL' - 3 po\\ rful nnd 'highly intcgrnted sulte of t a;hing and learning re,oun.-es dosignnal 3.: h II ~Iud '1doo . . olutions of selt"Cted e\ample.... anim:nion, f pen1l1ent 1,.'\m(,."C'pt. (b..."'llh ~ b) Prole>""r Ed DD
Preface
vi
vii
Preface
and aut hor-created an im:ttt.::d Po\\crPoint >;. pili:' cour~c an d homcwork managemcnt lOob. in one ~al:.y-to- li se wcb:, itc. To learn how to aCCC:":" thcsc fC~lIu re~. go 10 the Book Co mpa ni on Site at \\ w\\.w iley.comlcollcgelvahid. or w \ \ \\.dd\ ahid.com.
HOW TO USE THI S BOOK Thi... book \\a~ tlcsigned to allow nc\ ibil ity to choose among the most C0 l111110n appro:lt·hc:. to ma terial covc ragl!. We desc ribc :.cvcra l ilp proachcs below.
1Oe;
Completely traditional approach
RTl· focused appro a ch A n RTL-focu:-cd approach wo uld :.irnpl y covc r the fir!)t 6 chapters in ord er:
I. Introduction (C hapte r
controllers) before combinational components (e.g .• adders. comparators. etc.,. Such reordering may lead into RTL des ign more natu rall y than a tmditional approach. foll""lI1. instead an a~pr~ac h of increas ing abstraction rather than the traditional approach that arat es co mbmatlonal and sequentiaJ de ign. HD Ls can aga in be introduced at the end. left for another cou rse, or integrated after eac h chapter. This approach could aJw be used as an intermediary lep when migrating from a fu lly-trad itional approach to an RTL approac h. Migraling might involve gradually postponing the Chapter 6 sectjon~ - for example. covering Chapters 2 and 3. and then Sections 6.2 and 6.3. before mo,in. on to ~~~ -
I)
2. Co mbina tional logic de"-ign (Chaptl:f 2) J. Scquenti al logic design (C hapter 3) ..,t COlllbinmional and ~eqllc nti ;l l com ponent design (Chapter-t ) 5. RTL dc~ i gn (Chapter 5) 6. Optimizations and Tradeoffs (Chapter 6). to the extent desi red 7. Phyo;;ic;\I implcmcnl:ltion (C hapter 7) and/or Processor design (Chapter 8). to the c'Xlcnt des ired. We thin!'" thi ... io;; a great way to order the 1l1~lIcri'll. re:-.ulting in stud ents doi ng in teres ting RTL dc:..ign:- in abollt 7 \\ech. HDL" cnn be int roduced at the cnd if tim e pe rm its. or left fo r a !-Iccond course on digital desig n (as donc at UC R). or covcred immcdi ate ly a rter cach ch"ptcr - ,,11 threc app roac he~ appea r to be quil c C0 111111 0 n . Tra dition a l approach with some reordering
Thi", book can be readily u~ed in a trad itional approach that int roduces optim izatio n along \~ ith ba~ic dcsign. wit h a slight diffcrcnce from thc traditio nal approach bcing th e wapping of cove rage of combinat ion'll component.:. and sequent ial logic. a~ follo\V~: I . Introduction (Chaptcr 1) 2. Co mbinational logic dC!o.ign (C hapter 2) fo llo\\cd by combi nati onal logic opti m i~ n ll ion (Sec tion 6.2) 3. Scquential logic des ign (C hapter 3) fo llowed by ...cqucnti al Im! ic optimizati on (Section 6.3) -t o Combinati onal and sequcntial componc nt de\ign (C haptcr 4) fo llowed by componellt tradcoffs (Section 6.4) 5. RTL dc ... ign (Chapter 5) to the ex ten t dc, ired. followed by RTL opti1l1 i / ~ll ion/ tradeoff, (Swion 6.5) 6. Phyo.,ical i~l1plcmcn t::nion (Chapter 7) and/or Proccv.• or dc,ig n (C hnptcr 8). to the extcnt d e~ lrcd.
Till ... i".. :I ve ry rcao.,onabh.: and ef~·ec.t iv~ approach. completing all d i ~cus,ion or Oll l.! tu pie (c.~ .. I-SM dL''''lgn ~I'''. \\c ll :to., Optl l11 l1~lI l~lI1) he fore mov ing on to the nl.!x t topic. The n:nrtienng lrom .1 tr:ldlliona l ,Ipproach Introduce", h~h l c ,cqucnli al dC'Ign (FS M' tlild
Th is book could also be used in a com pletely traditional approach. '" follo\\ : I. Introd uction (Chapter I) 2. Combina ti onal logic design (Chapter 2) follo\\ed by combtnational logic opumi· zation (Section 6.2) 3. Co mbi national component design (Section 4.1. 4.3. 4.4. 4.5. 4.7. 4 .. 4.91 fol· lowed by co mbin ati onal component uadeoffs (Section 6A - Adders 4. Seq uential logic des ign (Chapter 3) followed b) sequential logic opumizanon (Section 6.3) 5. Sequential component design (Chapter 4. ecuons 4.2. 4.6. 4.101 follo\\OO b~ sequential co mponent tradeoffs (Section 6A - ~ l ultiplie~) 6. RTL design (Chapter 5) to the extent desired. follo\\OO b~ RTL opumizationl tradeolTs (Sectio n 6.5) 7. Ph ysical implementation (Chapter 7) andlor Proce",or design (Chapter l. to the ex tent desired.
This is thc mos t widespread approac h durin g. the past (\\ 0 decnde~. \\ ith the addition of RTL towards the end. Al though the emphasized distinction be{\\ een combmationJ.l and scquentia l design may no longer be rele\'ant in the era of RTL de... ign ~\\here both type:... of design are imemli xed). some people belic\-e that such distinction make~ for ~ C3.... ier learnin g path. which may be true. HOLs an be in luded at the end. left for a tller C\."')lII"'e. or integmted throughout.
ACKNOWLEDGEMENTS Man) people and organization~ contributed to thb ediuon I.)f the tx,,-"'l.. tafT memben. at Joh n \\'ile\ and Son ... Pubh ... he", hJ\e e\len"'l\el~ ",upP'-"'noo ~ book's de\'elopment. includi-ng Cutherine hultZ, GlJd~ ... l.)tO, Dana J....l!lk;g. and Kelly B ylc. Bill Zobrist ,upported m) e3J'lier ··Emb«lded ~ ,tern o,,'tgn- N . motivated me to \\ rite the pre~ent btlOk. Jnu pro\ IUNI g~.lt JJ\ II.: ~ thl\.\Ughl'lllt develop ment. R):111 ~ l :U1nion contributed man) lIem~. II1dUJ,lOg the Jrrcnu11.: • nwt".~I'\\U'" I: xamplc"- and C\C'rcl~e:.. ~e\ eml :.ub ... t: 'lion.... the ':I.)mrl<.'le !.'\ClX'l,e ,,,-)Iuth.)n ... manual. fnct.chcc!...tn\!, e\ ten'l\e proo(re~tdtng. IJ\:'mend\.,u ... J.."t'I .•lnl.:· Junn£. P(\"duclI(ln. help \\ Ith th;' ,lid6. plent) llf I...ka., dunnt! ..IN.'u''1 ...''n' .•\OJ l11u,,--h m\m!
viii
Preface Ro man Lyscc ky deve loped numerouS exampl es and exe rcises. contri buted most of the conte nt of the HDL chapler. and co-authored our accompanyin g HDL-introduction books. Roman and Susan Lysecky providcd muc h proo freading assistance. Numerous reviewe rs provided outstanding feedbac k on various vers ion s o f the book. Spec ial thanks go to earl y adopters, such as Niki l Out!, Shannon Tauro. J. Dav id Gillanders, Shcldon Tan. Trav is Doo m. Roman Lysecky, a nd others. who prov ided excelle nt feedba ck from them se lves and from their students. Th e importance of th e support provided to my resea rch and lcachin g caree r by the Natio n'll Science Fou ndation cannot be overstated. Additional suppo rt from th e Se mi condu ctor Researc h Corporation ca tal yzed industry co llaboratio ns lhat in tum inOuenced mallY of th e perspectives in thi s boo k.
ABOUT THE COVER The cove r's image of shrinking squares graphically depicts the amaz ing rcal-life pheno men a of di gital ci rcuits ('computer chips' ) shrinking in size by one half roughl y every 18 mont hs. for several decades now. a phenomena ofte n referred to as Moore's Law. Such shrinki ng has enab led in credibly powerfu l computing circuits to fit in tiny devices. like modem ce ll phones, medical devices, and portable video games. See pages 34 and 35 for a disc uss ion of Moore's Law.
ABOUT THE AUTHOR Frank Vahid is a Professor of Computer Science & Engineering at the Uni versity o f Ca lifornia. Ri vers ide. He holds Electrical Engin eering and Compu ter Science degrees: has worked/consu lted for Hewlett Packard. AMCC. NEe. Motorola. and medica l equipm ent makers: holds 3 U.S. patents: has received several teaching awards; hclped se tup UCR's Computer En gineering program; has a uthored two prcvious textbooks: and has published ove r 120 papers on digital desig n to pics (automation. architeclu re, and low- power).
Reviewers and Evaluators Rehab Abdel-Kader Otmane Ail Moha med Hussa in AI -Asaad Rocio Alba-Aores Basse m A lhalabi Zekeriya Ali yaz iciog lu Visha l Anand Bevan Baas Noni Bohonak Don Bouldin David Bourner Elah eh Bozorgzadeh Frank Cand oc ia Ralph Carestia Rajan M . Chandra Ghulam Chaudhry Michael Chelian Ru sse ll Clark James Conrad Kevan Croteau Sa njoy Das Ja mes Davis Edward Doering Travis Doom Jim Duckworth Nikil Dutt De nni s Fairclough Paul D. Franzo n Subra Ganesan Zane Gastineau J. Dav id Gill a nder, C lay Gl oste r Ardian Grcca Eric Ha nse n Bruce A. Harvey John P. Hayes Mi chae l Helm William HolT Erh-We n Hu Baback ILadi
Georgia Southern University Concordia University University of California. Davis University of Mjnnesota. Duluth Florida Atlantic Un iversity Cal iforn ia Pol ytechnic State UniversIty. Pomona SUNY Brockpon University of California. Davis Uni versity of South Carolina. Lancaster University of Tennessee University of Maryland Baltimore Coun!) Uni versity of California. m i ne R orida International University Oregon Institute of Technology California Polytechnic State Universi!). Pomona University of Mis ouri. Kansas Cit~ Californi a State University. Long Bea h Saginaw Val ley State Univcrsit} University of Nonh Carolina. Charlotte Francis Mari on University Kansas Slare Unh'ersity Uni versi ty of South Carolina Rose-Hu lman Institute of Technolog) \Vrighl Slate Uni \ crsiry \Vorcester Pol) technic institute University of California. Iryine Utah Valle) late College 'orth Carolina uue Unher;il'\ Oakland Uni, ersit) . Harding ni,ersi!) Arkansas tate Unherslt) Howard nh ersil) Georgia S uthem l'nhersit) Dartmouth College FAM U·FSll College of Englne-ering Uni\·e~it) of ~1 ichigan
Texas Tech
Unt\t:'~lt~
C lorad chool of Mine. \ i1liam Ptllcf'lon Unt\en.lt) of l\'e\\ Jef't:~
UNY 'e\\ P:tlu
Reviewers and Eva luators
viii
Jerf J 3ck~OIl An ura J ay a ~ ulllan;} Bruce Johnson Ri chard J o hn ~ toll RJji v Kapadia Bahadir Knruv Robe rt Klenke Clint Koh l Ht:rrnann Kromphol z Timoth y KUI7;Wt:g JUl1lokc L ~l d eji - Osi3s
Jeffrey Lillie
ABOI
David Livingston Hong Man Gihan M ilndour Di ana M :lrculesc tl Miguel [l,llarin M Ll ryHIll M ouss avi
Olb
ABO
Na~raoui
P;:1Irici~1 Nava John Nestor Roge lio Pal oll1cra Ji.IIllC:-. Peckal \Vitale! Pedrycz Andrew Pcrry Denis Popel Tariq Qilyyum Gang Qu M ih:lclu RLldu Suresh Rai William Rcid Mu!.okc Scndnu ln SCOlt Smith
Gary Spivey Lnrry St ephens Jamc!. Stine Philip Swain Shannon T
University or Alabama Colorado State Uni versity Universit y or Nevada, Reno Lawrencc Technologic
Springfield College Bakcr University Cali romia Polytec hnic State Universit y. Pomona University of Maryland Rosc-Hulman Insti tute or Tcc hnology Louisiana Statc UniverSity. Bnt on Rouge Clemson Uni versity Temple Univcrsity Boise Statc University Gcorge Fox University Univcrsity or South Carolina Ill inois InstitUic or Technology Purduc University University or California. Irvinc Gonzaga Universi ty
Oregon Institute of Techn logy Univcrsity or Kansi:\'\ Wright State Ullivcr~ ity Ncw York In,titutc of Tcchnology Roc;hcM:r Institut e of Technology
Califom" Sto te Univcr\ it y. Lo ng Be.lch San Jaoqui n Delt a oll ege
Contents Preface iii
3.3 3A 3.5
Finite-State Machines (FSMs) and Controllers I II Controller Design 120 More on Flip-Flops and Controllm
3.6
Sequential Logic Oplimizations and Tradeoff~
Content s xi
CHAPTER 1 1
Introduction 1. 1 1.2 1.3
1.4 1.5
Digital Sys tems in the World Around Us Th e World or Digital Systems 4 Implemcnting Di gital Systems: Programming Microprocessors versus Designing Digital Circuits 17 About thi s Boo k 23 Exercises 24
(See Section 6.3) 3.7
Sequenlial Logic Descrip[ion using Hardware Description Language..,
CHAPTER 5 Register-Transfer level (RTl) DeSign 1_S 5.1 Introdu("lton .!!.S .5 ..! RTL IX'lell \ l
xii
Contents
vi ii 5.5 Behavioral-Level Design: C to Gates (Oplional) 254 5.6 Memory Components 258 5.7 Queues (FIFOs) 27 1 5.8 Hierarchy-A Key Design Concept 275 5.9 RTL Design Optimiza ti ons and TradeofTs (See Section 6.5) 278 5.10 RTL Design using Hard ware Dcscriplion Languages (Sec Section 9.5) 279 5. 11 Produci Profi le: Cell Phone 279 5. 12 Chaptcr Summary 285 5. 13 Exercises 285
AS
AE
CHAPTER 6 Optimizalions and Tradeoffs 294 6.1 Imroduct ion 294 6.2 Combinational Logic Optimizalions and Trodeoffs 296 6.3 Scquelllial Logic Optimizalions and Tradeoffs 317 6A Dalnpalh Componelll Tradeoffs 333 6.5 RTL Design Optimizations and Tradeoffs 345 6.6 More on Oplimizations and Tradeoffs 354 6.7 Product Profile: Digital Video Playerl Recorder 36 1 6.8 Chapler Summary 370 6.9 Exercises 370 CHAPTER 7 Physical Implementation 379 7. 1 In lroduClion 379 7.2 ManufaclU rcd IC Technologies 379 7.3 Programmable IC Technology-FPGA 388 7.4 Other Technologies 40 1 7.5 IC Technology Comparisons 409 7.6 Prod uel Profile: Giani Video Display 412 7.7 Chapler Summary 416 7.8 Exercises 4 17 CHAPTER 8 Programmable Processors 421 8.1 In!roduclion 42 1 8.2 Basic Architecture 422 8.3 A Three- Instruction Programmable Proce!)sor 428
8A
A Six- Instruction Programmable Processor 434 Example Assembly and Machine Progrnms 438 8.6 Funher Extensions 10 the Programmable Processor 439 8.7 Chapler Summary 44 1 8.8 Exercises 442 8.5
CHAPTER 9 Hardware Description Languages 445 9.1 Introduction 445 9.2 Combinational Logic Description Using Hardware Description Languages 447 9.3 Sequential Logic Description Using Hardware Description Languages 459 9.4 Dmapmh Companelll Deseriplion Usi ng Hardware Description Languages 467 9.5 RTL Design Using Hardware Description Languages 475 9.6 Chapler Summary 492 9.7 Exercises 492
1 Introduction 1.1 DIGITAL SYSTEMS IN THE WORLD AROUND US Meet Arianna. Arianna is a five-year-old girl who lives in CaJjfomia. She's a cheerful. outgoing kid who loves to read, play soccer. dance. and lell jokes thai she makes up be""lf.
APPENDIX A Boolean Algebras 496 A. I BOOlean Algebra 496 A.2 SWilching Algebra 497 A.3 Impanam Theorems in Boolean Algebra 498 AA Olher Examples of Boolean Algebras 504 A.5 Funher Readings 504 APPENDIX B Additiona l Topics in Binary Number Systems B.I Inlroduclion 505 B.2 Real umber Represcnlation 505 B.3 Fixed Poilll Arilhmelic 508 8.4 Floming Poim Represelll," ion 509 B.5 Exercises 514
505
APPENDIX C Extended RTL Design Example 515 C.I Inlroduclion 515 C.2 DeSigning Ihe Soda Di 'pen,cr Con !roller 516 C.3 Undemanding Ihe Behavior of Ihe . odn Dispcn;cr COlllrOlicr nnd Dn",,,nlh 5 19 Index 526
One day. Ananna's family was driving home from n soccer game. She was in the middle of excitedly talking about the game when suddenly the van in which she was riding was clipped b~ 3 car thai had crossed O\'er to the wrong side of the higb", a~ . Although lhe aceidenl wasn·, panicularly bad. the impa I caused a loose item from the rear of the van 10 project forward inside Lhe: van. slriking Ananna in the back of the head. he "cnt unconsciou . Annnna wns rushed to a hospital. Doctors immediatel) noticed that tk!r b~athmg wns vcry weak-a common situ:llion after a se\ ere blo" to the head-.. o ~~ put her onto n ventilator. which is Amedical dl!vice lh::u ~bL' with breathing. he;' hJd ... ~t3Jnro brain tmumA dunng the blow (0 the hend. nnd she rel1lain~ unco~(:i~ for ~ \ern1 weeks. All her vi tal signs were !)t3ble, ex ept ,he ("onllnued to re-qulre breaming a.. . . . I.. Innce fro m the ventilmor. Patients in such tl Idtu3tion some tames 1'l'\."'O\er. .:md 'nnl
I Introduction
viii
1.1 Digital Systems in the World Around Us Thanks to the advenl of modern port able venti lators, Arianna's parents were gi ven the opti on of taking her home while they hoped for her recovery, an option they chose. In addition to the remote monitoring of vi tal signs and the daily at-home visits by a nurse and respiratory therapist. Arianna was surrou nded by her parents, brother, sister. cousins. other family, and frie nds. For the majority of the day. someone was hold ing her hand , singing to her,
Portable ventilators help not only trauma victims. but even more commonly help patientS with debi litating diseases, like multiple sclerosis. to gain mObility. Such people can today move about in a wheelchair, and hence do things like attend school. visi l museum . and take part in a family picnic. experiencing a far better quality of life than was feasible JUSt a decade ago when those people would have been confined to a bed connected to a large. heavy, expensive ventilator. For example. the young gi rl pictured on the left will li kely require a ventilator for the rest of her life-but he will be able to Phoro courtesy of PlllmOI1l'li('~ move about in her wheelchair quite freely. rather than being mostl y confined to her home. The LTV 1000 ventilator described above was conceived and de igned by a mall group of people. pictured on the lefL who sought to build a ponable and reliable ventilator in order to help people like Arianna and thousands of others like her (as well as to make ome good money doing o!). Those designers probably started off like you. reading textPholO cOllrles), oj PIIIII/Ollel;c,,' books and taking courses on digital de ign. programming. electronics. and/or other subjectS. The ventilalor is just one of literally thol/sands of use ful device that have Come about and continue to be created thanks to the era of digital circuits. If you top and think about how many dev ices in the 1V0rid around you rely on or are made po sible becau e of digital cirCuits, you may be quite surpri sed. A few such devices include:
whispering in her ear. and encourag ing her LO recover. Her
sister slept nearby, Some studies show th at such hu man interaction can indeed increase the chances of recovery. And recover she did. One day, several months later, with Arianna's mom sitting at her side, Arianna opened her eyes, Later that day. she was transported back to the hospital. After some time. she was weaned from the ventilator. Then, after a lengthy time of recovery and rehabilitation. Arianna finall y went home. Today, six-yearold Arianna shows few signs of the accident that nearly took her life. What does th is story have to do with digi tal design? Arianna's recovery was aided by a portable ventilator device, which in turn is possible thanks to di gital circuits. Over the past three decades, the amoun t of digital circu itry that can be stored on a single computer chip has increased dramatically_by nearly 100.000 times . bel ieve it or not. Thus. ventilators, along with almost everything else that runs on electrici ty, can take advantage of incredibly powerful and fast yet inexpensive digital circuits. The ventilator in Arianna's case was the Pulmonetics LTV 1000 ventilator. Whereas a ventil ator of the early 19905 might have been the size of a large copy machine and cost perhaps $100,000. the LTV 1000 is not much biooer or hea' h 00 I'ler t an this textbook and costs on ly a few thousand dOllars~small enough, and inexpensive enough, to be c,arned In med ical rescue helicopters and ambulances for life-saving Situat ions, and even to be sent home with a patient. The digital circuits in side conti nua lly mon itor the pat ient 's breathing, and provide just the right amount of air preSSure and volume to Ihe palient. Evel), breath thai the deVice deli vers requ ires 1II;/I;OIlS of compulations for proper delivery, computat ions carri ed ou t by the digital CirCUitS inside.
AI
A
g
Portable velllilator
3
Antilock brakes. ai rbags. aUlofocus cameras. automatic teller rn3 hines. aircraft conrroUers and navigators, camcorders. CilSh regi ster. ce ll phones. computer net\\orks. credit card readers, cruise controllers. dcfibrillmors. digital cameras. DVD players. electri card reader'S. electron ic games. electronic pianos. fax machine!), fingerprint identjfiers. hearing aids. home
securi ty systems. modems. pacemakers. pagers. personal compute". personal digita1 assislants. photocopiers, port able music players. robotic aml . I.,canner-, lele\"ision~. IDc!nn Stat
cOlllrolicrs. TV se t-top boxes. ventilators. vid\!o game consoles-the a ile il/dicalor oj Ihe ra fe I"ar lIe\\' ;III'(:' m;OIl .\' are
deve/oped is Ih e
number of 11(:,11' ptllelltS gran/ct/-
170.000 per yellr i" the U.S. (llolle!
Ii.:,(
goe\ on.
Those devices were created by tens of thousands of designers. including omputer sc ientists. computer engineers. electrical engineers. mechanical engineers. and others. working together wi th scienti sts. doctors. busine s people. teachers. etc. One thing that seems clear is thai new devices wil l continue to be inyented for the foreenelit. Future designers. li ke YOllrselr perhaps. \\ ill h Ip dl'tennine th;}t.
4
1.2 The World of Digital Systems
1 Introduction
1.2 THE WORLD OF DIGITAL SYSTEMS Digital versus Analog
.
. h one of a finite sel of possIble values, A digilal signal is a signal Ihal al any lime can ave log signal can have one of an . ' I [n contraSI , an alia continuouS sional. A signal I.S · I k an d I S a so ' nown as a discrete Si g na. . . . d ' Iso known as a 0 mfil1lle number of possIbl e values, an IS a . I I every inslant of time. An . . I h a unIque va ue a JUSI some physIcal phenomena 11al as ts'lde because phys ical tem. . h temperature ou " . everyday exam ple of an analog sIgnal IS t e b 92 356666 degrees An ture may e · .. . . perature is a continuous value-the lempera ft· you hold up because the . . humber 0 lIlgers , eve ryday examp le of a di gital sIgnal IS l e n fi '1 set of values [n fac t the . 7 8 9 or IO--a 111 e ., va lue must be en her 0, I, 2. 3, 4, 5, 6. , , ' . . (d"1 s) 111eaning finoer .. " .. . d f "dl on" Igl U , 0 . lerm dlgnal comes from Ihe Lalln wor or 0 . I those th'lt can have one of dOoital siona s are ( In compuling syslems, Ihe mOSI common 10 0 d 1 or 0) . Such a two-valued . I'k ff (often represenle as on Iy two possIble values. I'e on or 0 . d' '1 I slem is a system that takes . . k b' resenlauon. A Igl a sy representauon IS ' nown as a lIIary rep .. .. . nnection of digital com.. . .. I A dlgllal clfclIIl IS a co dlgnal mputs and generates dlgna out pUIS. . b k the term dioital wi ll refer 00 ponenlS Ihat logelher comprise a digilal system. [n thIS text 1 k' own as a binary digit or A' I binary slona IS n , , . . . 10 systems wnh bmary-valued sIgnals. slllg e 0 I ular in the mid-1900s bil fo r short (binary digit). Digi lal electrolllcs became extreme YbPOPI med 011 or off usin o . ' switch thaI can e uh 0 after the . mve. nllon of the transIstor, an eIectnc . . f rther in the next c apler. another electric signal. We' ll descnbe IranslSlors u .
A geneml-pllrpose compllfer
Embedded systems
Digital circuits are the basis for computers d . b bl . . ICIrCUI ' 'Is 'n The most well -k nown use of dlgna I the world aroun us IS pro a yI'kto build the microprocessors that serve as the brain of general-purpose computers, I e h t you mi ooht have at. home. Generalthe personal computer or laptop computer ta purpose computers are also used as servers, \vhich operate behllld . the . scenes to implement banking, airline reservation, web search, payroll , and SImilar such systems. General-purpose computers take digital input data, such as lellers and numbers received from files or keyboards, and output new dIgItal data, such as n~w lellers and numbers stored in files or di splayed on a monitor. Lear,~ lI1 g about dlglt~~ design is therefore useful in understanding how computers work u.nder the hood, and hence has been required leaming for most computing and ele~t nca lengineenng majors for decades. Based on material in upcoming chapters, we II deSIgn a SImple com puter in Chapter 8. Digital circuits are the basis for much more " Increasingly, di gital circuits are being used for much more than Implem: ntmg general-purpose computers. More and more new applicallonsconve.rt analog SIgnals to digital ones, and run tho e digital signal s through customIzed dlgllal CirCU Its, .to achieve numerous benefits. Such applications include cell phones, automobIle engine controllers, TV set-lop boxes, music instruments, digital cameras and camcorders, video game consoles, and so on. Digital circuits found inside applications other than general-purpose computers are often called embcllded sysl ems, because those digital systems are embedded inside another electronic device.
o ~
5
The world is mostly analog, and therefore many applications were previously implemented with analog circuits. But many implementalions have changed or are changing over to digital implementations. To understand why, we might first notice Lhat although the world is Sound waves •_____ ..::::L ________ . most ly analog, humans often obtain advantages when converting move the analog signals 10 digital signals before "processing" that infonnation. For example. a car horn is actually an analog signal-the volume cao take on infinite possible va lues, and the volume varies over time due to variations in the battery sLrength, temperature, etc. But. we i + j the magnet. humans neglect those variati ons, and we "digitize" the sound we hear , , into one of two values: the car hom is "off." or the car hom is "on" (gel out of Ihe way!). Converting analog phenomena to digital. for use with digital cirwhich creates CUi IS, can also yield many advantages. Let's illustrate this point by current in the nearby wi re considering one example, audio recording, in some detail. Audio is clearly an analog signal. with infinite possible frequencie and volumes. Consider recording an audio signal. li ke music, through a microphone. 0 that the music can laLer be played over speakers in an electronic stereo y tem. One type of microphone. a dynamic microphone, works based on a principle of electromagnetism-moving a magnet near a wire causes changing current (and hence voltage) in a nearby wire. The more the magnet moves. the higher the VOltage on the wire. So a microphone has a small membrane attached to a magnel near a wire-when sound hits the membrane, the magnet moves. causing current in the wire. Likewise. a peaker works on the same principle i; reverse--a changing current in a wire wi ll cause a nearby magnet to move, which if allached to a membrane wi ll create sound . (If you get a chance. open up an old speaker- you'lI find a strong magnet inside.) If the microphone is allached directly to the speaker (through ao amplifier that strengthens the microphone' output current), then no digitization is required. But what if we want to save the sound on ome sort of media, so \\e cao record a song now and play the song back later? We can record sound using analog methods or digital methods. but di gital methods have many advantages. One advantage of digital methods is lack of deterioration in qualiry over time, When I was grow ing up, the audio casselle tape, an analog method. was the mo t common method for recording song. Audio tape contain huge numbers of magnetic particles that can be moved to particular orientations using a magnet and that hold that orientation even after the magnet is removed. Thus, using magnetism, we could hange the tape' surface. ome pans up. ome higher. some down. etc. This is similar to how you can -pike your hair, some up, some sideways. some down. using hair ge\. The po ible orientations of the tape's particles. and your hair, are infinite, so the tape is definitely anal g. To record onlO a tape, we pas the tape under a "head" that generates a magnetic field based on the electric current over the wire coming from a microphone. The tape' panicle "ould thus be • the t:lpe moved to particular orientations. To playa recorded song back. \\c \\ uld under the head again, but this time the head operate in reverse, genernting current Q\ r a wire based on the changing magnetic fie ld of the tape. and that current then gets amplified and sent to the speakers.
:I '+
: '
I IU 6.'d i::i~hb:::~s
t ===_
l ___ ~!:~ ~~~_~~_'!--. .:-="=:
,
6
1.2 The World of Digital Systems
I Introduction analog signal on,wire
, ,, ,, ,
", ___ digitized signal ,,--- 000 11 01011 111101101 000
. d' . I . al (top). and vice versa (bollom). Notice Figure 1.1 Converti ng an analog Signal 10 a Igna sign some quality loss in the reproduced signal.
is that the orientations of the panicles on the tape's ~ . . . A pro blem W .ith aud'10 tape surface change over time- just like a spiked hatrdo In the morning eventually flatten s o~t throughout the day. Thus, audio tape quality deteriorates over time. Such detenoratlOn IS a problem with many analog systems. . .. . Di gitizing the audio can reduce such deterioration. Digiti zed audIO :"orks as shown in Figure 1. 1. The fig ure shows an analog signal on a wire dunng a period of ttme. We sample that sional at panicular time intervals, shown by the dashed hnes. Assummg the analog signal ~an range from 0 Volts to 3 Volts, and that we plan to store each sample usin o two bits. then we must ro und each sample to the nearest Volt (0, 1, 2, or 3), shown as p~ints in the figure . We can SlOre 0 Volts as the two bits 00, I Volt as the two bits 01 , 2 Volts as the two bits 10, and 3 Volts as the two bits 11. Thus, we wou ld conven the shown analog signal into the fo llowing digital signal : 00011010111111 0 11 0 1 000. To record thi s di gital signal, we just need to store Os and Is on the recording media. We could use regu lar audio tape, using a short beep to represent a 1 and no beep to represent a 0, for example. While the audio signal on the tape wi ll deteriorate over time, we can still certai nly tell the difference between a beep and no beep, just like we can tell the difference between a car hom bei ng on or off. A sligllll y quieter beep is still a beep. You 've likely heard digi ti zed data commu nicated using a manner simi lar to such beeps when you've picked up a phone being used by a computer modem or a fax machine. Even betler than audio tape, we can record the digital signal using a media spec ifically designed 10 store Os and Is. For example, the surface of a D (compact di sk) can be configured to ei ther refl ect a laser beam to a sensor strongly or weak.ly,
7
Ihu s sloring Is ~nd Os eas il y. Likewise. compUler hard disks in compuler use magnetic panicle onematl on 10 Slore Os and Is, making such disks si mil ar 10 audio tape. but enabling fas ler access to random pans of the disk since the head can move sideways across the top of the spinning disk. To play bac k this digitized audi o signal, we can simpl y conven the digital value of eac h sampling peri od to an ana log signal, as shown at the bOllom of Figure 1. 1. Notice Ihal Ihe reproduced signal is not an exact repli ca of the ori gi nal analog signal. However. the faster we ample Ihe analog signa l and the more bits we use for each sample. the closer Ihe reproduced analog signal derived from the digil ized signal will be to Ihe origina l analog signal- a! so me poinl , humans can' l not ice Ihe difference between a pure audio signal and one thm has been digitized and then convened back to analog. Another advan lage of digitized audio is compres ion. Suppose Ihat we'lI be lOring each sample with ten bits, in stead of IWO bits like above, 10 achieve much beller quality due 10 less rounding. But thal 's a lot more bils for the same audi o-the signal in Figure 1. 1 has eleven amp les, and a[ len bils per sample. that yields one hundred ten bits 10 store the audio. If we sampl e hundreds or Ihousands of time a second. we end up with huge numbers of bil s. Suppose, though, that a panicular audio recording has many samples th at have Ihe value 0000000000 and Ihe value 111111111l. We could compress the digital file by using the following trick: if the firsl bit of a ample i O. the nex l bit being 0 means the sample is actually supposed 10 be expanded 10 0000000000: the nex t bi t being I means the sample i 111111111l. So 00 i shonhand for 0000000000. and 01 is shonhand fo r 1111111111. If the first bil of a sa mple is l. then the next len bits represent the actuaJ sample . So the digitized signal "0000000000 0000000000 0000001111 1111111111 " would be compre cd to "00 00 10000001111 01." The receiver. which must know the com pres ion scheme, wou ld decompress that signal into the original digitized signal. There are many other tricks that can be used 10 compress digitized audio. Perhaps the mo tly widely known audio compression scheme is known as MP3. which is popular for com pres ing digitized songs. A typical song mighl requ ire many lens of megabyle uncompre ed. bUI compressed usually only req uires about 3 or 4 megabyte . An audio CD can lore aboul 20 songs uncompressed. but aboul 200 ongs com pres cd. Thanks 10 compre ion (combined wilh higher-capacily disks), loday ' ponable music players can tore thousands of songs-a capability undreamt of by mo I people in Ihe 1990 . Di giti zed audio is widely used not only in mu ic recording, but also in voi e communicali ons. For example. digilal ce llul ar telephones digitize your voice and then compres the digilal signal before transmilling Ihe ignal. enabling far more cell phones to operate in a panicul ar region than possible using analog cell phones. Satellites DVD Video players recorders Portable Cell phones music players Cameras 1995
1997
1999
2001
2003
2005
MusJCal instruments
TVs 2007
Figure 1.2 More and more analog produ ts are bt.-coming primarily digit!!.!.
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•
1.2 The Wo rld of Digital Systems
8
Introductio n
9
Digital Encodings and Binary Numbers
manner sl11111ar 10 that descnbed for aud.o. Pi ctures and video can be dlgll ized In a , h ghl y-co mpressed dl glla l fo rm . and pictures In I Dl glla l Cdmems. for example, slOre d sks In compressed form too dlgllal Video recorders SlOre Video onlO tapes or I few of the hundreds of new a nd d Video arc Just a . Dlg lli zed audiO, pictures. an of ana 100 phenome na As shown 111 zalion '" d Illl ure ,'ppl ,callo ns th at bene fi t from dl",lI '" lar products prev IO usly base o n d de numerouS popu ' ani 10 dlgllal technology Ponable muSiC Figure I 2. over the past eca. to CDs In the midd le 1990s, a nd "n 310g technology. ha ve conve rted pnm, Y I d from cassette tapes I \I phones used analog comm UOlcapl,.ye rs. for exampl e. SWIIC1e lecent ly to MP3s and other dlgll al form ats Ear y ce mdar In Idea to that shown 111 1990 d tal commulllcallon , S. tl o n. but In the late s Igl , I 2000s, analog VHS v.deo players gave way Figu re 1. 1. beca me do minant In the ear y b t dl ollize v.deo be fo re stonng the 'd corders have egun 0 '" to d lg llal DVD players. VI eo re d fi l ntlfely and In stead slOre photos m e . ha ve eliminate vlcleo o nto tape. wh. Ie cameras Iy d. gllal-based wllh e lectrontC 1 t l1cnts are Increasmg . uSin g dlglla l cards Muslca inS rU I ' rit and electnc gUllars w llh d .g .tal prodrums and keyboa rds IIlc reasIng III popula Y'. . Y 10 di oital TV. Hundreds of . . I A aloo TV IS also giVing wa '" cess lIlg appea nng recent y. n '" . . I' st decades such as cloc ks a nd other dev ices have conve rted from analog 10 d.glta InhPa ometers (' which now wo rk in t human temperature term watches, ho usehold th ermosta s, ) gine controllers oasoline the car ra ther than under the tongue or other places car en . e
The previous section showed an example o f a di gital system, which involved digitizing an aud io signa l into bits, which we could the n process using a digital circuit to achieve several bene fits. Those bits el/coded the data of interest. Encodi ng data into bits is a central tas k in di g ita l systems. Some of the data we want to proces may already be in di gita l fo rm, whi le other data may be in ana log form (e,g. aud io, video. temperature) and th us req uire convers ion to dig ital data first , as illustrated at the top of Figure 1.3. A di gital syste m takes di gi tal data as input, and produces di g ita l data as output. E ncoding a na log phenomena An y ana log phe no mena ca n be digitized, and hence cou ntle s a pplications have evolved and contin ue to evolve that digiti ze ana log phenomena. Automobiles digitize informatio n about the e ng ine te mperature, car speed. fue l leve l. e tc., 0 that an on-chip compute r ca n moni to r and contro l the vehicle. The ventilator we introduced earlier digiti zes the measure o f the air fl ow into the patient, so that a compute r can make calcu lations on how muc h addition a l Row to provide. And so on. Digitizing analog pheno mena req ui res;
t
pumps. hea rin g aids. and so on.
. d bein o introduced in di gital form from the o. .' . .d oes have been di gital sillce thelf IIlceplion . . ve ry start. For example. VI eo ",am .' 1 d Os. Computations uSlllg Di giti zat ion requ ires that we encode tillngs Into sl an d Os We introduce these di gi tal circuits require that we represent numbers usmg s an . aspects of digital circuits now.
Many devices were never analog. IOstea
Figure 1.3 A typical di gital system.
Sell and his assistant Watson disagreed on
operates using the electromagnetic principle described earlier-your speech creates sound waves that move a
how
membrane. wh ich moves a magnet, which creates
current on a nearby wire. Run that wire to somewhere far away. put :l magnet connec ted 10 a membrane near that wire. and the membrane will move, producing sound
waves tha. sound like you talking. Much of .he telephone system today di gitizes the audio '0 improve quality and quantity of audio transmissions over long distances. A
couple of illleresting facts about the .elephone; Believe it or no•. Western Union actuall y tumed dow n Sell's initial proposal to develop the telephone. perhaps .hinking that the then-popular telegraph was all people needed.
to answer the
phone; Watson wanted "Hello:' which won. but Sell wanted "Hoy hoy" instead, (Fans of the TV show "The Simpsons" may have noticed lhat Homer's boss, Mr. Sums, answers the phone with a "hoy hoy." )
o0
1 0 000 1
"' t's 33 degrees" All early-slyle ,elepltolle.
(Source of some of the above materia l: www.pbs.org. trunscript of '1'he Telephone").
An alia log-la-digital call verIer that convens the electrical ignal into binary e ncodi ngs. The converter must sample (measure) the e lectrical signal at a panicular rate and conve n each sample to some value of bits. Such a converter was featured in Figure 1.1, and hown as the A2D compo nent in Figure 1.3. Likewise. a digilal-Io-allalog COli verier (s hown as D2A in Figure \.3) convens bits back 10 an e lec trical s ignal , a nd an achlOlor convens mat electrical signal back to physica l phenomena. Sensors and actuators together represent type of devices known as Irallsdllcers--devices that convert one form of e nergy to anomer. In many examples th roug hout this book, we will utili ze idealized sensors mat themselves directly output di g itized data. For example. we might utilize a temperature sen or that reads me present tempe rature and sets its 8-bit output to an encoding mat represents the te mperature as a binary numbe r (see next sections for binary number encoding ).
.. THE TELEPHONE. The telephone. pmented by Alexander Graham Sell in the late 1800s (though invented by Antonio Meucci).
A sel/sor that mea ures the analog physical phe nomena and converts me measured va lue to an ana log e lectrical signa l. One example is the microphone (which measures sound ) in Fi gure 1. 1. Other common examples include video capture devices (whi ch measure li ght), thermo meters (which measures temperature). and speedo me te r (whic h measure peed).
E ncoding digita l phenomena Other phenomena a re inhere ntl y di g ital. Such phenomena can only as ume one value from a finite set of values. So me d ig ita l phenomena can a ume only one of two pos ible value. and mus can be straigh tforward ly e ncoded as a sing le bit. For example. the following types of sensors may output an e lectri cal signal that a umes one of twO valu : Motion sensor; o utputs a positive voltage (say volts when no mot ion is sensed.
+.' )
when motion is en
. 0
10
1 Introduction
1.2 The World of Digital Systems
when li oht is sensed, 0 V when dark. ' . d 0 V when Light sensor: outputs a pOSlllve volta " C " .. I ge when the button IS presse . Button (sensor): outputs a posllive vo ta nOl pressed . r's output to a bit. with 1 representi ng We can straight forwardly encode each senso I tl oughout thi s book we will the pos iti ve voltage and 0 representing 0 V. In examp es . lr I ' .. . . . I t t the encoded b11 va ue. utili ze Idea lized sensors that dIrect y OUpu 'bl I s For example a keypad , e several POSSI e va ue . Other digital phenomena can assum ' bl k A desioner mi oht create a ' oreen.' and. ac. " 001;" blue might d blu ~." may have four bUllons. co lored re. h the value circuit such that when red is pressed. a three-bll output as d the output mioht be 000. output 010 . green 011. and black 100 . If no bunon IS presse , " "
a
a
t
a
.
0
na IS the Enollsh alphabet. Each FIgure I 4 Illustrates such a keypad An even more general di gItal phenome " keyboard " fi t set of characters so typtng on a f ' th d tal data to bIts by charactcr comes rom a nt e I data We can convert e Igl results tn dlgl ta I. not ana og, . I odll1 o of Engltsh assl o nll1g a bl l encodtng to each character A popu ar e~c d" d Code for cha;;'cters IS known as ASCII (standtng for Amencan tan ar F des each character tnto seven blls. or 'A" "1000001" and Inlormalton Interchange). wIllCh enco CII d fo r Ihe uppercase lener IS , example. Ihe AS enco IIIg . , , , 00001 " d 'b' IS "1100010." for 'B' IS "1000010 " A lowercase a IS 11 , an 1000010 Th ' h e "ABBA" would be encoded as "1000001 us. I e nam d ' II 26 I tters (upper 10000101000001 " ASCII defi nes 7-blt enco tngs .or a . e . I sy mb0Is 0 tllrouoh and lowercase), Ihe numenca '" 9 punctuatIon " . marks, ande even a number of encod ings fo r nonprinlable "control operaltons. There ar 128 encodings 10lal in ASC Il . A subset of ASCli encodll1gs .IS shown .in Figure 1.5. Another encoding, Unicode, is increasi ng tn popul anty due to Its support of international languages. Unicode uses 16 bils per character, II1s tead of jusl the 7 bils used in ASC II , and represenls characters from a dIversity of languages in the world .
Figure 1.5 Sample ASCn encodings. Encoding numbers . . Perhaps the most important use of digital circuits is to perform arithmetIC computallOns. In fact , a key dri ver of earl y digital com puter design was the arithmetic computations of ballistic trajectories in World War L1 . To perform arithmetic computat ions, we need a way to represent numbers using binary digi ts-we need binary numbers.
~
WHY BASE TEN?
Humans have len fingers. so they chose a numbering system where cHeh digi t can represent len poss ible
values. There's nOlhing magical aboul base ten. If humans had nine fingers, we'd probably usc a base nine numbering sys tem. It !Urns Out thut base twelve was used somewhat in the past 100, because by using our lhumb. we can easily point 10 twe lve different
spots on the remaining four fingers on that Ihumbs's
523
Figure 1.6 Base len number system.
The Wt,b s('(lf'C:h engin e Google's Illlm e cOllieS from ,IIe lI'om "googol"
f ollowed by JCKJ :.elves,
-(J }
aplJllrelllJy
imply ing the ellg ille ellll search
a/% j '-,l/o rl1lal;oll.
o Figure 1.7 Base Iwo number system.
I sail' the/ollowillg 011
II
a T-shirt, ami
Jound il rather
filllllY:
"TIlere nrc I0 types or people in the world: those who get binnry. and
those who don't."
hand-the four tops of those fingers. the four middJe pans of Ihose fingers , and the four bottoms of those fingers. Thm 's likely why the number twelve is common in human counting today. Uke the use of the term "dozen," and lhe lwelve hours of a clock. (Source: " Idem. and Information: ' Arno Pen'lias. W.W. Nonon and Compa ny).
To under tand binary numbers, we might firsl ensure Illat we understand decimal numbers. Decima l numbers use a base len numbering syste m. The basic definition of base len is a numbering syslem where the rightmost digit represent the number of ones ( LO~ we have. the nexi digit represents the number of groups of tens (10 1) we have. the next digit represents the number or groups of len tens ( 102) we have. and so on, as illu trated in Figure 1.6. So the digi ls "523" in ba e 10 represent 5* 102 + 2*10 1 + 3*100. Because humans have ten fin ger. they developed and used a ba e ten numbering system . They came up with symbols to represent quan litie ranging from no fingers (0) to all the fin gers but one (9)-lhese are called "ones" rather than "fingers" though. because we aren' t always counting fin gers. To represem a larger quantily than nine one , humans introduced another digil to represent the number of groups of all the fingers. called "ten." NOle thai we don't need a unique symbol for the quantity ten itself. ince that quantity can be represented as one group of ten and no ones. To represent more than nine tens. humans introduced yet another digit, 10 represent the number of groups of len tens. which are called "hundreds." To represent ten hu ndreds, they introduced another digit. called "thousands. " English (as spoken in America) doesn't have a name for a group representing ten thousands. nOr for the group representing ten ten thousand . which is referred to as hundred thousands. The next group is called millions, and further group that are mu ltipl es of one thousand have names too (billions. trillions, quadrillions. etc.). Now that we better understand base ten numbers. we can introduce base two numbers. know n as bi/lary /lllll/b ers . Since digital circuits work with values that are either "on" or "off," such circu its need only two symbols. rather than ten ymbols. Let tho e two symbols be 0 and I. I f we need to represent a quantity more than I. we'll use another digil, whi ch wi ll represent the number of groups of 21 which we'll call two. So "10" in base two represenlS I IWO and 0 ones. Be careful nOI to call "10" ten-in tead. you might say "one-two." If we need a bigger quantity. we'll use another digil. which "ill represent the number of groups of 2 2 , which we'll call four. The weights of each digit in base two are shown in Fi gure 1.7. For example. the number 101 in base IWO equal 1*2 2 + 0*2 1 + 1*_0. or 5. in base ten. In other words. 10 1 can be poken as "one-four zero-two one-one." I t people comfortable with binary might instead ju t say "one zero one." To be "ety lear, you might say "one zero one, base two:' But you should definitely /lOT say "one-hundred ne, base two." 101 is one-hundred one in base ten. but Ihe leftmost 1 does not repre,.;em nehundred in base IWO.
12
1 Introduction
1.2 The World of Digital Systems Knowing powers of two
~ COUNTING "CORRECTL Y" IN BASE TEN. The fJe l Lhill there are name~ for ~omc of the groups in base ten. but 110( o lhcn" prevents many people from
g3i ning an intuitive underslunding of base ten. Further liddi ng to the co nfusion arc the abbreviated names for
gr ups of lens-the numbers 10. 20. 30..... 90 should be ca ll ed One len. two ten. three len..... ninc ten . but instead use abbreviated nam es: one tc n as just "ten:' Iwo tell as " twe nt y:' three len us " thirt y," " .. and nine len as ·'ninety." YOLI can sec how "n inety" is a
I think makes more sense). Thus. the num ber 523
~~:~
Id be spoken as "fi ve- hundred two-ten lhree" rnt~er "five-hundred twenty- three:' I believe Lhat kids
have a harder time learni ng math because ofin thea
confusing number naming-for example. carry g one from the ones column to the tcns"column make~ more sense if the ones column adds ( 0 o n~ ten seven rather than to "seventcen"-the resul ~ obvl ~ u s l y. adds
!-honcning of "nine ten:' Funhcnnore. short names arc also used for the numbers between 10 an d 20. II o;hould be "o ne len o ne: ' but is instead "cleven," wh ile
one 10 Ihe tens column. Learning btnary tS slightly harder for some studenls due 10 a lack of a solid understanding of base 10. caused largely by the naming confusion. Perhaps. when a store clerk tells
19 should be " one ten nine" but is instead "nineleen," Tab le 1.1 indictll es how 10 count "correclly" in b3se ten
you "that will be ninety-nine cents." y~u can co~ecl him by saying "you mean ~ine: ten nme ~ent s . Lf
(where I boldly define "correcll y" us counling the way
enough of us do Ihis. perhaps 11 wtll calch on.
TABLE 1.1 oto 9
,
helps in learning binary:
Counting "correctlv .. in base ten. A s usu:.ll: "zero;' ··one." "two;' etc.
10 10 99
".:" "one 10. 11. 12. , .. 19: "one tcn," "one ten onc... ..one len I wo, .. ten nine" 'ne" 20. 2 1. 22 .. ... 29: "two ten:' "two ten one," "two len two, ... two len nl 30. 40 . ... 90: "three len," "four ten," ... "nine len"
100 10 900
As usual: "one hundred." "two hundred," ... "nine hundred." Even bener wou ld be 10 replace the \ ord "hundred" by "len to the power of 2."
1000 and up
As usual. Even bener: replace "thousand" by "ten 10 Ihe power of 3". "len thousand" by "len to the power of 4:' e IC.• eliminati ng all the names.
as "one zero one in base two equals five in ba e ten."
16
8
2
Figure 1.8 Basc two
num ber
"'y~ l e l11 .
EXAMPLE 1.1
256 512 1024 2048 ...
EXAMPLE 1.2
When converting from binary to decimal , people often fi nd it useful to be comfortable knowing the powers of two. since each Success ive place to the left in a binary number is two times the previous pl ace. In binary. the firs!. righlmost place is 1. the second place is 2, then 4, then 8. 16. 32. 64. 128, 256. 512. 1024. 2048. and 0 on. You might top at this poinl to practice counting up by powers of Iwo: 1,2.4.8. 16.32,64. 128, 256. 512. 1024. 2048, etc .. a rew times. Now. when you see the number 10000 Ill. YOll might move along the number from righ t to lefl and count up by powers of two for each bit to delermine Ihe weight of the leftm ost bit: 1.2,4.8. 16.32.64. 128. The nexl highest 1 ha a weight of (counting up again) 1,2. 4; add ing 4 to 128 gives 132. The next I has a weighl of 2; addi ng Lhat to 132 gives 134. The rightmost 1 has a we ight of I; adding Ihat to 134 gives 135. Thus. 10000 III eq ual 135 in base ten. Counting in binary Count ing from 0 10 7 in binary looks as follows: 000. 001. 010. 011 , 100. 101. 110. III. An interesting fact abo ut binary numbers-you can quickly determi ne whether a binary num ber is odd j ust by checking if the rightmost digit has a I. If the righLmost digil is a O. Lhe number mllst be even, since the number is the sum of even number . Converting between decimal and binary numbers using the subtraction method As we saw earli er, converting a bin ary number to decimal is easy-we j u t add the we ights of eac h dig it having a 1. Converting a decimal number to binary take slightly more effort . One mel hod for converting a decimal number to a binary number that is easy for humans to carry o ut by hand, which we' ll call the sllb/ractioll m e/hod. i hown in Table 1.2. The met.hod starts wiLh a binary number thal is all Os. TABLE 1.2 Subtraction method for converting a decimal number to a binary number. Slep Descripti on
When we are writ ing numbers of different bases and the base of the number is not obv ious. we indicate the base with a subscript, as follows: 101 2 = 5 10 , We mt ght say thiS
o
lJ128
2 4 8 16 32 64
13
,
Note that since bi nary isn' t as popular as decimal. people haven I created short names for its groups of 21. 22, and so on. like they have for groups in base ten (hundreds, Lhousands. millions, etc.). Instead . people just use the equivalent base len name for the group--a sou rce of some confusion to people just learning binary. Nevertheless, tt may sLil1 be eas ier to think of each group in base two uSlllg base 10 names, rather than increasing powers of two, as show n in Fig ure 1.8. Binary to decimal Convertlhe following binary numbers to deci mal numbers: 1. 11 O. 10000. 10000 Ill. and 001 10. 0 12 is jusl 1*2 . or I/ o. . . 110, is 1*2 2 + 1' 2 + 0*20. or 6 10, We mighl lhink of Ihis using the group wetghls shown In Figure 1.8: 1' 4 + 1*2 + 0*1. or 6. 10000, is 1' 16 + 0*8 + 0' 4 + 0' 2 + 0' 1. or 1610, looooi 1h is 1' 128 + 1' 4 + 1*2 + 1' 1 = 135 10, Not ice Ihis lil11e Ihat we didn ' l bother to write O~I th e groups with a 0 bit. 001 102 is Ihe sal11e as 11 02 above - the leading O's don'l change Ihe value.
0. PUllin PUI a 1 in the highesl binary place who e weigh I is less than or equal 10 the c:;;" highest place dec imal number. Updale N Updale the decimal number by Subtntcling the highesl binary place's \\ eight from 0. decimal the decimal number. The new decimal number is lhe remaining quanti£)' to be c:;; " number converted 10 binary. If Ihe updaled deci mal number is nOI zero. return 10 step I.
For example. we can convert the decimal number 12 as shown in Figure 1.9.
1. Put 1 in highest place Try place 16. too big (16)12) Next place. 8. is highest (8<12) 2. Update decimal number Decimal not zero. return to Step 1 1. Put 1 highest place Next place. 4. is highest (4=4) 2. Update decimal number Decimal number is zero. done.
Decimal Binary 12 )( 1 0 0 0
168421
(current value
is 8)
-8 4
1
-4 -0-
1 0
0
168421
(cumm' value IS 12)
Figure 1.9 Converting Ihe decimal number 12 10 binary usi ng the ubtntclIon "lethO
14
Int rodu ction 1.2 The World of Digha l Systems W
e cu n c heck Our wo rk by co nven in " 1100 back to eC 'Il n ,al'. 1*8+ 1*4 +0*2 +0*2. = 12. A s a no th e r example. Figure 1. 10 illustrates the subtrac ti o n method fo r convert 109 t~e d ec ima l number 23 to bin ary. We can chec k our wo rk by co nvertlll g the lesu lt, 101 1 ,
15
d
~ 1. Put 1 in highest place Place 32 too big, but 16 works. 2. Update decimal number Decimal not zero, return to Step 1
1. Pu t 1 in highest place Next place is 8 . too big (8)7) 4 works (4<7) 2. Update deci mal number
23
~ 10
0 00
168421
-16
2. Divide quotient by 2
(current value
is 16)
1 0
0
168421
(current value is 20)
1 0
1. Put 1 in highest place
Decimal nol zero , return to Step 1
Decimal number is zero, done
1 1
0
168421
-2
1
3. Divide quotient by 2 Insert remainder Into the binary number Continue since quot ient (1) is greater than 0
213
4. Divide quotient by 2
2V1 -0 l'
-2
l'
o
Insert remainder into the binary number Quotient Is 0, done
(current value is 22)
Figure 1.11 Converti ng th e decimal num ber 12
10
0
0
21 (current value: 0)
1 0 4 2
0 1
(current value: 4)
1 0
0
8421 (current value: 12)
binary using the divide-by-2 method.
1
EXAMPLE 1.4
1. Put 1 in highest place
Nexl place is 1, works (1=1) 2. Updale decimal number
o
-4
-3-
Decimal number not zero, return to Step 1
Next place is 2. wo rks (2<3) 2. Updale decimal number
2.[6 -6
Insert remainder into the binary number
Continue since quotient (3) is greater than 0
- 7 1 0
~+'J
1. Divide deci mal number by 2 Inse~ rem~inder into the binary number Conllnue since quotient (6) is greater than 0
back to d ecimal: 1* 16+0*8+ 1*4+ 1*2 + 1* 1 =23.
1
0
1
1
168421
-I
(current value
i523)
Convert th e followi ng numbers to bi nary using the div ide-by -2 method: 8. 14.99.
o
Figure 1.10 Conve ni ng the decimal number 23
to
To convert 8 to binary, we start by di vidi ng 8 by 2: 812=4, remainder O. Then we divide the quoti ent , 4, by 2: 412=2. remainder O. Then we divide 2 by 2: 212=1 . remainder O. Finally. we divide I by 2: 1/2=0. remainder I. We stop di vidi ng because the quotient is now O. Combining all the remainders. least sig nifican t.digi t. fi rst, yields the binary number 1000. We can check this answer by mullip lYlllg eac h binary dig it by liS weight and adding the terms: 1*23 + 0*22 + 0'2 + 0'20 = 8. ' To conven 14 tn binary, we follow a similar process: 1412=7. remainder 0.712=3. remainder I. 3/2= I, remainder I. 112=0, remainder I. Combining the rem ainders gi ves us the binary number 1110. Checki ng the answer verifies that 1110 is correct: 1' 23 + 1*22 + 1'2' + 0' 20 = 8 + 4 + 2 + 0 = 1.1. To conven 99 to binary. the process is the arne but natumll y takes more step: 9912=49 remainder I. 49/2=24, remainder I. 24/2= 12, remai nder O. 1212=6. remainder O. 612=3 , remainder O. 312= I. remai nd er I. 112=0. remai nde r I. Combining th e remainders tnge ther gives us the binary number I 1000 1I. We know from Example 1.3 th at this i the correct answer.
binary using the sublIacti on method.
EXAMPLE 1.3 Decimal to binary Convert th e fo llowing deci mal numbers to binary using the subtrac ti on me thod : 8, 14, 99. To convert 8 to binary. we start by putting a I in Ihe 8's place, yieldin g 1000. Since 8-8=0, we are done-the answer is 1000. To co nve rt 14 to bi nary, we stan by pUiting a I in the 8's place (16 is too much). yielding 1000. 14 -8 =6. sn we PU I a I in th e 4' place. yielding 11 00.6 - 4 = 2, so we put a I in th e 2's place, yieldi ng I I 10. 2 - 2 = 0, so we are done-the answer is 111 0. We can quick ly chec k our work by conve rtin g back 10 decima l: 8 + 4 + 2 = 14. To convert 99 to bi nary, we stan by pu tting a I in the 64 's place (the nex t hi gher place, 128. is too bi g-noti ce that being able to count by powers of two is handy in this problem), yielding 1000000.99-64 is 35, so we PU I a I in the 32's place, yieldi ng 1100000.35-32 is 3. so we put a I in the 2's place. yieldi ng 11 000 10.3 -2 is I. so we put a I in the I 's place, yielding th e fina l answer of I 1000 I I. We can chec k our work by conven.ing back to dec ima l: 64 + 32 + 2 + I = 99. Convertin g betwee n decimal and binary numbers using the divide-by-2 method An a lte rn ative approach for co nverting a decimal number to binary, perh aps less intuitive th a n the s ubtrac ti o n method but easier to automate using a comp ute r p rogram , invo lves re pea ted ly dividing th e decimal number by 2-we' ll call this the divide-by-2 m ethod. The rem a inder at each s te p (ei ther 0 o r I) beco mes a bit in the binary numbe r, s tarting from the leas t s ig nifi cant (ri g htmost) digit. For exa mple, th e process of convertin g the dec imal number 12 to binary us ing th e d ivide-by-2 method is show n in Fi g ure 1. 11.
Decimal to binary using the divide-by-2 method
Con ve rting fr om any base to any other base using the di vide-by-n method We have bee n di v iding by 2 in o rder to conven to base 2, but we can u e the arne basi meth od to conve rt a base 10 number to a number of any base. To conven a number from base 10 to base 11. we s impl y repeatedly divide the number by /I and add the remainder to the new base /I number, sta n ing from the lea t s ignifican t digit.
EXAMPLE 1.5
Decimal to arbitrary bases us ing the divide-by-n method Conven the num ber 3439 to base 10 and to base 7. We kn ow the num ber 3439 is 3439 in base 10. but let's use the divide-by", (where n i- 10l meth od to illustrate that the method works fo r any base. We tart by di\;ding 3439 b) 10: 3439/ 10=343, remainder 9. We th en divide the quotient by 10: 343110=34. remainder 3. We do the same with the new quoti ent: 34/3=3. remai nder 4. Finally, we divide 3 by 10: 3/10=0. remainder . Combining the remainders. least signifi ant digit firs t. gives us the base 10 number 3439.
16
1.3 Implementing Digital Systems: Programming Microprocessors versus Designing Digital Circuits
IntrOdu ction . " 1 excepl we now divide by 7. We begin by our calculations we get: 49 117==70, < < , dividing 3439 by 7: 3439n=-191. rematn er -' . 3 In=o remainder I. Thus. 3439 in base remai nder I. 70n= 10. remainder O. Ion = I, remalOder . I ' sull' I*r' + 3*73 + 0*72 + 1*71 To conven 3439 to base 7. the approac h IS Simi ~r. .' . d ? Continuing
7 is 130 12. Checking the answer ve ri fies Ihat we have the corree re + 2*70 = 240 1 + 1029 + 7 + 2 = 3439.
.
d from one base to another by first convening Generall y, a number can be convene n number to the desired base using the that number to ba e ten. then convenm£ the base te clivide-bY-/l method. Hexadecimal and octal numbers. . . . b known as " exadecl/lwl /ltlmbers or Just "ex, are 164 163 162 161 160 Base SIxteen num ers. b . d' 't is also 0 ular in digital design. mainly because one. ase sIxteen Igl. A F . PI P r r base twO di oits making hexadeCImal numbers a Illce eq ulva ent to 'ou " ' . I fi d" t t t . for binary numbers. In base SIxteen , t le rst Igl0 shonhan d represent.llon fif nes-the sixteen sy mbols commonl y used are , 10001010 1111 represents up 10 teen 0 _ . binary I. 2..... 9. A, B. C. D. E, F (so A=ten, B=eleven, C=twelve, D-thlneen, hex binary hex ---+-_.:...E=fourteen and F=fifteen). The next digll represents, the number of 0 0000 8 1000 group of 1'6 1 Ihe next di gil the number of groups of 16-, ebc., as shown 0001 9 1001 . F' I 12 S SAF equals S*162 + 10*16 1 + 15* 16, or 2223 10 , 0010 A 1010 111 Igure . . a 16 d~ d" . b t a 1011 Since one digit in base 16 represents 16 values, an our Iglts III ase w 0011 8 4 0100 1100 represents 16 values, each digit in base 16 represents fo ur dIgIts III base C 5 0101 0 1101 two, as show n at the bOllom of Figure 1.1 2. Thus, to convert SAF I6 to 6 0110 E 1110 binary. we convert 816 10 10002, AI 6 to 10102, and FI6 to 111 .12' resulllllg 7 0111 F 11 11 in 8AF I6 = 1000 101 0 1111 2, You can see why hexadeclll1al IS a popular Figure 1.12 Base sixleen number system. shonhand for binary: SAF is a lot easIer on the eye than 100010101111. To convert a binary number to hexadecimal , we Just substItute every fou r bits with the corresponding hexadecimal digit. Thus, to convert 10 II 0 II 0 12 to hex, we group the bi ts into oroups of four staning from the right, yielding I 0 II 0 110 I. We then replace each group" of four bits with a single hex digit. 110 I is D, 0 II 0 IS 6, and I IS I, resulting in the hex number 16D 16. 8
,
A
F
EXAMPLE 1.6 Hexadec imal to/from binary Conven the following hexadecimal numbers 10 binary: FF. 1011 , AOooo. You may find il useful to refer 10 Figure 1.12 10 expand each hexadecimal digillo four bils. FFI 6 is 1111 (forthe left F) and 1111 (for the righl F), or 11111111 2, 10 1116 is 000 1. 0000. 000 1. 000 I. or 000 1000000010001 2, Don'l be confused by lhe facI that 1011 didn'l have any symbols bUI I and 0 (which makes Ihe number look like a bll1ary number). We said il was base 16, so it was. If we said il was base 10. then 1011 would equal one Ihousand and eleven. AOOOO l6 is 1010, 0000,0000, 0000.0000. or 1 0 I OOOOOOOOOOOOOOO~ . Convert the following binary numbers 10 hexadecimal: 0010. 0111111 0, 1111 00. 00102 is 2 16, o I I I I I 102 is 0 I I I and I I 10. meaning 7 and E, or 7E 16. 1111 00, is II and 1100. which is 00 11 and 1100, meaning 3 and C. or 3C 16. NOlice that we start-grouping bits into groups of fou r from Ihe righl. nOI tlte left.
17
. The subtraction or di vide-by- 16 method can al 0 be used to conven decimal to hexadecul1al, however, convening directly from decimal to hexadecimal can be a bit unwieldy for humans SUlce we are not used to working with powers of sixteen. Instead. it is often qUIcker to conven from dec imal to binary u ing the ubtraction or divide-by-2 method and then conventng from btnary to hexadecim al by grou ping set of 4 bi ts.
EXAMPLE 1.7 Decimal to hexadecimal COIll'en 29 base 10 10 base 16. To perform thi s conversion, we can firs t convcn 29 to bi nary and lhen conven the binary result to hexadecimal .
Convening 29 to binary i straighlforward usi ng Ihe divide-by-2 method: 29/2= 14. remainder I. 14/2=7 . remai nder O. 712=3. remainder I. 312= 1, remainder I. 112=0. remainder I. Thus. 29 is 111 01 in base 2. Convert ing 111 012 10 hexadecimal can be done by grouping selS of four bilS. so 11101, is I, and 1101 2. meaning 116 and D16, or ID I6. Of course. we can use Ihe divide-by-16 method 10 conven directly from decimal 10 bexadecimal. Slarti ng wi lh 29. we di vide by 16: 29116=1 , remainder 13 (DI6). 11 16=0. remainder I.
Combi ning the remainders togelher gives us I D 16 - Though lhis particular conversion was simple. convening larger numbers directly from decimal to hexadecimal can be lime-<:on uming. and lhe two-step convers ion may be preferable.
Base eight numbers. known as oClallllllllbers, are sometimes used as a binary honhand too. since one base eight digit equal s three binary digits. 503 8 equals 5*82 + O*SI +3 *So 323 10, We ca n convert 503 8 directly to binary imply by expanding each digit Into three bits, resulting in 503 8 = 101 0000 II , or 1010000 I !,. Likewise. we can conven binary 10 octal by grouping the binary number into groups o(three bits starring from the right, and then replacing e.ch group with the corresponding octal digit. Thus. 1011101 2 yields I 011 101 , or 135 8, Appendix A di scu ses number represemations further.
=
1.3 IMPLEMENTING DIGITAL SYSTEMS: PROGRAMMING MICROPROCESSORS VERSUS DESIGNING DIGITAL CIRCUITS Designers can implement a digital system for an application using one of tWO common digital system implementation methods-programming a microprocessor or creating a custom digital circuit (known as digi tal design) . As a concrete example, consider a simple application that !Urn on a lamp whenever there is moti on in a dark roo m. Assume a motion detector has an output wire alled a that outputs a 1 bit when motion is detected , and a 0 bit otherwise. Assume a light sensor bas an output wire b that outputs a 1 bit when light i sensed. and a 0 bit othen\ise. And a sume a wire F turns on the lamp when F is 1, and rum off the lamp when O. dra\\ing of the system is shown in Figure 1. 13(a). The design problem i to detennine what goes in the block named Dm'Clor. The Detector block takes wires a and b as inputs. and generates a \'lliue on F. -uch that the light turns on when motion is detected when dark. The Detector :lpplicati n is readil) implemented a a digital system. as the application ' inpull and utpUtf obviousl) are
18
Introduction
1,3 Implementing Digital Systems: Programming Micro processors vers us DeSigning Digital Circuits
. "
' . h A desioner can implement the Detector (li gna !. haVing only two pOSS Ible values eac. 3(b"')) 'no 'J custom di oital cirCUIt block by programming a microprocessor (FIgure I, I or USI ", ' '" (Figure 1.13(c)).
~II
Detector
Digital System
>~
Detecto r
a
Detector
Micro-
----~
(b)
(c)
(b) implementation
Software on Microprocessors: The Digital Workhorse
Desioners that need to work with digital phenomena often buy an off-the-shelf microprocess;r and write software fo r that microprocessor, rather than design a custom dtgttal circui t. Microprocessors are really the "workhorse" of digital systems, handltng most dig it al process ing lasks.
Figure 1.14 Basic microproce sor's in put and output pins.
J US! meallS sl1Ial/
here. The
microproce.uor lerm became
popular il/ Ihe 19805 whell
processors shrank
dOlvlIfrom mulliple cflips to
jusl OIlC. Th e first single-chip microprocessor was the Imel 4004 chip ill 1971.
a and ! b ,
F
Figure 1,13 MOlion-in-lhe-dark-deleclor syslem: (a) sySlem block di agram, using a microprocesso r. (c) implementation using a custom digit al c irc uI t.
"~
Ivhile (1) { PO ~ 10 && ! 11 : 1/ F
PO
~ -- - -- --- ---
A "processor" processes. or tralls/orms, dow. A "m icroprocessor"
shown in Figure LI S. The des igner connects the a wire to the microprocessor input pin 10, the b W, re to Input pin 11 , and output pin PO to the F wire, The designer could then speCIfy the II1structions for the microprocessor by wri ting the fo llowing C code: void rnain() {
(a)
10 11 12 13 14 15 t6 t7
19
A microprocessor is a programmable digital device that executes a user-specified sequence of instructions, known as a prog ram or as software, Some of those instructions read the microprocessor's inputs, others write to the microprocessor's outputs, and other instructions perfo rm computati ons on the input data, Let's assume we have a bas ic microprocessor wi th eight input pins named 10, 11, ..., !7, and eight output pins named PO, PI, .. ., P7. as shown in Figure 1.l4(a), A photograph of a real microprocessor package with such pi ns is show n in Figure L 14(b) (the ninth pin on thi s side is for power, on the other side for ground). A microprocessor-based solution to Ihe motion-in -the-dark detector application is ill ustrated in Figure 1.1 3(b), and a photograph of an actual physical implementation
C is one of several popular lanmotion sensor guages for describing the desired F instructions to execute on the microproce sor. The above C code works as fo llows. The mi croprocessor. after lamp being powered lip and reset, executes the instructions within rna in's cllrl y brackets ( ). The fi rst instruction is "wh i 1e (1) " which simply means to repeat the insrructions in the while's curly brackets forever. Inside the while's curly brackets is only one instruction "PO = 10 && ! 11," Figure 1,15 Physical motion-in-the-dark which assigns the microprocessor's detector implementation using a microprocessor. output pin PO with a 1 if the input pin lO is 1 alld (written as &&) the input pin I 1 is not 1 (meani ng 11 is 0). Thus, the output pin PO, which tums a O --~ the lamp on or off, forever gets 1 assigned the appropriate value based b on the input pin values, which come 0-------' fro m the motion and light sensors. 1 F Fi gure 1. 16 show an example O--~ of signals a, b, and F over time, I I I I 6:00 7:057:06 9:00 9:01 time with time proceeding to the right. As tim e proceeds, each signal Figure 1.16 Timing diagram of motion-in-the-
•
I
20
1.3 Implementing Digital Syste
Introduction wi th lime proceeding
Ihe riohl. and Ihe va lues or digital signals show n by high or ·IS known as a IWll . .llg <> d ' (a and' b) 10 bef Iow I' Ines. lagram . We draw Ihe inpul lines . whalever va lues we walll . bU I Ihen the oUlpul line (F) musl desc ribe Ihe behavIOr 0 Ihe digilal sys lem . EXAMPLE 1.8
10
Outdoor motion notifier lIsing a microprocessor LeI's use th e basic microprocessor of Figure 1.1 4 to implement a 10
PO 11 P1 ~ 12 n P2
13 14
buzzer
sy~ l cm thai sounds a bu zzer when moti on is detec ted at any of Lhree mOlion sensors outside a house. We connect the motion sensors ~o
microprocessor inpul pins 10. 11. and 12. and conneCI OUlpUI pill PO 10 a buzzer (Figure 1.17). (We assume Ihe mOli on sensors and
.g P3 g P4
buzzers have appropri ate elcclro nic interface to th e micro processor pins.) We can then wri lc the foll owing C program :
'"
15 ~ P5 Q 16
P6
17
void main()
P7
( ~Ihile
molion sensor
PO
(1) =
10
(
II
II
II
IlIlel named 'heir t!VO/l,illg 1980S/
12:
90s desktop processors using /llimbers: 80286, 80386. 80486. As pes bc(:ame popular. Intel switched 10 c(lu:hier ,wmes: the 80586 lVas called 0 PemiuIII
Figure 1.17 Motion sensors connected to
mi cro processor.
The progrnm executes the statement inside the while loop repeated ly, That Sla tcmcnt will set
PO 10 I if lO is I sels PO 10 O. EXAMPLE 1.9
01'
(wrillen as
II
in Ihe C language) I I is I or 12 is 1. olherwise Ihe slalemenl
Counting the number of active motion sensors
("pellfa" mealls
5),JollolI'ed by the
In this example. wc'lI usc the basic microprocessor of Figure I 14 to implement a sim ple di gital system th at outputs in binary the number of Illation sensors that presently detect motion , We' ll assume two motion sensors, meaning we'll need to ou tput a two-bit binary number, whi ch can represent the possible counlS 0 (00). I (0 I). and 2 (10). We' ll connecl Ihe mOlion sensors to microprocessor
Pentium Pro. Ihe Penlium II, alld
others, £1'e"llIall)~ the "ames tiomill(IIeti over the nllmbers,
inpul pins 10 and I I and OUlpullhe bi nary number onto outpul pi ns PI and PO. We can Ihen wrile the follOwing C progrzHll:
void main()
.p '. ms. rogrammlllg Microprocessors versus DeSigning Digital Circuits
Designers like 10 use microproce _ sors In their digi tal systems because microprocessors are readily avai lable, Inexpensive. easy 10 program. and ea y to reprogram. II may surpri se you 10 learn Ihat you ca n buy cenai n microprocessor chips for under $ 1. Such microprocessors are found in places lIke lelephone answering machines. mi crowave ovens. cars, IOYs. certain medical devices, and even in shoes with blinking lighl s. Examp les include Ihe 805 1 (ori ginally designed by Inlel). the 68 HC II (made by Motorola). and Ihe PIC (made by Mi croChip). Other microprocessors may cos I lens of do l-
21
(a)
(b)
Figure 1.18 Microproeessorchip packages: (a) PIC and 805 1 microprocessors. costing aboUI S I each. (b) a Pen tiu m proces or with pan of ilS package cover removed. showing the si licon chip inside,
lars: found in pl aces like cell phones, ponable digital assistams. office automation equlpmenl, and med ica l equipmenl. Such processors include the ARM (made by the ARM corporal Ion), Ihe MIPS (made by the MIPS corporation). and others. Other microprocessors, like Ihe well -known Pentium processors from Intel. may cost several hundred dollars and may be found in desklop computers. Some microprocessors may cost s~veral thousa nd dollars and are fou nd in a main frame compuler running perhaps an alrlme reservallon system. There are literal ly hundreds, possibly even thousands, of differem microprocessor Iypes avai lable, di ffe ring in performance. cost. power. and olher melrics. And many of Ihe small low-power processors cost under $1. Some readers of Ihi book may be fami li ar with software programming. others may no\. Knowledge of programmi ng is not essemial 10 learning Ihe material in this book. We wi ll on occasion compare custom digilal circuits with their corre ponding software implememali ons-the ullim ale conclusions of Ihose comparisons can be understood withoul knowledge of programming it elf.
Digital Design- When Microprocessors Aren't Good Enoug h
(
while (J) if ( ! 10 && ! I I) ( P1 = 0; PO = 0 : II output 00 . meaning zero
With microprocessors readi ly avai lable, why would anyone ever need to design new digital circuits, olher Ihan those relatively rew people de igning microprocessors themselve ? The reason is that sofI ware nlnning on a microproce sor often isn 'l good enough for a particular applicalion. In many cases. software may be too slow. Microproce sors only execUle one instruclion (or aI most a rew instructions) at a time. But a custom digital circuit can execute dozens, or hundreds. or even thousands of compUlations in parallel. Many applicalions, like picture or video compression. fingerprim recognition. voice command detection. or graphics display. require huge numbers of computation to be done in a hon period of time in order to be praclical-afler all , who wants a voice-controlled phone thaI requires minutes 10 decode your voice command. or a digilal camera that require 1- minutes t take each picture? In other ca e , microprocessors are too big. or nsume mu h power. or would be too costly, making ustom digital cireuils preferable.
else if( ( 10 && ! ] 1 ) II ( !] O && ] 1 ) ) ( PI = 0 ; PO = 1 : II output 01. meaning one else if (]O && ]ll ( P1 = 1 : PO = 0 : 1/ output 10 . meaning two
n
22
1 Introduction
1.4 About this Book
For the mOlion-in-the-dark-detector application. an ahernati ve to the I.llicroprocesso rbased dc.!\ign lISC!) a custom digital circui t inside the. De~ec1O" ~I ock. A c~~cll.1I IS an lIl~erc~n·t· r I . W Sl desion ·lcII'CUllthat.loreach dlffelent combInauon ne~ 1011 0 C eClnc components. C I11U e' lIch circuit is shown in Fi ure or Input, a and b. gcnerate, the proper val ue on F. One S .g ' 1 1 d 'b I ts ' I n Lilat circuit later. But you've now ' V I . 13( C.) \' C c~cn c Ile componen . , . seen one SImple example of designing a digita l circuit to solve a design problem. The mIcroprocessor also has a circuit inside. but becallse that ci rcuit is designed to execute programs rather Lhan Just cietect 1110tion at ni ght. the microprocessor's ci rcuitml1Y conwin about ten thousa nd components. compared to j ust two components in Ollr custom digital Cl rClI lt. Thus" our custom di gi tal circuit may bl! smaller. cheaper. fas ter. and consume less power than an llTIplemental ion on a microproccs~or.
. ..
.
Many applica ti on use bot h microprocessors and custom dI gItal deS Igns w attam a ~ys t cm th aL ~Ichil!vc~ j u!'.t the right balance of performance. cost, power, Size, deS ign time,
flexibil ity. etc.
EXAMPLE 1.10
DeCIding among a microprocessor and custom digital circuit \VC I11U"" dc~ign a digita l ~y~ t cll1lo conlrol a figiller jet's aircra ft wing. In order to properl y control the aircrafl. the diuital ,ystCIll must execute. 100 li mes per second . .a computation lask th at adjust the wing'S pos it io; ba~\.!d on the aircraft'lj prescnI and desired speeds. pi tch. yaw, and other night fac tors. SllPPO~C we e~til11atc thai software on n microprocessor would req uire 50 ms (milliseconds) for each execlition of the computa ti on uhk. whereas a custom digital circuit would requ ire 5 ms per execution. Execliting the computation task 100 times on the microprocessor wou ld req uire 100 * 50 ms = 5000 ill S. or 5 ... econcis. But we require those 100 executions to be done in I second. so th e microprocc~sor i:.. not fast enough. ExecUl ing the task 100 times with the custom digi tal circuit would
require 100 • 5 111'
= 500 111,. or 0.5 seconds. As 0.5 seconds is less than
I second. the custom
digi tal circuit can !'tali:..!'y the system's performance constraint. We thus choose to implemen t the digita l sys tcm as J c u~tom digital circuit.
EXAMPLE 1.11
Partition ing tasks in a digital camera A digita l Cilmera cap turcs pictures digi tally usi ng several steps. \Vhen the shuller button is pressed, a grid of a few million light-sensitive electron ic clements capture th e image. each elemenL storing a binary number (perhaps 16 bit~) representing the intensity of light hilling the element. The camera Ihen performs several tasks: the cnmera reads th e bits of each of these clements. compresses the tens of millions orbits into perhaps il few mill ion bits. andslOl-es lhe compre ssed bilSas a file in the camcrn's nash memory. among other ta sks. Table 1.3 provides sample task exec ution tim es on an inexpcnsive low-power microprocessor versus a custom digital circui!.
TABLE 1.3 Sample digital camera task execution times lin seconds) on a microprocessor versus a digital circuit, Task
Microprocessor
Read
5
0. 1
Compress
8
0.5
Store
Custom digital circuit
0.8
. We need '0 decide which tasks to Irn~l emcnt on the microprocessor and which to ~mpl e mcnl as a CUstom digital ci rcuit. s U~Jecl to the constraint Ihal we shou ld strive 10 minimize the amount of Custom digital circuitry in order 10 reduce chi C.OSl~. Such decisions are known as parll.. t tO lllIIg. Three panitioning opt ions are hown in Figu re 1.19. I f we implement all three tasks On th e microprocessor th e camera wi ll require 5 + 8 + I = 14 se~ol1d s to take a picture-too much lime for the camera 10 be popular wilh consumers. \Ve cou ld implemelll all the tasks as Custom
digi.al ci rcuits. resulting in 0. 1 + 0.5 + O. = 1.4 seconds. We could ins.ead implement lhe read and compress tasks wilh CUStom digital ci rcuit s. while leaving the store uisk to th e microprocessor, resulting in 0. 1 + 0.5
+ I. or 1.6 seconds. We might decide on this lasl implementation Option. to save COS t without much noti ceable time overhead.
23
Microprocessor (a)
(Read. Compress. andSlore)
(b)
(c )
Figure 1.19 Digi tal camera implemenred with: (aJ a microprocessor. (b) CUStom ci rcuits. and (c) il combination of Custom circuits and a microproces or.
1.4 ABOUT THIS BOOK Section 1.1 di scussed how digital systems now appear everywhere arou nd us and iooificant ly il~pact the way we li ve. Section 1.2 highlighted how learning digital d~ign accompli shes two goals: showing us how microprocessors work "under the hood." and enabling us to implement ystems usi ng custom digi tal circuit rather than or alon2 ide microprocessors to achieve beller implementati ons. This latter goal i becomin2 inc~as ingly significant since so many analog phenomena. like music and video. are becomin2 digital. That section also introduced a key method of digitizi ng analog igoal. namely binary numbers. and described how to convert among decimal and binary numbers. Section 1.3 described how designers tend to prefer to implement digital ystcms by writing software th at executes on a microprocessor. yet designers often use u tom digital circuits to meet an applicati on's performance req uirements or other requirement . [n the remainder of this book you will learn about the exciting and challenging field of digi tal design. wherein we convert desired system funcLionality into a custom digital circuit. Chapter 2 will introduce the most basic foml of digital circuit. combinational circu its. whose ou tputs are simply a functi on of the present values on the circuit"s inputs. That chapter will show how to u e a foml of math ca lled Boolean algebra to de - ribe our desired circuit functionality. and will provide clear sleps for conve-rting Boolean equations to circui ts. Chapter 3 will introduce a more advanced type of ircuit. equential circuits, whose outputs are a function not only of the present input value. but aI 0 of previou input val ues-i n other words. sequential circuits have memory. uch circuits are commonly referred to as controllers. ThaL chapter will show us how t u' another
26
1.5 Ex ercises
Introduction . ' . . etll od: 1. 12 Convert lhe foll owing decimal IHllllbcr::. to binary Ilumbers uSing the dl vlde-by-2 nl
(") 9
J.2J Convert the following hexadecimal numbers to binary: (a) BOC4
1.22 Convcn Ihe following hex adeci mal num bers 10 decimal: (a) FF
(") 19
(b) FOA2
(b) 30 (c) 64
(e) OFIOO (d) 100
(d) 128 . ' . . e l h Od : 1. 1-' Convert the fo llowing deci mal numbers to binary numbers lI smg the c11 vlde-by-2 111
(") 3 (b) 65 (e) 90
(d) 100 . ' . . ? m e l ]1od: 1.15 COllvert th e following decimal numbers 10 blllary numbers usmg the dlv ldc-by--
,
(") 23 (Il) 87 (e) 123 (d ) 101
l.16 Conve rt the followi ng binary numbers to hexadecimal: (") 11110000 (b) 111 11111 (e) 010110 10
(d) 1001101 101101
1.17 COnVl:ft th e foll owing bi nary numbers 10 hexadecimal:
(d) 1101101111100
1.18 COllvert the f llowillg binary numbers 10 hexadecimal:
1.26 Delenni ne the decimal num ber ra nges thal can be represented in bina,). octal. decimal. and number range 0 Ihrough 3 in binary (00 through II ). 0 through 63 in octal (00 through 77), 0 Ihroug h 99 in decimal (00 th rough 99), and 0 through 255 in he,xadecimal (00 through FF). (a) I
(b) 11 00 1000 (C) 10100 100
11'11
1.19 Convert the following hexadecimal numbers to binary: (a) FF
(b) FOA2 (c) OF IOO (d) 100
1.20 Convert the following hexadecirnallllllllber!> to binary:
(d) DEED
(e) 999,999 hexadecimal using the following numbers of digits. For example. 2 digits can represent decimal
(a) 111 00 111
(b) 3FAD
1.25 Compare the number of digits necessary 10 represent the followi ng decimaJ numbers in bioary. octal, decil11111. and hex adecimal representauons. You need nOI determine the actual representations-j ust the number of required dig it s. For example , representing the decimal number 12 requires four di gits in binary ( 1100 is th e aClUal representalion), two digital in oct:JJ ( 14) . twO digils in decimal ( 12). and o ne d igi l in hexadeci mal (C). (a) 8
(d) 1000
(c) 11 110001
(e) 3E2 A
1.201 Conve rt (h e dec imal number 128 to the foll owing number sys tems: (a) binary (b) hex adeci mal (c) base Ihrce (d) base fi ve (c) base fineen
(c) 300
(Il) 10100101
(a) 4F5E
1.23 Convert the rollowing hexadecima l numbers to decimal : (a) 10 (b) 4E3 (c) FFO (d) 200
(b) 60
(a) 11001101
(d) (JIll
].7
(b) 3
(e) 6 (d) 8
SECTI ON 1.3: IMPLEMENTING DIG ITAL SYSTEMS: PROGRAi\(,\IlNG M IC RO PROCESSORS VE RSUS DES IGNING DIG ITAL C IRCUITS 1.27 Use a microprocessor like thai in Figure 1.14 to implement a system that sounds :In aJ3.lTll whenever there is motion detec ted al the same lime in three different roon ~. Each n.'){)m~s mot ion sensor output comes to us on tl wire as a bit 1 meaning motion. 0 meaning no mou(\o. \Ve sound the alann by selling an Output wire "alann" to 1. hm\ the l'Onnt."Ctions tl'l..Uld tn.")nl the microprocessor. and the C code to execute on the micropf"()C"e ·or.
28
Introduction 1.5 Exerc ises . I ent a system th at counts the number of . I hat III . FI gure I, 14 10 nnp em 1.28 Use a mi croprocessor like has a senso r th at o ut put s a 1 .I f a car is cars in a parking 101 wit h seven spaces. Each space h Id be written in binary over three . e The output 5 all prC~l: nl . and thaI outputs a O Qt herWls . d the C code. Hint : use a loop an d an wires. Show the connecti ons with the microprocessor an a 1 if-else state ment or a switch b f cars present. then usc < I i nteger va riable to caunl the nutll er 0
fO nate 3-bit output.
state ment to convert the integer 10 the app P . thn! displays the number . ... I 1410 Implemenl a syslem . d 1.29 Use a microprocessor Itke thai In Figure . . II LEOs 'Irranged III a rowan display There are elg 1 , 1 th LED of people in a wai ting roo m o nlO an • ' . . th at wi ll output a when e I . ped with a sensor < • eight chairs in the wa iting room, eac 1 equip d I number of sealS being occupied, · LED 1"1 viII corres pon 10 11e fi I SCa l is in lise. The number 0 S I \ f l ' h two seats those are), th e r5t two . h · d (regardless 0 1I' 1iC " ed the first three LEDs in th e row will hg t up. For insHlllcc. if two se:lts are OCC Up lC LEDs will lig ht l~ P: if lh~ee seats are OCCUpl i~d the lights will light up incrementall y. Show Regard less of whic h particular seals arc occup c ~ ro ri ate C code. th e connec ti ons with the microprocessor and th l PP P . d I ' d c pIing I orts encrypted Video. an t lal e ry 1.]0 Suppose a pan icul ar TV SCI-lOp box al a hole supp C Th ec uli on limes of each lask on each video frame consists of three sub· tasks A . B. and . e ex I 1S ~o r A 10 I11 S versus 2 . I ' . are 100 ms ve rsus n • a microprocessor versus a custom dl·glla CirCUl i th e microprocessor and f C Panilion Ihe tasks among ms fo r B, and 15 ms ve rsus I ms or . . f Stom di gital circuitry, while custom d igital circ uit ry, sllch that you minimize the amount 0 cu meetin o the constra int of decrypting at least 30 fram es per seco nd. e .. a er tic kets for oaining entrance to base1.31 The owner of a ba ebnll stadium wan Is to ei1mll1a~e p p w tho~e auending the game to ba ll na mes. She would like 10 sell lickels eleclrollicall y and allo . . II . Ihe fin gerprinl e . . TI has two opllons for Instu II1g enter by sc~u1lling theIr finge rpnnt. le owner . h fi erprint recoonition .. yst"m thm Implements L e 1I1g 0 T fi recog nition system, ~e rst opt~on IS a s t: The'second option is a custom di gital circuit using soft ware exec uting on a m,lcroproces.s?r, Th ftware system req uires 5.5 seconds to d' . I ' '1 desig ned specificall y for fi ngerpnm recognition. e so · and costs 550 pe. r unit . whereas th e Iglta ClrCUI recoe· nize an indiv idual'S finge rprmt ' th I requie res 1.3 seconds for recognition and costs S I00 pe' r Ull!'t. The owner wants to ensure d Ih as u . be able 10 enter thestad·IU111 befo re Ihe ga me' starts, Can everyone attend ing the game will needs 10 be ab le 10 suppon 100,000 people enlerin g Ihe sladium wilhin 15 mmules. ompare the two altern ati ve systems in terms of how many people per minute each sys Le~l1 can s~ppon, how ma ny un its of each system would be neede d to support 100000 ' . people 111 15 mmules, and what Ihe overall cost of installation would be for the two competing systems. 1.32 How ma ny possible partiti onings are there 0 f a set 0f lasks where each (ask can be implemen ted on il microprocessor or ilS a custom di gi tal circuit? 1.33 *Wrilc a program th at automati call y partitions a set of 10 tasks among 0 l"e a pnrlllioning approach Ihal makes Some ed ucmed gues,"s. Your program lif..c ly won." I. "': able 10 g uaran lee lhal il find, Ihe "':Sl panilioni ng, bUI il , houl d (I I le"'1 li nd a good parlillorlillg.
29
~ DESIGNER PROFILE
---.:::;:;;:::;::;::::"!!
Kelly firsl became interested in engineering while allending a lalk about engineering at a career rair in hi gh chool. " I was dazzled by Ihe interestin g ideas and the cool graphs." While in college. Ihough. she learned Ihat "Ihere was much more to engineering - ......._ .........__
Ihan ideas and graphs. Engineers apply Iheir ideas and ski lls 10 build Ihings lhat reall y make a difference in people 's li ves, for generat ions to comc." In her first few years as an enginee r. Kell y has worked on a varicty of project "(hat may help numerous individuals," One project was a ventilator system li ke the one mentioned earlier in this chapter. "We designed a new conlrol system that may enable people on ve ntilators to breathe with mOre comfort while still getting the proper amount of oxygen," In addition, she examined alternative implementations of Ihat control system. incl Uding on a microprocessor, as a Custom di gital circuit, and as a combination of Ihe Iwo. 'Today"s lechnologies. like FPGAs, provide so many differenl oplions. We examined several options to see what the tradco ffs were among Ihem. Underslanding the Iradeoffs among Ihe oplions is quite important if we wanl to build the best system possible:' She also worked on a projecl Ihal developed ·'small self-explanalory eleclronic blocks Ihal people could connect together to build useful electron ic systems
involving almoSI any kind of sen or. like motion or lighl sensors. Those blocks could "': used by Jcids 10 learn basic concepls of logic and compUlers, concepts which are quite important 10 leam these days. Our hope is that these blocks will "': used as leaching lools in schools. The blocks can also "': used 10 help adu lts sel up useful systems in their homes, perhap to mOrU lOr an aging parenl, or a child al home sick. The polential for these blocks is greal-il will "': interesting 10 see whal impacl Ihey have:· "My favorite thing about engineering i the variety of skills and creativily invo lved. We are faced with problems Ihat need 10 "': solved. and we solve them by applying known techn iq ues in crealive ways. Engineers must continually learn new [echnologies. hear new ideas. and lrac k current prod ucls, in order 10 be good designers. It's all very exciting and challenging. Each day a( work is diffe rent. Each day is exciting and is a learning ex penence. '·Studying 10"': an engineer can "': a great deal of work bUI it"s wonh il. The key is 10 lay focused, 10 keep your mind open. and to make good use of available resources. Staying focused means to keep your priorities in orderfor exa mple. as a Student. studying Come firsL recreation second. Keeping you r mi nd open mean [0 alway be willing [0 listen to different ideas and [Q learn about ne\llo' technologies. Maki ng good use of resources means to ao g:ressively seek informatio n. from the lnterneL from from books. and 0 on. You ne\ er knO\\ where you ~ goi ng 10 get )our ne'U importrult bi, of info rmation. and you \\ On'l get that infonnarioo un} you seek il:·
c~iieagues.
2.2 Switches
31
Electronics 101
2
You '. re probably fam iliar with the idea of e lectrons, or let's just say charged panicles. fl ow ll1g through wires and causing lights to illu minate or stereos to blast mu ic. An anaJogous situation is Wate r flowin g through pipes and causing sprinklers 10 pop up Or turbi nes to turn . We now describe th ree bas ic e lectrical terms: Although
Combinational Logic Design 2.1 INTRODUCTION of the A dio ita l c ircuit. whose out puts d epend sole ly on the present . .combinatioll .. b circlIit . b t . ". I 's called a combillatiollal circllit. Combll1ali onal CirCUIts are a aS lc u II/PillS va lies / , b . ponantly . I . f di oital c irc uits ab le to imple ment some syste ms. ut more 1m Important c ass 0 ,," f' . T I 's chapter introduce the scrvin o as the basis for more complex classes 0 ClrCLlIlS. 11 . ( des ion"of bas ic combinational c ircuits. Late r chapters will deal with mo re ad ~anced combi na7ion'1 1 c ircu its and with sequent ial circu its. whose outputs depend on t e seqhuedn?re " . UIt. ,s.Inpu ts .Fio (hi story) of va lues . that have appea red at t he CirC " ure 2 . I Illustrates te l -
Voltage is the difference in e lectri c potential between two points. Voltage is measured in volts (V). Conventi on says that the emh. or ground. is 0 V. [nformally, voltage tells us how "eager" the charged panicles on one side of a wire are to get to grou nd (or a ny lower voltage) on the wire's other side. Voltage is analogous to rhe press ure of wa ter trying to flow th rough a pipe-water under higher pressure is more eager to fl ow. even if the wa ter can't actually flow perhap becau e of a closed faucet.
logic gtlles is Optiollal,II/("' )I peoplejilld II basic IIlu/ersflIlldillg satisjies IIIlIch clIriOSilY alld al,..o helps ill I/Iulersullldil/g SOllie of the 1/01/· ideal digital gate behavior later 01/.
Current is a measure of the fl ow of the charged panicles. Informally, current teli us the rate that panicles are ac tua ll y flowing. Currem i analogou to water flowing th ro ugh a p ipe. Cu rrent is measured in amperes (A). or amps for hon. Resistance is the tendency of a wire (o r anything. really) to re i t the flow of curre nt. Res istance is a nalogous to a pipe's diameter-a narrO\ pipe re isIS water fl ow. while a wide pipe lets wate r flow more freely. Electrical resistance i measured in o hms (Q ).
Ference between combinati ona l and seque ntIal Clrcu tts. f"
a b
'"l>
If we know the present input bi t values, then we can determine the output value. If ab=OO. then F is a
tl ab=O l , then F is 0 If ab= l 0, then F is 1 If ab=ll, then F is 0
F
F
We cannot determine the output value
just lrom tooking at the present input values. We must atso know the history 01 input va tues. e.g., il ab was 00 and then 10, F is 0 but il ab was 11 and then 10. F IS 1
Figure 2.1 Combinati onal versus sequential digital circui ts.
The chapter will introduce the basic bu ilding blocks o f combinati o na l c irc uits, know n as logic gates. and will also introd uce a form of ma thema tiCs, known as Boolean a lgeb ra, that is usefu l for designing com binationa l c ircuits.
2.2 SWITCHES Electronic sw itc hes form the basis of all di gital c ircuits, so they make a good sta ning point for the disc ussion of di gi ta l circuits. You usc a type o f switch, a li ght ,witch, whel.lever you turn li ghts on or ofr. To understand a switch, it help, to understand some ba IC e lec tron ics.
30
2 ohms 9V
Cons ider a battery. The panicles at the positive terminal Want to flo" to the negat ive te rmina l. How "eager" are they to flow ? That depends on the \oltage diffe rence be tween the terminals-a 9 V battery'S panicles are more eager to flow than a 1.5 V battery's panicles. because the 9 V battery'S panicles ba\e more potential energy. Now suppose yo u connect the positive tenninai through a light bul b back to the negati ve terminal as shown in Figure 2.~ . The 9 \ ' batteI) will result in more current fl owing. and thus a brighter lit light. than the 1.- V baneI). Prec isely how muc h current will flow is detemlined using the equation:
V = IR (k nown a Ohm's Law) 4.5A
Figure 2.2 9V battery connected to light bulb.
where V is voltage, I is current. a nd R is resistance (in this case. of the light bulb). So if the res istance were 2 ohms. a 9 V battery would re ult in ~.) A lsint'e 9 = 1*2) of c urrent. while a I.) V battery would re ult in 0.75 A. Rewriting the equation as I = VIR might make more inruitive ense--the higher the voltage. the more current: the higher the resistance_ the k -- current. Ohm's Law is perhap the most fundamental equation in electroni s.
The Amazing Shrinking Switch Now back to swi tc hes. Figure 2.3(b) show_ that a s"'it h has three pans-let's call them the source input. the o utput , a nd the ontrol input. The source input has hlgher \OIt3~ than the ou tput. so c un'ent wanlS to flo\\ from the source input through the ,,,it -h It> the OUlpUt. The who le )JlIIlJose of a switch is to block t1U1 current" h 'n th' 'onrrol '{~ th switc h "ofr." and to allow that cmrent to Ilo\\ \\ hen control, 'ts th <\\I(.:h "(,n." F...'r exa mple. when yo u flip a light switch up to tum th' ,,, it-'h on. the ," Itch 'au ,~, t
32
Combinational Logic Design 2.2 Switches
wire so curren t flows. When you flip the Source input wi re to physically touch the output . ' II ates the source input from . . If h 'tch physlca y separ switch down to turn the SWItch a . t e SWI . I'k r cet valve that determi nes the o utput. In our wa te r analogy. the control input IS I 'e a au , whether water fl ows through a pipe. conlrol input
•
source
I \
input
discrete transistor
quarter
(a)
(to see the relative size)
output
con trol input
Ie
vacuum tube
relay
/
"off"
~ MDfBUGGING" In 1945, a moth got stuck in one of the relays of the Mark 11 computer at Harvard. To get the compu ter working properl y again. technicians found and removed the bug. Though the tern, "bug" had been used for decades before by engineers to indicmc a defect in mechanical Or electrical eq uipment. the removal of that moth in 1945 is considered to be the origin of the term "debugging" in computer programming. Technl~.ans taped that moth to their written log (shown in the picture to the s.de), and that moth is now on display at the National Museum of American History in Washington , D.C.
"on"
The machine said to be the world 's first general.purpose computer. the ENIAC (Elec~ trOI1J~ Nu mencal Integrator And Computer), was completed in the U.S. in 1946. ENIAOO
output
contatned about 18.000 vac uu m tubes and 1500 relays. weighed over 30 ton . was I fee l long and 8 feet high (so it would likely not fit in any room of your house. unles you have a n absurdly big house). and consumed 174,000 wans of power. Imagine the heat generated by a room full of 1740 IOO·wan light bulbs. That' hot. For all thaI. E'llAC could compute aboul 5000 operations per second-compare that to the billions of operations per second of today's personal computers, and even the tens of millions of computations per second by a handheld cell phone.
I source
33
input (b)
Figure 2.3 (a) The evolution of switches: relays (1930s), vac uum tubes ( I940s). discre.te transistors ( 1950s). and integrated ci rcuits (Ies) contain ing transistors ( 1960s-present). lC's on gmally held about len lransislors: now they can hold more than a billion. (b) Simple view of n SW Jlch.
Although vacuu m tu bes were faster than relays. they consumed a lot of power. geoerated a lot of heat, and failed frequeJ1lly.
Switc hes are what cause digital ci rcuits to uti lize binary numbers made from ~its the on or off nature of a switch corresponds to the Is and Os in binary. We now dtscuss the evolution of swi tches over the 1900s, leading up to the CMOS tran sistor switches commonly used today in digital circuits.
Vacuum tubes were commonplace in many electronic appliances in the 19605 and 1970s. I remember taking trips to the store with my dad in the early 19705 to buy replacement tubes for our television set. Vacuum rubes sti ll live today in a few electronic de\;c<7' One place you might still find tubes is in electric guitar amplifiers. where the rube unique-sounding a udio amplification is still demanded by rock guitar enthusiasts who want their version of classic rock songs to ound just like the originals.
1930s -Relays Enaineers in the 1930s tried to devise ways 10 compute using electronically controlled sw~ches-s\Vitches whose control input was another voltage. One such swi tch , an electro· magnetic relay like tha t in Figure 2.3(a), was already being used by telephone industry for switching telephone calls. A relay has a control input that is a type of magnet, whtch becomes magnetized when the control has a positive voltage. In o ne type of relay, that magnet pulls a piece of metal down, resulting in a connection from the sou rce input to the output-akin to pulling down a drawbridge to connect one road to another. When the control input re turn to 0 V, the piece of metal returns up again (perhap pushed by a small spring), disconnecting the source input fro m the output. In telephone systems, relays enabled calls to be routed from one phone to another, without the need for those nice human operators that previously would manually connect one phone's line to another.
Jo ck Kilby 01
1940s-Vacuum Thbes
Texas IlIsfmmellls mill Roben No}'ce
Relays relied on metal pans moving up and down, and thus were rather slow. In the 1940s and I 950s. vacuum tubes, shown in Figure 2.3(a) and ori ginally used to amplify weak e lec tri c signals like those in a telegraph , began to replace relay. in computers. Vacu um tubes had no moving pans, so the tubes were much faster than relays .
1950s-Discrete Transistors T he invention of the transistor in 1947. credited to William Shockley. John Bardeen. and Walte r Brattain of Bell Laboratories (the research am, of AT&n. resulted io mailer and lower-power computers . A solid·state (discrete) transistor. hown in Figure 1.:(a). uses a small piece of silicon. "doped" with some extra materials. to create a wit h. inee these switches used "solid" materials rather than a vacuum or even moving pans io a rein}. the} were common ly referred to as solid·state transistors. Solid· tate transi tors were maller. c heaper. fas ter. and more reliable than rubes. and became the dominant mputer swit h in the 1950s and I 960s.
01 Fojr"hild
.
SemicOIu/lictors
lire often credited
1I';,h ellch/IO"'·lIg illriept'lIdt'lIIly im't'lIled rhe I e.
1960s-lntegrated Circuits The invention of the illtegrated circuit (IC) in 195 reall) Ie\ luti nized computing. An Ie. n.k .a. a chip. packs numerou tiny tran$i'tor.; on a fingernail·sized pi f :ili o. So instead of 10 transistors requiring 10 discrete ele troni mponc.>nt> n} our lx>ani. 10 transistor.; can be implemented on one component. the ·hip. Figure _.:\3) .. \\ . a picture of an IC thut ha$ a few million transistors. Though earl} I ,fe3tured < nl_ t us f
I
34
Combinational Logic Design
2.3 The CMOS Transistor
lransistors. improvemen ls in IC technology have resulied in nearly ONE BfLLlON tran· sistors on a chip loday. IC lechnology has shrunk transislors down 10 a tota lly dIfferent scale. A vacu um lUbe (aboul 100 mm long) is 10 a modem IC transislor (aboul 100 nm) as a skysc raper (aboul 0.5 km) is 10 Ihe Ihickness of a credi l card (aboul 0.5 mm). I've been worki ng in Ihis field for IWO decades. and Ihe amounl of transIstors on a chip slill amazes me. The num ber I bill ion is bigger than mosl of us have an intuilive feel for. Th ink of pen nies, and consider Ihe volume Ihal I billion pennies would occupy. Would Ihey fil in your bedroom? The answer is probably no (unless you have a really huge bedroom), since a Iypica l bedroom is aboul 40 cubic meiers, while I billion pennies wou ld occupy aboul 400 cubic melers. So you would need aboul 10 bedrooms, roughly Ihe size of an el1lire house, packed from wall to wall , floor 10 ce iling, wi th pennies, 10 slore all Ihal money. And if we Slacked the pennies, Ihey would reach nearly 1000 miles imo Ihe sky-for comparison. a jel fli es at an allilude of about 5 mi les. That 's a lot of pen ni es. BUI we manage to fi l I billion lransislors onto si licon chips of jusl a few square cemimelers. Truly amazing. The wi res thai connecl all those transistors on a chip, if straightened into one straight
~
35
HOW 00 THEY MAKE TRANSISTORS SO SMALL? USING PHOTOGRAPHIC METHODS
If you look a pencil and made Ihe smallest dOl Ihat you could on a sheel of paper. Ihat dOl'S area would hold many thousands of transi stors on a modem sil icon chip.
How can chip makers create such liny transistors? The
key lies in photographic mel hods. Chip makers lay a special chemical OnlO the chip, special because Ihe chemical changes When exposed 10 light. Chip makers Ihen shine Iighl through a lens Ihal focuses the lighl down to ex tremely small regions on the chi p-si milar to how a microscope' lens ICls us Sec li ny things by focusing light. but in reverse. The chemical in Ihe small illu mi nated region changes. and lhen a solvent washes away th e chemical-but some regions stay because of
the lighl that changed thaI region. Those remaining
regions form pans of transislors. Repeating this proces over and over again. with different chemicals at different steps, results not only in transistors. but also wires connecting [he transistors. and insuJators preventing crossing wires from touching.
Photograph of a Pentium processor's silicon chip haviflg millions of lraflsislors. Acltlal si:e is about I em each side.
wire. wou ld be several miles long.
IC Iransistors are much smaller, more reliable, fasler. and less power-hungry than discrele lransislors. Thus, IC lransistors are now by far the mo t com monly used switch in computing.
ICs of the early 1960s could hold tens of transistors, and are known today as small. scale il1legrati on (SS/). As transistor sizes shrank. in the late I960s and early I970s, ICs cou ld hold hundreds of transistors, known as medi um-scale integration (MS/). The 1970s saw the developmem of large-scale integration (LS/) ICs with thousands of transistOrl;, while very- large scale integrat ion (VLS/) chips evolved in the I980s. Since then, ICs have cominued to increase in their capacity, to around I billion transistors. To calibrate your underst:lI1ding of thi s number. consider thai the first Pentium microprocessor of the early 1990s required only aboul 3 million transistors, and some popular but relatively small microprocessors require only about 100,000 transistors. Many of today' high-end chips Iherefore comai n dozens of microprocessors, and can conce ivably comain hundreds of the relatively small microprocessors (or just one or two big microprocessor ). IC density has been doubling roughly every 18 months since the I960s. The doubling of IC densi ty every 18 months is widely known as Moore's Law, named after Gordon Moore, a co-fo under of [ntel Corporat ion, who made predict ions back in 1965 that the num,ber of componenls per IC would double every year or so. At some point, chip makcrl; won t be able 10 hnnk transIstors any fun her. After all . the transistor has to at least be
~ A SIGNIFICANT INVENTION We now know lhal lhe inven tion of the transistor was the sian of the amazing computation and communication
revolutions thaI occurred in the laller half of Ihe 20th century. enabl ing us 10 loday do Ihings like see the world On TV. surf Ihe web. and lalk on cell phones. Bul Ihe Implications of the transistor were not known by mOSI
people at Ihe time of its invenlion. Newspapers did nOl headline the news. and mosl stories Ihat did appear predlcled "mply Ihal transislOrs would improve things like rad,os and heari ng aids. One may wonder whal recently invented bUI unnoti cd lechnology mighl SIgnificantly Change Ihc world once again.
D
wide enough to lei electrons pass through. People have been predicting the end of Moore's Law for over a decade now. but transistors keep shrinking. Not only do smaller transistors and wire provide for more functionality in a Chip. but they also provide for Faster circuits. in pan because electrons need not travel as far to get from one transistor to the next. This increased speed is the main reason why personal computer clock speeds have impro ed so drastically over the past few decade. from kilohem frequencies in the 1970 to gigahenz freq uencies in the early 2000 .
2.3 THE CMOS TRANSISTOR The most popu lar type of IC transistor is the CMOS transi tor. Although a detailed e.~pla nation of how a CMOS tran istor works is beyond the cope of this book. nevertheless. I've found that a simplified explanation seems to satisfy much curiosity. A chip is made primarily from the element silicon. A hip. also known as an integrated circuit, or IC, is typically about the size of a fingernail. Even if you open up a computer or ot her chip-based device. you would not actually see the ilicon chip, inee chips are actually inside a larger. usual ly black. protccti"e package. But )OU ""'nainl) should be able to see those black package. mounted on a printed ireuit board_ in ide a variety of household electronic devices. Figure 2.4 illustrates a cross section of a tiny pan of silicon hip. howing the ' ide view of one type of CMOS transistor-an nMOS trnnsistor. The trnnsistor has the thre..> parts of a switch: ( I) the SOl/ree input: (2) the output. which is ailed the drain. I suppobecau e electric panicles flow to the drain like water Hows to 3 drain: and (3) the :onO'OI input. which is ca lled the gate. I suppose because the gate blocks the current Ho\\ like a gate bl ocks a dog from e caping the ba kyard . A hip maker o-eates the soun-e and drain by injecting cenai n elements into the -iii on. Figul'e _..! al'o 'ho\\ _ the el 'O'Onic s)mool of an nMO transistor. Suppose the drain was onne 'ted to a slllall po -ithe ,oltagc (Illodem t 'ho'iogi: use about I or 2 ) knO\\~l as the "power suppl):' and the source \\:l> X'nn ·ted thn.'\U.gh
36
2 Combinational Logic Design A positive
... aHracts electrons here, turning the channel between Source and drain into a conductor.
vol tage here ..
2.3 The CMOS Transistor
nMOS~ gate--jl
~
{
conducts
37
~
~l
does not conduct
(bJ
(aJ
PMOS~
,"'-4,
Figure 2.4 CMOS transistors: (aJ transistor on silicon. (b) nM OS tran sistor symbol with indicati on of conductin g when
~
'4
l
does not conduct (c)
'-4\J conducts
gate; I. (c) pMOS transistor symbol condu cts when gate; O. a resistor to grou nd. Current would thus want to Row from drain to source, and on to gro und . (Note: unfortunatel y, conve ntion is that current How is de fined using positive cha rge, even tho ugh ac tuall y negati vely charged electrons are fl ow ing-so you may notice that we say current fl ows from drain to source, even though e lecLrons flow from source to drain .) However, the silicon channel between source and drain is not normally a cond uctor, or in other words, the channel is normall y an in sula tor. We can think of an insul ator as a n extremel y large resistance. Since I ; VfR, then I will essentiall y be O. The sw itc h is off. The really inte resting thing about silicon is that we can c hange the chan nel from a n ins ul ato r to a conductor just by applying a sma ll positive voltage to the ga te. Th at ga te voltage doesn' t result in cu rrent fl ow from the ga te to c hannel , beca use o f the s ma ll insulator (ox ide) between the ga te a nd the c hannel. But, that gate vo ltage does create a posi ti ve electric fie ld that a ttrac ts e lec trons, whi c h have a negat ive c harge, fro m the larger silicon region into the channe l regio n-a kin to how yo u can mo ve paper clips on a tab letop by mov ing a magne t under the tab le. When e nough e lectrons gather into the chan nel, the cha nne l all of a sudde n becomes a co nd uctor. A co nd uctor has ex treme ly low resistance, so c urren t flow s a lmost free ly betwee n drain and source. The sw itch is now on. As yo u can see, s ili co n is not quite a conduc tor but no t quite a n in sulator ei ther, mlhe r re presenting something in betwee n- he nce the te rm semicOllducl or. An a na logy to the cu rrent trying to cross the channe l is a pe rson try in g to cross a ri ve r. No rma ll y, the ri ver mi ght not have e nough stepping sto nes for the pe rson to be ab le to wa lk across. But if we could altract stones from othe r pa rt o f Ihe river into one pathway (the c hannel), the pe rson could eas il y wa lk ((cross the river (Figure 2.5).
Figure 2.5 CMOS transistor operation analogy-A person may not be able to cross a river until JUSt enough stepping stones are attracted into one pathway. Likewise, electrons can 't cross the channel between Source and drain until just enough electrons are attracted into the channel.
We mentioned that nMOS was one type of CMOS transistor. The other type is pMOS . A pMOS is similar except that the channel has the opposite functionality-the chan nel is a conductor norma ll y, and then doesll'r conduct when the gate has a positive voltage. Figure 2.4 shows the e lectronic sy mbol for a pMOS transistors. The use of these two "complementary" types of transistors is where the C comes from in CMOS. The MOS stands for Metal Oxide Semiconductor, but the reasons for that name go beyond the scope of thi s discussion .
~ SILICON VALLEY, ANO THE SHAPE OF SILICON Silicon Valley is not a city, but refers to an area in Northern Califomia. about an hour south of San Francisco, that includes several cities like San Jose, Mountain View. Sunnyvale, Milpitas, Palo Alto. and others. The area is heavily populated by computer and other high-technology companies, and to a large extent is the result of Stanford University's (located in Palo Alto) effons to attract and create such companies. What shape is silicon? Once. as my plane arri ved in Silicon Valley, the person next to me (who happened to be a college senior studyi ng Computer Science) asked "What shape is a silicon anyways?" I eventually rea li zed he thought silicon was a type of polygon. like a pentagon or an octagon. Well . the words do sound similar. Silicon is not a shape. but an element. like carbon or aluminum or sil ver. Silicon has un atomic number of 14, has a chemical symbol of"Si:' and i the second most abundan t element (next to oxygen) in the earth's crust, found in items like sand and clay. Silicon is lIsed to make mirrors and glass. in nddition to chips.
In fact. to the naked eye. a silicon chip actw!lJy looks like a small mirror.
A d rip packagt w;lh its chip coveT ~mQ\-nJ-."ou see rhl! mirror-like SiliCOII chip ill lite ctnur.
C'lUt
38
2 Combinational Log ic Design
2.4 Boolean Logic Gates- Building Blocks for Dighal Circuits
2.4 BOOLEAN LOGIC GATES- BUILDING BLOCKS FOR DIGITAL CIRC UITS You'vc seen that CMOS transistors can be used to implement switches on an incredibly tiny scale. However. trying to usc switches as Our building blocks to bui ld complex digital ctrcults is aki n to urying to use small rocks to build a bridge. as illustrated in Figure 2.6. Sure, you could probably bui ld someth ing from rudimentary building blocks, bu t the building process would be a real pain . Switches (and small rocks) are just too low-level as buildi ng blocks.
Figure 2.6 Hav ing Ihe ri ght build ing blocks can make all the difference when building thi ngs.
Boolean Algebra and Its Relation to Digital Circuits Fonunately. Boolean logic gates help us in the design task by representing digital circuit bu ilding blocks that are much easier to work with than switches . Boolean logic was developed in the mid- 1800s by the mathematician George Boole. not to bui ld dig ital circuits (which weren' t even a glim mer in anyone's eye back then), but rather as a scheme for u ing algebraic methods to formali ze human logic and thought. An algebra is a branch of mathematics that uses letters or sy mbols to represent numbers or values, where those letters/symbols can be combined according to a set of known rules . Booleall algebra uses variables whose val ues can on ly be 1 or 0 (representing true or false, respectively) and whose operators, li ke AND, OR , and NOT, operate on such variables and return 1 Or O. So we might declare variables x, y . and z, and then say th at Z = x OR y , meaning z is 1 only if at least one of x or y is 1. Likewi se. we might say z = x. AND NOT(y). meaning z is 1 only if x is 1 ;lI1d y is O. Contrast Boolea n algebra with Ille regular algebra you 're familiar wi th from perhaps high school, in which variabl e va lues could be integers (for example), and operators cou ld be addition, subtracti on, and multipli cation. The basic Boolean operators are AND, OR. and NOT: A D return. 1 if both its operands are 1. So the result of a A D b is 1 if both a ~ 1 and b= 1, otherwise the result is O.
OR returns 1 if either or both of its operands are 1. So the result of a OR b is 1 the following cases: ab=OI , ab= 10, ab= 11. Thus, the only time a OR b IS 0 IS when a b-O O.
111 any.or
NOT returns 1 if its operand is O. So NOT(a) return 1 if a is O. and returns 0 if a IS 1. We use Boolean logic operators all the time in everyday thought such as in the statement "I'll go to lunch if Mary goes OR John goes, AND Sally does ~ot go." To represent thIS uSll1g Boolean concepts, let F represent my ooing to lunch (F-l means I'll go to lunch , F=O means I won ' t go). Let Boolean variables m, j, and 5 represent Mary, John. and Sally each going to lunch. Then we can translate the above English sentence into the Boolean equation:
F - (m OR j) AND NOT (s)
One thing we can do is determine the value of F for different values of m. j . and 5: • m=I , j=O, 5-1 ~ F = (l OR 0) AND NOT(l) • m=I , j=I , s=O ~ F = (lOR 1) AND NOT(O)
- -.._
--
= 1 AND 0 = 0 = 1 AND 1 = 1
In the first case, I don 't go to lunch; in the second, I do. A second thing we could do is apply some algebraic rules (which we'll discuss later) to modify the original eq uation to the equ ivalent equati on:
F - (m and NDT(s») OR
(j
and NOT(s»)
In other words, I'll go to lunch if Mary goes AND Sall y doe not go. OR if John goes AND Sally does not go. That statement, as different as it may look from the earlier ooe. is eq uivalent to the earlier one. A third th ing we could do is formally prove propertie about the equation. For example, we could prove that if Sally goes to lunch (5=1). then I don't go to lun b (F=O) no matter who else goes, using the equation:
F - (m OR j) AND ND T(I) - (m OR j) AND 0
0
No matter what the values of m and j . F will equal O. Noting all the mathematical activities we can do using Boolean equati ns. you can stan to see what Boole was trying to accomplish in formalizing human reasoning.
EXAMPLE 2.1 Converting a problem statement to a Boolean equation Convert Ihe following problem st3lemenlS 10 Boolean equation. u ing 10rs. F shou ld equal I only if: I. a is I and b is 1. A llslI'er: F = a A D b
2. ci lher of a or b is 1. AllslI'er: F = a OR b
~.
39
So F wi ll eq ual 1 if either m or j is 1. and s is O. ow that we've translated the English sentence into a Boolean equation. we can perform several mathematical activities with that eq uation.
DOD The right building blocks ...
"ob==O J" ij' s/rorrlullld fo r "0= 0. b=I."
roo
R. and :O\OT
('3-
40
Combinational Logic Design
2.4 Boolean Logic Gates- Building Blocks for Digital Circuits
J. both a and b are not O. AIl.\,wer:
(a l Oplion I: F; NOT(a) AND NOT(b) tbl Oplion 2: F ; a OR b 4. a is 1 and b is O. AII.m·er. F ; a AND NOT(b) .
atemcnts
J
Convert the followin g English prob em 51
"
. (0
Boolean equati ons:
d h
.
r ifhiah heat
IS
sensed an
ys tcm is set to enabled.
I CS
"
d F rep _
I A fire sprinkler system should spray wale . o . d " e represent "enabled, an . Answer: LeI Boolean variable h represent "'ugh heat IS sense .
.
,. TI
resent "sprayln g wate r.
quation is' F; hAND e.
len all e .
.
haken or the door is
.
bl d and eilher Ihe car IS s
, A ca r alarm shou ld sound if the alann I S e lla e . I "car 'IS shaken " d represent ., . bled" S rcprcsen , opened. AIIslI'er: Lei a re present alarm IS ena" ' i n is' F = a AND (s OR d). .. . ' ~d " and F represent "alarm sounds. Then an equat 0 .
_..
door ISopcne . ' . or d ro resenlS "door is closed" inslead of open (al Alternali vely. assunllng Ihal our door sens p blain the following equation : F; ( mc~ning d=l when the door is closed, 0 when open), we 0 a AND (s OR NOT(d)).
EXAMPLE 2.2 Evaluatin g Boolea n eq uations
f . bles a b Evaluale Ihe Boolean equalion F ; (a AND b) 0 R (c AND d) for Ihe given values 0 vana " C. and d: a=I, b=I , c-1. d- O. AIISII'er. F = (1 AND 1) OR (1 AND 0) a=O . b=1. c=O, d=I. AIISII'er. F a-I. b- 1. C= l.d =l. AIISh'er. F
(0 AND 1) OR (0 AND 1) ( 1 AND 1) OR (1 AND 1)
1 OR 0
1.
o OR
0
O.
1 OR 1
1.
One might now be wondering what
SIUlIIlIOfl,
by,he
1\'0)', ;.roI50
co".ridered the fa/hero! illfimllorioll theory dill' /0 "if later l1'ork 0 11 diXllal commlmic(J/WII .
Boolean algebra has to do with bui lding circu its using switches. In 1938, an MIT orad uate student named Claude Shannon ~vrote a paper (based on hi s Masters thesis) describin o how Boolean algebra could be applied t~ swi tch-based circuits, by showing that "on" switches could be treated as a I (or true). and "ofr ' switches as a 0 (or fal se), by connecting Ihose switches in a certain way (Fi oure 2.7). His thesis is widely considered as ~he seed that developed into modem dioital design. Since Boolean algebra comes w~h a rich set of ax ioms, theorems, postulates, and rules, we can use all those things to manipul ate digital circu its USing algcbra. In other wo rds:
Boolean algebra (mid-1800s)
Switches (1930s)
j !
Shannon (1938)
~
oro
gate
10
refer
"'ogic gOle."
/0
a
Let's first implement Boolean logic gates using CMOS transistors. and then later we' ll show you how Boolean algebra helps bui ld better circuits. You really don ' t hove to understand the underlyi ng transistor implementations of logic gates to learn the digital design methods in the rest of this book, and in fact many textbooks omit the tranSistor discussion entirely. But an understanding of the underl ying transistor implementation can be quite satisfyi ng to a student, leaving no "mysteries." Such an understanding can also help in understanding the nonideal behavior of logic gates that one may later have to learn to deal with in digital design. We ' ll start by using "I " to represent the power suppl y's voltage level, which today is usually arou nd I to 2 V for CMOS technology (e.g., 0.7 V, or 1.3 V). Let"s use "0" to represe nt ground. Note that we could have chosen any two symbols or words. rather than "I -and "0," to represent power and ground voltage levels. For example, we could bave used " t rue" and " f a 15 e," or " H" and "L." Remember that the "1 '- does nO! nece sarily correspond to I V, and the "0" does not neceSSari ly correspond to 0 V. In fact each usually represents a voltage range, like "1" representing any VOltage between 1.2 V to 1.4 V_
Symbol
For telephone switching and other
electronic uses Showed application of Boolean algebra to design of switchbased circuits
Truth table
NOT
OR
~
y 0 0 0 0 1 0
Figure 2.7 Shan non applied Boolean .. algebra 10 swilch-based circuils. p~vld ll1g a form al basis 10 digital circuil deSign.
1
1 0
Figure 2.8 Basic logic gales symbols, trulh lables, and transislor circuits: (a) NOT (i nverter) gate. (b) 2-i npul OR gate, (c) 2-input AND gate. Warning: rea l AND and OR g",es arell " aClually buill this way, but ra th er in n more complex manner-sec Section 2.8.
AND
xV- F ;D-F ;D-F xF xF o
Digital design
We ca n build circuits by doing math.
-... - -
Earlier we said a "gate" was the .flilitch c:ofllrol iI/put of a CMOS tralls is to r, but fl OW we're tlllkiflg about "logic: gates." III all ulI/orluI/ate Iwming similarity, the sallie \.... (gate) refers to two different things. D Oli '/ worry /h ollgh; (I/ter Ihe "ext sec/io l/, we '/I jus t be /I sing the wo rd
To bui ld digital circuits that can be manipulated using Boolean algebra, we tirst implement the Boolean operators AND, OR, and NOT using small circuits of switches, and we call those circuits Boolean logic gates. Then, we fo rger obour swirches_ and instead use Boolean logic gates as Our building blocks. Suddenly, we have the power of Boolean algebra at Our fingertips when deSigning more complex circuits! This is akin to first asse mbling rocks into three shapes of bricks, and then building structures like a bridge from those bricks, as illustrated in Figure 2.6. Trying to build a bridge from small rocks is much harder than bUilding a bridge from the three basic brick shapes. Likewise, trying to build a moti on-in-the-dark circui t (or any digital circuit) from switches is harder than building a circuit from Boolean logic gates.
Boole's intent: formalize human thought
That 's an ex tremely powerful concept. We' ll be building circuits by doing math throughout this chaptcr.
..
41
AND, OR, & NOT Gates
Transistor circuit
F
(a)
(b)
y
~
0
1
0
0
0
42
2 Combinational Logic Design 2.4 Boolean Logic Gates- Building Blocks for Digital Circuits
NOT Gate I s be the oppos ite, or inverse, A NOT gale has an input X and an output F. F should n way We can bu ild a NOT C • • I ' called an /IIver a f X-lor thI s reason. a NOT gate IS common) . F' ler . ? 8(a) The tri anole at . s shown In IOllfC _ . ,. co gate using one pMOS and one nMOS transIstOr, a of' l ower supply which .. e voll '.0. aoe a lIe p ents ground , which the top of Ihe transistor circuit represents the POSII1V we represent as 1. The seri es of lines at the battorn of Ihe ClfCUlt" repres11 onduct ,but the , we represe11l as O. When Ihe .1I1put x .IS 0, Ihe pMOS transIstorh'WkI cf the circuit as a . not. as shown .111 F,gure . ?_. 9( a) . In Ih a t case nM OS will , we can t In. a1 the nMOS will . fl'O m 1 to F, so when x =0, F =1. 0 n tIIe a ther hand when X IS , e can think of " wife 29(b) . . In that. case, F' w 28 called a conduCI, bu t Ihe pMOS wil. l not, as shown .In FIgure " the ClfCUlt as . a Wife from 0 10 F, so when X= 1, F-- O. The table 111 ' Iguret .t ,for every Irlllll lab le, summarizes the NOT gate's behavior by listing the gate s au pu poss ible input.
o~
F
Figure 2.11 OR gate conduclion paths when: (a) one inpul is l. and (b) bOlh inputs are O.
time
Figure 2.12 OR gate liming diagram.
Figure 2.9 In ve rt er conducti on paths when:
D-
(a) the input is O. and (b) the input is 1.
F1 ~ o - - - - -...
time
Figure 2.10 Inverter liming diagram.
Figure 2. 10 shows a liming diagram for an inverter-when the input is 0, the output is 1; when the input is 1, the output is O. Electrically, combining pMOS and nMOS in this way has the benefit of low-power. otice in Fi gure 2.8(a) th at fo r any value of x, either the pMOS or nM OS tranststor wi ll be nonco nducting. Thus (conceptually), current can never now fl'Om the power source to ground- thi s feature will also be true fo r the AND and OR gates we' ll define next. Thi s feature makes CMOS circuits consume far less power than other transistor techn ologies, and part ly exp lains why CMOS is the most popular logic gate tranststor technology today. OR Gate A basic OR gale has two inputs x and y and an OUIPUI F. F should be 1 only if at least one of X or y is l. We can bui ld an OR gate using two pMOS transistors and two nMOS trans istors, as shown in Figure 2.8(b) (although we will see in Section 2.8 th at OR gates are actually built in a more complex manner). If al least one of X or y is 1. then we get a connecti on from 1 to F, but no connection from 0 to F, so F is 1, as shown in Figure 2.II(a). If both X and y are 0, then we get a connection from 0 10 F, but no connection from 1 to F, so F is 0, as shown in Figure 2.11 (b). The truth table for the OR gate appears in Figure 2.8(b).
43
. Figure 2.1 2shows a timing diagram for an OR gate. (See Section 1.3 for an introductIon to lIm1l1g diagrams.) We set inputs x and y to each possible combination of values. and show that F wlil be 1 if ei ther Or both inputs is a 1. Larger OR gates, having more than two inputs, are also pos ible. If at least one of the OR gate 's inputs are 1, the output is l. For a three-input OR gate. the tran iSlOr clrcuit Figure 2.8(b) would have three pMOS transistors on top and three nMOS transi [Ors on the bottom, instead of two transistors of each kind .
AND Gate A basic AND gale has Iwo inputs x and y and an outpul F. F should be 1 only if both x and y are l. We can build an AN D gate usi ng two pMOS transi stors and two nMOS transistors, as shown in Figure 2.8(c) (again, we will see in Section 2.8 that AND gates are actually built in a more complex manner). If both x and y are 1. then we get a connection from power to F, but no connection from ground to F, so F is l. as hown in Figure 2. 13(a). If at least one of x or y is 0, then we get a connection from ground [0 F. but no connection from power to F, so F is 0, as shown in Figure 2.13(b). The truth table for the AND gate appears in Figure 2.8(c).
x~JLJ
~~
F
0----1'
Figure 2.13 AND gate conduction paths when: (a) all inpuls are l. and (b) and input is O.
time
figure 2.14 AND gate timing di:'lgram.
Figure 2. 14 shows a tim ing diagram for an AND gate. We set input$ \ and) to a h possible combination of va lucs. and show that F \\'ill be 1 onl) if both inputs :II\' a .
- - - - - -- - -- - ._-44
,-
, 1 onl y if 'ble The output IS aroer AND oates, having more than twO inPhu ts, are P sO t ~~lcir~uit Figure 2. 8(b) wo uld L • " " . . ut AND oate. t e transl . tead of '111 the inputs are 1. For a three-tnp d h " nMOS transistors on the bOllom , tnS ;,ave three pMOS transistors on top an tree twO transistors of each ktnd.
2.4 Boolean Logic Gates-Building Blocks for
Combinational Logic Design
Building Simple Circuits Using Gates Detector
a -,.- - --1
EXAMPLE 2.5
how how to build
:%, ;0-, (3)
examp les.
Convert the following equation to a circuit:
F :
a AND NOT( b OR NOHe)
We start by drawing F on the ri ghi, and then worki ng backwards toward ',he inputs. (We ~ould instead start by drawing the Inputs on (h.c left and work ing toward the output.) The equation for F
ANDs IWO ilems: a. and the OUtpUI ~f a NOT. We thus begi n by draw ing the CIrCUit of Figure 2.. 15(a). The NOT's inpul comes from an OR of Iwa Items: b. and NOT(C). We th us complete the drawtng tn Figure 2. 15(b) by includi ng an OR gate and NOT
(b)
Figure 2.17 Using multiple-input AND gates: (a) using 2-input AND gates. (b) using a 3-input AND gate.
-i>D-F (3)
,~' Figure 2.t5 Building the circuit for F: (a) partial, (b) complete.
The same approach applies to OR gates. For example. F = a OR b OR e "auld typically be implemented using a single three-input OR gate. We now provide examples tarring from Eng lish problem de criptions. which we convert to Boolean equations, and then fi nally implement as a ci rcuit.
EXAMPLE 2.6 Seatbelt warning light Suppose you
Want
to design a system for an au tomobile Lhal
illuminates a warning light whenever the driver's seatbelt is not fastened and the key is in the ignition. Ass ume the followiog sensors: a sensor with output S indicates whether the driver's belt is fastened (5 = 1 means the belt is fastened ). and
gate as shown .
EXAMPLE 2.4 M e examples converting Boolean equations to gates
. or . . s to circui ts bUilt from Fioure 2. 16 provides IwO more examples of convertmg Boolean equ~ lI on e fi ure shows the lo:ic gates. We agai n start fro m the output and wo rk backwards to th~ tnputs. ~~e I~ced each gate " a ndenee between equa ti on operators and gates. and the order In which p corresp in the circui t. F = (a AND NOT(b)) OR (b AN D NOTlc)) 2 1 3
F
a sensor with output k indicates whether the key is in
the igni tion (k =1 means the key is in).
Assume the warni ng light has a single input wthaI i1luminales the light when w is I. So the inputs to our digital system are 5
and k, and the Outpul is w. wshou ld equal 1 when both of the fOllowi ng occur: 5 is 0 and k is I. Let's first write a simple C program executing on a microproce sor to solve thi s design problem. If we connect S
to 10, k to n, and I. to PO, then Our C code inside the C program's main () function would be: wh i 1 e (1) I PD - ! 10 && I I :
(3)
(b)
Figure 2.16 Examples of conve ning Boolean equations to circuits.
45
Figure 2. 17(a) shows an implementalion of the equation F = a AND bAND c. using two-input AND gates. However. deSigners would typically instead implement such an equation using a single threetnput AND.gate, shown in Figure 2. 17(b). The function is Ihe same. but the three-input AND g3le uses fewer tran IStOrs, 6 rather than 4 + 4 =8 (as well as having Ie s delay-more on delay later). Likewise, F = a AND b AND c AND d would typically be implemented u ing a four-input AND gate.
.. bl k f om transistors, we now s F' Having bu il t logic gate butldtng ~Ic ~ r Recall the digi tal system example of Igure use ful circ ui ts from those bUlld tng oc s. t'on and b=O meant dark, so we . d ark de tector. a= l meant 010 Ih , . erter to get NOT ( b ) , and I 13 the mo ti on-tn-the. . d F - a AN D NOT(b). We can connect b throug an tnv . F The resulting circuit wante . AND oate whose output IS . '" . We now provide more ect the result along with a tnto an conn I 13(c) to the left for conve ntence. appears .111 F'19ure . , shown again ....
EXAMPLE 2.3 Convertin g a Boolean equation to a circ uit with logic gates
Dig~a l Circuits
Using AND and OR gates with more than two inputs
The code repeatedly checks the sen ors and updates the warning lighl. Now leI's write a Boolean equlllion describing a ircui[ implementing the design: w - NOT( 5) AND
46
2 Combinational Logic Design
.
lete the
.
ccd earlier. we can eas il y cam p Usi no the AND and NOT logic gales that w~l1ltrod~ ld connect ing the resultin g NOT(s) and ' n ' f ~ur first system. by con necting s to a N? ~3te, [
~e~~o:~~ inputs of a 2-input AND gate,. as shO\~n l~h:'~~r~Cu~: I ~~ a timing diagralll, we can set :~~ Figu re 2. 19 provides n IImmg dwgram or
draw the ou tput line to match the Clfeu
whatever values we want. but theOn \V~,;~U~~ then 10. then 11. The onl y time that the . I h figure we set 5 and k to . t , function. n t c . ' . 0 d k ' 1 as shown in the fi gure. output \'1 wi ll be 1 IS when S IS an IS . inputs
a
to
Inpuls
kl~
BeltWarn
o
5 1
0
_ _ __
J
OulpUIS
wl~ o ..
warni ng cireui !.
fu~her
L.et·s
ex.tend th e previous example. Automo_
biles tYPically IIghl up all their warning lights when you first lurn the key. so yo u can check that all the
BeltWam
wa~,"g IJ g,hts are working, Assume that Our sys tem
receives an Input t that is 1 for th e first 5 seconds after a key is inserted into th e ignition, and 0 afterward (don't worry aboui who Or whal sets t in thai way). So we wan! '1=1 when p=l and s =D and k=l , OR when t =1. NOle that When t =l . we illuminale the light, regardless of the values of p, s, and k. The new circuil equation is:
w
=
(p AND NOT (s)
AND k) DR t
Figure 2.22 Extended seat belt warning ci rcuit.
The circuit is shown in Figure 2.22.
Some circuit drawing rules and conventions There are some rules and conventions thaI designers commonly fOllow When drawing circuits of logic gates: Logic gates have one or more inputs and one outpul, bUI we typically don ' l label each gate's inpUlS or output. Remember that the order of the inputs inlo a gate doesn'l impact the logical behavior of the gale.
We stated earli er that logic gates are more approp riate than transistors as building blocks for desionin o digital Clrcutts. Note, however, that the 100 i; oates are ultimately implemented " as shown I.n . F'Igure .-:??O For using trans"istors, ' _
w
C programmers, an analogy IS Ihal w rltmg soft-
ware in C is easier than wri ting 10 assembly. even though the C ultimalely gets implemenled using asse mbly. Notice how much less mlUltlve and less descripti ve is Ihe tran s l slor-bas~d circuit in Figure 2.20 than the equi valent logiC gate-based circuil in Figure 2.18. Figure 2.20 Seat belt warning
EXAMPLE 2.7 Seat belt wa rn ing light with driver sensor
Seat belt warning light with initial illumination
ti me
Figure 2.19 Timing diagram for seatbell warning circuit.
Seatbelt
Figure 2.18 Seat belt
2.5 Boolean Algebra
EXAMPLE 2.8
circuit usin g transisto rs,
Each wire has an implicit direction. going from one gate's Outpul to another gate's inpuI, but we typiCally don' l draw arrows showing each direction.
no
yes
=D- D-
A single wire can be branched OUI inlo two (or more) wires going 10 multiple gate inputs-the branches have Ihe same value as the si ngle wire. But two wires can NOT be merged into one wire-whal wo uld be the value of that one wire if the incomi ng IWO wire had different values?
Let 's extend the previous example by adding a sensor. wi th ou tput p. that detects whether a
perso~ IS
aClUally sitting in the dri ver's seat, and by
ehang~ng
the system 's behavior
LO
BellWarn
on ly illuminate the warning
when a person is detected in the seat (p=l) . So the new ci rcuit equation is:
w-
P AND NDT(s ) AND k
In this case, we need a 3-input AND gate. The cireuil is shown in Figure 2.2 1. Be aware thaI the order of the AN D gale's inputs does not matter,
Figure 2.21 Seal be ll warning circuit with person senso r,
2.5 BOOLEAN ALGEBRA Logic gales are lIseful for implementing circuits. bUI equations are bener for manipulating circui ts. The algebraic tools of Boolean algebm enable us to manipulate Boolean equations so we can do th ings li ke simplify the equations. check if two equati as are equivalent, find the inverse of an equation . prove properties about the equati n . et '. Since a Boolean equation consisting of AND. OR. and 'OT opemti n an be straightforwardly transformed into a circuil of AND. OR. and 'OT gate' . manipulating Boolean eq uations can be con idered as manipulating digital circuils. Well informally introduce some of the most u 'eful algebraic I' f Bool an a lgebra . API endi x A provides a fOrlnal definition of B lean algebr.l.
47
48
2.5 Boolean Algebra
2 Combinational Logic Design
TABLE 2.1 Symbol
Notation and Terminology d 'b' n o Boolean equati ons. We' ll . d linolooy fo r escn I " I" book We now define some notation an tem use these definitions extensively throughout t 1e .
(J
Name Parentheses NOT
Operators tors in equatio ns is cumbersome. Thus, Boolean Writing out the AN D, O R and NOT opera . . f those operators. _, I 'whic h o ne peaks of as algebra uses si mpler notauon or . .. ' or a. We I use a , "NOT (a)" is typIca ll y wn tten as a I t of a or the illl'erse o f a . . k 1 as the comp emell . "a prime." a ' IS a lso ' noWI ' fi ' 11y 'Intended to look similar to . "a + b " spec l C,I f "a OR b" is typica ll y wntten as :, b'" ve n referred to as the slim 0 . I loebra. a + IS e II b" lhe addition operator III regu ar a 0 " b" is usually spoken of as a or . . a and b. a + . . "* b" or "a. b." specifically Intended to look "a AN D b" is typ Icall y wntten as a. I Ige bra and even re fe rred to as . I' . operator \0 regu ar a J ..." ~ h sim ilar to the multlp Icatlon . I b a we can even wnte a b ,or t e t as In regular a ge r , . I d b are separate va riabl es IS c ear. the product of a and b. Jus f and b as lon o as the fact that a an ". prod uct 0 a . Of" d b" or even just as . a b. "a *b" is usually spoken 0 as a an . . h otations for Boolean operators, but the above nota. s like ly due to the Intenuonal MathematiCIans often use ot er n tions seem to be the most popular among englnee;o;' b simil ari ty of those operators wi th regul~r algea:~~;:xaampie of: Usi ng the simpler notallon, our ear ler se
w = (p AND NOT(s) AND k) OR t could be rewritten more conci sely as:
w = ps ' k
+ t
which wo uld be spoken of as "w equals p s prime k, or I." EXAMPLE 2.9
Speaking Boolean equations Speak the fo llowi ng equations: I. F = a' b'
2. F :::
a +
+ e. Allswer: "F equals a prime b prime or c." b
*
c ' . Answer: "F equals a or band c prime:'
Convert the fo llowing spoken eq uations into wti ucn equations: I. "F equals a b prime c prime." Answer: F = a b ' e' .
2. "F equals abc or d e prime." Answer: F = a be + de'. Th rul:
les o f Boolean algebra require that we evaluate expressions using Ihe precedence
~at * has precedence over +, that complementing a v:triablc has precedence over *
d that we of course compute what's in parentheses first. We can make the earlter d+ an • an .. . , r II " w _ (p * (5') * equation'S order of evaluation explICIt uSlOg parentheses as 0 OWS. k) + t. Table 2. 1 summarizes Boolean algebra precedence rule, .
49
Boolean algebra precedence, highest precedence first
AND
+
OR
Desc ription Evalullle expressions nested in parentheses fi rst
Evaluate from left to righl Evaluate from left to right Evaluate from lefl to right
Conventions Although we borrowed the multiplication and add ition operations from regular aJoebra and even use the terms sum and produ ct, we dOli '! say "times" for AND or "plus" fo~ OR. Dtgl ta l. deSIgn tex tbooks typicall y name each variable u ing a single character. bec~use uSlOg a slOgle charac ter makes for concise equations like the equations above. We II be WfltlO g many equations, so conci eness wi ll aid understanding by preventing equations that ~rap across multiple lines or pages. Thus. we'l l usuall y follow the conventIOn of uS lOg slOg Ie charac ters. However, when you de cribe digital systems using a hardware description language or a programming language like C. you hould probably use much more deSCriptive names so that your code is readable. So in tead of u ing " s " to represeot the o utput of a seat-belt-fastened ensor, you might instead use " SeatBel tFastened." EXAMPLE 2.10
Evaluating Boolean equations using precedence rules Evaluale the following Boolean equations. ass uming a=l, b=l. e - D, d=l. J. F = a * b + C. Answer: * has precedence over +. 1 ) + 0 = (1) + 0 = 1 + 0 = 1.
0
we evaluate the equation as F ::: (1 '"
2. F = a b + e . Allswer: the problem is identical to the previous problem. using the hortband notation for *. a b ' . Answer: we first evaluate b' because OT has precedence O\'er AND. resulting in F = 1 * (1 ' ) = 1 * (0) = 1 * 0 = D.
3. F
4. F = (ae) ' . Allswer: we first evaluate what is inside the parentheses. then \\e :"OT the result. yielding (l *0) ' = (0)' = 0' = 1. 5. F = (a + b ' ) * c + d ' . Alls,,·.r: The parentheses h"e highest preceden e. Inside the parentheses. NOT has highest precedence. So we evaluate the parentheses pan !IS ( 1 l ' 1 (] + (0» = (] + 0) = 1. ext. * has precedence O\er +, yielding (] ~ 0 - l ' ( 0) + 1 ' . The NOT has preceden e over the OR. gi"ing (0) + ( I' ) = ( 0) _ = 0 + 0 - O. Variables, Literals, Terms, and Sum of Products Le t's define a few more concepts, u ing the e 'ample equation: F ( a . b. e)
abc' + ab + c.
a' c
Variable : A variable represen ts a quantil) (0 or D. The abo\e equJtit>n h ,three variables: a . b. and c . We typically USe \:uiables in Boolean <'quation, to repn'sent the inputs of our system ometimes \\e e'\plicitl) li,t" fun,'u n', \arlabl , as above ("F (a. b. c) = ..... ). Other times we omit th e'Pli~it Ii,t (" F _ ..... \.
50
2 Comb inational Logic Design
2.5 Boolean Algebra
. ble in either true or complemented Literal: A literal is the appearance of a v~n ab ' a b c ' a, b, and e . form. The above eq uati on has 9 literals: a .' e, T'h ' b 'equat ion has four . a product of hterals. e a ove Prodllctterm : A product term IS . f d t terms is known as terms: a' be, a be ' , a b, and e. . . as an OR1I1" 0 pro uc SlI m-oJ-Prodll cts: An eq ual10n wntten quation for F is in sum-of. f d f n The above examp e e , bei ng 111 sum-o -pro ucts . on . . II in sum-of-products form: producls form. The follow1l1g equations are a
i
a + a' = 1 a * a' = 0 This also makes intuitive sense. Regardless of the value of a, a' is the opposite. so yo u get a 0 and a 1, or you get a 1 and a O. One of (a, a ') will always be a 1. so ORlllg them (a+a ' ) must yield a l. Likewise, one of (a, a ' ) will always be a 0, so AND1I1g them (a*a') must yield a O.
abc + abc ' a b + a ' e + a be h ve ' ust one literal). a + b ' + a e (note Ihat a prod uct term can a J . ' SUIn -of-products form: The fo llowing equal10ns are alI NOT 111
+ b)e (a b + be) (b + c)
Let's now apply these basic properties to some digital desi!m examples to see how these 0 , propertjes can help us.
(a
(a') ' + b a(b + e(d + e)) (ab + be) '
Some Properties of Boolean Algebra I bra. Assume a, b, and e are Boolean We now li st some of the key ru les of Boolean age variables, which each hold either the value of 0 or 1.
Basic Properties The followin g properties, known as postu lates, are assumed to be true:
51
Makes intuit ive sense right? OR ' . 0 . . 1I1g a with (a+o) Just means that the result will b h .. , . e*w atever a IS. After all , 1+0 is 1, while 0+0 is O. Likewise, ANDing a with 1 (a 1) results 111 a. 1 *1 is 1, while 0*1 is O. • Complement
EXAMPLE 2.11
Applying the basic properties of Boolea n algeb ra Use Ihe properties of Boolean algebra for Ihe foll owing problems: Show Ihal abc ' is equ ivalenllO c ' ba . The commutative property allows us 10 swap the operands bein. ANDed, so a*b*c' a*e ' *b = c ' *a*b = c ' *b*a = c ' ba . Show thai abc + abc ' = ab . The firsl di slributive property allows us 10 factor out the a b tenn: abc + abc' a b (e+c ' l. Then, the compie men I property allow us to replace the c+c' by 1: a b (c+c ' ) = a b ( 1 ). Finally. the identity property allows us to remove the 1 from the AND lerm:ab(1) = ab*1 = abo Show that Lhe equati on X + x ' Z is equivalent to X + z.
• COlllmutative
a + b a * b
=
b + a
=
b * a
This property should be obvious. Just try it for different values of a and b. • Distriblltive
a * (b + c) = a * b + a * c a + (b * c) = (a + b) * (a + c) (litis aile is Irick)'!) Careful , the second one may not be obvious. It 's different than .regular algebra. But yo u can verify that both of the distributive properti es hold Imply by evaluating both sides for all possible values of a, b, and e. • Associative (a + b) + c = a + (b + c) (a * b) * c = a * (b * c) Again, try it for different values of a and b 10 see Ihat this holds. • Identity o + a = a + 0 - a
1
* a
~
a * 1 - a
The second distributive property (the tricky one) allows us to replace x+x' Z by (x+x' )*(x+zl. The complement property allows us to replace (x+x' ) by 1. and the identity property allows us to replace 1*( x+z) by X+Z.
EXAMPLE 2.12 Simplification of an automatic sliding door system Suppose you wi sh to des ign a system to conlTOl an
aUlomatic sliding door. like one ~l at might be found at a grocery slore's entrance. An input p lO ou r system
indicates whether a sensor detects a person in front of the door (p= I means a person is detected). An input h indicates whether the door should be manually held open (h =1) regardless or whelher a person is detected. An inpul C indicate whether the door should be rorced to stay closed (like when the store is closed for business)-c = 1 means the door shou ld SlOy closed. The latter two wou ld nomlally be set by a manager with the Figure 2.23 Initial door opener ircui!. proper keys. An OUlput f opens the door when f is l. We want to open the door if the door is set to be manunlly held open. OR ir the door is nOi set to manually held open but a person is detected. However. in either ase, we nl~ open the door if the door is not set lO stay closed. \Ve can tmnslate these requirements into 3 Boolean equurion as: f - he ' + h' pc '
52
Combinational Logic Design
he ' + h'pe' e ' h + e 'h'p e ' (h + h ' p) e ' ( ( h+h ' ) * (h+p) ) e ' ((l)*(h + p» e ' (h+p)
(by the commutative property) (by the first distribu ti ve property) . I (by the 2nd distributive property-tncky one ,) (by the complement propert y) (by the identi ty property)
Note that th e simpler equation still makes intuitive sense-we open the door only if the door is not set to stay
DoorOpener
• Idempotent Law a + a a * a -
• Involution Law (a ' ) ' - a Again, fairly obvi@s, If a is 1, the first negation gives 0, while the second gives 1 aga in . Ltkewlse, If a tS O. the first negation gives I, while the second gives 0 agai n.
• DeMorgall 's Law (a + b) ' - a'b ' (ab) ' = a'
menting thi s equation is shown in Figure 2.24. Thu s. by
Simplification of logic circuits will be the focus of Section 2. I I .
figure 2.24 Simplified door opener circuit.
Equ ivalence of two automatic s li di ng door systems Suppose yo u found a reall y chea p device for automatic sliding door systems. The device had inputs e . h. and p and output f , as in Examp le 2. 12, but the device's documen tati on satd that. f
=
e ' hp + e ' hp' + e ' h ' p
Does that device do the same as that in Example 2. J 2? One way to check is = =
e 'hp + e ' hp' + e ' h'p e ' h(p + p') + C'h'p e ' h(l) + e ' h ' p e 'h + e ' h'p he' + h'pe '
(by (by (by (by
~Ions intUIti vely here, Consider ( a + b)' = a' b ' . The left side will only be 1 tf (a + b) evaluates to 0, which only occurs When both a AND b are 0 meanina a ' b' - the right side, Likewise, consider ( a b)' - a' + b'. The left ide only be 1 if (a b) evaluates to 0 , meaning at least one of a OR b muSt be O. meaning a' + b ' - the right s ide. DeMorgan 's Law can be stated in Englisb as follows: The complement of a sum equals the product of the complements: the complement of a product eq ua ls the sum of the complements. DeMorgan's Law i WIdely used, so take the ttme now to understand it and to remember it.
will
Let's apply some of these additional properties in more example.
EXAMPLE 2,14 Applying the additional properties (0
see if we can manipu-
late the above equation into the equation in Example 2.12:
f f
+ b'
Thes~ are. not as obvious. Their proofs are in Appendix A. Let's consider both equa-
appl yi ng the algebraic properties. we obtained a simpler ci rcuit. In other words, we used math to simplify the circuit.
a a
Again, this should be fairly obvious. If a is 1 1+1-1 d 1*1-1 hil'f a' 0 O+O ~ O and 0*0-0. ,an , weI IS.
closed (e ' ), AND either the door is set to be manua ll y held open (h) OR a person is de tected (p). A circuit imple·
EXAMPLE 2.13
53
2.5 Boolean Algebra
.' h'· "" ( on as in Figure 2.23. \Ve could bui ld a ci rcuit to lI11plemcnt ( IS cqua.l .' . d 'b'd earl 'ler Looki ng al the equa. . the properties escn l: ~ . . . 'ow let's manipulate the cquttllon lISlI1g . h b"" ble to simplify th e rema lnmg tion we believe we call factor Oul the c ' . We might 1 el~ ca e " "h+'h ' p" part toO. Let's try some transformations. fi rst factonng out
the distributive propert y) the complement property) the identity property) the commutat ive property)
That's the same as th e origi nal equation of Example 2. 12. so the device should work for us. Additional Pro perti es Let 's consider some add itional propenies. whic h happen to be known as theorems becau e they can be proven using the above postu lales:
• N ull elements
a + I - 1 a * 0 - 0 These sho uld be fairly obvious. I OR anything i, going to be anything is going to be 0,
1. while 0 AND
Convert the equation F = a b (e +d ) into sum·oF-products fonn. The distributive property allows us to "multiply out" the equation to F = a be Convert th e equation F
=
a bd.
wx (x ' y + zy ' + xy) into sum-of.productS form. and make
any obvious simplifications.
The distributive property allows us to "multiply out" the equation: wx (x ' y+zy' T y) = wxx ' y + wxzy ' + wxxy. That equation is in sum-of·products form. The complemen! property allows us to replace wxx ' y by w*O*y. and the null element property means thO! w*O*y = 0, The idempotent property al lows us to replace wx xy by wxy (because xx = Xl. The res ultin g equation is 0 + wxzy' + wxy - wxzy' + w y. Prove tha t x ( x ' + y ( X ' +y . ) ) can never evaluate to I. Repeated application of the first di tributive property yields: xx' +xy ( '+y') - x • + xy x ' + xy y , . The complement property tells us that X ' -0 and yy '-0. ~;elding + O*y + x*O. The null element property leads to 0 + 0 + O. \\hich equals O. Thus. the equation always evaluates to O. regardless of the a tunl \'a1ues of x and y. Determine the opposite function of F = ( a b' + e l. The desired fun ction is G = F' = (ab' +e ) ' . DeMortlan's Ul\\ ,i elds G a ' , * e', Applying DeMorgan's Law again to the firs t term-) ields G ~ ( a'·.-( b' 1 ' e ' . The involution property yields (a' + b ) ~ c ' . Finall). the dlstributh. prope~ yie lds G - a' c ' + be ',
54
2 Combinational Logic Design
2.6 Representations of Boolean Functions
~ YOUR PROBLEM IS MY PROBLEM
. raft lavatory sign EXAMPLE 2.15 Applying DeMorgan ,s Law .In an alrc .
~s
. 'Iled sioo indlcatCommercial ai rcraft Iypica ll y have ,an 'II I ~ J1lm. .:= se an airin£! whether a lavatory (bathroom)
IS
available. Suppo t
c~ft has three lavalorics. Each lav:llory has a sensor ~u ~u 1 if the lavalory door is locked. 0 otherwise. OUf circuli .
(linD
'0
WI
from those sensors. as
0
have three inputs. a. b. and c. camino . 'cd (whether shown in Fiourc 2.25. If (lilY lav:llory door IS un lock. .
55
Figure 2.25 Aircraft lavatory sign block.
The use of Boolean algebra for digital design is an example of ~l e powerful general concept of mapping one problem to another. By mapping a new problem (digital desig n) to an old problem (logic representation). the SOlutions (Boolean algebra) to the old problem can
"shou ld I1lul11lnate one. two. oreall three doors ~lre un lk oc ed) , \\1,; 1
be applied to the new problem. Immediately. the new problem can benefit from perhaps decades of work of solving the old problem. Mapping one problem to another is extremely common in engineering. especialJy in computing. Afler all, why reinvent the wheel?
the "Available" si!!.Jl by setting the ci rcuit's output S to .
\\l~th' th is understanding.
we recogni ze that the OR fu nc-
tion suits the problem. as OR ou tpu tS 1 if any of ,its i n~~ts are
" 1 We beglll 1. regardless 01. how many II1P.UtS ~re. '. ~ an 0 equation fo r S. 5 should be 1 If a IS 0 OR b IS 0 OR c . wnun o
Saying a is 0 is the same as sayi ng a
I.
Circuit
Su ppose your autommic door Contro l has an input with the opposite polarity as what we expect: 0 means open th e door, while 1 means close. \Ve can compUle the function 9 lhat opens the door. and simplify tha t func ti on, as fo llows:
a
Thus. the equatIOn for
9 9 9 9 9
5 is: S-a '+ b ' +c ' \Ve tran slate Ihe equation to Ihe ci rcuit in Figure 2.26. \Ve can apply DeMorgan's Law (in reverse) 10 the equation by noting th ai (a be) a +b +c so we can I
(by sub tituting the equation for f) (by DeMorgan's Law) (by the Involution Law) (by DeMorgan 's Law)
replace the equation by:
= (abc) ' The circuit for that equation appears in Figure 2.27.
:$5Cf
2.6 REPRESENTATIONS OF BOOLEAN FUNCTIONS A Booleall jUllctioll is a mapping of each possible combination of values for the function's variables (t he inputs) to either a 0 or 1 (the output). An example of a Boolean funcrion described in regu lar English is a function F of variables a and b. such that the fun ction out pu ts I when a is 0 and b is 0, or when a is 0 and b is 1. There are e\'eraJ bener representati ons than Engli sh for de cribing a Boolean function. including equati ons, circu its, and truth tables, as shown in Figure 2.28. Each repre emarion has its own advantages and di sadvantages, and each is useful at different times during design . Yet all the representations, as different as they look from one another. represent the very arne funct ion. It 's like how there are different ways to represent a particular recipe for chocolate chip cookies: wri tten words, pictures, or even a video. But no matter how the recipe is represented, it 's the same recipe.
Figure 2.27 Circuit after applying DeMorgan's Law.
EXAMPLE 2.16
Proving a property of the automatic sliding door system Your boss wants you 10 prOl'e lhal the automati c sliding door circuit of Example 2. 12 ensures th:t the
door will stay closed when the door is supposed to be forced to stay closed. namely,when c- 1. [f the function f = c ' (h+p) describes the sliding door, you can prove the door wil l stay closed (f=O) using propenies of Boolean algebra: f = C ' (h+p) Let C = 1 (door forced closed) f 1'(h+p) f O(h+p) f Oh + Op (by the distributive prope rty) f 0 + 0 (by the nu ll elements propenyl f = 0
Therefore, no matter what the va lues of hand p, if c= 1, f wi ll eq ual O-thc door will stay closed.
EXAMPLE 2.17 Automatic sltding door with opposite polarity In Example 2. 12, we computed the function to open an automatic sliding door as: f-c'(h+p)
English 1: "F outputs 1 when a is 0 and b is 0, or when a is 0 and b IS 1:' English 2: " F outputs t when a is O. regardless of b's value."
(a)
o
I
Figure 2.28 Seven
1
I 0
representations of th e very
Truth table
F (b)
same function F(a.b): (a) nvo English descriptions, (b) two eq uations, (c) two circuils, (d) a truth table.
a~F~
/~
~~ ~ 1 1 0
I 0
(d)
56
2 Combinational Logic Design
2.6 Representations of Boolea n Functions
Equations One way to represent a Boolean function is by using an equation. An eqllatioll is a Il) . ' 'b' all) ematical statement equatll1g one ex pressIon with another. F ( a , b) = a + a ' b .' an example of an eq uation. The right-hand side of the equation is often referred to as IS expressioll . wh ich evaluates to either 0 or l. at) We've seen Il,at differe11l equations can represent the same function. The eqUa . F(a . b) = a ' b' + a ' b represents the same function as does the equation F ( a , b )tll)ll. a ' . BOlh equations pcrfonn exactly the same mapping of the input values to output values '" pick any input va lues (e.g .. a=O and b=O). and both equations map those II1put values tl) ------same output value (e.g .. a =0 and b=O would be mapped to F= 1 by either equation). One advantage of an equation as a Boolean functi on representation compared other representations is that we can easil y manipulate an equation using propertie tl) Boolean algebra, enabling us to simplify an equation. prove that twO equation s repre:eI)f the same func!lon. prove propertIes about a function, and more. I)t
th~
Circuits A second way to represent a Boolean function is using a ci rcuit of logic gates. A c;r is an interconnection of components. Because each logic gate component has a Cll;, . f ' I .' Pre defi ned mappmg a Input . va ues to output values, and because wIres Just tran smit tl)e'va lues unchanged. a cIrcuIt descnbes a function. ItWe've seen that differe11l circu its can represent the same function . The two circu its' Figure 2.28 both represent the same function F. The bOllom circuit uses fewer gates b II) the function is exactl y the same as the top circuil. ' Ut One advantage of a circuit as a Boolean function repre entation compared to Otl)er representa!lons IS that a CIrcuit may represent an actual physical implementation I)f Boolean function. and ultimatel y our goal is to implement digital circuits physical! a Another advantage IS that a CIrcuit drawn graphically can enable quick and easy corn y. hension of a function by humans. pre_
Truth Table A th ird way to represent a Boolean function is usin o a trllth table. A truth table's left side lists the input variabl es, and shows all possible valli e cOlllbillatiolls oj th ose illPlIts, with
Inputs a b
o o
Output F
0
one row per combination, as shown in Figure 2.29. A truth 1 o table's ri ght side wou ld then li st the function 's output va lue (l or 0) for the row's particul ar co mbination of input values, as was shown in Figure 2.28(d). Any function of two variabl es figure 2.29 Trulh lable wi ll have those fou r input combinati ons on the left side. Mfucture for a twoPeople usuall y list the inpu t combinations in order of input funclion Fen.b), increasing binary val ue (00=0,01= 1,10=2,11 =3), as we've done above, though strictl y speaking. we could list the combi nations in any order as long as we li sted all possible combi nations. For any comb ination of input va l ue~ (e.g., a-O, b-O). we merely need to look at Ihe corre, ponding vaJue in
_
the oUlput column (i n the case of a=O b= :>7 determ1l1e the function 's output. , 0 , the OUtPUt shown in Figure 2.28(d) is 1 ) to FIgure 2.30 shows the truth tabl fu nc t'lon , and a four-input function e structure s ~or a tWO-input functi on a th . . ' ree-IOpUt a b 0
o o
1
o (aJ
F
a b c 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 (b)
Figure . 2.30 Trut h table structure for: (a) • two-Input functIOn F(. ,b). (b) • th ree-input rullCbtlon F(. ' b.c).' an d (c. ) four-input function F( . a·l,c,d)· Defining. specific function would In.vo ve fi lIing in the rightmost column for F wuh • 0 or a I for each row.
F
a b c d 0 0 0 0 0 0 0 0
F
0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1
1
1
0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1
(e)
. . Truth tables are not only found in d~gllal deSIgn. If you've studied basic
Gene
pair
Outcome
M o bIOlogy, you've likely seen a type of truth F blue blue blue table describing the Outcome of various blue brown brown gene pairs. For example, the table on the brown blue brown fight shows outcomes for different eye brown brown brown color genes. Each person has two genes for eye color, one (labeled M) from the mom , one (labeled 0) from the dad. Assumin o ani . bl ue and bro wn the table lists all ·bl" .y two poSSIble values for each "ene POSSI e combmati f " ' , person may have. For each combinau' th b . ons a eye color gene pairs that a 0 an. e ta Ie h ts the t as two blue eye genes will they h bl au come. . nly when a person h . ave ue eyes' hav' 0 results In brown eyes (due to th b . . m" one or two brown eye 2cn . e rown eye gene bemo d . - Unhke eq uations and circuits a Boolea "ommant over the blue eye gene.) representation . , n functIOn has ani 0111' truth table
One advantage of a truth table as a Boolean funetio . other representations is the fact that a f unctIon . h representauon compared to as only onen truth bl ' we can conven any other Boolean f ' . ta e representanon. so .,.. uncnon representatIOn t th bl ' a tru ta e to determine if d.Illerent . representations represent th e same f un lion-if th tlon. theIr truth tables will be identical T th bl C) rep,re :nt the same fun.:readers, as a truth table clearly h tho ru ta e are also quite mtuiti\'e to human ow e output for el'e 'bl ' that we 1I ed truth tab les in Figure 8 t d ' be . . f) .p."' I e mpul. Thu '. n'ti, basic logic gates. - . a esen 111 an IIltulme manner the beha\ior l f
58
Combinational Logic Design
2.6 Representations of Boolean Functions
ber of inpuls the number of truth A drawback of Irul h tables is Ihal fo r a Iarge num ' h b f input tabl e rows can be ex trem e))1 laroe. Given a function with It inputs, t e n~11l ~r 0 " . Id h 2 10 - 1024 pOSSIble IIlpUI comcombinations is 2". A funcl ion wilh 10 mputs wou ave -. f . . . I ble havlllg 1024 rows A unction binali ons-you can' l easily sec much of anythmg m a a . with 16 inpuls would have 65 .536 rowS in ils trulh lable.
EXAMPLE 2.18
Captu ring a function as a truth ta ble TABLE 2.2
Create a truth tab le describing a funct ion th at detects wh~ther a three-bit input 'S' v
Truth table for
5-or-greater fun ction.
a 0 a a a 1 1 1 1
b 0 a 1 1 a 0 1 1
C
a 1 a 1 a 1 a 1
F a a a 0 a 1 1 1
greater. Table 2.2 shows a trulh table for the funclion. We first list all possible combinations of Ihe three Inpul bitS, whIch III
all
remaining rows.
Given Ihe above representat ions, we can view combina~1, tional logic design as defining Ihe appropriate Boolean Equa1ions ' - - 2 / ~IS funcli on 10 solve a parlicu lar problem, and then creaLing a ci rcui l representalion of Ihal function. Defining the appropriale Boolean funClion requires nOl only thaI we Ihink aboul what Lhal function should be, bUI also ' - Trulh lables -"" Ih at we capl ure Ihal function in some form-Iypically eithe r as an equal ion or a trulh table. Then , we musl Figure 2.31 Possible conversions conven Ihe caplured funclion representation inlo a cir- from one Boolean fu nction cuit. Thus, combinalional logic design requires Ihal we represen tation to another. know how 10 conven from one Boolean funclion represemation 10 another. For Ihe three representations we have di scussed so far (equalions, circuils, and truth lables), there are six possible conversion from one represenlation 10 another, which we now describe (Figure 2.3 I).
( ----4
3)
6)
(
5
I. Equations to circuits Co nverting an equation 10 a circ uil can be done slraighlforwardl y by using an AND gale for every A D operator. an OR gale for every OR operalor, and a NOT gale for every NOT operalOr. We already gave several examples of such conversion. in Secti on 2.4.
2. C ircuits to eq uations Conven ing a circuil inlo an equation can be done by slaning from Ihe circuils inpuls. and then wriling the OUIPUI of each gate as an expression invol ving Ihe gale's inpuls, The ex pres ion of Ihe lasl gale before the OUlpUt represents the expression for Ihe circuil's
.
Figure 2.32 Converting a circuit 1O
an equation.
Q
we' ve labeled a. b. and C. We then enter a 1 in the outpu~ row
if the inputs represent 5. 6. or 7 in binary. We enter as
Converting among Boolean Function Representations
..
funcli on Fo h . ' . r exa mple, suppose we are given [ e CIfCUIl In Figure 2.32. To convert to an equall on,. we Slart wilh Ihe inverter, whose OUIPUI wI ll represen l C ' . We continue wilh Ihe OR gale-nOle Ihat we can'l delermine Ihe OUIPUI for Ihe AND gale yel umil we creale expr,essions for all Ihat gale's inpulS. The OR gale s OUIPUI represents h+p . Finally. we wrile Ihe ompul of Ihe AND as C ' ( h+p) . Thus, Ihe equallon F ( C . h , p) C' ( h+p ) repre ents Ihe same funclion a Ihe circuit.
-_. _---
3. Equations to truth lables o Convertin . " an equat'ton 10 a Iruth lable can be done by fi rsl creallng a Irulh lable struclure appropriale for the number of . bl . funcll on InpUI . vana es. and then evaluallng the riahl-hand SIde of Ihe equali on for each combination of inpul values. For example, 10 conven Ihe eq uation F ( a , b) = a' b' + a ' b 10 a truth lable, we would firsl creale Ihe truth lable structure for a IWO-InPUI funclion , as shown in Figure 2.30(a). We would then eva luate the righI-hand side of the equation for each row's comblnallOn of inpul va lues, as follows:
o Figure 2.33 Truth table for F(a.b)=a'b'+ab. + 0 0 + 1
1
0
0
0
0 + 0
0
We would Ihere fore fi ll in Ihe lable' righl column as shown in Figure 2.33. NOle thaI we applied propenies of Boolean algebra (mostly the identity pro~ny and null elemems propenYl 10 evaluale Ihe equations. Notice Ihal convening the equation F ( a . b ) =a ' 10 a truth lable re ults in exa t1v the same truth lable as shown in Figure 2.33, [n particular. evaluating the right-hand ide of the equatIOn for each row 's combinalion of inpul values yields: a =O and b=O, F a=O and b=1. F
0' :
0'
1
a= 1 and b=O. F = 1 ' 0 a = 1 and b= 1. F 1' = 0
Inputs a b 0 0
Output F
a' b'
a' b
0
1
0
1
1
0 0 0
1
1
1 0 0 0 1 1 Some people find il use ful 10 creale inter0 0 mediate columns in the lruth lable 10 compule Ihe eq uat ion's inlermediate value. Ihus filling Figure 2.34 Truth ubi. for Fla.b)=ab - , ~ with intemledinte lumn ~ eac h column of Ihe lable from lefl 10 righl. moving 10 the neXI column only after filling all ro\\S of the ' umm lliumn. An e:l.:lmpl for Ihe equallon F ( a . b ) - a' b' + a ' b is h \\ n in Figure ~ .3 ~ .
I
59
60
Combinational Logic Design
4. T ruth tables to equations To conve rt a truth table to nil equation. we cre:.l (C a product lenn for cach 1 in the outpu t column. a nd we Ihe n OR a ll the product terms. For the table on the ri ght (Figure 2.35). we get the terrns shown in Ihe ri glllll10st column of lhat tab le. ORing those terms yields F = a ' b ' + a ' b.
5. C ircuits to truth tables
2.6 Aepresentations of Boolean Functions Inputs b
0 0
Outputs
Term
F
F - s um of a' b' a' b
0 1
1
0
0 0
P • a 'b' c + a ' be ' + ab ' e ' + abe We could Ihen d ' h - . cSlgn 1 C Circuit using four A 0 gales and an
OR gate.
Note that even p ' d . h amy OC5n t Illean for Sure that {he data is correct ( note 1 at we were c'lref J I . was "assumed" (0 b . <, U 0 say earlier that the transmission two errOrs OCc e c?rrecI If I~C parity was correct), In particular. if For e . I ur On dlffere nl blls. Ihen Lhe parity will sLill be even . . xamp e, the sender may se d Oli 0 1111 1111 . ' . n . but Ihe receIve r may receive · . has even pari ty and thus looks correct. More powerful error detecl lon meth ods 'bl nrc POSSI c to detect multiple errors like this b . one, ut al the price of add ing ex tra bi ts.
Figure 2.35 Converting a truth table to 3n equatio n.
W e can convert a combi nnLional circuit to a truth
,
tabl e by firsl conve rtin g Ihe c ircu it to an eq uation (described earlier). a nd Lhe n converttng the equation 10 a lruth tab le (descri bed earl ier).
Parity generator circuit design sta rting from a truth table Nothing is perfect, and digital ci rcuits are no exception. Some ti mes a bit on a wire c ha"g~s when it's not supposed to. So a 1 becomes a O. or a 0 becomes a 1. For example. a 0 may be travehng along a wire. when suddenly some electrical noise comes out of nowhere and chang.es the
For
tllIJ
exllmple,
Harling/rom a
wble IS II more natural IfUl/J
{'/J oice t/Jall (III t!qUUfIfHl,
a 10 n. 1. While we
can redu ce the like lihood of such crrors. perhaps by usi ng we ll -insulated wires. we can"t completely preven t such errors. nor ca n we de lec t nod correc t all of th em- but we can de lcct some of them. Designers typicall y look for situat ions where errors are likely to occur, such as data being Lransmitted between two chips over long wires-like from u compu ter over a printer cable to a printer, or from a computer over a telephone line to anoLher computer. For those silUJ tions. designers add circuits that at least tfY to detect that an error has occurred. in which case the recei vi ng circuit can ask the sending circui t to resend the data. One common method of detec tin g an error is called parity. Say we ha ve 7 data bi ts to transmit. We add an extra bit. ca lled Ihe parity bi!. to make 8 bits tala I. TIle sender sets the parity bit to a 1 if Lhat wo uld make Ihe lotal number of 1s even-thai's called evell parity. For example. if the 7 data bils we re 0000001. then the parity bil would be 1. making the 10 101 number of Is eq ual to 2 (an even number). The complete 8 bi ls wou ld be 00000011. If Ihe 7 data bits were 1011111, then the parity bit would be O. making Lhe total number of Is eq ual 10 6 (a n even num ber). The complete 8 bi lS would be 10111110. The receive r now can detec t if a bit has changed du ring transmission by checki ng lhat there's an even number of 1s in the 8 bits received. If even, the transmission is assumed correct. If not even, an error occurred durin g tra nsmission. For example. if the rece iver receives 0000 0011. the trans mission is assu med 10 be correct, and the parity bit can be di scarded. leavi ng 000 0001. Suppose instead Ihat an error occurred and the receiver receives 10000011. Seei ng the odd num ber of 1 s, the receiver knows th at an error occurred- note that the receiver docs tlot know which bil i, erroneous. Likewise, 000000 I 0 would represenl an error 100. NO lice in this case that the error occurred in the parity bit. but the receive r doesn' t know where the error occurred. Let's describe a fun ction Ihat ge nemles an even paril y bit P for 3 dal" bit> a, b. and e . Staning from an equation is hard-what's the equation? For Ihis example. sian ing with a truLh lable is the natural choice. a, , hown in Table 2.3. For cach configuration of dOIa bil' (i.e .. for each row in the Lruth lable). we 'et the parily bilto make Ihe lOla I num ber of 1, eVCl1. From Ihe (ruth tub lc. we then obtain the followi ng equati n for the pari ly bi!:
TABLE 2.3 Even parity for 3-bit data.
o o o o
b
e
p
o o
o
o
o o
o
o o
o o o
Odd parity is also a common ki nd of parily-the parity bit value rna kes the lotal numb I' 1 od b . er a s d. There's no quality difference etween even parrly and odd parity- the key is simply Lhat the sender and receiver must both lise lhe same kind of parity. even or odd. A popular rcpresenlalion of lellers and num bers is known as ASCII which encodes each character Into 7 blls. ASCII adds 1 bi t for parity. for a tOlal of 8 bils pcr ch~cter.
6. Truth tables to circuits . We can convert a truth tab le 10 a c ircuit by first convertin g Ihe trut h tab le to an equatton (desc ribed earli er). and then convening the equation 10 a circ uit (described earlier).
EXAMPLE 2.19
61
EXAMPLE 2.20
Converting a combinational circuit to a tru th table Conven the circuil depicted in Figure 2.36(a) inlo a truth table. .
We beglll by convenin g the circ ui t 10 an equation. Starting from the gales closest (0 the AND gale and the invener in thi case-we labe l each aate's output as an express Ion of Ihe gate's inputs. We label Ihe leflmost AND gate' outpu t. for ex:mple. as a b. likeWIse,. we label .the leftmost inve ner's Output as C •. Continu ing through the circuit's oates. we label the nghlmosl Inverter' ( b) ' _ . e ( ) s OUlput as a . Frnally. we label the nghtmo t D .ate's OUtpUl as a b ' c ' . which corresponds 10 the Boolean equation for F. The full y labeled ci';;uit is hown in FIgu re 2.36(b).
IOPuts~the leftmost
.
From the Boolean equation. we can now construct the truth table for the combinational circWL
~lIlce our circuit has three in pu ts-a, b. and C-there are 23 = possible combinations of inputs (I.e. abe~OOO. 001. 010. 011. 100. 101. 110. 111). so our truth table has the ei.ht rows ~hown in Figure 2.37. For each input. we compute the value of F and fill in the correspondim! com
i
the lruth lab le. For example. when a ~O . b~O. and e=O. F is (00) • ~O' - (0)' ~ 1 : I ~ 1~ We con~pute the circuit's output for the remaining combinations of input using a truth table with IIllcrmedmlc values. shown in Figure 2.37. In
=,
F
F
Figure 2.36 (a) Combinalional ireu il. and (b) cireuit
\I
it h gates' output c' prc:"on, lJt-ckd.
62
2 Combinational Logic De Sign
2.6 Representations of Boolean Functions Outputs
Inputs
a
b 0 0
e 0
1 1
0
1 1
0 0
0
1
1
0
1
1
1
0 0 0 0
1 1
1
(ab)'
1
F 1
0
0
c'
ab 0 0 0 0 0 0
1 1 1 1 1 1
1
1
0
1 1
0 0
0
0 0 0
1
1
0
0
1
Figu re 2 37 TrUlh table ror the circu it 's equation
Standard Representation and Canonical Form Truth tables as a Boolean function standard representation We stated ea rli er that . although there are many possible equation representations and circu it represem3tions of the same Boolean function. there is only one pos ible truth table representation of a Boolean function . Truth tables therefore represent a standard representation of a function-for any func tion, there may be many poss ible equations, and many possible circuits, but there is only one truth table. The truth tabl e representation is unique. One use of a standard representation of a Boolean fu nction is for comparing two function s to see if they are equivalent. Suppose you wanted to check if two Boolean equation s were eq ui va lent. One way wou ld be to try to manipulate one equati on to be the same as th e ot her equation. like we did in our automatic sliding door example in Example 2. 13. But suppose we were not successful in gelling them to be the sa me- is that because they really arc not the same, or because we just didn't manipul ate the equation enough? How do we really know the two equations are not the same? A conclusive way to check if two fu nctions are the same is to create a truth F = a'b'+ F=ab+a ' table for each. and then check whether the a' b + ab truth tables are identical. So to determine a b F b F whether F = a b + a ' is eq uivalent to F 1 o o 1 o o = a ' b ' + a ' b + a b. we could geno 1 1 1 erate truth tables for each, using the o o o method described earlier of evaluating the function for eac h output row, as shown to the right. We see that the two functi ons are indeed equivalent, because the outputs are F = (a+b) , identical for each input combinati on. Now let's check if F = ab + a ' is equi valent b b F F a to F = (a+b) ' by comparing truth tables. o o o o As seen to the right, those two func1 o 1 1 o o o tions are clearly not equ ivalent. Comparing o o truth tables leaves no doubt.
63
While compari ng truth tables works fine when a function has only? inputs wh t 'f 10 32? , a J a functton has 5 ' . tnputs, or . ,or . . Creating truth tables becomes increasingly cumber;?'~' and tn many cases Just pl atn unrealistic, since a truth table' number of rows equals , here n tS the number of tnpulS. 2" grows very quickly. 232 is approximately 4 billion for example. We can't reali stically expect to compare 2 tables of 4 billion rows each. . However, 111 many cases, the number of output Is in a truth table may be very small cOmpared to the number of output Os. For example. consider a function G of 5 variables a b, c, d, and e : G = a bcd + a ' bc de. A truth table forth is fu nction would have 32 rows' but .only three Is in the output column-one 1 from a ' bcde, and two 1 from abed (which covers rows corresponding to a bcd e and a bcde '). This lead to the question : Is there a more compact but still standard representation of a Boolean function ?
Canonical Form-Sum-of-Minterms Equation The answer to the above. question is "yes". The key is to create a tandard representation that only deSCribes the situations where the function outputs 1. with the other situations assumed to output O.A n equation, s uch as G = abcd + a ' bcde. is indeed a repre entatIOn that only deSCribes the Slluatl ons where G is 1, but that representation is not unique. that IS, the representation is not tandard . We therefore want to define a standard form of a Boolean equation, known a a cal/ol/ical Jorm . You've seen canonical forms in regular algebra. For example, the canonical form of a 2 polynomlal ofdegree twoi s:a x 2 + bx + c. Tocheck if the equation 9x 2 + 3x + 1 is equivalent to the equation 3 * (3x 2 + 1 + x), we conven each to canonic,a1 form , resulting in 9x 2 + 3x + 3 for both equation. One canonical form for a Boolean function i known as a um-of-minterrns. A mil/term of a function is a product term whose literals include every variable of the funclion eraclly ollce. in either true or complemented form. The function F (a . b . e l = a' bc + abc ' + ab + c has four terms. The firs t two terms, a' be and abc ' . are minterrns. The third term, a b. is not a minterm since c does not appear. Likewise. the fourth term. C. is not a min term, since neither a nor b appears in that term. An equation i in sum-oJ-minterms Jorm if the equation is in sum-of-product form. and every product term i a mimerm. Convening any equ ation to sum-of-minterms canonical form can be done follo\\i n!! just a few steps: T
l. First, we manipulate the eq uation until il i
III um-of-product form . uppo ewe are given the equation F( a . b . e) =( a+b)(a '+ aclb. We manipulate it as follows:
F = (a +b )( a '+a c) b
F = ( a+b )(a 'b+ac b l F = a ( a ' b+a c b ) + b( a' b+acb) F = aa ' b + aa cb + ba' b + ba cb
F = O*b + a c b + a ' b + acb F = acb + a'b + acb F = a c b + a' b
(b. the di triburiYe propenYl (distributive property) (distributi"e propel'!) ) (complement. commUl3ti\e. idempotent) (null elements) (idempotent)
64
Combinational Logic Design 2.6 Representations of Boolean Functions 2. Second, we expand each tenn until every term is a minterm:
F F F
aeb + a'b aeb + a ' b* l aeb + a'b* (e+e ' ) a e b + a ' be + a 'b e '
(identity)
H - a ' bede + abede ' + abede
(complement) (d istributive)
is the sum of the minterms 15,30, and 31 , which can be com pactly written as:
H
3. (Optional step) For neatness, we can arrange the literals within each te~m to a con-
sistent order (say alphabetical), and we can also arrange the terms they would appear in a truth table:
F
~
In
the order
a ' be ' + a ' be + abc
The equation is now in sum-of-minterms form . The equation is in sum-of-products form, and every product term includes every variable exactly once. An alternati ve canonical form is known as product-of-maxterms. A max/erm is a sum term in which every variable appears exactly once in either true or complemented form. such as (a + b + e ') for a function of three variables a, b, and e. An equation is in produc/-of-maxterms form if the equation is the product of sum terms, and every sum term is a maxteml. An example of a function (different from that above) in productof-maxterms form i J ( a . b, c) ~ (a + b + e') ( a ' + b ' + e ' ). To avoid confusing the reader. we will not discuss the product-of-maxterms form further here, as sum-of-minterms form is more common in practice, and suffi cient for our purposes.
~
Multip le-Output Combinational Circuits Many combinationa l circuits not only invol ve more than one input. but also involve more than one output. The simplest approach to handling a multiple-output circuit is to treat each output separately. leading to a separate circuit for each output. Actually, the circuits need not be completely separate-they could share common gates. We'lI show how to handle multiple-output circuits through examples.
EXAMPLE 2.22 Two-output combinational circ uit Design a circuit to implerncnllhe rollowing two equations of three inputs a. b. and c:
Comparing two functions using canonical form
G
Suppose we wanllo delenmine whelher Ihe fun ctions G( a , b, e , d . e) ~ abed + a' bede and H(a,b.e . d . e) = abede + abede' + a ' bede + a ' bede(a ' + e) are eq uivalent. We
=
ab + e ' ab + be
We can design the circuit by simply creating Iwo separate circ ui ts. as in Figure 2.38(a).
first com'cn G to sum-of-minterms form :
G G G G-
1:m(l5 , 30 , 31)
The summation symbol means the sum , and then the numbers insi de the parentheses represent the minterms being summed on the right side of the equation.
F EXAMPLE 2.21
65
corresponds to 1111 0, or 30; and a be d e corresponds to lIllI, or 3 I. Thu . we can say that the function H represented by the equation:
a
abed + a ' bede abed( e+e') + a ' bede abede + abede ' + a ' bede a ' bede + abede ' + abede
b
F
F
We then conven H to sum-of-m imerms form:
H H H H H
abede + abede ' + a'bede + a'bede (a ' + e) abede + abede ' + a ' bede + a'bedea ' + a 'b edee abede + abede ' + a 'b ede + a ' bede + a ' bede abede + abede ' + a' bede a ' bede + abe de ' + abede
G
(b) (a)
Clearly, Gand Hare equivalent.
Figure 2.38 Multiple-output circuit: (a) trealed as two separale circuits. :lIld (b) \\ ith gale sharing.
NOle thai checking Ihe equivalence using truth tables would have resulted in 2 rather large tru lh lables having 32 rows each . Using sum of mintenms was probably more appropriale here.
We can instead notice thai the lenn a b is common to both equations. ThUs. the
£\\ 0
circuits an
share Ihe gate thai compules a b. as shown in Figure _.3S(b). Compact sum-of-minterms representation A more compac~ represent~tion of sum-of-minterms form involves listing each minterrn as a number, ~Ilh each mtnterm 's number determined from the binary representation of Its vanables values. For example, a' bede corresponds to 01111. or 15 ; abede '
EXAMPLE 2.23
Binary number to seven-segment display converter 1nny electronic appliances display
3
number for us
10
read. E.ample applian< - indud: a d
mi~ro\Vave oven. and a telephone answering ma hine. A \ cry ~pul~ and simple dC\I:-e tor dl~r tJ.~. ing a single digit number is a se"en-segment display. illustraled III FIgure 2.39.
66
.-, , ,", ,,: '..'
Combinational Logic Desig n a f -----, b 9 e -----, e - - - -_ d ------,
abedefg =
1111110
(0)
2.7 Combinationa l Logic Design Proc ess
We can create a Custo m logic ci rcuit to implement th e converter. Note that the above table is in
the fonn of a truth table hav ing multiple outpu ts (a th rough g). We can treat each output separatel y. so ~e deSign a circuit for a . then for b, elc. Looking al the Is in the a column. we obtain the fol -
lOWing equation for a:
a - w' x ' Y' Z' + w' x ' yz ' + w' x ' yz + w' xy ' z + w' xyz ' w' xyz + wx ' y ' z ' + wx ' y ' z
1101101
0110000
The displ ay consists of seven light seg ments. each of which can be illu minated independently of the others. We can display the desired di git by sell ing the signals a , b . c , d . e: f , and 9 appropriately. So to display the di git 8, we set all seven signals to 1. To display the di git 1, we set b and C 10 1. A useful combi national circu it is one thai converts a binary number to the seven-segment display signal s a- g thm display the number as a deci mal digil. We need fo ur bi ~s . say w, x, y, ~d z. to represent the binary values of the ten possible di gits 0 to 9. Table 2.4 deSCri bes the conversion of cach binary nu mbe r to the seven-segment display's signals. We decided to ac tivate no segments for the nu mbers 10 through 15. Fo r rhis t·xwnple. starting f rom a table is a mo re natural choice {han all eqllarion.
TABLE 2-4
4-bit biDary number to seven-segment dis pl av truth table
w
x
y
z
a
b
c
d
e
f
9
a a a a a a a a
a
a
1
1
1
1
1
1
0
a a
1
0
1
1
0
a
a
a a
0
1
0
1
1
a
1
1
0
1
0
1
1
1
1
1
1
0
a
1
1
a a
0
a
1
1
a
1
1
1
1
1
a
1
1
1
1
1
I
1
1
I
a a
0
1
1
I
1
1
1
I
a
0
0
0
0
1
1
1
0
1
1
1
1
I
I
1
0
a a
0
1
1
1
1
I
1
0
1
1
1
0
1
0
0
1
0
1
1
1
I
a
a a a a a a
a a a a
a a a
0
0
0
a
a a a a a a
a a a a a a
a a a a a a
1
1
a a
1
1
1
a
1
1
1
1
1
0 0
a a 0
0
+
Looking at the 1s in the b column, we obtain the following eq uation for b:
(c)
(b)
b - w' x ' y ' z ' + w' x ' y ' z + w' x ' yz ' + w' x ' yz + W' xy ' z ' + w' xyz + wX ' y ' z ' + wx ' y ' z
Figure 2.39 Seven-segment display: (3) connections of inpu ts 10 segments. (b) input values for numbers O. I. ::md 2. ~nd (c) a pni r of real seven-segment display components.
Inlll!
67
.-.'-'
We could then proceed to create equ ations for lhe remaining outputs C through g. Finally. we would create a circuit for a hav ing 8 4-inpul AN D ga tes and an 8-input OR gale, another circuit for b hav ing 8 4-input AND gates and an 8-i nput OR ga te. and so on for C throu gh g. We coulci of Co urse, have minimi zed the logic for each equ::uion before cremi ng each of the circuits. You may notice th at the equat ions for a and b have several terms in common. For exam ple. the term w' x ' y ' Z ' appears in both eq uations. So it would make sense fo r both outpu ts to share one AND gate ge nerating th at term . Looking al the trul h table. we see that the tenn w' X ' Y , z ' is in fact needed for outp uts a, b, C, e, f, and g, and thus the one AND gate generating thaI te rm cou ld be shared by all six of th o e outputs. Likewise. each of the olher requ ired tenTIS is shared by several outputs. meaning each gate ge nerating each term could be shared among severa l outpu ts,
2.7 COMBINATIONAL LOGI C DESIGN PROCESS
• a:-. :.-.•
.'-1- .-
.:..-. :J. .:.. :.
-. -.
Based on the prev ious sections, we can define a traighrforward method for designing combi national log ic, sum mari zed in Table 2.5 TABLE 2.5
Combinational logic design process.
Step Capture the ~ f unclion 0.
N
fr
COllvert (0
equm iol/s
c;:j
Description
Create a truth table or equations. whichever is most natural for the gin~n problem. to describe the desired behavior of the combinational logic. This step is onl y necessary if you captured the function using 3 truth rable instead of equations. Create an equation for each output by ORing all the mintenns for lhat output. Simpl ify the equations if desired.
~ Implem efll as a
J5
For each out put. crente a circuit corresponding ro the outpu( equation. gate-based cireuit (Sharin g gales among multiple Outputs is OK optionally.)
Gate-based circuits designed such thaI Ihe inpul reed into a column of , that feeds into a single OR gale are known as two-iel'eilog;c impiemenlariollS.
glHl!S
EXAMPLE 2.24 Three 1s pattern detector We want 10 implemelll a circuit th at cnn detec t whether :1 pattern of at least thret' adJ3~nt h IJxur anywhere in an 8-bit input. and that outputs a 1 illthut case. The inputs are a . b. c . d. e. f. g. JnJ ".
68
Combinational Logic Design
2.7 Combinational Logic DeSign Process
_ 000 III aI y should be !. si nce there are three and the output is y. So for an input of a bc de f~th;; 10 I aI aII: the output should be a,. since th~re Is 111 a row (on IIl puts d. e . and f J. For an IIlp III I 0000 should res ult in y = !. Slllce havlllg are not three Is in a row anywhere. An Input of h . uil is an ex treme ly simple example of I '11 tput a I Sue a wc Id h •. p . de tectors arc widely used, for exarnp e, more than three I s in a row S Oll 511 Oll . . k lIem delcclOrs altern d a general class of CirCUits ' nown as pOl . k ' a digi ti zed video image. or to elect in image processing to detect things. like humans or tan ' 5, In specific spoke n words in a digitized audio stream. . . For this example. stoning f rom an
Step I:
eqllMiml is a lIIo re
naruml choice fholl a lrutf, toble.
Step I:
Capture the funclion. Capturing the function for this example is most naturally aChieved usi ng a truth table. We list al l the possible input combinations, and the desired output nu mber, as in Table 2.6. TABLE 2.6 Truth table for number-of-ls counter. Inputs
re the functi on as a rathe r large truth table, listing . Capillre Ihe JII"cllO". We could captu . 1 'or y in eac h row where at least .. f . ts and entenng a ., , out all 256 combmnllons 0 I,"PU . od for ea turing this particu lar function is to th ree I s occur. However. a slmple~ melh currence:of three Is in a row. One possibility create an equation th at lists thepoSSlble oc =111 Likewise, if cde =11!. def=lll, is that of a bc= 11 J. Anot her IS that of bcd I h possibi lity the values of the , fd e f g= 1J1 orfgh=1 11 we should output a . or eac . ' , . S 'f a bc= III we output a I. regardless of the values 0 , other In puts don I mailer. 0 1 .. ' .' . e . f, g, and h. Thus. an equ ati on desc nbmg y IS simply.
F
y
=
Convert to equations. We can skip this step since we already have an equation.
Step 3:
. . No simp . I'fi Implem ellt as a gate-based CIrcUli. I ea t"Jon of the equation is possible. The
(# of l s)
Outputs
b
c
0
0
0
( 0)
0
0
( I)
0
0
(])
0
0 0
a bc + bc d + cde + def + efg + fgh
Step 2:
69
1
1
( 2)
0
0
(I )
y
z
0
0
0 0
0
1
(2)
0
1
0
(2)
0
(3 )
1
resulting circ uit is shown in Figure 2.40.
Step 2:
Convert to equations. We create eq uations for each
OUrpUI
as follows:
y - a'bc + ab'c + abc ' + abc l - a'b ' c + a'bc ' + ab'c' + ab c We can simpli fy the first eq uation algebraically: y
Step 3:
g--_1-1
Figure 2.4ll Three Is pattern detector.
=
a'bc + ab ' c + ab (c ' + c) = a'b c + ab' c + ab
Implement as a gate-based circuit. We then create the final circuits for the two outputs. as shown in Figure 2.41.
a b
a b c
g c
EXAMPLE 2.25 Fo r fh is e;wmple.
starring fro m a I fll l h wb/t! is a more natural cho ice Ihon an
equation.
Num be ~o~l s coun~r
a
b
We want to design a circuit that counts the number of Is present on 3 inputs a. b. c. and outputs that number in bi nary using 2 outpu ts, y and l. An input of 110 has two I s. so our circu it should output 10. The number of I s on 3 inpu ts can range from ato 3. so a 2-bit output is suffi cient. since 2 bit can represent 0 to 3. A nu mber-of- Is COunter circuit is useful in a varie ty of situations. such as detecting the density of electronic particles hitting a collection of sensors by countin g how many sensors are ac tivated. As another example, there are airpon parking lots th at have sensors above each parking spot, coupled with signs that inform drivers of the number of avai lab le parking spots on a panicular level of a multilevel parking Structure (by cou nting the number of zeros, but th ut's the same as counting the num ber of ls with all inputs first complemented).
c Figure 2.41 Number-of-ls counter gate-based circuit.
Simplifying circuit nolations
.
We u ed a couple of new simpli fying nOlations in our circuits in ~e pre.n u~ ex~ple. One simplifying nOla lion is to lisl the inputs multiple times. to a,·o.d hanog ltn~S tn OUT drawi ng crossing one anolher-an inpul lisled multiple times is - umed to ha,e been branched from the same input.
70
Combinationa l Logic Design
2.7 Combi national Logic Design Process Another s implify ing nolttli on is Ihe use o f a n inversio n bubble at th e inpul o f a g al e. ra th er th a n the use of a NOT ga te. An tnpUI th:ll is inverted in to many gates is ass umed 10 feed throu gh a s ing le inve n er th at is then
~ SLOW DOWN! THE QWERTY KEYBOARD
branched ; ut to those gates. An alternative simplifi ca ti o n is to simpl y .include co mp lem e tHed va ria bles. like b ' . as tnputs. EXAMPLE 2.26
12-button keypad to 4-bit code co nve rte r Yo u've pro bably seen 12-bullon keypads in many
Fo r t"is example. starling Jrom equatio ns is a mOre natural c" oice I" {UI a Irwh table. although lI 'e used all inJo rmol table (1101 a lruth table) 10 help LIS dete nnille the equations.
TABLE 2.7
diffe rent places. like on n telephone or at an ATM mnchi nc as shown in Figu re 2.42. The first row has _r1 bUllons I. 2. and 3. th e second row has 4. 5. and 6. Ihe third row has 7. 8. and 9. 3nd th e las l row has *, O. and #. The ou tputs of such a keypad consist of _r2 seven signals-one fo r ench of the fo ur rows (r 1. r 2 . r 3 . and r 4). and one fo r eac h of the three col_<3 um ns (c l. c2, and c3). Pushing a part icul ar button causes exactly two outpu ts 10 become 1. correspond ing to the row and co lumn of Ihal button. So pushing butto n ''1'' causes r I : I and C I: I. while pushin g bUllan " #" ca uses r4 :: 1 and c3=1. \Ve c1 c2 c3 wa nt to design a circuil th nt co nve rts the seven signa ls frolll (he keyp.:ld illla a 4-bit binary number Figure 2.42 12- bullon keypad. 'v-I XY Z indi cat ing whic h bU lton is pressed. We wa nl buttons "0" to "9" to be coded as 0000 th rough 100 I (0 th rough 9 in binary), res pectively. Let's encode butt on " . .. as 1010. # as lOll. and let's let III I mea n that no button is pressed. Let's ass ume for now lhat only "one" bu tton can ever be pressed at a given time. \Ve could capture the functi ons forw, X. y, and Z using a truth lab Ie. with the seven inputs on the left side of the tab le. and the fou r outputs on the ri ght side. but that table would have 2' = 128 rows, and most of Lhose rows wou ld correspond merely to multi ple bunons bei ng pressed. Le t's try instead to capture the functio ns using eq uat ions. The infonn al Table 2.7 mi ght he lp us ge t tarted.
Inside a standard computer keyboard is a small microprocessor and a ROM . The microprocessor delec ts which key is being pressed. looks up th e 8-bit code for that key (muc h like the 12-button keypad in Exa mpl e 2.26) fro m th e ROM . an d send s th at code to the computer. There's an intercstin g story behind the way th e keys are arranged in a standard PC keyboard , whi ch is known as a QWERTY key board beca use th ose are th e keys that beg in th e top left row o f lette rs. The QWERTY arrangement was made in th e era of typewriters (s hown in the picture below), whi ch, in case yo u have n' t seen one, had each key conn ected to an arm th ai woul d swi ng up and press in k ribbo n an agai nSI paper.
Keys cOllnected to arms
Signals
w
I
rl
cl
0
2
rl
c2
3
rl
c3
0 0
4
r2
cl
0
Bullon
y
0
0
r3
c2
0
0
0
0
9
r3
c3
0
0
I
r4
cl
0
0
r4
c2
0 0
I
0
0
a
r4
c3
5
r2
c2
0
I
II
6
r2
c3
0
0
( no ne )
7
r3
cl
0
' '--'---
0
r 2c l + r 2c2 + r2 c3 + r3cl + rl ' r2 ' r3 ' r4 ' cl ' c2 ' c3 ' rlc2 + r l c3 + r 2c3 + r 3cl + r 4cl + r 4 c3 + rl'r 2 'r 3 ' r4 ' c l' c2 ' c3 ' : r lc l + rl c3 + r2c2 + r3cl + r3c3 + r4c3 rl' r2 'r 3 ' r4' c l' c2 ' c3 '
Y
8
0
r 3c2 + r3c 3 + r4 c l + r4 c3 + rl ' r2 ' r3 ' r4 ' cl ' c2 ' c3 '
X
y
4-bit code outputs
w
>,
We could then creale a circuit ror each OUlpUt. Obviously. the h SI teml of each equation L'OUld be shared by a ll fo ur out puts. Likewise. other tenns could be shared too (like r2c31. No te that th is ci rcuit wou ld not work well if multiple bUllons can be pre~ "00 ~i muJtaneousl~ . Our circuit will outp ut ei ther a valid or inval id code in that situation. depending on \\hich bunoos we re pressed. A prererable circuit would trem multiple buttons being pres!'cd as no button being pressed, \Ve leave the desig n of that circui t as an exercise.
I
0
..
Signa ls
An annoying problem with rype:writers was that arms would often get jammed side-byside up near the paper if you typed too fastlike too many people getting jammed sideby-side while Irying 10 Arms stuck! simultaneou Iy walk through a doorway. So typewrite r keys were arranged in the QWERTY arrangeme nt 10 slow down typing by separaring common lellers. since slower typing reduced me occurre nces of jammed keys. \Vhen Pes were invented. the QWE RTY arrangement was the natural choice for PC keyboards. as people were accuslomed to that arrangeme nt. Some say the differently-arranged D\orak keyboard enables faster r) ping. but that type of keyboard isn' t very common. as people are JUSt too accustomed to the QWERTY keyboard.
Us ing this fab le. wc call derive equ rni ons for each of the fo ur OUlpUlS, as follows:
Informal table for the 12-bunon keypad to 4-bit code converter. 4-bit code outpu ts
Bulton
71
Circuit s sim ilar 10 what we des igned above exis t in computer ke~ board..!., e',,"eptlhat lh~re are a lot more rows and colu mns, EXAMPLE 2.27
Sprinkler valve co ntroller
Automatic law n sprinkler systems use a digital y ~ tem to control th~ opc:nmg. and d o'-mg of w:uc-r va lves. A sprinllcr system u~lIull) !':upports se\ernl ditTcrent zonc~, ~UCh;b the;" bal' ~.ln.i. kft 'Ide ya rd. rig ht si Ie yard. fro ll! yard, elc. Onl~ on~ zone 's \'!the can ~ o~~t."'d 3t.1 tlTlk~ In \.wdt"r tQ m~ tain enough water prcs~ure in the !t:ns e:lch \'ahc ani) nt sJ:k~\.'itic tim!?!' of the d!t~ ~Uld fo r 'J.lt.."Cltk Jut'"J two, :urp...r
72
Comb inational Logic Design
2.8 More Gates 4
( I pi ns avaihble to control the va lves. not 8 outputs as req uired all pu th Illic
th e microprocessor onl y. has ~ h 8 les We C'1O Instead program or I e
ZOI.
<
.
e . b' Th we the 3 other ins to output th e active zone (0. I, ... , 7) In mary. us,
should be opened. and u,eiollal circuit ~avi llg 4 inputs. e (the enabler) and a. b. c (Lhe bi nary value need to deSign . combln.L . 8 d7 . d6 . ...• dO (Lhe val ve controls). as shown In Figure . ) and haVing outputs 1 of th e nC ll ve zone . (.
2.43. When e: 1. the clrCUiL. shauId decode the 3-bit binary input by setting exacLl y one ou tput to .
Step I:
Capture t he fune ron I . Valve 0 should be ac ti ve when abc:OOO and Lion for dO is: dO : a ' b ' c ' e
decoder d6f-- - - - --., d7f------." Figure 2.43 Sprinkler valve controller block diagram. For this example, stoning from equations is a
The eq uati ons ror the remaining outpu ts can be
determ ined similarl y:
lable.
NAND
A NAND gale (short for "not AND") has the opposite output as an AND gate, OUtputting a
o when all inputs are 1, and outputting a 1 if any input is a O. A NAND gate has the same behavior as an AND gate followed by a NOT gate. Figure 2.45(a) illustrates a AND gate. A NOR gate (short for " nol OR") has the opposite output as an OR gaLe, OUtputting a 0 if at least one input is a 1, and outputting I if all inputs are O. A NOR gate has the same behavior as an OR gate followed by a NOT gate. Figure 2.45(b) illustrates a OR gate. We earlier warned you in Section 2.4 Lhat our CMOS transistor implementations of AND and OR gates were not realistic. Here's Why. It turns out that pMOS transistors don'l actually conduct Os very we U, but they conduct I s just fine. Likewise. nMOS transistors don ' t conduct Is well , but they conduct Os just fine. The reasons for these asy mmetries are beyond this book's scope. But the implications are that the AND and OR gates we built earlier (see Figure 2.8) are not feasi ble, since they rely on pMOS transistors to conduct Os (but pMOS conducts Os poorly) and nMOS rransistors to conduct Is (but nMOS conduc ts 1s poorly). On the other hand, if we swap power and ground in the AND and OR circuits of Fig ure 2.8, we obtai n the gates shown in Figure 2.45 (a) and (b)Those gates have the behavior of NAND and NOR gates, which makes sense since output I s become replaced by Os, and Os by 1s.
dO d2 d3 d4 d5 d6 d7
more nQlltral c hoice {han a IrIIlh
NAND & NOR
NOR
d2f-------~--_,
processor
We earlier introduced three basic logic gates: AND, OR, and NOT. Designers commonly use several other lypes of gates too: NAND, NOR, XOR, and XNOR.
G =I>-
. .sc. vaJ ve I SIlOUIdbeacLive when abc:OOl and e:l,so LheequaLionfor dl iS: LlkevJl
a ' bc'e a ' bce ab ' c ' e ab ' ce abc ' e abce
NAND
dl d2
Convert to equations. No conversion is needed since we already have equ ati ons.
Step 3:
Implement as a gate-based circuit. The circui t implementing the equations is shown in Figure 2.44. The ci rcuit we've
y 0 0 0 1 0
y 0 0 0 0
1
0
XOR
XNOR
D D-
1
0 0 0
xy 0 0 0 1 0
F
0
1 1
xy 0 0 0 1 0
0
d4
dS
designed is aCLually a commonly used component known as a decoder lVilll
ellable. We'll introduce decoders as a building block in an upcoming section.
NOR
;GF;D-F x F x F
d3
Step 2:
d6
x-cj
F
F
x---1 d7
Figure 2_44 Sprinkler valve conLrolier Circuit (actually n 3x8 decoder wi th enahle).
73
2.8 MORE GATES
(e)
Figure 2.45 Additional gates: (a) NA D. (b)
OR. (c) XOR. Cd) XNOR.
(d)
F
0 0
74
Combinational Logic Design 2.8 More Gates
We can sli ll implemenl an AND gale in CMOS. bIll we would do so by appending a NOT gale aI Ihe OlliPUI of a NAND gale (NAND fo llowed by NOT gives us AND). as shown in Figure 2. ~ 6. Likewise. we would implemen l an- OR gale by appending a NO: gale at Ihe OUIPUI of a NOR gale. BUI Ihal s ~bviouSl y slower Ihan a circuil direclly implemenled as NA ND and NOR . FOriunalely. we
F
can apply straightforward meth ods to convert any AN D/ORINOT cireuil 10 a NA D-only
Airc raft lavatory sign using a NAND gate
Figure 2.46 AND gate in CMOS .
Example 2. 15 cre~Hed a 1 i1\,~lI ory available sign using
the followi ng eq uatio n:
s•
Circuit ( a be)
,
a-<-+--; b -<~--(
Notici ng that the lenn on the ri ght side corres ponds
XNOR gates can be used to compare two data ilems for equalily. ince a 2-input )(}\:OR oUlputs a 1 only when Ihe inpu ts are bOlh a Or are both 1. For example. suppose a byte II1pUI A (a7a6a 5... aO) to your system i counting down from 99. and you want 10 sound an alarm when A has Ihe sa me va lue as a econd byte inpul B (b7b6b5 ... bO). You can detect such equality u ing eight 2-input XNOR gate . by connecting a7 and b7 to the firsl XNOR gale, a6 and b6 to Ihe second )(j OR gale. elc. Each X OR gate leUs us whether the bits in Ihal panicular pos iti on are equal. By ANDing all the XNOR OUlpUlS. we can te ll whether every pos iti on is equ al. Generating and detecting parity using XOR
circuit. or 10 a OR -only circuit. We 'll desc ribe Ihose melhods in Seclion 7.2. EXAMPLE 2.28
c -<~--(
P-- - t - S
to a NAND. we can implement the circuit using a single NAND gale. as show n in Fig ure 2.47.
Figure 2.47 Circ uit usi ng NA ND.
An XOR gate can be used to generate a parily bit for a set of dala bilS (see Example 2. 19). XORing Ihe dala bits result in a 1 if there's an odd number of 15 in the data. so XOR computes the correCI parity bit for even parity. ince Ihe XOR's output 1 would make the tOlal number of 1s even. Notice that Ihe truth table we created for generating an even parity bil in Table 2.3 does in fact represe nt a 3-bi t XOR. Likewise, an XNOR gate can be used 10 generale an odd parit) bit. XOR can also be used to detect proper pari ly. XORing the incoming data bilS along with the incoming parity bit wi ll yield 1 if the number of I s is odd. Thu . for even parity. XOR ca n be used to indicate that an error ha occurred. since the number of I s i upposed 10 be even. XNOR ca n be used to delect an error when odd parity is used.
XOR & XNOR Completeness of AND/OR/NOT, AND/NOT, OR/NOT, NAND, NOR A 2- inpul XOR gale. shorl for "exclu sive or" and pronounced as "ex or:' ou lPUIS a 1 if exact/" one of Ihe Iwo inpu ls is a 1. So if such a gale has inpuls a and b, then the output' F is 1 if a· l and b·O, or if b'l and a·O. Figure 2.45(c) illustrates an XO R gate (for si mpli city. we omit the transistor-leve l im plement at ion of an XOR gate). For XOR ga tes with 3 or more inputs, the output is 1 onl y if the num ber of input Is is odd. A 2- input XOR ga te is equ ivalenl to the fun cti o n F ab ' + a ' b.
An XNOR gale. shari fo r "exc lusive nor" and pronounced "ex nor," i simply the opposite of XOR. A 2- input X OR is equi va lent 10 F - a' b ' + abo Figure 2.45(d) illu strales an XNOR ga le. omitting the transistor-level impl ementation for imp lic ity.
Interesting Uses of These Additional Gates Detecting all as using NOR
o o o
7S
Detecting equality using XNO R
A NOR ga le can detect the situation of a data ilem eq ual 10 O. ; ince NOR outputs a 1 only when all inputs are O. For example. suppose a byte (S-b il ) inpu t to your system i counting down from 99 10 0, and when the by Ie reache O. you wi~h to ound an alarm. You can delect Ihe byte being equal to 0 by si mply connecting the 8 bit.'> of Ihe byte into an 8-input NOR gale.
It should be fairly obviou that if you have AND gate. OR gate. and NOT gates. you can implement any Boolean functi on. Th is is because a Boolean function can be represented as a sum of product . which consists only of Al D. OR. and NOT operations. What might be slightly les obviou is that if you had onl) ro and ;\OT gat"". you could still implement any Boolean fu nction. Why' Here ' a simple explanatioll--lO obtain an OR. si mpl y put NOT gates at the input and ourputs of an .~'\'O. TJtis \\Qrks because F ~ ( a ' b' ) ' ~ a" + b" (by DeMo'llan' Law) ~ a - b. Likewise. if you had on ly OR and NOT gates. you could implement any Boolean functi on. To obtain an AN D. you could si mply invert the inpuls and ourpUts of an OR. sinceF ~ ( a ' +b ' ) ' ~ a"*b " ~ a bo It follows thai if you ollh' had NAN D gates a,ailable to you. you uJd still implement any Boolean fun cti on. Why? Because we can think of a NOT gate - a I-input NA ND gate. and we an imp lement an D gate using n 1'1 , D gate follo\\ed by a 1_ input NA D gate. Since we can implemem any Boolean fun tion l"ing ;\OT and :\_'\'0. we can therefore impl emen l any Boolean fun lion u>ing just :\'A~D . :\ X ;\D gate" thus known as a 1I11i1'er sa/ gme. Li kewi e. if )OU had ~lly I OR gate. you ould implement any Bool an fun,ti,n. because we an implement a NOT gUlf a! a I-inpul NOR gate. and an R gat llio~ng l NOR fo llowing by a I-input 'OR. inc" NOT and OR C~lIl lI11plement Jny B, ,I an tun ,li on. so can OR. OR gate is thus abo I.m",n 3< a uni,e _,t/ gat
76
2 Combinational Log ic Desig n
2.9 Decoders and Muxes
Number of Possible logic Gates Having seen several diffcrent types of basic 2-input logic gales (A I D, OR , lAND, NOR, XOR. XNOR). one might wonder how many poss ible 2- inputlogic gales ex ist. That quest ion is the same as as king how many Boolean functions ex ist for two variables. To answer the
b 0 1 0
0 0
question. we firs t note th ai a two-vari-
2 choices 2 choices 2 choices 2 choices
~
'"
'"
'"
Figure 2.48 Cou nting the number of possible Boolean functions of two variJ bJ es.
0 0
0
11 0 0
12 0 0 1 0
13 0 0
14 0
1 0
15 0 1 0
0
D
'"
0
z
D
16 0
f7
D
a:
x
18
0 0 0 0
1 0
0
..:
D
a:
0
D
a:
0
z
'" '" '"
'"
Decoders A decoder is a higher-level building block commonly used in digital circuits. A decoder decodes an inputl/-bi t binary number by selling exactly one of the decoder's 2" OUtputs to 1. For example, a 2-inpu t decoder, illustrated in Figure 2.50, would have 22=4 outputs. d3. d2. d 1, dO. If the two inputs iIi 0 are 00 , dO would be 1 and the remaining outputs would be O. If iIi 0=01 , dl would be 1. If iIi 0=10, d 2 would be l.lf i 1 iO=ll, d3 would be 1. The internal design of a decoder i straightforward. Consider a 2x4 decoder. Eacb output dO, dl, d2 , and d3 is a distinct fun ction. dO should be 1 only wben i 1=0 and iO=O , so dO il'iO '. Likewise, dl=il ' iO, d 2=iliO ' , and d3 =iliO. Thus. we build the decoder with one AND gate for each OutpUl. connecting the true or complemented values of i 1 and iO ta each gate, as shown in Figure 2.50.
=
Figure 2.49 lists all 16 of those functio ns. We indicate the 6 familiar func tions in the figure. Some of the mher function s are 0, a, b, a', b', and 1. The remaini~g functions are not necessaril y common functions, but each could be usefu l for some panlcular apphcati on. Thus, we don't necessarily need to build logic gates to represent those fu nctions, but we instead wou ld build those fu nctions as a circuit of the basic logic gates. 10 0 0 0 0
Two additional components, a decoder and a multiplexer. are also commonly used as digital circuit building blocks, though they themselves can be buill from logic gates.
F
Oar 1 Oor 1 Oorl Oar I
possible functions
able functi on's truth table will have 22=4 rows. For each row. the funct ion could output one of two poss ible values (0 or 1). Thus. as illustrated in Figure 2.48. there are 2 * 2 * 2 * 2 = 2' = 16 possible functions.
A more general question of interest is how many Boolean fun cti ons exist for a Boolean function of N variables. We can detemline this number by first noting that an
N- vari able fun ction will have 2N rows in its truth tabl e. Then, we note lhat each row can outputNone of two possible va lues. Thus. Ihe number of possible fun ctions will be 2 • 2 • 2 *_2 times. Therefore, the total number of func tion~ is: 22N
2 '
So 16 there arc:
= 2 = 65,536
8
2 ' = 2 = 256 possible Boolean possible functions of 4 variablc~.
dO 0 iO dl 0 il d2 0 d3
function~
of 3 vuriablc." and
dl d2 d3
D
z ..: z
z x
il
iO
(b)
Figure 2.50 2x4 decoder: (a) outputs for possible input combinations. (b) internal design .
etc.
2
dO 0 dO 0 iO dl I 0 iO dl 0 il d2 0 1 il d2 d3 0 d3 0 (a)
0
0
Figure 2.49 The 16 possibfe BOOlean func tions of two variables.
2
77
2.9 DECODERS AND MUXES
The internal design of a 3x8 decoder is similar: dO =i 2 ' iI ' i 0 '. d -i 2" A decoder often co Illes with an extra inpm called el/ab/e. When enable is 1. the decoder acts normally. But when enable is O. the decoder outputs all Os-no output is a 1. The enable is useful when sometime you don't want to activate any of the outputs. Without an enable, one output of the decoder mllSf be a 1. because the decoder has an output for every possible value of lhe decoders II-bit input. We rented and used a decoder with enable in Figure ~A-I. A block diagram of a decoder with enable appears in Figure _.51.
•i ,
dO
0
iO
dl
0
10) : '
il
d2
0
11
e d3
~O
1
0
(a)
(b)
Figure 2.51 Dec."Od
outrut- O.
0
d2 - 0
78
Combinational Logic De sign . . h'ck if part (or all ) of the ,ystcm's functionWhen designing :1 partIcular system. we C c . d cod'r red uces the amount of . -. d oder USIng a e " . '11 sec in Example 2.30. ah ty could be calTled oul by a ec combinat ional logic design thaI we need to perfonll. as YOLI EXAMPLE 2.29
Basic questIons about decoders I. \Vll a! would be
AIIJWel.
2. \Vhat wou ld be a 2x~ decoder's output va lues when the inputs arc II'!
AIlSII'er:
d2-0 . d3-0.
-.
I'
dO-O. dl-0.
ne of Ihe decoder's OUlpul; 10 be 1 al Ihe f d d ' Ulputs can be 1 at a
same time ? AflSI,'er: No such input vn llles exisl. Onl y onc 0 a ceo er S 0
given lillle.
'.,
.,
·t \Vh m wo uld the input va lues of a decoder be If the output \allles.lre dO Answer. The in put vi:llues Illllst be ; 1=0. i 0= l. This question i ~
.
.
'f I.he outpuI \'alues arc dO- 1 " d 1 - 1 d2:0. d3-0? . not valid. A decoder only has Olle ou tput equ:1lto 1 at any time.
5. \Vha! wo uld the inpu t val ues of a decoder be<> AIlS11'e r;
:0 dl= l d2-0. d3-0?
I
6. How Illany outputs would:1 5-input decoder have'? Answer: 25. or 32.
EXAMPLE 2.30
New Year's Eve countdown display A New Year's Eve counldown display could make use of a decoder. The di>play may have 60 lighl
Notice that we implemented this system without having to design any gate-level combinatiOnal logic-we merely used a decoder and connected it to the appropriate inputs and outputs.
•
d2-0. d3-1. J. \Vhm in put va lues of a 2x4 decoder cause more t lan 0
Multiplexer (Mux) A multiplexer ("mu x" for short) is another higher-level building block in digital circuits. An Mx I multiplexer has M data inputs and I output, and allows only one input to pass th rough to that output. A set of additional inputs. known as select inputs, determines which input to pass thro ugh. Multiplexers are sometimes called selectors because they select one input to pass through to the ourput. A mux is like a rai lyard swi tch that connects multiple input tracks to a single outpur track, as shown in Figure 2.53 . The swi tch ·s control lever causes the connection of Lbe appropriate inpu t track 10 the output track. Whether a train appear al the output depends on whether a train exists on the presently selected input track. For a mUll. the switch 's control is not a lever, but rather select inputs, which represent the desired connection in binary. Rather than a train appearing or nOI appearing at the ourpul a mUll outpu ts a 1 or a 0 depending On whether the connected input ha a 1 or a O.
bulbs goi ng up a tali pole. We want one light per second to turn on (with the prevIous one turning
off). slanin-g from bu lb 59 al the bollOIll oflhe pole. and ending wilh bulb 0 al the lOp. We could use a microprocessor [0 cou nl down from 59 to 0, butlhe microprocessor probably d ocsn ~t hflve 60 OU I put pin s that we cou ld use to control each light. Our microprocessor progr~m cou ld Instead output
the num bers 59. 58 ..... 2. I. 0 in binary on a 6·bit OUIPUI pan (Ihus oUlpuIIlllg 1110 11. ~ 11010• .... 000010 . 000001. 000000). We could conneCI Ihose six bits 10 a 6-lIlput. 64 (2 )-OUlpUI decoder. wilh decoder OUlput d59 lighling bulb 59. d58 lighling bulb 58. elc. . We'd probably want an enable on our decoder in Ihis example. since we'd wa nt all Ihe IIghlS off until we started the COuntdown. The microprocessor would initially sct enable to 0 so that no li.hlS would be illuminated. When Ihe 60 second countdown begin,. Ihe microprocessor would sel e;able to 1. and Ihen Outpul 59. Ihen 58 (I second laler). Ihen 57. "IC. The final system would look like that in Figure 2.52.
Figure 2.52 Using a 6x64 decoder 10 interface a microprocessor and a column
of ligh" for a New Year', Eve di ' play. The microprocec,,')or sets e - 1 when the la.." minute countdown begin..,. and th en counte., down from 59 100 in binary on
Ihe pill' i 5 .. i O.
ole Ihal Ihe
microprocessor ... hould never output 6(),
61.62. or63 on i 5 .. i O. and Ihu, Iho," OUlPU" of Ihe decoder go unu,cd
iO (; - - il ill i2 i3 ~ a. i4 e i5 u
.,
~
Happy New Yearl
dO dl d2 d3
...
6x64 d62 dcd d63
Figure 2.53 A multiplexer is like a rn ilyard swilch. detennining \\ hich inpul track conn IS to !be single outpul track. according 10 Ihe SWilCh's contrOl lever. A 2- inpul mUltiplexer, known as a 2x I multiplexer. has two dala inputs i 1 and i~ . one elect input 5 O. and o ne dnta output d. a- shown in Figure 2 .~. If 50-0. . . \llIue passes th rough . If 50=1. i l's value pa' ses th roug h.
d58 d59 d60 d61 )59
79
Whenever you have outputs such that ex actly one of those outpu ts should be set 10 1 based on the value of inputs representing a binary number. think about u ing a decoder.
_ dO-l d 1-0
2x.-l decoder's output values when the inputs nre DO?
:J
2.9 Decoders and Muxes
The intern al design of a 2x I multiplexer is hown in Figure 2 . ~ . When 50- i1. the top A D gate OU lputs 1* i 0- i O. and the bOIlOIll AND gate outputs ~. 1- . Tb ' . th OR gate output iO+O - iO. a iO pa es th rough u, desired. U ke" i-. \\hen S -:. the bOIlOIll gate passe i 1 while the t p gate outputs O. re.ulling in the R pass ing i 1.
80
2 Combinational l ogic Design
2x1 iO i1
2.9 Decoders and Mu.es
88 iO
I. S IsO -.0 1. A llswer : Because sls0-01 passes inpul i Ilhrough value of 1 1, whIch presently is 1.
i1
2. S 1 sO ~ I!. AlISlVer : Thai config uralion of seleci line inpul values passes i 3 through. so d wo uld have Ihe value of 1 3, which presently is O.
i1
sa
sa 1
sa
0
w
3.
~ ~ ~ Fig ure 2.542 x I multiplexer: (a) block symbol, (b) conneclions for sO-O , and sO-l, and (c)
4.
internal design.
A 4-i nput muiliplexer. known as a 4xl multiplexer, has four data inputs.i 3, i 2, i 1, and i O. two seleci inpulS S 1 and sO, and one dala outpul d (a mu x a/ways has Just one data Outpul , no matler how many inpulS). A 4x I mux block diagram IS shown III Figure 2.55.
4x1 iO i1 d i2 i3 51 sO
i1
~any inpu ts arc there on a multiplexer hav ing fi ve select inpUlS? Answer: Five select inputs
can unIquely identify one of 2'=32 inputs 10 pass through
10
the OUlpUt.
Mayor's vote display using a multiplexer Mayor's switches
Cates his vote on Ihe proposal (approve or de ny). Very consislently. righl after Ihe mayor indicales his
i2
vote, the town's citizens boo and shout profanities at the mayor-no matter wh ich way he Vo tes. Having
i3
had enough of Ihis abuse, Ihe mayor selS up a simple digital system (Ihe mayor happens 10 have laken a
sa (b)
Figu re 2.55 4 x I muhiplexer: (a) block symbol and (b) internal design. The internal design of a 4x I multiplexer is shown in Figure 2.55 . When S 1 sO-DO, the to p AN D gale out puts i 0*1 * 1= i O. the next AND gate outputs i 1 *0* 1-0. the next gate o ut pu ts i 2*1 *O~O, and the bOllom gate outpu ts i 3*0*0=0. The OR gale outpulS i O+O+O+O~ i O. Thus, i 0 passes through, as des ired. Li kewise, when s 1 sO-O l. the second AN D gate passes i l. while the remaining AN D gates all o utput O. When 5150=10, the third AND gate passes i 2, and the other AND gates output O. When s 1 5 0= 11, the bOllom AND gate passes i 3, and the other AN D gates OUtput O. For any value on s 1 sO, onl y I AN D gate will have two 1s for its select inputs and will thus pas its data input ; the other AND gates wi ll have at least one 0 for its select inputs and will thus ou tpu t O. An 8x I multiplexer would have 8 data inputs i 7... i 0,3 selec t inputs 52 . s l and sO, and one data outpu t. More generally, an Mx I multiplexer has M data inputs, log2(M) select inputs, and one data outpu t. Remember. a mult iplexer always has just one output.
EXAMPLE 2.31
d, then d would have the
~ow many s~lecl lines arc there on a 4x2 multiplexer? Answer: This question is not valid--there IS no such thIng as a 4x2 multi plexer. A multiplexer has exac ily one ompul.
S. How
EXAMPLE 2.32
10
~ow many select inp~ls mus., be ,present on a J 6x I mulLiplexer? Ansu:er: Four select inputs ould be needed 10 ulllquely Ide ntI fy which of Ihe 16 inputs 10 pass through 10 the OUlpUt since log,( 16)=4.
Con.sider a srn alJ IOwn with a very unpopular mayor. Dunng every town mee ting, th e ci ty manager presents four proposals to the mayor. who then indi -
iO
sl (a)
81
iO
Basic questions about multiplexers
AS5u.me a 4x I muhipJexer's four input.; presently have the followlllg valuc" i 0-1. iI - I. i 2-0, and 13-0. Whal wou ld be Ihe value on muhiplexcr', OUIPUI d for Ihe folio" illS ,ciCCI inpul volu ?
course in digital design), shown in Figure 2.56. He provides himself with four switches that can be positioned up or down, outpUlling 1 or O. respecti vely. Wh en the time comes during th e mee ting for
him 10 VOle on the fi rst proposal. he places the firs l swilch either in the up (accept) or down (deny) position-bUI nobody else can see the position of the switch. When th e lime comes to Vote on the second
Figure 2.56 Mayor's \Ole displa~ ~S[em implemented using a 4x I mu.<.
proposal. he VOles on the second proposal by placing the second swilch up or do"n. And 00_ When he has fini shed casting all his VOles. he leaves Ihe meetine and he~ds OUI for off"". \\ith the mayor gone, the city manager power up a large green/red light. \\'hen the input to the lighl is ,
the lighl Iighls up red. When the inpul is 1. the lighllighlS up green. The cil} manager controls!VoO switches th at can route any of the mayor's switch outputs to the light. and so the manager sreps
through each configuralion of Ihe swilches. slarring with configuration 00 (and alling OUI "n,., mayor's VOle on Ihis proposal is ..... ). then 01. the n 10, and finally 11. causing the lighl lolighl either green or red for each configuratio n depending on the IX> itions of the 013)Or'£ S\\;tcbes. The sys tem can easily be implemented lIsi ng a 4x I mu ltiplexer. as shown in Figure 1.56,
N-bit Mxl multiplexer Muxes are oft en used to sele ' rively po s through n t ju tingle bilS. but 'v-bit data item..<. For example, one set of inputs A may onsist of four bits a3, aZ. d 1, a .:md anocMr: ( of inputs B may a lso consist of four bi ts b3 . b2. b1. bOo \\' \\:int t mullipl \ th< inputs to a four-bit output C. consi ti ng of c3. c2, cL eO. Figure 2.5 (al >hO\\S h,)\\ to accomplish ' uch mult iplexing using ~ ur _\ I lllU \ CS .
Because mux ing data is so common. another common building bloc k is lhat of an N-bit- w ide Mx I mul7iplexer. So in our example. we wo uld use a 4 ·bil 2x I mu x. Don't get confused. lho ug h- an N-bil Mx I muhiplexe r is reall y just the same as N separa le Mx I multi plexers. with a lilhose muxes sharing the same select inpuls. Fi gure 2. 57(b) provIdes the sy mbo l fo r a 4- bi l 2x I mu x.
Multiplexed automobile above ·mirror display
Some cars come with a displ ay abovc the rcarview mirror, ::I S shown in Figure 2.58. Th e car's driver can press a button named mode to select among di5.playing the outside tcmperatu re, th e average miles-per-gallon of lhe car, lhe instantaneous miles-per-gallon, and th e approx imate mi les remaining until the C:1r ru ns out of gasoline. Assume the car's cenlral compUier sends
Figure 2.59 Above-mirror display using an 8-bil 4x I mux. Notice how many wires must be run from the car's central computer. which may be under the hood , to the above-mirror display-B * 4 = 32 wires. That's a lot of wires. We'll see in a later chapter how to reduce the number of wires.
. Notice in the previous example how simple a design can be when we can utilize hIgher-level building blocks. If we had to use regular 4x I mu xes. we would have 8 of them, and lots of wires drawn . If we had to use 2ates. we would have -lO of them. Of course, underlying Our simple design in Fig ure 2~59 are in fac I eight 4x I muxes. and underlyi ng those are 40 gates. And unde rl ying those gates are lOIS more rransislOrs. We see that the higher- level building blocks make our design task much more managable.
2.10 ADDITIONAL CONSIDERATIO NS Schematic Capture and Simulation
Ihe dala 10 the di splay as four 8·bil binary num. bers. T (the temperature). A (average mpg). I (inslanlaneo us mpg). and M (miles rema ini ng). T consists of 8 bils: t7. t6. t5. t4 . t3. t2. tL to. Likewise for A. l. and M. Assume Ihe display sys tem has two add itional inputs X and y. which always change accord ing (0 the fol-
;:;~ 8g-
0
(e)
Figure 2.57 -J -bit 2x I 11l1lX: (a) intern ;}1design using four 2x I nlu xes for selec ti ng al11.ong 4-bi l data items A or B. and (b) block diagr:lJl1 of iI -I.-bit 2x I mu x component: (e) The block diagram uses a C01111110n simpli fying notation. using one thick wire with a slanted line and the number 4 to
EXAMPLE 2.33
~~
83
Figure 2.58 Above· mirror di'play.
lowing seq uence-OO. 0 I. 10. ll-whenever the mode bU llon i, prc"cd (\I c'lI ,cc in [I lata chapler how 10 creale such a ,equence). When xy-OO. we wanl lo di'play T. When xy - O1. we wa nt to di'play A. When xy - l O. we wa nl lo di' play I. and when xy- I I. we wnnl to di'p lny M. A
When we design a circuil , how do we know that we designed the circuit correctly" Perhaps we created the truth tab le wrong, puning a 0 in an outpul column where we houId have PUI a 1. Or perhaps we wrote down lhe wrong mintenn . writing y z when we should bave wrole xy Z '. For exa mple, consider the num ber-of-one's counter in Example 2.25. We c reated a tru th table, then equations. and fin all y a circu it. Is the circuit correcl? One method of checking our wo rk is to re verse engineer the function from the c ircuit-staning with the c irc uit. we could conve n lhe circuil to equations. and then the equatio ns to a trulh table. If we gel the same ori ginal tru th table. then the circuil 5h uld be correct. Howeve r, sometimes we stan with an equalion ralher lhan a truth l:tble. 3S in Example 2.24 . We can reverse eng ineer lhe circuit to an equati n. but that equation ma~ be different than o ur ori g ina l equation. espe ia lly if we algebmicaIl) manipu!JI~ the original equalion when des igning the c ircuit. A nd checking that two equati ns are equi\'a le nt may requ ire convening to canonical rOm! (su m-of-minten11S1. \\hich may result in huge equalions if our functi o n has a large numbe r f inputs. In fact . e ve n if we didn ' t make nny mistakes in nvening ur mental undersr.mding of the desired func lion into a lruth lable or eq uatio n. ho\\ d \\ e \"no\\ that our mental
.' Ih'lI (I circuil works (IS we expect is called A commonl y used method for checkmg ' f 'd' g omple in l)U IS 10 the circuit . . . . . ' . h process 0 provl In u sl mul allon. SlIlIlIlatlOlI of a CirCUli IS I e . ' 1' OUIPUI for the given inputs. th I compules Ihe Circul s and running a compu ler program a I The compUler program that We can then check Ihal the OUIPUI malches whal we expec . performs simulalion is called a s;mllialor. To use simulalion 10 check a circuit, we mUSI describe the circuit using a method that enables compuler programs 10 read the. Cl rcui!. One melhod of descri bing a cIrCUlI IS to draw the circuil using a schematic capture 1001. A schemat;c caplllre 1001 allows a user 10 place logic gates on a com pUler screen and 10 draw wires con necting those gates. The 1001 allows users to save their ci rcuit drawinos as compuler files. All the circuit dr~wings in this chapter have represented examples of schematics-for example, the circui l drawing in Figure 2.50(b), repreFigure 2.60 Display snapshot of a commercial schematic senting a 2x4 decoder. was an example ofa capture tool. schematic. Figure 2.60 shows a schematic for Ihe same des ign. drawn usi ng a popular Inpuls commercial schemalic capture tool. Schematic capture is used nOI onl y to capture circuils for simul ator lools, but also for tools that map our circuits to physical implementai1 Outputs Outputs nd3 d3~Ltions, which wi ll be di scu ed in Chapler 7. Once we've created a circuit u ing sched2 d2-.rmatic capture, we must provide the simulator d1 d1JL with a sel of inputs for which we want to check for proper output. One way of prodO dO~ viding the inputs is by drawing waveforms (a) (b) for the circuit 's input ' . An input's waveform Figure 2.61 Simulation: (a) begins wilh us defining Ihe inputs is a line thaI goe from left to right , represignal over time. (b) automatically generales the oUlput senting the va lue of the input as time waveforms when we ask the simu lato r to sim ulate the circui t. proceeds 10 the right. AI different times, we draw the line as high 10 represent 1, and low to represenl 0, as shown in Figure 2.6 1(a). After we are sat isfied wi th our input waveforms, we instruct the si mulator 10 simulale our ci rcu it for the given inpu ts waveforms . The simulator determines what the circuit outputs wou ld be for each unique combination of inputs, and generates waveforms for the outpUts. as illustraled in Figure 2.6 1(b). We can then check that the output waveforms malches the outpul val ues Ihat we wou ld expect for each input. Such checki ng can be done visuaJly. or by providing certain checking statements (often called assertions) to the simulalor. Simulation still does not guarantee thaI our circuil is correct. but rather increa es our cOllfidence that our circuit is correct.
iO---.-fL
I'.M+
i1~mulat~
~ .
.-- - -
85
Nonideal Gate Behavior-Delay Ideally, logic gale oUlputs would change Immediately in response to changes in the gate's inputs. The liming diagrams earlier in this chapter all ass umed such x ideal zero-delay gates, as shown again in o ! Figure 2.62(a) for an OR gale. Unfortunalely, real gate oUlputs don' l change 1 immedialely, but ralher after some short lime delay. After all , even the fastesl F 1 au tomobi les can't go from 0 10 60 milesF per-hour in 0 seconds. The delay in gates o , O ! .. is due in part 10 Ihe fac t that transistors time time don't switch from nonconducting to con(a) (b) ducting (or vice versa) immedi ately-it Figure 2.62 OR gale timing diagram: (a) withoul takes some time for electron to accumugale delay. (b) with gale delay. late in Ihe channel of an nMOS
1Ju- 1Ju-
:lr ~Jt-i___..
! ro-f-l
JJ
transistor, for example. Furthermore, electric current travels at the speed of light. which, whi le extremely fast. is slill nOI infinitely fast. Additionally, wires aren'l perfect and can slow down electric current because of "parasitic" characteristics like capacitance and inductance. The timing diagram in Figure 2.62(b) illustrales how a real gate' output changes slightly after change in the inpulS. Gales delays for modem CMOS gates may take less than I nanosecond to respond 10 changes--extremely fast. but still not zero.
Demultiplexers and Encoders Two additional components, demultiplexers and encoders. can also be con idered as combinational build ing blocks. However, those component" are far les commonly used than their counterparts of multiplexers and decoders. everlheless. for completeness. we' ll briefiy introduce Ihose addi lional components here. You may notice throughout thi s book thaI demultiplexers and encoders don't appear in many examples. if in any examples at all . Demultiplexer A demultiplexer has roughly the opposite functionality of a mulriple_
86
Combinational Logic Design
2.14 Exercises 87 and NOT gates, enabling . us to build d . ex tremely powerful conee t S ' ~n manipulate circuits by using mathB I p . ecnon 2 6 Introduced I ' an 00 ean function s namely equation '.. severa dIfferent representatiOIl5 of straightforward th;ee-step process fO~' d~;~ UItS, and truth tables. Section 2.7 described a exa mples of bui lding real circuits usin th g~ng combinatIOnal CIrcuits. and gave several NA ND and NOR gates are actuall get ree-step process. Section 2.8 described why CMOS technology, and showed y mare commonly used than AND and OR eates in could be built with NAND gates ~~~ea:~ ~~~It built from AND. OR. and NoT gates two other commonly used gates XOR d gates alone. That seCllon also introduced commonly used combinational bUildin an XNOR. Section 2.9 introduced two additional bl Introduced schematic capture tools ;. hoCI~s. decoders and mUltiplexers. Section 2.10 puter programs can re'ld thos . ,w IC a . ow us to draw our circuits uch that comd d' . , e CirCUitS and als ' the output waveforms for user-pro 'd d' . a Intra uce SImulation. which generates ' . . VI e Input waveforms t hi a CirCUIt correctly. That section also discu a e p us venfy that we created between the time that I'n t h ssed how real gates actually have a small delay pu s canoe and the t' b h ' secti on also introduced sam I '" Ime t at t e gate s output changes_ The . e ess common ly used c b' . aI . . tlplexers and encoders. am illatIOn building blocks. demul-
OU lpUt is 00 . 0010 yields 01, 0100 yields 10 . and 1000 yields 11. In other words, d O~ 1 resul ts in an OUl pUt of 0 in binary, d 1 ~ 1 results in an output of 1 '~ blllary, d 2- 1 results in an output of 2 in binary. and d3~ 1 results in an omput of 3 ttl btnary. A priority e/l eoder has si mil ar behavior, but handles situations where more than one input is 1 at the same ti me. A priority encoder gives pri ori ty to the hIghest Input that IS a 1. and outputs the binary value of that input. For example. if a 4x2. pri ority encoder has inputs d3 and dl both equal LD 1 (so the inputs are 1010). the pnonty encoder gIves pnority to d3 , and hence outputs 11.
2.11 COMBINATIONAL LOGIC OPTIMIZATIONS AND TRAOEOFFS (SEE SECTION 6.2) The earlier secti ons in this chapter described how to create basic combinational circuits. This section. Secti on 2. 11 , physically appears in this book as Secrion 6.2, and describes how to make those circuits better (smaller, fas ter, etc.)-namely, how to make optimizations and tradeoffs. One use of this book covers combinational logic optimi zations and tradeoffs immed iately after introducing basic combi national logic design, meaning covering that section now (as Section 2. 11 ). An alternative use of the book covers that section later (as Section 6.2) , after al so introducing basic sequential design, datapath components. and register-transfer level design- namely, after Chapters 3, 4, and 5.
2.14 EXERCISES Any problem noted with an asterisk (*) represent an especially challenging problem. SECTION 2.2: SWITCHES
2.12 COMBINATIONAL LO GIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAG ES (SEE SECTION 9.2) Hardware description languages (HDLs) allow designers to describe their circuits using a textual language rather than as circuit drawi ngs. Thi s section. Secti on 2. 12, introduces the use of HDLs to describe combinati onal log ic. The section physically appears in the book as Section 9.2. One use of mi s book introduces HDLs now (a~ Section 2. 12), immediately after introducing basic combinational logic. An alternative use of the book introduces HDLs later (as Section 9.2), after mastery of basic combinational, eq uenti al, and regIster-transfer level design.
2.13 CHAPTER SUMMARY Section 2. 1 introduced the idea of u. ing a custom digi tal circu it to implement a system's desired fu nctionality and defi ned combinational logic as a digi tal circuit whose outputs are a function of the circuit's present inputs. Section 2.2 provided a brief history of digital switches, starting from relays in the 19305 to today's CMOS transi. tors, wi th the main trend being the amazing pace at which switch size and delay have continued to shrink for the past several decades, lead ing to ICs capable of containing a billion transistors or mar:. Sect ion 2.3 described the basic behavior of a CMOS tr. nsiMor. j ust enough informatIOn to remove the mystery of how trans i s to r~ work . ecti on 2.4 introduced three fundamenta l bui lding blocks fo r bui lding di gital ci rc uit ~-A D gates. OR gates. and NOT ga te~ (i nverters), which arc far c.1sier to work with thun tranSiMor~ . Section 2.S showed how Boolean algebra could be u,cd to rcprc,ent circuit; built from D, OR,
2.1 A microprocessor in 1980 used aboul 10.000 transislors How . would fil In a modern chip having J billion transistors? . mallY of those mtcroprocessors
2.2 The fi rsl Pentium microprocessor had about 3 processors would fi l in a
'1"
.
od . . m~ I~on lr.lnSISIOrs. HO\\ many of those microm em chip havmg I billion transistors?
2.3 Define Moore'S Law.
~ PLUS
2.4 Assume for a pan icular year that a panicular ' h' . cOOlain I billion t ' . sIze C lp uSing tate-of-Lhe-an technolo!!)
ranSlSlOrs. ASSUll11112 Moore's Law h Id
same size chip be able 10 contai n in Ie; years ?
2.5 Assume a cell phone co the phone used vacu um I cubic inch?
.
50
0
s.
h
0\\
man)
-
:lD
rran~islors will the
"
:~~~Sinst~:~I~~~r::::~t~rs.
How. big would such 3 cell pb oe be If ' assumIng :1 \ 1} uum rube has a \olume of
2.6 bi A modem desktop proces. sor, suc h as [he Pentium -f, has about 300 million tr.Utsistors.. H
V3~UUI11 [U~ ~~~::~la~:k~~PI ~::re ~I:C~? if we used vacuum rube
of the I
~ . -suoun~
a
SECTION 2.3: THE CMOS TRANSISTOR 2.7 Describe the behavior of Ihe CMOS lransislor circuit
shown .in Figure 2.63. Slstor ClrCUiI conducts.
clearly indicati ng when the tr:Jn-
2.8 If we apply a voltage 10 the gate of a CMO lransbtor, \~hy ?ocsn', the CUITCnt fl ow from the gale 10 lht: tr..tnSistor S source or drain?
Figure 2-63 Ctrcuit, Nlt lrung t\\ O
~t
tr.ll~L"h.."'f'.
88
Combina tional Logic Desig n 2.14 Exercises
SEC TION 1.4: 800LEAN LOGIC GA TES-8 UILDING 8LOCKS FOR DIGITAL C IRCUITS . . OT . appropriatc for cach of Ihe fo li ow lOg. 2.9 \Vhich Boolean opcralion. AN D. OR. or . IS d' 'I house (c~lch motion sensor outputs 1 when Illolion is detected). ",' ssed simultaneous ly (eac h bUBo n ou tputs I when (b) Detectin g that th ree bu ttons arc bt: lOg pre
a
bu lt~1I
is being pressed)"
r oll! sensor (the ligh t sensor out puts 1 when light is 10
sensed).
.
Boolca." equ ations:
2. J 0 COllvcn the rollowing English probl em sl.lI~mel ' d "d ' d th e system is set 10 enabled. n h Id a pump If water IS CICCI!.; an (a) A ood deleclor S ou lum on , . ; 11 if il is nig hl and lig hl i delecled inside a (b) A house energy monitor should sound an a an .
.,.
lIS 10
room bu t 1110 [ion is n OI de tected. . . . wate r valve if the sys te m is enabled and (c) A n irriga ti on sys tem should open the spnnkl er s neither rai n nor freezing tempelJ.tures are de tec ted. . 1.11 Eva luale Ihe Boo lean equali on F = (a AND b) OR c OR d fo r Ih e g ive n va lues o f vanables a . b. c. and d: (a) a-I. b=1. c=1. d=O (b) a=O. b=1. c=1. d=O (c) a=1. b=1. c=O . d=O (d) a-I. b-O . c= l. d-l
e.
o
PLUS 2.20 A DJ ("·disc joc key." meaning someo ne who plays the mus ic al a party) would like a system to aUlo malically conlrol a strobe li ghl and disco ball in a dance hall depending on whether music is play in g and anyone is dancin g. Assume we have a sound sensor with output S mat indicates whelh er mu sic is pl ay ing (5= 1 means music is p laying) and a motion sensor M that indicates whether peopl e are dancing (11- 1 means people are danc ing). The strobe light bas an input L Ihal lums Ihe lig hl on when L is 1. and the di sco ball has an inpul B thai turns the ball on when B is 1. The DJ wants Ihe di sco ball 10 tu m o n on ly when music i playiDg and nobody is dan ci ng. and Ih e DJ wan Is the strobe li ghl lo lum o n o nly when music is playing and people are danCing. Using A D. OR. and NOT gales. creale a si mple digilal circuil to activate: (a) the di sco ba ll. and (b) Ih e stro be li ght.
2.21 We wanl to concise ly descri be the fa llowing si ruation usi ng a Boolean equation. \Ve Wanl to fire a foolball coach (by setting F -1) if he is mean (represented by M= 1). If he is nor mean. but has a losing season (represented by the Boolean variable L- 1). we wanl 10 fire him anyway. Write an equ ation thai translales the siluation directly 10 a 8 00lean equation for F. "ithout any simplificmi on.
2. 12 Eva lu ale Ihe Boo lean eq uali on F = a AN D (b OR c ) AN D d fo r Ihe g ive n va lues o f variables a . b. c. and d: (a) a=l. b-1. c=O. d-l (b) a=O. b=O. c=O, d-l (c) a-I. b-O. c=O , d=O (d) a-I. b=O. c=1. d=1 2.13 Eval uale the 8 00 lean eq uation F ab ies a . b. c . an d d: (a) a-I, b-1. c-O. d-l (b) a-D. b-O. c-O . d-l (c) a-l. b-O. c=O. d - O (d) a-l. b-O. c-1. d - l
=a A
a + bcd'
2. 19 We Want to design a system that sounds a buzzer inside Our home whenever motion outside is detec led al ni ght. Ass um ing we have a mo ti on se nsor wi th o utput M thal indicates whether mol ion is delec led (M-l means motion delecled) and a lighl sensOr wilh Outpul L that indica les if li ghl is delecled (L = 1 means li ghl is delecled). The buzzer inside the home has a sing le inpul B Ihat when 1 crea les a loud warn ing sound. Usi ng AND. OR. and NOT gates. creale a s imple dig ital circuit 10 impl ement the mo ti on detec tor at night system.
(a) Detecti ng mOl ion in any Illolion se nsor surrOUIl 109 •
(e) Delccllng (he :1 bscncc of light from a
SECT/ON 2.5: 800LEAN ALGE8RA 2.22 Fo rthe funclion F = a + a' b + acd + c': (a) Lis l all Ih e vari ables. (b) Lisl all Ihe li lerals. (c) Lis l all Ihe prod uci lerms.
D (b OR (C AND d) ) fo r Ihe g iven va lu es of vari·
2.23 Fo r Ihe fun cli o n F - a ' d' + a ' c + b' cd' (a) Lisl all the varia bles. (b) Lisl all the lilerals. (c) Lisl a ll Ihe prod uci lerms.
2. 1 ~ Show the conduc li on paths an d OUIPUI va lue of the OR gale transi lor c irc uil in Figure 2.11
+ cd:
2.24 Lei varia bl es T represent being tall. H bei ng heavy. and F being fast. Let" consider an)ooe who is nOI lall as short . not heavy as li gh l. and not fast as slow. Write a Boolean equation to represe nl Ihe fo llowing:
when: (a) x = 1 and y = O. (b) x - I and y = I. 2.15 Show the conduc lion paths and OUIPUI va lue o f Ihe AN D ga le lrans i'lo r circ uil in Fig ure 2.1 3 when: (a) x = 1 and y - O. (b) x = 1 and y - 1.
(a) Yo u moy ride a panicu lar amu semen l park ride only if you are either tall !Uld ligb~ or s hort and heavy.
2. 16 Conven eac h of Ih e fo ll Ow ing equali ons directly 10 gate-level circlIi l-" (a) F a b ' + bc + c ' (b) F - ab + b ' c 'd'
(b) YOll may NOT ri de an amuse ment park ride if you are either tnll !Uld lighl. or -bon !Uld heavy. Use a lge bru 10 si mp lify the eq uatio n 10 sum-of-produ IS. (c) Yo u are e li g ibl e 10 play o n a panicul", baskelball leam if you are tall !Uld fast. or tall :tnd s low. Sim plify Ihi s equ alio n.
(e)
F
E
« a + b' )
*
(c ' + d»
+
(c + d
+
e' )
(d) Yo u are OT e lig ible 10 play on " particular foolball 1
2.17 Conven each of Ihe following equali ons direclly 10 gate-leve l circ uits:
+ b' c
(a) F -
a ' b'
(~ F (c) F -
ab + b c + cd + de (( a b) ' + (c» + (d + e f) ,
2. IS Conven each of Ihe fOllowing equation; direell y 10 gale- leve l C"ClliL'. (a) F - abc + a' bc
89
+ a e + f' (c) F = (a + b) + (c ' * (d + e + f9» (b) F -
fu-s
2.25 Le i variab les 5 represenl n pockagc being -mall. H being he3\). and £ being <\pensl\e. Let", co ns ider a package th aI b not small as big. nO( heJ.\') ~ light. and not c:\pensl\~" \ nsi"c. \ rile n 8 00lean equmion I represent Ihe fOllowing:
90
~
Combinat ional Log ic Design
2.14 Exercises
inexpen sive.
.
(b) You can NOT deli ve r a package Ihal IS
r
15
b
led above. Use nlgebru to simplify th e eq ua tion .
10 sum -of-products . k I 'f Ihe pockoges "rc small and lighl, small (c) You can load the pac bges into you r truc on ~ I . S' rfy Ihe equallon . and heavy. or big and light. IInp I "b d ' bove Simplify to sum -of-products. OT I d h packaoes descn ea . (d) You can N oa l e , . o I ' equarion (0 sum-of-products form: 2.26 Use algebraic manipu lation to convert the fol OWing (b - c)(d ' ) + ac ' ( b + d ) F a aloebrnic + h followin 2.27 Use manipu lation to conve rt te d )'o equation to sum-of-products ronn: a ' b( ; + d ' ) +a ( b ' + c) +a ( b+ c.. +a 'b
.
f the following equatio n: F
;;;:
abe
c
F
a o a
a
0
0
a o o o a
T}BlE 2.10
~·S
a
G
b
c
F
a
1
c>
a
c:- - - f igure 2.65 Combinalional circuil C.
2.35 Fill in Tab le 2.S's columns for Ihe equalion: F- ab + b ' . TABLE 2.8 Truth table,
a a
d
a
o o a a a
1
a
2.34 Convert each of lhe foll owing Boolean equalions 10 a !ruth table: (a) F ( a , b . c) = a' + bc ' (b) F( a , b , c) = ( ab ) ' + a c ' + bc ab + a c + a b ' c ' + c ' (c) F( a , b , c ) (d) F ( a , b , c , d ) = a ' bc + d '
Truth table.
0
2.3 1 Creme a Boolean equation representalion of the dig ital circuit in Figure 2.64.
10
an equalion. Don'I minimize
2043 Creale a lrulh table for Ihe circuil of Figure 2.65.
--.a
c'
2.33 Convert each of Ihe Boolean equalions in Exercise 2.30 lrulh table.
10
2.41 Use algebraic man ipulat ion to minimize rile equation obtained in Exercise 2AO, 2.42 Creale a lrulh table for Ihe circuil of Figure 2.64.
2.4~
(J
2.32 Create a Boolean eq uat ion repre entation for the dig ital circuit in Figure 2.65.
b -----r~
2.37 Use algebraic manipulafion to minimize the equation obtained in Exercise 2.36.
Convert Ihe funclion F shown in Ihe lrulh lable in Table 2.9
10
a digital circui t.
2.45 Convert Ihe funclion F shown in Ihe lrulh lable in Table 2. 10 10 a digital circuit.
SECTION 2.6: REPRESENTATIO S OF BOOLEAN
(d) F ( a . b , c )
an equation. Don't minimize
2.39 Use algebraic manipulation to minimize the equaLion obtained in Exercise 2.38.
'
Figure 2.64 Combinalional circuit F.
10
2.40 Convert the function F shown in the truth table in Table 2. I I to an equation. Don't minimize the equat ion.
.
FU CTIONS . 2.30 Convert Ihe following Boolean equalions 10 a digi lal circ u,,: (a) F (a , b , c ) a ' bc + a b (b) F ( a , b , c ) a' b (c ) F( a , b , c ) abc + ab + a + b + c
2.36 Convert the functi on F shown in the truth table in Table 2.9 [he equation.
2.38 Convert Ihe funclion F shown in Ihe lrulh lable in Table 2. 10 the equation.
1
a a
2,28 Usc DeMoroan's Law 10 find Ihe IIl verse 0 . F ' = ( a bc + a ' b) , e r Hint' Stan wllh Redu ce 10 sum· of-products ,om1. . . ' .F _ ' + a bd' + ac ' 9 Use DeMorg an's Law to find the .In verse 0 f the follo\\llOoe equation . PLU·S _.- acd . Reduce 10 sum-of-produc ls fom1 .
o
91
TABLE 2.9 Truth table.
k "'S are either small and c,'
o Truth table.
TABtE 2.11
b
c
F
o a
a
o
1
1
a o o
a a a
a
o
a
o o a a
a
2.46 Convert the function F shown in the truth table in Table 2, 1J to a digital circuit. 2.47 Convert th e following Boolean equa tions to canonical sum-of-m imenns fonn: (a) F ( a , b , c ) a ' bc + a b (b) F (a , b , c) a'b (c) F(a , b, c) a bc + ab + a + b + c (d) F (a , b , c) c' 2.48 Delenn ine whelher Ihe Boolean funclions F ( a + b ) ' *a and G equivalen!. using: (a) algebraic manipulation. and (b) !ruth lables.
a
T
b' are
2.49 Detennine whelhcflhe Boolea n funclion s F = a b ' and G = ( a ' + a b) ' are eq ui\'alenl using: (a) algebraic manipulalion. and (b) lrulh lables.
2.50 Delennine whelher Ihe Boolean funclion G _ a 'b'c + ab' c + a bc ' + abc isequivalent to the function represented by the circuit in Figure 2.66.
b H
2.51 Determ ine whether the two circuits in Figure 2.67 are eq ui va lent circuits using: (3) algebraic manipulalion. and (b) lrulh lables.
Figure 2.66 Combinational irruil H.
G
Figure 2.67 Combinntional circuils F and C. . 2.52 · Figure 2.68 shows two circuit~ in \\ hich Ihe- inputs of the cirt'uil'\ Jre un~;)tx-Ied_ (a) Dctenninc whether the 1\\ 0 circu jt~ arc cquh-ak nl. Hint : Tr) ;1JI ~l\.)'~I t'tle IJ~hng' ,)t lM inpulS fi r both circuit:"
92
Combinational log ic Design
2.14 Exercises
' . ,'II au need 10 perform to dc temli nc if IWO circuits with (b) How many circ uli compansolls ,\ I Y 10 unlabeled inputs arc C(lui va lenl ? ..
D
Dr>-F
2.60
Sh~w the conduction pmhs and ou tput va lue of the NAND gale transistor circuil in Figure 2.4) when: (a) X = 1 and y = O. (b) x = 1 and y z 1.
2.61 Show Ihe eonduelion parhs and OUlpUI valu'e of Ihe NOR gale lransislor eireuil in Figure 2"+5 when: (a) X = I and y - O. (b) x - a and y = O. 2.62 Show the conducti on paths and output va lu e of the AN D gale lransislOr circuit in Figure 2.46 when: (a) X = 1 and y - 1. (b) X = a and y _ 1. 2.63 Two people, denoted using variables A and B, wanl (Q ride with you on your mOlorcycle. Write <'1 Boolean cquUlion that indicates thaI exac lly one of the Iwo peopl e can come (A=l means A can cOllle, A=O means A can ', come). Then use X OR 10 si mpli fy your equation. 2.64 Simplify Ihe fo llowing equarion by using XOR wherever possible: F = a ' b + ab' ~ cd ' + c ' d + ae.
G
Figure 2.68 Combinalional eireuils F and G. SECTION 2.7: CO/l'IBI NA TIONAL LOGIC DESIGN PROCESS 1.53 A mu seum has three rooms. each with a IllOlion sensor (m O. ~1. and m2) ,thai outputs 1 when moti on is detected. At nigh!. the only person in the museum IS one s~c unly guard who wal~ from room to room Create a circuit thai sounds an alaml (by CUing an output A to l ~ Ir nlOl ion is ever dClcc;ed in more than one room at a lime (i .e~ . in two or three rooms). meanmg there must be an imruder or inlnJders in the museum. Start with a truth table.
2.54 Creale a cireuil for the musem of Exercise 2.53 thaI delccls whelher the guard is properly patrolling the museum. detected by exactly one mOlion sensor being 1. (If no mOlion sensor is 1. Ihe guard musl be sining or sleeping.) 2.55 Consider the museum security aJarrn function of Exerci se 2.53. but, for
sages musl be rese n!. Using the eombinarional design process of Table 2.5. creale a collision detec tion circuit for a router that connects 4 computers. The circuit has 4 inputs labeled MO th rough M3 th aI are I when Ihe corresponding compuler is
2.57 Using Ihe eombinalional design process of Table 2.5. creale a 4· bil prime number deleclOl. The eireuil has four inpu ts. N3. N2. NI. and NO Ihar corre'pond 10 " 4-bil number (N3 is the most ~ i gni ficam bit) and one output named P Ihal outpUl!oo a 1 when th e input is a prime number or 0 otherwise.
2.65 Use XOR odd.
10
creale " cireuil thaI OUIPUIS a 1 when the num ber of Is on inputs a. b. c. d i
2.66 Use XOR or.XNOR
[Q
creme a eireuil Ihal deleclS if al l inputs a. b. c. d are as.
2.67 Use XOR or XNOR are Is.
10
creme a eircuil Ihal de leels if an even nu mber of rhe inputs a. b. c. d
2.6S Show Ihal a 4-bi l XOR gale is an odd funelion (meaning Ihe OUIPUI is 1 only if rhe number of inpUI Is is odd). SECTION 2.9: DECODERS AND MUXES 2.69 Design a 3x8 decoder using AND. OR. and NOT gates.
2.70 Design a 4" 16 decoder using AND. OR. and NOT gales. 2.71 Design a 3x8 decoder with enable using AND. OR. and NOT gares. 2.72 Design an 8x I mu hi plexer using AND. OR . and NOT gales. 2.73 Design a 16xl muhiplexer using AND. OR , and
OT gales.
2.74 Design a 4-bit 4x I rnull iplexer using 4x I multiplexers. 2.75 Create a circuit th at rings a bell whenever motion is dClccrcd from one oflwo motion .sensors. A switch 5 determines which sensor to pay allention to: 5=0 means ring the bell when there's moti on at motion sensor 1. 5=1 means motion sensor 2.
2.76 A home enlenainmenr cenler has four differenr audio ourees thar can be pla)ed over rhe same sel of speakers. Each aud io Source. named A. B. C. and D. is eonnccled using " ires on "hieb the digitized audio signal is tmnsmiued. The user seleclS wttich audio Duree i.:,
=
SECTION 2.10: ADDITIONAL CONSIDERA TIONS 2.78 Design a Ix 8 de muhiplexer using AN D. OR. and NOT gale . 2.79 Design a 4x2 encoder using A D. OR. and NOT gales.
5-bil binal) number. Create a circuit that iliumlllarcs a "low tire prc.."'''iurc'' inthc;.lIor fift ht (by setting an YOIl
mighl find
II
""'Ier 10 ereale l
ci rCUli that detccl,lhe invcl'M! ru nction. You can lhcnjU"i1append an IIlvencr 10 'he outpul circuit
ort~
be pla)ed
output the user's selec ted audio source.
2.-9 A car has a low- ti re-pre\'~u re ~ nsor Ihat outputs the current lire prc ...... ure as
3
10
using a rolary swilch wilh four OUlpUIS. 5 O. 51. 52. 53 . of which e.• a tI) one wil1 be . . al any give n lime. If 5 a = ' I ' . Ihe audio souree A shoul d be pla)ed. if 5 I = 'I '. rhe audio B should be played. and so on. Creare a digilal cireuil \Virh a single -bit ourpur a thaI "ill
2.58 A car has a fuel-level deleclor th aI OUlpu ts Ihe currenl fuel-level ", a 3-bil binary number. wirh 000 mea ning emply and III meaning full. Create" cireuil Ihal ilium in:!le, a " low fuel" indio calOr lighl (by , cuing an OUlpO! l 10 1) when Ihe fucl level droJl~ below level 3.
OUIPUI T 10 I) when the lire pre"ure drops below 16. Il in!:
93
SECTION 2.8: MORE GATES
2.77 Design a 1..4 demulriplexer using A D. OR. and NOT gores.
2.110 Design an 8x3 encoder using AND. OR. and
OT gale . . , ume rhal onl)
Oil<'
inpul will be
I ;.11 any given time. 2.8 1 Design 3 -'-':2 priori t)' encoder usi ng
a is encoded as 00.
D. OR. nnd NOT gales. ""urne th;u e\
9-1
2 Combinational Logic Design ~
DESIGNER PROFILE
experience. "For the sma ller team projc~l . each pe~on had more responsibility. and overull effiCiency was high. focu sed his advanced For the lame team project. each per!;on worked on a i<.lUdics on integrated spec ific pa'; of the project-the chip lVas div ided into circuit (Ie) design. clu sters. each clu ster into units. and each unit had a be lieving the industry to leader, We relied heavi ly on design nows and ha ve a great future. methodologies." Years laler now. he Sam son has seen th e industry's peaks and valleys reali zes he was right: during th e past IwO decades: "Li ke any industry. the Ie "Looking brick 20 years job market has ils ups and downs." He believes the in high tcc h. we have industry survives the low !>oims in large pan due to experienced four major "innov3lion:' "Brand name sell products. but without revo lutions: the PC innovation , markets go elsewhere, So we have to be very rc\ OiUlion. digital rC\Olulion. cOlll l1luni ca ti on revolution. innovati ve, crea ting new products so lhal we are always Jnd Internet rc\oJution-all four enabled by the Ie ahead in the e:lobal competition," indul.,ll') . The impacl of these revolutions 10 ollr daily life But. "inno~alion doesn't grow on trees ," Samson points is profound:' out. "There are two kinds of innovations. The first is He has found his job to be "vcry challenging. invention. which requires a good unders tanding of the interestin!! . and exciting. I cO lllinually learn new skills to physics behind technology. For example. to make an keep up. ; nd to do m~ job more efficicm ly:' analog TV into a digi tal TV, we must know how human One of SJmson's key design projects was for digital eyes perceive video images, whi ch parts can be digitized, television. namely. high-definition TV (HDTV). involving how digital images can be produced on a silicon chip. elc. companies like Zenith, Philips, and Intel. In particular, he The second kind of innovmion reuses existing technology led the 12-person design teal11 that built Inters first Liquid for a new application. For example, we can reuse Crystal on Silicon (LCoS) chip for rear-projection HDTY. ad vanced space technologies in a new non-space product "Traditional LCoS ch ips are analog. They apply different serving a bigger market. c·8ay is ano ther example-it analOR voltage.. on each pixel of the display chip so it can reused Internet technology for on-line auctions. produ~e an image. But analog LeoS is very sensitive to Innovations lead 10 new products, and thus new jobs for noise and temperature variation. We used digital signals to many years, do pube width modulation on each pixel." Samson is
quite proud of his team', accompli,hments: "Our HDTV picture quality was much bener." Sam son also \\-orked on the 200-mcmber design team for Inlers Pentium II processor. Thai was a very differen!
Thus. Samson point out that ''The industry is counting
on new engineer from college to be innovative. so they
can continue to drivc the high tech industry forward. When you graduate from college. it'~ up to ),011 to make things beuer."
~3
Sequential logic Des ignCo ntro" e rs 3.1/NTRODUCT/ON The output of a comb ina tion a l circu it is a function o nl y of the circuit's present inputs. A combina tion a l c irc uit has no me mo ry-we cannot to re bits into a combinational ci rc uit a nd later read the bits o ut th at we saved. Combinational circuits by them eh' are rather limited in the ir usefulness. Desig ners ins tead typicall y use combinational circ uits as part of larger c irc uits called sequ entia l ci rc uits--circuits that do have memon . A sequel/tial circllit is a circuit w hose o utputs depend not only on the circuit's prese~t inputs, but also o n th e c irc uit 's present state, which is all the bits stored in the circuit. The circuit 's s ta te in turn depends on the past sequel/ce of value that ha\'e appeared at the c irc uit 's inputs. An everyday example of a combinational circuit i a doorbell-push the button (the input) now. and the bell (the o utput) rin gs. Push the butt on again. and the bell rings again. Pus h the button tomorrow. o r next week. and the bell ring the arne en h time. A doorbell has no state, no memory-its o utput value (whether the bell ring or not ) depends solely on its present input value (whether the button i pressed or not ). In ontnst. an example of a sequentia l circuit is an automa ti c garage door sy tem-pu h the button (the input) now. and the door opens. Push the button again. and this time the door loses. Pu b the button tom orro w. a nd the door opens again. The system' output (\\ hether the door opens or closes) depends o n the s ta te of the system (whether the door is pre. entl~ open or closed). which in [urn depe nds on the sequ ence of pasl input value in e we turned on the ystem . Most di gita l sys tem with which you are familiar in\'oh e sequential cin:-uits that store bits. A handheld ca lculator mus t contain a sequential cin:-uit. because [he ,'a/culator mus t store the numbers you en te r. in order to operate on tho ' e nWllbe~. A digital amen s tores pictures. A traffic lig ht controller store. infonnmion indicaring \\ hi h light i. prese ntly g reen. A c ircuit t.h at counts d wn from 59 to 0 Stores the present 'l'unt \ alu', to kn ow what the nex t val ue should be. In th is c hap ter. we describe ba~ic sequential ireuit building bl 'I..s. Jnd th- d "tgn 01 a cennin c1a~~ of sequential circui ts kno\\ n as c ntrollers .
.
---~
. --
-
96
3 Sequential Logic Design-Contro llers 3.2 Storing One Bh-Flip-Aops
3.2 STORING ONE BIT-FliP- FLOPS To build a sequential circui!. we need a Call ~_r---, Blue light building block that enables us to store a buHon ~ bi!. By store a bi!. we mean that we can save a bit in the block (say a 1) and latcr Cancel~ ~ bunon come back 10 see what we saved. As an example. suppose we want to bui ld the fli ght attendant call-button system in Figure 3.1 Flight attendant ca ll-button Figure 3.1 . An airline passenger can push system. Pressing Call turns on the light, the Call bunon to tum on a small blue which stays on afl er Ca ll is released. Pressing Cancel turns otT the light. light above the passenger's sea!. indicati ng 10 a fli ght attendant that the passenger . needs service. The light stays on even after the call button is released. The hght can be turned off by pressing the Callcel button. Since the light has to stay on even after the call button is released. we need a way to " remember" that the call button wa pressed. We can remember by u ing a bit storage block. and storing a 1 in the block when the call button is pressed. and storing a 0 when the cancel button is pressed. We connect the output of this bit storage block to the blue ligh!. The light illuminates when the block's output is 1. To introduce the internal design of such a bit storage block, we' ll introduce several increasi ngly complex circuits able to store a bit-a bas ic SR latch. a level-sensitive SR latch. a level-sensitive 0 latch, and an edge-triggered 0 flip-flop . The 0 flip-flop will then be used 10 create a block capable of storing multiple bits, known as a register, which will serve as our primary bit storage block in the rest of the book. Each success ive circuit elimi. nates some problem of the previous one, leading to the robust 0 Rip-flop and then register. Be aware that designers rarely use bit storage blocks other than 0 flip-nops. We introduce the other blocks primarily to provide the reader with the underlying intuition of the 0 flip-flop 's design.
Feedback-The Basic Storage Method The basic method used to store a bit in a digital circuit isfeedback . You've surcly experienced feedback in the form of audio feedback, when omeone talking into a microphone stood in front of the speaker. causing a loud continuous humming ound to come out of the speake~ (in tum causing everyone to cover their ears and snicker). The talkcr gcnerated a sound that was picked up by the microphone, came out the peakers (ampli fied), was picked up again by the microphone, came out the speakers again (amplified even more), etc. That' feedback. Feedback in audio systems is annoying, but in digital sy terns is ex tremely useful. Intuitively. we know that we need to somehow feed the output of a logic gate back into the gate itself, so that the stored bit ends up looping arou nd and around, like a dog chasing its own tail. We might try the circuit in Figurc 3.2. Suppose initially 0 is 0 and 5 is O. At some poi nt. uppose we set 5 to 1. That ca uses 0 to become 1. and that 1 feeds back into the OR gate, causing 0 to be 1. ctc. So even when S rctums Ftgure 3.2 FiNt (failed) attempt at u\lng fecdbxk to O. 0 stays 1. Unfonunmely, 0 St;ty~ 1 from then on. and we
Srf2j-
to '-lore a bi!.
have no way of reselling 0 to O. But hopefully you understand the basic idea of feedback now-we did successfully store a 1 using feedback. . We draw in Figure 3.3 the timing diagram for our attempted feedback circuit from Ftgure 3.2. NOIe that we assume the OR gate has a small input to output delay, as was discussed in Section 2. 10. Initially, we assume both OR gate inputs are 0 (Figure 3.3(a)). Then we set S to 1 (Figure 3.3(b», which causes 0 to become 1 slighlly later (Figure 3.3(c» , which in tum ca uses t to become 1 lightly later (Figure 3.3(d». Finally. When we change S back to 0 (Figure 3.3(e». 0 will stay 1 because t is I. The firsl curved line with an arrow indicates that the event of 5 changing from 0 to 1 cau es the eVent of 0 changing from 0 to 1. The second curved line with an arrow indicates that the eVent of 0 changing from 0 to 1 in turn causes Ihe eVent of t changing from 0 10 I. And that 1 then Continues to loop around, forever, with no way of 5 resetting 0 to O.
S~ t
f
Q0
~l2J-~l~~ ! (a) :
;
~L
\
\
~C},:
(b)
'
' ----fei) -'
(e)
/-;f'/
(
~)f-;£":;'~/__/_/_---__________ 0 stays 1 forever
\,
Figure 3.3 Tracing the behavior of our first attempt at bit storage.
SR Latch Basic SR Lalch It turns out that the simple circuit in Figure 3.4. called a basic SR latch . implements the bil slOrage building block we desire. The circuit consists of just a pair of cross-coupled NOR gates. Making the cireui!"s S input equal to 1 causes Q to become 1. while making R equal to 1 causes Q 10 become O. Making both 5 and R equal to 0 causes whatever value 0 i. 10 keep loopi ng around. In other words, S "sets" the latch to 1. and R "resets" the latch to O-hence the lellers 5 (for set) and R (for reset). Let's ee why the basic SR lalch works as it does. Recall that a OR gate outputs 1 when all the gate 's input ' equal 0; if at least one input equals 1. the NOR g1tle outputs O.
s
o Figure 15
R latch \\ hen
0-----
o
=0 and R =I.
98
3 Sequential Logic Design- Conlrollers
3.2 Storing One Bit- Flip-Rops S k 5 0 d R-l as in Ihe SR Imch ci rcuil or Figure 3.5. and that . e bOllom 'ate or Ihe cireuit has at uppose. lhm we ma 'c = an - . • we don'l 11lIllally know the va illes or 0 and t. SlI1ce Ih . . g. . 1 . becoming equal 10 1 (R). the gale oulPUIS 0- in Ihe IImlll "O dlagrmn. R. . leasl one IIlpUI callScs 0 10 become O. In the circuil. O's 0 reeds back 10 Ihe lap OR ga te. wh Ich WIU have . OUIPUI equaI Ia 1. In the limin "o dIagram. 0 becoming 0 bOlh li. S .IIlPUIS equal 10 0 and liS . callses t 10 become 1. In Ihe cirell il. thai 1 reeds back 10 Ihe bOllom OR gale. whIch has al leasl one inpul eqllal 10 1 (nclUnlly. bOlh inpuls equal 1). and so Ihe botiom gate will contin lle 10 Oll lplll O. Thlls the OUlp11l 0 equals O. and all values are slable. Now suppose we make 5=0 and S 1 R=O . as in Figllre 3.6. The bOllom gme 0---- slill has aI leasl one inpu l equal 10 1 (Ihe input coming rrom the top gale). so the
botiol11 gale cOlliinues 10 OIl IPUI O. The lOp gale cOlllin lles 10 have bOlh inpu ls equal 10 0 and cOlllinlles 10 OUlpu l 1. The OUlpUi 0 willihus slill eq ual O. Thus Ihe earli er R= 1 srored a 0 inlo Ihe SR lalch. also known as resellillg Ihe Ialch . and Ihal 0 remains slOred even when we Figure 3.6 5R laleh relUm R 10 O. when 5=0 and R= O. Now lei's make 5= 1 and R=O . as in afler R equaled I. Figure 3.7. The lap gale in the circuil now has one inplII cqual 10 1. so Ihe lap gate ou tputs a O- the liming diagram shows Ihe change or 5 rrom 0 10 1 causing t 10 change from 1 10 O. The lOp ga le'. 0 OUIPUI reeds back 10 Ihe ,_ - 1 _----- 0 botiom gale. which now has both inpUis \. . . :><.: ,. ,. ", equa l 10 0 and OUIPUIS l - Ihe limi ng \~Q di agram shows Ihe change or t rrom 1 10 0 causing 0 10 change rrom 0 10 1. R=O The botiom gale's (0) 1 OUiPUI reeds Figure 3.7 5R Inlch back 10 Ihe lap gale. which has al leasl when S= I and R=O. one inpu l equal 10 1 (ac lUally. bOlh inputs equa l 1 now). a Ihe lap gale conlinues 10 OUIPU I O. The OUIPUI 0 Iherefore equa ls 1. and all va lues are slable. _---- 0 I ow lei's make 5- 0 and R=O aga in , ,_ - t , a, in Figure 3.8. The top gale slill has aI leasl one inpu l eq ual to 1 (the inpul Q comi ng from the botiom gale). so the lOp gale cOnlin ue, 10 output O. The botiom R=O ga le cOnli nuc, 10 have bolh inputs equa l Figure 3.8 SR laleh 10 a and eOnlinue, to oU lpul I. The when 5=() and R =0. ou ipul 0 " 51ill eq ual to I. Thu" Ihe aflcr 5 equaled I.
o
Level-Sensitive SR Latch A problem wilh Ihe bas ic SR Ialch is 5 and R both equaling 1 al Ihe same time causes
Q
0
S
~
0
R 0
- ---------1
~ --
earlier 5= 1 stored a 1 into the SR latCh, also known as sellillg Ihe lalch, and thai 1 remains slored bunon even when we relU rn S 10 O. The basic SR Ialch can be used 10 implemenl the flighl allendant cal/-bullon syslem (Figure 3.9). We conneCI the ca ll bUllon 10 5, Ihe Cancel cancel button 10 R. and Ihe lighl 10 bunon O. Pressing Ihe call bUllon sels 0 10 I, Ihus lurning on Ihe lighl. 0 stays I even when the call button is Figure 3.9 Flight auendant caIJ-bulton system using a basic SR laleh. released. Pressing Ihe cancel bUllOn reselS 0 10 0, Ihus turn ing orf the lighl. 0 Slays a even when Ihe cancel bUllon is released.
unden ned behavior-we mighl have stored a I, we mighl have slored a 0, or we might even cause Ihe latch ourp Ui 10 oseillale from 1 10 0 10 1 10 O. and so on. Lei's ee wby. If 5 = 1 and R= I, both gales have at leasI one inpul equal 10 1. and thu both gate OUlput 0, as shown in Fig ure 3. 1O(a). A problem occurs when we rerum 5 and R 10 O. Suppose 5 and R rerum to 0 al exaclly the same time. Then both gates will have all 0 ar Iheir inpulS, so Iheir ourp uls wi ll change from Os to Is. as shown in Figure 3.1 0(b). Those Is feed back 10 the gate inpuls, causing Ihe gates 10 OUIPUI as. as hown in Figure 3. IO(c). Those as feed back 10 the gale inputs again. causing the gates to OUtpUI Is. And 0 on. Going from I 10 a 10 1 10 0 and so on is cal/ed oscillation . Oscillation is not a de irable fealure of a bil slorage block.
0
Q
0
~~
S
R
\~::: :~------- 1
0
Figure 3.1 0 The silUation or S = I and R = I causes problems-Q as il/Oies \\ hen R re!Urn 0
Q
0
to
00.
In a real circuil . the delays or Ihe upper and lower gales and wires lI ould b.! ,tightl~ different fro m one anot her. a after a lime of os illation. one of the gale. ma~ gel ahead of the olher (Ou lpu ll ing a 1 before Ihe other d . then a 0 b.!fore the other on de -, cle.). II ntil it gets rar enough lI hend to cause the cirt'uil I enler a ~Iable siluati n of ither OaO or 0= I-which case will happen. li e don'l knOll . u 'h a ~irualion. in IIh,,-h th· tinal
99
100
Sequential Logic Design-Controllers 3.2 Storing One Bit-Flip-Flops
value of a memory circuit depe nds on the delays of gates and wires, is known as a race condition . Figure 3. 11 shows a race condit ion involving oscillation but end ing with a stable situation of 0: I. But we did n' t know wh ich value 0 wou ld eventually sellie into (it could have settled into 0:0), so Figure 3.11 Q eventually seliles to the fact that 0: I is not useful to us in our use of ei ther 0 or I. due to race condition. the bit storage block. In our fl ighl attendant call -bullon system, if the passenger pushes both buttons at the same lime. the result could be thallhe blue light slarts osc ill ating. and then Ihe lighl either ends up on or off. 5 and R should In summary. Sand R should never both equal 1 in an SR lalch. flt'I'U bOlh equal In practice. we would never aClually conneci buttons directl y to an SR latch's inputs I in all SR lotch (we did Ihal just for the purpose of an intuiti ve example). So we can safely ass ume the S and R inpuls come from a digi tal circuit. Thus. we can desig n that digi lal circuit such thai 5 and R should never both equal 1. BUI even if we Iry 10 design Ihal circuit such thai S and R sho uld never both be 1. we could still fi nd that S and R inadvertentl y bOlh become I at the same time. For example. cons ider the simple circui l in Figu re 3. 12. In Iheory, S and R can' l both be I -if X:l. then 5: ] bUI R:O . If X:O. R may equal 1 bUI 5:0. So S and R can' l both be I -in Iheory. In rea lilY, both 5 and R could both be ] for a short lime in Ihis circuit. because of the delay of real gales. as introduced in Figure 2.62. Suppose X has been and Y has been ] for a long time, so 5:0 and R: l. Then suppose we change X 10 1. 5 wi ll change 10 I almost immediately. but R will stay] for a short while as the new value of Xpro!>, agates Ihrough the inverter and Ihe AND gate, after which R changes to O. If each componenl has a delay of I ns (nanosecond). then 5 and R wou ld aClu ally both be I for 2 ns (Figure 3. 13). Temporary values on ignals ca used by ga te delays are referred 10 as glitches.
a
' . --1J," .'
' ,!.'::-'' "--------
1
Figure 3.12 Conceptually. Sand R can' t both be I in thi' sample circuit. But in reality. they can. due to the delay of the invene r and AND gate.
A
I
~
:
: SA = 11
1~ ' /! :\
o
A
Figure 3.14 Level-sensitive SR latcban SR latch with enable input C.
The introduction of the enable input leads 10 the idea of setting the enable to I only when we are sure that Sand R have stable val ues. Figure 3.15 shows the inverter/AND circuit from Figure 3.1 2, this time using an SR latch with an enable inpu t. If we change X, we should wait for at least 2 ns before setling the enable input C to 1 in order to ensu;:' that the SR inputs to the latch are stable and are not equal to II . Level·sensitive SA latch
S~~ 1
R 0
: '.. _
'
il'--+-----
c~ 1 ; i r IL S1~
:
>2ns Figure 3.15 Level-sensitive SR latch-an SR latch with enable input C.
! ;
o
o
c
: !'
o~
y
S
Level'sensitive SA latch
~'-----------
1
I
I
figure 3 13 Grllc delny' Con cau,c SR = II.
101
S
l---f-, : .L...;;_ _ _ __ Rl 0
, X
A partial solution to this problem is to add an enable input C to the SR latch. as shown in Figure 3.1 4. When C:l, the S and R signal s propagate th rough Ihe two AND gates to the S I and Rl inpu ts of the basic SR latch circuit , because S*I:S and R*I=R. However, when C:O, the two AND gates cause S I and Rl to be O. regardless of the values of S and R. Thus, when C:O, the basic latch 's value cannot change. (You might note that a difference in the lOp and bottom AND gate delays could result in S I and RI both being I for a very short time equal to that difference, but that time is too short to cause a problem.)
An SR latch with an enable is lenown as a level-sensitil'e SR latch . beeau e the lat h is only sensilive to its S and R inpu ts when the level of the enable input is 1. uch a Iat b is also called a transparent latch, beca use setting the enable input 10 1 makes the internal SR latch transparent 10 the 5 and R inpulS. You may have noticed tllal the lOp NOR gate of an SR lalch outputs the opposite val ue as the bottom gale, which i connecled 10 the oUlput O. Thus, we can include an o utput 0' on an SR lalch almost for free , j ust b connecting the top gate to Ihat out put. Mosl latche ' do in faci come with bOlh 0 and 0 ' outpul . The symbol for a Figure 3.16 ymbol for level-sensirive SR IMCh wilh such dual outputs is hown dual-{lU(put 10\ ek nsnh in Fig ure 3. 16. R lalch.
102
3 Sequential Logic Design- Controllers 3.2 Storing One Bn-Flip-Flops
Clocks and Synchronous Circu its ble si nal C that we must sct to 1 a rter we are The level-sensitive SR latch uses an ena gd h to set the enable C to I? Most bi B t how do we decI e w en 5 d R sure an are sta e. U '0 al that ulses at a constan t rate. For example, sequentia l circuits simply use an enableslon, I0 ~s then low for IOns, then high for we could make the enable SIgnal go hIgh for ' 10 ns, then low for 10 ns. etc .. as in Figure 3. 17. Freq.
X. Y safe 10 change must not change X, y
100 GHz 10 GHz 1 GHz 100 MHz 10MHz
/~,
t
elk
o
o
Figure 3.17 An example of a clock signal named elk. Circuil inputs should only change while z 0, such that lalch inputs will be stable when e lk - I .
elk
The time high and time low need not be the same-for example, we cou ld create a . . signal that is low for 10 ns, high for I ns, low for 10 ns. hIgh for I ns. etc . Such a pulsing enable signal is called a clock signal. because the Ignal licks (hIgh, low, high. low) like a clock. A circuit whose storage elements (Ill thIS case. latc.hes) can only change when a clock signal is ac tive is known as a sync hronous sequenttal CirCU li, or j ust synchronous circllit (the sequential aspect is implied-there's no such thlllg as a synchronous combinational circuit). A sequent ial circuit that does not use a clock is caHed an asynchronous circllit. We leave the important but cha llengi ng topic of asynchronous circui t design for a more advanced di gital design textbook . The majori ty of seq ue ntial circ uits designed and used today are synchronous. Designers typicall y use an a ci llato r to generate a clock ignal. An oscillator is a circuit that outpu ts a signal that aitemates between I and 0 at a constant freq uency, like that in Figure 3. 17. An osci llator component typica ll y has no inputs (o ther than power), and has an output representing the clock signal. ~
HOW ODES IT WORK?-OUARTZ OSCILLATORS,
Concept u al l y, a n oscillator can be thought of as an inverter feeding back to itself, as shown on the left. If C is initially 1, the value will feed back through the inverter and so C will become 0, which feeds back through the inver1er causing C to become 1 again, and so on. The oscillation frequency would depend on the delay of the inverter. Real oscillators mu t regulale the oscillation frequency more precisely. A common type of oscillator uses qULJrlZ, a mineral consisting of silicon dioxide in crystal (arm. Quartz happens to be such that it vibrates i( we apply an electric current, and thaI vibration i, at
a precise frequency determined by the quartz size and shape. Furthermore, when quartz vibrates, it generates a voltage. So, by making quanL a specific ,ize and shape and then Oscillator Ie applying a current, we ge t a preci,e electronic o,cillator. We attach the o«illator 10 an IC', clock slg"al input, a' shown above. Some IC, come with a built-Ill osci liator,
Period 0.01 ns 0.1 ns
1 ns 10 ns 100 ns
103
. A c lock signa l's period is the time after which the signal repealS ilSelf-or mare SImply, the tllne between successive Is. The signal in Figure 3.17 has a period of20 ns. A clock cycle refers to one such segment of time. meaning o ne segment where the clock IS 1. and then O. Fig ure 3. I 7 shows th ree and a half clock cycle. A clock signa)'s frequ ellcy IS the number of cycles per second, and is compu ted as I/(the clock period). The slgn~1 III F,g ure 3. I 7 has a frequency of 1/20 ns = 50 M Hz. The units of frequency are Hert z, or Hz, whe re I Hz = I cycle per second. MHz is short for Megahertz_ meaning one mdl'on Hz. . A convenient way to menta lly convert common computer clock periods to frequenc Ies. a nd VIce ve rsa, IS to remember that a I ns period equals a I GHz (Gigahertz, meanll1g I bIllI on Hz) frequency. Then , if One is slower (or faster) by a factor of 10. the other is slower (or fas ter) by a fac tor of 10 a lso-so a 10 ns period equals 100 MHz. whde a O. I ns period equals 10 GHz.
D Flip-Flop While the SR la tch is useful for introd ucing the notion of storing a bit in a digital circuiL most c irc uits actua ll y use slightly more advanced devices. namely. D latches and D llipnaps, to store bi ts. Level-Sensitive 0 Latch-A Basic Bit S tore
Olaleh
The SR latch has the an noying problem of entering all unde fined tate if the 5 and R inputs are both I when the clock is high. Ensuring that we desig n c ircuits that don 't set 5 a nd R to both 1 imposes a burden on the deSigner. One way to relieve designers o f this burden is to instead u e a new type of latc h. called a D latch . shown in Figure 3.1 8. A D latch sto res whatever value is present at the la tch's D input when C= 1. a nd holds that val ue when C = O. Internally. the latch's D input connects to 5 d irectly. a nd to R through an inverte r. Fig ure 3. I 9 provides a timing diagram of the D latch for sample input values on D and C. When D is I a nd C is 1. the latc h is et to 1. because 5 is I and R is O. When D is 0 and C is 1. the la tch is reset to O. because R is 1 a nd 5 is O. By making R the opposite of S. we are ass ured that 5 and R won 't both be I at the sa me time. as long as we ani c hange 5 and R when C is O.
The symbol fo r " 0 lalch wilh dual-oUlpU IS (0 and 0 ') is shown in Figure 3.20. Figure 3.20 D larch symbol.
--fo+
o lalch
~
Edge-Triggered 0 Flip-Flop-A Robust Bit Store The 0 latch slill has a pOlentially nasly problem Ihat can Ca use unprediclable circuil behavior- namely_ signals can propagale from a lalch OUlpul 10 an olher lalch's inpul while the clock signal is 1. For example, consider Ihe circui l in Figure 3.2 1. When e lk = I. Ihe va lue on Y wi ll be loaded inlO Ihe firsl lalch and appear al thaI latch's output. If ( 1 k slill equals I. Ihen Ihat value will also gel loaded into Ihe second latch . The value wi ll keep propagating Ihrough the latches umi l (1 k returns 10 O. Thro ugh how many la tches will the value propagale? It 's hard 10 say-we would have 10 know the precise tim ing delay information of each lalch.
Clkt==================--.J '---'--'---(a)
Clk~
01
0 2 02
03
03
04
_ _-..J
r , Too short-ol
01
0 1102
--.l '
01 /02 _ _ _ _ _ __
S2_______
S2===:t,)SR= 11
R2 _____________
02~dlalChsel 01
-
Clk ~e
01
R2
y
o latch
(b)
04
0 2 _ _ _ _ _ __ (e)
Figure 3.22 A problem wilh level-sensitive lalches: (a) while C~ 1. 01 's new value may propagale 10 D2. (b) such propagation can cause S2 and R2 10 both be 1 for a shan time while the latch 's enable is 1 (bul SR ~ 11 is never supposed 10 occu r). or can cause an unknown number of latches along a chain 10 gel updaled, (c) Irying 10 shonen Ihe clock's high lime 10 avoid propagalion 10 the neXl lalch, bUI long enough 10 allow a lalch 10 reach a slable feedback silualion. is hard. because making the c1ock's high lime 100 short prevents proper loading of the latch.
=-.....=_--l
Clk .....----+-__
Figure 3.21 A problem wilh lalches-through how many Ialches will Y propagale for each pulse of Clk_A ? For Clk_B?
Figure 3.22 ill uslrates Ihis propagat ion problem in more delail. Suppose 01 is inilially 0 for a long lime, changes 10 1 long enough 10 be stable. and Ihen C1 k becomes I. 0 1 wi ll th us change fro m D 10 I after aboul Ihree gate delays, and Ihus 02 will also change from 0 10 1. as hown in Ihe left timing diagram. If C1 k is slill 1. then thaI new va lue for 02 wi ll propagale through Ihe AND gales of Ihe second latch. causing S2 10 change from 0 10 1 and R2 from 1 10 D. Ihus changing 02 fro m 10 I, as shown in the left IlmlOg diagram. Also nOle in the left liming diagram that changing 02 whi le C2-1 causes S2 and R2 10 both equal 1 for a short lime, due 10 Ihe extra delay on the palh 10 R2 cau ed by Ihe Inverter. Ihough Ihe lime thaI bOlh are I is probably 100 short 10 cause a prob lem.
a
You mighl suggesl maki ng the clock signal such thaI the clock is I onl y for a shan amount of tl,,;e .. so there's nOI enough li me fo r Ihe new OUIPUI of a lalch 10 propagate 10 Ihe nexl lalch s mpulS. BU I how short is shan enough? 50 ns? IOns? Ins? 0. 1 ns? And if we ~ake Ihe clock's time m I 100 short, Ihat li me may nOI be long enough for the bit al a lalch s 0 mpullo Sl~btl l z~ m Ihe lalch's feedback circuil . and we mighl Iherefore nOI successfully Slore Ihe bll , as tl luslraled in Figure 3.22 (c).
A good solution is 10 des ign a more robuSI block fo r storing a bil- a block that stores Ihe bil al Ihe 0 inpul at Ihe illslalll lhal the clock rises from 0 10 1. Note thaI we didn 't say thaI the block Slores the bil inslantly. Rather, the bit thaI wilJ eventually get slOred into the block is Ihe bil Ihat was slable at 0 al Ihe inslal1l Ihal Ihe clock rise from to 1. Such a block is ca lled an edge-Iriggered D flip-flop . The word "edge" refers 10 the vertical pan of Ihe line representing the clock signal, when the signal !Tansirions from 10 1. Figure 3.23 shows three cycles of a clock signal. and indicales the Ihree ri sing Figure 3.23 Risi ng clock edges. clock edges of those cycles.
a
a
Edge-Triggered D Flip-Flop Usillg a Masler-Serllalll Desigll. One \\'a 10 design an edge-triggered D flip-flop is to use 111'0 D latches. as shown in Figure 3.24. The first 0 lalch. known as the mOSIer. is enabled (can slore new val ue on Om) \I hen C1 k is (due 10 the inverter). while the second D latch. known as the sen ·OIll. is enabled when C1 k is 1. Thus, while C1 k is O. Ihe bil on 0 is slOred into the masler lal h. and hence Om and Os are updaled- bul the servant latch doe nOI lore this new bil beenu Ihe serva nl latch is nOI enabled ince C1 k is nol 1. When C1 becomes 1. the mn ter
a
105
106
3 Sequential logic DeSign- Controllers
,
o flip·flop o lalch
o
Om
Om
o lalch Os
Os'
0'
Os 0 servant
,
Clk - - r - - - L ~O/Om
..'--,
i
Cm Om/Os
Cs
Os _ _ ---,c-'
Figure 3.24 A D fli p- flop implemenling an edge-lriggered bil slomge bolOCk. in l e r~a:I Ycut~ng ~w~ latches in a master-servan t arrangement. The master D i3lch slores 1,IS m Input W I e : : : : , UI lhe new va lue appearing al Om and hence al Os does 1101gel slored mlo the servant latch. because the servanl lalch is disabled when elk = O. When elk becomes 1. Ihe servanl D lalch becomes enabled and Ihus gelS loaded wilh whalever value was in Ihe mas'er lalch JUSI before elk changed from 0 10 1. latch becomes disabled (relai ns ils stored value), thus hold ing whalever bit was at the 0 input j usl before the clock changed from 0 to 1. Also, when elk is 1: the servant lalch becomes enabled. thus storing the bil that the master IS stonng. wh ,ch 's the bll thaI was al the D inpu l jusl before elk changed from 0 to I-hence implementing an edge-triggered storage block. The edge-triggered y 01 01 02 02 block using two inlernal 03 03 latches thus prevents the stored bi t from propagating thro ugh more Ihan one elk ....-===::.....~==::.....~ lalch when Ihe clock is 1. Consider the chai n of flip Aops in Figure 3.25. which is simil ar to the chain in Figure 3.25 Using D Rip-flops. we now know through how Figure 3.2 1 bUI with 0 Rip- many Rip-Rops Ywill propagale for C1 k_A and for C1 k_Bfl ops in place of 0 lalches. one Rip-Rop exaclly per pulse. for either clock signal. We know that Y will propagate Ihrough exactly one Rip-flop on each clock cycle. The drawback of a maSler-servanl approach is that we now need two 0 lalches 10 store one bit. So Figure 3. 25 shows four Rip-Aops, but Ihere are IWO latches inside each Aip-flop, for a tOlal of eight lalches.
__----'
The common
name ;s actually "master-slave... Some clroou insll!ad to use the term "servant "
due 10 some people finding lire
term "slave " offenSive. Others use the turns "primary.ucondary. "
There are many ahemati ve methods other Ihan the maSler-servant method for designing an edge-triggered Aip-Aop. In fac t, Ihere are hundreds of different designs for latches and Aip-flops beyond the designs we showed above, with those designs differing in lenns of their size, speed. power, etc. When we use an edge-triggered Aip-nop, we usually don'l worry aboul whether the flip-flop achieves edge-triggering using Ihe masterservant melhod or using some olher method. We need only know that the f1ip-Rop is edgetriggered, meaning the data value present when the clock edge is rising is the value thai gets loaded into Ihe flip-Aop, and that appears atlhe flip-fl op's outpul some time later.
-
-_._---
3.2 Sloring One Bit- Flip-Flops
107
We'~e aClually been describing whal's known a.• positive Or risillg edge-triggered flipAops. wh,ch are Inggered by Ihe clock signal going from 0 10 I. There are also Aip-Aops known as lIegati,'e or Jallillg edge-lriggered fl ip-ft0l s. which are triggered by Ihe Signal gOll1g from 1 10 O. We can build a negalive edge-triggered 0 flip-llop usi ng a maSler-servalll deSIgn where Ihe second fl ip-fl op 's clock inpul is invened. rather than the fi rst fli p- Aop 's. Posi tive edge-Iriggered fli p- fl ops are drawn using a small triang le al Ihe clock inpul. and negative edge-Iriggered fli p-flops are drawn USing a small Iriangle along wilh an in version bubble. as shown in Figure 3.26. Bear in mind thar all hough Our maSler-scrva l1l design doesn'l change Ihe output unlil Ihe railing Figure 3.26 Posili ve (shown on lhe clock edge. Ihe fl ip-fl op i slill po ilive edgeleft) and negalive (righl) edgeIriggered. because Ihe fl ip-flop Slores Ihe value Ihal Iriggered D fl ip. flops. The sideways was al Ihe 0 inpul al Ihe in' Wnl thm Ihe clock edge
In ill
j
riSing.
rriungle input rcprescnls an edge-
Iriggered clock inpul.
Latches ,'ersus Flip-Flops: Various lex lbooks defi ne the temls latch and fli p-nop differently. We'lI use what seems to be the mOSI common convention among des igners. namely:
A latch is level-sensilive. and • A jlip-jlop is edge-Iriggered.
So saying "edge-Iriggered flip-Rop" is redundanl , since flip-fl ops are by defin ilion edge-triggered. Li kew ise. saying "Ievel-sensilive latch" is redundant. since latches are by defi nili on level-sen ili ve. Figure 3.27 uses an example liming ,, diagram 10 illuslrale the di fference belween , level-sensili ve and edge-Iriggered bil IOrage blocks. The fig ure provides an example of a clock signal and a value On a signal D. The nex t signal trace is for Ihe 0 OUIPUI of a 0 larch, which as we know is level-sensili ve. The lalch ignores Ihe firs l pulse on D(labeled Q (0 latch) a 3 in the fi gure) because elk is low. However, when elk becomes high (I), the latch 0 (0 flip.flop) f oUIPUI follows the D inpul , so when 0 :9 10:fr--changes from 0 10 1 (4), so does the latch OUlpul (7). The latch ignores Ihe nexl changes on 0 when elk is low (5). but then Figure 3.21 Lalch versus flip-Rop liming. follows D again when elk is high (6, 8). Compare this wilh the nex l signal trace. howing the behavior of a rising-edge-triggered 0 Aip-fl op. The Aip-fl op amples D at the fi r t ri ing clock edge (I). fi nding 0 to be O. The flip-flop thus slores and oUlpul a 0 (9). The Rip-fl op amples 0 al the next rising clock edge (2). finding D 10 be 1, and thus stores and outputs a 1 (10). Olice that the Ripfl op ignores all changes 10 0 Ihat occur belween Ihe ri ing clock edges (3. -1. 5. 6)-even ignoring changes On 0 when Ihe clock is high (4. 6).
Clk~
O~
,
i
108
3 Sequenti al Logic Design- Controllers
EXAMPLE 3.1 Flight attendant call-button uSing a D fl ip-flop Lei· ... dc\i gll ollr ni el ill ,lItcm.lant cu ll -bullon system lIsing a D
3.2 Storing One Bit- Flip-Flops
TABLE 3.1 0 truth table for call-button system.
flip-nop. If Ca 11 e i~ prcs:-.cd. we wanl 10 store a 1. If Cance 1 i ~ prc',cd. \\ C \\Iu nl !oo lo re n O. If neither is pressed, we W;J1l1 to siore whatever i, prcscnll y Siored. meaning O. \Vc Ihu, I1c~d ;1 , imp/c l'olnbin:.Hiollal circuit in fron t of the 0
inpul. dc,cribe
Level-sensitive 5R lalch
Ca ncel
0
0
o latch
0
0
0
0
Om Om
0
0
)
)
lowing eq ual io n for 0:
D B Cancel ' 0 + Call
0
)
0
0
)
)
0
)
0
0
)
Problem:
1
0
1
)
5R=11 yield undefined O.
)
1
0
1
1
1
)
)
o flip-flop Olalch Os Os, O' Cs Os 0
0
B
Aner ~OIl1 C algebraic liimplific:l.lion. we obtain (he fol-
o lalch
5
Ca II
Fealure: 5 =1 Fealure: 5 and R only sels 0 101 , R=I have eHecl when C=I. resels 0 10 O. We can design oUlside
circuil so SA:: 11 never
happens when C=I . Problem: avoiding 5R=11 can be a burden.
Fealure: 5R can'l be 1/ if 0 is slable before and while C= I , and will be II for only a brief glilch even if 0 changes while C=l . Problem: C=I 100 long
Fealure: Only loads 0 value presenl al rising clock edge, so values can'l propagate 10 olher flip-flops during same clock cycle. Tradeotf. uses more gales inlernally Ihan 0
propagates new values
lalch. and requires more
Ihrough 100 many lalches; exlernal gales than 5R- but too Short may nOI enable gate count is less of an issue
The final !
a slore.
loday.
Figure 3.29 Increasingly better bit storage blocks. leadi ng to the 0 flip-llop. The D flip-fl op-based design uses more gates tha n Ihe SR lalch-based in Fig ure 3.9 (w hich could have just as eas il y used an SR fl ip-flop) . One reason ror the exira gate!' is Ihal a D flip- fl op always slores ils D inpul on every c lock cycle, so we muSI explicil ly feed 0 back inl o D 10 mainta in the same va lue. In contrast. we could just SCI S=R~O 10 mainlain Ihe same va lue wilh an SR flip-fl op. Furthermore. we must convert Ihe bU lion presses 10 the appropriate D inpul value, requiring ext ra logic. rather than just cuing ei ther 5 or R 10 1. In Ihe late 1970s and
earl y I 980s. Ihose ex tra gates were a big deal. beca use ICs came with just a
Call ,--, burton Cancel button
_-'
Flight altendant call-button system (a)
Call button Cancel button
Basic Register-Storing Multiple Bits A reg ist er is a sequcn lia l componen l thai can store multiple bits. We ca n bui ld a basic reg isler simply by us ing multi ple fli p-flops, as shown in Figure 3.30. That reg ister can hold 4 bi ts. When the clock rises, all 4 fli p-fl ops get loaded wi lh inpu ts 10, 11. 12, and 13 si multaneously. 13
12
f1
(b)
Figure 3.28 Flight attenda nt call -button system: (a) block diagram. and (b) implemented using a o fli p-flop.
few gales on Ihem , so extra gales often meant extra ICs, meaning ex tra size, cost, power, etc. But today, in Ihe era of mill ion-gate ICs, the savings of an SR flip-fl op are trivial. In modern des ign. nearl y all designs u e D flip-fl ops, not SR flip-fl ops. As a poin l of informal ion, deSigners commonly refer to fl ip-fl ops simply as flops . We wenl Ihrough several inlermediale designs before arri ving at our robust D flipfl op design for Our desired bil storage block. Figure 3.29 summ arizes those designs, including Iheir features and their problems, leading to the robust edge-triggered D flip-flop . In look ing Over the summary, notice that the D flip-fl op reli es on an internal SR lalch to mai nt ain a stored bil be/ ween clock cycles, and re lies on the designer to introdu ce feed back outs ide Ihe D fl ip- fl op to mai ntain a stored bit fro rn aCIVss clock cycles.
109
01
00
Figure 3.30 A basic 4-bit register internal design (left) and block symbol (right). This register, made simply from multi ple fli p- fl ops. is the mo t basic fornl of a register-so basic that some companies refer 10 s uch a register simply as a "4-bit D fl ipfl op." We' ll describe more advanced regislers, namely, registers with more feat ures and operations, in Chapter 4.
EXAMPLE 3.2 Temperature history display using registers We Want to design a system that records the outside temperature every hour and displays the last three recorded rcmperalUrcs. so thai an observer can see the lcmpermure trend. An architecture of
the system is shown in Figure 3.3 J. A timer generales a pulse on signal C every hou r. A tel11pera!u~ cnsor outputs the prese~I
lemperature as a 5-bit binary number ranging from 0 to 31 . cOlTespo~dtng to those temperatures Celsius. Three display COIll'e l1 Iheir 5-bit binary inputs into a numencal dtsplay.
This example dcmollSlrnres one of Ihe grea t things lIbOU I synchronous circuits built from edgetriggered nip-nops-many Ihings happen at once. yel we need nOI be concemed aboul signals propagating
))) Figure 3.31 Temperatu re hislory display syslem.
[00
fast through
II
register to nnOlher register. The rcason we need nOI be concerned is
because registers ollly gel loaded 011 lhe rising clock edge. which effectively is an infinitely small period of lime. so by fhe lime signli is propagate through a register to a second regislcr. it's too laIc-that second register is no longer paying attention to its data inputs.
TemperalureHistoryStorage
timer
C
We should mention that , in practice. designers typically try to avoid connecting any signal other than an oscillator ou tpul to the clock input of a Rip-flop or register. So in practice. we might Iry to avoid connecti ng the signal C to the registers' clock inputs, since C comes rrom a timer output, not an osci llator. We' ll show in Chapter 4, Example 4.3, how to des ig n a s imi lar ys tem using an osci llator ror the clock.
avoid connecting the timer output
(In practice. we would actually ( 9 an oscillator output to a clock input.)
C to a clock input, instead only connec In
. S" componen t usin o three 5-bil registers, a ·1/ Ill > prese~t teml>era ture on inputs .. 31 E I I' signal C loads a WI 1 " shown In Figure ~. _. ~c 1. pll se 0.11 . R . I the 5 input bits). At the same time that register x4 . . xO (by load lllg the) flip-naps IIlslde a W.1t 1 Rb octs loaded with the value th at was in Ra. Ra 2CIS loaded wi th that present tempera ture. reglstc~ d Ol · ';]1 the sam e time namely on the \'Ve can implemen t the Temperal/lreHlsfOl)' IOIfI!fR'
rising edge of C. The errect is [hat th e v:ilucs that wcre shifted illlO Rb and Re. respec ti ve ly.
---------
04 03 02 01 00
a4 a3 a2 al a0 r - 14 04 13 03 12 02 It 01 10 00
r~
r~
,----
f-:-1 4
~13 ~12 ~It
Figure 3.32 lnlemal design of (h e TemperalllreHiSlory Storage com ponent.
~IO xO
c
.
re Ih; clock
Just befo
b4 b3 b2 bl bO , - - - 14 13 12 tl 10
cd e
et
g g
c4
c3 c2 cl cO
04J03 I - 02 ~ 01 00
I~ TemperatureHistoryStorage
Fieure 3.33 shows sample values in Ihe regislers for several clock cycles, assuming all ihe reg-
isters i~itially held Os. and assuming that as tim e proceeds the inputs x4 .. xO have the values shown al th e (OP of rhe timing diagram .
3.3 FINITE-STATE MACHINES (FSMS) AND CONTROLLERS Registers store bits in a dig ital circuit. Stored bits means the circui t has memory, also known as slale. resulting in what are known as sequential circuits. While a register storing bits happens to result in a circuit with state. we can ac tually use state to design circuits that have a . pecifi c behavior over time. For example, we can specifically design a circuit that o utputs a 1 for exactly three cycles whenever a button is pressed. Or we cou ld design a circuit that blinks lights in a specific pattern . Or we could design a circuit that detects ir three buttons get pushed in a particular sequence and that then unlocks a door. In all the e cases. we wo uld be making use of sta te to create specific time-ordered behavior for Our circ uit. A sequential circuit that controls Boolean Ou tpulS based On Boolean inputs and a specific time-ordered behavior is often referred to as a cOlllroller.
EXAMPLE 3.3 Three-cycles-high laser timer-a poorly done first design Consider the design of a pan of a laser surgery syslem. such as a syslem for scar removal or correc tive vision. Such systems work by turning On a laser for a precise amounl of time (see "How doe it work ?laser surgery" on page I 12). A general archilec ture of such a system is hown in
Figure 3.34. A surgeon activates the laser by
Figure 3.33 Example of va lues in the
Temperolure Hislory Storage registers. One
panicuJar daw item ) J 8, is shown moving through Ihe regiSlers on each clock cycle.
Ra Rb Rc
clk patient
Figure 3.34 Laser timer system. pressing the bUllon. Assume Ihe la er . . should Ihen Slay on for exaclly 30 ns. Assuming our clock 's period is 10 ns. 30 ns means 3 clock cycles. (Assume thai b IS synchroruzed with the clock and Slays high for onl y I clock cycle.) We need 10 design a controller component Ihal. once delecting Ihal b ~ I. holds X high for exactly 3 clock cycles. thus luming on the laser for exaclly 30 ns. . . This is one example for which a software solution may nol work. USlllg JUSI regular programming statements reading inpul pons and wriling OUtpUI pons, we may nOI have a way 10 hold an OUlput pan high for exaclly 30 ns-for example. when Ihe microprocessor clock frequency IS not fasl enough. or when each slalemenl takes 2 cycles 10 execule.
112
Sequential log ic Design-Conlrollers
J.J Finite-Slate Machines IFSMs) and Controllers
Let's try to crea te a sequential circuit implementation for the system. After th inking about the problem for a while. we miglll come up with the (nol so good) implementation in Figure 3.35. Knowing we need 10 hold the output high for three clock cycles, we used three flip-flops. with the idea bein!! that we'll shift a I throu gh those three flipflops. taking three clock cycles for the bit (0 move
lhrough all lhree flip-naps. We ORed the nip-nap outputs 10 generate signal x, so Ihal if any flip-flop comains a 1. the laser will be on. \Ve made b the
In the previous chapler, you. saw Ihal we cou ld design a combinational circuit by first descnbmg the deSired CirCUli behaVIOr using a malhematical formalism known as a Boolean eq uation , and then converting the equation 10 a circuit. For a sequential circuit. a Boolean equatIOn alone is not sufficient 10 describe behavior-we need a mOre powerful malhematlcal formali sm Ihal incorporales lime.
clk
Figure 3.35 Firsl (bad) allempl 10
Finite-slale machines (FSMs) are jusl s uch a method. The name is a bil but Ihe concepl is straighlforward . An FSM consists of severa l Ihings, the mOS I Imponanl of wh ich IS a sel of states representing every possible stale, Or mode, of a system.
awkw~rd ,
implement Ihe laser surgery syslem.
inpu l lO the firsl flip-flop. so when b= 1, the firsl nip-Hop Slores a 1 on Ihe nex i clock cycle. One (0 0, Ihe firsl flip-flop will gel loaded with O. One clock cycle Imer. Ihe third flip-fl op wi ll gel loaded wi!h 1. and Ihe second flip-flop wilh O. One clock cycle Ialer, Ihe Ihird nip-flop wi ll gel loaded wi!h O. Thus. the circuit held the aUipul X at 1 for three clock cycles after the bulton was pressed. clock cycle Imer. the second flip-fl op will get loaded with 1, and assuming b has now returned
~
~··:'-d . ·~I .1 "
_
. "
".
The prel'iolls example illllsrra,ed rhe need for a way of describing 'he desired behol'ior of a sequential cirr;ui,.
~
We did nOI do a very good job implementing this syslem. First of all, what happens if the surgeon presses the button a second time before the three cycles are completed? Such a situation could cause the laser 10 Slay on 100 long. Is Ihere a simple way to fix our circuit to accounl for that behavior? Second, we didn'l use any orderly method for designing the circuil-we came up with the ~Ring of nip-flop OUlputs, bUI how did we come up wilb that? Will thai merhod work for all lime-ordered behavior that we mighl wan l 10 design? We need IWO Ihings 10 do a bener job al designing circuilS having time-ordered behavior. Firsl, we need a way 10 explicitly represenlthe desired time-ordered behaviorwe' ll introduce the finite -slale machine represenlation for thi s purpose. Second, we need an orderl y method for implemenling such behavior as a sequenlial circ uit-we' ll introduce such a standard method.
.
-
-
.
.
1
'. i
'
1.like 10 u~e my daughler's hamsler as an intuitive example. After baving a hamster as a family pel, I ve learned Ihal hamsters basically have four stales: Sleeping, Eating, Run IIlIIg 011 The Wheel, and Try illgToEscape. They spend mOSI of their day leeping (being nocturnal), a bit of tllne ealing or running On the wheel, and the rest of their time desperalely Irylng 10 escape from Ihei r cage.
As a more electronics-oriemed example, lei 's design a system thai repealedly sets an OUlpul X 10 0 for one clock cycle and 10 1 for one clock cycle. The syslem clearly has on ly two states, which we' ll ca ll Off and Oil. In slate Of(, X = 0; in stale 011_ x = 1. We can show Ihose slales, and the transilions between them , usi ng the state diagram in Figure 3.36.
~~~~ Outputs: x
clk cycle
Outputs:
~
I I
I I
I
t
I I
i
i
!
i
hcycle 2 hcycle 3 hcycle 4 i
1
slate~
HOW DOES IT WORK?-LASER SURGERY.
Laser surgery has become very popular in the pasl decade, and has been enabled due 10 digilal syslems. Lasers. invented in Ihe early I960s, generale an intense narrow beam of coherenl light with pholOns having a single wavelength and being in phase (like being in rhythm) wilh one another. [n contraS!, a regular light's pholons fly OUI in all directions. with a diversily of wavelengths. Think of a laser as a plaloon of soldiers marching in synch, while a regular lighl is more like kids running oul of school althe end-of-theday belL A laser's lighl can be so inlense as 10 even CUI steel. The ability of a digilal circuilto carefully control the location, intensilY. and duralion of the laser is whal makes lasers so useful for surgery. One popular use of laser for surgery is for Scar removal. The laser is focused on the damaged cells sljghlly below the surface, causing Ihose cells 10 be
vaporized. The laser can also be used 10 vaporize skin ceUs !hat fonn bumps on Ihe skin. due 10 scars or moles. Similarly. lasers can reduce wrinkles by smoothing ille skin around the wrinkle to make the crevices more gradual and hence less obvious, or by stimulating lissue under Ihe skin 10 slimulale new collagen growth. Another popular use of lasers for surgery is for cOlTecling vision. [n one popular laser eye surgery method, the surgeon CUIS open a fl ap on the surface of Ihe comea_ and Ihe la er Ihen reshapes the cornea by thlOnlOg Ihe cornea in a panicular pallem, with such IhlOmng accomplished Ihrough vaporizing cells. A digilal syslem conlrols the laser's localion, energy, and dural ion, based on programmed informalion of the d~Slred procedure. The availabilily of lasers, combined wuh low-coSi high-speed digilal circui ts. makes such precise and useful surgery now possible.
---- - -
113
Finite-State Machines (FSMs)
X
I
I
,
I
--r--1---J!
Figure 3.36 A simple slale diagram (len) and Ihe timing diagram de cribing the state diagram's behavior (ri ght). Above the timing diagram. we see the FSM going from one
Sl'ate 10
the other in
each clock cycle. "e 1 k A" represenls Ihe rising edge of the clock signal. Assume we Slarl in Slale Off. The diagram shows thai x is set 10 0 while the y lem is in Slale Off. The diagram also shows thai on Ihe neXI rising edge of the clock signal . C/kA, the syslem Iransilions 10 Slale 011, and the diagram shows thul i el 10 I in Ibal Slale. On the next rising edge of the clock, [he diagram shows lhal the y "lem tran ilions 10 slale Off again . A l.iming diagram showing the sy lem' beha,~or i hown in Figure 3.36. Recall in Example 3.3 thai we wan led a syslem Ihal held ils OUrpUI high for three cycles. Toward that end. lel's extend the simple Sime diagram of Figure 3.36 I ha\e on off Siale and three on slales, as shown in Figure 3.37. The OUIPUI will be 0 for one C) -Ie.' and Ihen 1 for Ihree cycles. as shown in the liming diagmm of the figure.
Sequential Logic Design- Controllers
Outputs: x
=o
3.3 Finite-State Machines (FSMs) and Controllers IkA
1
~ elkA x=1 Onl
Off
~
elkA~ ~~3 ~
~
elk
JUULJLILJLJLJl-
EXAMPLE 3.4
We can create an FSM to describe Ihe earlier introduced laser timer system. The system might have four states: Off, all / , 0112. and On3. In the Off state, the laser should be off (x -D). The anI state wo uld be the first clock cycle the laser is On (x - 1), On2 the second cycle, and On] the third cycle. The state dIagram of Ihe FSM is in fact identical to that shown in Figure 3.38. . Here's how Ihe FSM shou ld be interpreted. We start in our initial state Off. We stay in state Off until One of Us two outgoing transitions has a true conditi on. One of those transitions has the condition of b' AND rising clock (b ' *c1 kA)-in Ihal case, we transition right back to state Off. The other of Ihose transilions has Ihe condi tion of a b AND a rising clock (b*c 1 k A)-in that case, we transitIOn to Siale 0111. We Slay in Slale a,,} until its one outgoing transition 's condition. a rising clOCk. becomes true-in which case we transition to stale On2. Likewise, we stay in On2 until the ~ex( riSing clock. Iransilioning to 0113. We Slay in 0,,3 until the next rising clock. causing a transitIon back 10 slate Off. In stale Off. we have associaled the action of setling x-O, while in states anI, 0112, and On3, we have associated the action of selling X= 1.
State@ff lonl ;on2pn310ff lonlpn2 iO n310ff l
~
Outputs:
-.J
U
L
x
. 'He diaornn1 (left). timing diagr:111l (ri ght ). Fi ure 3.37 Three-cycles-hi gh system. st. 0 . g 'ti ons 10 funh e r ex tend the behaV ior. . ditions on the LranSI .. . '. 38 b hanoin o the condillOn on the tra nSition We can introduce Input con . 11 in F, oure 3 Y c ~" . " I k d' We ex tend the stat e wgn.lI e Ih~ new cond ition require s not Just a n S I ~l? CDC, fro m state Off to stale ani. such that.. f OljJback to Off. wi th the condlLlon ofa dd a tranSillon rom ' d . . the fi oure shows the state an outpUt but also that b= 1. VIIe a Iso a . ' " . . . d b=O The liming diagram Ill . rlSlIlg clock an . '. values on b. behav ior for the given IIlput
elk Inputs: b
Thus. we have precisely described the desired time-ordered behavior of the laser timer system
using an FSM.
JLJLJLJllJuLl ,,
rn
/t 's inleresting to examine the behavior of this FSM if the button is pressed a second time
,,
while the laser is on. No[ice thm the lransilions among the On sta tes are independent of the value of
b. So this system will always lurn Ihe laser on for exactly three cycles and then return to the Slale 10 awail another press of the bUllon.
1
'
i
I
L
I I I I jonl:on210n~ Off I
Srate !Off Off Off Off Off Outputs:
-------------"
. h system.. state diaorom (left), liming diagram (right). Figure 3.38 Three·cycles·hlg e
A set of states. Aur ex a mple had four states: {Onl. On2, 01/3,. Offl· . A set of IIlputs, and a set 0 f outputs. Our example had one IIlpllt: {b }, and one output: {x }. -' al tate, name Iy, a s tate to stan in . when we power An .Illili d ' up dthe d ystem. . h An . ' al tate can be .In d I'cated graphically by a ;lIlgle ItCCle e ... ge, Wit FSM 's .IIllli , I no . ' '(al source state , Ihat pOint to t he 1111 I . tate . An FSM can only have one IIltlia state. Our example's initial stale was Off. . ' on 0 f Ihe nex t sa t te to go 10 based on the cu rre nt sta .le and thedva.l A deSCripti ' . ues of lhe inputs. ur exam p Ie u.sed directed edges. .with a,wciated "Input carr. IflOns to tell us Ihe nex t state. Those edges wilh condil lon arc known ,l~ trlll/Slfrorrs. _
.
a
'
. . of what OUlput values 10 generate in each Mate. Our exa mple a signs A d eSCrlplion . M ' .. Ii a value to X in every slate. Assigning an outpU I In an FS "nown as an ac on.
.1\
VII sed a graphical represenlation of an F M. kn own a slale diagram , to ho" e ufo r our exa mp Ie. We co u ld have repre5ented the FSM " the F M lex luall y lIl'tead. but stale diagram~ arc very popular for visualiting an FSM , hchavlOr.
Off
Simplifying FSM Notation: Making the Rising Clock Implicit
,
macilirr e, or FSM, is a mathFrom the above examples. we can see that . ajirrile-slate . emalical fomlalism consisLing of several things.
115
FSM for the three-cycles-high laser timer
a"clkA
(J+D a'
C:r-D
Thus far, we have included the rising clock edge (c 1 k A) as pan of the condition of every FSM transi tion. We included that edge because we are onl y considering the design of sequential circuits that are synchronous and that use rising edgetriggered Rip-Rops to store bits. Synchronous sequential c irc uits with edge-triggered Rip-Rops make up the Vast majority of sequential circuits in modem design practice. As such, most textbooks and designers, to make their state diagrams more Figure 3.39 readable, follow the convention lhat every transiassuming every tmn irion is ANDed tion in an FSM is implicirly ANDed with a rising with a rising clock . c lock edge. For example, a transition labeled "a '" ac tua ll y means "a' *c1 kA." Hencefonh. we will not include the rising clock edge when drawing FSM transitions, and we will follow the convention that every transition is
~ "STATE" I UNDERSTAND, BUT WHY THE TERMS uFlNITEu AND "MACHINE? . FinilC-Slate machines, or FSMs. have a mther "machine" is used in irs mar.hematical or computer awkward name th m sometimes causes confusion. The science sense, being a concepTUal object that can term "finite" is there 10 contrast FSMs with a similar execute an abSlr3et language--specificaJl . that sense representation used in mathematics Ih31 can have i.U1 of machine is not hardware. Finite- tnte m3ClliMs are infinite number of stliles; Ihal represenlmion is nOI also known :IS jinile-S14U aUlolfllJllJ. FSMs ~ used very useful in digilal design. F Ms, in contmst. have for many things other than just digilllJ design. n limiled, or finite, number of SIUI.S. n,e lem,
116
Sequential Logic Design-Controllers
3.3 Finite·State Machines (FSMs) and Controllers
• ' do Fioure 3.39 illustrates the laser timer state implicitly ANDed wiLh a nSlllg clock c ~e. . " ,. . lock d sino an Imp Jell C . diagram fro m Figure 3..l0. re rawn u ~.. . ply tra nsi tions o n the next clock cycle, A transition-with no assoc iated condlllon slIn . ' .
0----0
because of the impl ici t rising clock edge. . ho v 10 describe lime-ordered behavior Let's consider a rew more examples shOWing \ using FSMs.
EXAMPLE 3.5
Secure car key
. . ew aUlOmobiles have ::J thicker plastic h ea~ t~ a~ III the H<1 ve you nOllced... that Ihe keys for J~lan). 11 believe it or 11 0 1, there is a computer chi p IIlslde the past (see Figure .lAO)? Th~ reason IS th~I., In n basic version of suc h a secure car key, when (which is under the hood and commuhead of th e key, implemcntll1g a secure car ke~, the driver tums the key in the ignition, the car s com puler . 'onal aski ng the car key 's chip to h b {'OI) sends out a ra d 10 510 .. nicates using what's ca~led t, e a~esta ' ~ '0 The chi in Ihe key then responds by sending respond by sendin g an Identifier via a rad iO sIena!. P s onder ;'transmits" in "response" the identifier (ID) usin o what's known as a transponder (a tJan P , h fD d'f ' e . es ponse or the key s response as an 1to a request), If the bases!ation d~es not rece,l\'e a r h com uter shuts down and the car ferent than the lD program med 1111 0 the car s computer. ( e p won't start. •
. "
•
I
Figure 3.40 Why are the he3ds of keys gelling thicker? Note th31 .the key on the ri ght is .thicker than the key on the left. The key on the right has a computer chip inSIde that sends an Iden lJ fier to the car's compu ter, thus helping to reduce car thefts. Let's design the controller for such a key having an ID of 10 11 (re31lDs are typically 32 bits long or more. not just 4 biLS). Assume the controller has an input a that is 1 when the car's computer requests the key's ID. Thus the controller initially waiLS for the input a to become I. The key should then send its ID (lOll) serially, staning with the right· most bit, on an output r: the key send 1 on the first clock cycle. I on the second cycle. 0 on the third cycle, and finall y 1 on the fourth cycle. The FSM for the controller is shown in Figure 3.4 1. Note that the FSM sends the bits 'lUning from the bit on the right. which is known as the leart significant bit (LSB). Figure 3.42 provides a timing diagram for the FSM for a particular Silu. ation. When we set a - 1, the FSM ente" ,tate K J and output.> r - 1. The FSM
\
Inputs: a; Oulputs: r
---- .
Inputs
Timing di agrams represe nt a particular situation defi ned by how we sel
the inputs. What wou ld have happe ned if we had held a = I for many more clock cycles? The timing di ag ram in Figure 3.43 illustrates that situalion. Notice how the FSM, after retu rning to stare Wait. proceeds to Slate K I again on the nex t cycle.
Figure 3.41 Secure car key FSM.
clk~ Inputs~
a State
I iNail Flail I K t I K2 I K3 1 K4 IWait!W8iti
lJ7
Clk~
even thoug h we returned inpUi a to O.
a _ _ _--'
State
IIWait IWail I Kl I K2 I K3 I K4
Wait Kj
Outputs
r~ Figure 3.43 Sec ure car key timing diagram for a different sequence of values on input 3.
The computer chip in the car key has circuiLry that converts radi o signals 10
bi ts and vice versa,
"So my car key may someday need its batteries replaced?" you might ask. Actually, no-those chips in keys draw their power as we ll as their clock from the magnetic componem of the radiofrequency field genermed from the computer baseslaLion. The extremely low power requiremem makes Custom digi tal circuitry, ramer th an software on a microprocessor, the preferred implementation method. Computer chi p keys make stea ling cars a lot harder-no more "ha l- wiring" 10 stan a car, since the car's compuler won' t work unless it also receives the correct idemifier, And the method above is acrually an overly simplistic method-many cars have more sophisticated commun ication berween the computer and the key, in volvi ng several communi cmions in both directions, even using encrypted communicmion- maki ng fooling the car's compUler even harder. A drawback of secure car keys is that you can't just run down to the local hardware Store and copy those keys for S5 any longer-eopying keys requi res special tools th at today can run $50-$ I 00. A common problem while computer chip keys were becoming popular was that low-cost locksmiths didn't realize the keys had chips in them. so copies we re made and the car owners went home and later couldn't figure ou{ why their car wouldn 't start. even th ough the key fi t in the igni tion slot and turned.
EXAMPLE 3.6 Code detector
Figure 3.42 Secure car key tllTlIng diagram.
....
Ihen proceeds Ihrough K2. KJ, and K4, OutpUlling r: 1, 0, and 1, respect ively.
You 've probably seen doors in airpons or hospitals th at require a person to press a panicular sequence of bUllons (i.e .. a code) to unlock the door. For example, there migh t be th ree bUllons, colored red, green, and blue. and 3 fourth bUllon for starting the code. Pressing the stan bUllon. then the fo llowing bUllon sequence-red. blue, green, red- unlocks the door. wh ile any other sequence does not un lock the door. Such a system may have the ge nernl architecture shown in Figure 3.44. An extra output from the bUllons component, a, is 1 whenever a ll)' button is pressed.
Start Red
Green Blue
Code detec10r
Door lock
Figure 3.44 Code detector W"Chitocture.
We can de cribe the behavior of the CodeDetector block using an FSM ""cured as the SOte diagra m shown in Figure 3.45. . For simplicity, ass ume th at the bUllons each h3ve a pecial ireuit that S) n h~nlZes the butt n with the clock ignal. nnd cre'lles a pulse exn tly one clock yele " ide for e3<,h unique press of the
118
Sequential logic Design-Controllers bUllon . This is necessary
to
3.3 Finite-State Machines (FSMs) and Controllers Inputs: s.r.g,b,a; Outputs: u
en!'urc
Lhal the CUlTcm SIZlIe does n '( inadvcncnr ly change 10 another Slate if a
button press i:.Isls longer thall a single clock cycle. (\Vc'lI design such a synchronization circu it in Example
3.9.) The behavior of Ihe FSM is a~
fo llows:
Sia le . As long as the slart bU IIon is nOl pressed (5 ' ), the
FS M
Figure 3.45 Code deleclOr -
Standard Controller Architecture for Implementing an FSM as a Sequential Circuit
.
the Sian Slale.
d bl FSM is now ready (0 delcct the sequence re . ue, green, . S I If a bUlIan is pressed AN D that bUI. d ( ') he FSM stays ," tar. red. If no bUllon IS presse a . I R /I If a bUllon is pressed A D Ihal bUllon . db (a r) the FSM noes 10 slale et . ' . Ion IS the re ullon. e h Wa i t stalc-nole Ihal when III Ihe Wall . b ( r ' ) the FSM retums 10 I e . IS nOI Ihe red ullon a . Id be i.nored. unlil the SIan bUllon IS pressed stare. further presses of the colored butlons wo u ~ FSM oaes •
10
0,
Being
In
buttons simultaneously, fo ur time in a row? Well , the way we defined the FSM. the door wo uld unlock! A solution to this undes ired ituation is to mOdify the conditions on the arcs that go back to the Wail state. Rather than the condition a r ' , we could use the condition a (r '+b+g). Thus, when the FSM expects the red bUllon, then not pressing the red button. Or pressing the blue or green bUllon , causes a transit ion back to the Wail stateand so does not unlock the door. Likewise when we are ex pecting other specific buttons. An improved FSM is shown in Fig ure 3.46. Fixing the FSM was easy: trYing to fix a circui t deri ved from the FSM wo uld have been much harder. It turns Out that the FSM in Figure 3.46 still has a problem-a fairly seriou one. We' ll describe that problem in Exampl e 3. 13.
The FSM begins in the Wait
FSM slays in m,il: when Ihe sIan bUllon is pressed ( S). Ihe
J 19
the 5wrr stal e means the
agai n. b lion is pre sed (a'). If a bullon is pressed and The FSM stays in Slate Redl as long as no U 81 "f Ihal bUllon is nOI blue (ab ' ) Ihe thaI bU llon is blue (ab). the FSM goes 10 Slale lie. I , FSM relUrns to state 1'0i1. , . state B1/Ie as Iong as Likewise. the FSM stays 10 .. no bUllon , is pressed (a ). and goes 10 Slale Green on con ditio n a g. and state Wair on cond ition a 9 . .. Finally. Ihe FSM slays .III Creen 'f I no bIn ur a is pres ed. and goes 10 Slale Red2 on condItIon a r. and to state \~0il on condition a r R d2 h eans that Ihe user pressed Ihe bUllons III the correel If Ihe FSM makes il 10 slale e . I al m kin Ihe door. Ole thaI all olher Slates sell/=O. sequence-Ihus, Red2 sets 1/= I. thus unloc g I
The FSM then relums to slate Wail.
•
Recall tha l every transi tion' condi ti on is implicitly A
Checking FSM Behavior Correctl y defi ning the behavior of a system is hard. The earlier we fi nd problems, the easier they are to fix. So after we create the FSM , we migh t take time to as k que tions abou t how the ystem behave under cenain input si tuations and then verify that the FSM responds as we expect. Consider the code detector FSM in Figure 3.45. What happens if the user presses the stan button and then presses all three colored
•
Ded with a rising clock edge.
Inputs: s,r,g,b,a; Outputs: u
~
Now that we 've seen how to desc ri be seq uential behavior using an FSM. we need a Structured method to conven the FSM to a sequential circuit. The method is actually very straightforward when we use a standard implementation archi tecture for the circuit. consisting of a state register and combinational logic_ LOgether known as a conlroUer. There are many other ways to implement an FSM, but stiCking to the tandard architecture results in a straig htforward design method. The standard architecture may not yield the minimum nu mber of transistors, but as we've mentioned many times. that's not a drawback these days. A standard cont roller architecture for an FSM consists of a state register and combinational logic. The standard architecture for the laser timer FSM of Figure 3.39 is sho wn in Fig ure 3.47. The architecture consists of a state reg i ter and combinati onal logic. The state register is a 2-bi t regis ter that holds a binary num ber representi ng the present state (i n thi s case, the reg ister is 2 bits wide to represent each of the 4 possible states). Figure 3.47 Standard conlroller The combinational logic's inputs are the architecture for the laser timer. input of the FSM (in this case, b), as well as the state register's ou tputs (s 1 and sO). The combinational logic 's outputs are the outputs of the FSM ( x ), as well as the nex t tate bi ts to be loaded into the state register (n 1 and nO). The details of the com binational logic detemline Ule behavior of the circuit. The prace s for creati ng those detai l wi ll be covered in the next secti on. A more general view of the tandard controller architecture appears in Figure 3.-18. Th31 fig ure ass umes a state register that is 11/ bits Figure 3.48 tandanl ,,,,"troller wide. aJ"('hireC'ture--genl"ml \ i '\\.
120
3 Sequential Logic Design-Controllers
3.4 Controller Design
3.4 CONTROLLER DESIGN
us to easily sec which rows correspond to whi ch Slates. We fi ll all combinati
~~ the left, as usual for a truth table. For each row, we look at the state dia~ i ;,puts
0Cb:
I' five step process summari zed in Table 3.2. We'll illus. , We can deSign a control er uSing a tra te thi s process with some examples.
Likewise, for the two rows slarting with
Descri ption
5 150 = a 1 (state 0111). x should be 1 and the nex t state should be 0112 (regardless of the value of b), so nInO should be 10. We
Create an FSM th at describes the desired beha vior of the controller,
complete the lasl four rows similarly.
TABLE 3.2 Controller design process. Step
fr
Be careful [Q nOle the difference between the FSM inputs and outputs of Figure 3.49. and the combinational logic Inputs and outputs of Figure 3.5O--the latter
ii;
Creale the N
arc/ZirecllIre
a.
"
ii;
Encode (h e slates
r.
fr
ii;
"'fr"
Create the standard architecture by using a stale reg ister of appropriate width. and combinati onal logic With.inputs being the state regiSler bits and the FSM inpuls and ou tpul S bemg the next state bits
and the FSM outputs.
Creme the stale table
Assign a unique binary number 10 each s t~le . Each bin~ number represen ting a state is kn own as an ellcodlllg. Ally encodlJ1g will do as long as each stale has a unique encoding.
Create a truth table for the combinational logic such that the logic the inputs with state bits fi rst makes this truth table describe the state behavior. so the table is a state lab Ie,
.,.,
Implement the combinational logic using any method .
c.
"
ii;
Imp/emelll the combil1alioll{l//ogic
EXAMPLE 3.7 Three -cycles-h igh laser timer controller Icontinued) We can implement th e laser limer (see Example 3.4) as a sequential circuit using the fi ve·step process.
Step I:
Capture the FSM. The FSM was created earlier (see Figure 3.39).
Step 2:
Create the architecture. The standard contrOller architecture for the laser timer FSM was shown in Figure 3.47. The Slate regi ster has two bilS to represent each of the four states. The combinational logic has external input b and inputs 51 and sO coming from the state register, and has external output x and outputs nl and nO going to the state register.
Step 3:
mcludes the bits from and
Step 5:
Encode the states, We can encode the states as follows-Off 00. 0,,/ : aI, 0,,2 : la , a,,]: 11. Remember.
the stale register.
outputs:
On3
0,,1
sO
nl
nO
a a a a a a o a a a a o a a a
o o a a
o o
o
a
x = 51 + sO (note fromthetabIe that x=I if S1=lorsO=I ) n1 n1
51 ' sOb ' + 51 ' sOb + s1s0'b' + sIsO'b 51 ' 50 + 5150 '
nO
SI ' 50 ' b + sIsO ' b ' + S150 ' b 51 ' sO ' b + 5150 '
nO
We th en obtain lhe sequential circuit in Figure 3.50. implementing the FSM .
Many textbooks will organize the state table in different ways than that in Table 3.3. However, we intentionally organize the table so that it serves both as a state table and a truth table that can be used to design the combinational logic of the controller.
The state diagram with encoded states is shown in Figure 3.49. Create the state table. Given the implementation architecture and the
binary encod ing of each state, we can create the state table for the combinational logic, as shown in Table 3.3. Listing the inputs from the state register first in the input columns allows
Implement the combinational logic. We ~an fi nish the design by using the combinational logic design process from Chapter 2. From the truth table, we obtain the following equa!lOns for the three combinational logic
wi ll generate the correc t FSM outputs and nex t state signals. Ordering
ii;
O
. 9 to determine the appropriate outpu ts. For the two rows starting with SI~O Ig~~ ~:ta~~ should be O. If b - 0, the controller should stay in state Off, so nInO Sh:uld '" . I, the controller should go to state anI. so nInO should be 01.
Five-Step Controller Design Process
CapillI" Ihe FSM
121 f'
Figure 3.49 Laser timer state diagra m with encoded ~tate s. Figure 3.50 Final implementation of the threc·cyc les-high Inser tim er controller,
Combinational logic o c: -5 c:
0;
122
3 Sequential Logic Design- Controllers
3.4 Controller Design
EXAMPLE 3.8 Understanding the laser timer controller's behavior ,
EXAMPLE 3.9
.
FSM leI's trace through the behav ior of the
. "~ II in state 00 (5 I 50-0 0). b is 0, and lhree-cycl~s- hl gh laser (liner controller. A~sume \~e are m~~l. yba sed 0 11 the combinational logic, X the clock IS currentl y low. As shown in Figure 3.) 1 (left ~ I de). . a ' h I 00
To betler understand how" controller implements ,In
. wtll be
a (the desired output in state 00). nI
'II b 0 'lI1d nO will be . mc.lnlng t e va ue
e .' d 00 wi ll be waiti ng
b( ><.=.1 _
x= 1
-<$))b'
x=1
~~110n3
b( ~ __
x=1
e oa e
In
0
~ __ x=1 x=1 s-'~110n3
0&
e
We want to build :l circuit that synchroni zes a bUlion press to a clock signal. such Lhat when a user presses the bUllon. the result is a signal thm is high
elk
:
:
---r-1----
Capture Ihe FSM. Figure 3,53(a) shows an FSM describing the circuit' behavior. The FSM waJt~ In slate A, outputting bo""O . until bi is 1. Th e FSM then transitions to stale B, OUlptlt,llng bo:; I. Th e FSM will then tran sition to either sla te A or C. which both set bo=O again, so that bo was 1 for just one cycle, as desired. The FSM 0DCS from B toA if b 1 returned to O. If b i is still 1. the FSM goes to Slate C. where the °FSM wailS for b i fa return D. causing a trans ition back to Slale A. FSM inputs:
bi; FSM outputs: bo
~ i'
o !lL----~s=lal~e=~OO~---t
hcycle2 ncycle3 ncycle4
~e~entmg the but ton b,eing pressed, we want to se t bo to 1 for exactly one cycle. We [hen wait for 1 t~ return to a agalll , alld then wa ir for bi to become 1 again. which would represent the next pre ssmg of th e button ,
elk r'-"*O-F'-,
o
cycle 1
bi -..J ' for exactly one clock cycle. Such a synchronized , L Outputs: J : Signal IS ~se rul (0 prevcm a single bulton press th at I~s ls mu ltI ple cycles from being interpreted as mU/ bo (I?'e blltto~ presses. Figure 3.52 uses a liming diagram to Illustrate the desired circuit behavior. The ci rcuit's input wi ll be a signal bi and Figure 3.52 DeSired lIming diagram oflhe the output a sjonal bo Wh bl' bcco mes. I' rep- bu([on press synchromzer , 0 < , en
Step 1:
slale=OO
clk Inputs:
4
b(
x=1
s-'S-<11
WI
-~ -b-'----""
x=o _ - - - - _
- <$:»b'
' 11 b i d d ' t th
WI
\.
bi
b"
bi
A
slale=01
r
bi
B
C
b"
bo=O
bo= 1
FSM inputs:
bi; FSM outputs: bo
r
bo=O
(a) Inputs:
b - - - - - -____~ Outputs:
" '___________ ,
--------------------------~ Figure 3.51 Traci ng the behavior of the three-cycles-high laser timer controller. Now suppose b become I. As shown in Figure 3.51 (middle). x will still be O. as desired. n I will be O. but nO wi ll be I. meaning the value 01 will be waiting at the stale regisler's inputs. Thus, on the lIex( clock edge. aI will be loaded inlo the state register, as desired. As shown in Figure 3.5 1 (right side). soon after 01 is loaded into the state registe r, X will become I (after the register i loaded, theres a slight delay as the new values fo r 5 I and sO propagate through the combinational logic gates). That output is correct-we should output X= 1 when in state 01. Also. n1 wi ll become 1 and nO will equal 0, meaning the value 10 will be waiting at the state register inputs. Thus. on the next clock edge. 10 will be loaded into the state register. as desired. After lO is loaded into the state regiSle r, x will Slay I , and n I nO will become II. When another clock edge comes. 11 will be loaded into the register. x will SlaY I. and nl nO wi ll become 00. When anOlher clock edge comes. 00 will be loaded into the register. Soon aftcr. x wi ll become O. and if b is O. nInO wi ll stay 00 : if b is I. nInO will become 01. No tice we're bnck where we started. Understanding how a State register and combinational logic implement a state machine can take a wh ile, ince in a particular state (indicated by the value presentl y in the state regisler). we generate the eX lemal output for that state. and we generate the signal, for Ihe lI ext state-bul w. don't lran ;i tion to that next state (i.e .. we don't load the
123
Button press synchronizer
(b)
bo=1
n1 = s1 'sObi + s1s0'bi nO = s1 'sO'bi bo = s1 'sObi' + s1 'sObi = 51 '50
bo=O
(c ) Combinational logic
Inpuls s1 sO bi 0 0 0 0 0 1
Oulpuls n1 nO bo 0 0 0 0 1 0
0 --cn--o- Tb-T-' o CD --1-'0-0-6-'0--0--' 1 1
Figure 3.53: Bulton press synchroni zer design steps:
(0