Ajay Kumar Garg Engineering College, Ghaziabad Department of EN NOTES FOR SUBJECT: POWER ELECTRONICS SUBJECT CODE: EEE 602 PREPARED BY: VANI BHARGAVA, NUPUR MITTAL Evaluation Scheme Subject Code EEE602
Name of Subject Power Electronics
L 3
Periods T P 1 2
CT 30
Evaluation Scheme TA TOTAL ESC 20 50 100
Subject Total 150
Credit 4
UNIT I: syllabus: Power semiconduct s emiconductor or Devices: Power semiconductor devices their symbols and static characteristics Characteristics and specifications of switches, types of power electronic circuits Operation, steady state and switch characteristics & switching limits of Power Transistor Operation and steady state characteristics of Power MOSFET and IGBT Thyristor – Operation V- I characteristics, two transistor model, methods of turn-on Operation of GTO, MCT and TRIAC
UNIT II: syllabus: Power Semiconductor Devices(Contd) Protection of devices. Series and parallel operation of thyristors Commutation techniques of thyristor DC-DC Converters: Principles of step-down chopper, step down chopp er with R-L load Principle of step-up chopper, and operation with RL load, classification of chop pers
UNIT III: syllabus: Phase Controlled Converters Converters Single phase half wave controlled con trolled rectifier with resistive and inductive loads, effect of freewheeling diode. Single phase fully controlled and half controlled con trolled bridge converters. Performance Parameters Three phase half wave converters Three phase fully controlled and half controlled con trolled bridge converters, Effect of source impedance Single phase and three phase dual converters
UNIT IV: syllabus : AC Voltage Controllers Principle of On-Off and phase controls Single phase ac voltage controller c ontroller with resistive and inductive loads Three phase ac voltage controllers c ontrollers (various configurations and comparison only) Single phase transformer tap changer.
UNIT I: syllabus: Power semiconduct s emiconductor or Devices: Power semiconductor devices their symbols and static characteristics Characteristics and specifications of switches, types of power electronic circuits Operation, steady state and switch characteristics & switching limits of Power Transistor Operation and steady state characteristics of Power MOSFET and IGBT Thyristor – Operation V- I characteristics, two transistor model, methods of turn-on Operation of GTO, MCT and TRIAC
UNIT II: syllabus: Power Semiconductor Devices(Contd) Protection of devices. Series and parallel operation of thyristors Commutation techniques of thyristor DC-DC Converters: Principles of step-down chopper, step down chopp er with R-L load Principle of step-up chopper, and operation with RL load, classification of chop pers
UNIT III: syllabus: Phase Controlled Converters Converters Single phase half wave controlled con trolled rectifier with resistive and inductive loads, effect of freewheeling diode. Single phase fully controlled and half controlled con trolled bridge converters. Performance Parameters Three phase half wave converters Three phase fully controlled and half controlled con trolled bridge converters, Effect of source impedance Single phase and three phase dual converters
UNIT IV: syllabus : AC Voltage Controllers Principle of On-Off and phase controls Single phase ac voltage controller c ontroller with resistive and inductive loads Three phase ac voltage controllers c ontrollers (various configurations and comparison only) Single phase transformer tap changer.
Cyclo Converters Basic principle of operation, single phase to single phase, three phase to single phase and three phase to three phase cyclo converters, output voltage equation
UNIT V: syllabus : Inverters Single phase series resonant inverter Single phase bridge inverters Three phase bridge inverters Voltage control of inverters Harmonics reduction techniques Single phase and three phase p hase current source inverters
Contents UNIT I: Semiconductor Devices 1.1 Power Diode 1.2 Bipolar Junction Transistor (BJTO) 1.3 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1.4 Silicon Controlled Rectifier (SCR) 1.5 Insulated Gate Bipolar Transistor (IGBT) 1.6 TRIAC 1.7 GTO UNIT II: Unit II – Power Semiconductor Devices (contd.) & DC-DC Converters 2.1 Thyristor Protection 2.2 Series and Parallel Operation of Thyristor 2.3 Commutation Techniques of Thyristor 2.4 DC-DC Converters: Step Down Chopper 2.5 Step Up Chopper 2.6 Classification of Choppers UNIT III: Phase Controlled Converters 3.1 Single Phase Half Wave Controlled Converter 3.2 Single Phase Full Wave Controlled 3.3 Three Phase Half wave Controlled Rectifier 3.4 Three Phase Full Wave Controlled Rectifier 3.5 Performance Parameters of Converters 3.6 Dual Converters 3.7 Effect of Source Impedance
UNIT IV: AC Voltage Controllers 4.1 Principle of On-Off Control & Phase Control 4.2 Single Phase AC Voltage Controller 4.3 Three Phase AC Voltage Controller (Configurations & Comparison) 4.4 Single Phase Transformer Tap Changer 4.5 Single Phase to Single Phase Cycloconverter 4.6 Three Phase to Single Phase Cycloconverter 4.7 Output Voltage Equation of Cycloconverter UNIT V: – 5.1 Single Phase Bridge Inverter 5.2 Three Phase Bridge Inverter 5.3 Voltage Control of Inverters 5.4 Harmonic Reduction Techniques 5.5 Current Source Inverter 5.6 Series Resonant Inverter
UNIT I
1.1 Power Diode
A p-n junction diode is formed by placing p and n type semiconductor materials in intimate contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type silicon crystal or by the opposite sequence. In an open circuit p-n junction diode, majority carriers from either side will defuse across the junction to the opposite side where they are in minority. These diffusing carriers will leave behind a region of ionized atoms at the immediate vicinity of the metallurgical junction. This region of immobile ionized atoms is called the space charge region. This process continues till the resultant electric field (created by the space charge density) and the potential barrier at the junction builds up to sufficient level to prevent any further migration of c arriers. At this point the p-n junction is said to be in thermal equilibrium condition. Variation of the space charge density, the electric field and the potential along the device is shown in Fig 1.1 (a). When an external voltage is applied with p side move negative then the n side the junction is said to be under reverse bias condition. This reverse bias adds to the height of the potential barrier. The electric field strength at the junction and the width of the space change region (also called “the depletion region” because of the absence of free carriers) also increases. On the other hand, free minority carrier densities (n in the p side and p in the n side) will be zero at the edge of the p
n
depletion region on either side (Fig 1.1 (b)). This gradient in minority carrier density causes a small flux of minority carriers to defuse towards the deletion layer where they are swept immediately by the large electric field into the electrical neutral region of the opposite side. This will constitute a small leakage current across the junction from the n side to the p side. There will also be a contribution to the leakage current by the electron hole pairs generated in the space change layer by the thermal ionization process. These two components of current together is called the “reverse saturation current Is” of the diode. Value of I is independent of the reverse s
voltage magnitude (up to a certain level) but extremely sensitive to temperature variation.
Fig 1.1: Space change density the electric field and the electric potential in side a p-n junction under (a) thermal equilibrium condition, (b) reverse biased condition, (c) forward biased condition.
When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse current increases rapidly. The diode is said to have undergone “reverse break down”. Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated by the large depletion layer electric field due to the applied reverse voltage may attain sufficient knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom. The liberated electron in turn may repeat the process. This cascading effect (avalanche) may produce a large number of free electrons very quickly resulting in a large reverse current. The power dissipated in the device increases manifold and may cause its destruction. Therefore, operation of a diode in the reverse breakdown region must be avoided. When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is lowered and a very large number of minority carriers are injected to both sides of the junction. The injected minority carriers eventually recombines with the majority carries as they defuse further into the electrically neutral drift region. The excess free carrier density in both p and n side follows exponential decay characteristics. The characteristic decay length is called the "minority carrier diffusion length" Carrier density gradients on either side of the junction are supported by a forward current I F
(flowing from p side to n side) which can be expressed as
IF=IS(exp (qv/Kt))-1
(1.1)
Where I = Reverse saturation current (Amps) s
v = Applied forward voltage across the device (volts) q = Change of an electron k = Boltzman’s constant T = Temperature in Kelvin The i-v characteristics of a p-n junction diode can be drawn as shown in Fig 1.2. While drawing this characteristics the ohmic drop in the bulk of the semiconductor body has been neglected.
Fig 1.2: Volt-Ampere ( i-v ) characteristics of a p-n junction diode 1.2 Bipolar Junction Transistor (BJT)
Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control over its Turn on and Turn off operations. A junction transistor consists of a semiconductor crystal in which a p type region is sandwiched between two n type regions. This is called an n-pn transistor. Alternatively an n type region may be placed in between two p type regions to give a p-n-p transistor. Fig 1.3 shows the circuit symbols and schematic representations of an n-p-n and a p-n-p transistor. The terminals of a transistor are called Emitter (E), Base (B) & Collector (C) are also shown in the figure 1.3.
Fig. 1.3: Bipolar junction transistor (a) n – p – n transistor ; (b) p – n – p transistor.
Constructional Features of a Power BJT Following Section summarizes some of the constructional features of a Power BJT. Since Power Transistors are predominantly of the n-p-n type.
· A power BJT has a vertically oriented alternating layers of n type and p type semiconductor materials as shown in Fig 1.4(a). The vertical structure is preferred for power transistors because it maximizes the cross sectional area through which the on state current flows. Thus, on state resistance and po wer lass is minimized.
·
In order to maintain a large current gain “” (and hence reduce base drive current) the emitter doping density is made several orders of magnitude higher than the base region. The thickness of the base region is also made as small as possible.
·
In order to block large voltage during “OFF” state a lightly doped “collector drift region” is introduced between the moderately doped base region and the heavily doped collector region. The function of this drift region is similar to that in a Power Diode. However, the doping density donation of the base region being “moderate” the depletion region does penetrate considerably into the base. Therefore, the width of the base region in a power transistor can not be made as small as that in a signal level transistor. This comparatively larger base width has adverse effect on the current gain () of a Power transistor which typically varies within 5-20. As will be discusses later the collector drift region has significant effect on the out put characteristics of a P ower BJT.
·
Practical Power transistors have their emitters and bases interleaved as narrow fingers. This is necessary to prevent “current crowding” and consequent “second break down”. In addition multiple emitter structure also reduces parasitic ohmic resistance in the base current path.
These constructional features of a Power BJT are shown schematically in Fig 1.4a
Fig. 1.4: Constructional Features of a Power Bipolar Junction Transistor (a) Schematic of Construction, Output i-v characteristics of a Power Transistor
A typical output (i vs V ) characteristics of an n-p-n type power transistor is shown in Fig C
CE
1.5. A power transistor exhibits “Cut off”, “Active” and “Saturation regions” of operation in its output characteristics similar to a signal level transistor. In fact output characteristics of a Power Transistor in the “Cut off” and “Active” regions are qualitatively identical to a signal level transistor.
Fig. 1.5 Output ( ic – vCE ) characteristics of an n – p – n type Power Transistor In the cut off region (i the collector current is almost zero. The maximum voltage between B ! 0 )
collector and emitter under this condition is termed “Maximum forward blocking voltage with
base terminal open (iB=0) and is denoted by VCEO . For all practical purpose this is the maximum voltage that can be applied in the forward direction (C positive with respect to E) across a power transistor since a power transistor is expected to see any significant forward voltage only with i B
This blocking voltage can however be increased to a value VCBO by keeping the emitter terminal open. In this case iB < o. Actually VCBO is the breakdown voltage of the collector base = 0.
junction. However, since the open base configuration is more common the value of VCEO is used by the manufacturers as the maximum voltage rating of a power transistor. Power transistors have poor reverse voltage withstanding capability due to low break down voltage of the baseemitter junction. Therefore, reverse voltage (C negative with respect to E) should not appear across a power transistor. In the active region the ratio of collector current to base current (DC current Gain ()) remains fairly constant upto certain value of the collector current after which it falls off rapidly. Manufacturers usually provide a graph showing the variation of as a function of the collector current for different junction temperatures and collector emitter voltages. This graph is useful for designing the base drive of a Power transistor. Typically, the value of the dc current gain of a Power transistor is much smaller compared to their signal level counterpart. The maximum collector-emitter voltage that a power transistor can withstand in active region is determined by the Base collector avalanche break down voltage. This voltage, denoted by V SUS
in Fig, 1.5 is usually smaller than V
. The voltage V
CEO
SUS
can be attained only for relatively
lower values of collector current. At higher collector current the limit on the “total power dissipation” defines the boundary of the allowable active region as shown in Fig 1.5. At still higher levels of collector currents the allowable active region is further restricted by a potential failure mode called “the Second Break down”. It appears on the output characteristics of the BJT as a precipitous drop in the collector-emitter voltage at large collector currents. The collector voltage drop is often accompanied by significant rise in the collector current and a substantial increase in the power dissipation. Most importantly this dissipation is not uniformly spread over the entire volume of the device but is concentrated in highly localized regions. This localized heating is a combined effect of the intrinsic non uniformity of the collector current density distribution across the cross section of the device and the negative temperature coefficient of resistively of minority carrier devices which leads to the formation of “current filamements” (localized areas of very high current density) by a positive feed-back mechanism. Once current filaments are formed localized “thermal runaway” quickly takes the junction temperature beyond the safe limit and the device is destroyed. It is in the saturation region that the output characteristics of a Power transistor differs significantly from its signal level counterpart. In fact the saturation region of a Power transistor can be further subdivided into a quasi saturation region and a hard saturation region. Appearance of the quasi saturation region in the output characteristics of a power transistor is a direct consequence of introducing the drift region into the structure of a power transistor. In the quasi saturation region the base-collector junction is forward biased but the lightly doped drift region is
not completely shorted out by excess minority carrier injection from the base. The resistivity of this region depends to some extent on the base current. Therefore, in the quasi saturation region, the base current still retains some control over the collector current although the value of decreases significantly. Also, since the resistivity of the drift region is still significant the total voltage drop across the device in this mode of operation is higher for a given collector current compared to what it will be in the hard saturation region. Switching characteristics of a Power Transistor The switching wave forms shown in Fig 1.6 (b) are the expanded and to some extent “idealized” version of the actual waveforms that will be observed in a clamped inductive switching circuit as shown in Fig.1.6 (a). Some simplifying assumptions have been made to draw these waveforms. These are
· The load inductor has been assumed to be large enough so that the load current does not change during Turn ON period.
· Reverse recovery characteristics of D has been ignored. · All parasitic elements have been ignored.
·
Fig 1.6 Turn ON characteristics of a power transistor; (a) Switching circuit, (b) Switching wave forms
Before t = 0, the transistor (Q) was in the “OFF” state. In order to utilize the increased break down voltage (V ) the base-emitter junction of a Power Transistor is usually reverse biased CBO
during OFF state. Under this condition only negligible leakage current flows through the transistor. Power loss due to this leakage current is negligible compared to other components of power loss in a transistor. Therefore, it is not shown in Fig 1.6 (b). The entire load current flows through the diode and V is clamped to V (approximately). CE
CC
To turn the transistor ON at t = 0, the base biasing voltage V
BB
changes to a suitable positive
value. This starts the process of charge redistribution at the base-emitter junction. The process is akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often represented by a voltage dependent capacitor, the value of which is given by the manufacturer as a function of the base-emitter reverse bias voltage. The rising base current that flows during this period can be thought of as this capacitor charging current. Finally at t = t the BE junction is d
forward biased. The junction voltage and the base current settles down to their steady state values. During this period, called the “Turn ON delay time” no appreciable collector current flows. The values of i and V remains essentially at their OFF state levels. O
CE
At the end of the delay time (t
) the minority carrier density at the base region quickly
d ON
approaches its steady state distribution and the collector current starts rising while the diode current (i ) starts falling. At t = t + t the collector current becomes equal to the load current d
dON
ri
(and i becomes zero) I . At this point D starts blocking reverse voltage and V d
L
CE
becomes
unclamped. t is called the current rise time of the transistor. ri
At the end of the current rise time the diode D regains reverse blocking capacity. The collector voltage V which has so far been clamped to V because of the conducting diode “D” starts CE
CC
falling towards its saturation voltage V
CE
(sat). The initial fall of V
CE
is rapid. During this period
the switching trajectory traverses through the active region of the output characteristics of the transistor. At the end of this rapid fall (t ) the transistor enters “quasi saturation region”. The fv1
fall of V
CE
in the quasi saturation region is considerably slower. At the end of this slow fall (t
fv2
)
the transistor enters “hard saturation” region and the collector voltage settles down to the saturation voltage level V (sat) corresponding to the load current I . Turn ON process ends CE
L
here. The total turn on time is thus, T
SW
(ON) = t
d (ON)
+t +t ri
fv1
+t . fv2
Turn Off Characteristics of a Power Transistor During Turn OFF a power transistor makes transition from saturation to cut off region of operation. Just as in the case of Turn ON, substantial redistribution of minority charge carriers are involved in the Turn OFF process. Idealized waveforms of several important variables in the
clamped inductive switching circuit of Fig. 1.6 (a) during the Turn OFF process of Q are shown in Fig 1.7 (a)
Fig. 1.7: Turn off, characteristics of a BJT. (a) Switching wave forms
The “Turn OFF” process starts with the base drive voltage going negative to a value -V . The BB
base-emitter voltage however does not change from its forward bias value of V (sat) BE
immediately, due to the excess, minority carriers stored in the base region. A negative base current starts removing this excess carrier at a rate determined by the negative base drive voltage and the base drive resistance. After a time “t ” called the storage time of the transistor, the s
remaining stored charge in the base becomes insufficient to support the transistor in the hard saturation region. At this point the transistor enters quasi saturation region and the collector voltage starts rising with a small slope. After a further time interval “t ” the transistor completes rv1
traversing through the quasi saturation region and enters the active region. The stored charge in the base region at this point is insufficient to support the full negative base current. V starts BE
falling forward –V
BB
and the negative base current starts reducing. In the active region, V
CE
increases rapidly towards V
CC
V
CE
and at the end of the time interval “t ” exceeds it to turn on D. rv2
remains clamped at V , thereafter by the conducting diode D. At the end of t CC
rv2
the stored
base charge can no longer support the full load current through the collector and the collector current starts falling. At the end of the current fall time t the collector current becomes zero and fi
the load current freewheels through the diode D. Turn OFF process of the transistor ends at this point. The total Turn OFF time is given by Ts =t +t +t +t (OFF)
s
rv1
rv2
fi
As in the case of “Turn ON” considerable power loss takes place during Turn OFF due to simultaneous existence of i and V in the intervals t , t and t . The last trace of Fig 3.7 (a) c
CE
rv1
rv2
fi
shows the instantaneous power loss profile during these intervals. The total energy last per turn off operation is given by the area under this curve. For safe turn off the average power dissipation during t + t + t should be less than the power dissipation limit set by the FBSOA rv1
rv2
fi
corresponding to a pulse width greater than t
rv1
+t
rv2
+t . fi
Turn OFF time intervals of a power transistor are strongly influenced by the operating conditions and the base drive design. Manufacturers usually specify these values as functions of collector current for given positive and negative base current and case temperatures. Variations of these time intervals as function of the ratio of positive to negative base currents for different collector currents are also specified. In this section and the precious one inductive load switching have been considered. However, if the load is resistive. The freewheeling diode D will not be used. In that case the collector voltage (V ) and collector current (i ) will fall and rise respectively together during Turn ON and rise CE
c
and fall respectively together during Turn OFF. Other characteristics of the switching process will remain same. The switching Power loss in this case will also b e substantially lower.
1.3 MOSFET
A MOSFET is a voltage controlled majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is controlled by the voltage applied on the control electrode
(called gate) which is insulated by a thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate voltage modulate the conductivity of the semiconductor material in the region between the main current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like their integrated circuit co unterpart, can be of two t ypes (i) depletion type and (ii) enhancement type. Both of these can be either n- channel type or pchannel type depending on the nature of the bulk semiconductor. Fig 1.8 (a) shows the circuit symbol of these four types of MOSFETs along with their drain current vs gate-source voltage characteristics (transfer characteristics).
Fig 1.8: Different types of power MOSFET. (a) Circuit symbols and transfer characteristics
Constructional Features of a Power MOSFET A power MOSFET using VDMOS technology has vertically oriented three layer structure of alternating p type and n type semiconductors as shown in Fig 1.9 which is the schematic +
representation of a single MOSFET cell structure. The two n end layers labeled “Source” and “Drain” are heavily doped to approximately the same level. The p type middle layer is termed +
the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than n -
regions on both sides). The n drain drift region has the lowest doping density. Thickness of this -
region determines the breakdown voltage of the device. The gate terminal is placed over the n and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device. Similarly all gate terminals are also conn ected together.
Fig. 1.9: Schematic construction of a power MOSFET
Operating principle of a MOSFET Application of a positive voltage at the gate terminal with respect to the source will covert the silicon surface beneath the gate oxide into an n type layer or “channel”, thus connecting the Source to the Drain. The gate region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide layer and the p-body silicon forms a high quality capacitor. When a small voltage is application to this capacitor structure with gate terminal positive with respect to the source (note that body and source are shorted) a depletion region forms at the interface between the SiO and the silicon as shown in Fig 1.10 (a). 2
Fig. 1.10: Gate control of MOSFET conduction. (a) Depletion layer formation; (b) Free electron accumulation; (c) Formation of inversion layer.
The positive charge induced on the gate metallization repels the majority hole carriers from the interface region between the gate oxide and the p type body. This exposes the negatively charged acceptors and a depletion region is created. Further increase in V causes the depletion layer to grow in thickness. At the same time the GS
electric field at the oxide-silicon interface gets larger and begins to attract free electrons as shown in Fig 1.10 (b). The immediate source of electron is electron-hole generation by thermal ionization. The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized by electrons from the source.
As V
GS
increases further the density of free electrons at the interface becomes equal to the free
hole density in the bulk of the body region beyond the depletion layer. The layer of free electrons at the interface is called the inversion layer and is shown in Fig 1.10 (c). The inversion layer has all the properties of an n type semiconductor and is a conductive path or “channel” between the drain and the source which permits flow of current between the drain and the source. Since current conduction in this device takes place through an n- type “channel” created by the electric field due to gate source voltage it is called “Enhancement type n-channel MOSFET”. The value of V at which the inversion layer is considered to have formed is called the “Gate – GS
Source threshold voltage V
GS
(th)”. As V
GS
is increased beyond V (th) the inversion layer gets GS
some what thicker and more conductive, since the density of free electrons increases further with increase in V . The inversion layer screens the depletion layer adjacent to it from increasing GS
V . The depletion layer thickness now remains constant. GS
Steady state output i-v characteristics of a MOSFET The output characteristics of a MOSFET is then a plot of drain current (i ) as a function of the D
Drain –Source voltage (v ) with gate source voltage (v ) as a parameter. Fig 1.11 (a) shows DS
GS
such a characteristics.
Fig. 1.11: Output i-v characteristics of a Power MOSFET With gate-source voltage (V ) below the threshold voltage (v (th)) the MOSFET operates in GS
GS
the cut-off mode. No drain current flows in this mode and the applied drain–source voltage (v ) DS
is supported by the body-collector p-n junction. Therefore, the maximum applied voltage should be below the avalanche break down voltage of this junction (V ) to avoid destruction of the DSS
device.When V
GS
v
DS
(v
DS
is increased beyond v (th) drain current starts flowing. For small values of GS
< (v – v (th)) i is almost proportional to v . Consequently this mode of operation is GS
GS
D
DS
called “ohmic mode” of operation. In power electronic applications a MOSFET is operated either in the cut off or in the ohmic mode. The slope of the v – i characteristics in this mode is called DS
D
the ON state resistance of the MOSFET (r (ON)). DS
At still higher value of v
DS
(v
DS
> (v – v GS
GS
(th)) the i – v D
DS
characteristics deviates from the
linear relationship of the ohmic region and for a given v , i tends to saturate with increase in GS
D
v . The exact mechanism behind this is rather complex. It will suffice to state that, at higher DS
drain current the voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer end. In addition, at large value of the electric field, produced by the large Drain – Source voltage, the drift velocity of free electrons in the channel tends to saturate. As a result the drain current becomes independent of V and determined solely by the gate – source DS
voltage v . This is the active mode of operation of a MOSFET. Simple, first order theory GS
predicts that in the active region the drain current is given approximately by I D
= K (VGS - VGS (th )) 2
1.2
Where K is a constant determined by the device geometry. At the boundary between the ohmic and the active region V DS Therefore,
I D
= (VGS - VGS (th)
= KV DS 2
1.3 1.4
Equation (1.4) is shown by a dotted line in Fig 1.11 (a). The relationship of Equation (1.2) applies reasonably well to logic level MOSFETs. However, for power MOSFETs the transfer characteristics (i vs v ) is more linear. D
1.4 Thyristor
GS
Thyristors are usually three-terminal devices with four layers of alternating p- and n-type material (i.e. three p-n junctions) in their main power handling section. The control terminal of the thyristor, called the gate (G) electrode, may be connected to an integrated and complex structure as part of the device. The other two terminals, anode (A) and cathode (K), handle the large applied potentials (often of both polarities) and conduct the major current through the thyristor. The anode and cathode terminals are connected in series with the load to which power is to be controlled. Thyristors are typically used at the highest energy levels in power conditioning circuits because they are designed to handle the largest currents and voltages of any device technology (systems with voltages approximately greater than 1 kV or currents higher than 100 A).
Basic Structure and Operation
Figure 1.12 shows a conceptual view of a typical thyristor with the three p-n junctions and the external electrodes labeled. Also shown in the figure is the thyristor circuit symbol used in electrical schematics.
Fig.1.12 Simple cross section of a typical thyristor and the associated electrical schematic symbols. The operation of thyristors is as follows. When a positive voltage is applied to the anode (with respect to a cathode), the thyristor is in its forward-blocking state. The center junction J2 is reverse-biased. In this operating mode the gate current is held to zero (open-circuit). In practice, the gate electrode is biased to a small negative voltage (with respect to the cathode) to reverse bias the GK-junction J3 and prevent charge-carriers from being injected into the p-base. In this condition only thermally generated leakage current flows through the device and can often be approximated as zero in value (the actual value of the leakage current is typically many orders of magnitude lower than the conducted current in the on-state). As long as the forward applied voltage does not exceed the value necessary to cause excessive carrier multiplication in the
depletion region around J2 (avalanche breakdown), the thyristor remains in an off-state (forward blocking). When a positive gate current is injected into the device J3 becomes forward-biased and electrons are injected from the nemitter into the p-base. Some of these electrons diffuse across the p-base and are collected in the n-base. This collected charge causes a change in the bias condition of J1. The change in bias of J1 causes holes to be injected from the pemitter into the n-base. These holes diffuse across the n-base and are collected in the p-base. The addition of these collected holes in the p-base acts the same as gate current. The entire process is regenerative and will cause the increase in charge carriers until J2 also becomes forward biased and the thyristor is latched in its on-state (forward-conduction). The regenerative action will take place as long as the gate current is applied in sufficient amount and for a sufficient length of time. Two transistor analogy
The underlying operating principle of a thyristor is best understood in terms of the “two transistor analogy” as explained In figure 1.13.
Fig. 1.13: Two transistor analogy of a thyristor construction. (a) Schematic Construction, (b) Schematic division in component transistor (c) Equivalent circuit in terms of two transistors.
Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive with respect to the cathode and the gate terminal open. With this voltage polarity J & J 1
are forward biased while J reverse biased. 2
Under this condition.
= a1 I A + I co1 ic 2 = a 2 I k + I co 2
ic1
1.5 1.6
3
Where
1
&
2
are current gains of Q & Q respectively while I 1
2
co1
&I
co2
are reverse saturation
currents of the CB junctions of Q & Q respectively. 1
2
Now from Fig 1.13 (c). ic1 + ic 2 & I k
= I A
1.7
= I A
1.8
Combining Eq 1.5 & 1.8 I A
=
I CO1 + I CO 2 1 - (a1 + a 2 )
I CO
=
1 - (a1 + a 2 )
1.9 Where ICO = ICO1 + ICO2 is the total reverse leakage current of J2. Now as long as V
AK
is small I
co
is very low and both
1
&
2
are much lower than unity.
Therefore, total anode current I is only slightly greater than I . However, as V A
co
to the avalanche break down voltage of J I 2,
multiplication process. As I increases both co
co
1
&
AK
is increased up
starts increasing rapidly due to avalanche
2
increase and
1
+
2
approaches unity.
Under this condition large anode current starts flowing, restricted only by the external load resistance. However, voltage drop in the external resistance causes a collapse of voltage across the thyristor. The CB junctions of both Q & Q become forward biased and the total voltage 1
2
drop across the device settles down to approximately equivalent to a diode drop. The thyristor is said to be in “ON” state. Just after turn ON if I is larger than a specified current called the Latching Current I , and a
L
1
2
remain high enough to keep the thyristor in ON state. The only way the thyristor can be turned OFF is by bringing I below a specified current called the holding current (I ) where upon & A
2
H
1
starts reducing. The thyristor can regain forward blocking capacity once excess stored charge
at J is removed by application of a reverse voltage across A & K (ie, K positive with respect A). 2
It is possible to turn ON a th yristor by application of a positive gate current (flowing from gate to cathode) without increasing the forward voltage across the device up to the forward break-over level. With a positive gate current equation 1.8 can be written as I K
= I A + I G
Combining with Eqns. 1.5 to 1.7 I A
=
+ I CO 1 - (a1 + a 2 ) a 2 I G
Obviously with sufficiently large I the thyristor can be turned on for any value of I (and hence G
V
co
). This is called gate assisted turn on of a Thyristor. This is the usual method by which a
AK
thyristor is turned ON.
When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.) junctions J and J are reverse biased while J is forward biased. Of these, the junction J has a 1
3
2
3
+
very low reverse break down voltage since both the n and p regions on either side of this junction are heavily doped. Therefore, the app lied reverse voltage is almost entirely supported by junction J . The maximum value of the reverse voltage is restricted by 1
a) The maximum field strength at junction J (avalanche break down) 1
-
b) Punch through of the lightly doped n layer. -
Since the p layers on either side of the n region have almost equal doping levels the avalanche break down voltage of J & J are almost same. Therefore, the forward and the reverse break 1
2
down voltage of a thyristor are almost equal.Up to the break down voltage of J the reverse 1
current of the thyristor remains practically constant and increases sharply after this voltage. Thus, the reverse characteristics of a thyristor is similar to that of a single diode. If a positive gate current is applied during reverse bias condition, the junction J becomes 3
forward biased. In fact, the transistors Q & Q now work in the reverse direction with the roles 1
2
of their respective emitters and collectors interchanged. However, the reverse
1
&
2
being
significantly smaller than their forward counterparts latching of the thyristor does not occur. However, reverse leakage current of the thyristor increases considerably increasing the OFF state power loss of the device. If a forward voltage is suddenly applied across a reverse biased thyristor, there will be considerable redistribution of charges across all three junctions. The resulting current can become large enough to satisfy the condition + = 1 and consequently turn on the thyristor. 1
2
This is called dv/dt turn on of a thyristor and should be avoided. Static output i-v characteristics of a thyristor
The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in this figure. With ig = 0, V has to increase up to forward break over voltage V before significant anode AK
BRF
current starts flowing. However, at V
BRF
forward break over takes place and the voltage across
the thyristor drops to V (holding voltage). Beyond this point voltage across the thyristor (V ) H
AK
remains almost constant at V (1-1.5v) while the anode current is determined by the external H
load. The magnitude of gate current has a very strong effect on the value of the break over voltage as shown in the figure. The right hand side figure in the inset shows a typical plot of the forward
break over voltage (V
BRF
) as a function of the gate current (I ). After “Turn ON” the thyristor is g
no more affected by the gate current. Hence, any current pulse (of required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient to effect control. The minimum gate pulse width is decided by the external circuit and should be long enough to allow the anode current to rise above the latching current (I ) level. L
Fig. 1.14: Static output characteristics of a Thyristor
. The left hand side of Fig 1.14 shows the reverse i-v characteristics of the thyristor. Once the thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding current (I ). The gate terminal has no control over the turn OFF process. In ac circuits with H
resistive load this happens automatically during negative zero crossing of the supply voltage. This is called “natural commutation” or “line commutation”. However, in dc circuits some arrangement has to be made to ensure this condition. This process is called “forced commutation.” During reverse blocking if i = 0 then only reverse saturation current (I ) flows until the reverse g
s
voltage reaches reverse break down voltage (V
). At this point current starts rising sharply.
BRR
Large reverse voltage and current generates excessive heat and destroys the device. If i > 0 g
during reverse bias condition the reverse saturation current rises. This can be avoided by removing the gate current while the thyristor is reverse biased. Thyristor Gate Characteristics
The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop and low reverse break down voltage. This characteristic usually is not unique even within the same family of devices and shows considerable variation from device to device. Therefore, manufacturer’s data sheet provides the upper and lower limit of this characteristic as shown in Fig 1.15.
Fig. 1.15: Gate characteristics of a thyristor.
Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximum average gate power dissipation limit (Pgavmax)These limits should not be exceeded in order to avoid permanent damage to the gate cathode junction. There are also minimum limits of Vg (Vgmin ) and Ig (Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (V ng ) is also specified by the manufacturers of thyristors. All spurious noise signals should be less than this voltage Vng in order to prevent unwanted turn on of the thyristor. The useful gate drive area of a thyristor is then b c d e f g h. The actual operating point will be some where between S & S 1
2
depending on the particular device. For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav Max curve without violating Vgmax or Igmax ratings. Therefore, for a dc source E c f represents the optimum load line from which optimum values of E & R g can be determined. Switching Characteristics of a Thyristor
During Turn on and Turn off process a thyristor is subjected to different voltages across it and different currents through it. The time variations of the voltage across a thyristor and the current through it during Turn on and Turn off constitute the switching characteristics of a thyristor. Turn on Switching Characteristics A forward biased thyristor is turned on by applying a positive gate voltage between the gate and cathode as shown in Fig 1.16
Fig. 1.16: Turn on characteristics of a thyristor
Fig 1.16 shows the waveforms of the gate current (ig), anode current (iA) and anode cathode voltage (VAK ) in an expanded time scale during Turn on. The reference circuit and the associated waveforms are shown in the inset. The total switching period being much smaller compared to the cycle time, IA and VAK before and after switching will appear flat. As shown in Fig 1.16 there is a transition time “tON ” from forward off state to forward on state. This transition time is called the thyristor turn of time and can be divided into three separate intervals namely, (i) delay time (td) (ii) rise time (t r ) and (iii) spread time (t P). These times are shown in Fig 1.16 for a resistive load. Delay time (td): After switching on the gate current the thyristor will start to conduct over the portion of the cathode which is closest to the gate. This conducting area starts spreading at a finite speed until the entire cathode region becomes conductive. Time taken by this process constitute the turn on delay time of a thyristor. It is measured from the instant of application of
the gate current to the instant when the anode current rises to 10% of its final value (or V AK falls to 90% of its initial value). Typical value of “td” is a few micro seconds. Rise time (tr ): For a resistive load, “rise time” is the time taken by the anode current to rise from 10% of its final value to 90% of its final value. At the same time the voltage V AK falls from 90% of its initial value to 10% of its initial value. However, current rise and voltage fall characteristics are strongly influenced by the type of the load. For inductive load the voltage falls faster than the current. While for a capacitive load VAK falls rapidly in the beginning. However, as the current increases, rate of change of anode voltage substantially decreases. If the anode current rises too fast it tends to remain confined in a small area. This can give rise to local “hot spots” and damage the device. Therefore, it is necessary to limit the rate of rise of the ON state current (diA/dt) by using an inductor in series with the device. Spread time (t P): It is the time taken by the anode current to rise from 90% of its final value to 100%. During this time conduction spreads over the entire cross section of the cathode of the thyristor. The spreading interval depends on the area of the cathode and on the gate structure of the thyristor. Turn off Switching Characteristics
Once the thyristor is on, and its anode current is above the latching current level the gate loses control. It can be turned off only by reducing the anode current below holding current. The turn off time tq of a thyristor is defined as the time between the instant anode current becomes zero and the instant the thyristor regains forward blocking capability. If forward voltage is applied across the device during this period the thyristor turns on again. During turn off time, excess minority carriers from all the four layers of the thyristor must be removed. Accordingly tq is divided in to two intervals, the reverse recovery time (trr ) and the gate recovery time (tgr ). Fig 1.17 shows the variation of anode current and anode cathode voltage with time during turn off operation on an expanded scale. The anode current becomes zero at time t1 and starts growing in the negative direction with the same diA /dt till time t2. This negative current removes excess carriers from junctions J1 & J3. At time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse current and the anode current starts decreasing. The value of the anode current at time t2 is called the reverse recovery current (Irr ). The reverse anode current reduces to the level of reverse saturation current by t3. Total charge removed from the junctions between t1 & t3 is called the reverse recovery charge (Qrr ).
Fig. 1.17: Turn off characteristics of a thyristor.
Fast decaying reverse current during the interval t2 t3 coupled with the di/dt limiting inductor may cause a large reverse voltage spike (Vrr ) to appear across the device. This voltage must be limited below the VRRM rating of the device. Up to time t2 the voltage across the device (VAK ) does not change substantially from its on state value. However, after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK starts following supply voltage v . At the end i
of the reverse recovery period (trr ) trapped charges still exist at the junction J2 which prevents the device from blocking forward voltage just after trr . These trapped charges are removed only by the process of recombination. The time taken for this recombination process to complete (between t3 & t4) is called the gate recovery time (t gr ). The time interval tq= trr + tgr is called “device turn off time” of the thyristor. No forward voltage should appear across the device before the time tq to avoid its inadvertent turn on. A circuit designer must provide a time interval tC (tC > tq) during which a reverse voltage is applied across the device. tC is called the “circuit turn off time”. Thyristor Turn-ON methods:
·
Forward voltage triggering: In this method when anode to cathode forward voltage is increased with gate circuit open, then the reverse bias junction J2 will have a avalanche breakdown at a voltage called forward break over voltage VBO. At this voltage thyristor or SCR changes from OFF state to ON state. The
forward voltage drop across the SCR during ON state is of the order of 1 to 1.5V and increases slightly with increase in the load current.
·
Thermal Triggering (Temperature Triggering): Width of the depletion layer of the thyristor decreases on increasing the junction temperature. Thus in the SCR when the voltage applied is very near to the breakdown voltage, the device can be triggered by increasing its junction temperature. By applying the temperature to certain extent, a situation comes when the reverse biased junction collapse making the device to conduct. This method of triggering the thyristor by heating is known as the Thermal Triggering process.
·
Radiation Triggering (Light Triggering): Thyristors are bombarded with energy particles such as neutrons and protons. Light energy is focused on the depletion region results in the formation of charge carriers. This lead to instantaneous flow of current with in the device and the triggering of the device.
· .dv/dt Triggering: In this method of triggering if the applied rate of change of voltage is large, then the device will turn on even though the voltage appearing across the device is small. We know that when SCR is applied with forward voltage across the anode and cathode, junctions j1 and j3 will be in forward bias and junction j2 will be in reverse bias. This reverse biased junction j2 will have the characteristics of the capacitor due to the charges exist across the junction. If the forward voltage is suddenly applied a charging current will flow tending to turn on the SCR. This magnitude of the charging current depends on the rate of change of applied voltage.
·
Gate Triggering: This is the most commonly used method for triggering the SCR or thyristor. For gate triggering a signal is applied across the gate and cathode of the device. By applying a positive signal at the gate terminal of the SCR it will be triggered much before the specified break over voltage. Three types of signals can be used for triggering the SCR. They are either dc signal,ac signal or pulse signal. 1.5 IGBT
Vertical cross section of a n channel IGBT cell is shown in Fig 1.18. Although p channel IGBTs are possible n channel devices are more common. The IGBT cell has a parasitic p-n-p-n thyristor structure embedded into it. The top p-n-p transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and the p type body layer as the collector. The lower n p-n transistor has the n+ type source, the p type body and the n type drain as the emitter, base and collector respectively. The base of the lower n-p-n transistor is shorted to the emitter by the emitter metallization. However, due to imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading resistance between the base and the emitter of the lower n-p-n transistor.
Fig. 1.18: Vertical cross section of an IGBT cell.
If the output current is large enough, the voltage drop across this resistance may forward bias the lower n-p-n transistor and initiate the latch up process of the p-n-p-n thyristor structure. Once this structure latches up the gate control of IGBT is lost and the device is destroyed due to excessive power loss. A major effort in the development of IGBT has been towards prevention of latch up of the parasitic thyristor. This has been achieved by modifying the doping level and physical geometry of the body region. The modern IGBT is latch-up proof for all practical purpose. Fig 1.19(a) and (b) shows the circuit symbol and photograph of an IGBT.
Fig. 1.19: Circuit symbol of an IGBT.(a) Circuit symbol. (b) Photograph. Operating principle of an IGBT
Operating principle of an IGBT can be explained in terms of the schematic cell structure and equivalent circuit of Fig 1.20 (a) and (c).
Fig. 1.20: a) Schematic structure of an IGBT cell. c) Approximate equivalent circuit
From the input side the IGBT behaves essentially as a MOSFET. Therefore, when the gate emitter voltage is less then the threshold voltage no inversion layer is formed in the p type body region and the device is in the off state. The forward voltage applied between the collector and the emitter drops almost entirely across the junction J . Very small leakage current flows through 2
the device under this condition. In terms of the equivalent current of Fig 1.20(c), when the gate emitter voltage is lower than the threshold voltage the driving MOSFET of the Darlington configuration remains off and hence the output p-n-p transistor also remains off. When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer and an electron current flows from the emitter through this channel to the drain drift region. This in turn causes substantial hole injection from the p+ type collector to the drain drift region. A portion of these holes recombine with the electrons arriving at the drain drift region through the channel. The rest of the holes cross the drift region to reach the p type body where they are collected by the source metallization.
From the above discussion it is clear that the n type drain drift region acts as the base of the output p-n-p transistor. The doping level and the thickness of this layer determines the current gain “” of the p-n-p transistor. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output p-n-p transistor collector. This helps to reduced the voltage drop across the “body” spreading resistance and eliminate the possibility of static latch up of the IGBT. The total on state voltage drop across a conducting IGBT has three components. The voltage drop across J1 follows the usual exponential law of a pn junction. The next component of the voltage drop is due to the drain drift region resistance. This component in an IGBT is considerably lower compared to a MOSFET due to strong conductivity modulation by the injected minority carriers from the collector. This is the main reason for reduced voltage drop across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop across an IGBT is due to the channel resistance and its magnitude is equal to that of a comparable MOSFET. Steady state characteristics of an IGBT
The i-v characteristics of an n channel IGBT is shown in Fig 1.21 (a). They appear qualitatively similar to those of a logic level BJT except that the controlling parameter is not a base current but the gate-emitter voltage.
Fig. 1.21: Static characteristics of an IGBT (a) Output characteristics; (b) Transfer characteristics
When the gate emitter voltage is below the threshold voltage only a very small leakage current flows though the device while the collector – emitter voltage almost equals the supply voltage (point C in Fig 1.21(a)). The device, under this condition is said to be operating in the cut off
region. The maximum forward voltage the device can withstand in this mode (marked VCES in Fig 1.21 (a)) is determined by the avalanche break down voltage of the body – drain p-n junction. Unlike a BJT, however, this break down voltage is independent of the collector current as shown in Fig 1.21(a). IGBTs of Non-punch through design can block a maximum reverse voltage (VRM) equal to VCES in the cut off mode. However, for Punch Through IGBTs VRM is negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer. As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active region of operation. In this mode, the collector current ic is determined by the transfer characteristics of the device as shown in Fig 1.21(b). This characteristic is qualitatively similar to that of a power MOSFET and is reasonably linear over most of the collector current range. The ratio of ic to (Vge – vge(th) ) is called the forward transconductance (g ) of the device and is an fs
important parameter in the gate drive circuit design. The collector emitter voltage, on the other hand, is determined by the external load line ABC as shown in Fig 1.21(a) As the gate emitter voltage is increased further ic also increases and for a given load resistance (R ) vCE decreases. At one point vCE becomes less than vge – vge(th). Under this condition the L
driving MOSFET part of the IGBT enters into the ohmic region and drives the output p-n-p transistor to saturation. Under this condition the device is said to be in the saturation mode. In the saturation mode the voltage drop across the IGBT remains almost constant reducing only slightly with increasing vge. In power electronic applications an IGBT is operated either in the cut off or in the saturation region of the output characteristics. Since vCE decreases with increasing vge it is desirable to use ,
the maximum permissible value of vge in the ON state of the device. Vge(Max) is limited by the maximum collector current that should be permitted to flow in the IGBT as dictated by the “latch-up” condition discussed earlier. Limiting Vge also helps to limit the fault current through the device. If a short circuit fault occurs in the load resistance R L (shown in the inset of Fig 1.21(a)) the fault load line is given by CF. Limiting v ge to vge6 restricts the fault current corresponding to the operating point F. Most IGBTs are designed to with stand this fault current for a few microseconds within which the device must be turned off to prevent destruction of the device. 1.6 The Triac
The Triac is a member of the thyristor family. But unlike a thyristor which conducts only in one direction (from anode to cathode) a triac can conduct in both directions. Thus a triac is similar to two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case of a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gate terminal. The gate looses control over conduction once the triac is turned on. The triac turns off only when the current through the main terminals become zero. Therefore, a triac can be categorized as a minority carrier, a bidirectional semi-controlled device.
Construction and operating principle
Fig. 1.22 (a) and (b) show the circuit symbol and schematic cross section of a triac respective. As the Triac can conduct in both the directions the terms “anode” and “cathode” are not used for Triacs. The three terminals are marked as MT (Main Terminal 1), MT (Main Terminal 2) and 1
2
the gate by G. As shown in Fig 1.22 (b) the gate terminal is near MT and is connected to both N 1
3
and P regions by metallic contact. Similarly MT is connected to N and P regions while MT is 2
1
2
2
2
connected to N and P regions. 4
1
Fig. 1.22: Circuit symbol and schematic construction of a Triac (a) Circuit symbol (b) Schematic construction.
Since a Triac is a bidirectional device and can have its terminals at various combinations of positive and negative voltages, there are four possible electrode potential combinations as given below: 1. MT positive with respect to MT , G positive with respect to MT 2
1
1
2. MT positive with respect to MT , G negative with respect to MT 2
1
1
3. MT negative with respect to MT , G negative with respect to MT 2
1
4. MT negative with respect to MT , G positive with respect to MT 2
1
1
1
The triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2
and 3 are used. Trigger mode 4 is usually averded. Fig 1.23 (a) and (b) explain the conduction mechanism of a triac in trigger modes 1 & 3 respectively.
Fig. 1.23: Conduction mechanism of a triac in trigger modes 1 and 3 (a) Mode – 1 , (b) Mode – 3 .
In trigger mode-1 the gate current flows mainly through the P N junction like an ordinary 2
2
thyristor. When the gate current has injected sufficient charge into P layer the triac starts 2
conducting through the P N P N layers like an ordinary thyristor. 1
1
2
2
In the trigger mode-3 the gate current I forward biases the P P junction and a large number of g
2
3
electrons are introduced in the P region by N . Finally the structure P N P N turns on 2
3
2
1
1
4
completely. Steady State Output Characteristics of a Triac
A triac is similar to two thyristors connected in anti parallel. Therefore, it is expected ex pected that the V-I st
rd
characteristics of Triac in the 1 and 3 quadrant of the V-I plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 1.24, with no signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (V ) of the device. However, the turning on of the triac can be controlled by BO
applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current). However, in a triac the two
conducting paths (from MT to MT or from MT to MT ) interact with each other in the structure structure 1
2
1
1
of the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than thyristors.
Fig. 1.24: Steady state V – I characteristics of a Triac 1.7 GTO
Like a thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differ from conventional thyristor in that, they are designed to turn off when a negative current is sent through the gate, thereby causing a reversal of the gate current. A GTO is also a four layer layer three junction p-n-p-n device. Fig.1.25 shows the circuit symbol and two different schematic cross section of a GTO.
Fig. 1.25: Circuit symbol and schematic cross section of a GTO (a) Circuit Symbol, (b) Anode shorted GTO structure, (c) Buffer layer GTO structure. In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make contact with the same anode metallic contact. Therefore, electrons traveling through the base can directly reach the anode metal contact without causing hole injection from the p+ anode. This is the classic “anode shorted GTO structure” as shown in Fig 1.25 (b). Due to presence of these “anode shorts” the reverse voltage blocking capacity of GTO reduces to the reverse break down voltage of junction J (20-40 volts maximum). In addition a large number of “anode shorts” 3
reduces the efficiency of the anode junction and degrades the turn on performance of the device. Therefore, the density of the “anode shorts” are to be chosen by a careful compromise between the turn on and turn off performance. p erformance. -
In the other method, a moderately doped n type buffer layer is juxtaposed between the n type base and the anode. As in the case of o f a power pow er diode dio de and BJT this relatively high density buffer -
layer changes the shape of the electric field pattern in the n base region from triangular to trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in a conventional “anode shorted” GTO structure would have increased the efficiency of the anode shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high probability of crossing this layer without stimulating hole injection. This is called the “Transparent emitter structure” and is shown in Fig 1.25 (c). Operating principle of a GTO
GTO being a monolithic p-n-p-n structure just like a thryistor its basic operating principle can be explained in a manner similar to that of a thyristor. In particular, the p-n-p-n structure of a GTO can be though of consisting of one p-n-p and one n-p-n transistor connected in the regenerative configuration as shown in Fig 1.26
Fig 1.26: Current distribution in a GTO (a) During turn on; (b) During turn off.
From the “two transistor analogy” (Fig 1.26 (a)) of the GTO structure one can write ic1
i B1
= a p I A + I CBO1
= iC 2 = a n I k + ICBO 2
= I A + I G and I A = iB1 + iC 1
I k Combining
=
I A
With applied forward voltage V
AK
+ I CBO1 + I CBO 2 1 - (a n + a P )
a n I G
less than the forward break over voltage both I
CBO1
are small. Further if I is zero I is only slightly higher than (I G
both
n
and
p
A
CBO1
are small and ( + p
n
+I
CBO2
and I
CBO2
). Under this condition
) <<1. The device is said to be in the forward blocking
mode. To turn the device on either the anode voltage can be raised until I
CBO1
and I
CBO2
increases by
avalanche multiplication process or by injecting a gate current. The current gain of silicon transistors rises rapidly as the emitter current increases. Therefore, any mechanism which causes a momentary increase in the emitter current can be used to turn on the device. Normally, this is done by injecting current into the p base region via the external gate contract. As + n
approaches unity the anode current tends to infinity. Physically as
n
p
+ nears unity the device p
starts to regenerate and each transistor drives its companion into saturation. Once in saturation, all junctions assume a forward bias and total potential drop across the device becomes approximately equal to that of a single p-n diode. The anode current is restricted only by the external circuit. Once the device has been turned on in this manner, the external gate current is no longer required to maintain conduction, since the regeneration process is self-sustaining. Reversion to the blocking mode occurs only when the anode current is brought below the “holding current” level. To turn off a conducting GTO the gate terminal is biased negative with respect to the cathode. The holes injected from the anode are, therefore, extracted from the p base through the gate metallization into the gate terminal (Fig 1.26 (b)). The resultant voltage drop in the p base above the n emitter starts reverse biasing the junction J and electron injection stops here. The process 3
originates at the periphery of the p base and the n emitter segments and the area still injecting electron shrinks. The anode current is crowded into higher and higher density filaments in most remote areas from the gate contact. This is the most critical phase in the GTO turn off process since highly localized high temperature regions can cause device failure unless these current
filaments are quickly extinguished. When the last filament disappears, electron injection stops completely and depletion layer starts to grow on both J and J . At this point the device once 2
3
again starts blocking forward voltage. However, although the cathode current has ceased the anode to gate current continues to flow (Fig 1.26 (b)) as the n base excess carriers diffuse towards J . This “tail current” then decays exponentially as the n base excess carriers reduce by 1
recombination. Once the tail current has completely disappeared does the device regain its steady state blocking characteristics. “Anode Shorts” (or transparent emitter) helps reduce the tail current faster by providing an alternate path to the n base electrons to reach the anode contact without causing appreciable hole injection from anode. Steady state output and gate characteristics
(b)
Fig. 1.27: Steady state characteristics of a GTO (a) Output characteristics; (b) Gate characteristics. This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig. 1.27 (a). However, the latching current of a GTO is considerably higher than a thyristor of similar rating. The forward leakage current is also considerably higher. In fact, if the gate current is not sufficient to turn on a GTO it operates as a high voltage low gain transistor with considerable anode current. It should be noted that a GTO can block rated forward voltage only when the gate is negatively biased with respect to the cathode during forward blocking state. At least, a low value resistance must be connected across the gate cathode terminal. Increasing the value of this resistance reduces the forward blocking voltage of the GTO. Asymmetric GTOs have small (2030 V) reverse break down voltage. This may lead the device to operate in “reverse avalanche”
under certain conditions. This condition is not dangerous for the GTO provided the avalanche time and current are small. The gate voltage during this period must remain negative.Fig 1.27 (b) shows the gate characteristics of a GTO. The zone between the min and max curves reflects parameter variation between individual GTOs. These characteristics are valid for DC and low frequency AC gate currents. They do not give correct voltage when the GTO is turned on with high dia/dt and dIG/dt. V in this case is much higher. G
UNIT-2 2.1 Thyristor Protection
· For reliable operation of SCR, it should be operated within the specific ratings. · SCRs are very delicate devices and so they must be protected against abnormal operating conditions. Various protection of SCR are a.
di/dt Protection
b.
dv/dt Protection
c.
Over voltage Protection
d.
Over Current Protection.
di/dt Protection: · di/dt is the rate of change of current in a device.
·
When SCR is forward biased and is turned ON by the gate signal, the anode current flows.
·
The anode current requires some time to spread inside the device. (Spreading of charge carriers)
·
But if the rate of rise of anode current(di/dt) is greater than the spread velocity of charge carriers then local hot spots is created near the gate due to increased current density. This localised heating may damage the device.
·
Local spot heating is avoided by ensuring that the conduction spreads to the whole are very rapidly. (OR) The di/dt value must be maintained below a threshold (limiting) value.
·
This is done by means of connecting an inductor in series with the thyristor as shown in fig.2.1
Fig.2.1: An inductor in series with the thyristor
·
The inductance L opposes the high di/dt variations.
·
When the current variation is high, the inductor smooths it and protects the SCR from damage. (Though di/dt variation is high, the inductor 'L' smooths it because it takes some time to charge). L " [Vs / (di/dt)]
dv/dt Protection: dv/dt is the rate of charge of voltage in SCR. ·
·
We know that iC=C.dv/dt. ie, when dv/dt is high, iC is high.
·
This high current(iC) may turn ON SCR even when gate current is zero. This is called as dv/dt turn ON or false turn ON of SCR.
·
To protect the thyristor against false turn ON or against high dv/dt a "Snubber Circuit" is used shown in fig.2.2.
SNUBBER CIRCUIT:
fig.2.2: Snubber Circuit
·
The snubber Circuit is a series combination of resistor 'R' and capacitor 'C'.
·
They are connected across the thyristor to be protected.
·
The capacitor 'C' is used to limit the dv/dt across the SCR.
·
The resistor 'R' is used to limit high discharging current through the SCR.
·
When switch S is closed, the capacitor 'C' behaves as a short-circuit.
·
Therefore voltage across SCR is zero.
·
As time increases, voltage across 'C' increases at a slow rate.
·
Therefore dv/dt across 'C' and SCR is less than maximum dv/dt rating of the device.
·
The capacitor charges to full voltage Vs; after which the gate is triggered, and SCR is turned ON and high current flows through SCR.
· As di/dt is high, it may damage the SCR.To avoid this, the resistor R in series with 'C' will limit the magnitude of di/dt.
·
The technique of 'snubbing' can apply to any switching circuit, not only to thyristor/triac circuits.
·
The rate of rise of turn-off voltage is determined by the time constant R LC. Where R L is the circuit minimum load resistance, for instance the cold resistance of a heater or lamp, the winding resistance of a motor or the primary resistance of a transformer.
Overvoltage Protection:Overvoltage may result in false turn ON of the device (or) damage the device. ·
·
SCR is subjected to internal and external over voltage.
Internal Overvoltage:
·
The reverse recovery current of the SCR decays at a very fast rate. ie, high di/dt.
·
So a voltage surge is produced whose magnitude is L(di/dt).
External Overvoltage:
·
These are caused by the interruption of current flow in the inductive circuit and also due to lightning strokes on the lines feeding the SCR systems.
·
The effect of overvoltage is reduced by using Snubber circuits and Non-Linear Resistors called Voltage Clamping Devices.
Voltage Clamping Device:
·
It is a non-linear resistor called as VARISTOR (VARIable resiSTOR) across the SCR.
connected
·
The resistance of varistor will decrease with increase in vo ltage.
·
During normal operation, varistor has high Resistance and draws only small leakage current.
·
When high voltage appears, it operates in low resistance region and the surge energy is dissipated across the resistance by producing a virtual short-circuit across the SCR.
Over Current Protection: · In an SCR due to over-current, the junction temperature exceeds the rated value and the device gets damaged.
·
Over-current is interrupted by conventional fuses and circuit breakers.
·
The fault current must be interrupted before the SCR gets damaged and only the faulty branches of the network should be isolated.
·
Circuit breaker has long tripping time. So it is used for protecting SCR against continuous over loads (or) against surge currents of long duration.
·
Fast acting current limiting fuse is used to protect SCR against large surge currents of very short duration.
Electronic Crowbar Protection:
Fig2.3:Schematic diagram of Electronic Crowbar Protection
·
SCR has high surge current ability.
·
SCR is used in electronic crowbar circuit for overc urrent protection of power converter.
·
In this protection, an additional SCR is connected across the supply which is known as 'Crowbar SCR'.
·
Current sensing resistor detects the value of converter current.
·
If it exceeds preset value, then gate trigger circuits turn ON the crowbar SCR.
· ·
So the input terminals are short-circuit by SCR and thus it bypass the converter over current. After some time the main fuse interrupts the fault current.
2.2 Series & Parallel Connection of an SCR
Fig.2.4:Circuit diagram of series connection of SCR When the required voltage rating exceeds the SCR voltage rating, a number of SCRs are required to be connected in series to share the forward and reverse voltage. As it is not possible to have SCRs of completely identical characteristics, deviation in characteristics lead to the following two major problems during series connections of the SCRs: (i) Unequal distribution of voltage across SCRs. (ii) Difference in recovery characteristics. Care must be taken to share the voltage equally. For steady-state conditions, voltage sharing is achieved by using a resistance or a Zener diode in parallel with each SCR. For transient voltage sharing a low non-inductive resistor and capacitor in series are placed across each SCR, as shown in sufficient to over damp the circuit. Since the capacitor C1 can discharge through the SCR during turn-on, there can be excessive power dissipation, but the switching current from C1 is limited by the resistor R 1 This resistance also serves the purpose of damping out ‘ringing’ which is oscillation of C1 with the circuit inductance during commutation. All the SCRs connected in series should be turned-on at the same time when signals are applied to their figure. Diodes D1 connected in parallel with resistor R l, helps in dynamic stabilisation. This circuit reduces differences between blocking voltages of the two devices within permissible limits. Additionally the R-C circuit can also serve the function of ‘snubber circuit‘. Values of R 1 and C1 can primarily be calculated for snubber circuit and a check can be made for equalization. If #Q is the difference in recovery charge of two devices arising out of different recovery current for different time and #V is the permissible difference in blocking voltage
then C 1 = Q/ V. . Parallel Connection of an SCR
Fig.2.5:Circuit diagram of parallel connection of SCR When the load current exceeds the SCR current rating, SCRs are connected in parallel to share the load current. But when SCRs are operated in parallel, the current sharing between them may not be proper. The device having lower dynamic resistance will tend to share more current. This will raise the temperature of that particular device in comparison to other, thereby reducing further its dynamic resistance and increasing current through it. This process is cumulative and continues till the device gets punctured. Some other factors which directly or indirectly ad d to this problem are difference in turn-on time, delay time, finger voltage* and loop inductance. Arrangement of SCRs in the cubicle also plays vital role. When the SCRs are connected in parallel, it must be ensured that the latching current level of the all the SCRs is such that when gate pulse is applied, all of them turn-on and remain on when the gate pulse is removed. Further the holding currents of the devices should not be so much different that at reduced load current one of the device gets turned-off because of fall of current through it blow its holding current value. This is particularly important because on increase in load current, the device which has stopped conducting cannot start in the absence of gate pulse. Another point to be considered is the on-state voltage across the device. For equal sharing of currents by the devices voltage drop across the parallel paths must be equal. For operation of all the SCRs connected in parallel at the same temperature, it becomes necessary to use a common heat sink for their mounting, as illustrated in figure. Resistance compensation used for dc circuits is shown in figure. In this circuit the resistors R x and R 2 are chosen so as to cause equal voltage drop in both arms. Inductive compensation used for ac circuits is shown in figure The difference in characteristics due to different turn-on time, delay time, finger voltage, latching current, holding current can be minimized by using inductive compensation. Firing circuits giving high rate of rise can be used to reduce mismatch of gate characteristics and delay time. Current sharing circuits must be designed so as to distribute current equally at maximum temperature and maximum anode current. This is done to ensure that the devices share current equally under worst operating conditions. Mechanical arrangement of SCRs also plays an important role in reducing mismatching. Cylindrical construction is perhaps the best from this point of view.
Derating. Even with all the measures taken, it is preferable to derate the device for series/parallel operation. Another reason for derating is poor cooling and heat dissipation as number of devices operate in the same branch of the circuit. Normal derating factors are 10 to 15% for parallel connection of SCRs depending upon the number of devices connected in parallel. Higher voltage safety factor is taken when SCRs are connected in series. 2.3 THYRISTOR COMMUTATION TECHNIQUES
In practice it becomes necessary to turn off a conducting thyristor. (Often thyristors are used as switches to turn on and off power to the load). The process of turning off a conducting thyristor is called commutation. The principle involved is that either the anode should be made negative with respect to cathode (voltage commutation) or the anode current should be reduced below the holding current value (current commutation). The reverse voltage must be maintained for a time at least equal to the turn-off time of SCR otherwise a reapplication of a positive voltage will cause the thyristor to conduct even without a gate signal. On similar lines the anode current should be held at a value less than the holding current at least for a time equal to turn-off time otherwise the SCR will start conducting if the current in the circuit increases beyond the holding current level even without a gate signal. Commutation circuits have been developed to hasten the turn-off process of Thyristors. The study of commutation techniques helps in understanding the transient phenomena under switching conditions. The reverse voltage or the small anode current condition must be maintained for a time at least equal to the TURN OFF time of SCR; Otherwise the SCR may again start conducting. The techniques to turn off a SCR can be broadly classified as
· Natural Commutation · Forced Commutation. NATURAL COMMUTATION (CLASS F)
This type of commutation takes place when supply voltage is AC, because a negative voltage will appear across the SCR in the negative half cycle of the supply voltage and the SCR turns off by itself. Hence no special circuits are required to turn off the SCR. That is the reason that this type of commutation is called Natural or Line Commutation. Figure 2.6 shows the circuit where natural commutation takes place and figure 2.7 shows the related waveforms. t c is the time offered by the circuit within which the SCR should turn off completely. Thus t c should be greater than t q , the turn off time of the SCR. Otherwise, the SCR will become forward biased before it has turned off completely and will start conducting even without a gate signal.
T +
vs
~
R
vo -
Fig. 2.6: Circuit for Natural Commutation
Supply voltage vs
p
Sinusoidal
3p
0
2p
wt
wt
a Load voltage vo Turn off occurs here
wt
p
3p
0
2p
wt
Voltage across SCR tc
Fig. 2.7: Natural Commutation – Waveforms of Supply and Load Voltages (Resistive Load)
This type of commutation is applied in ac voltage controllers, phase controlled rectifiers and cyclo converters.
FORCED COMMUTATION
When supply is DC, natural commutation is not possible because the polarity of the supply remains unchanged. Hence special methods must be used to reduce the SCR current below the holding value or to apply a negative voltage across the SCR for a time interval greater than the turn off time of the SCR. This technique is called FORCED COMMUTATION and is applied in all circuits where the supply voltage is DC - namely, Choppers (fixed DC to variable DC), inverters (DC to AC). Forced commutation techniques are as follows:
· · · · · · ·
Self Commutation Resonant Pulse Commutation Complementary Commutation Impulse Commutation External Pulse Commutation. Load Side Commutation. Line Side Commutation.
SELF COMMUTATION OR LOAD COMMUTATION OR CLASS A COMMUTATION: (COMMUTATION BY RESONATING THE LOAD)
In this type of commutation the current through the SCR is reduced below the holding current value by resonating the load. i.e., the load circuit is so designed that even though the supply voltage is positive, an oscillating current tends to flow and when the current through the SCR reaches zero, the device turns off. This is done by including an inductance and a capacitor in series with the load and keeping the circuit under-damped. Figure 2.8 shows the circuit.This type of commutation is used in Series Inverter Circuit. Circuit.
T
i
R
L
Vc(0) + -
Load
V
Fig. 2.8: Circuit for Self Commutation Commutation EXPRESSION FOR CURRENT
C
At t = = 0 , when the SCR turns ON on the application of gate pulse assume the current in the circuit is zero and the capacitor voltage is V C ( 0 ) .Writing the Laplace Transformation circuit of figure 2.8 the following circuit is obtained when the SCR is conducting.
R I(S)
T
sL
VC(0) 1 S CS + - + C
V S
Fig.: 2.9:
éëV - V C ( 0 ) ùû I ( S )
S
=
R + sL + C S éëV
=
1 C S
- V C ( 0 ) ùû
S RCs + s 2 LC + 1
C éëV
=
- V C ( 0 ) ùû
é ë
LC ê s 2 + s V
ù L LC úû
R
+
1
- V C ( 0 )
= s 2 + s
L R L
+
1 LC
(V - V ( 0 ) ) C
=
L 2
R R s + s + + æç ö÷ - æç ö÷ L LC è 2 L ø è 2 L ø 2
R
1
2
(V - V ( 0 ) ) C
L
= æ s + R ö ç 2 L ÷ è ø
é 1 æ R ö2 ù +ê -ç ÷ ú LC êë è 2 L ø úû
A
=
Where A
2
( s + d )
(V - V ( 0 ) ) = C
L
2
+ w 2
,
2
,
=
d
R 2L
R - æç ö÷ w = LC è 2 L ø 1
,
2
w is called the natural frequency I ( S ) =
A
w
w ( s + d )
2
+ w 2
Taking inverse Laplace transforms i (t ) =
A w
e-d t sin w t
Therefore expression for current i (t ) =
Peak value of current
V
- V C ( 0 ) w L
=
- R
t
e 2 L sin w t
(V - V ( 0 ) ) C
w L
Expression for voltage across capacitor at the time of turn off
Applying KVL to figure 2.8 vc
= V - vR - VL
vc
= V - iR iR - L
di dt
Substituting for i, vc
A
= V - R e -d t sin w t - L w
æ A e -d t sin w t ö ç ÷ dt è w ø d
A
A
vc
= V - R e-d t sin w t - L
vc
=V -
vc
A R = V - e-d t éê R sin wt + w L cos w t - L sin w t ùú w 2 L ë û
vc
=V -
w
A w
A w
e( w
dt
w cos w t - d e - d t sin w t )
e -d t [ R sin w t + w L cos w t - Ld sin w t ]
é R sin w t + w L cos w t ù úû ë2
e -d t ê
Substituting for A, vc ( t ) = V
-
(V - V ( 0 ) ) C
w L
vc ( t ) = V
-
é R sin w t + w L cos w t ù úû ë2
e -d t ê
(V - V ( 0 ) ) C
w
é R sin w t + w cos w t ù úû ë 2 L
e-d t ê
SCR turns off when current goes to zero. i.e., at w t = p . Therefore at turn off vc
=V -
(V - V ( 0 ) ) C
w
-dp
e
w
( 0 + w cos p )
-dp
vc
= V + éëV - VC ( 0 ) ùû e w - Rp
Therefore
vc
= V + éëV - VC ( 0 )ùû e 2 Lw
Note: For effective commutation the circuit should be under damped. 2
æ R ö < 1 ç 2 L ÷ LC è ø
That is
· With R = 0, and the capacitor initially uncharged that is V C ( 0 ) = 0 i= But
V w L
= w =
sin
1 LC
t LC
Therefore
i=
V L
LC sin
t LC
C sin L
=V
t
LC
and capacitor voltage at turn off is equal to 2V.
· Figure 2.10 shows the waveforms for the above conditions. Once the SCR turns off ·
voltage across it is negative voltage. p Conduction time of SCR = . w
V
C L
Current i
0
p/2
wt
p
2V Capacitor voltage
V
wt
Gate pulse
wt
wt -V Voltage across SCR
Fig. 2.10: Self Commutation – Wave forms of Current and Capacitors Voltage
RESONANT PULSE COMMUTATION (CLASS B COMMUTATION)
The circuit for resonant pulse commutation is shown in figure 2.1 1.
L T
i a b
C
IL
V
Load FWD Fig. 2.11: Circuit for Resonant Pulse Commutation
This is a type of commutation in which a LC series circuit is connected across the SCR. Since the commutation circuit has negligible resistance it is always under-damped i.e., the current in LC circuit tends to oscillate whenever the SCR is on. Initially the SCR is off and the capacitor is charged to V volts with plate ‘a’ being positive. Referring to figure 1.13 at t = t 1 the SCR is turned ON by giving a gate pulse. A current I L flows through the load and this is assumed to be constant. At the same time SCR short circuits the LC combination which starts oscillating. A current ‘i’ starts flowing in the direction shown in figure. As ‘i’ reaches its maximum value, the capacitor voltage reduces to zero and then the polarity of the capacitor voltage reverses ‘b’ becomes positive). When ‘i’ falls to zero this reverse voltage becomes maximum, and then direction of ‘i’ reverses i.e., through SCR the load current I L and ‘i’ flow in opposite direction. When the instantaneous value of ‘i’ becomes equal to I L , the SCR current becomes zero and the SCR turns off. Now the capacitor starts charging and its voltage reaches the supply voltage with plate a being positive. The related waveforms are shown in figure 2.12.
Gate pulse of SCR t1 V
t
p Capacitor voltage vab
t
I p
i
IL
p w
tC
t
Dt
ISCR
t Voltage across SCR t
Fig. 2.12: Resonant Pulse Commutation – Various Waveforms
EXPRESSION FOR t c , THE CIRCUIT TURN OFF TIME
Assume that at the time of turn off of the SCR the capacitor voltage vab
» -V and load current
I L is constant. t c is the time taken for the capacitor voltage to reach 0 volts from – V volts and is derived as follows. V
=
V =
1
t c
ò I dt
C 0
I L t c C
L
t c
=
VC I L
seconds
For proper commutation t c should be greater than t q , the turn off time of T. Also, the magnitude of I p , the peak value of i should be greater than the load current I L and the expression for i is derived as follows. The LC circuit during the commutation period is shown in figure 2.13.
L T
i + VC(0) =V
C
Fig. 2.13: LC circuit during the commutation period
The transformed circuit is shown in figure below. I(S) sL T
1 Cs +
-
V s
V I ( S ) =
s sL +
1 Cs
æ V ö Cs ç s ÷ I ( S ) = è2 ø s LC + 1 I ( S ) =
VC
æ è
LC ç s 2 +
ö ÷ LC ø 1
I ( S ) =
V L
1
´
s 2 +
1 LC
æ 1 ö V çè LC ÷ø 1 ´ I ( S ) = ´ 1 L æ 1 ö s 2 + LC çè LC ÷ø æ 1 ö ç ÷ C è LC ø I ( S ) = V ´ 1 L s 2 +
LC
Taking inverse LT C
i (t ) = V
Or
Therefore
i (t ) =
V w L
I p
LC
sin w t
= V
sin w t
1
w =
Where
L
= I p sin w t
C L
amps .
EXPRESSION FOR CONDUCTION TIME OF SCR
For figure 2.12 (waveform of i), the conduction time of SCR p = + Dt w
=
p w
æ I L ö ç I p ÷÷ è ø
sin -1 ç
+
w
RESONANT PULSE COMMUTATION WITH ACCELERATING DIODE
D2
iC(t)
IL
T1 C
L
iC(t)
T2
+ VC(0)
-
L O
T3
V
FWD
D
Fig. 2.14(a)
A diode D2 is connected as shown in the figure 2.14(a) to accelerate the discharging of the capacitor ‘C’. When thyristor T 2 is fired a resonant current iC ( t ) flows through the capacitor
= t 1 , the capacitor current iC ( t ) equals the load current I L and hence and thyristor T . 1 At time t current through T is reduced to zero resulting in turning off of T . 1 1 Now the capacitor current
iC ( t ) continues to flow through the diode D2 until it reduces to load current level I L at time t 2 . Thus the presence of D2 has accelerated the discharge of capacitor ‘C’.
iC IL 0
t
VC 0 V1 VC(O)
t1
t2 tC
Fig. 2.14(b)
t
Now the capacitor gets charged through the load and the charging current is constant. Once capacitor is fully charged T 2 turns off by itself. But once current of thyristor T reduces to zero 1 the reverse voltage appearing across T is the forward voltage drop of D2 which is very small. 1 This makes the thyristor recovery process very slow and it becomes necessary to provide longer reverse bias time. From figure 2.14(b)
t2
= p
LC - t1
VC ( t 2 ) = -VC (O ) cos w t 2 tC = t2 - t 1
Circuit turn-off time
COMPLEMENTARY COMMUTATION (CLASS C COMMUTATION, PARALLEL CAPACITOR COMMUTATION)
In complementary commutation the current can be transferred between two loads. Two SCRs are used and firing of one SCR turns off the other. The circuit is shown in figure 2.15. The working of the circuit can be explained as follows. Initially both T and T 2 are off; Now, T is fired. Load current I L flows through R1 . At the same 1 1 time, the capacitor C gets charged to V volts through R2 and T 1 (‘b’ becomes positive with respect to ‘a’). When the capacitor gets fully charged, the capacitor current ic becomes zero. To turn off T , reverse biases it, hence T turns 1 T 2 is fired; the voltage across C comes across T and 1 1 off. At the same time, the load current flows through R2 and T 2 .
IL R 1
R 2 ab
V
iC
C T1
T2
Fig. 2.15: Complementary Commutation
.
The capacitor ‘C’ charges towards V through R1 and T 2 and is finally charged to V volts with ‘a’ plate positive. When the capacitor is fully charged, the capacitor current becomes zero. To turn off T 2 , T is triggered, the capacitor voltage (with ‘a’ positive) comes across T 2 and T 2 turns off. 1 The related waveforms are shown in figure 2.16. EXPRESSION FOR CIRCUIT TURN OFF TIME t c
From the waveforms of the voltages across T 1 and capacitor, it is obvious that t c is the time taken by the capacitor voltage to reach 0 volts from – V volts, the time constant being RC and the final voltage reached by the capacitor being V volts. The equation for capacitor voltage
vc ( t ) can be written as
+ (Vi - V f ) e -t t
vc ( t ) = V f
Where V f is the final voltage, V is the initial voltage and t is the time constant. i At
t
= t c , vc ( t ) = 0 , t = R1C , V f
= V , Vi = -V , - t c
Therefore
0 =V
+ ( -V - V ) e
R1C
- t c
0 =V
- 2Ve
R1C
-t c
Therefore
V
= 2Ve
R1C
-t c
0.5 = e
R1C
Taking natural logarithms on both sides ln0.5 =
tc
-t c R1C
= 0.693R1C
This time should be greater than the turn off time t q of T . 1 Similarly when T 2 is commutated tc
= 0.693R2C
And this time should be greater than t q of T 2 .
R1 = R2
Usually
=R
Gate pulse of T2
Gate pulse of T1
p
t
V
IL
Current through R 1
V R1
2V R1
t 2V
Current through T 1
R2
V R1
t Current through T 2
2V R1 V R2
t
V Voltage across capacitor v ab
-V
tC
tC
Voltage across T 1
t
tC
Fig. 2.16: waveform of Complementary Commutation IMPULSE COMMUTATION (CLASS D COMMUTATION)
The circuit for impulse commutation is as shown in figure 2.17.
IL
T1 T3 V
VC(O) L
+
C T2 FWD
L O A D
Fig. 2.17: Circuit for Impulse Commutation
The working of the circuit can be explained as follows. It is assumed that initially the capacitor C is charged to a voltage VC ( O ) with polarity as shown. Let the thyristor T 1 be conducting and carry a load current I L . If the thyristor T is to be turned off, T 2 is fired. The capacitor voltage 1 comes across T , reverse biased and it turns off. Now the capacitor starts charging through 1 T is 1 T 2 and the load. The capacitor voltage reaches V with top plate being positive. By this time the capacitor charging current (current through T 2 ) would have reduced to zero and T 2 automatically turns off. Now T and T 2 are both off. Before firing T 1 1 again, the capacitor voltage should be reversed. This is done by turning on T 3 , C discharges through T 3 and L and the capacitor voltage reverses. The waveforms are shown in figure 2.18.
Gate pulse of T3
Gate pulse of T2
Gate pulse of T1 t
VS Capacitor voltage t
VC tC
Voltage across T1 t
VC
Fig. 2.18: Impulse Commutation – Waveforms of Capacitor Voltage, Voltage across T 1 . EXPRESSION FOR CIRCUIT TURN OFF TIME (AVAILABLE TURN OFF TIME) t c
t c depends on the load current I L and is given by the expression VC
=
1
t c
ò I dt
C 0
L
(assuming the load current to be constant) V C =
t c
=
I L t c C
VC C I L
seconds
For proper commutation t c should be > t q , turn off time of T . 1 Note:
· T is turned off by applying a negative voltage across its terminals. Hence this is voltage 1 ·
commutation. t c depends on load current. For higher load currents t c is small. This is a disadvantage of
·
this circuit. When T 2 is fired, voltage across the load is V
+ V C ; hence the current through load
shoots up and then decays as the capacitor starts charging.
EXTERNAL PULSE COMMUTATION (CLASS E COMMUTATION)
T1
VS
T2
R L
L
2VAUX
+
-
C
T3
VAUX
Fig. 2.19: External Pulse Commutation
In this type of commutation an additional source is required to turn-off the conducting thyristor. Figure 2.19 shows a circuit for external pulse commutation. V S is the main voltage source and V UX is the auxiliary supply. Assume thyristor T is conducting and load R L is connected across 1 supply V S . When thyristor T 3 is turned ON at t = 0 , V UX , T 3 , L and C from an oscillatory circuit. Assuming capacitor is initially uncharged, capacitor C is now charged to a voltage 2V AUX with upper plate positive at t = p LC . When current through T 3 falls to zero, T 3 gets commutated. To turn-off the main thyristor T , 1 thyristor T 2 is turned ON. Then T 1 is subjected to a reverse voltage equal to VS
- 2V AUX . This results in thyristor T being turned-off. Once T is off capacitor 1 1
‘C’ discharges through the load R L LOAD SIDE COMMUTATION
In load side commutation the discharging and recharging of capacitor takes place through the load. Hence to test the commutation circuit the load has to be connected. Examples of load side commutation are Resonant Pulse Commutation and Impulse Commutation. LINE SIDE COMMUTATION
In this type of commutation the discharging and recharging of capacitor takes place through the supply.
L
T1
+
IL +
T3 VS
_ C Lr
FWD
L O A D
T2
_ Fig.: 2.20 Line Side Commutation Circuit
Figure 2.20 shows line side commutation circuit. Thyristor T 2 is fired to charge the capacitor ‘C’. When ‘C’ charges to a voltage of 2V, T 2 is self commutated. To reverse the voltage of capacitor to -2V, thyristor T 3 is fired and T 3 commutates by itself. Assuming that T 1 is conducting and carries a load current I L thyristor T 2 is fired to turn off T . 1 The turning ON of T 2 will result in forward biasing the diode (FWD) and applying a reverse voltage of 2V across T . 1 This turns off T , 1 thus the discharging and recharging of capacitor is done through the supply and the commutation circuit can be tested without load. 2.4 DC-DC Converters:
A chopper is a static device which is used to obtain a variable dc voltage from a constant dc voltage source. A chopper is also known as dc-to-dc converter. The thyristor converter offers greater efficiency, faster response, lower maintenance, smaller size and smooth control. Choppers are widely used in trolley cars, battery operated vehicles, traction motor control, control of large number of dc motors, etc….. They are also used in regenerative braking of dc motors to return energy back to supply and also as dc voltage regulators. Choppers are of two types:
· Step-down choppers · Step-up choppers. In step-down choppers, the output voltage will be less than the input voltage whereas in step-up choppers output voltage will be more than the input voltage.
