BASIC DIGITAL ELECTRONIC EXPERIMENTS FOR PHYSICISTS
A.Necmeddin YAZICI
D0
D1
D2 A D3
B E
University of GAZİANTEP
BASIC DIGITAL ELECTRONIC EXPERIMENTS FOR PHYSICISTS
A.Necmeddin YAZICI
Faculty of Engineering Department of Engineering Physics
University of GAZİANTEP 2001
ii
University of Gaziantep, (2001). All rights reserved. This book, or therefore, may not be reproduced in any form without permission of the publisher.
Published by the University of Gaziantep Gaziantep-Turkey
ISBN………………………..
University of Gaziantep Presss Tlf: 0 (342) 360 12 00 – 15 72
iii
CONTENTS
Page
1.
Contents
iv
2.
Preface
v
2.
EP 427 Digital Electronic Introductory Remarks for the Student
1
3.
Introduction
4
3a.
Laboratory Rules
4
3b.
Safety Precautions
4
3c.
Laboratory Report
5
4.
Experiment 1 : Basic Logic Gates
7
5.
Experiment 2 : Boolean Algebra and Simplification of Logic Equations
17
6.
Experiment 3 : DeMorgan’s Theorem
22
7.
Experiment 4 : Exclusive-OR and Exclusive-NOR Gates
25
8.
Experiment 5 : Half-Adder and Half-Subtractor
29
9.
Experiment 6 : Binary Comparators
32
10.
Experiment 7 : Parity Generators and Checkers
34
11.
Experiment 8 : Full-Adder and Full-Subtractor
38
12.
Experiment 9 : Code Converters
44
13.
Experiment 10 : Decoders and Encoders
48
14.
Experiment 11 : Multiplexers and Demultiplexers
55
15.
Experiment 12 : Flip-Flops
62
16.
References
67
17.
Appendix A : Glossary of Login and Integrated-Circuit Terminology
68
18.
Appendix B: Supplementary Index of ICs
74
19.
Appendix C: TTL Pin Connections
76
iv
PREFACE
This laboratory manual book has been developed to provide laboratory training and experience in elementary digital electronic for physicists and physics engineers using integrated circuits in the laboratory environment of the industrial electronics laboratory. Thus, this manual has been prepared as an auxiliary book for EP 427 Digital Electronic course. This course has been taught in the Department of Engineering Physics for many years as a technical elective course at senior level. Twelve experiments are included in this manual to provide through coverage of basic digital principles. They begin with a series of experiments on the principles of basic logic gates and their application in digital electronics and follow with the last experiment of flip-flops. Many types of IC logic families have been explained in the relevant sections and pin connections of many TTL have been given at the end of the laboratory manual book. Each experiment is divided into four sections: 1-) Purpose, 2-) Theory, 3-) Experimental Procedure, and 4-) Discussion and Conclusions about the experiment. The theory section gives required brief information about the experiment’s subject. Although the theoretical background for the experiment is provided at the theory section through each experiment, the necessary further information should be obtained during the theoretical consideration of this course and from many auxiliary books that are available in our library. The discussion and conclusion part should include the necessary interested questions about the experiment and related subjects to understand very well the experiment and its related subjects and also for the evaluation and the significance of the results of the experiment. I wish to express my thanks to Expert Ziya GESOĞLU, MsC student V.Emir KAFADAR and for all of the staffs in Engineering Physics Department for their assistance and friendship during the preparation of this laboratory manual. Especially, I would like extent my thanks and appreciation to my wife and daughters for their patience and encouragement during the preparation of this book.
Assist.Prof.Dr.A.Necmeddin YAZICI December 2001,Gaziantep University
v
EP 427 DIGITAL ELECTRONIC INTRODUCTORY REMARKS FOR THE STUDENT In analog electronic circuits, voltage levels can vary continuously in time. A transistor amplifier, for example, can amplify any voltage level within a specified range. Digital circuit voltage levels, however are restricted to values which are predetermined. In most digital circuits there are only two allowed voltage levels which are 0 V and 5 V. These voltage levels are referred to as logic levels. The levels 0 V and 5 V correspond to logic-0 and logic-1 as binary variable. This shows that any logic function which uses binary variables can be implemented by digital circuits. In digital circuits, logic-1 and logic-0 may be represented by voltage regions. The voltage regions between 2 V and 4 V may be accepted as logic-1. Similarly, the region between -0.5 and 0.5 is taken as logic-0. The intermediate region between these allowed regions is crossed only during state transition. The input terminals of digital circuits accept binary signal within the allowable tolerances and respond at the output terminal with binary signals that fall within the specified tolerances. Digital circuits are invariably constructed with integrated circuits (IC). An IC is a small silicon semiconductor crystal, called a chip containing various electrical components. The various components are interconnected inside the chip to form an electronic circuit. The chip is mounted on a metal or plastic package, and connections are welded to external pins to form the IC. The envelope of the IC package is made of plastic or ceramic. Most packages have standard sizes, and the number of pins ranges from 8 to 64. IC has a numeric designation printed on the surface of the package for identification. Each vender published a data book or catalog that provides the necessary information concerning the various products. The IC’s in the experiment are all in the dual-in-time 14-pin or 16-pin configuration. They do not have a great over voltage tolerance before their dissipation is exceeded. The procedure of calibrating the cathode ray oscilloscope (CRO) and checking the power supply voltage against IC will protect it against over voltage and at the same time provide some additional CRO experience. Although the wiring in some experiments is somewhat complex, a wiring layout as clone as possible to the circuit drawing will help in trouble-shooting.
1
A long lead from a bistable, or counter, or intermediate outputs of a counter, or monostable multivibrator may cause undesired loading and prevent the bistable from toggling or dividing properly, or the monostable from functioning properly. If such difficulties are encountered, a composition of 2200 decoupling resistor at the IC end of the lead can eliminate the loading problems. The lead length from the 2200 resistor to the IC should be kept short. This decoupling may be needed both for the CRO vertical input and for external triggering. The pin terminals progress in a counterclockwise direction seen from the top side away from the pins. The IC’s are in either 14-pin or l6-pin location by an identifying symbol, or the location pins 1 and 14 (14 pin IC) or pins 1 and 16 (16 pin IC) are identified by an index notch at the end of the case where these pins are located This is illustrated in the below figure.
The laboratory sheets were developed to provide you with laboratory experiments and experience to let you more easily understand the theoretical material covered in the classroom, and to provide you practical illustrations of how combinations of these simple building blocks can yield complex and useful systems. To analyze the performance of these digital blocks, the most useful measuring tool is the CRO because it not only measures voltage but it can measure time, displaying both the waveforms of digital electronics and their relative time of occurrence. Almost all measurements in the experiments are performed by the CRO. While wiring the circuits diagrams use the connecting wires as short as possible. Leads that are too long introduce capacitive loading and may introduce spurious pulses and glitches. If trouble occurs, neat and orderly wiring will make it easier to locate the fault. Measure voltages as accurately as possible. Be sure that the CRO is measuring voltage correctly. When CRO sketches are required, they should be drawn carefully on a scaled paper. They should be drawn accurately enough so that you can read voltage and time from
2
them at any point. Generator waveforms should be displayed on the CRO with respect to the graticule as closely as possible to those shown in manual. Data obtained experimentally with the CRO are in volts. Then translate these voltage readings into loqic-1 and logic-0, depending on the voltage ranges mentioned before. In the discussion section these logic levels are analyzed. Careful study of the data and of your textbook will enable you to answer the questions asked in discussion.
3
INTRODUCTION This part gives us brief information and general rules of laboratory work. It also includes basic information of safety precautions, laboratory practice and laboratory report. A-) LABORATORY RULES: 1. There are nine set in the circuit analysis laboratory room. If the student number is higher than 18 then everybody has to choose a partner to perform the experiments together with. Each pair will be given a group number. Nobody can change his partner unless permission given by the instructor. 2. There should be no laud talking in the laboratory. 3. No smoking in the laboratory. If you must smoke ask for permission from your laboratory instructor to go out into the hall. 4. No visitors are permitted in laboratory. 5. Bring your laboratory book each session. 6. Exactly, read the laboratory sheet and know procedure. 7. If an instrument in your set gets out of work, please inform the assistant or instructor. 8. No transfer of any equipment between the tables by the students. 9. During the experiments, some important subject will be given to you by your assistant or instructor. If any point is not understood after you starting the experiment please ask your assistant and instructor clearly. 10. Don’t supply the high voltage to the circuit. 11. Before leaving the laboratory please arrange everything in your set to the first position. B-) SAFETY PRECAUTIONS 1.
Performing of an experiment requires a careful reading of laboratory manual, a clear understanding of each step involved in the required procedure before its actual performance and often a written, planned program (notes on references, rough outline of proposed procedure, circuit to be investigated, preliminary calculations). Science organization is a guiding principle to be followed throughout the preparation, performance and reporting of an experiment.
2.
Always disconnect the power supply before connecting or charging to your circuit.
3.
Be sure that the measuring instruments such as voltmeter, ammeter, etc. are connected in correct places with sufficient ranges on the circuit. i.e, please pay attention that the ammeter is not used in the voltmeter position and vice versa. 4
4.
If the power supply is active on the circuit, an ohmmeter is never connected to this circuit.
5.
After the planning good experimental organization entails the neat assembly of the circuits so that they may be easily visualized and checked, and the neat entering of data with descriptive headings and complete information regarding meters and apparatus used.
6. Make a rough plot of the data in the laboratory as soon as they have been taken, whenever possible. If there are points out of line, they can be rechecked while the apparatus is still set up. 7.
The laboratory notebook is the record of what you did in the laboratory, together with the result, calculations, and conclusion which may be drawn from your experiments. The recording of data on separate pages of paper and copying it into the notebook is not permitted.
8.
If you must correct an entry in your notebook, draw a line through the incorrect entry, and write a brief explanation of the correction.
9.
The lab report must be turned in due the next lab period (usually the following week). Late lab reports will not be accepted.
10. Before you leave the laboratory, you must have your instructor or assistant sign his initials in your notebook. This says he is satisfied that you have cleaned up properly and that the data is satisfactorily recorded in your notebook. No lab report will be accepted without this signature. 11. Students are expected to do their own lab work and write their own lab reports. 12. Ratings of the components must be properly selected. C-) LABORATORY REPORT 1.
All laboratory reports should be written to an A4 paper.
2.
Each report should give sufficient information about the experiment.
3.
All pages should be numbered. The first page should contain course number and name, all partners name, group number and also name of the experiment.
4.
All reports must be written in pencil, ball-point pen, typewriter but only in the headings colored pencil or ball-points are allowed.
5.
Below is a brief outline of how your report should be kept:
At the top of second page:
5
Title of the experiment and the data,
A short statement of the object of the experiment,
The necessary theoretical work or calculations about the preliminary work,
For step "b" and "c", you should read the experiment at home and complete these steps before coming to lab,
Procedure, observation, and data. If the data is to be recorded in a chart, you may prepare the chart before coming to lab.
Calculations. Sometimes these must be done during the lab period; at other times you will be permitted to complete them at home. It is suggested that you do the rough calculations on a piece of scratch paper before making any entries in your notebook.
Discussion (or results). Conclusion which may be drawn from the experiment, possible sources of errors (when applicable), and answers to the questions asked in the discussion part.
6
EP 427 DIGITAL ELECTRONIC EXPERIMENT-1 BASIC LOGIC GATES 1-) PURPOSE : To study the operation principles of basic digital logic gates AND, OR, INVERTER, NAND, NOR and the representation of their functions by truth tables, logic diagrams and Boolean algebra. 2-) THEORY : In the Integrated Circuit’s (IC) inputs and outputs occur as voltage levels. These voltage levels may be measured by some instruments and depending on the predefined voltage ranges they are accepted as logic-1 or logic-0. The two digits in the binary system, 1 and 0, are called bits, which is contraction of binary digit. During our experiments, any measured voltage between 2.5 and 5.0 V will be considered as logic-1 and the voltage between –0.5 and 0.5 V will be accepted as logic-0. Due to the type of the ICs used, these ranges may vary considering the supply voltage connected. Despite the difference in voltage levels, a basic operation will be the same. As shown in Figure 1.1, each voltage range has an acceptable deviation from each other by a transition region. Volt 5.0 Tolerance allowed for logic-1
Logic-1 3.75 2.5 Transition Region 0.5 Logic-0 0 -0.5
Tolerance allowed for logic-0 Figure 1.1 : Example of binary signals.
Electronic digital circuits are also called logic circuits. Logic gates are the basic building blocks for forming digital electronic circuitry. Logic circuits that perform the
7
logic operations of AND, OR, NOT (Inverter), NAND and NOR are shown with their graphics symbols, algebraic functions and truth tables in Table 1.1. Digital circuits, switching circuits, logic circuits and logic gates are used in the same means. Table 1.1 : Truth table, algebraic function and graphic symbol of basic 2-input logic gates. Name
Graphic Symbol
x y
AND
OR
NOT
NAND
NOR
F=x.y
F
x
F
y
x
Algebraic Function
F=x+y
F
x y
x y
Truth Table x
y
F
0 0 1 1
0 1 0 1
0 0 0 1
x
y
F
0 0 1 1
0 1 0 1
0 1 1 1
F=x’
F=(x.y)’
F
F=(x+y)’
F
8
x
F
0 1
1 0
x
y
F
0 0 1 1
0 1 0 1
1 1 1 0
x
y
F
0 0 1 1
0 1 0 1
1 0 0 0
The operation principles of basic five logic gates can be explained as follows: 2.1-) The AND Gate : The AND gate is one of the basic gates from which all functions are constructed. It is a multi-input circuit that may have two or more than two inputs in which the output is a logic-1 only if all inputs are logic-1. The output produces a logic-0 signal if any input is logic-0. The truth table, algebraic function (Boolean equation) and graphic symbol of 2-input AND Gate are shown in Table 1.1. 2.2-) The OR Gate: The OR gate is another of the basic gates from which all logic functions are constructed. It is also a multi-input circuit that may have two or more than two inputs in which the output is a logic-1 when any of the inputs is a logic-1. Its output becomes logic-0 if all input signals are logic-0. The truth table, algebraic function (Boolean equation) and graphic symbol of 2-input OR Gate are shown in Table 1.1. 2.3-) The INVERTER (NOT) Gate : The inverter (NOT circuit) performs the operation called inversion or complementation. The inverter changes one logic level to the opposite level. In terms of bits, the output is logic-0 when input is logic-1, and the output is logic-1 when the input is logic-0. The truth table, algebraic function (Boolean equation) and graphic symbol of an INVERTER (NOT) Gate are shown in Table 1.1. 2.4-) The NAND Gate : The NAND gate is a popular logic element because it can be used as a universal gate; that is, NAND gates can be used in combination to perform the AND, OR and inverter operations. The NAND gate is simply AND followed by INVERTER gate. Therefore, NAND gate produces a logic-0 output only all inputs are logic-1. When any of the inputs is logic-0, the output will be logic-1. The truth table, algebraic function (Boolean equation) and graphic symbol of 2-input NAND Gate are shown in Table 1.1. 2.5-) The NOR Gate : The NOR gate, like the NAND gate, is a useful logic element because it can also be used as a universal gate, that is, NOR gates can be used in combination to perform the AND, OR and inverter operations. Then it is simply OR followed by INVERTER gate. The truth table, algebraic function (Boolean equation) and graphic symbol of 2-input NOR Gate are shown in Table 1.1. The NAND and NOR functions are the complements of AND and OR functions, respectively. The NAND and NOR gates are extensively used as standard logic gates.
9
2.6-) VOLTAGE TABLE : Representation for the measured voltages at the indicated points on a logic circuit for every possible combination of the inputs. 2.7-) TRUTH TABLE : Representation of the output logic levels of a logic circuit for every possible combination of the inputs. This is the best done by means of a systematic tabulation. The truth tables of some logic gates are given in Table 1.1. 2.8-) IC PIN CONNECTIONS : Each of the ICs used are in a 14-pin dual-in-line case. The base pins progress in a counterclockwise direction as seen from the side away from the pins, as shown in Figure 1.2. | 14
| 13
| 12
| 11
| 10
| 9
| 8 Top view (away from pins)
Index notch Pin 1 identification
1 |
2 |
3 |
4 |
5 |
6 |
7 |
Figure 1.2 : IC Pin location, 14-pin dual-in-line case. The basic logic gates are available as integrated circuits (ICs). The logic behaviour of various basic IC gates are given as: 7404 7408 7432 7400 7402
Hex inverters Quadruple 2-input AND gates Quadruple 2-input OR gates Quadruple 2-input NAND gates Quadruple 2-input NOR gates
the pin assignments of these gates are shown in Figure 1.3. In here, the terms “Hex and “Quadruple” means that there are six and four gates within the package, respectively. PRELIMINARY PRECAUTIONS : It is extremely important that the exact required voltage be applied to the IC. The power supply should be the last connections made. Before connections to the power supply are made, its voltage should be checked with power supply’s voltmeter and a calibrated CRO. All measurements in this experiment are made with a calibrated CRO. Before making any measurement, calibrate the CRO. After the CRO is calibrated, use it to check the power supply voltage. If a disagreement occurs between the power supply voltmeter reading and the CRO measurement, call the laboratory assistant or your instructor. 10
Figure 1.3 : Basic digital gates in IC packages with identification number and pin assignments. 3-) EXPERIMENTAL PROCEDURE : For each part of the experiment apply the indicated voltage which is given below and make voltage measurements at the points indicated to complete the voltage tables. Use the Cathode Ray Oscilloscope (CRO) to measure the voltage. Use CRO in a sensitivity of 1 V/div and make measurements to within 0.1 Volt. 11
Important Note : Apply Vcc= + 5.0 Volt is to the pin-14 and 0.0 (ground) apply to the pin7 for all ICs. 3.1-) INTGRATED CIRCUITS (ICs) : Note : The ICs type 7408, 7432, 7400 and 7402 have four 2-input AND, OR, AND and NOR gates within their packages, respectively. The IC type 7404 has six one-input INVERT gates within its package. You must use only one of these gates in this experiment. For example, the gate 7408 AND gate whose input pins are pins 1 and 2 and whose output pin is pin 3. If it is defective, you must select one of the other gates in the same package. 1-) Select one of the gate from IC, 2-) Set up the following circuit, 3-) Control the selected basic logic gates, 4-) If it is defective, you must select one of the other gates in the same package, 5-) Complete truth table of basic logic gates, 6-) Repeat above steps for all basic logic gates. 3.1.a-) OR Gate (7432) : 5.0 V 0
+ +5 Pin-1
7432 Pin-3
Pin-2 Figure 1.4 : IC OR gate. Table 1.2 : IC OR gate. Pin 1
Pin 2
0
0
0
+5
+5
0
+5
+5
12
Pin 3
3.2.b-) AND Gate (7408) :
5.0 V -
+ +5
0
Pin-1 7408
Pin-3
Pin-2 Figure 1.5 : IC AND gate. Table 1.3 : IC AND gate. Pin 1
Pin 2
0
0
0
+5
+5
0
+5
+5
Pin 3
3.3.c-) INVERTER (NOT) Gate (7404) : 5.0 V 0
+ +5 Pin-1 7404
Pin-2
Figure 1.6 : IC INVERTER (NOT) gate. Table 1.4 : IC NOT gate. Pin 1
Pin 2
0 +5
13
3.4.d-) NOR Gate (7402) : 5.0 V -
+ +5
0
Pin-1 7402
Pin-3
Pin-2 Figure 1.7 : IC NOR gate. Table 1.5 : IC NOR gate. Pin 1 Pin 2 Pin 3 0
0
0
+5
+5
0
+5
+5
3-5.e-) NAND Gate (7400) : 5.0 V 0
+ +5 Pin-1 7400
Pin-3
Pin-2 Figure 1.8 : IC NAND gate. Table 1.6 : IC NAND gate. Pin 1
Pin 2
0
0
0
+5
+5
0
+5
+5
14
Pin 3
4-) DISCUSSIONS : 4.1-) Convert all voltage tables completed in the experimental parts into logic tables. 4.2-) Compare your experimental results with theoretical results. 4.3-) Explain the basic logic gates, complete three and four input logic gates truth table. 4.4-) Realize NAND and NOR functions using only AND, OR and INVERT gates. 4.5-) What is the purpose of a truth table and algebraic function? 4.6-) What is the purpose of an inverter in a digital circuit? 4.7-) If we were to build a truth table for a 16-input AND gate, how many different combinations of inputs would we have? 4.8-) Make a truth table for the diagram in Figure 1.9. 4.9-) Considering the given truth table, realize the function using with minimum number of gates. C
A
D
B F E
Figure 1.9 : A combinational basic logic circuit. A
B
0
0
0
1
1
0
1
1
C
D
E
F
4.10-) Sensors are used to monitor the pressure and the temperature of a chemical solution stored in a vat. The circuitry for each sensor produces a HIGH voltage when a specific maximum value is exceeded. An alarm requiring a LOW voltage input must be activated when either the pressure or the temperature is excessive. i-) Tabulate the truth table of the system. ii-) Design a circuit for this application. 4.11-) Design a burglar alarm using basic logic gates. 15
4.12-) Give a brief explanation about Negative-OR and Negative-AND gates. 4.13-) How is a logic probe and logic pulser used to troubleshoot digital ICs? 4.14-) A particular logic family defines a LOW signal to be in the range 0.0-0.8 V and a HIGH signal to be in the range 2.0-3.3 V. Under a positive-logic convention, indicate the logic value associated with each of the following signal levels : (a) 0.0 V
(b) 3.0 V
(c) 0.8 V
(d) 1.9 V
(e) 2.0 V
(f) 5.0 V
(g) –0.7 V
(h) –3.0 V
4.15-) Repeat 4.14 using a negative-logic convention.
16
EP 427 DIGITAL ELECTRONIC EXPERIMENT-2 BOOLEAN ALGEBRA AND SIMPLIFICATION OF LOGIC EQUATIONS 1-) PURPOSE : To study the methods of representing and simplifying logic equations by Boolean Algebra laws and rules. 2-) THEORY : Generally, you will find that the simple gate functions AND, OR, NAND, NOR and INVERTER are not enough by themselves to implement the complex requirements of digital systems. The basic gates will be used as the building blocks for the more complex logic that is implemented by using combinations of gates called combinational logic. Combinational logic employs the use of two or more of the basic logic gates to form a more useful, complex function. The systematic reduction of logic circuits is performed using Boolean algebra. Boolean algebra is the mathematics of digital systems. A basic knowledge of Boolean algebra is indispensable to the study and analysis of logic circuits. In the previous experiment (Ex.1), Boolean operations and expressions in terms of their relationship to NOT, AND, OR, NAND, and NOR gates were introduced. This experiment reviews the material and provides additional definitions and information. Additionally, it demonstrates the relationship between a Boolean function and the corresponding logic diagram. The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented. The exact implementation of many digital logic circuits will result in a circuit those functions as expected. Nevertheless, many such circuits can be reduced to a simpler form by the application of Boolean algebra and by Karnaugh mapping. The basic Boolean reducing equations are given below.
(A’)’=A +5V A.1=A
A.A=A
0V A.0=0
A.A’=0
+5V A+1=A
A+A=A 17
0V A+0=A
A+A’=1
Many times a complex logic circuit can reduce its simplest form or change its form to a more convenient one to implement the expression most efficiently by using these rules as a base. In simplification procedures, a variable and its complement are treated as separate variables and logic equations can be expanded and combined as in ordinary algebra using the priorities of ordinary algebra. All Boolean expressions, regardless of their form, can be converted into either of two standard forms: the sum-of-products for (SOP) or the products-of-sum form (POS). Reductions can be made using the Boolean algebra simplification techniques or Karnaugh maps which provide a graphical/visual means of logic simplifications. 3-) EXPERIMENTAL PROCEDURES : 3.1-) To obtain the correct wave shapes it is necessary to calibrate your CRO using a Square Wave Generator (SWG). a-) Connect the output of SWG to the input of CRO. b-) Adjust the output of SWG to +5.0 Volt at 1 kHz. c-) View the shape of square wave and adjust the CRO horizontal sweep rate so that each cycle occupies two horizontal division as shown in Figure 2.1.
Function Generator + 5.0 Volt SWQ 1 kHz +
CRO
Figure 2.1 : Cathode Ray Oscilloscope (CRO) connections to Square Wave Generator (SWG) and its output waveform. 3.2-) There are two procedures in this section. In one; a voltage table must be made and in the other, waveforms are viewed on the CRO and sketched on the graph paper. a-) When a table must be made, use the CRO to make voltage measurements at the points indicated to complete the table. b-) When a signal input is applied from the SWG, view the waveforms on the CRO and sketch the waveforms at the indicated points. 18
PRECAUTIONS! : For all IC’s in this experiment Vcc=+5.0 Volt to pin-14, pin-7 to ground (0.0 Volt). 3.3.1-) Construct Figure 2.2 and make voltage tables and sketch the waveforms of variables x and y at the points indicated on Figure 2.2. 5 Volt 0
+ +5 Pin-1
Pin-3 x
Pin-2
y
A Figure 2.2 : A combinational logic circuit with NAND and inverter gates. Table 2.2 : Pin 1
Pin 1 at + 5.0 V
Pin 1 at + 5.0 V
Pin 2 (A)
x
y
Pin 1 at 0V
Pin 1 at 0V
x
y
19
x
y
3.3.2-) Construct Figure 2.3 and complete its voltage tables at the indicated points and sketch the waveforms of variable f. 5 Volt -
+
0
+5 A
B
x
f y
Figure 2.3 :A basic logic circuit. Table 2.3 : A
x
B
y
f
x
y
f
4-) DISCUSSIONS : 4.1-) Construct voltage and logic tables for all parts of the experimental procedure. Comment about the implemented simplifications and any contradictions between experimental observations and theoretical expectations. 20
4.2-) Complete three and four input logic gates timing diagrams. 4.3-) Simplify the following functions using Boolean simplification techniques; a-) F=A(A+B) b-) F=AB+AB’+A’B c-) F=(A+C’)(A+D)(B+C’)(B+D) d-) F=A(A+B)+ A’(A+B)’ e-) F=A+ABC+AB+A’BC 4.4-) Design of a logical device that receives a four-bit binary number A4A3A2A1, and indicate the prime numbers. 4.5-) When the input waveforms (A,B) are supplied to a logic circuit, the output waveform (F) is obtained as shown in figure 2.4. Implement the logic circuit inside the box using minimum number of gates. A B
A B Logic Circuit
F
Figure 2.4 : Input and output waveforms of a logic circuit.
21
F
EP 427 DIGITAL ELECTRONIC EXPERIMENT-3 DeMORGAN’S THEOREM 1-) PURPOSE : To simplify and modify Boolen logic equations by means of DeMorgan’s theorem to arrive at simplified equivalent equations. 2-) THEORY : Frequently, the direct representation of a logic circuit results in a form that is not the most desirable immediately. For example, the solution may yield OR/NOR, where as it is desired to use AND/NAND. Sometimes the system solution results in a combination of OR/NOR and AND/NAND when a single form of logic is desired. To simplify circuits containing NANDs and NORs, we need to use a theorem developed by the mathematicians Augustus De Morgan. DeMorgan’s theorem permits conversion of logic for OR/NOR to AND/NAND and AND/NAND to OR/NOR. DeMorgan’s is given by the equations. (A+B)’=A’B’ (AB)’=A’+B’ Also, for three or more variables, (A+B+C)’=A’B’C’ (ABC)’=A’+B’+C’ The procedure in applying DeMorgan’s theorem is the following: 1-) Replace AND with OR or OR with AND. 2-) Invert the variables. 3-) Invert the final result. 4-) If possible, simplify by applying double inversion. DeMorgan’s theorem is applicable to any number of variables and to the whole or any part of a Boolean equation. 3-) EXPERIMENTAL PROCEDURES : For each part of the experiment, wire the circuits shown and use the Cathode-RayOscilloscope (CRO) to make voltage measurements at the points indicated to make the associated table. As you perform the experiment, for each point on the logic diagram
22
express the Boolean equation in terms of the input variables and write it on the diagram. For all the ICs in this experiment; apply Vcc=5.0 Volt to pin-14 and ground 0 volt to pin-7. 3.1-) Set up the following logic circuit (Figure 3.1) and complete its voltage tables at the indicated points and then verify the DeMorgan’s theorem.
5 Volt -
U
+
X
+5
0
B
A
V
Y
W Figure 3.1 : A combinational logic circuit to proof DeMorgan’s Theorem. Table 3.1. A
B
0
0
0
5
5
0
5
5
U
V
W
X
Y
3.2-) Set up the following logic circuit (Figure 3.2) and complete its voltage tables at the indicated points and then verify the DeMorgan’s theorem. 5 Volt 0
U
+
X
+5 A
B V
Y
W Figure 3.2 : Another combinational logic circuit to proof DeMorgan’s theorem.
23
Table 3.2. A
B
0
0
0
5
5
0
5
5
U
V
W
X
Y
4-) DISCUSSIONS : 4.1-) For part 3.1, what are the Boolean algebra equations of U, V, W, X and Y in terms of the variables A and B? Express the DeMorgan’s relationship between A, B, X and Y. Simplify the output using DeMorgan’s theorem and then draw them with a minimum number of basic logic gates. 4.2-) Repeat above question for part 3.2. 4.3-) Apply DeMorgan’s theorems to the expressions A’B’C’, A’+B’+C’, A’B’C’D’, A’+B’+C’+D’, and (A’B’C’D’)’. 4.4-) Why is DeMorgan’s theorem important in the simplification of Boolean equations? 4.5-) Use DeMorgan’s theorem to prove that a NOR gate with inverted inputs is equivalent to an AND gate. 4.6-) Simplify the following Boolean equations applying DeMorgan’s theorem and Boolean algebra simplification techniques. a-) X=[(AB)’+CD]’ + (ACD’)’ b-) Y=(ABC’+D)’ + (AB’+BC’)’ 4.7-) According to DeMorgan’s theorem, the complement of X + YZ is X’Y’ + Z’. Yet both functions are 1 for XYZ = 110. How can both a function and its complement be 1 for the same input combination? What is wrong here?
24
EP 427 DIGITAL ELECTRONIC EXPERIMENT-4 EXCLUSIVE-OR AND EXCLUSIVE-NOR GATES 1-) PURPOSE : To describe the operation principles and methods of generating the Exclusive-OR and Exclusive-NOR functions. 2-) THEORY : The exclusive-OR and exclusive-NOR gates are actually formed by a combination of other basic logic gates already discussed in experiment 1. However, because of their fundamental importance in many applications, these gates are treated as basic logic elements with their own unique symbols. 2.1-) The Exclusive-OR Gate : The exclusive-OR, abbreviated XOR or EOR. The exclusive-OR gate has a graphic symbol similar to that of the OR gate, except for the additional curved line on the input side. The exclusive-OR is an odd function, i.e.; it is equal to 1 if the input variables have an odd number of 1’s. This means that when the bits are alike, the EOR output is a 0; and when the bits are not alike, the EOR output is a 1 for a two bits inputs exclusive-OR gate. If the inputs are represented by A and B, the equation of EOR is; X=AB’+A’B=(AB+A’B’)’=AB
(4.1)
Although there are many ways of implementing the EOR, they can be shown to reduce to one of the forms of equation 4.1. The graphic symbol, algebraic function and truth table is shown in Figure 4.1. The XOR gate has only two inputs, unlike the other gates we have discussed in experiment 1, it never has more than two inputs. Graphic Symbol
A B
X
Algebraic Function
X=AB’+A’B =AB
Truth Table A
B
X
0
0
0
0
1
1
1
0
1
1
0
1 Figure 4.1 : The exclusive-OR gate. 25
2.2-) The exclusive-NOR Gate : Standard symbol for the exclusive-NOR (XNOR) gate, algebraic function and its truth table are shown in Figure 4.2. Like the XOR gate, the XNOR has only two inputs. The bubble on the output of the XNOR symbol indicates that is output is opposite that of the XOR gate. When the two input logic levels are opposite, the output of the exclusiveNOR gate is logic-0. If both of the input levels are logic-1 or logic-0, the output of the exclusive-NOR gate becomes logic-1. Graphic Symbol
A B
X
Algebraic Function
X=AB+A’B’ =AB
Truth Table A
B
X
0
0
1
0
1
0
1
0
0
1
1
1
Figure 4.2 : The exclusive-NOR gate. 3-) EXPERIMENTAL PROCEDURE : For each part of the experiment, set-up the following circuit which shown in below figures. Make voltage measurements at the points indicated to construct the necessary tables. 3.1-) Set up the following logic circuit.
5 Volt 0
U
+ +5
Y A
B V
X
W
Figure 4.3 : Exclusive-OR generator.
26
Table 4.1. A
B
0
0
0
5
5
0
5
5
U
V
W
X
3.2-) Set up the following logic circuit. 5 Volt -
+ +5
0
X A
B
Figure 4.4 : The exclusive-OR gate Table 4.2. A
B
0
0
0
5
5
0
5
5
X
3.3-) Set up the following logic circuit. 5 Volt 0
+ +5 X A
B
Figure 4.5 : The exclusive-NOR gate
27
Y
Table 4.3. A
B
0
0
0
5
5
0
5
5
X
4-) DISCUSSIONS : 4.1-) Show that the circuits in part 3.1 and 3.2 are equivalent to each other. (Hint : Use DeMorgan’s theorem for the outputs of U and X, and draw a Karnaugh map) 4.2-) Show that (ABC)’=ABC=ABC. 4.3-) How does an exclusive-OR gate differ from an OR gate in its logical operation? 4.4-) Design a logic circuit that to detect when two bits are different from each other. 4.5-) Describe in words the operation of an exclusive-OR gate; and exclusive-NOR gate. 4.6-) Design an exclusive-OR gate and exclusive-NOR gate constructed from all NOR and NAND gates.
28
EP 427 DIGITAL ELECTRONIC EXPERIMENT-5 HALF-ADDER AND HALF-SUBTRACTOR 1-) PURPOSE : To study the half-adder and half-subtractor. 2-) THEORY : 2.1-) Half-Adder : A combination circuit that performs the addition of two bits is called half-adder. The half-adder circuit needs two binary inputs and two binary outputs. The input variables are designated as the augends and addend bits; the output variables produce the sum and carry. The truth table is shown for a half-adder in Table 5.1. Table 5.1. X
Y
C
S
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
The simplified Boolean function for the two outputs can be obtained directly from the truth table. The simplified sum of product expressions are; S=X’Y+XY’
(5.1)
C=XY
(5.2)
2.2-) Half-Subtractor : A half-subtractor is also a combinational circuit that subtracts two bits and produces their difference. The half-subtractor needs two outputs. One output generates the difference (D), and second output, designated as B for borrow. The truth table for the input-output relationships of a half-subtractor is shown in Table 5.2. Table 5.2. X
Y
B
D
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
29
The Boolean functions for the two outputs of the half-subtractor are derived directly from the truth table; D=X’Y+XY’
(5.3)
B=X’Y
(5.4)
3-) EXPERIMENTAL PROCEDURE : For each part of the experiment, set up the circuits shown. Make voltage measurements at the points indicated to construct the necessary tables. Since the half-adder and half-subtractor require the exclusive-OR as part of their logic. 3.1-) Half-Adder
S
5 Volt -
+ +5
0
C Y
X
Figure 5.1 : Half-adder. Table 5.3. X
Y
0
0
0
1
1
0
1
1
C
S
3.2-) Half-Subtractor
D
5 Volt 0
+ +5 B X
Y
Figure 5.2 : Half-subtractor.
30
Table 5.4. X
Y
0
0
0
1
1
0
1
1
B
D
4-) DISCUSSIONS : 4.1-) Write out a truth table for a half-adder and compare with the result of Table 5.3. Discuss. 4.2-) Write out a truth table for a half-subtractor and compare with the result of Table 5.4. Discuss. 4.3-) Implement the four Boolean functions listed using three half-adder circuits. D=ABC E = A’BC + AB’C F = ABC’ + (A’ + B’) C G = ABC
31
EP 427 DIGITAL ELECTRONIC EXPERIMENT-6 BINARY COMPARATORS 1-) PURPOSE : To study the binary comparators. 2-) THEORY : The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares the magnitude of two binary numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A>B, A=B, or A
5 Volt 0
+ +5 F2 B0
A0
F3 Figure 6.1 : One-bit binary comparator. Table 6.1 A
B
0
0
0
1
1
0
1
1
F1
32
F2
F3
3.2-) Set-up the following Figure 6.2 5 Volt 0
+
F
+5 A0
B0
A1
B1
Figure 6.2 : A binary comparator. 4-) DISCUSSIONS : 4.1-) Complete the truth tables of one-bit binary comparators and then obtain simplified Boolean expression of output functions. 4.2-) Determine the type of the comparator of circuit in Figure 6.2 and explain its function. 4.3-) Design a system-called a parallel binary comparator that compares the 4-bit string A (A3A2A1A0) to the 4-bit binary string B (B3B2B1B0). If the strings are exactly equal, provide a high-level output to drive a warning buzzer. 4.4-) Use two 4-bit binary comparators (7485) to compare the magnitudes of two 8-bit numbers. Show the comparators with proper interconnections. 4.5-) The waveforms in below figure are applied to the 2-bit comparator as shown. Sketch the output waveforms. A0 A1 B0 B1 F1
A0
F1 (A
A1
2-Bit Logic Comparator
F2 (A=B)
B0 F3 (A>B)
B1
F2 F3 Figure 6.3 : Block-diagram of 2-bit binary comparator.
33
EP 427 DIGITAL ELECTRONIC EXPERIMENT-7 PARITY GENERATORS AND CHECKERS 1-) PURPOSE : To explain the concept of parity and study the operation principles of basic parity generators and checker. 2-) THEORY : Errors can occur as digital codes are being transferred from one point to another (i.e from one digital device (computer) to another (printer) within a digital system or while codes are being transmitted from one system to another. The errors take the form of undesired changes in the bits that make up the coded information; that is, a 1 can change to a 0, or a 0 to a 1, because of component malfunctions, electrical noise or other disturbances. In most digital systems, the probability that even a single bit error will occur is very small, and the likelihood that more than one will occur is even smaller. Nevertheless, when an error occurs undetected, it can cause serious problems in a digital system. Exclusive-OR and equivalence functions are very useful in systems requiring errordetection and error-correction codes. A parity bit is a scheme for detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message, including the parity bit, is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond to the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator; the circuit that checks the parity in the receiver is called a parity checker. Parity systems are defined as either odd parity or even parity. The parity system adds an extra bit to the digital information being transmitted. A 2-bit system will require a third bit, an 3-bit system will require a forth bit, and so on. In an odd-parity system, the parity bit that is added must make the sum of all n-bits odd. In an even-parity system, the parity bit makes the sum of all bits even. The parity generator is the circuit that creates the parity bit. On the receiving end, a parity checker determines if the n-bits result is of the right parity. The type of system (odd 34
or even) must be agreed on before hand so that the parity checker knows what to look for (this is called protocol). Also, the parity bit can be placed next to the MSB or LSB as long as the device on the receiving end knows which bit is parity and which bits are data. For example, during the transmission of BCD number 9 (1001) in an odd-parity system, the parity generator puts a 1 on the parity-bit line to make the sum of all bits odd (1+0+0+1+1=3). The parity checker at the receiving end checks to see that the transferred all-bits are odd, it assumes that no error then BCD information is valid. Otherwise, an error indicator indicates an error. The error indicator is actually a signal that initiates a retransmission of the original signal or produces an error message on a computer display. A block diagram of a parity generator and checker system is shown in Figure 7.1.
B C D
B C D
Error Indicator
Parity Bit Parity Checker
Parity Generator
Receiving Device
Transmitting Device
Figure 7.1 : A parity generator/checker system. 3-) EXPERIMENTAL PROCEDURE : 3.1-) Parity Generator : Set-up the following circuit.
5 Volt 0
+ +5 P X
Y
Z
Figure 7.2 : 3-bit parity generator
35
Three-bit message
Parity bit generated
X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3.2-) Parity Checker : Set up the following circuit.
P
5 Volt 0
+
F
+5 X
Z
Y
P
Figure 7.3 : A 3-bits parity checker. Parity error generated
Four-bits received X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 36
P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
F
4-) DISCUSSIONS : 4.1-) Determine the type of the system in part 3.1 and .2. 4.2-) Write the Boolean expression of P and F in the simplest form. 4.3-) Add a parity bit next to the LSB of the following hexadecimal codes to form even parity: 0011, 1000, 1101, 0111, 1010, 0001, 0000, 0100. 4.4-) Suppose that a computer and printer system uses 4-bit odd parity generator and checker, a-) Tabulate the truth table of parity generator. b-) Write and simplify the output function of parity generator using any simplification technique which you learned. c-) Implement the logic circuits of parity generator and checker in the simplest form. d-) Discuss in which conditions parity checker gives error. 4.5-) Design a logic circuit that detects the errors occur when a binary information transferring from a computer to a printer. Restrict that the long of binary information are four bits. 4.6-) One popular 9-bit parity generator/checker is the 74280 TTL IC or 74HC280 CMOS IC (see Figure 7.4). Using 74280s, design a complete parity generator/checking system. It is to be used in an 8-bit, even parity computer configuration. 8
I0 I1 I2 I3 I4 I5 I6 I7 I8
Function Table Number of HIGH data Sum Output inputs (I - I ) Even Odd
9 10 11 12 13 1 2 4
74280 TTL IC
E O HIGH LOW LOW HIGH
E 5 VCC= Pin-14 GND=Pin-7
o 6
4.7-) Which output of the 74280 parity generator is used as the parity bit in an odd system? A0
A0
A1
A1 Parity Generator A2
A2
A3 A3 Figure 7.4 : Input waveforms and block diagram of parity generator. 37
P
EP 427 DIGITAL ELECTRONIC EXPERIMENT-8 FULL-ADDER AND FULL-SUBTRACTOR 1-) PURPOSE : To study methods of generating circuits that perform the arithmetic operations of full addition and full-subtraction. 2-) THEORY : 2.1-) Full-Adders : A full-adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables, denoted by X and Y represent the two significant bits to be added. The third input, Ci represents the carry from previous lower significant position. The outputs are designated by symbols S for sum and Co for carry. The binary variable S gives the value of the least significant bit of the sum. The binary variable Co gives the output carry. When all input bits are 0’s, the output is 0. The S output bits equal to 1 when only input is equal to 1 or when all three inputs are equal to 1. The Co output has a carry of 1 if two or three inputs are equal to 1. The input-output logical relationship of the full-adder circuit may be expressed in two Boolean functions, one for each output variable. The truth table of the full-adder is as follows : X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
Ci Co 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 1
S 0 1 1 0 1 0 0 1
We can simplify the representation of a full-adder by just drawing a box with the input and output lines, as shown in Figure 8.1a. When drawing multibit adders, a block diagram is used to represent the addition in each column, as shown in Figure 8.1b.
38
X Y Ci
X3 Y3 Ci FA
FA
C0
C0
3
X2 Y2 Ci
X1 Y1 Ci
X0 Y0 Ci
FA
FA
FA
C0
2
C0
1
C0
0
(b)
(a)
Figure 8.1 : Block diagrams of (a) full-adder; (b) 4-bit binary adder. Medium-scale-integration (MSI) ICs are available with four full-adders in a single package. Table 8.1 lists the most popular adder ICs. Each adder in table contains four fulladders, and all are functionally equivalent; however, their pin layouts differ. They each will add two 4-bit binary words plus one incoming carry. The binary sum appears on the sum outputs (1 to 4) and the outgoing carry. Figure 8.2 shows the functional diagram and the logic symbol for the 7483. Table 8.1 : MSI Adder IC’s Device 7483 74LS83A 74LS283 74HC283 4008
Family TTL TTL TTL CMOS CMOS
Description 4-Bit binary full adder, fast carry 4-Bit binary full adder, fast carry 4-Bit binary full adder, fast carry 4-Bit binary full adder, fast carry 4-Bit binary full adder, fast carry
2.2-) Full-Subtractors : A full-subtractor is also a combinational circuit that performs a subtraction between two bits, taking into account that a 1 may have been borrowed by a lower significant stage. This circuit has three inputs and two outputs. Three inputs X, Y and Bi denote the minuend, D and Bo represent the difference and output borrow, respectively. The simplified Boolean functions for the two outputs of the full-subtractor are derived from the maps. The logic function for output D in the full-subtractor is exactly the same as S in the full-adder. Moreover, the output Bo resembles the function for Co in the full-adder, except that the input variable X is complemented. Because of these similarities, it is possible to convert a full-adder into a full-subtractor by merely complementing input X prior to its application to the gates that from the carry output.
39
X1
Y1
X2
Y3
X3
Y2
X4
Y4
Fast-lookahead carry
Cin
Ci
C0
C0
Ci
C0
Ci
FA1
FA2
FA3
1
2
3 (a) 10 11
1
Cout
7483
Cin
Cout
16
A1 B1 A2 B2 A3 B3 A4 B4 13
C0
4
3 4
8 7
Ci FA4
1
2
3
4
9
6
2
15
Vcc=Pin-5 GND=Pin-12 14
(b) Figure 8.2 : The 7483 4-bit full-adder :(a) functional diagram; (b) logic symbol.
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
40
B i Bo D 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1
3-) EXPERIMENTAL PROCEDURE : For each part, set up the circuit shown and make voltage measurements at the points indicated to complete the table. 3.1-) Full-adder :
5 Volt -
S + +5
0
X
Y
Ci
Co
Figure 8.3 : A full-adder circuit constructed with two half-adders and one OR gate. X
Y
Ci Co
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
S
3.2-) Full-Subtractor :
5 Volt 0
D + +5 X
Y
Bi
Bo
Figure 8.4 : A full-subtractor circuit constructed with two half-subtractors and one OR gate and one INVERTER.
41
X
Y
Bi Bo D
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
4-) DISCUSSIONS : 4.1-) Compare the full-adder data of part 3.1 and full-subtractor data of part 3.2 with a truth table for a full-adder and full-subtractor, respectively. 4.2-) Implement a full-adder circuit using only AND, OR and INVERTER gates. 4.3-) Does output in Figure 8.5 give the result of output carry of a full-adder circuit. Explain its Boolean expression equivalence with Figure 8.1.
Co
5 Volt 0
+ +5 X
Y
Ci Figure 8.5
4.4-) The Boolean expression for the borrow out B0 of a full-subtractor is given by B0=X’YBi + X’YBi + XYBi + X’YBi’ by means of a Karnaugh map, this can be reduced to XY + YBi + XBi. Using the 7400 and 7410 ICs, draw a logic diagram showing pin connections for this Bo reduced.
42
4.5-) Show that carry four (C4) in a full-adder circuit (for 4-bits two-numbers A3A2A1A0 and B3B2B1B0) can also be given in the form of C4=G3 + F3G2 + F3F2G1 + F3F2F1G0 + F3F2F1F0C0 4.5-) Show how two 74LS83A adders can be connected to form an 8-bit adder. 4.6-) Implement the 12-bit parallel adder with 74LS283 adders. 4.7-) In a full-adder circuit, the initial carry (Cin) is always setted to zero (no carry). Explain how could you implement initial carry with zero? 4.8-) The input waveforms in Figure 8.6 are applied to a 2-bit adder. Determine the waveforms for the sum and the output carry in relation to the inputs by constructing a timing diagram. A1 A2 B1 B2 Cin Figure 8.6.
43
EP 427 DIGITAL ELECTRONIC EXPERIMENT-9 CODE CONVERTERS 1-) PURPOSE : To examine some methods or using combinational logic circuits to convert from one code to another and generating their logic circuits. 2-) THEORY : The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems or by a computer. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational circuit performs this transformation by means of logic gates. The design procedure of code converters will be illustrated by means of a specific example of conversion from the BCD to the excess-3 code. The most famous example of code conversion is between BCD and other base. Because, the BCD is very important code for visual display communication; i.e., between a computer and human beings. But BCD is very difficult to deal with arithmetically. Algorithms, or procedures, have been developed for the conversion of BCD to binary by computer programs (software) so that the computer will be able to perform all arithmetic operations in binary. Calculators and other devices with numeric displays use another form of code conversion involving BCD-to-seven-segment conversion. The term seven segment come from the fact that these displays utilize seven different illuminating segments to makeup each of the 10 possible numeric digits. The Gray code is another useful code used in digital systems. It is used primarily for indicating the angular position of a shaft on rotating machinery, such as automated lathes and drill presses. The determination of the
44
Gray code equivalents and the conversion between Gray code and binary code are done very simple with exclusive-OR gates, as shown in Figure 9.1. B0
G0
B1
G0
(LSB)
G1 Gray code output G2
G1
Binary input
Gray code output
B2
G2
B3
(MSB)
G3
B0 (LSB)
B1 Binary input B2 B3 (MSB)
G3 (b)
(a)
Figure 9.1 : (a) 4-bit binary-to-gray conversion logic; (b) 4-bit gray-to-binary conversion logic. The logic symbol in Figure 9.2 shows eight active-HIGH binary outputs. Y1 to Y5 are outputs for regulate BCD-to-binary conversion. Y6 to Y8 are used for a special BCD code called nine’s complement and ten’s complement. Inputs 13 12 15 14 E
G
D
C
11 10 B
A Vcc=Pin-16 GND=Pin-8
74184 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 1
2
3
4 5 Outputs
6
7
9
Figure 9.2 : Logic Symbol for the 74184 BCD-to-binary converter.
3-) EXPERIMENTAL PROCEDURE : 3.1-) Set up the following circuit and complete its truth table.
45
F3 5 Volt -
+
F2 +5
0
A
C
B
D
F1 Fo
Figure 9.3 : A converter from BCD to 9’s complement. Table 9.1 A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
F3 F2 F1 F0
3.2-) Set up the following Figure and complete its truth table. F3
F2 5 Volt 0
+
F1 +5 A
B
C
D Fo
Figure 9.4 : A code converter.
46
A 0 0 0 0 0 1 1 1 1 1
B 0 1 1 1 1 0 0 0 0 1
C 0 1 1 0 0 1 1 0 0 1
D 0 1 0 1 0 1 0 1 0 1
F3 F2 F1 F0
4-) DISCUSSIONS : 4.1-) Find and simplify the Boolean expression of output function in Figure 9.3 using Boolean function simplification techniques. 4.2-) Find the Boolean expression of output functions in Figure 9.4 in their simplest form and then discuss the type of the code converter. 4.3-) Implement 8-bit binary-to-Gray code and 5-bit Gray-to-binary code converter using only exclusive-OR gates. 4.4-) Using 74184 ICs, implement a logic circuit to convert a 3-bit BCD number to binary. 4.5-) Design a combinational logic circuit that converts a decimal digit from 8421 code to 2214 code using a decoder and if necessary the other basic logic gates. 4.6-) Design of a combinational logical device that converts a decimal digit from 6,3,2,-1 BCD code to 8,4,2,1 BCD code. 4.7-) Design a combinational logic circuit that converts a decimal equivalent from 6461 code to 8421 code using minimum number of necessary logic gates. 4.8-) Design a combinational logic circuit either in block diagram or not that converts a decimal digit from its decimal number system to binary number system when you press the key of decimal digit.
47
EP 427 DIGITAL ELECTRONIC EXPERIMENT-10 DECODERS AND ENCODERS 1-) PURPOSE : To study the function of a decoder and encoder and design the internal circuitry for encoding and decoding. 2-) THEORY : 2.1-) Decoder : Decoding is the process of converting some code (such as binary, BCD) into a singular active output representing its numeric value. Therefore, a decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n-bit decoded information has unused or don’t-care combinations, the decoder output will have less than 2n outputs. In order to decode all possible combinations of 2-bits, 4 decoding gates are required (22=4). This type of decoder is commonly called a 2-line-to-4-line decoder because there are two inputs and four outputs. Therefore, the decoders are called as n-to-m line decoders where m2n. To design a decoder, it is useful first to make a truth table of all possible input/output combinations. Before design is made, we must decide if we want an active-HIGH-level output or an active-LOW-level output to indicate the value selected. For example, the active-HIGH truth table shows that for an input 10 (2), output 2 is HIGH, and all other outputs are LOW. The active-LOW truth table is just the opposite (output 2 is LOW, all other outputs are HIGH). A list of the four binary codes and their corresponding decoding function is given in Table 10.1. In here, each output representing one of the minterms of the 2-input variables. The two inverters provide the complement of the inputs, and each one of the four eight AND gates generate one of the minterms as shown in Figure 10.1. Table 10.1 : Decoding functions and truth table of a 2x4 decoder. (a) Active-HIGH Outputs Binary Decoding Inputs Function
Outputs
A
B
D0 D1 D2 D3
0
0
A’B’
1
0
0
0
0
1
A’B
0
1
0
0
1
0
AB’
0
0
1
0
1
1
AB
0
0
0
1
48
(b) Active-LOW Outputs Binary Decoding Inputs Function
Outputs
A
B
D0 D1 D2 D3
0
0
A’B’
0
1
1
1
0
1
A’B
1
0
1
1
1
0
AB’
1
1
0
1
1
1
AB
1
1
1
0
D0
D1 5 Volt 0
D2
+ +5 A
D3
B
Figure 10.1 : A 2-to-4 line docoder. Integrated-circuit decoder chips provide basic decoding as well as several other useful functions. Rather than designing decoders using combinational logic, it is much more important to be able to use a data book to find the decoder that you need and to determine the proper pin connections and operating procedure to perform a specific decoding task. Table 10.2 lists some of the more popular TTL decoder ICs. Table 10.2 : Decoder ICs. Device Number Function 74138 1-of-8 octal decoder (3-to-8-line decoder) 7442 1-of-10 BCD decoder (4-to-10-line decoder) 74154 1-of-16 hex decoder (4-to-16-line decoder) 7447 BCD-to-seven-segment decoder The 74138 is an octal decoder capable of decoding the eight possible octal codes into eight separate active-LOW outputs, just like our combinational logic design. It also 49
has three enable inputs for additional flexibility. The 7442 is a BCD-to-decimal decoder. It has four pins for the BCD input bits (000 to 1001) and 10 active-LOW outputs for the decoded decimal numbers. Decoders are used in many types of applications, i.e. in computers for input/output selection. 2.1-) Encoder : Encoding is used to generate a coded output (such as BCD or binary) from a singular active numeric input line. Therefore, an encoder is a combinational logic circuit that essentially performs a reverse decoder function. An encoder accepts an active level on one of its inputs representing a digit, such as a decimal or octal digit, and converts it to a coded output, such as BCD. So, an encoder has 2n (or less) input lines and n output lines. The design of encoders using combinational logic can be done by reviewing the truth table (see Table 10.3) for the operation to determine the relationship each output has with the inputs. For example, by studying Table 10.3 for a decimal-to-BCD encoder, we can see that A output (20) is HIGH for all odd decimal input numbers (1, 3, 5, 7, and 9). The B output (21) is HİGH for decimal inputs 2, 3, 6, and 7. The C output (22) is HIGH for decimal inputs 4, 5, 6, and 7, and the D output (23) is HIGH for decimal inputs 8 and 9. The design of other encoders uses same procedures, but of course many of them are available in ICs form. For example, the 74174 decimal-to BCD, and the 74184 octal-tobinary. The 74147 is a priority encoder, which means that if more than one decimal number is input, the highest numeric input has priority and will be encoded to the output. Table 10.3 : Decimal-to-BCD Encoder Truth Table. Inputs Decimal Input D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 5 0 0 0 0 0 1 0 0 0 0 6 0 0 0 0 0 0 1 0 0 0 7 0 0 0 0 0 0 0 1 0 0 8 0 0 0 0 0 0 0 0 1 0 9 0 0 0 0 0 0 0 0 0 1
50
BCD Output D C B A 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1
1 A
2 3
B
4 5 6 7
C
8 D 9 Figure 10.2 : Basic decimal-to BCD encoder. 3-) EXPERIMENTAL PROCEDURE : 3.1-) Decoder : Set up the following circuit and sketch the output waveforms.
A0
1
16
Vcc
A1
2
15
D0
A2
3
14
D1
13
D2
5
12
D3
E3 6
11
D4
D7
7
10
D5
GND 8
9
D6
E1’ 4 E2’ +5 V
74138
Figure 10.3 : The 74138 pin-connections.
51
+5 V
E1’ A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 3.2-) Encoder : Set up the following circuit and sketch the output waveforms. +5 V
I4’
1
16
Vcc
I5’
2
15
EO’
I6’
3
14
GS’
I7’
4
13
I3’
EI’
5
12
I2’
A2’ 6
11
I1’
A1’ 7
10
I0’
GND 8
9
A0’
74148
Figure 10.4 : The 74148 pin-connections. 52
+5 V
EI’ I6’ I7’ A0’ A1’ A2’ EO’ GS’
4-) DISCUSSIONS : 4.1-) Would you select a decoder/driver with active-HIGH or active-LOW outputs to drive a common-cathode 7-segment LED display? 4.2-) BCD numbers are applied sequentially to the BCD-to-decimal decoder in below Figure. Draw a timing diagram, showing each output in the proper relationship with the others and with the inputs. BCD/DEC
0 1 2
A0 A1
A0
1
3
A1
2
4
8
6 7
A2 A3
A2
7442A 4 5
8
A3
9 4.3-) How does an encoder differ from a decoder? 53
4.4-) If more than one input to a priority encoder is active, which input will be encoded? 4.5-) What are the five outputs of the 74148? Are they active-LOW or active-HIGH? 4.6-) Design a 4-line to 2-line priority encoder. Include an output E to indicate that at least one input is a 1. 4.7-) Construct a 5 x 32 decoder with four 3 x 8 decoder / demultiplexers with an enable input and a 2 x 4 decoder. Use block diagrams of all necessary circuits. 4.8-) Draw the logic diagram of a 2 x 4 decoder using only minimum number of NOR gates. 4.9-) Implement a combinational logic circuit that converts a decimal equivalent from 6461 code to 8421 code using a decoder which is constructed with NAND gates and minimum number of necessary basic logic gates. 4.10-) A combinational circuit is specified by the following three Boolean functions; F1=x’y’ + xz’, F2 = y’ + x’z, F3 = x’y + yz. Implement the circuit with a decoder which constructed with NAND gates and minimum number of external NAND gates. 4.11-) Design a combinational logic circuit that is converted a decimal digit from 8421 code to 2214 code using a decoder and if necessary the other basic logic gates. 4.12-) Design a logic circuit of a keyboard that converts decimal digits (0,1,2,…,9) to its binary number system when you press the keys on the keyboard. 4.13-) Consider the following functions f1(x,y,z)=(0,1,2,4,5,7) f2(x,y,z)=(0,2,3,4,5,7) Implement the both functions using a decoder and if necessary the other basic logic gates.
54
EP 427 DIGITAL ELECTRONIC EXPERIMENT-11 MULTIPLEXERS AND DEMULTIPLEXERS 1-) PURPOSE : To explain the basic operation of a multiplexer and demultiplexer and their use as a logic function generator. 2-) THEORY : 2.1-) Multiplexers (Data Selectors) : Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer (MUX) is a device (combinational circuit) that selects binary information from one of many input lines and directs it to a single output line. Because data can be selected from any one of the input lines, a multiplexer is also known as a data selector. The multiplexer has two or more digital input line signals connected to its input. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines. A logic symbol, logic diagram and data select input codes (function table) are shown in Figure 11.1 for a 4-line to 1-line multiplexer. Each of the four input lines D0 and D3 is applied to one input of an AND gate. The data select control inputs (S1 and S0) are responsible for determining which data input is selected to be transmitted to the dataoutput line (Y). The S1 and S0 inputs will be a binary code that corresponds to the datainput line that you want to select. If S1=0, S0=0, then D0 is selected, if S1=0, S0=1, then D1 is selected, and so on. We can therefore, derive a logic expression for the output in terms of the data input and the select inputs. The total expression for the data output is Y=D0S1’S0’ + D1S1’S0 + D2S1S0’ + D3S1S0 The AND gates and inverters in the multiplexer resemble a decoder circuit and, indeed, they decode the input selection lines. In general, a 2n-to-1 line multiplexer is constructed from an n-to-2n decoder by adding to it 2n input lines, one to each AND gate. The outputs of the AND gates are applied to a single OR gate to provide the 1-line output. As in decoders, multiplexer ICs may have an enable input to control the operation of the unit. When the enable input is in a given binary state, the outputs are disabled, and when it is in the other state (the enable state), the circuit functions as a normal multiplexer. 2-, 4-,
55
8-, and 16-input multiplexers are readily available in MSI packages. Table 11.1 lists some popular TTL and CMOS multiplexers. Data Select Control Data Input Inputs Selected S1 S0 0 0 D0 0 1 D1 1 0 D2 1 1 D3
D0 Data D1 Inputs D 2
4x1 MUX
Y Output
D3
S1 S0 Data selection lines
(a)
(b) D0
D1 Y
D2 D3
S1
S0 (c)
Figure 11.1 : (a) Data selection, (b) Block diagram, and (c) logic diagram for a 4x1 multiplexer. The 74157 consists of four separate 2-input multiplexers. Each of four multiplexers shares a common data-select line and a common Enable, as shown in Figure 11.2. Because there are only two inputs to be selected in each multiplexer, a single data-select input is
56
sufficient. As you can see in the logic diagram, the data-select inputs is ANDed with the B input of each 2-input multiplexer, and the component of data-select is ANDed with each A Table 11.1 : TTL and CMOS Multiplexers Function Quad 2-input
Dual 8-input
8-input 16-input
Device 74157 74HC157 4019 74153 74HC153 4539 74151 74HC151 4512 74150
Logic Family TTL H-CMOS CMOS TTL H-CMOS CMOS TTL H-CMOS CMOS TTL
input. A LOW on the Enable input allows the selected input data pass through to the output. A HIGH on the Enable input prevents data from going through to the output, that is, it disables the multiplexers. The multiplexer is a very useful MSI function and has a multitude of applications. It is used for connecting two or more sources to a single destination among computer units, and it is useful for constructing a common bus system. A useful application of the data selector/multiplexer is in the generation of combinational logic functions in sum-of products form. When used in this way, the device can replace discrete gates, can often greatly reduce the number of ICs, and can make design changes much easier. Although multiplexers and decoders may be used in the implementation of combinational circuits, it must be realized that decoders are mostly used for decoding binary information and multiplexers are mostly used to form a selected path between multiple sources and a single destination. 2.2-) Demultiplexers : Demultiplexing is the opposite procedure from multiplexing. It takes data from one line and distributes them to a given number of output lines. For this reason, we can think of a demultiplexer (DEMUX) is also known as a data distributor. As you will learn, decoders can also be used as decoders/demultiplexers. Figure 11.3 shows a 1-line-to-4-line demultiplexer circuit. The data-input line goes to all of the AND gates. The
57
two data-select lines enable only one gate at a time, and the data appearing on the datainput line will pass through the selected gate to the associated data-output line. Decoder/demultiplexer circuits can be connected together to form a larger circuit. For example two 3x8 decoders with enable inputs connected to form a 4x16 decoder. Integrated-circuit demultiplexers come in several configurations of inputs/outputs. Two of them are the 74139 dual 4-line demultiplexer. A0 Y0
A1 A2
Y1
A3
Function Table E S Y 1 X all 0's 0 0 select A 0 1 select B (b)
B0 Y2
B1 B2
Y3
B3
S (select) E (enable) Figure 11.2 :
(a) (a) Logic diagram and (b) function table for a quadruple 2-to-1 line multiplexer.
58
E A B D0 1 X X 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1
D1 1 1 0 1 1
D2 1 1 1 0 1
D3
D0
1 1 1 1 0
E Input
1x4 DEMUX
D1 D2 D3
B A Select
(a)
(b) D0
D1 D2 A D3
B E (c)
Figure 11.3 : (a) Data selection, (b) Block diagram, and (c) logic diagram for a 1x4 demultiplexer. 3-) EXPERIMENTAL PROCEDURE : 3.1-) Multiplexer : Set up the following circuit and sketch the output waveform. S0
E’ 7 S0 11
S1 S2
MUX
S1 10 S2 9
E’
D0 4 D1 3
D0 D1 D2
D2 2 D3 1
D3 D4
D4 15 D5 14
D5
D6 13 D 12
D6 D7
7
59
5
74151A
Y
6 Y’
3.2-) Demultiplexer : Set up the following circuit and sketch the output waveforms. S
I D0
S S
D1
D S0
D
D2
D3
D S1 D
4-) DISCUSSIONS : 4.1-) Why is a multiplexer and demultiplexer sometimes called a data selector and data distributor, respectively? 4.2-) Design the logic circuit of a 4x1 multiplexer using only NAND gates. 4.3-) Design the logic circuit of a 1x4 demultiplexer using only AND gates. 4.4-) Implement a full-subtractor logic circuit with multiplexers. 4.5-) The data-input and data-select waveforms in below figure are applied to the multiplexer in Figure 11.1. Determine the output waveform in relation to the inputs. Do D1 D2 D3 S0 S1 Y 60
4.6-) Sketch the output waveforms at Y for the 7451 shown in below figure
+5 V
I3 1
16 Vcc
I2 2
15 I4
I1 3
14 I5
I0 4
13 I6
+5 V
0V
74151 Y 5
12 I7
Y’ 6
11 S0
E’ 7
10 S1
GND
9
8
S2
S0 S1 S2 Y 4.7-) What is the function of the S0, S1, and S2 pins on the 7451 multiplexer? 4.8-) Use a multiplexer to implement the function X=A’B’C’D + AB’C’D + ABC’D’ + A’BC + A’B’C 4.9-) Implement the logic function Y= (1, 2,5,6,7,8, 10 ,12,13,15)by using a 74151A 8input data selector/multiplexer. Compare this method with a discrete logic gate implementation. 4.10-) Using two 74151s, design a 16-line multiplexer controlled by four data select control inputs. 4.11-) What is the function of the A0, A1, A2, and A3 pins on the 74154 demultiplexer? 4.12-) Design a circuit that will output a LOW whenever a month has 31 days. The month number (1 to 12) is input as a 4-bit binary number (January = 0001, and so on). Use a 74150. 61
EP 427 DIGITAL ELECTRONIC EXPERIMENT-12 S-R FLIP-FLOPS 1-) PURPOSE : To study the characteristics and operation principles of various type bistables. 2-) THEORY : In this example, we cover bistable, monostable, and astable logic devices called multivibrator. Two categories of bistable devices are the latch and the flip-flop. Bistable devices have two stable states, called SET and RESET; they can retain either of these states indefinitely, making them useful as storage devices. The latch is a type of bistable storage device that is normally placed in a category separate from that of flip-flops. Latches are basically similar to flip-flops because they are bistable devices that can reside in either of two states by virtue of a feedback arrangement, in which the outputs are connected back to the opposite inputs. The basic difference between latches and flip-flops is the way in which they are changed from one state to the other. This type of digital circuitry is called sequential logic, because it is controlled by and is used for controlling other circuitry in a specific sequence dictated by a control clock or enable/disable control signals. The flip-flop is a basic building for counters, registers, and other sequential control logic. 2.1-) S-R Latches (Flip-Flops) : A latch is a bistable multivibrator and it is a data storage circuit that can be constructed using the basic gates. An active-HIGH input S-R (SETRESET) flip-flops is formed using a cross-coupled two NOR gates an active-LOW input S’-R’ flip-flop is formed using a cross-coupled two NAND gates, as shown in Figure 12.1a and b, respectively. Notice that the output of each gate is connected to an input of the opposite gate. This produces the regenerative feedback that is characteristic of all multivibrators. S
Q
S’
Q
Q’ Q’ R R’ Figure 12.1: (a) Active-HIGH input S-R flip-flop; (b) Active-LOW input S’-R’ flip-flop. 62
To understand the operation principles of the flip-flop, let’s start our analysis by placing a 1 (HIGH) on the SET and a 0 (LOW) on the Reset (Figure 12.1a) This is defined as the Set condition and should make the Q output 1 and Q’ output 0. A HIGH on the Set will make the output of the upper NOR equal 0 (Q’=0) and 0 is fed down to the lower NOR, which together with a LOW on the Reset input will cause the lower NOR’s output to equal a 1 (Q=1). Now, when the 1 is removed from the Set input, the flip-flop should remember that it is Set (that is, Q=1, Q’=0). So with Set=0, Reset=0, and Q=1 from previous being set, let’s continue our analysis. The upper NOR has a 0-1 at its inputs, making Q’=0, while the lower NOR has a 0-0 at its inputs, keeping Q=1. Great the flipflop remained Set even after the Set input was returned to 0 (called the Hold condition). Now we should be able to Reset the flip-flop by making S=0, R=1. With R=1, the lower NOR will output a 0 (Q=0), placing a 0-0 on the upper NOR, making its output 1 (Q’=1); thus the flip-flop “flipped” to its Reset state. The only other input condition is when both S and R inputs are HIGH. In this case, both NORs will put out a LOW, making Q and Q’ equal 0, which is a condition that is not used. Also when you return to the Hold condition from S=1, R=1 you will get unpredictable results unless you know which input returned LOW last. Table 12.1 summarizes the logic operation in truth table form. Table 12.1 : Truth (Function) Table for (a) Figure 12.1a and (b) Figure 12.1b. S 0 1 0 1
R Q Q' Comments 0 Q Q' Hold Condition (no change) 0 1 0 Flip-Flop Set 1 0 1 Flip-Flop Reset 1 0 0 Not used
S 0 1 0 1
R Q Q' Comments 0 Q Q' Hold Condition (no change) 0 1 0 Flip-Flop Set 1 0 1 Flip-Flop Reset 1 1 1 Not used
The symbols used for an S-R flip-flop are shown in Figure 12.2. The symbols show that both true and complemented Q outputs are available. The second symbol is technically more accurate, but the first symbol is found most often is manufacturers data and through this experimental manual book. S
Q
S
Q
R
Q’
R
Q
Figure 12.2 :Symbols for an S-R flip-flop.
63
Q’
2.2-) Gated S-R Flip-Flop : Simple gate circuits, combinational logic, and transparent S-R flip-flops are called asynchronous (not synchronous) because the output responds immediately to input changes. Synchronous circuits operate sequentially, in step, with control input. To make an S-R flip-flop synchronous, we add a gated input to enable and disable the S and R inputs. Figure 12.3 shows the connections that make the cross-NOR SR flip-flop into a gated S-R flip-flop. Set
Sx Q’
Gate Enable Q Rx
Reset
Figure 12.3 : Gated S-R flip-flop. The Sx and Rx lines in Figure 12.3 are the original Set and Reset inputs. With the addition of the AND gates, however, the Sx and Rx lines will be kept LOW-LOW (HoldCondition) as long as the Gate Enable is LOW. The flip-flop will operate normally while the Gate Enable is HIGH. The logic symbol and function chart (truth table) are illustrated in Figure 12.4. G 0 0 0 0 1 1 1 1
S R 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
Q Q Q Q Q Q 0 1 0
Q' Q' Q' Q' Q' Q' 1 0 0
Comments Hold Condition Hold Condition Gate inputs Hold Condition disabled Hold Condition Hold Condition Gate inputs enabled Reset Set Unused
Q
S G
Q’
R (b)
(a) Figure 12.4 : Function table and logic symbol for the gated S-R flip-flop. 3-1 ) EXPERIMENTAL PROCEDURE : 3.1-) Set up the following circuit and applying below input waveforms, sketch the waveform of output Q and Q’. 64
+5V
S
14
Q 13
12
11
10
9
8
5
6
7
7402
1
2
3
4
Q’ R
S R Q Q’ 3.2-) Make the necessary connections to the 7408 quad AND and 7402 quad NOR gate ICs to form the gated S-R flip-flop and then applying the below waveforms, sketch the output waveforms of Q and Q’. G S R Q Q'
65
4-) DISCUSSIONS : 4.1-) What levels must be placed on S and R to Set and S-R flip-flop? 4.2-) What effects do S=0 and R=0 have on the output level at Q? 4.3-) Explain why the S-R flip-flop is called asynchrous and the gated S-R flip-flop is called synchronous. 4.4-) Sketch the Q output waveform for a gated S-R flip-flop, given the inputs at S, R, and G shown in below Figure. G
S R
Q
Q'
66
REFERENCES 1. William Kleitz, “Digital Electronics”, Prentice Hall, (1996). 2. Thmos L.Floyd, “Digital Fundamentals”, Prentice Hall, (1997). 3. M.Morris Mano, “Digital Design”, Prentice Hall, (1984). 4. Morris E.Levine, “Digital Theory and Experimentation Integrated Circuits”. Prentice Hall, (1982). 5. John F.Wakerly, “Digital Design”, (2000).
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APPENDIX A GLOSSARY OF LOGIN AND INTEGRATED-CIRCUIT TERMINILOGY1 Access Time : Active-LOW : Adder : Adjacent Cell : Address : Analog :
Analog-to-digital (A/D)Conversion: Analog-to-digital converter (ADC): AND Gate : AND-ORINVERT Gate (AOI) : ASCII Code :
Astable Multivibrator: Asynchronous: Asynchronous Input : Asynchronous Operation : BCD : Bidirectional : Binary : Binary String : Binary Word : Bistable : Bit : Bit time : Boolean Equation : Boolean Reduction : Borrow : Byte : Cary generation: 1
Time required to obtain stored in a memory. An output of a logic circuit that is LOW when activated or an input that needs to be LOW to be activated. Circuitry that performs the operation of adding two numbers. Cells within a Karnaugh map that border each other on one side or the top or bottom of the cell. A unique binary value that is used to distinguish the location of individual memory bytes or peripheral devices. A system that deals with continuously varying physical quantities such as voltage, temperature, pressure, or velocity. Most quantities in nature occur in analog, yielding an infinite number of different levels. The process of converting an analog signal to digital form. A device used to convert an analog signal to a sequence of digital codes. A logic circuit that produces a HIGH output only when all of the inputs are HIGH. An integrated circuit containing combinational logic consisting of several AND gates feeding into An OR gate and then an inverter. It is used to implement logic equations that are in the SOP format. American Standard Code for Information Interchange. ASCII is a 7-bit code used in digital systems to represent all letters, symbols, and numbers to be input or output to the outside world. An oscillator having two outputs. The output levels are complementary, when one output is high, the other is low. (Not synchronous) A condition in which the output of a device will switch states instantaneously as the inputs change without regard to an input clock signal. Inputs to a flip-flop which affect the output of the flip-flop independent of all other inputs. An operation that proceeds independently within a system independent of any clock signals. Binary-coded decimal. A 4-bit code used to represent the 10 decimal digits 0 to 9. A device capable of functioning in either of two directions, thus being able to reverse its input/output functions. The base 2 numbering system. Binary numbers are made up of 1’a and 0’s, each position being equal to a different power of (2 3, 22, 21, 20, and so on). Two or more binary bits used collectively to form a meaningful binary representation. A group, or string, of binary bits. In a 4-bit system a word is 4 bits in a box format. A circuit having two stable states. A single binary digit. The binary number 1101 is a 4-bit number. The interval of time occupied by a single bit in a sequence of bits; the period of the clock. An algebraic expression that illustrates the functional operation of a logic gate or combination of logic gates. An algebraic technique that follows specific rules to convert a Boolean equation into a simpler form. When subtracting numbers, if the number being subtracted from is not large enough, it must “borrow”, or take an amount from, the next-more-significant digit. A group of eight bits. The process of producing an output carry in a full-adder when both input bits are 1s.
This section is completely taken from Digital Fundamentals by Thmos L.Floyd.
68
Carry propagation : Carry-In : Carry-Out : Cell : Chip : Clear : Clock : Code : Code Converter : Comparator : Combinational Logic : Comparator : Complement : Controlled Inverter : Counter : CPU : Data : De Morgan’s Theorem : Decade Counter: Decimal : Decoder : Demultiplexer : D Flip-Flop : Digit : Digital :
Digital-to-analogconverter (DAC): Disable : Disabled : Don’t Care :
Dual Symbols: Edge Triggered : Edge-triggered flip-flop :
The process of rippling an input carry an input carry to become the output carry in a full-adder when either or both of the input bits are 1s and the input carry is a 1. A amount from a less-significant-digit addition that is applied to the current addition. When adding numbers, when the sum is greater than the amount allowed in that position, part of the sum must be applied to the next-more-significant position. Each box within a Karnaugh map. Each cell corresponds to a particular combination of input variable logic levels. The term given to an integrated circuit. It comes from the fact that each integrated circuit comes from a single chip of silicon crystal. Set a binary to the 0 state. A device used to produce a periodic digital signal that repeatedly switches from LOW to HIGH and back at a predetermined rate. A set of bits arranged in a unique pattern and used to represent such information as numbers, letters, and other symbols. A device that converts one type of binary representation to another, such as BCD to binary or binary to Gray code. A device used to compare the magnitude or size of two binary bit strings or words. Logic circuits formed by combining several of the basic logic gates to form a more complex function. A device or system that identifies an equality between two quantities. A change to the opposite digital state. 1 becomes 0and 0 becomes 1. A digital circuit capable of complementing a binary string of bits based on an external control signal. A digital circuit capable of counting electronic events, such as pulses, by progressing through a sequence of binary states. Central processing unit; a major component of all computers that controls the internal operations and processes data. Information in numeric, alphabetic- or other form. A Boolean law used for equation reduction that allows the user to convert an equation having an inversion bar over several variables into an equivalent equation having inversion bars over single variables only. A digital counter having ten states. The base 10 numbering system. The 10 decimal digits are 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. Each decimal position is a different power of 10 (10 3, 10, 101, 100, and so on). A device that converts a digital code such as hex or octal into a single output representing its numeric value. A device or circuit capable of routing a single data-input line to one of several dataoutput lines; sometimes referred to as a data distributor. A type of bistable multivibrator in which the output follows the state of the D input. A symbol used to express a quantity. A system that deals with discrete digits or quantities. Digital electronics deals exclusively with 1’s and 0s, or ONs and OFFs. Digital codes (such as ASCII) are the used to convert the 1’s and 0’s to a meaningful number, letter, or symbol for some output display. A device in which information in digital codes to an analog form. To disallow or deactive a function or circuit. The condition in which a digital circuit’s inputs or outputs are not allowed to accept or transmit digital states. A variable appearing in a truth table or timing waveform that will have no effect on the final output regardless of the logic level of the variable. Therefore, don’t-care variables can be ignored. The negative-AND is the dual symbol for the NOR gate, and the negative-OR is the dual symbol for the NAND gate. The term given to a digital device that can accept inputs and change outputs only on the positive or negative edge of some input control signal or clock. A type of flip-flop in which the data are entered and appear on the same clock edge.
69
Electrical Noise : Enable : Enabled : Encoder : Error Indicator : Equivalent Circuit : Excess-3 Code: Exclusive-NOR: Exclusive-OR: Even Parity : Fast-Look-Ahead Carry :
Flip-Flop : Float : Full-Adder : Function Table: Gate :
Gray Code : Half-Adder : Hard disk : Hardware/ Software : Hex : Hexadecimal :
Hex Inverter : Input : Integrated Circuit :
Inversion Bar :
Inversion Bubbles : Inverter :
Unwanted electrical irregularities that can cause a change in a digital logic level. To allow or activate a function or circuit. The condition in which a digital circuit’s inputs or outputs are allowed to accept or transmit digital states normally. A device that converts a weighted numeric input line to an equivalent digital code, such as hex or octal. A visual display or digital signal that is used to signify that an error has occurred within a digital system. A simplified version of a logic circuit that can be used to perform the exact logic function of the original complex circuit. An unweighted digital code in which each of the decimal digits is represented by a 4-bit code by adding 3 to the decimal digit and converting to binary. A gate that produces a HIGH output for both inputs HIGH or both inputs LOW. A gate that produces a HIGH output for one or the other input HIGH, but not both. The condition of having an even number of 1s in every group of bits. When cascading several full-adders end to end, the carry-out of the last full-adder can’t be determined until each of the previous full-adder additions is completed. The internal carry must ripple or propagate through each of the lower-order adders before reaching the last full-adder. A fast-look-ahead carry system is used to speed up the process in a multibit system by reading all the input bits simultaneously to determine ahead of time it a carry-out of the last full-adder is going to occur. A basic storage circuit that can store only one bit at a time; a synchronous bistable device. A logic level in a digital circuit that is neither HIGH nor LOW. It acts like an open circuit to anything connected to it. An adder circuit having three inputs, used to add two binary digits plus a carry. It produces their sum and carry as outputs. A chart that illustrates the input/output operating characteristics of an integrated circuit. The basic building block of digital electronics. The basic logic gate has one or more inputs and one output and is used to perform one of the following logic functions: AND, OR, NOR, NAND, INVERTER, exclusive-OR, or exclusive-NOR. A binary coding system used primarily in rotating machinery to indicate a shaft position. Each successive binary string within the code changes by only 1 bit. An adder circuit used in the LS position when adding two binary digits with no carry-in to consider. It produces their sum and carry as outputs. A magnetic storage device mounted in a sealed housing. Sometimes solutions to digital applications can be done using hardware or software. The software approach uses computer program statements to solve the application, whereas the hardware approach uses digital electronic devices and ICs. When dealing with integrated circuits, a term specifying that there are six gates on a single IC package. The base 16 numbering system. The 16 hexadecimal digits are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Each hexadecimal position represents a different power of 16 (163, 162, 161, 160, and so on). An integrated circuit containing six inverters on a single DIP package. The signal or line going into a circuit; a signal that controls the operation of a circuit. The fabrication of several semiconductor and electronic devices (transistors, diodes, and resistors) onto a single piece of silicon crystal. Integrated circuits are increasingly being used to perform the functions that used to require several hundred discrete semiconductors. A line over variables in a Boolean equation signifying that the digital state of variables is to be complemented. For example, the output of a two-input NAND gate is written X= AB . An alternative to drawing the triangular inversion symbol. The bubble (or circle) can appear at the input or output of a logic gate. A logic circuit that changes its input into the opposite logic state at its output (0 to 1 and 1 to 0).
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J-K flip flop : Johnson counter: Karnaugh Map: Latch : Leading Edge : Least Significant Bit (LSB) : Logic Probe : Logic Pulser : Logic State : Logic Symbol : LSI : Master-slave flipflop : Microprocessor :
Minimization : Most Significant Bit (MSB) : MSI :
Multiplexer :
Multivibrator:
NAND Gate : Negative Edge : Negative Logic: Negative-AND: Negative-OR : Nibble : NOR Gate : NOT : Octal : Odd Parity : One’s Complement : Ones catching:
OR :
A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes. A type of register in which a specific pattern of 1s and 0s is shifted through the stages, creating a unique sequence of bit patterns. A two-dimensional table of Boolean output levels used as a tool to perform a systematic reduction of complex logic circuits into simplified equivalent circuits. A bistable digital device used for storing a bit. The first transition of a pulse. The bit having the least significance in a binary string. The LSB will be in the position of the lowest power of 2 within the binary number. An electronic tool used in the troubleshooting procedure to indicate a HIGH, LOW, or float level at a particular point in a circuit. An electronic tool used in the troubleshooting procedure to inject a pulse or pulse into a particular point in a circuit. A 1 or 0 digital level. Graphic representation of basic logic gates. Large-scale integration; a level of IC complexity in which there are 100 to 9999 equivalent gates per chip. A type of flip-flop in which the input data are entered into the device on the leading edge of the clock pulse and appear at the output on the trailing edge. A large-scale integration (LSI) integrated circuit that is the fundamental building block of a digital computer. It is controlled by software programs that allow it to do all digital arithmetic, logic, and I/O operations. The process that results in an SOP or POS Boolean expression containing the fewest possible terms with the fewest possible literals per term. The bit having the most significance in a binary string. The MSB will be in the position of the highest power of 2 within the binary number. Medium-scale integration. An IC chip containing combinational logic that is packed more densely that a basic logic gate IC (small-scale integration, SSI) but not as dense as a microprocessor IC (large-scale integration, LSI). There are 12 to 99 equivalent gates per chip in a MSI. A device or circuit capable of selecting one of the several data input lines for output to a single line; sometimes referred to as a data selector. A class of digital circuits in which the output is connected back to the input ( an arrangement called feedback) to produce either two stable states, one stable state- or no stable states, depending on the configuration. A logic circuit in which a LOW output occurs if and only if all the inputs are HIGH. The edge on a clock or triggered pulse that is making transition from HIGH to LOW. The 1 level is more negative than the 0 level. A NOR gate equivalent operation in which there is a HIGH output when all inputs are LOW. A NAND gate equivalent operation in which there is a HIGH output when all inputs are LOW. Four bits. A logic circuit in which the output is LOW when any or all of the inputs are HIGH. When reading a Boolean equation, the word used to signify an inversion bar. For example, the equation X=A’B’ is read “X equals NOT AB”. The base 8 numbering system. The eight octal numbers are 0, 1, 2, 3, 4, 5, 6, and 7. Each octal position represents a different power of 8 (8 3, 82, 81, 80, and so on). The condition of having an odd number of 1s in every group of bits. A binary number that is a direct (true) complement, bit by bit, of some other number. A feature of the master-slave flip-flop that allows the master section to latch on to any 1 level that is felt at the inputs at any time while the input clock pulse is HIGH and then transfer those levels to the slave when the clock goes LOW. A basic logic operation in which a true (HIGH) output occurs when one or more of the input conditions are true (HIGH).
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OR Gate : Overflow : Parallel Adder: Parity : PAL : PIC : PLA : PLD : Positive Edge : Priority : Priority Encoder : Product-of-Sums (POS) Form : Pulse : Pulse Triggered : Quad : Register : Registered : Reset : Ring Counter : Ripple Carry : Sequential Logic :
Set : Setup Time :
Sign Bit : Shift : Sign Bit : S-R flip-flop : SSI : Stage : State Diagram: Storage : Storage Register : Strobe Gates : Sum-of-Products (SOP) Form :
A logic circuit that produces a HIGH output when any of the inputs is HIGH. The condition that occurs when the number of bits in a sum exceeds the number of bits in each of the numbers added. An adder in which all bits are added simultaneously. An error-detection scheme used to detect a change in the value of a bit. Programmable Array Logic. A device with a programmable AND array and a fixed OR array. Programmable interrupt controller. Programmable logic array. A device with programmable AND and OR arrays. Programmable logic device. The edge on a clock or triggered pulse that is making the transition from LOW to HIGH. When more than one input to a device is activated and only one acted on, the one with the highest priority will be acted on. An encoder in which only the highest value input digit is encoded and any other active input is ignored. A Boolean equation in the form of a group of ORed variables ANDed with another group of ORed variables (for example, X=(A+B’)(A+C+D)(B+D’). A signal of short time. The term given to a digital device that can accept inputs during an entire positive or negative pulse of some input control signal or clock. (Also called level triggered) When dealing with integrated circuits, the term specifying that there are four gates on a single IC package. A digital circuit capable of storing and shifting binary information; typically used as a temporary storage device. A PLD output configuration where the output comes from a flip-flop. The state of a flip-flop or latch when the output is 0; the action of producing a RESET state. A register in which a certain pattern of 1s and 0s is continuously recirculated. A method of binary addition in which the output carry from each adder becomes the input carry of the next higher-order adder. Digital circuits that involve the use of a sequence of timing pulses in conjunction with storage devices such as flip-flops and latches and functional ICs such as counters and shift registers. The state of a flip-flop or latch when the output is 1; the action of producing a SET state. The length of time before the active edge of a triggered pulse (control signal) that the inputs of a digital device be in a stable digital state. (That is, if the set up time of a device is 20 ns, the inputs must be held stable 20 ns before the triggered edge) The leftmost, or MSB, in a two’s-complement number, used to signify the sign of the number (1=negative, 0=positive). To move binary data from stage to stage within a shift register or other storage device or to move binary data into or out of the device. The left-most bit of a binary number that designates whether the number is positive (0) or negative (1). A SET-RESET flip-flop. Small-scale integration; a level of IC complexity in which there are twelve fewer equivalent gates per chip. One storage element (flip-flop) in a register A graphic depiction of a sequence of states or values The capability of a digital device to retain bits; the process of retaining digital data for later use. Wo or more data storage circuits (such as flip-flops or latches) used in conjunction with each other to hold several bits of information. A control gate used to enable or disable inputs from reaching a particular digital deice. A Boolean equation in the form of a group of ANDed variables ORed with another group of ANDed variables (for example, X= AB’C + ACD + BD’.
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Synchronous : Synchronous Counter : Terminal Count: Timer : Timing Diagram : Toggle : Trailing Edge: Transmission : Transparent Latch : Trigger : Tristate : Troubleshooting : Truth Table : TTL :
Twisted-Ring Counter : Two’s Complement : ULSI : Universal Gates : Universal shift register : Up/Down Counter : Variable : VLSI : Word : Word Length :
A condition in which the output of a device will operate only in synchronization with (in step with) a specific HIGH or LOW timing pulse or trigger signal. A type of counter in which each stage is clocked by sample pulse. The final state in a counter’s sequence. A circuit that can be used as a one-shot or as an oscillator. A diagram used to display the price relationship between two or more digital waveforms as they vary relative to time. The action of a flip-flop when it changes state on each clock pulse (Q changes to the level Q’ and Q’ changes to the level of Q). The second transition of a pulse. The transfer of digital signals from one location to another. An asynchronous device whose outputs will hold onto the most recent digital state of the inputs. The outputs immediately follow the state of the inputs without regard to trigger input and remain in that state even after the inputs are removed or disabled. A pulse used to initiate a change in the state of a logic circuit. A type of output in logic circuits that exhibits three states : HIGH, LOW, and open (disconnected). The open state is called the high-Z state. The work that is done to find the problem in a faulty electrical circuit. A tabular listing that is used to illustrate all the possible combinations of digital input levels to gate and the output that will result. Transistor-transistor logic. The most common integrated circuit used in digital electronics today. A large family of different TTL ICs is used to perform all the logic functions necessary in a complete digital system. A ring counter in which the state of the input stage is the complement of the final stage. A binary numbering representation that simplifies arithmetic in digital systems. Ultra large-scale integration; a level of IC complexity in which there are more than 100.000 equivalent gates per chip. The NOR and NAND logic gates are sometimes called universal gates because any of the other logic gates can be formed from them. A register that has both serial and parallel input and output capability. A counter that can progress in either direction through a certain sequence. A symbol used to represent a logic quantity that can have a value at 1 or 0, usually designated by an italic letter. Very large-scale integration; a level of IC complexity in which there are 10.000 to 99.999 equivalent gates per chip. A complete unit of binary data. The number of bits in a word.
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APPENDIX B Supplementary Index of ICs All the logic gates are available in various configurations in the TTL and CMOS families. This is an index of the integrated circuits (ICs).
7400 Series ICs 7400 74LV00 7404 7408 74HCT08 74HC11
Quad 2-input NAND gate Quad 2-input NAND gate Hex Inverter Quad 2-input AND gate Quad 2-input AND gate Triple 3-input AND gate
74HC00 7402 74HC04 74HC08 7411 7414
74HC14 74HC21 7430 74HC32 7442
Hex inverter Schmitt trigger Dual 4-input AND gate 8-input NAND gate Quad 2-input OR gate BCD-to decimal decoder
7421 7427 7432 74HCT32 7447
7454
7474
7475 74LS76 7485
4-wide 2- and 3-input ANDOR-invert gate (AIO) Quad bistable latch Dual J-K flip-flop 4-bit magnitude comparator
7490 7593
Decade counter 4-bit binary ripple counter
7492 74H106
74109
74LS112
74121
Dual J-K positive edgetriggered flip-flop Monostable multivibrator
74S124
Voltage-controlled oscillator
74132
74138
1-of-8 decoder/demultiplexer
74LS138
74HCT138
1-of-8 decoder/demultiplexer
74139
74147
10-line-to-4-linr priority encoder 16-input multiplexer 1-of-16 decoder/demultiplexer 4-bit binary counter
74148
8-bit serial/parallel-in, serialout shift register BCD-to-binary converter
74181
8-input multiplexer 1-of-16 decoder/demultiplexer 8-bit serial-in parallel-out shift register 4-bit arithmetic logic unit
74185
Binary-to-BCD converter
74150 74154 74160 74165 74184
7476 7483 74HC86
74123
74151 74LS154 74164
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Quad 2-input NAND gate Quad 2-input NOR gate Hex inverter Quad 2-input AND gate Triple 3-input AND gate Hex inverter Schmitt trigger Dual 4-input AND gate Triple 3-input NOR gate Quad 2-input OR gate Quad 2-input OR gate BCD-to seven-segment decoder/ driver Dual D-type flip-flop Dual J-K flip-flop 4-bit full adder Quad –input exclusive-OR gate Divide-by-twelve counter Dual J-K negative edgetriggered flip-flop Dual J-K negative edgetriggered flip-flop Dual retriggered monostable multivibrator Quad 2-input NAND Schmitt trigger 1-of-8 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer 8-input priority encoder
Presettable BCD decade up/down counter Presettable BCD decade 74192 up/down counter 4-bit bi-directional universal 74194 shift register Octal buffer (3-state) 74241 74ABT244 Octal buffer (3-state) 74HCD273 Octal D flip-flop 74190
74193 74HCT238
Octal buffer (3-state) Octal transceiver (3-state) 9-bit odd/even parity generator/checker Octal D flip-flop with 3satate outputs 4-bit BCD adder
74LS244 74LS245 74280
74HC283
4-bit full adder with fast carry
74LS373
74395A
4-bit cascadable shift-register with 3-state outputs Inverting octal bus tarnsceiver
74HC583
74LS640
Presettable 4-bit binary up/down counter Presettable 4-bit binary up/down counter 1-of-8 demultiplexer
74191
74HCT4543
BCD-to-seven-segment latch/decoder/driver
Other ICs 4001 4011 4050
Quad 2-input NOR gate Quad 2-input NAND Hex non-inverting buffer
4008 4049 4051
4069B 4543
4504B 2118
2147H 2732 LF198
Hex inverter BCD-to-seven-segment latch/decoder/driver 4K X 1 static RAM 4K X 8 EPROM Sample and hold circuit
ADC0801 MC1408 NE5034 10125
Analog-to-digital converter Digital-to-analog converter Analog-to-digital converter ECL level shifter
PAL16H2 PAL16R8 8051 7805 741 IRF130 LM35 IN749
Programmable array logic Programmable array logic 8-bit microcontroller Voltage regulator Operational amplifier Power MOSFET Linear temperature sensor Zener diode
4-bit binary full adder Hex inverting buffer 8-channel analog multiplexer/demultiplexer Level-shifting buffer 16K X 1 dynamic RAM
2K X 8 EPROM Dynamic RAM controller Programmable-gain instrumentation amplifier DAC0808 Digital-to-analog converter AM3705 Analog multiplexer switch ECL level shifter 10124 Field programmable logic 82S100 (PLS100) array PAL16L8 Programmable array logic 8-bit microprocessor 8085A 8-bit microcontroller 68HC11 Timer 555 Opto-coupler 4N35 Phototransistor TIL601 Precision reference diode LM185 2716 3242 LH0084
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APPENDIX C TTL PIN CONFIGURATION
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EXPERIMENT-…… DATA SHEET Name of the Group Members
Sign
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Date:…./…../20
RESULTS
Lab.Assistant:……………………………………………. Sign:…………………….. 77
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