FPGA-Based CMOS Image Acquisition System Chao Li, Yu-lin Zhang, and Zhao-na Zheng School of Information science and Engineering, University of Jinan, Jinan, 250022, P.R. China
[email protected]
Abstract. This paper provides a plan about the high-speed acquisition and realtime process of image data based on FPGA (Field Programmable Gate Array). This design manages to acquire digital image data and store them into SDRAM with FPGA chips which belongs to Cyclone’s series of Altera Company, and sends them to VGA display in the end after the real-time process of image data using FPGA. This design is distinguished from traditional image acquisition system, and provides a universal solution that implements image acquisition with logic controlling based on FPGA. The system designed by abovementioned way achieves a satisfying effect by experimental verification. Keywords: Image Acquisition; Real-time; FPGA.
1 Introduction With the rapid development of image processing technology, image acquisition and processing systems are applied in all aspects increasingly [1]. In the current market of image sensors, CMOS sensor has more and more favor of consumers owing to its low prices. In the current applications, the majority of image acquisition and processing systems use DSP to control image sensors and collect image data, which is transmitted to PC through the USB interface. And these systems read image data with software, which will waste instruction cycles undoubtedly. Therefore, these image acquisition systems cannot meet real-time data acquired in high-speed [2]. For real-time image acquisition systems, which need high performance requirement because of a large amount of image data processed [3]. So, special hardware or technology of parallel processing is particularly important, and FPGA chips have natural advantages for real-time image processing system because of their specific units on the logical structure [4]. Therefore, in order to collect a mass of image data in real-time, this paper provides a design is that high-speed image acquisition system based on FPGA, which is realized with the OV9620 CMOS image sensor.
2 The Structure Performance Performance and Working Working Principium Principium of CMOS CMOS Image Sensor The system use OV9620 color digital CMOS image sensor of Omni Vision company, The OV9620 (color) are high-performance 1.3 mega-pixel for digital still image and video L. Qi (Ed.): FCC 2009, CCIS 34, pp. p p. 122–127, 122–127, 2009. © Springer-Verlag Berlin Heidelberg 2009
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camera products. The resolution for the OV9620 is 1280 x 1024(SXGA) pixels and 640 x 480(VGA) pixels, which can up to 30 frames per second (fps), and with some features such as high sensitivity, wide dynamic range, anti-blooming. All the parameters of images such as exposure, gain, white balance, frame rate, the output image data format, image timing signal polarity, window size and location, etc, can be set up through the SCCB interface, and take effect immediately [5]. The key parameters of OV9620 as following: Image Area is 6.66 mm×5.32 mm; Pixel Size is 5.2μm×5.2μm; resolution is 1280 x 1024 pixels (SXGA) and 640 x 480 pixels (VGA); Dynamic Range is 60dB; Scan Mode is Progressive. OV9620 embedded within a 10-bit A / D converter, which can simultaneously output 10 bit video streaming D [9…0]. In the output of digital video streaming, while CMOS senor also providing simultaneous pixel clock (PCLK), and the horizontal reference signal (HREF) and frame synchronization signal (VSYNC), facilitates the external circuit to read image data [6].
3 The Structure of System Design Diagram of the structure of this system as shown in Figure 1, as shown of the figure 1, the CMOS image sensor responsible for image acquisition, and FPGA is used to control CMOS image sensor, SDRAM is used to store image data. When the system runs, firstly, CMOS mode is initialized by FPGA through the SCCB bus, and then through the FPGA to control CMOS image acquisition, and then the collected CMOS sensor data transit into RGB format and storage to SDRAM. Finally, the image data are sent to the VGA display when one frame of image data are acquired.
SCCB Control OV9620
RGB VGA
FPGA CMOS Data
VGA Control
Read SDRAM
Write SDRAM SDRAM
Fig. 1. Basic Diagram of System’s structure
4 Operating Principle and Implementation of System Modules 4.1 Implementation of CMOS Image Acquisition
The OV9620 CAMERA CHIP offers 10-bit RGB raw data output. The default output sequence for the odd lines of output will be: RGRG… RG. The even lines of output will be: GBGB… GB. CMOS image sensor collects image data by FPGA.
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Once power on, the system first initializes CMOS image senor chip, and to determine its mode of operation. These parameters are controlled by corresponding value of the register within OV9620, FPGA controls the SCCB bus to configure these parameters. If system configuration is correct and the work mode is assured, the CMOS image senor begins to work. Figure 2 and figure 3 are pixel output timing drawing and frame output timing drawing respectively in VGA mode. In the figures, the VSYNC is vertical synchronization signal, the HREF is horizontal reference signal, PCLK is the pixel output synchronization signal. From figure 2 can be seen that CMOS image senor begins to collect valid data when the HREF signal is high, and the arrival of PCLK falling edge shows that valid data is generated, the system transmits one datum when one PCLK falling edge arrives. In the period of HREF is high, the system transmits 640 data in all. From figure 3 can be seen that HREF will appear 480 times high during the VSYNC is low. And one frame image that resolution is 640 × 480 is collected completely when the next VSYNC signals rising edge arrives.
Fig. 2. Pixel output timing
Fig. 3. Frame output timing
In the programming, this design uses two conditions to control VSYNC and HREF signals. First when VSYNC is low, the design is enter a cycle, and then begin to collect image data if HREF is high. The part code of this module is following: If (mCMOS_VS is low) && (mCMOS_HS is high) Begin to work: if (X_Cont
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Y_Cont <= Y_Cont + 1'b1; else Y_Cont <= 0 ; end 4.2
The Module of VGA
With the rapid development of computer display technology, computer industry has developed many kinds of display interface protocol, from the original MDA interface protocol to the mainstream VGA (video graphics array) interface protocol at present. in the framework of VGA interface, which is divided into different display mode according to the resolution and refresh rate: VGA(640×480), XGA 800×600 and VGA(1024 ×768). The timing of VGA include the horizontal timing and the vertical timing, which have parameters following: The horizontal (vertical) synchronization pulses; the interval between the end of horizontal (vertical) synchronization pulses and the beginning of display area(Back porch); display interval; the interval between the end of display area and the beginning of horizontal (vertical) synchronization pulses (Front porch). The function of VGA display module is to be processed image data signal displayed on the monitor. VGA timing parameters is required by look-up table after the display mode is determined. The resolution is 640 × 480, field frequency is 60HZ, which parameters are shown in Table 1. Table 1. VGA timing parameter
Format 640×480 60HZ
Horizontal (in Pixels)
Vertical (in Pixels)
Pixel Clock (MHZ)
Active Video
Front Porch
Sync Pulse
Back Porch
Active Video
Front Porch
Sync Pulse
Back Porch
25
640
16
96
48
480
11
2
31
Digital signals of images should be in accordance with the VGA timing signals in line as the format requested, and adding to some synchronization control signals. In this design, the synchronization signal is especially important, the reason is that if the synchronization signal is not correct, there will be some problems, such as display is divided into two part at a time and the image distortion.
5 The Results of This Design The final effect picture is shown in Figure 4. As a real-time acquisition system, the system has strict requirements in processing speed. In the current market, the majority of image acquisition and processing systems use DSP to control image sensors and collect image data, which is transmitted to PC through the USB interface. And these systems read image data with software, which will waste instruction cycles undoubtedly. Therefore, these image acquisition systems cannot meet real-time data acquired in high-speed.
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Fig. 4. The final effect
This image acquisition system is based on the FPGA, which has the following advantages compared to other image acquisition systems. First of all, it can improve system speed and system flexibility and adaptability; Secondly, it can improve sharply the performance of the system because of use FIFO to data buffer in FPGA; last but not least, it is fully implemented in hardware description language to control the image data collection and storage and also send the image to the VGA display in the end, therefore which makes external hardware circuit is simple and reduce the complexity in hardware design.
6 Conclusions As the price of FPGA chips is cheaper, and the real-time data acquisition for image system was designed based on FPGA has satisfying performance. This method is fitted to some cases which call for acquired in high speed and cost-effective. The system is designed in that way, and achieves a satisfying effect by experimental verification. This design provides a common model for the real-time data acquisition for image system.
References 1. Lei, S.-M., Sun, M.-T.: An entropy coding system for digital HDTV applications. IEEE Transactions on Circuits and Systems for Video Technology 1(1), 147– 155 (1991) 2. Murat Tekalp, A.: Digital Video Processing. Tsinghua Uni versity Press, Beijing (1998)
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3. Akermatt III, A.: Pyramidal Techniques for Multi-sensor Fusion SPIE: Sensor or Fusion V, vol. 1828, pp. 124–131 (1992) 4. Shui-ming, C.: The Application of FPGA on Real-time Image Pretreatment Algorithm. Electronic Technology of Shanxi Province (05) (2007) 5. Omni Vision Technologies, Inc. OV9620 Data Sheet (Version 2.5). September 15 (2003) 6. Gokhale, M.: Building and Using a Highly Parallel Programmable Logic Array. IEEE Computer, 81–89 (January)
