+V ).)
D
C2
H
2
AKL r
AND HIGH-FREQUENCY MODEL
At frequencies co (g /C ), can be neglected. In such case, quency resulting? Compute the case: C = 0.5 pF, C = 2 pF, g
C2
D
L
t
0
P4.99
^
L
+ C)
gs
FIGURE
sig
V
0
374
CHAPTER 4
/
MOS FIELD-EFFECT TRANSISTORS (MOSFETs)
PROBLEMS
at least a decade lower. (Hint: In determining the pole due to C , resistance R can be neglected.)
Vi=V - •• Vnn/2 is
SECTION 4 . 1 0 : THE CMOS DIGITAL LOGIC INVERTER
where V is the Early voltage for Q and Q . Assume Q and Q to be matched. (b) A CMOS inverter with devices having k'„(W/L) = k' (W/L) is biased by connecting a resistor R = 10 M Q between input and output. What is the dc voltage at input and output? What is the small-signal voltage gain and input resistance of the resulting amplifier? Assume the inverter to have the characteristics specified in Problem 4.105 with
C 2
-2
IV,
DD
• 4.7
m -oV
0
100 k í i —VW—
10 k Q
0.01 ixF
p
p
(a) the output resistance for v = V and for v = V (b) the maximum current that the inverter can sink or source while the output remains within 0.1 V of ground or V , respectively (c) V, , V ,NM , and NM 0
©
p
D D
10Mil?
:l0ju,F
2kfi.
0L
0
N
P
N
p
2
tp
0H
n
p
p
G
50 V.
\V
A
IL
H
L
SECTION 4 . 1 1 : THE DEPLETION-TYPE MOSFET
lk
FIGURE P 4 . 1 0 1
4 . 1 ©2 The NMOS transistor in the discrete CS amplifier circuit of Fig. P4.101 is biased to have g = 1 mA/V and r = 100 kQ. Find A . If C = 1 pF and C = 0.2 pF, fmd/ . m
M
gs
a
gd
sig
G
L
m
u
L
4 , 1 0 4 Figure P4.104 shows a MOS amplifier whose bias design and midband analysis were performed in Example 4.10. Specifically, the MOSFET is biased at I = 1.06 mA and has g = 0.725 mA/V and r = 47 kQ. The midband analysis showed that V/V,- = -3.3 V/V and R = 2.33 MQ. Select appro priate values for the two capacitors so that the low-frequency response is dominated by a pole at 10 Hz with the other pole D
m
p
n
p
p
n
n
ff
D 4 . 1 0 3 Consider the low-frequency response of the CS amplifier of Fig. 4.49(a). Let R = 0.5 MQ, R = 2 MQ, g = 3 mA/V, R = 20 kQ, and R = 10 kQ. Find A . Also, design the coupling and bypass capacitors to locate the three lowfrequency poles at 50 Hz, 10 Hz, and 3 Hz. Use a minimum total capacitance, with capacitors specified only to a single significant digit. What value off results? D
th
0
m
+ 15 V A
2
D
IL
4 . 1 0 8 Repeat Exercise 4.41 for V
DD
H
= 10 V and 15 V.
2
v
c
c
A
2
A
A
{
A
A
A
c
t
2
1
DS
* 4 . 1 1 7 Neglecting the channel-length-modulation effect show that for the depletion-type NMOS transistor of Fig. P4.117 the i—v relationship is given by i = lk' (W/L)(v
-2V,v),
n
2
tn
D2
A
n
4 . 1 0 9 Repeat Exercise 4.42 for V, = 0.5 V, 1.5 V, and 2 V. 4.11® For a technology in which V = Q.2V , show that the maximum current that the CMOS inverter can sink while its low output level does not exceed 0.1 V is Q.Q15k' (W/L) V . For V = 3 V, k' = 120 uA/V , and L„ = 0.8 urn, find the required transistor width to obtain a current of 1 mA.
E
4.116 For a particular depletion-mode NMOS device, V = - 2 V, k' W/L = 200 aA/V , and X = 0.02 V" . When operated at v - 0, what is the drain current that flows for v = 1 V, 2 V, 3 V, and 10 V? What does each of these currents become if the device width is doubled with L the same? With L also doubled? GS
4 . 1 0 7 For an inverter designed with equal-sized NMOS and PMOS transistors and fabricated in the technology speci fied in Problem 4.105 above, find V and V, and hence the noise margins.
m
3
2
4 . 1 1 5 A depletion-type n-channel MOSFET with k' W/L = 2 mA/V and V, = - 3 V has its source and gate grounded. Find the region of operation and the drain current for v = 0.1 V, 1 V, 3 V, and 5 V. Neglect the channel-length-modulation effect. n
4 . 1 0 6 For the technology specified in Problem 4.105, investigate how the threshold voltage of the inverter, V , var ies with the degree of matching of the NMOS and PMOS devices. Use the formula given in Exercise 4.44, and find V for the cases (W/L) = (W/L) , (W/L) = 2(W/L) (the matched case), and (W/L) = 4(W/L) .
n
2
DD
H
2
DSS
4 . 1 0 5 For a digital logic inverter fabricated in a 0.8-am CMOS technology for which k' = 1 2 0 a A / V , k' = 60 aA/ V , V,„ = \V \ = 0.7 V, V = 3 V , L „ = L = 0.8um,W„ = 1.2 am, and W = 2.4 am, find: n
3
2
t
A
2
0.1 yuF
on the bias of Q but provides an interesting function. R acts as load resistor in the drain of Q . Assume that and Q are fabricated together (as a matched pair, or as part of an IC) and are identical. For each depletion NMOS, I = 4 m A and | V,\ =2 V. The voltage at the input is some value, say 0 V, that keeps Q, in saturation. What is the value of k' (W/L) for these transistors? Now, design 7?] so that I = I = 1 mA. Make R = R Choose R so that v = 6 V. For v = 0 V, what is the voltage v ? Check what the voltage v is when v = ±1 V. Notice the inter esting behavior, namely, that node C follows node A. This cir cuit can be called a source follower, but it is a special one, one with zero offset! Note also that R is not essential, since node B also follows node A but with a positive offset. In many applica tions, R is short-circuited. Now, recognize that as the voltage on A rises, Q will eventually enter the triode region. At what value of v does this occur? Also, as v lowers, Q will enter its triode region. At what value of v 1 (Note that between these two values of v is the linear signal range of both v and v .) 2
0
G
(V /2)-V 47 M Q .
375
i = -\k' (W/L) V , n
for v>V,
for v < V,
DD
2
DD
n
n
DD
(Recall that V, is negative.) Sketch the i-v relationship for the case: V = -2 V and k' (W/L) = 2 mA/V . 2
t
n
2
DD
n
4 . 1 1 1 For the inverter specified in Problem 4.105, find the peak current drawn from the 3-V supply during switching. 4 . 1 1 2 For the inverter specified in Problem 4.105, find the value of t when the inverter is loaded with a capacitance C = 0.05 pF. Use both Eq. (4.156) and the approximate expression in Eq. (4.157), and compare the results. PHL
RD
10 k Q r
—vw Cci
g
10 M i l
4 . 1 1 3 Consider an inverter fabricated in the CMOS technol ogy specified in Problem 4.105 and having L = L = 0.8 am and (W/L) = 2(W/L) . It is required to limit the propagation delay to 60 ps when the inverter is loaded with 0.05-pF capaci tance. Find the required device widths, W and W . n
RL
10 k Q
© FIGURE P 4 . 1 0 4
p
p
FIGURE P 4 . 1 1 7
4 . 1 1 8 For the circuit analyzed in Exercise 4.51 (refer to Fig. E4.51), what does the voltage at the source become when the drain voltage is lowered to +1 V?
GENERAL PROBLEMS:
n
n
p
* 4 . 1 1 4 (a) In the transfer characteristic shown in Fig. 4.56, the segment BC is vertical because the Early effect is neglected. Taking the Early effect into account, use small-signal analysis to show that the slope of the transfer characteristic at
FIGURE P 4 . 1 2 0
4 . 1 1 9 A depletion-type NMOS transistor operating in the saturation region with v = 5 V conducts a drain current of 1 mA at v = - 1 V, and 9 m A at v = +1 V. Find I and V . Assume X = 0. DS
GS
GS
DSS
t
* * 4 . 1 2 1 The circuits shown in Fig. P4.121 employ negative feedback, a subject we shall study in detail in Chapter 8. Assume that each transistor is sized and biased so that g = 1 mA/V and r = 100 kQ. Otherwise, ignore all dc biasing detail and concentrate on small-signal operation resulting in response to the input signal v . For R = 10 kQ, R, = 500 kQ, m
0
D 4 . 1 2 0 Consider the circuit shown in Fig. P4.120 in which (2i with R, establishes the bias current for Q . R has no effect 2
2
sig
L
376
:
CHAPTER 4
M O S FIELD-EFFECT TRANSISTORS
and R = 1 M Q , find the overall voltage gain v /v and the input resistance R for each circuit. Neglect the body effect. Do these circuits remind you of op-amp circuits? Comment. 2
a
sig
1B
V
DD
A
(MOSFETs)
For NMOS transistors with V, = 0.6 V, find V , k' (W/L), and V to bias each device at I = 0.1 mA and to obtain the values of g and r specified in Problem 4.121; namely, g 1 mA/V and r = 100 kQ. For R = 0.5 M Q , R = 1 MQ, and R = 10 kQ, find the required value of V . ov
A
n
D
m
0
m
0
x
L
DB
* * 4 . 1 2 3 In the amplifier shown in Fig. P4.123, transistors having V = 0.6 V and V = 20 V are operated at V = 0.8 V using the appropriate choice of W/L ratio. In a particular application, Q is to be sized to operate at 10 pA, while Q is intended to operate at 1 mA. For R = 2 kQ, the (R , R ) net work sized to consume only 1% of the current in R , v , having zero dc component, and I = 10 ^ A , find the values of R and R that satisfy all the requirements. (Hint: V must be +2 V.) What is the voltage gain vjvp. Using a result from a theorem known as Miller's theorem (Chapter 6), find the input resis tance R as R /( \ - v /Vi). Now, calculate the value of the overall voltage gain v /v . Does this result remind you of the inverting configuration of the op amp? Comment. How would you modify the circuit at the input using an additional resistor and a very large capacitor to raise the gain v /v to - 5 V/V? Neglect the body effect. t
A
GS
t
2
L
wv
}
L
x
2
0
m
2
0
0
Ag
0
(a)
2
sig
t
©
=
2
Bipolar Junction Transistors (BJTs)
Ag
Introduction 5.1
Device Structure
5.2
5.4 5.5
B i a s i n g in B J T
T h e BJT Internal
and
5.10
421
Amplifier
436
5.11
460
Capacitances 485
F r e q u e n c y R e s p o n s e of t h e Common-Emitter
407
BJT C i r c u i t s at D C
Circuits
R -WV
5.9 392
The BJT as an Amplifier as a S w i t c h
Single-Stage BJT Amplifiers
and High-Frequency Model
378
Current-Voltage Characteristics
5.3
5.8
and
Physical Operation
©
5.7
377
Amplifier
The Basic BJT
Digital
L o g i c Inverter
503
The S P I C E BJT Model
and
Simulation Examples
507
Summary
516
Problems
517
491
2
5.6
Small-Signal Operation Models
and
443
INTRODUCTION
(b) FIGURE P 4 . 1 2 3 FIGURE P 4 . 1 2 1
4 . 1 2 2 For the two circuits in Problem 4.121 (shown in Fig. P4.121), we wish to consider their dc bias design. Since f has a zero dc component, we short circuit its generator. sig
4 . 1 2 4 Consider the bias design of the circuit of Problem 4.123 (shown in Fig. P4.123). For k' = 200 pA/V and V = 3.3 V, find (WIL) and (WIL) to obtain the operating conditions specified in Problem 4.123. 2
n
l
2
DD
In this chapter, w e study the other major three-terminal device: the bipolar junction transistor (BJT). T h e presentation of the material in this c h a p t e r parallels b u t does n o t rely o n that for the M O S F E T in C h a p t e r 4 ; thus, if desired, the B J T can b e studied before the M O S F E T . T h r e e - t e r m i n a l devices are far m o r e useful than t w o - t e r m i n a l ones, such as the diodes studied in C h a p t e r 3, b e c a u s e they can b e u s e d in a m u l t i t u d e of applications, r a n g i n g from signal amplification to t h e design of digital logic a n d m e m o r y circuits. T h e basic principle involved is t h e u s e of t h e v o l t a g e b e t w e e n t w o terminals to control the current flowing in the third terminal. In this w a y , a three-terminal device can b e u s e d to realize a controlled source, w h i c h as w e learned in C h a p t e r 1 is t h e basis for amplifier design. A l s o , in the extreme, t h e control signal c a n b e u s e d to c a u s e t h e current in the third terminal to c h a n g e from zero to a large v a l u e , thus allowing t h e device to act as a switch. A s w e learned also in
CHAPTER 5
5.1
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
C h a p t e r 1, t h e switch is the basis for the realization of the logic inverter, the basic element of digital circuits. T h e invention of the B I T in 1948 at the Bell T e l e p h o n e L a b o r a t o r i e s ushered in the era of solid-state circuits, w h i c h led to electronics c h a n g i n g the w a y w e w o r k , play, and indeed, live. T h e invention of the B J T also eventually led to the d o m i n a n c e of information technology and t h e e m e r g e n c e of t h e k n o w l e d g e - b a s e d e c o n o m y . T h e b i p o l a r transistor e n j o y e d n e a r l y t h r e e d e c a d e s as t h e d e v i c e of c h o i c e in the d e s i g n of b o t h discrete and i n t e g r a t e d circuits. A l t h o u g h t h e M O S F E T h a d b e e n k n o w n v e r y early on, it w a s n o t until t h e 1970s a n d 1980s that it b e c a m e a serious c o m p e t i t o r to the B J T . A t t h e t i m e of this w r i t i n g ( 2 0 0 3 ) , t h e M O S F E T is u n d o u b t e d l y t h e m o s t widely u s e d electronic d e v i c e , a n d C M O S t e c h n o l o g y is t h e t e c h n o l o g y of c h o i c e in t h e design of i n t e g r a t e d circuits. N e v e r t h e l e s s , t h e B J T r e m a i n s a significant d e v i c e that e x c e l s in certain a p p l i c a t i o n s . F o r i n s t a n c e , t h e reliability of B J T circuits u n d e r s e v e r e e n v i r o n m e n t a l c o n d i t i o n s m a k e s t h e m t h e d o m i n a n t d e v i c e in a u t o m o t i v e e l e c t r o n i c s , an i m p o r t a n t and s t i l l - g r o w i n g area. T h e B J T remains popular in discrete-circuit design, in w h i c h a very w i d e selection of B J T types are available to the designer. H e r e w e should mention that the characteristics of the bipolar transistor are so well understood that one is able to design transistor circuits w h o s e performance is remarkably predictable and quite insensitive to variations in device parameters. T h e B J T is still the preferred device in v e r y d e m a n d i n g analog circuit applications, both integrated and discrete. This is especially true in very-high-frequency applications, such as radio-frequency (RF) circuits for wireless s y s t e m s . A v e r y - h i g h - s p e e d digital logic-circuit family b a s e d o n bipolar transistors, n a m e l y emitter-coupled logic, is still in use. Finally, bipolar transistors can b e c o m b i n e d with M O S F E T s to create i n n o v a t i v e circuits that take a d v a n t a g e of the h i g h - i n p u t - i m p e d a n c e and l o w - p o w e r operation of M O S F E T s and the very-high-frequency operation and high-current-driving capability of bipolar transistors. T h e resulting technology is k n o w n as B i M O S or B i C M O S , and it is finding increasingly larger areas of application (see Chapters 6, 7, 9, and 11). In this chapter, w e shall start with a simple description of the physical operation of the BJT. T h o u g h simple, this physical description p r o v i d e s c o n s i d e r a b l e insight r e g a r d i n g t h e perform a n c e of the transistor as a circuit element. W e then quickly m o v e from describing current flow in t e r m s of e l e c t r o n s a n d h o l e s to a s t u d y of the t r a n s i s t o r t e r m i n a l characteristics. C i r c u i t m o d e l s for transistor operation in different m o d e s will b e d e v e l o p e d and utilized in the analysis a n d design of transistor circuits. T h e m a i n objective of this c h a p t e r is to develop in t h e r e a d e r a h i g h degree of familiarity w i t h t h e B J T . T h u s , b y t h e end of the chapter, the r e a d e r should b e able to p e r f o r m rapid first-order analysis of transistor circuits and to design single-stage transistor amplifiers and simple logic inverters.
5.1
DEVICE STRUCTURE A N D PHYSICAL O P E R A T I O N
Metal contact
Emitter (E)
Collector
(Q
Emitter-base junction (EBJ)
Base (B)
FIGURE 5.1
Collector-base junction (CBJ)
A simplified structure of the npn transistor.
Metal contact n Eo—
Emitter region
Collector region
B.I-.C
WÈÊ0È
-oC
6
B FIGURE 5.2
A simplified structure of the pnp transistor.
A terminal is c o n n e c t e d to each of the three s e m i c o n d u c t o r regions of t h e transistor, w i t h the terminals labeled e m i t t e r (E), b a s e (B), and collector (C). T h e transistor consists of t w o pn junctions, the e m i t t e r - b a s e j u n c t i o n (EBJ) and the collector-base j u n c t i o n (CBJ). D e p e n d i n g on the bias condition (forward or reverse) of each of these junctions, different m o d e s of operation of the B J T are obtained, as s h o w n in Table 5 . 1 . T h e active m o d e , w h i c h is also called forward active m o d e , is the one u s e d if the transistor is to o p e r a t e as an amplifier. S w i t c h i n g applications (e.g., logic circuits) utilize b o t h the cutoff m o d e and t h e s a t u r a t i o n m o d e . T h e r e v e r s e active (or inverse active) m o d e h a s very limited application b u t is conceptually important. A s w e will see shortly, c h a r g e carriers of b o t h p o l a r i t i e s — t h a t is, electrons and h o l e s — participate in t h e c u r r e n t - c o n d u c t i o n p r o c e s s in a bipolar transistor, w h i c h is t h e reason for the n a m e bipolar.
DEVICE STRUCTURE AND PHYSICAL OPERATION
5.1.1 Simplified Structure and Modes of Operation Figure 5.1 s h o w s a simplified structure for the B J T . A practical transistor structure will be s h o w n later (see also A p p e n d i x A , w h i c h deals with fabrication t e c h n o l o g y ) . A s s h o w n in Fig. 5 . 1 , the B J T consists of three s e m i c o n d u c t o r regions: the emitter region (n type), t h e b a s e region (p type), and the collector region (n type). S u c h a transistor is called an npn transistor. A n o t h e r transistor, a dual of the npn as s h o w n in Fig. 5.2, has a /?-type emitter, an w-type b a s e , and a / H y p e collector, and is appropriately called a pnp transistor.
:
. :'• .. -I 5 . "!
BJT Modes of Operation
Mode
EBJ
CBJ
Cutoff Active Reverse active Saturation
Reverse Forward Reverse Forward
Reverse Reverse Forward Forward
380
-L^'
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
Forward-biased V
5.1
DEVICE STRUCTURE A N D PHYSICAL O P E R A T I O N
Reverse-biased _ ^
-
Emitter (n)
EBJ depletion region
Base
CBJ depletion region
(P)
Collector
c
E O-
—CI-
Injected ho.e- i • ,• i
Recombined electrons ('«2)
+ -o v
+
o—
BE
-° v
CB
o-
BP ^
Distance (x)
1(-
V
BE
+
VCB
+
F I G U R E 5 . 3 Current flow in an npn transistor biased to operate in the active mode. (Reverse current components due to drift of thermally generated minority carriers are not shown.)
Effective base width W F I G U R E 5 . 4 Profiles of minority-carrier concentrations in the base and in the emitter of an npn transistor operating in the active mode: v >0 and < 7 > 0 . BE
CB
5.1.2 Operation of the n p n Transistor in the Active Mode 1
Let us start b y considering the physical operation of the transistor in the active m o d e . This situ
L e t us n o w c o n s i d e r t h e electrons injected from the emitter into t h e b a s e . T h e s e electrons
ation is illustrated in Fig. 5.3 for the npn transistor. T w o external voltage sources (shown as
will b e m i n o r i t y c a r r i e r s in t h e p - t y p e b a s e region. B e c a u s e the b a s e is u s u a l l y very thin,
batteries) are used to establish the required bias conditions for active-mode operation. T h e voltage
in the steady state the e x c e s s minority-carrier (electron) c o n c e n t r a t i o n in the b a s e will h a v e
V
BE
causes the />-type base to be higher in potential than the n-type emitter, thus forward-biasing
the emitter-base junction. T h e collector-base voltage V
CB
causes the «-type collector to b e at a
higher potential than the /?-type base, thus reverse-biasing the collector-base junction.
an almost-straight-line profile, as indicated b y t h e solid straight line in F i g . 5.4. T h e electron concentration will b e h i g h e s t [denoted b y n (0)] tration n (0) p
Current Flow
at t h e emitter side and l o w e s t (zero) at t h e
p
2
collector s i d e . A s in t h e c a s e of a n y f o r w a r d - b i a s e d pn j u n c t i o n (Section 3.7.5), the c o n c e n will b e proportional to e
V B E / V r
,
In the following description of current flow only diffusion-current c o m p o
nents are c o n s i d e r e d . Drift currents, due to t h e r m a l l y g e n e r a t e d m i n o r i t y carriers, are usually
n (0) p
1
= ne
(5.1)
p0
very small and can be neglected. Nevertheless, w e will h a v e m o r e to say about these reversewhere n
current c o m p o n e n t s at a later stage.
p0
T h e forward bias on t h e e m i t t e r - b a s e j u n c t i o n will c a u s e current to flow across this
is the t h e r m a l - e q u i l i b r i u m v a l u e of the minority-carrier (electron) c o n c e n t r a t i o n
in the b a s e r e g i o n , v
BE
is t h e forward b a s e - e m i t t e r bias v o l t a g e , and V is t h e thermal volt T
j u n c t i o n . C u r r e n t will consist of t w o c o m p o n e n t s : electrons injected from t h e emitter into
age, w h i c h is e q u a l to a p p r o x i m a t e l y 2 5 m V at r o o m t e m p e r a t u r e . T h e r e a s o n for the zero
the b a s e , and h o l e s injected f r o m the b a s e into the emitter. A s will b e c o m e apparent shortly,
c o n c e n t r a t i o n at t h e collector side of the b a s e is that t h e positive collector v o l t a g e v
it is h i g h l y desirable to h a v e the first c o m p o n e n t (electrons from emitter to b a s e ) at a m u c h
the electrons at that e n d to b e swept across the C B I depletion region.
CB
causes
h i g h e r level than the second c o m p o n e n t (holes from b a s e to emitter). This can b e a c c o m
T h e tapered minority-carrier concentration profile (Fig. 5.4) causes the electrons injected
plished b y fabricating the d e v i c e with a h e a v i l y d o p e d emitter and a lightly d o p e d b a s e ; that
into the base to diffuse through the base region toward the collector. This electron diffusion
is, the d e v i c e is d e s i g n e d to h a v e a high d e n s i t y of electrons in t h e emitter and a l o w density
current /„ is directly proportional to the slope of the straight-line concentration profile,
of holes in the b a s e . T h e current that flows across the e m i t t e r - b a s e j u n c t i o n will constitute the emitter current i , as indicated in F i g . 5.3. T h e direction of i is " o u t of" the emitter lead, w h i c h is in the E
E
/.
=
A
d E
q
D
- ^
n
d
X
(5.2)
direction of the h o l e current and o p p o s i t e to t h e direction of the electron current, w i t h the emitter current i b e i n g equal to the s u m of these t w o c o m p o n e n t s . H o w e v e r , since the electron E
c o m p o n e n t is m u c h larger than the h o l e c o m p o n e n t , t h e emitter current will b e d o m i n a t e d by the electron c o m p o n e n t .
1
The material in this section assumes that the reader is familiar with the operation of thepn junction under forward-bias conditions (Section 3.7.5).
This minority-carrier distribution in the base results from the boundary conditions imposed by the two junctions. It is not an exponentially decaying distribution, which would result if the base region were infinitely thick. Rather, the thin base causes the distribution to decay linearly. Furthermore, the reverse bias on the collector-base junction causes the electron concentration at the collector side of the base to be zero.
381
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
5.1
where A is t h e cross-sectional area of t h e b a s e - e m i t t e r j u n c t i o n (in t h e direction perpendi cular to t h e p a g e ) , q is t h e m a g n i t u d e of t h e electron charge, D is t h e electron diffusivity in the base, a n d W is t h e effective w i d t h of t h e b a s e . O b s e r v e that t h e n e g a t i v e slope of t h e minority-carrier concentration results in a n e g a t i v e current /„ across t h e b a s e ; that is, /„ flows from right t o left (in t h e n e g a t i v e direction of x). S o m e of t h e electrons that are diffusing t h r o u g h t h e b a s e region will c o m b i n e w i t h holes, which a r e t h e majority carriers in t h e b a s e . H o w e v e r , since t h e b a s e is usually v e r y thin, the proportion of electrons "lost" t h r o u g h this r e c o m b i n a t i o n process will b e quite small. Never theless, t h e recombination in t h e b a s e region causes the excess minority-carrier concentration profile t o deviate from a straight line a n d take t h e slightly c o n c a v e s h a p e indicated b y the broken line in F i g . 5.4. T h e slope of t h e concentration profile at t h e E B J is slightly higher than that at t h e C B J , with t h e difference accounting for t h e small n u m b e r of electrons lost in the b a s e region t h r o u g h r e c o m b i n a t i o n . E
n
DEVICE STRUCTURE A N D PHYSICAL O P E R A T I O N
The Base Current T h e b a s e current i is c o m p o s e d of t w o c o m p o n e n t s . T h e first c o m p o nent i is d u e to t h e holes injected from t h e b a s e region into t h e emitter region. This current c o m p o n e n t is p r o p o r t i o n a l to e , B
m
V B B / V j
_ A qD n] E
"»
v /v
p
BE
T ( 5
" ~^L—
-
5 )
w h e r e D is t h e h o l e diffusivity in t h e emitter, L is t h e h o l e diffusion length in t h e emitter, and N is t h e d o p i n g concentration of t h e emitter. p
p
D
T h e s e c o n d c o m p o n e n t of b a s e current, i , is d u e t o holes that h a v e t o b e supplied b y t h e external circuit in order t o r e p l a c e t h e holes lost from t h e b a s e t h r o u g h t h e r e c o m b i n a t i o n process. A n expression for i c a n b e found b y noting that if t h e a v e r a g e t i m e for a minority electron to r e c o m b i n e with a majority hole in t h e b a s e is denoted x (called minority-carrier lifetime), then in T seconds t h e minority-carrier c h a r g e in t h e b a s e , Q , r e c o m b i n e s w i t h holes. Of course in t h e steady state, Q is r e p l e n i s h e d b y electron injection from t h e emitter. T o replenish t h e holes, t h e current i m u s t supply t h e b a s e with a positive c h a r g e equal to Q every % s e c o n d s , B2
B2
b
h
n
n
The Collector Current
F r o m the description above w e see that m o s t of the diffusing elec trons will r e a c h t h e b o u n d a r y of t h e c o l l e c t o r - b a s e depletion region. B e c a u s e t h e collector is more positive than t h e b a s e (by v volts), these successful electrons will b e s w e p t across the C B J depletion region into t h e collector. T h e y will thus get " c o l l e c t e d " to constitute t h e collector current i . T h u s i = I , w h i c h will yield a n e g a t i v e value for i , indicating that i flows in t h e n e g a t i v e direction of t h e x axis (i.e., from right t o left). S i n c e w e will take this to b e t h e positive direction of i , w e c a n drop t h e negative sign in E q . (5.2). D o i n g this and substituting for n (0) from E q . (5.1), w e can thus express t h e collector current i as
B2
n
CB
c
c
n
c
i2
(5.6)
=
B
%
c
c
p
T h e minorify-carrier charge stored in the base region, Q , can b e found b y reference to Fig. 5.4. Specifically, Q is r e p r e s e n t e d b y t h e area of t h e triangle u n d e r t h e straight-line distribution in t h e base, t h u s n
n
c
v /V BE
Q
T
=
n
i
= Ie
c
(5.3)
s
A qx\n {Q)W E
p
Substituting for n (0) from E q . (5.1) a n d r e p l a c i n g n p
p0
b y n,/N
A
r
gives
w h e r e t h e s a t u r a t i o n c u r r e n t I is given b y s
I
s
=
A qD n /W E
n
p0
Substituting n = nf/N , w h e r e n is t h e intrinsic carrier density a n d N is t h e d o p i n g con centration in t h e b a s e , w e c a n express I as p0
A
t
A
which c a n b e substituted in E q . (5.6) to obtain
_ \A qWn)
s
v /v
E
= S
E
BE
B2 ~ 7j 7T7J—e %N
A qD n]
T
(5.S)
2
n
A
NW A
C o m b i n i n g E q s . (5.5) a n d (5.8) a n d utilizing E q . (5.4), w e obtain for t h e total b a s e current i the expression
B
A n i m p o r t a n t observation t o m a k e h e r e is that t h e m a g n i t u d e of i is i n d e p e n d e n t of v . That is, as long as t h e collector is positive w i t h respect to t h e b a s e , t h e electrons that reach the collector side of t h e b a s e region will b e s w e p t into t h e collector a n d register as collector current. T h e saturation current h is inversely p r o p o r t i o n a l to t h e b a s e w i d t h W a n d is directly c
CB
proportional to t h e area of t h e E B J . T y p i c a l l y I
—12 1 Z
s
is in t h e r a n g e of 1 0 " 2
n
2D T )
p
n
b
C o m p a r i n g E q s . (5.3) a n d (5.9), w e see that i c a n b e e x p r e s s e d as a fraction of i as follows: B
c
A to 1 0 ° A h
l
= j
(5.-10)
{
That is, fl \ s
s
BE
D
—18 _ 1
(depending o n t h e size of the device). B e c a u s e I is p r o p o r t i o n a l to n , it is a strong function of temperature, approximately d o u b l i n g for e v e r y 5 ° C rise in t e m p e r a t u r e . (For t h e depen dence of nf o n t e m p e r a t u r e , refer to E q . 3.37.) Since I is directly proportional to t h e j u n c t i o n area (i.e., t h e device size), it will also b e referred t o as t h e scale c u r r e n t . T w o transistors that a r e identical except that o n e h a s an EBJ area, say, t w i c e that of t h e other will h a v e saturation currents with that s a m e ratio (i.e., 2 ) . T h u s for t h e same value of v t h e larger device will h a v e a collector current twice that in t h e smaller device. This c o n c e p t is frequently e m p l o y e d i n integrated-circuit design. s
\D N L
w h e r e ß is g i v e n b y
v /V BE
T
11\
AFTER 5
C
f r o m w h i c h w e s e e that ¡3 is a c o n s t a n t for a p a r t i c u l a r transistor. F o r m o d e r n npn transistors, ¡3 is in t h e r a n g e 5 0 to 2 0 0 , b u t it c a n b e as h i g h as 1 0 0 0 for s p e c i a l d e v i c e s . F o r r e a s o n s that will b e c o m e clear later, t h e c o n s t a n t ¡3 is c a l l e d t h e c o m m o n - e m i t t e r c u r r e n t gain. Equation (5.12) indicates that the v a l u e of f3 is highly influenced b y t w o factors: the w i d t h of the b a s e region, W, and the relative d o p i n g s of t h e b a s e region a n d the emitter region, (N /N ). T o obtain a h i g h ¡3 ( w h i c h is highly desirable since ¡3 represents a gain p a r a m e t e r ) the b a s e should b e thin (W small) and lightly d o p e d and the emitter heavily d o p e d ( m a k i n g N /N s m a l l ) . F i n a l l y , w e n o t e that t h e d i s c u s s i o n t h u s far a s s u m e s an i d e a l i z e d situation, w h e r e ¡3 is a constant for a g i v e n transistor. A
D
A
DEVICE STRUCTURE A N D PHYSICAL O P E R A T I O N
5.1
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
Q
ic
<£>>
v
"nr.' T
B o-
B oJ_
/>,;
D
QSE
=
+
%
/a
h r) V
BE
The Emitter Current Since the current that enters a transistor m u s t leave it, it can be seen from Fig. 5.3 that the emitter current i is equal to the s u m of the collector current i and t h e b a s e current i ; that is, E
c
B
(b)
(a) = ic + i
(5.13)
s
FIGURE 5 . 5 Large-signal equivalent-circuit models of the npn BJT operating in the forward active mode.
U s e of E q s . (5.10) a n d (5.13) gives h = ^ r i c ß
(5.14)
T h a t is,
R e c a p i t u l a t i o n a n d E q u i v a l e n t - C i r c u i t M o d e l s W e h a v e presented a first-order m o d e l for t h e o p e r a t i o n of t h e npn t r a n s i s t o r in t h e a c t i v e (or " f o r w a r d " a c t i v e ) m o d e . B a s i cally, t h e forward-bias v o l t a g e v causes an exponentially related current i to flow in the collector terminal. T h e collector current i is i n d e p e n d e n t of the value of the collector voltage as long as t h e c o l l e c t o r - b a s e j u n c t i o n r e m a i n s reverse-biased; that is, v ^ 0. T h u s in the active m o d e t h e collector terminal b e h a v e s as an ideal constant-current source w h e r e the value of t h e current is d e t e r m i n e d b y v . T h e b a s e current i is a factor 1 / / 3 of the collector current, and t h e emitter current is equal to t h e s u m of t h e collector and b a s e currents. Since i is m u c h smaller than i (i.e., [3 > 1), i — i . M o r e precisely, t h e collector current is a fraction a of the emitter current, with a smaller than, b u t close to, unity. BE
c
c
iE-
(5.15)
h
ß
Alternatively, w e can express Eq. (5.14) in the form k
CB
BE
= ah
(5.16)
B
c
B
F
E
F
w h e r e the constant a is related to ¡3 b y
F
c
F
T h i s first-order m o d e l of transistor o p e r a t i o n in t h e f o r w a r d a c t i v e m o d e c a n b e r e p r e sented b y t h e e q u i v a l e n t circuit s h o w n in F i g . 5.5(a). H e r e d i o d e D h a s a scale c u r r e n t I equal to (I /a ) a n d thus p r o v i d e s a c u r r e n t i r e l a t e d to v a c c o r d i n g to Eq. (5.18). T h e current of t h e c o n t r o l l e d s o u r c e , w h i c h is e q u a l to t h e collector current, is c o n t r o l l e d b y v a c c o r d i n g to t h e e x p o n e n t i a l r e l a t i o n s h i p i n d i c a t e d , a r e s t a t e m e n t of E q . ( 5 . 3 ) . T h i s m o d e l is in e s s e n c e a n o n l i n e a r v o l t a g e - c o n t r o l l e d c u r r e n t s o u r c e . It c a n b e c o n v e r t e d t o the c u r r e n t - c o n t r o l l e d c u r r e n t - s o u r c e m o d e l s h o w n in F i g . 5.5(b) b y e x p r e s s i n g t h e current of t h e c o n t r o l l e d s o u r c e as a i . N o t e that this m o d e l is also n o n l i n e a r b e c a u s e of t h e e x p o n e n t i a l r e l a t i o n s h i p of t h e current i t h r o u g h d i o d e D a n d t h e v o l t a g e v . F r o m this m o d e l w e o b s e r v e that if t h e transistor is u s e d as a t w o - p o r t n e t w o r k w i t h t h e i n p u t p o r t b e t w e e n E a n d B a n d t h e o u t p u t p o r t b e t w e e n C a n d B (i.e., w i t h B as a c o m m o n t e r m i nal), t h e n t h e c u r r e n t g a i n o b s e r v e d is e q u a l to a . T h u s a is called t h e c o m m o n - b a s e current g a i n . E
a
( 5
= j 3 h
-
1 7 )
T h u s t h e emitter current in Eq. (5.15) can b e written
s
F
E
SE
BE
BE
i
E
= (l /a)e
(5.18)
s
Finally, w e can u s e E q . (5.17) to express ¡3 in t e r m s of a; that is,
F E
E
P = ^
(5.19)
It can b e seen from Eq. (5.17) that a is a constant (for a particular transistor) that is less t h a n b u t very close to unity. F o r instance, if ¡3 = 100, t h e n a — 0.99. E q u a t i o n (5.19) reveals an i m p o r t a n t fact: S m a l l c h a n g e s in a c o r r e s p o n d to very large c h a n g e s in ¡3. T h i s m a t h e matical observation manifests itself physically, with t h e result that transistors of the s a m e t y p e m a y h a v e w i d e l y different values of ¡3. F o r r e a s o n s that will b e c o m e apparent later, a is called the c o m m o n - b a s e c u r r e n t g a i n . Finally, w e should note that b e c a u s e a and ¡3 characterize the operation of the B J T in t h e " f o r w a r d - a c t i v e " m o d e (as o p p o s e d to the " r e v e r s e - a c t i v e " m o d e , w h i c h w e shall discuss shortly), t h e y are often denoted a and /3 . W e shall u s e a and a i n t e r c h a n g e a b l y and, similarly, ¡3 and j3 . F
F
F
F
E
F
BE
F
WÊÊÊÊÊÊÈÊÊm 5.1 Consider an npn transistor with v
BE
Ans. 0.64 V ; 0.76 V
= 0.7 V at i = 1 m A . Find v c
Br
at /<• = 0.1 mA and 10 mA.
385
CHAPTER 5
3 8 6
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
DEVICE STRUCTURE A N D PHYSICAL
5.1
OPERATION
C 5.2
Transistors of a certain type are specified to have ¡5 values in the range 50 to 150. Find the range of their a values. Ans. 0.980 to 0.993
5.3
Measurement of an npn BJT in a particular circuit shows the base current to be 14.46 i/A, the emitter current to be 1.460 mA. and the base-emitter voltage to be 0.7 V. For these conditions, calculate or, j8. Ans. 0.99; 100; 1 0 "
5.4
15
B
A
Calculate ¡5 for two transistors for which a = 0.99 and 0.98. For collector currents of" 10 mA, find the base current of each transistor. F I G U R E S . 7 Model for the npn transistor when operated in the reverse active mode (i.e., with the CBJ forward biased and the EBJ reverse biased).
O E
Ans. 99; 49; 0.1 m A ; 0.2 m A
T h e large scale current I h a s the effect that for t h e s a m e current, the C B J exhibits a lower v o l t a g e d r o p w h e n forward b i a s e d t h a n the forward voltage d r o p of the E B J , V . This point will h a v e implications for the B J T ' s operation in t h e saturation m o d e . sc
BE
5.1.3 Structure of Actual Transistors F i g u r e 5.6 s h o w s a m o r e realistic (but still simplified) cross-section of an npn B J T . N o t e that the collector virtually surrounds t h e emitter region, t h u s m a k i n g it difficult for t h e electrons injected into the thin b a s e to e s c a p e b e i n g collected. In this w a y , the resulting a is close to unity and /3 is large. A l s o , observe that the d e v i c e is not s y m m e t r i c a l . F o r m o r e detail on the physical structure of actual devices, the r e a d e r is referred to A p p e n d i x A . F
F
T h e fact that t h e B J T structure is n o t s y m m e t r i c a l m e a n s that if t h e emitter and collector are interchanged and the transistor is operated in the reverse active m o d e , the resulting values of a a n d ¡3, d e n o t e d a a n d fi , w i l l b e different f r o m t h e f o r w a r d a c t i v e m o d e v a l u e s , a a n d j3 . F u r t h e r m o r e , b e c a u s e t h e structure is o p t i m i z e d for forward m o d e operation, a and /3 will b e m u c h l o w e r than their forward m o d e counterparts. Of c o u r s e , a a n d /3 wee related b y e q u a t i o n s identical to those that relate a and [5 . Typically, a is in t h e r a n g e of 0.01 to 0 . 5 , and t h e c o r r e s p o n d i n g r a n g e of /3 is 0.01 to 1. T h e structure in F i g . 5.6 indicates also that t h e C B J h a s a m u c h larger area t h a n t h e E B J . It follows that if the transistor is operated in the r e v e r s e active m o d e (i.e., with t h e C B J forward b i a s e d a n d t h e E B J r e v e r s e b i a s e d ) a n d t h e o p e r a t i o n is m o d e l e d in t h e m a n n e r of Fig. 5.5(b), w e obtain the m o d e l s h o w n in Fig. 5.7. H e r e diode D represents the collector-base j u n c t i o n a n d h a s a scale current I that is m u c h larger than the scale current I of d i o d e D . T h e t w o scale currents h a v e , of c o u r s e , t h e s a m e ratio as t h e areas of the c o r r e s p o n d i n g j u n c tions. F u r t h e r m o r e , a simple and elegant formula relates t h e scale currents I , I , and I and t h e current gains a and a , n a m e l y R
R
5.5
F
K
SF
sr
A
Ans. 1 0 "
F
F
A particular transistor is said to have a = 1 and a = 0 . 0 1 . Its emitter scale current (I ) is approximately 10 • A. What is its collector scale current ( / ) ? What is the size of Ihe collector junction relative to the emitter junction? What is the value of/J ,? 13
A; 100 times larger; 0.01
R
R
R
F
F
R
R
R
5.1.4 The Ebers-Moll (EM) Model T h e m o d e l of F i g . 5.5(a) can b e c o m b i n e d with that of F i g . 5.7 to obtain t h e circuit m o d e l s h o w n in Fig. 5.8. N o t e that w e h a v e relabelled t h e currents t h r o u g h D and D , and the corr e s p o n d i n g control currents of the controlled sources, as i and i . E b e r s a n d M o l l , t w o E
DE
c
DC
c
sc
SE
SE
F
C
E
sc
Q
s
R
(5.20)
a RISC
E
B
o
c
Q
7
FIGURE 5 . 6 Cross-section of an npn BJT.
Bo-
o
7 FIGURE 5 . 8 The Ebers-Moll (EM) model of the npn transistor.
387
338
DEVICE S T R U C T U R E A N D P H Y S I C A L O P E R A T I O N
5.1
CHAPTER 5 BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTs)
3 8 9
early w o r k e r s i n t h e area, h a v e s h o w n that this c o m p o s i t e m o d e l c a n b e u s e d t o predict t h e operation of t h e B J T in all of its possible
modes.
T o s e e h o w this c a n b e d o n e , w e derive
expressions for t h e t e r m i n a l currents i , i , a n d i i n t e r m s of t h e j u n c t i o n v o l t a g e s v E
c
B
and
BE
Saturation
v . T o w a r d that end, w e w r i t e an e x p r e s s i o n for t h e current at e a c h of t h e three n o d e s of t h e BC
model in Fig. 5.8 as follows: =
i
A
IDE ~
(5.21)
L
R DC
c
= -i
B
= (l-a )i
(5.22)
+ (X l E
D C
F D
(5.23) i
F
Then w e u s e t h e d i o d e e q u a t i o n t o e x p r e s s i i
D E
= l
S
+ (l-a )i
D E
D E
R
and i
D C
D C
as
( e ^ - l )
E
(5.24)
and ioc = h c ( e Substituting for i
D E
and i
D C
B
c
/
V
T
-D
i n E q s . (5.21), (5.22), a n d (5.23) a n d u s i n g t h e relationship i n
(
/ -
/
FIGURE 5 . 9 The i -v characteristic of an npn transistor fed with a constant emitter current I . The transistor enters the saturation mode of operation for v < -0.4 V, and the collector current diminishes. c
CB
E
CB
Eq. (5.20) yield t h e r e q u i r e d e x p r e s s i o n s :
)
Expanded scale
(5-25)
^ _ l
)
_ 7
s
/ -
(
/
^ - l )
'
(5.26) In e a c h of t h e s e three e q u a t i o n s , o n e c a n n o r m a l l y n e g l e c t t h e s e c o n d t e r m o n t h e r i g h t - h a n d
/
c
= / , ( / ^ - l ) - f ^ V ' a,
B
c
/
V
r
- l )
(5.28).
T h u s far, w e h a v e s t a t e d t h e c o n d i t i o n f o r f o r w a r d a c t i v e m o d e o p e r a t i o n a s v
CB
>0
to e n s u r e t h a t t h e C B J is r e v e r s e b i a s e d . I n a c t u a l fact, h o w e v e r , a pn j u n c t i o n d o e s n o t
vpV
F
side. This results i n t h e familiar current-voltage relationships w e d e r i v e d earlier, n a m e l y , Eqs. (5.18), (5.3), a n d (5.11), respectively.
kXe'^-^JkXe^-l) ßJ
.(5-27)
b e c o m e effectively forward biased until the forward voltage across it exceeds approxi where
m a t e l y 0.5 V . I t f o l l o w s t h a t o n e c a n m a i n t a i n a c t i v e m o d e o p e r a t i o n o f an npn transistor ß
(5.29)
-
for negative v
CB
d o w n t o approximately - 0 . 4 V o r so. This is illustrated i n Fig. 5.9, w h i c h
shows a sketch of i versus v c
CB
f o r a n npn t r a n s i s t o r o p e r a t e d w i t h a c o n s t a n t - e m i t t e r c u r
r e n t I . O b s e r v e t h a t i r e m a i n s c o n s t a n t at a I E
and
c
F
for v
E
CB
going negative to approximately
- 0 . 4 V . B e l o w this v a l u e of v , t h e C B I b e g i n s t o c o n d u c t sufficiently that t h e transistor CB
R
R
=
(5-30)
leaves t h e a c t i v e m o d e a n d e n t e r s t h e s a t u r a t i o n m o d e o f o p e r a t i o n , w h e r e i e q u a t i o n s t o verify t h a t t h e t e r m s c o n t a i n i n g
A s a first application of t h e E M m o d e l , w e shall u s e it t o predict t h e t e r m i n a l currents of a transistor o p e r a t i n g i n t h e forward active m o d e . H e r e v
BE
0.6 V to 0.8 V , a n d v
BC
c
decreases.
W e shall s t u d y B J T s a t u r a t i o n n e x t . F o r n o w , h o w e v e r , n o t e that w e c a n u s e t h e E M V B c / V j e
remain negligibly small for v
BC
as
h i g h a s 0.4 V .
is positive a n d i n t h e r a n g e of
is n e g a t i v e . O n e c a n easily see that t e r m s c o n t a i n i n g e
will be
negligibly s m a l l a n 4 c a n b e n e g l e c t e d t o o b t a i n v
I s . \ ^ r
+
I
(
l
_ ± )
(5
.31) 5.6
/Y
. *>* r :Ise
+
I
s
( ±- i ) \a R
(5.32)
!
1 or a KIT with it, - u.«J»>. • 0.(i2. and /• - Id " A. calculate i l v -.ccond lerin on the riglu-haml Mikof each of Eqs. (5.31), (5.32). and (5.33) to verify that they can be ignored. Then calculate i . i , and i for v = 0.7 V. F
Bli
Ans - I d '
V 4 < ) •. Id \ V - 3 • l<>
r
A;
m . \ : I. I l(. i n \ : I U I I 4 5 m \
c
B
CHAPTER 5
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTs)
5.1
DEVICE STRUCTURE A N D PHYSICAL O P E R A T I O N
EXERCISE 5.7
(a) U s e t h e E M expressions in Eqs. (5.26) and (5.27) t o show that the ir-v relationship sketched in Fig. 5.9 can b e described by i = a I + / [ a - (l/a )]e » . Neglect all terms not containing exponentials. CB
v
c
F
B
s
F
c/VT
K
15
(b) For the case I = K ) " A , I = 1 m A , a = 1, and a = 0.01, find i for v +0.54 V , and +0.57 V. Also find the value of v at which i = 0. s
E
F
R
BC
(c) At the value of v
BC
c
BC
= - 1 V, +0.4 V, +0.5 V,
c
that makes i zero, what do you think i should be? Verify using Eq. (5.28). c
B
Ans. (b) 1 m A: 1 m A ; 0.95 mA; 0.76 m A ; 0.20 m A ; 576 m V ; (c) 1 m A
5.1.6 The p n p Transistor W
0
T h e pnp transistor operates in a m a n n e r similar t o that of t h e npn d e v i c e described a b o v e . Figure 5.11 s h o w s a pnp transistor biased t o operate i n t h e active m o d e . H e r e t h e voltage V causes the p-type emitter t o b e h i g h e r i n potential than t h e ra-type b a s e , thus forward-biasing the b a s e - e m i t t e r j u n c t i o n . T h e c o l l e c t o r - b a s e j u n c t i o n is reverse-biased b y t h e voltage V , which k e e p s t h e p-type collector l o w e r in potential than t h e /?-type b a s e . U n l i k e t h e npn transistor, current in t h e pnp device is m a i n l y c o n d u c t e d b y holes injected from t h e emitter into t h e b a s e as a result of t h e forward-bias v o l t a g e V . S i n c e t h e c o m p o n e n t of emitter current contributed b y electrons injected from b a s e to emitter is k e p t small b y u s i n g a lightly d o p e d b a s e , m o s t of t h e emitter current will b e d u e to h o l e s . T h e electrons injected from b a s e to emitter g i v e rise t o t h e first c o m p o n e n t of b a s e current, i . Also, a n u m b e r of t h e holes injected into the b a s e will r e c o m b i n e w i t h t h e majority carriers in t h e base (electrons) a n d will thus b e lost. T h e disappearing b a s e electrons will h a v e t o b e replaced from t h e external circuit, giving rise to t h e s e c o n d c o m p o n e n t of b a s e current, i . T h e holes that succeed in reaching t h e b o u n d a r y of t h e depletion region of t h e c o l l e c t o r base j u n c t i o n will b e attracted b y t h e n e g a t i v e voltage o n t h e collector. T h u s these holes will be swept across t h e depletion region into t h e collector a n d appear as collector current. EB
FIGURE 5 . 1 0 Concentration profile of the minority carriers (electrons) in the base of an npn transistor operating in the saturation mode.
BC
EB
3
5.1.5 Operation in the Saturation Mode Figure 5.9 indicates that as v is l o w e r e d b e l o w approximately 0.4 V , t h e B J T enters the saturation m o d e of operation. Ideally, v h a s n o effect o n t h e collector current in t h e active mode, b u t t h e situation c h a n g e s dramatically in saturation: Increasing v in t h e negative direction—that i s , increasing t h e forward-bias v o l t a g e of t h e C B J — r e d u c e s i . T o see this analytically, consider t h e E b e r s - M o l l expression for i i n E q . (5.27) and, for simplicity, neglect the terms n o t involving e x p o n e n t i a l s t o obtain CB
CB
CB
c
c
F./V
T
ff -\ — \e
Bl
B2
(5-34)
va,
Forward-biased T h e first term o n t h e right-hand side is a result of t h e forward-biased E B J , a n d t h e second term is a result of t h e forward-biased C B J . T h e second t e r m starts t o play a role w h e n v exceeds approximately 0.4 V or so. A s v is increased, this t e r m b e c o m e s larger and subtracts from the first term, causing i t o reduce, eventually reaching zero. Of course, o n e c a n operate the saturated transistor at a n y v a l u e of i l o w e r than a I . W e will h a v e m o r e t o say about saturation-mode operation in s u b s e q u e n t sections. H e r e , h o w e v e r , it is instructive t o e x a m ine the minority-carrier concentration profile i n t h e b a s e of t h e saturated transistor, as s h o w n in Fig. 5.10. O b s e r v e that b e c a u s e t h e C B J is n o w forward biased, t h e electron concentration at the collector e d g e of t h e b a s e is n o l o n g e r zero; rather, it is a value proportional to
Reverse-biased
BC
c
c
e
%c
/ v
r
A
l
s
o
n
o
t
e
m
a
t
t
n
e
s
i
o
p
e
0
f
m
e
F
- y
•PB ••IR
BC
FIII
mÈÈÈ
E
Injected e^aio'i«,
'J5
Un -m Recombined holes
c o n c e n t r a t i o n profile is r e d u c e d in c o r r e s p o n d e n c e
with the reduction in i . c
+
3
Saturation in a BJT means something completely different from that in a MOSFET. The saturation mode of operation of the BJT is analogous to the triode region of operation of the MOSFET. On the other hand, the saturation region of operation of the MOSFET corresponds to the active mode of BJT operation.
t. FIGURE 5 . 1 1
+
-° v
EB
o-
-°
v oBC
Current flow in a pnp transistor biased to operate in the active mode.
3 9 1
CHAPTER 5
392
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.2
CURRENT-VOLTAGE CHARACTERISTICS
OE
_ V :B
'
<
Bo-
I),
?(/,/«,)
Bo-
4
B O-
ÖE npn
6C pnp
(a)
(b)
FIGURE 5 . 1 3 Circuit symbols for BJTs.
FIGURE 5 . 1 2 Large-signal model for thepnp transistor operating in the active mode.
It c a n easily b e seen from t h e a b o v e description that t h e c u r r e n t - v o l t a g e relationships of t h e pnp transistor will b e identical to t h o s e of t h e npn transistor e x c e p t that v
BE
replaced b y v . EB
has to be
A l s o , t h e large-signal a c t i v e - m o d e o p e r a t i o n of t h e pnp transistor c a n b e
m o d e l e d b y t h e circuit d e p i c t e d in F i g . 5.12. A s in t h e npn case, a n o t h e r v e r s i o n of this e q u i v a l e n t circuit is possible in w h i c h t h e current s o u r c e is r e p l a c e d with a currentcontrolled current s o u r c e a i . F E
Finally, w e n o t e that t h e pnp transistor c a n o p e r a t e in the
saturation m o d e in a m a n n e r a n a l o g o u s t o that d e s c r i b e d for t h e npn device. (a)
EXERCISES
FIGURE 5 . 1 4 Voltage polarities and current flow in transistors biased in the active mode.
Consider the model in Fig, 5 «12 applied in t h e case o£®pnp
transistor whose base is grounded, the emit-
ter is»fcd h\ A CIMIMANT-cufrem SOURCE thai supplies a 2 - m A currciu into the emitter terminal, and the
collector is connected to a - 1 0 - V dc supplv. Find the emitter voltage, t h e b a s e current, and the collector current if for this transistor /? = 5 0 and 7 = 10 S
A.
drawing c o n v e n t i o n b y w h i c h currents flow from t o p to b o t t o m , w e will a l w a y s d r a w pnp transistors in t h e m a n n e r s h o w n in F i g . 5.13 (i.e., with their emitters o n t o p ) . F i g u r e 5 T 4 s h o w s npn a n d pnp transistors b i a s e d to o p e r a t e in t h e active m o d e . It s h o u l d
Ans. 0.65D \ : 3'>.1 u.-\: 1.96 m \ 5.9
(b)
b e m e n t i o n e d in passing that the biasing arrangement shown, utilizing t w o d c voltage sources, - 1
For a pnp transistor having I = 1 0 ' A and / ? = 100, calculate v s
EB
for i = 1.5 A. c
is n o t a usual o n e a n d is u s e d h e r e m e r e l y to illustrate operation. Practical biasing s c h e m e s will b e presented in Section 5.5. Figure 5.14 also indicates the reference a n d actual directions
Ans. 0.64? Y
of current flow t h r o u g h o u t t h e transistor. O u r c o n v e n t i o n will b e to take t h e reference direction to c o i n c i d e with t h e n o r m a l direction of current flow, H e n c e , n o r m a l l y , w e should n o t encounter a n e g a t i v e v a l u e for i , i , o r i . E
5.2
CURRENT-VOLTAGE CHARACTERISTICS
B
c
T h e convenience of the circuit drawing convention that w e h a v e adopted should b e obvious from F i g . 5 . 1 4 . N o t e that c u r r e n t s flow f r o m t o p t o b o t t o m a n d that v o l t a g e s a r e h i g h e r at the t o p a n d l o w e r at t h e b o t t o m . T h e a r r o w h e a d o n t h e emitter also implies t h e polarity
5.2.1 Circuit Symbols and Conventions
of the emitter-base; v o l t a g e that should b e applied in order t o forward bias t h e e m i t t e r - b a s e
T h e p h y s i c a l structure u s e d thus far to e x p l a i n transistor o p e r a t i o n is rather c u m b e r s o m e to
junction. J u s t a g l a n c e at the circuit s y m b o l of the pnp transistor, for e x a m p l e , indicates that
e m p l o y in d r a w i n g t h e s c h e m a t i c of a multitransistor circuit. F o r t u n a t e l y , a very descriptive
w e should m a k e t h e emitter h i g h e r in v o l t a g e than t h e b a s e (by v ) in order t o c a u s e current EB
a n d c o n v e n i e n t circuit s y m b o l exists for t h e B J T . F i g u r e 5.13(a) s h o w s t h e s y m b o l for t h e
to flow i n t o t h e emitter ( d o w n w a r d ) . N o t e that t h e s y m b o l v
npn transistor; the pnp s y m b o l is given in F i g . 5.13(b). In b o t h s y m b o l s t h e emitter is distin-
the emitter ( E ) is h i g h e r than t h e b a s e ( B ) . T h u s for a pnp transistor operating in t h e active
g u i s h e d b y a n a r r o w h e a d . This distinction is i m p o r t a n t b e c a u s e , as w e h a v e seen i n t h e last
mode v
section, practical B J T s are n o t s y m m e t r i c d e v i c e s .
F r o m t h e d i s c u s s i o n of Section 5.1 it follows that an npn transistor w h o s e E B J is forward b i a s e d will o p e r a t e in the active m o d e as long as the collector voltage does not fall below that of the base by more than approximately 0.4 V. O t h e r w i s e , t h e transistor leaves the active m o d e a n d enters t h e saturation r e g i o n of operation.
T h e polarity of t h e d e v i c e — n p n o r pnp—is
i n d i c a t e d b y t h e direction of t h e a r r o w h e a d
o n t h e emitter. T h i s a r r o w h e a d p o i n t s in t h e direction of n o r m a l current flow in t h e emitter, w h i c h i s also t h e f o r w a r d direction of t h e b a s e - e m i t t e r j u n c t i o n . S i n c e w e h a v e a d o p t e d a
EB
EB
is positive, w h i l e in an npn transistor v
BE
means the voltage by which
is positive.
'
.
393
ER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
TABLE 5.2 i
5.2
Summary of the BJT Current-Voltage Relationships in the Active Mode
= Ie
c
CURRENT-VOLTAGE CHARACTERISTICS
The transistor in the circuit of Fig. 5.15(a) has B = 100 and exhibits a v
s
BE
of 0.7 V at i = 1 m A . c
Design, the circuit so that a current of 2 m A flows through the collector and a voltage of +5 V h
=
•
I C _
IF
V
fis)
—
—
appears at the collector.
6
{J)
=
'ß
/V
BE T
+ 15 V A
\e
Note: For the pnp transistor, replace v
BE
+ 15 V A
with v . EB
I
= 2 mA
c
"
c
= ai
E
ic = A s H
i
B
= (1 - a)i
h = 03 + l ) î '
1-a
=
E
h
C
B
8+1
= -
0.02 mA
=
P
— » 4 r
y /
+ VBE
h=Ic+ h = 2.02 n i A i £ R
kT V = thermal voltage = — s 25 mV at room temperature
E
T
-15 V
-15 V
In a parallel m a n n e r , the pnp transistor will operate i n t h e active m o d e if the EBJ is forward biased
and the collector
voltage
is not allowed
(a)
to rise above that of the base by more
than 0.4 V or so. O t h e r w i s e , t h e C B J b e c o m e s f o r w a r d b i a s e d , a n d the pnp transistor enters
(b)
FIGURE 5 . 1 5 Circuit for Example 5.1.
t h e saturation r e g i o n of operation. F o r easy reference, w e present in T a b l e 5.2 a s u m m a r y of t h e B J T current-voltage relationships in t h e active m o d e of operation. N o t e that for simplicity w e u s e a a n d ¡5 rather than a
F
Soiufion Refer to Fig. 5.15(b). W e note at the outset that since w e are required to design for V = +5 V, the
a n d pV
C
CBJ will be reverse biased and the B I T will be operating in the active mode. T o obtain a voltage The Constant n
In t h e diode equation (Chapter 3) w e used a constant n in the exponential
and m e n t i o n e d that its v a l u e is b e t w e e n 1 a n d 2. F o r m o d e r n b i p o l a r j u n c t i o n transistors the
V = +5 V the voltage drop across R must b e 15 - 5 = 10 V. Now, since I = 2 m A , the value of C
R
C
C
c
should be selected according to
c o n s t a n t n is close t o unity e x c e p t i n special c a s e s : (1) at h i g h currents (i.e., h i g h relative to the n o r m a l current r a n g e of t h e particular transistor) t h e i - v c
for n that is c l o s e t o 2 , a n d (2) at l o w currents t h e i -v B
BE
B E
CBO
)
=
10 V 2 mA
5 kQ
relationship s h o w s a v a l u e for n of
a p p r o x i m a t e l y 2. N o t e that for o u r p u r p o s e s w e shall a s s u m e a l w a y s that T h e Collector-Base Reverse Current (/
Rr
relationship exhibits a value Since v
n=l.
BE
= 0.7 V at i = 1 m A , the value of v c
V
In o u r discussion of current flow in transis-
tors w e i g n o r e d t h e small reverse currents carried b y thermally generated minority carriers. A l t h o u g h s u c h currents c a n b e safely n e g l e c t e d in m o d e r n transistors, t h e reverse current across t h e c o l l e c t o r - b a s e j u n c t i o n deserves s o m e m e n t i o n . This current, denoted I , CB0
at i = 2 m A is
BE
BE
c
= 0.7 + y l n
= 0.717 V
r
Since the base is at 0 V, the emitter voltage should b e
is the
V
E
= -0.717 V
reverse current flowing from collector to b a s e with t h e emitter open-circuited (hence the subscript O). This current is usually in t h e n a n o a m p e r e r a n g e , a value that is m a n y times h i g h e r than its theoretically predicted value. A s with t h e d i o d e reverse current, I
CB0
substantial l e a k a g e c o m p o n e n t , and its v a l u e is d e p e n d e n t o n v . I CB
CB0
For/? = 1 0 0 , a = 1 0 0 / 1 0 1 = 0.99. Thus the emitter current should b e
contains a
. _2_
d e p e n d s strongly on
a
~ 0.99
2.02 m A
4
t e m p e r a t u r e , a p p r o x i m a t e l y doubling for every 1 0 ° C rise.
Now the value required for R can be determined from E
V
E
-(-15)
R* 4
The temperature coefficient of I leakage component.
CB0
is different from that of I because I s
CB0
contains a substantial
- 0 . 7 1 7 + 15 2.02
7.07 k Q
396
.
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
5.2
(BJTs)
CURRENT-VOLTAGE
CHARACTERISTICS
j This completes the design. W e should note, however, that the calculations above were made with a 1 degree of accuracy that is Usually neither necessary nor justified in practice in view, for instance, of ! the expected tolerances of component values. Nevertheless, w e chose to do the design precisely in I order to illustrate the various steps involved.
5.10 Tn the circuit shown in Fig. E5.10, the voltage at the emitter was measured and found to be - 0 . 7 V . l f • ••y- / > - 50, I hid //,-. /<-. and V .
FIGURE 5 . 1 6 The i -v transistor. c
c
BE
characteristic for an npn
5.2.2 Graphical Representation of Transistor Characteristics
5 kil.
-oV
It is s o m e t i m e s useful to describe the transistor i—v characteristics graphically. F i g u r e 5.16 shows the i -v characteristic, w h i c h is the e x p o n e n t i a l relationship c
BE
t
V
j
i
c
=
/V
BE T
he
w h i c h is i d e n t i c a l ( e x c e p t for t h e v a l u e of c o n s t a n t n) to t h e d i o d e i-v r e l a t i o n s h i p . T h e i -v a n d i -v c h a r a c t e r i s t i c s are also e x p o n e n t i a l b u t w i t h different s c a l e c u r r e n t s : I /a for i , a n d I /f3 for i . S i n c e t h e c o n s t a n t of t h e e x p o n e n t i a l c h a r a c t e r i s t i c , l/V , is quite h i g h (—40), t h e c u r v e rises v e r y s h a r p l y . F o r v s m a l l e r t h a n a b o u t 0.5 V , t h e current is n e g l i g i b l y s m a l l . A l s o , o v e r m o s t of t h e n o r m a l c u r r e n t r a n g e v lies in t h e range of 0.6 V to 0.8 V . I n p e r f o r m i n g r a p i d first-order d c c a l c u l a t i o n s w e n o r m a l l y will a s s u m e that V — 0.7 V , w h i c h is similar t o t h e a p p r o a c h u s e d i n t h e a n a l y s i s of d i o d e circuits ( C h a p t e r 3 ) . F o r a pnp transistor, t h e i - v c h a r a c t e r i s t i c w i l l l o o k i d e n t i c a l to that of F i g . 5 . 1 6 w i t h v r e p l a c e d w i t h v .
-oVt
E
BE
B
s
lOkii
BE
E
s
B
T
BE
5
BE
|
l
,
v
BE
FIGURE E5.10
c
Ans. u."3 in \ : I s . : p. A; 0.91 m \ : -5.45 \
BE
5.11 In the circuit shown in Fig. E 5 . 1 1 . measurement indicates V to b e +1.0 V and V to be +1.7 V. What arc a and p for this transistor? What voltage V do you expect at the collector? B
c
L
E B
EB
A s i n silicon d i o d e s , t h e v o l t a g e across t h e e m i t t e r - b a s e j u n c t i o n decreases b y about 2 m V for e a c h rise of 1°C in temperature, p r o v i d e d that the j u n c t i o n is operating at a constant current. F i g u r e 5.17 illustrates this t e m p e r a t u r e d e p e n d e n c e b y depicting ic~v curves at three different t e m p e r a t u r e s for an npn transistor. BE
The C o m m o n - B a s e Characteristics O n e w a y to describe t h e operation of a bipolar transistor is to p l o t i v e r s u s v for various values of i . W e h a v e already e n c o u n t e r e d o n e such graph, in F i g . 5.9, w h i c h w e u s e d to introduce t h e saturation m o d e of operation. A c o n ceptual e x p e r i m e n t a l setup for m e a s u r i n g such characteristics is s h o w n in F i g . 5.18(a). Observe that in these m e a s u r e m e n t s the base voltage is held constant, here at ground potential, and thus t h e b a s e serves as a c o m m o n terminal b e t w e e n t h e input a n d output ports. C o n s e quently, the resulting set of characteristics, s h o w n in Fig. 5.18(b), are k n o w n as c o m m o n - b a s e characteristics.
: s kii
V„o-
TO
<
c
V
r
CB
E
100 kfi :5kiî The i ~v characteristic is the BJT's counterpart of the i -v characteristic of the enhancement MOSFET. They share an important attribute: In both cases the voltage has to exceed a "threshold" for the device to conduct appreciably. In the case of the MOSFET, there is a formal threshold voltage, V„ which lies typically in the range of 0.5 V to 1.0 V. For the BJT, there is an "apparent threshold" of approximately 0.5 V. The i -v characteristic of the MOSFET is parabolic and thus is less steep than the i -v characteristic of the BJT. This difference has a direct and significant implication on the value of transconductance g realized with each device. c
—10
V
Ans. 0.994; 1 6 5 ; - 1 . 7 5 V
FIGURE ES. 11
BE
D
D
c
BE
m
cs
GS
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
5.2
CURRENT-VOLTAGE CHARACTERISTICS
.'_
3 9 9
Finally, turning to t h e saturation region, t h e E b e r s - M o l l e q u a t i o n s c a n b e u s e d t o obtain the following e x p r e s s i o n for t h e i - v c
i
c
C B
c u r v e i n t h e saturation r e g i o n (for i = I ), E
= aI F
- i l l - - a )e
E
E
V B c / V T
(5.35)
p
W e c a n u s e this e q u a t i o n to d e t e r m i n e t h e v a l u e of v
at w h i c h i is r e d u c e d t o z e r o . R e c a l l
BC
c
ing that t h e C B J is m u c h larger than t h e E B J , t h e f o r w a r d - v o l t a g e d r o p v
will b e s m a l l e r
BC
than v
BE
CE
FIGURE 5 . 1 7 Effect of temperature on the i -v characteristic. At a constant emitter current (broken line), v changes by - 2 m V / ° C . c
VBE
resulting i n a collector-emitter v o l t a g e , v , of 0.1 V to 0.3 V in saturation.
BE
BE
5.12 Consider a pnp transistor with v, = 0.7 V at i = l mA. Let lite base be grounded, the emitter be fed by a c . ; t ' . ^ m A i ' ^ n s t a n t r C u r r e n t source, and the collector be connect.ed.to a - 5 - V supply through a l - k £ i re&istancmvilAeJjempefature increases by 30°C, find the changes in emitter and collector voltages. Neglect I he effect o f / , . :B
E
Ans. - 6 0 raV: 0 V. 5.13 F i n d t h e value, o § % « 5 at which / . of an npn transistor operated in the C B configuration with 7/. = 1 m A is reduced (a) to half its active-mode value and (b) to zero. Assume a,. = 1 and a = 0.1. The value of V was measured for v = 0 (see measuring setup in Fig. 5.18(a)] and found lo be 0.70 V. Repeat (a) and (b) for cx = 0 . 0 1 . (
K
BE
CB
R
Ans.-0.628 V; - 0 . 6 4 5 V: - 0 . 5 6 8 V; - 0 . 5 8 5 V.
5.2.3 Dependence of i on the Collector Voltage-The Early Effect c
W h e n operated in t h e active region, practical B J T s show s o m e d e p e n d e n c e of t h e collector current on the collector voltage, with t h e result that their « - w c
C 5
characteristics are n o t per
fectly horizontal straight lines. T o see this d e p e n d e n c e m o r e clearly, consider t h e conceptual circuit s h o w n in F i g . 5.19(a). T h e transistor is c o n n e c t e d in t h e c o m m o n - e m i t t e r configura tion; that is, h e r e t h e emitter serves as a c o m m o n terminal b e t w e e n t h e input and output ports. T h e v o l t a g e V
c a n b e set to a n y desired v a l u e b y adjusting t h e d c source c o n n e c t e d
BE
b e t w e e n b a s e a n d emitter. A t e a c h v a l u e of V , t h e corresponding i -v E BE
F I G U R E 5 . 1 8 The
I -VCB C
characteristics of an npn transistor.
c
C
characteristic c u r v e
can b e m e a s u r e d point-by-point by varying t h e d c source c o n n e c t e d b e t w e e n collector a n d emitter a n d m e a s u r i n g t h e corresponding collector current. T h e result is the family of i - v c
In t h e active r e g i o n of operation, o b t a i n e d for v
CB
> - 0 . 4 V or so, t h e i - v c
C B
curves
d e v i a t e from o u r e x p e c t a t i o n s in t w o w a y s . First, t h e c u r v e s a r e n o t horizontal straight lines b u t s h o w a small positive slope, indicating that i d e p e n d s slightly o n v c
CB
in t h e active m o d e .
W e shall discuss this p h e n o m e n o n shortly. S e c o n d , at relatively large values of v ,
the
CB
C E
characteristic curves s h o w n in F i g . 5.19(b) and k n o w n as c o m m o n - e m i t t e r characteristics. A t l o w v a l u e s of v , CE
as t h e collector v o l t a g e g o e s b e l o w that of t h e b a s e b y m o r e than
0.4 V , t h e c o l l e c t o r - b a s e j u n c t i o n b e c o m e s forward b i a s e d a n d t h e transistor l e a v e s t h e active m o d e a n d enters t h e saturation m o d e . W e shall shortly l o o k at t h e details of t h e i - v c
C E
collector current s h o w s a rapid i n c r e a s e , w h i c h is a b r e a k d o w n p h e n o m e n o n that w e will
curves in t h e saturation r e g i o n . A t this t i m e , h o w e v e r , w e w i s h to e x a m i n e t h e characteristic
consider at a later stage.
curves in t h e active r e g i o n in detail. W e o b s e r v e that t h e characteristic c u r v e s , t h o u g h still
A s indicated in F i g . 5.18(b), e a c h of t h e characteristic curves intersects t h e vertical axis
straight lines, h a v e finite slope. In fact, w h e n extrapolated, t h e characteristic lines m e e t at a
at a current level e q u a l t o aI , w h e r e I is t h e constant emitter current at w h i c h t h e particular
point on t h e n e g a t i v e v
c u r v e is m e a s u r e d . T h e resulting v a l u e of a is a total o r l a r g e - s i g n a l a; that is, a -
i /i ,
ter for t h e particular B J T , with typical values in t h e r a n g e of 5 0 V t o 100 V . It is called t h e
w h e r e i a n d i d e n o t e total collector a n d emitter currents, respectively. H e r e w e recall that
E a r l y v o l t a g e , after J. M . Early, t h e engineering scientist w h o first studied this p h e n o m e n o n .
E
c
E
c
E
E
a is appropriately called t h e c o m m o n - b a s e c u r r e n t gain. A n i n c r e m e n t a l o r s m a l l - s i g n a l a
axis, at v
CE
CE
= -V .
A t a given v a l u e of v , increasing v
A
BE
CE
T h e v o l t a g e V , a positive n u m b e r , is a p a r a m e A
increases t h e reverse-bias voltage o n t h e c o l l e c t o r -
can b e d e t e r m i n e d b y m e a s u r i n g t h e c h a n g e in i , Az ,-. o b t a i n e d as a result of c h a n g i n g i by
base j u n c t i o n a n d t h u s increases t h e w i d t h of t h e depletion r e g i o n of this j u n c t i o n (refer to
an i n c r e m e n t Ai ,
c
c
E
as
Fig. 5.3). This in turn results in a d e c r e a s e in t h e effective b a s e w i d t h W. Recalling that I is
indicated in F i g . 5.18(b). U s u a l l y , t h e v a l u e s of i n c r e m e n t a l a n d total a differ slightly, b u t
inversely p r o p o r t i o n a l to W (Eq. 5.4), w e s e e that I will increase and that i increases p r o
w e shall n o t m a k e a distinction b e t w e e n t h e t w o in this b o o k .
portionally. T h i s is t h e Early effect.
E
a = Ai /Ai . c
E
This m e a s u r e m e n t is usually m a d e at a c o n s t a n t v , CB
s
s
c
CHAPTER 5
BIPOLAR JUNCTION
TRANSISTORS
5.2
(BJTS)
CURRENT-VOLTAGE
CHARACTERISTICS
Saturation region
-OC
+
4S
\i
E
(a) (a)
(b)
FIGURE 5 . 2 0 Large-signal equivalent-circuit models of an npn BJT operating in the active mode in the common-emitter configuration. -V
0
A
v
CE
(b)
differ only in h o w the control function of the transistor is expressed: In the circuit of Fig. 5.20(a), voltage v controls the collector current source, while in the circuit of Fig. 5.20(b), the b a s e current i is the control parameter for the current source fii . H e r e w e note that /3 represents the ideal current gain (i.e., w h e n r is not present) of the c o m m o n - e m i t t e r configuration, which is the reason for its n a m e , the c o m m o n - e m i t t e r current gain. BE
B
FIGURE 5 . 1 9 (a) Conceptual circuit for measuring the i -v characteristics of a practical BJT. c
CE
characteristics of the BJT. (b) The
i -v c
CE
B
0
T h e linear d e p e n d e n c e of i o n v can b e a c c o u n t e d for b y a s s u m i n g that I r e m a i n s constant a n d including the factor ( 1 + v /V ) i n the e q u a t i o n for i as follows: c
CE
s
CE
A
c
VBE/VT
Ie
il
s
+
^
(5.36) 5.14 Find the output resistance of a BJT for which V = 100 V at /< = 0 . 1 , 1. and 10 raA. A
T h e n o n z e r o slope of the i -VcE straight lines indicates that t h e o u t p u t r e s i s t a n c e looking into t h e collector is n o t infinite. Rather, it is finite and defined b y c
Ans. i \ l i > : IH()ki2: luk<> 5.15 Consider the circuit in Fig. 5.19(a). At V = I V, V is adjusted to yield a collector current of 1 mA. Then, while V is kept constant, V is raised to 11 V. Find the new value oi'I . For this transistor, V, = 100 V. cr
-t
di dv
Kr
(5.37)
c
CE
BE
cr
c
Ans. I.I n i . \
v = constant. BE
U s i n g E q . (5.36) w e can s h o w that
. _ v + v A
CE
(5.38)
0
Ic w h e r e I and V c
are the coordinates of the p o i n t at w h i c h the B J T is operating o n t h e partic-
CE
5.2.4 The Common-Emitter Characteristics A n alternative w a y of expressing the transistor c o m m o n - e m i t t e r characteristics is illustrated in Fig. 5.21. H e r e the base current i rather than the b a s e - e m i t t e r voltage v is u s e d as a parameter. That is, each i -v curve is m e a s u r e d with the b a s e fed with a constant current I . T h e resulting characteristics l o o k similar to those in Fig. 5.19 except that here w e show the breakd o w n p h e n o m e n o n , w h i c h w e shall discuss shortly. W e should also mention that although it is not obvious from the graphs, the slope of the curves in the active region of operation differs from the corresponding slope in Fig. 5.19. This, however, is a rather subtle point and b e y o n d our interest at this m o m e n t . B
ular i -v E c
c u r v e (i.e., the curve obtained for v
C
= V ). Alternatively, w e can write
BE
BE
c
(5.38a)
j,
O
w h e r e I' is t h e v a l u e of the collector current w i t h the E a r l y effect neglected; that is, c
I'c
(5.38b)
he
It is rarely necessary t o include the d e p e n d e n c e of i o n v in d c bias design and analysis. H o w e v e r , t h e finite output resistance r c a n h a v e a significant effect o n t h e gain of transistor amplifiers, a s will b e seen in later sections a n d chapters. c
CE
B
T h e output resistance r can be included in the circuit m o d e l of the transistor. This is illustrated in Fig. 5.20, w h e r e w e show large-signal circuit m o d e l s of a c o m m o n - e m i t t e r npn transistor operating in the active mode. Observe that diode D m o d e l s the exponential dependence of i o n v and thus has a scale current I = I /f3. Also note that the t w o models 0
B
B
BE
SB
s
BE
CE
B
The Common-Emitter Current Gain ¡3 A n important transistor parameter is the c o m m o n emitter current gain / 3 or s i m p l y ¡3. T h u s far w e h a v e defined ¡3 as t h e ratio of t h e total current in the collector t o the total current i n the b a s e , a n d w e h a v e a s s u m e d that ¡3 is constant for a g i v e n transistor, i n d e p e n d e n t of the operating conditions. I n t h e following w e e x a m i n e those t w o p o i n t s in s o m e detail. C o n s i d e r a transistor operating in t h e active region at t h e point labeled Q in Fig. 5 . 2 1 , that is, at a collector current I , a b a s e current I , and a collector-emitter voltage V . T h e F
CQ
BQ
CEQ
4 0
402
. IAPTER 5 B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
0
5.2
CURRENT-VOLTAGE CHARACTERISTICS
4^
IR
1 (a)
10
10
2
3
4
5
10 10 10 (1 mA) (10 mA) (100 mA)
W (M) C
(b) FIGURE 5 . 2 2 Typical dependence of j3 on I and on temperature in a modern integrated-circuit npn silicon transistor intended for operation around 1 mA. c
FIGURE 5 . 2 1 Common-emitter characteristics. Note that the horizontal scale is expanded around the origin to show the saturation region in some detail. ratio of the collector current to the base current is the large-signal o r d c ¡3, (5.39)
Pdc~
T
BQ
w h i c h is the ¡3 w e h a v e b e e n using in our description of transistor operation. It is c o m m o n l y referred to on the m a n u f a c t u r e r ' s data sheets as h , a s y m b o l that c o m e s from the u s e of the hybrid, or h, two-port parameters to characterize transistor operation (see A p p e n d i x B ) . O n e can define another /? based on incremental or small-signal quantities. Referring to Fig. 5.21 w e see that w h i l e k e e p i n g v constant at the v a l u e V , c h a n g i n g i from I to iJ + Ai ) results in i increasing from I to (I + Ai ). Thus w e can define the i n c r e m e n t a l o r a c /?, FE
CE
c
p\c>
a
CQ
CEQ
CQ
B
BQ
BQ
B
c
s
Ai
(5.40)
r
Ai
K
T h e magnitudes of / 3 and j3ic differ, typically by approximately 1 0 % to 2 0 % . In this b o o k w e shall not normally m a k e a distinction b e t w e e n the t w o . Finally, w e should mention that the small-signal ¡3 or j8 is also k n o w n by the alternate symbol h . B e c a u s e the small-signal ¡5 or h is defined and measured at a constant v —that is, with a zero signal c o m p o n e n t between collector and emitter—it is k n o w n as the s h o r t - c i r c u i t c o m m o n - e m i t t e r current gain. T h e value of ¡3 depends on the current at which the transistor is operating, and the relationship takes the form shown in Fig. 5.22. T h e physical processes that give rise to this relationship are b e y o n d the scope of this book. Figure 5.22 also shows the temperature dependence of ¡3. ac
ac
0
0.1 ' 0 . 2
0.3 0.4 0 . 5 . 0 . 6
0.7
0.8
% £
(v)
fe
fe
CE
FIGURE 5 . 2 3 An expanded view of the common-emitter characteristics in the saturation region.
by the circuit designer, a saturated transistor is said to b e operating at a f o r c e d ¡3 given by o
The Saturation Voltage V a n d S a t u r a t i o n R e s i s t a n c e ff A n e x p a n d e d view of the c o m m o n - e m i t t e r characteristics in the saturation r e g i o n is s h o w n in Fig. 5.23. T h e fact that the curves are " b u n c h e d " together in the saturation r e g i o n implies that the incremental [3 is l o w e r t h e r e t h a n in the active r e g i o n . A p o s s i b l e o p e r a t i n g p o i n t in the saturation region is that l a b e l e d X . I t is c h a r a c t e r i z e d b y a b a s e c u r r e n t I , a c o l l e c t o r c u r r e n t 7 , and a c o l l e c t o r - e m i t t e r voltage V . N o t e that 7 < J3 I . Since the value of 7 is established CEsat
__ 7 Csat
C s a t
C s a t
F
B
C s a t
(5.41)
j
1
B
CEsat
B
CEsat
Pforced Thus,
Abrced
<
(5.42)
PV
T h e ratio of [3 to j 8 is k n o w n as the o v e r d r i v e factor. T h e greater the overdrive factor, the d e e p e r the transistor is driven into saturation a n d the l o w e r V becomes. F
f o r c e d
C £ s a t
CHAPTER 5
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTs)
T h e i ~v E c
C
5.2
curves in saturation are rather steep, indicating that the saturated transistor
exhibits a l o w collector-to-emitter resistance ^
C £ s a t
series with a battery V
. T h u s the saturation voltage V
CEoS
d CE
(5.43)
dir
c
CE
the tangent at operating point X o f slope l / # sects the % - a x i s at a voltage V £
Typically, V
falls in t h e r a n g e of 0.1 V to 0.3 V . F o r m a n y applications t h e e v e n simpler
C £ s a t
El
istics g o right t h r o u g h t h e origin of the i ~v D
E
plane.
DS
axis at
It is interesting and instructive to use the Ebers-Moll m o d e l to derive analytical expressions
curves. W e have also shown in Fig. 5.24(b)
for the characteristics of t h e saturated transistor. T o w a r d that end w e u s e E q s . (5.28) and
CE
a value c o m m o n to all the i -v
R
(5-44)
+ ^Csat^CEsat
small, m a k e s the B J T less attractive as a switch t h a n the M O S F E T , w h o s e i ~'v ,s character-
c h a r a c t e r i s t i c c u r v e s of t h e s a t u r a t e d t r a n s i s -
C
tor shown in Fig. 5.24(a). I t is interesting to n o t e that the curve intersects the v VVln (\/a ),
VcEoff
m o d e l s h o w n in Fig. 5.24(d) suffices. T h e offset v o l t a g e o f a saturated transistor, t h o u g h
r a n g e s from a few o h m s to a few tens of o h m s .
F i g u r e 5.24(b) s h o w s o n e of the i -v E c
=
v
_
CEsat
can be found from
C E s a t
, ^Cfisat
Typically, R
CURRENT-VOLTAGE CHARACTERISTICS
C £ s a t
. W h e n extrapolated, the tangent inter-
, typically approximately 0.1 V. It follows that the
(5.27), substitute i =I , B
and neglect the s m a l l terms that d o not include e x p o n e n t i a l s ; thus,
B
i -v
CEoB
c
CE
U
h
/V
BE T
V
h
/V
BC T
(5.45)
characteristic of a saturated transistor can be approximately represented b y the equivalent circuit shown in Fig. 5.24(c). A t the collector side, the transistor is represented b y a resistance R
CEi!ii
in
/v
F
V
h
r
C
/V
BC T
(5.46)
he hsut i l
Dividing Eq. (5.46) b y E q . (5.45) and writing v
- v +
(
v /V
BE
v
BC
CE
enables us to express i in the form
CE
c
>
1 *
T
e
(5.47)
(PFIB) PR) This is the equation of the i -v c
CE
characteristic curve obtained when the base is driven with a
constant current I . Figure 5.25 shows a typical plot of the normalized collector current B
i /(P l ), c
F B
/^forced ï i ~ßE~
1.0 0.9 0.8 0.7 (b)
(a)
0.6 ^
V ]n(ÊL
- Slope = 10 V -
T
\ß*.
0.5
-o C
Bo-
- = -
M -
Bo— +
0.4 0.3
\
VBE
V,
= - n . - V
- ^ T 0 2\
o-
Ï
ß
R
F
=
100
0.2
*— • — •— E
a =0.1
V,
I
-*
0.1
—• E
iooA
v'
(d)
(c)
1 1
^ 1
0
v
V ln
CEo«
1
1 200
I
1
300
400
v (mV) CE
! 1
T
FIGURE 5 . 2 4 (a) An npn transistor operated in saturation mode with a constant base current I . (b) The ic- cEcharacteristic curve corresponding to i = I . The curve can be approximated by a straight line of slope 1/RcEsm( ) Equivalent-Circuit representation of the saturated transistor, (d) A simplified equivalentcircuit model of the saturated transistor. B
50 mV
v
B
c
B
FIGURE 5 . 2 5 Plot of the normalized i versus v for an npn transistor with fi = 100 and a = 0.1. This is a plot of Eq. (5.47), which is derived using the Ebers-Moll model. c
CE
F
R
4 0 5
4 0 6
«SA
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
which is equal to (B /B ), So!ce6
5.3
(BJTs)
versus v . A s shown, the curve can be approximated by a straight
F
CE
line coincident with the tangent at the point B /B tmxi
= 0 . 5 . It can b e shown that this tangent
F
effect. A circuit arrangement to prevent E B J b r e a k d o w n in I C amplifiers will b e discussed in Chapter 9. Transistor b r e a k d o w n and the m a x i m u m allowable p o w e r dissipation a r e i m p o r t a n t parameters in t h e design of p o w e r amplifiers (Chapter 14).
-
has a slope of approximately 10 V , independent of the transistor parameters. Thus, ^c£sat = 1 / 1 0 / V B
THE BJT AS AN AMPLIFIER A N D AS A SWITCH
.
(5.48)
Other important parameters of the n o r m a l i z e d plot are indicated in F i g . 5.25. Finally, w e can obtain an expression for y
C £ s a t
by substituting i = 7 c
y
_
y
V c E s a %
l
1+
n
C s a t
= /3 J tmc
and v
B
CE
=V
CEs3t
in E q . (5.47), 5.18 What is the output voltage of the circuit in Fig. E5.18 if the transistor BV
(forced + D / &
BC0
( 5
l - ( / W & )
T
-
= 70 V ?
4 9 )
+ I11 \
EXERCISES 5.16yAmsnpn transistor characterized by /}, = 100 a n d « s = ; 0 ; l is operated in saturation with a constant basecurrent of 0.1 m A and a forced B of 10. F i n d t h e v a l u e s of V at i - 0. R ^. and V . c U s e ' 4 h e latter two figures to obtain an approximate value for [i.e., using the equivalent circuit model of Fig. 5.24(c)]. • F i n d a more accurate value for V --,.„ using Eq. (5.49), and compare results. Repeat for a y3 a of 201 CE
(
CL
rM
(7
:
!
force
Ans.58mV; 10 £2: 120 m V ; 130 mV and 118 m V ; 140raVand 1 3 7 m V
5.17 Measurements made on a BIT" operated in saturation with a constant base-current drive provide the „ following data: at i . = 5 m A . v, . = 170 mV; at i = 2 mA, v = 1 1 0 mV. What are the values of die offset voltage V . and saturation resistance R -sm. ' situation? Ans. 'i||,\::iiii (
7
c
Ml
FIGURE E5.18
a :
m
c/
l n
s
a
Ans.-60 V
7
5.2.6 Summary
5.2.5 Transistor Breakdown
W e c o n c l u d e o u r study of t h e current-voltage characteristics of the B J T w i t h a s u m m a r y of
T h e m a x i m u m v o l t a g e s that c a n b e applied to a B J T are limited b y t h e E B J a n d C B J break
important results in T a b l e 5 . 3 .
d o w n effects that follow t h e a v a l a n c h e multiplication m e c h a n i s m d e s c r i b e d in Section 3.7.4. C o n s i d e r first t h e c o m m o n - b a s e configuration. T h e i -v B c
C
characteristics in F i g . 5.18(b)
indicate that for i = 0 (i.e., with t h e emitter open-circuited) t h e collector-base junction breaks E
7
d o w n at a voltage denoted by BV .
F o r i > 0, b r e a k d o w n occurs at voltages smaller than
CB0
BV . CB0
T y p i c a l l y , BV
CB0
E
F ? 5.3 THE BJT AS AN AMPLIFIER AND AS A SWITCH
is greater than 5 0 V .
N e x t consider t h e corrrmon-emitter characteristics of F i g . 5 . 2 1 , w h i c h s h o w b r e a k d o w n
H a v i n g studied t h e t e r m i n a l characteristics of t h e B J T , w e are n o w r e a d y t o c o n s i d e r its t w o 6
Here, although b r e a k d o w n is still of t h e avalanche type, the
major areas of application: as a signal a m p l i f i e r , and as a digital-circuit switch. T h e b a s i s
effects on t h e characteristics are m o r e c o m p l e x than i n t h e c o m m o n - b a s e configuration. W e
for t h e amplifier a p p l i c a t i o n is t h e fact that w h e n t h e B J T is o p e r a t e d in t h e active m o d e , it
occurring at a voltage BV . CE0
will n o t explain' these in detail; it is sufficient to p o i n t o u t that typically BV
CE0
BV . CB0
Ojt-fransistor data sheets, BV
CE0
is about half
is s o m e t i m e s referred to as t h e sustaining voltage
acts as a v o l t a g e - c o n t r o l l e d current s o u r c e : C h a n g e s i n t h e b a s e - e m i t t e r v o l t a g e v
BE
give
rise to c h a n g e s i n t h e c o l l e c t o r current i . T h u s i n t h e active m o d e t h e B J T c a n b e u s e d t o c
i m p l e m e n t a t r a n s c o n d u c t a n c e amplifier (see S e c t i o n 1.5). V o l t a g e amplification c a n b e B r e a k d o w n of t h e C B J in either the c o m m o n - b a s e or c o m m o n - e m i t t e r configuration is not destructive as long as the p o w e r dissipation in t h e device is kept within safe limits. This, h o w
obtained s i m p l y b y p a s s i n g t h e collector c u r r e n t t h r o u g h a r e s i s t a n c e R , as will b e seen c
shortly.
ever, is n o t t h e case with t h e b r e a k d o w n of the e m i t t e r - b a s e junction. T h e E B J breaks d o w n in an avalanche m a n n e r at a voltage BV much EBO
smaller than BV . CB0
Typically, BV
EB0
is in the
range of 6 V to 8 V , and the b r e a k d o w n is destructive in t h e sense that the /J of the transistor is permanently reduced. This does not prevent u s e of t h e E B J as a zener diode t o generate refer ence voltages in I C design. In such applications o n e is n o t c o n c e r n e d with the /j-degradation
6
An introduction to amplifiers from an external-terminals point of view is presented in Sections 1.4 and 1.5. It would be helpful for readers who are not familiar with basic amplifier concepts to review this material before proceeding with the study of BJT amplifiers.
408
>
"•"Os
CHAPTER 5
TABLE 5.3
BIPOLAR JUNCTION TRANSISTORS
(BJTs)
5.3
THE BJT AS AN AMPLIFIER A N D AS A SWITCH
4 0 9
Ebers-Moll M o d e l S u m m a r y of t h e BJT Current-Voltage Characteristics
Circuit Symbol a n d Directions of Current Flow
E o
npn Transistor
pnp Transistor
C
*DE^
E p
Q
a
B o
B o-
a
'ߣ =
hs(
e
-
e
*z>c = hd BE>VBE™>
%s> V
^ S £ o n = 0.5 V
; V
EBon
2. CBJ Reversed Biased
"acSV
Ä C o n
=> v
Typically, v
= 0.7 V
BE
DE
Fh
; V
v ïV ;
= 0.4V
5 C o n
CB
=> v
> 0.3 V
CE
V
CBon
-
EC
he /op
= 0AV
CBon
> 0.3 V
a
=
Rhc
«f a
-
-1)
E
DC -
a
= 0.7 V
EB
= h (e
l
- 1)
= 0.5 V
EBon
kc\
1)
E
Typically, v
(he)
l
R DC
Operation in t h e Active M o d e (for Amplifier Application)
V
A
l
R DC
E
B
Conditions: 1. EB J Forward Biased
(ISE)
Bo
VB
VC
V
7sc(e SC
-1)
J
h
CBJ Area EBJ Area
=
f f
Operation in t h e Saturation M o d e
Conditions: Current-Voltage Relationships
ir = he
k = he k = Wß
«
i
<=> i
= i /a
F
r
1. EBJ Forward-Biased
BE > V
B£on
; V
BEm
Typically, v
BE
k = ßk r
V
2. CBJ Forward-Biased
= ai
v >V ;V BC
BCoB
Large-Signal Equivalent-Circuit Model (Including the Early Effect)
= 0.7-0.8 V
l-a
EB
= 0.7-0.8 V
v >V ;V CB
= 0.5-0.6 V
CBon
= QAV
CBon
Typically, v
CB
= 0.5-0.6 V
^ % c = I W = 0.1-0.2 V
ß+1 Currents
Bo-
Venon = 0-5 V
Typically, v
= 0AV
BCon
BC
ß =
V
VEB > EBov
F
Typically, v •
= 0.5 V
PtOTCtih
ßf
-OC
Abrced - ß f >
- = Overdrive factor
/^forced
+
Equivalent Circuits
VBESL
t>CE
ß>
t/ß)
+
ß
VB E
h
O B
Si
CEsnt
0.7 V
Bo-
E
R
:
-^W\r-
Q
-OC
.V,
• 0.1 V
-OC
0.7 V B o
/V
fh~\
"BE T
V
Is\
E B
/
V
"ECoiï
= 0.1 V
e
c
V
V
=I e ' ^ [ l s
-^
+
ir = he
E B
AP
a
= V /(I e A
s
V
,
T ( ,
V
EC
For
/V
FR T
R
T
)
V /(I e A
1+
V
(^forced
1+T
V /V
r
/
s
)
piforced
0 /2: F
ECsat
i — V W — — -OC
T
V i
v
fl
C£sat
= 1/10J3 7 F
B
CHAPTER 5
5.3
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
S i n c e w e a r e particularly interested in linear amplification, w e will h a v e to d e v i s e a w a y to a c h i e v e it in t h e face of t h e highly n o n l i n e a r b e h a v i o r of t h e transistor, n a m e l y , that t h e collector current i is exponentially related to v . W e w i l l u s e t h e a p p r o a c h d e s c r i b e d in g e n e r a l t e r m s in Section 1.4. Specifically, w e w i l l b i a s t h e t r a n s i s t o r to operate at a d c b a s e - e m i t t e r v o l t a g e V and a c o r r e s p o n d i n g dc c o l l e c t o r c u r r e n t I , T h e n w e will s u p e r i m p o s e t h e signal to b e amplified, v , o n t h e d c v o l t a g e V . B y k e e p i n g t h e a m p l i t u d e of t h e signal v small, w e will b e able to c o n s t r a i n t h e t r a n s i s t o r to o p e r a t e o n a short, a l m o s t linear s e g m e n t of t h e i -v characteristic; t h u s , t h e c h a n g e in c o l l e c t o r current, i , will b e linearly related to v . W e will study t h e s m a l l - s i g n a l o p e r a t i o n of t h e B J T later in this section a n d in greater detail in Section 5 . 5 . First, h o w e v e r , w e will l o o k at thé " b i g p i c t u r e " : W e will study t h e total or large-signal o p e r a t i o n of a B J T amplifier. F r o m the transfer characteristic of t h e circuit, w e will b e able to see clearly t h e r e g i o n o v e r w h i c h t h e circuit c a n b e o p e r a t e d as a linear amplifier. W e also will b e able to see h o w the B J T c a n b e e m p l o y e d as a switch. c
Cutoff - H Active mode
BE
BE
T H E BJT AS A N A M P L I F I E R A N D A S A S W I T C H
Saturation •
C
he
BE
be
c
c
BE
be
5.3.1 Large-Signal Operation-The Transfer Characteristic F i g u r e 5.26(a) s h o w s the basic structure (a skeleton) of t h e m o s t c o m m o n l y u s e d B J T amplifier, the g r o u n d e d - e r n i t t e r or c o m m o n - e m i t t e r ( C E ) circuit. T h e total input voltage v, (bias + signal) is applied b e t w e e n b a s e and emitter; that is, v = Vj. T h e total output voltage v (bias + signal) is t a k e n b e t w e e n collector and g r o u n d ; that is, v = v . Resistor R has t w o functions: to establish a desired dc bias voltage at t h e collector, and to convert t h e collector signal current i to an output voltage, v or v . T h e supply voltage V is n e e d e d to bias the B J T as well as to supply the p o w e r n e e d e d for the operation of the amplifier.
0-5
V
BE
BE
0
0
c
ce
CE
cc
F i g u r e 5.26(b) s h o w s the voltage transfer characteristic of the C E circuit of Fig. 5.26(a). T o u n d e r s t a n d h o w this characteristic arises, w e first express v as 0
v
= v
0
= V
CE
c
-R i
c
1.5 1.0
I"
c
B
f
c
VftF =
V,
(5.50)
e
Next, w e o b s e r v e that since v = v,, the transistor will b e effectively cutoff for Vj 0.5 V or so. T h u s , for the r a n g e 0 < vj < 0.5 V, i will b e negligibly small, and v will b e equal to the supply voltage V ( s e g m e n t X Y of the transfer c u r v e ) . A s vj is increased a b o v e 0.5 V , the transistor b e g i n s to conduct, and i increases. F r o m E q . ( 5 . 5 0 ) , w e see that v d e c r e a s e s . H o w e v e r , since initially v w i l l b e l a r g e , t h e B J T will b e operating in the active m o d e , which gives rise to the sharply d e s c e n d i n g s e g m e n t Y Z of the voltage transfer curve. T h e equation for this s e g m e n t can be obtained by substituting in Eq. (5.50) the a c t i v e - m o d e expression for i , n a m e l y ,
Time (a)
BE
c
(b)
0
cc
c
0
0
FIGURE 5 . 2 6 (a) Basic common-emitter amplifier circuit, (b) Transfer characteristic of the circuit in (a). The amplifier is biased at a point Q, and a small voltage signal v is superimposed on the dc bias voltage V . The resulting output signal v appears superimposed on the dc collector voltage V . The amplitude of v is larger than that of v by the voltage gain A„. t
BE
a
CE
0
t
c
O b s e r v e that a further increase in v causes v to decrease only slightly: In the saturation region, v = V , w h i c h falls in the n a r r o w r a n g e of 0.1 V to 0.2 V. It is the almostconstant V* that gives this region of B J T operation the n a m e saturation. T h e collector current will also r e m a i n nearly constant at t h e v a l u e / c , BE
.
V
_
/V
BE T
T
CE
CE
CEsat
C£sat
=
he
s a t
w h e r e w e h a v e , for simplicity, neglected the Early effect. T h u s w e obtain
j 1
Csat
v
0
= V
c c
-R I e c
s
v / V T
„
/
•—
c
P.DZ)
(5.51)
W e observe that t h e exponential term in this equation gives rise to the steep slope of the Y Z segment of the transfer curve. Active-mode operation ends when the collector voltage ( % or v ) falls by 0.4 V or so b e l o w that of the base (v, or v ). At this point, the C B J turns on, and the transistor enters the saturation region. This is indicated b y p o i n t Z o n t h e transfer curve. CE
BE
^CC ~~ V~CEsat -
W e recall f r o m o u r s t u d y of t h e saturation r e g i o n of o p e r a t i o n in the p r e v i o u s section that t h e s a t u r a t e d B J T e x h i b i t s a v e r y s m a l l r e s i s t a n c e i ? b e t w e e n its c o l l e c t o r a n d emitter. T h u s , w h e n s a t u r a t e d , t h e transistor in F i g . 5.26 p r o v i d e s a l o w - r e s i s t a n c e p a t h b e t w e e n the c o l l e c t o r n o d e C a n d g r o u n d a n d h e n c e c a n b e t h o u g h t of as a c l o s e d s w i t c h . O n t h e o t h e r h a n d , w h e n t h e B J T is cut off, it c o n d u c t s n e g l i g i b l y s m a l l (ideally z e r o ) C £ s a t
41 1
4 1 2
C"''?
CHAPTER 5
5.3
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
THE BJT AS AN AMPLIFIER A N D AS A SWITCH
c u r r e n t a n d t h u s acts as an o p e n s w i t c h , effectively disconnecting n o d e C from g r o u n d .
without the amplifier entering the saturation region. If this h a p p e n s , the n e g a t i v e p e a k s of
T h e status of t h e s w i t c h (i.e., o p e n or c l o s e d ) is determined by the v a l u e of t h e control
the w a v e f o r m of v will b e flattened. Indeed, it is t h e n e e d to allow sufficient r o o m for out-
voltage v .
p u t signal s w i n g that d e t e r m i n e s t h e m o s t effective p l a c e m e n t of t h e b i a s p o i n t Q on t h e
BE
V e r y shortly, w e will s h o w that t h e B J T switch can also b e c o n t r o l l e d b y the
0
active-region segment, Y Z , of the transfer c u r v e . P l a c i n g Q too high o n this s e g m e n t not
b a s e current.
only results in r e d u c e d gain ( b e c a u s e V
is lower) but could possibly limit the available
RC
r a n g e of positive signal s w i n g . A t t h e positive end, t h e limitation is i m p o s e d b y the B J T cut-
5.3.2 Amplifier Gain
ting off, in w h i c h e v e n t the positive-output p e a k s w o u l d b e clipped off at a level e q u a l to
T o operate the B J T as a linear amplifier, it m u s t b e biased at a point in the active region.
V c- Finally, it is useful to n o t e that the theoretical m a x i m u m gain A is obtained b y bi as i ng
F i g u r e 5.26(b) s h o w s such a b i a s point, labeled Q (for q u i e s c e n t p o i n t ) , and characterized
the B J T at the e d g e of saturation, w h i c h of c o u r s e w o u l d not leave any r o o m for n e g a t i v e
b y a dc b a s e - e m i t t e r voltage V
signal s w i n g . T h e resulting gain is g i v e n b y
a n d a dc collector-emitter voltage V .
BE
current at this v a l u e of V
BE
CE
If t h e collector
C
V
is d e n o t e d I , that is, c
A
= JCC-VCE^
V
VeE/VT
I
= le
c
s
(
5
5
8
)
V
(5.53)
T
Thus, then from t h e circuit in Fig. 5.26(a) w e can write V
V
= V -R I
CE
CC
C
^RANAI =
(5.54)
C
N o w , if the signal to b e amplified, v is s u p e r i m p o s e d on V h
BE
and k e p t sufficiently small, as
C C
y
(5.59)
A l t h o u g h the g a i n can b e increased b y using a larger supply voltage, other considerations
indicated in Fig. 5.26(b), the instantaneous operating point will be constrained to a relatively
c o m e into play w h e n d e t e r m i n i n g an appropriate v a l u e for V .
short, almost-linear s e g m e n t of the transfer c u r v e around the bias point Q. T h e slope of this
t o w a r d using l o w e r and l o w e r supply voltages, currently a p p r o a c h i n g 1 V or so. A t such l o w
linear s e g m e n t will b e equal to the slope of t h e tangent to the transfer c u r v e at Q. T h i s slope
supply v o l t a g e s , l a r g e gain v a l u e s can b e o b t a i n e d b y r e p l a c i n g t h e r e s i s t a n c e R
is the voltage gain of the amplifier for small-input signals around Q. A n e x p r e s s i o n for the
constant-current source, as will b e seen in C h a p t e r 6.
CC
In fact, the trend h a s b e e n
c
with a
small-signal gain A can b e found b y differentiating the expression in E q . (5,51) and evaluV
ating t h e derivative at point Q; that is, for v =
V ,
I
d
=
A
BE
v
o dvj
(5.55) Consider a common-emitter circuit using a B J T having 4 = 1 0
Thus,
6.8 k£2, and a power supply V
CC
. K
1 j = - \ vT
v /v BE
(a) Determine the value of the bias voltage V
T
I s e
R
c
required to operate the transistor at V
BE
c
A, a collector resistance R
=
= 10 V. CE
= 3.2 V.
What is the corresponding value of 7 ?
T
C
(b) Find the voltage gain A at this bias point. If an input sine-wave signal of 5-mV peak ampli-
N o w , u s i n g Eq. (5.53) w e can express A in c o m p a c t form:
V
V
tude is superimposed on V , BE
J_ÇRÇ
A
=
_VRÇ
(
5
_
5
6
)
find the amplitude of the output sine-wave signal (assume linear
operation). (c) Find the positive increment in v
(above V ) that drives the transistor to the edge of satura-
BE
where V
RC
is the dc voltage drop across V
R
R,
tion, where v
c
C
= V
CE
C
C
- V
C
(5.57)
E
BE
= 0.3 V.
(d) Find the negative increment in v
BE
that drives the transistor to within 1% of cutoff (i.e., to
v =0.99V ). O
O b s e r v e that the C E amplifier is inverting; that is, the output signal is 180° out of p h a s e relative to t h e input signal. T h e simple e x p r e s s i o n in Eq. (5.56) indicates that the voltage gain of the common-emitter amplifier is the ratio of the dc voltage drop across R to the thermal voltage V (= 2 5 m V at r o o m temperature). It follows that to maximize the voltage gain w e should u s e as large a voltage drop across R as possible. For a given v a l u e of V , E q . (5.57) indicates that to increase V w e h a v e to operate at a lower V . H o w e v e r , reference to Fig. 5.26(b) s h o w s that a l o w e r V m e a n s a b i a s point Q close to the end of the activeregion s e g m e n t , w h i c h m i g h t not leave sufficient r o o m for the negative-output signal s w i n g c
CC
Solution (a)
T
c
RC
CC
CE
CE
' c c •V Rr
R
10-3.2
= 1 mA
414
ï
.
CHAPTER 5
5.3
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
The value of V
RF
THE BJT AS AN AMPLIFIER A N D AS A SWITCH
5.3.3 Graphical Analysis
can be determined from
A l t h o u g h f o r m a l graphical m e t h o d s are of little practical value in the analysis a n d design of 3
1 x KT =
l O - '
5
/
8
^
m o s t transistor circuits, it is illustrative to p o r t r a y graphically the o p e r a t i o n of a simple transistor amplifier circuit. C o n s i d e r t h e circuit of Fig. 5.27, w h i c h is similar to t h e circuit w e
which results in
h a v e b e e n s t u d y i n g e x c e p t for an a d d e d r e s i s t a n c e in the b a s e lead, R . A graphical analysis B
V
of t h e o p e r a t i o n of this circuit can b e p e r f o r m e d as follows: First, w e h a v e to d e t e r m i n e the
= 690.8 m V
RF
d c b i a s point. T o w a r d that e n d w e set v = 0 and u s e the t e c h n i q u e illustrated in F i g . 5.28 t
to d e t e r m i n e the d c b a s e current I . W e next m o v e to the i - v B
(b)
c
C E
characteristics, s h o w n in
Fig. 5.29. W e k n o w that t h e operating p o i n t will lie on t h e i -v E c
A
the v a l u e of b a s e current w e h a v e d e t e r m i n e d (the c u r v e for i = I ). B
V
-
c u r v e c o r r e s p o n d i n g to
C
CC-VCE
B
W h e r e it lies on the
c u r v e will b e d e t e r m i n e d b y the collector circuit. Specifically, t h e collector circuit i m p o s e s
V
T
the constraint = -
V
CE
U
^ 0.025
=. - 2 7 2 VA^ V
CE
= 2 7 2 x 0 . 0 0 5 = 1.36 V
0
(c) For v
1
i
cc
R
ic C
w h i c h c a n b e rewritten as
= 0.3 V,
i
— VCC ~~
10-0.3 , . = — — — = 1.617 m A 6.8
- L ^ ç Rc
K
w h i c h r e p r e s e n t s a linear relationship b e t w e e n v
CE
± c
v
a n d i . This relationship c a n b e r e p r e c
sented b y a straight line, as s h o w n in Fig. 5.29. Since R
c
To increase i from 1 m A to 1.617 mA, v c
c a n b e c o n s i d e r e d the amplifier load,
must be increased by
BE
Av =V ln[±f-^ BE
T
= 12 mV (d) F o r w = 0 . 9 9 V 0
CC
= 9.9 V, 10-99 " = 0.0147 m A 6.8
l
c =
n
To decrease i from 1 m A to 0.0147 mA, v c
BE
Av
BE
must change by
- V
In
r
FIGURE 5 . 2 7 Circuit whose operation is to be analyzed graphically.
j^a0147j Load line
-105.5 m V
EXERCISE 5.19 For the situation described in Example 5.2, while keeping I unchanged at 1 m A , find the value of R that will result in a voltage gain of - 3 2 0 V / V . What is the largest negative signal swing allowed at the output (assume that v is not to decrease below 0.3 V)? What (approximately) is the corresponding input signal amplitude? (Assume linear operation). c
c
CE
Ans. 8 k Q : 1.7 V ; 5.3 m \
FIGURE 5 . 2 8 Graphical construction for the determination of the dc base current in the circuit of Fig. 5.27.
CHAPTER 5
BIPOLAR J U N C T I O N TRANSISTORS
(BJTS)
Load line
FIGURE 5 . 2 9 Graphical construction for determining the dc collector current I and the collector-toemitter voltage V in the circuit of Fig. 5.27. c
CE
7
the straight line of slope -1/R
C
is k n o w n as the load l i n e . T h e d c bias point, or quiescent
point, Q will b e at t h e intersection of the load line and the i -v E c
c u r v e c o r r e s p o n d i n g to the
C
b a s e current I . T h e coordinates of point Q give the dc collector current I and the d c collectorB
c
to-emitter v o l t a g e V .
O b s e r v e that for amplifier operation, Q should b e in the active region
CE
and furthermore s h o u l d b e located so as to allow for a r e a s o n a b l e signal s w i n g as the input signal v is applied. T h i s will b e c o m e clearer shortly. t
T h e situation w h e n v is applied is illustrated in Fig. 5.30. C o n s i d e r first F i g . 5.30(a), t
w h i c h s h o w s a signal v h a v i n g a triangular w a v e f o r m b e i n g s u p e r i m p o s e d o n t h e d c voltage t
V . BB
C o r r e s p o n d i n g to e a c h i n s t a n t a n e o u s v a l u e of V
+ v (t), o n e c a n d r a w a straight line
BB
with slope -1/R .
t
S u c h an " i n s t a n t a n e o u s load l i n e " intersects t h e i -v
B
B
w h o s e coordinates g i v e the total i n s t a n t a n e o u s values of i and v B
ticular value of V
BB
BE
c u r v e at a point
c o r r e s p o n d i n g to the par
BE
+ v (t). A s an e x a m p l e , F i g . 5.30(a) s h o w s the straight lines correspond t
ing to Vj = 0, Vj at its positive peak, and v- at its n e g a t i v e p e a k . N o w , if the a m p l i t u d e of v is t
t
sufficiently s m a l l so that the i n s t a n t a n e o u s o p e r a t i n g p o i n t is confined to an almost-linear s e g m e n t of t h e i -v B
BE
c u r v e , t h e n t h e resulting signals i a n d v b
be
will b e t r i a n g u l a r in w a v e
form, as indicated in the figure. This, of course, is the small-signal approximation. In summary, t h e graphical construction in Fig. 5.30(a) c a n b e u s e d to d e t e r m i n e t h e total instantaneous value of i c o r r e s p o n d i n g to e a c h v a l u e of v . B
t
N e x t , w e m o v e to the ir-v
CE
characteristics of F i g . 5.30(b). T h e operating p o i n t will m o v e
along the load line of slope - \ / R
as i goes t h r o u g h the instantaneous values determined
c
B
from Fig. 5.30(a). F o r e x a m p l e , w h e n v is at its positive peak, i = i t
B
the instantaneous operating point in the i —v c
B1
(from Fig. 5.30(a)), and
plane will b e at the intersection of the load
CE
line and the c u r v e corresponding to i = i . In this w a y , o n e can d e t e r m i n e the waveforms of B
i and v c
CE
B2
and h e n c e of the signal c o m p o n e n t s i and v , as indicated in Fig. 5.30(b). c
ce
Effects o f Bias-Point L o c a t i o n o n A l l o w a b l e Signal S w i n g p o i n t in t h e ic-v
CE
T h e location of the dc bias
p l a n e significantly affects t h e m a x i m u m allowable signal s w i n g at the
-collector. Refer to F i g . 5.30(b) and o b s e r v e that t h e p o s i t i v e p e a k s of v
ce
cannot go beyond FIGURE 5 . 3 0 Graphical determination of the signal components v , i , i , and v when a signal component v is superimposed on the dc voltage V (see Fig. 5.27). ie
7
The term load line is also employed for the straight line in Fig. 5.28.
{
b
c
ct
BB
41 7
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.3
THE BJT AS AN AMPLIFIER A N D AS A SWITCH
v
cc *.Rc.
-vvv-1
FIGURE 5 . 3 2 A simple circuit used to illustrate the different modes of operation of the BJT.
5.3.4 Operation as a Switch T o o p e r a t e t h e B J T as a switch, w e utilize t h e cutoff a n d t h e saturation m o d e s of o p e r a tion. T o illustrate, c o n s i d e r o n c e m o r e t h e c o m m o n - e m i t t e r circuit s h o w n in F i g . 5.32 as the i n p u t Vj is v a r i e d . F o r v, less t h a n a b o u t 0.5 V, t h e t r a n s i s t o r will b e c u t off; t h u s i = 0, i = 0, a n d v = V . In this state, n o d e C is d i s c o n n e c t e d from g r o u n d ; t h e s w i t c h is in t h e open p o s i t i o n .
Load-line B
B
c
FIGURE 5 . 3 1 Effect of bias-point location on allowable signal swing: Load-line A results in bias point Q with a corresponding V which is too close to V and thus limits the positive swing of v . At the other extreme, load-line B results in an operating point too close to the saturation region, thus limiting the negative swing of v . A
CE
cc
c
cc
CE
T o turn t h e t r a n s i s t o r on, w e h a v e to i n c r e a s e v a b o v e 0.5 V . In fact, for a p p r e c i a b l e currents t o f l o w , v s h o u l d b e a b o u t 0.7 V and v, s h o u l d b e h i g h e r . T h e b a s e c u r r e n t will b e }
CE
BE
V, otherwise the transistor enters the cutoff region. Similarly, t h e n e g a t i v e peaks of v cannot extend b e l o w a few tenths of a volt (usually, 0.3 V ) , o t h e r w i s e the transistor enters the sataration region. T h e location of the bias point in Fig. 5.30(b) allows for an approximately equal s w i n g in e a c h direction. Next consider Fig. 5.31. Here w e show load lines corresponding to t w o values of R . Line A corresponds to a l o w value of R and results in the operating point Q , w h e r e the value of V is very close to V . Thus the positive swing of v will be severely limited; in this situation, it is said that there i s n ' t sufficient "head r o o m . " O n the other hand, line B , w h i c h corresponds to a large R , results in the bias point Q , w h o s e V is too low. T h u s for line B , although there is a m p l e r o o m for the positive excursion of v (there is a lot of head r o o m ) , the negative signal swing is severely limited by the proximity to the saturation region (there is not sufficient "leg r o o m " ) . A c o m p r o m i s e between these t w o situations is obviously called for. cc
ce
vi -
V
BE
(5.60)
R
R
and the collector current will b e
c
c
A
cc
ce
c
B
ic = ßi.
CE
(5.61)
which applies only w h e n t h e device is in the active m o d e . This will b e t h e case as long as the C B J is n o t forward biased, that is, as l o n g as v > v - 0.4 V , w h e r e v is g i v e n b y c
B
c
CE
v
R
cc
ce
- cic
(5.62)
O b v i o u s l y , as v is increased, i will increase (Eq. 5.60), i will correspondingly increase (Eq. 5.61), and v will decrease (Eq. 5.62). Eventually, v will b e c o m e lower than v b y 0.4 V, at w h i c h p o i n t the transistor leaves the active region and enters the saturation region. T h i s e d g e - o f - s a t u r a t i o n ( E O S ) point is defined b y t
B
c
c
5.20 Consider the circuit of Fig. 5.27 with V = 1.7 V, R = 100 k Q , V - 10 ,V, and R = 5 k Q . Let the transistor B = 100. The input signal t/,- is a triangular wave of 0.4 V peafcto-peak. Refer to Fig, 5.30, and use the geometry of the graphical construction shown there to answer the following questions: (a) -If V = 0.7 V, find I . (b) Assuming operation on a straight line segment of the exponential i - v . curve, show that the inverse of its slope is V /I , and compute its value, (c) Find approximate values for the peak-to-peak amplitude of i and of v . (d) Assuming the i —% curves to be horizontal (i.e., ignoring the Early effect), find l and V . (c) Find the peak-to-pcak amplitude of i and of «„.. (f) What is the voltage gain of this amplifier? BB
H
cc
BE
B
h
c
Ans.
bc
(T
1
c
B
T
c
w h e r e w e h a v e a s s u m e d that V
BE
v
-
3
cc-°
(5.63)
Rr
is a p p r o x i m a t e l y 0.7 V , and
B t
T _ -'FI(EOS)
R
t
C(EOS)
B
IC(EQS) 7j—
(5.64)
fc
c
T h e c o r r e s p o n d i n g value of w required to drive the transistor to the edge-of-saturation can b e found from 7
(a) 10 fiA; (b) 2.5 k Q ; (c) 4 //A, 10 mV: (d) 1 mA. 5 V: (e) 0.4 m A , 2 V; (f) - 5 V / V ^ 7 (EOS)
-
IB(EOS)RB
+
^BE
(5.65)
419
CHAPTER 5
BIPOLAR J U N C T I O N T R A N 5 I S T O R S (BJTS)
5.4
I n c r e a s i n g v, a b o v e V ) increases the b a s e current, w h i c h drives the transistor deeper into saturation. T h e collector-to-emitter voltage, h o w e v e r , decreases only slightly. A s a reasonable a p p r o x i m a t i o n , w e shall usually a s s u m e that for a saturated transistor, V s 0.2 V. T h e collector current then r e m a i n s nearly constant at 7 , 7 ( E 0 S
BJT CIRCUITS AT D C
" "J
For an overdrive factor of 10, the base current should be I
B
= 1 0 x 0 . 1 9 6 = 1.96 m A
C £ s a t
C s a t
Thus we require a value of R such that B
/ c
=
V
c
C
" /
C
£
s
a
t
(5-66)
Forcing m o r e current into the base has very little effect on 7 and V . In this state the switch is closed, with a low closure resistance 7 ? and a small offset voltage V (see Fig. 5.24c). Finally, recall that in saturation o n e can force the transistor to operate at any desired ¡3 b e l o w the n o r m a l value; that is, the ratio of t h e collector current 7 to the b a s e current can b e set at will and is therefore called the forced /3, C s a t
C £ s a t
C £ s a t
CEoS
C s a t
Aorced = ^
(5-67) 5.21 Consider the circuit in Fig. 5.32 for the case V = +5 V. v, = +5 V. R = R = 1 k Q , and f3 - 100. Calculate the base current, tire:collector current, and the collector voltage. If the transistor is saturated, find forced- What value should R be raised to in order to bring the transistor to the edge of saturation? Ans. 4.3 m A ; 4.8 m A ; 0.2 V; 1.1; 91.5 kil f r
A l s o recall that the ratio of I to / B
B ( E
os)
i s
k n o w n as the overdrive factor.
B
r
B
I be transistor in Fig. 5.33 is specified to have j3 in the range of 50 to 150. Find the value of R that B
IVMIIIS in saturation with an overdrive factor of at least 10.
!
• " 5.4 BJT CIRCUITS AT DC
+10 V
W e are n o w ready to consider the analysis of B J T circuits to w h i c h only dc voltages are applied. In the following e x a m p l e s w e will u s e the simple m o d e l in which, | V \ of a conducting transistor is 0.7 V and | V \ of a saturated transistor is 0.2 V , and w e will n e g l e c t the Early effect. Better m o d e l s can, of course, b e u s e d to obtain m o r e accurate results. This, however, is usually a c h i e v e d at the e x p e n s e of speed of analysis, and m o r e importantly, it could i m p e d e t h e circuit d e s i g n e r ' s ability to gain insight r e g a r d i n g circuit behavior. A c c u rate results using elaborate m o d e l s can b e obtained using circuit simulation with S P I C E , as we shall see in Section 5 . 1 1 . This is almost a l w a y s d o n e in the final stages of a design and certainly before circuit fabrication. C o m p u t e r simulation, h o w e v e r , is not a substitute for quick p e n c i l - a n d - p a p e r circuit analysis, an essential ability that aspiring circuit designers must muster. T h e following series of e x a m p l e s is a step in that direction. BE
CE
•=r
FIGURE 5 . 3 3 Circuit for Example 5.3.
A s will b e seen, i n a n a l y z i n g a circuit t h e first q u e s t i o n that o n e m u s t a n s w e r is: I n which m o d e is the transistor o p e r a t i n g ? In s o m e c a s e s , t h e a n s w e r will b e o b v i o u s . In m a n y cases, h o w e v e r , it will not. N e e d l e s s to say, as t h e r e a d e r gains practice and e x p e r i e n c e in transistor circuit analysis and design, the a n s w e r will b e o b v i o u s in a m u c h larger proportion of p r o b l e m s . T h e a n s w e r , h o w e v e r , can a l w a y s b e d e t e r m i n e d b y utilizing the following procedure:
Solution \\ lien the transistor is saturated, the collector voltage will be V
=V ^
c
0.2 V
CEs
Thus the collector current is given by /
c
s
a
t
=
r i O ^
=
9
.
8
m
A
A s s u m e that the transistor is operating in the active m o d e , and p r o c e e d to d e t e r m i n e t h e various voltages and currents that correspond. T h e n check for consistency of the results with the assumption of active-mode operation; that is, is v of an npn transistor greater than - 0 . 4 V (or v of a pnp transistor l o w e r than 0.4 V ) ? If the a n s w e r is yes, t h e n our task is complete. If the answer is n o , a s s u m e saturation-mode operation, and p r o c e e d to d e t e r m i n e currents and voltages and then to c h e c k for consistency of t h e results with the a s s u m p t i o n of saturationmode operation. H e r e t h e test is usually to c o m p u t e the ratio I /I and to verify that it is CB
To saturate the transistor with the lowest ¡3, w e need to provide a base current of at least
hvos)
= 7 p
=
IrT
=
196
°-
^
CB
C
B
4 2 1
CHAPTER 5
5.4
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
l o w e r t h a n the transistor ¡3; i.e., / 3
f o r c e d
< j8. S i n c e ¡3 for a given transistor varies over a wide
r a n g e , o n e should u s e the l o w e s t specified ¡3 for this test. Finally, n o t e that the order of these t w o a s s u m p t i o n s can b e reversed.
BJT CIRCUITS AT D C
Solution Glancing at the circuit in Fig. 5.34(a), w e note that the base is connected to +4 V and the emitter is connected to ground through a resistance R . It therefore is safe to conclude that the b a s e emitter junction will be forward biased. Assuming that this is the case and assuming that V is approximately 0.7 V, it follows that the emitter voltage will be E
BE
V
= 4 - V
E
B
E
=
4-0.7
= 3.3" V
Consider the circuit shown in Fig. 5.34(a), which is redrawn in Fig. 5.34(b) to remind the reader
W e are now in an opportune position; w e know the voltages at the two ends of R
of the convention employed throughout this book for indicating connections to dc sources. We
detennine the current I through it,
wish to analyze this circuit to determine all node voltages and branch currents. W e will assume that BIS specified to be 100.
E
and thus can
E
3.3 . . = — = 1 mA R 3.3 Since the collector is connected through R to the +10-V power supply, it appears possible that the collector voltage will be higher than the base voltage, which is essential for active-mode operation. Assuming that this is the case, we can evaluate the collector current from ,
VE-0
I
=
F E
E
c
+ 10 V
A R
+4 V
R
F
r
R
= 4.7 k f l
4 7
c
= -
k
ß
The value of a is obtained from
<
10 V a
=
/ _
ß+l 4 V -$r
£
*
£
=
Q
9
9
Thus I will be given by
=
c
3.3 kfl
= 3.3 k O
= 100 101
I
= 0.99 x 1 = 0.99 m A
c
We are now in a position to use O h m ' s law to determine the collector voltage V, V
C
(b)
(a)
0.99
X 1 = 0.99
rriA
C
C
= 10-0.99x4.7 =+5.3 V
Since the base is at +4 V, the collector-base junction is reverse biased by 1.3 V, and the transistor is indeed in the active mode as assumed. It remains only to determine the base current I , as follows:
+ 10 V (D
= 10-I R
B
j
4.7 kfl o 10 - 0.99 X 4.7 = 5.3 V +4 V
©
0
Before leaving this example w e wish to emphasize strongly the value of carrying out the analysis directly on the circuit diagram. Only in this way will one be able to analyze complex circuits in a reasonable length of time. Figure 5.34(c) illustrates the above analysis on the circuit diagram, with the order of the analysis steps indicated by the circled numbers.
1.00 - 0.99 = 0.01 rnA - o 4 - 0.7 = 3.3 V
©
3.3 kfl < { | f
=
1 mA
©
(c) FIGURE 5 . 3 4 Analysis of the circuit for Example 5.4: (a) circuit; (b) circuit redrawn to remind the reader of the convention used in this book to show connections to the power supply; (c) analysis with the steps numbered.
We wish to analyze the circuit of Fig. 5.35(a) to d e t e r m i n e the voltages at all nodes and the currents through all b r a n c h e s . N o t e that this circuit is identical to that of Fig. 5.34 except that the voltage at the b a s e is n o w + 6 V. A s s u m e that the transistor B is specified to be AT LEAST 50.
V*3
4 2 3
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
5.4
(BJTs)
Since the collector voltage calculated appears to be less than the base voltage by 3.52 V, it follows that our original assumption of active-mode operation is incorrect. In fact, the transistor has to be in the saturation mode. Assuming this to be the case, we have
-10 V
+ 10 V
0
=1.6 mAJ
4.7 kfl
4.7 kfl
0
- o 1 0 - 1.6 X 4.7 = Impossible, not in active mode
+6 V
+6 V
t_
- o 6 - 0.7 = +5.3 V
V
= + 6 - 0 . 7 = +5.3 V
h
=
V
= V +y
E
0
c
= L
3.3 k O £
1 'j | | =
1-6 mA
©
?f = 3.3
~ = 1-6 m A 3.3
£
T
i.3 kfl
BJT CIRCUITS AT
I
+10-5.5 4.7 -
=
= I -I
B
C £ s a t
E
- + 5 . 3 + 0.2 = +5.5 V Q
^
%
= 1.6 - 0 . 9 6 = 0.64 m A
C
Thus the transistor is operating at a forced ¡3 of (b)
(a)
R
= ^ = ^ = 15 h 0-64
^
Since jSf ed is less than the minimum specified value of ¡3, the transistor is indeed saturated. W e should emphasize here that in testing for saturation the m i n i m u m value of p should be used. By the same token, if w e are designing a circuit in which a transistor is to be saturated, the design should be based on the minimum specified p. Obviously, if a transistor with this minimum p is saturated, then transistors with higher values of p will also be saturated. T h e details of the analysis are shown in Fig. 5.35(c), where the order of the steps used is indicated by the circled numbers. 0re
10 V
(?) — •
w
— = 0.96 mA 4.7
11 'I
4.7 kft
-6 V
0
- o 5.3 + 0 . 2 = + 5 . 5 V
0.64 mA 0
6 - 0 . 7 = +5.3 V
0 0
We wish to analyze the circuit in Fig. 5.36(a) to determine the voltages at all nodes and the currents through all branches. Note that this circuit is identical to that considered in Examples 5.4 and 5.5 except that now the base voltage is zero.
3.3 kfl
0g
= 1.6 mA \
+ 10 V
(c) FIGURE 5 . 3 5 Analysis of the circuit for Example 5.5. Note that the circled numbers indicate the order of the analysis steps.
+ 10 V
0
BEI
R
r
J
0 mA
= 4.7 kfl
4.7 kfl
®
0 mA
>
o +10 V
Solution _L —
Assuming active-mode operation, w e have V
= +6-V
E
BE
= 6 - 0 . 7 = 5.3 V
R
E
= 3.3 kfl
L
3
-
3
k
ü
Cutoff o 0 V | | O m A
0
0
®
3
/ „ = I - = 1.6 m A E
V
r
J
3.3 = + 1 0 - 4.7 x l
c
= 10 - 7.52 = 2.48 V
The details of the analysis performed above are illustrated in Fig. 5.35(b).
(a)
(b)
FIGURE 5 . 3 6 Example 5.6: (a) circuit; (b) analysis with the order of the analysis steps indicated by circled numbers.
DC
26
Ï^S
CHAPTERS
BIPOLAR JUNCTION TRANSISTORS (BJTs)
5.4 BJT CIRCUITS AT DC
Solution
Solution Since the base is at zero volts and the emitter is connected to ground through R , the emitter-base
The base of this pnp transistor is grounded, while the emitter is connected to a positive supply
junction cannot conduct and the emitter current is zero. Also, the collector-base junction cannot
(y+ = +10 V) through R . It follows that the emitter-base junction will b e forward biased with
E
E
conduct since the re-type collector is connected through R to the positive power supply while the c
v =
p-type base is at ground. It follows that the collector current will b e zero. The base current will also have to b e zero, and the transistor is in the cutoff m o d e of operation.
E
y KP - 0.7 v
Thus the emitter current will be given by
The emitter voltage will obviously be zero, while the collector voltage will b e equal to +10 V, since the voltage drop across R is zero. Figure 5.36(b) shows the analysis details.
10-0.7
c
R
= 4.65 m A
2
E
Since the collector is connected to a negative supply (more negative than the base voltage) through R , it is possible that this transistor is operating in the active mode. Assuming this to be the case, we obtain c
D5.22 For the circuit in Fig. 5.34(a), find the highest voltage to which the base can b e raised while the transisah
tor remains in (lie active mode. A s s u m e a —..L.. Ans. + 4 . 7 V
Since no value for /j has been given, we shall assume B = 100, which results in a = 0.99. Since large variations in B result in small differences in a, this assumption will not b e critical as far as determining the value of I is concerned. Thus,
D5.23 Redesign the circuit <>f l i g . 5.34(a) (i.e., find new values for A'.- and R, i1«> establish a collector current of 0.5 m A and a reverse-bias voltage on the collector-base junction of 2 V. Assume a — 1.
c
Ans.R = 6.ft Li I: A', - s kii £
I
r
= 0.99 x 4.65 = 4.6 m A
5.24 For the circuit in Fig. 5.35(a). find the value to which the base voltage should be changed to so that the The collector voltage will be
transistor operates in saturation with a forced B of 5. Ans. 15.18 \
V
r
= V
l
R
' c c
- 1 0 + 4.6 x 1 = - 5 . 4 V Thus the collector-base junction is reverse biased by 5.4 V , and the transistor is indeed in the active mode, which supports our original assumption. It remains only to calculate the base current, W e desire to analyze the circuit of Fig. 5.37(a) to determine the voltages at all nodes and the currents through all branches. /3+1 +
V
= +10V A
jio_M
value of B will have no effect on the mode of operation of the transistor. Since B is generally an =
4
.
6
5
m
A
ill-specified parameter, this circuit represents a good design. As a rule, one should strive to design
@
2 kfl
the circuit such that its performance o +0.7 V
to the value of ¡3 as possible.
The analysis
©
= 0.05 mA
- o - 1 0 + 4.6 X 1 = - 5 . 4 V Rr = 1 kfl 1 kfl © V~ = - 1 0 V
0.99 X 4.65 = 4.6 mA j ' -10 V (b)
0 D5.25 For the circuit in Fig. 5.37(a). find the largest value to which R remains in ihe active mode. Ans. 2.26 kfl
c
Example 5.7: (a) circuit; (b) analysis with the steps indicated by circled numbers.
can b e raised while the transistor
D5.26 Redesign the circuit of Fig. 5.37(a) (i.e., find n e w values for 7 ^ and R ) to establish a collector current of 1 m A and a reverse bias on the collector-base junction of 4 V. Assume a —I. Ans. Rp = 9.3 k Q ; R = 6 k Q c
c
FIGURE 5 . 3 7
is as insensitive
details are illustrated in Fig. 5.37(b). ©
(a)
0.05 m A
Obviously, the value of B critically affects the base current. Note, however, that in this circuit the
+ 10 V
Rp = 2 kfl
4.65 101
427
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.4
B J T C I R C U I T S A T D< ""Saw
W e want to analyze the circuit in Fig. 5.38(a) to detennine the voltages at all nodes and the currents in all branches. Assume p = 100.
D5.27 T h e circuit of Fig. 5.38(a) is to be fabricated using a transistor type whose p is specified to b e in the range of 5 0 to 150. That is, individual units of this same transistor type can h a v e P values anywhere in this range. Redesign the circuit by selecting a new value for R so that all fabricated circuits are guaranteed to be in the active m o d e . W h a t is the range of collector voltages that the fabricated circuits m a y exhibit? c
+ 10 v A
+ 10 V
À
Ans.
I
+5 V
À
R
c
c
c
0
= 100 x 0.043 4.3 mA
c
2 kft
R = 1.5 Ml; V = 0.3 V to 6.8 V
5 V
~ ^ kîî
A
y 100 kft AA/V
©
I / = 4.3 + 0 . 0 4 3 ^ Y = 4.343 mA w
B
(a)
= 10 - 2 x 4.3 = +1.4 V
We want to analyze the circuit of Fig. 5.39 to determine the voltages at all nodes and the currents trough all branches. The minimum value of p is specified to be 30.
_ 5 - 0.7 6 ' ~ 100 +0.7 V = 0.043 mA Q
©
c
£
(b)
1 kfl FIGURE 5 . 3 8 Example 5.8: (a) circuit; (b) analysis with the steps indicated by the circled numbers. 1 kfi
V
E
Solution
V
£ C s a t
= V + 0.7 (3) B
= 0.2 V (5)
The base-emitter junction is clearly forward biased. Thus, V
c
= HlXsS - 5 ^ Z
7,
= 0.043 m A
10 kfl
100
= V + 0.5 (6) B
10 kfl
Assume that the transistor is operating in the active mode. W e now can write -5 V I
c
= pi
-5 V
= 100 x 0.043 = 4.3 m A
B
(a)
(b)
T h e collector voltage can now be determined as FIGURE 5 . 3 9 Example 5.9: (a) circuit; (b) analysis with steps numbered. V
c
= -+10 - 7 7 ? C
C
= 1 0 - 4 . 3 x 2 = +1.4 V
Solution Since the base voltage V is B
V
=
B
V ^+0.7V BE
it follows that the collector-base junction is reverse-biased by 0.7 V and the transistor is indeed in the active mode. The emitter current will be given by I= E
(¿3+ 1)1
B
= 101 x 0.043 = 4.3 m A
A quick glance at this circuit reveals that the transistor will be either active or saturated. Assuming active-mode operation and neglecting the base current, we see that the base voltage will be approximately zero volts, the emitter voltage will be approximately +0.7 V, and the emitter current will be approximately 4.3 mA. Since the m a x i m u m current that the collector can support while the transistor remains in the active m o d e is approximately 0.5 m A , it follows that the transistor is definitely saturated. Assuming that the transistor is saturated and denoting the voltage at the base by V (refer to Fig. 5.39b), it follows that B
W e note from this example that the collector and emitter currents depend critically on the value of p. In fact, if P were 10% higher, the transistor would leave the active m o d e and enter saturation. Therefore this clearly is a bad design. T h e analysis details are illustrated in Fig. 5.38(b).
V
F
=
V
c
=
V +V,
y
R
V -V E
ECat
B
+ o,7
= V + 0.7-0.2 = y R
H
+ 0.5
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
+5-V
5-V -0J f = 4.3-V mA
F
h
=
10
+ 15 V
B
=
B
= 0.1 V» m A V
RB
V -(-5) = „ 10
I
c
c
= +5 V
y + 0.5 + 5 = — = 0.1 V» + 0.55 m A 10
r C
B
8
Using the relationship I = I + I , w e obtain E
B
c
4.3 -V
= 0.1 V + 0.1 V + 0.55
B
B
B
which results in 3 75 V „ = — = 3.13 V 1.2 B
(b)
(a) Substituting in the equations above, w e obtain E
v
+ 15 V i
-15 V
= 3.83 V
v
= 3.63 V
c
1.28 mA
= 1.17 m A
h
Id = 0.86 m A
— o +8.6 V
+5 V
= 0.31 m A
h
0.013 mA =
^
100 kfl 0.013 mA
33.3 kO —VW—
It is clear that the transistor is saturated, since the value of forced ¡3 is
Aorced
103 m A
5 kfl
+4.57 V 6
- o +3.87 V
+4.57 V
~ 2-8
50 kfl
3 kO
I 0.09 mA
1.29 mA
which is m u c h smaller than the specified m i n i m u m B.
(d)
(c) FIGURE 5 . 4 0 Circuits for Example 5.10. W e want to analyze the circuit of Fig. 5.40(a) to determine the voltages at all nodes and the currents
Substituting for I by B
through all branches. Assume / j = 100.
Solution
¿3+1
The first step in the analysis consists of simplifying the base circuit using Thevenin's theorem.
and rearranging the equation gives
The result is shown in Fig. 5.40(b), where E
y B B
= +15—^2— R +R m
RBB
15—50— 100 + 50
=
B2
R
= <,RBIH BI)
= (100//50)
R +[R /{ß+l)] E
=
+
5
BB
V
For the numerical values given w e have
= 33.3 k Q
EG
/„ =
JÜÜf
^ P - ^ = 1.29 m A 3 + (33.3/101)
E
To evaluate the base or the emitter current, w e have to write a loop equation around the loop marked L in Fig. 5.40(b). Note, though, that the current through R
BB
is different from the current
T h e base current will b e
through R . T h e loop equation will b e E
V
BB
R
~ h BB
+
BE +
R
IE E
/ „ = — = 0.0128 m A 101 B
-!
CHAPTER 5
5.4
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
The base voltage is given by
BJT CIRCUITS A T D C
+ 15 V
A V
B
= V
+
BE
IR E
E
= 0 . 7 + 1 . 2 9 x 3 = 4.57 V
R, R
A s s u m e active-mode operation. W e can evaluate the collector current as
B1
R
= 2 kH
F1
= 5 kfl
r
= 100 kfl 02
I
= aI
c
E
= 0 . 9 9 x 1.29 = 1.28 m A
The collector voltage can now b e evaluated as V
c
= +15-I R C
C
= 1 5 - 1 . 2 8 x 5 = 8.6 V
It follows that the collector is higher in potential than the base by 4.03 V, which means that
' Rro = 2.7 k O • R
R2
= 50 kfl
the transistor is in the active mode, as had been assumed. The results of the analysis are given in
• Rr = 3 kfl
Figs. 5.40(c and d).
(a)
5.28 If t h e transistor in the circuit of Fig. 5.40(a) is replaced with another having half the v a l u e of /? (i.e., ¡3 • 50), find the n e w value of /,-, and express the change in /, as a percentage. A n s . / = 1.15 m A ; - 1 0 % C
0.103 mA o +9.44 V
+4.57 V j
W e wish to analyze the circuit in Fig. 5.41(a) to determine the voltages at all nodes and the cur-
|
rents through all branches.
o +7.43 V
Solution I W e first recognize that part of this circuit is identical to the circuit we analyzed in Example 5.10— namely, the circuit of Fig. 5.40(a). The difference, of course, is that in the new circuit we have
i
i
an additional transistor Q together with its associated resistors R^ 2
Bl
m
= +4.57V
I
= 1.29 m A
= 0.0128 m A
I
= 1.28 m A
E1
cl
Circuits for Example 5.11.
As far as Q is concerned, we note that its emitter is connected to +15 V through R^. 2
therefore safe to assume that the emitter-base junction of Q will be forward biased. Thus the
lector current I
emitter of Q will be at a voltage V
cl
m
will flow in the base lead of Q (I ). 2
As a first approximation we m a y assume
B2
is m u c h smaller than I ; that is, we may assume that the current through R C1
cl
equal to l . This will enable us to calculate c{
V
c
l
2
2
m
V:
V
a
^+\5-I
E2
c
l
R
c
l
given by
is almost = V
cl
+V \ EB
-
Qi
8.6 + 0.7 = +9.3 V
The emitter current of Q m a y now be calculated as 2
I
It is
However, the collector voltage will be different than previously calculated since part of the colthat I
I
(b)
x
FIGURE 5 . 4 1 y I
J
a
example:
|
I |
and R . A s s u m e that Q is
still in the active mode. The following values will be identical to those obtained in the previous
= 1 5 - 1 . 2 8 x 5 = +8.6 V +15- V
E2
Thus <2i is in the active mode, as had been assumed.
l
E2
R E2
_
15-9.3
= 2.85 m A
4 3 3
434
CHAPTER 5
5.4 BJT CIRCUITS AT D C
BIPOLAR J U N C T I O N TRANSISTORS (BJTS)
Since the collector of Q is returned to ground via R , 2
it is possible that Q is operating in the
C2
2
active mode. Assume this to b e the case. W e now find I
C2
as
5.30 T h e circuit in Fig. E5.30 is to be connected to the circuit in Fig. 5.41(a) as indicated; specifically, the base of<2 is to b e connected to the collector of Q , If has /J—100, find the new value of V and the values of V and I . 3
=
^C2
a
2^£2
2
E3
= 0.99 x 2.85 = 2.82 m A
C2
a
(assuming B = 100) 2
15 V
The collector voltage of Q will be 2
V
= IR
C2
which is lower than V
B2
C2
= 2.82 x 2.7 = 7.62 V
C2
To collector o of 2 in Fig. 5.41(a)
e
by 0.98 V. Thus Q is in the active mode, as assumed. 2
It is important at this stage to find the magnitude of the error incurred in our calculations by the assumption that I
B2
is negligible. The value of I
B2
/ 2
B
which is indeed much smaller than I
2
+ l
101
(1.28 m A ) . If desired, we can obtain more accurate results
a
by iterating one more time, assuming I
to be 0.028 m A . The new values will b e
B2
Current in R
= ? | 5 = 0.028 m A
JlL.
= B
is given by
CI
= I
V
C1
= 1 5 - 5 x 1.252 = 8.74 V
V
= 8.74 + 0.7 = 9.44 V
E2
c l
-I
= 2.78 m A
=
I
= 0.99 x 2.78 = 2.75 m A
V
C2
I
S2
Ans. +7.06 V: +6.36 V; 13.4 m A
= 1 . 2 8 - 0 . 0 2 8 = 1.252 m A
B 2
h i
C2
FIGURE E5.30
= 2.75 x 2.7 = 7.43 V =
=
0
_
0 2 7 5
m
W e desire to evaluate the voltages at all nodes and the currents through all branches in the circuit of Fig. 5.42(a). A s s u m e B = 100. +5 V A
A
101 Note that the n e w value of I
B2
+5 V
js3.9mA
is very close to the value used in our iteration, and no further itera-
tions are warranted. The final results are indicated in Fig. 5.41(b).
(3) 0.039 m A
0
^
The reader justifiably might be wondering about the necessity for using an iterative scheme in solving a linear (or linearized) problem. Indeed, we can obtain the exact solution (if w e can call anything w e are doing with a first-order model exact!) by writing appropriate equations. The reader is encouraged to find this solution and then compare the results with those obtained above.
ßi
10 kft + 5 V c—VW—"
+5 V o
It is important to emphasize, however, that in most such problems it is quite sufficient to obtain
io kn VW-
|0
®
5 - 0.7 l kn
an approximate solution, provided that we can obtain it quickly and, of course, correctly.
+ 3.9 V (7)
+ 4.6 V j
10 + 101 x 1
(5)
l
ka
02
0.039 mA In the a b o v e e x a m p l e s , w e frequently u s e d a p r e c i s e v a l u e of a to calculate the collector
3.9mAI
Off (2)
0
current. S i n c e a — 1, the error in such calculations will b e very small if o n e a s s u m e s a = 1 and i = i . Therefore, except in calculations that d e p e n d critically o n the v a l u e of a (e.g., the c
E
calculation of b a s e current), o n e u s u a l l y a s s u m e s a — I.
-5 V
-5 V
(a)
(b)
FIGURE 5 . 4 2 Example 5.12: (a) circuit; (b) analysis with the steps numbered. Forsthe circuit in Fig. 5.41. find die lolai current drawn from the power supply. Hence find the power dissipated in the circuit.
Solution
Ans. 4.135 m A ; 62 m W
By examining the circuit we conclude that the t w o transistors Q and Q cannot be simultay
2
neously conducting. T h u s if Q is on, Q will b e off, and vice versa. A s s u m e that Q is on. It l
2
2
4 3 5
436
CHAPTER 5
. . J
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.5
B I A S I N G IN B J T A M P L I F I E R C I R C U I T S
:
follows that current will flow from ground through the 1-kQ load resistor into the emitter of Q . Thus the base of Q will be at a negative voltage, and base current will be flowing out of the base through the 10-kO resistor and into the +5-V supply. This is impossible, since if the base is negative, current in the 10-kQ resistor will have to flow into the base. Thus w e conclude that our original assumption—that Q is on—is incorrect. It follows that Q will be off and <2i will be on. 2
|
2
2
2
T h e question n o w is whether g i is active or saturated. T h e answer in this case is obvious. Since the base is fed with a +5-V supply and since base current flows into the base of Q it follows that the base of Q will be at a voltage lower than +5 V. T h u s the c o l l e c t o r - b a s e junction of <2i is reverse biased and Q is in the active m o d e . It remains only to determine the currents and voltages using techniques already described in detail. T h e results are given in Fig. 5.42(b).
-OV .
-O
r
V
r
u
x
*R
^
x
l "1 (a)
(b)
EXERCISE FIGURE 5 . 4 3 Two obvious schemes for biasing the BJT: (a) by fixing V ; (b) by fixing I . Both result in wide variations in I and hence in V and therefore are considered to be "bad." Neither scheme is recommended. BE
c
5.31 Solve the problem in Example 5.12 with.the«voltage.feeding the bases changed;to -I-10 V. Assume that Z^,, = 30, a n d f i n d V , V . / , , , a n d / . . L
Ans.
w
(
B
CE
;
+4.8 V; +5.5 V; 4.35 mA: 0
V; 5.5
BIASING IN BJT AMPLIFIER CIRCUITS
T h e biasing p r o b l e m is that of establishing a constant dc current in t h e collector of the B J T . This current h a s to b e calculable, predictable, a n d insensitive to variations in temperature and to the large variations in the value of ¡3 e n c o u n t e r e d a m o n g transistors of the s a m e type. A n o t h e r i m p o r t a n t consideration in bias design is locating the dc bias point in the i ~ cE plane to allow for m a x i m u m output signal s w i n g (see the discussion in Section 5.3.3). In this section, w e shall deal with various approaches to solving the bias p r o b l e m in transistor circuits designed w i t h discrete devices. Bias m e t h o d s for integrated-circuit design are presented in C h a p t e r 6. v
c
Before p r e s e n t i n g the " g o o d " biasing s c h e m e s , w e should p o i n t out w h y t w o obvious a r r a n g e m e n t s are not good. First, attempting to bias t h e B J T b y fixing the voltage V by, for instance, using a v o l t a g e divider across t h e p o w e r supply V , as s h o w n in F i g . 5.43(a), is n o t a viable a p p r o a c h : T h e very sharp e x p o n e n t i a l relationship i - v m e a n s that any small and inevitable differences in V from t h e desired value will result in large differences in I and in V . S e c o n d , biasing t h e B J T b y establishing a constant current in the base, as s h o w n in Fig. 5.43(b), w h e r e I = (V - 0.7)/R , is also n o t a r e c o m m e n d e d approach. H e r e the typically large variations in the value of ¿8 a m o n g units of t h e s a m e device t y p e will result in c o r r e s p o n d i n g l y large variations in l and h e n c e in V . BE
(b)
(a)
FIGURE 5 . 4 4 Classical biasing for BJTs using a single power supply: (a) circuit; (b) circuit with the voltage divider supplying the base replaced with its Thevenin equivalent.
CC
c
B E
BE
c
F i g u r e 5.44(b) s h o w s t h e s a m e circuit w i t h t h e voltage-divider n e t w o r k replaced b y its T h e v e n i n equivalent,
CE
B
CC
R-,
B
c
V
=
B B
R
l
R
+
(5.68) 2
CE
R
R,
l
R
2
(5.69)
R + R l
5.5.1 The Classical Discrete-Circuit Bias Arrangement
2
T h e current I can b e d e t e r m i n e d by writing a Kirchhoff loop equation for the base-emitterground l o o p , labeled L , and substituting 1 — I /(/3+ 1): E
F i g u r e 5.44(a) s h o w s the a r r a n g e m e n t m o s t c o m m o n l y u s e d for biasing a discrete-circuit transistor amplifier if only a single p o w e r supply is available. T h e t e c h n i q u e consists of supp l y i n g t h e b a s e of the transistor with a fraction of t h e supply v o l t a g e V t h r o u g h t h e voltage divider R R . In addition, a resistor R is c o n n e c t e d to the emitter.
B
VBB-VBE
CC
h
2
E
E
R
E
+
(5.70) R /(ß+l) B
' 3 7
4 3 8
J
BIPOLAR JUNCTION TRANSISTORS (BJTs)
CHAPTER S
5.5 BIASING IN BJT AMPLIFIER CIRCUITS
T o m a k e I insensitive to t e m p e r a t u r e a n d ¡3 v a r i a t i o n , w e design t h e circuit to satisfy the following t w o constraints: 8
E
V
> V
BB
for possible signal swing at the collector. Thus, V
B
= +4V
V
E
= 4-V
(5.71)
BE
= 3.3V
B £
and R is determined from E
C o n d i t i o n ( 5 . 7 1 ) e n s u r e s t h a t s m a l l v a r i a t i o n s in V (=0.7 V) will be s w a m p e d by the m u c h l a r g e r V . T h e r e is a l i m i t , h o w e v e r , o n h o w l a r g e V c a n b e : F o r a g i v e n value of t h e s u p p l y v o l t a g e V , t h e h i g h e r t h e v a l u e w e u s e for V , t h e l o w e r w i l l b e t h e s u m of v o l t a g e s a c r o s s R a n d t h e c o l l e c t o r - b a s e j u n c t i o n (V ). O n t h e o t h e r h a n d , w e w a n t t h e v o l t a g e a c r o s s R t o b e l a r g e in o r d e r to o b t a i n h i g h v o l t a g e g a i n a n d l a r g e signal s w i n g (before t r a n s i s t o r c u t o f f ) . W e also w a n t V (or V ) to b e l a r g e t o p r o v i d e a large s i g n a l s w i n g (before t r a n s i s t o r s a t u r a t i o n ) . T h u s , as is t h e c a s e in a n y d e s i g n , w e h a v e a set of c o n f l i c t i n g r e q u i r e m e n t s , a n d t h e s o l u t i o n m u s t b e a c o m p r o m i s e . A s a r u l e of t h u m b , o n e d e s i g n s for V a b o u t | V , V (or V ) a b o u t | V , and I R about \V .
y„ 33 R„ = _ I = ±2 = 3.3 k Q
BE
BB
BB
cc
BB
c
From the discussion above w e select a voltage-divider current of 0 . 1 7
CB
c
CB
BB
cc
CB
£
= 0.1 x 1 = 0.1 m A .
Neglecting the base current, we find
CE
CE
cc
C
C
CC
C o n d i t i o n (5.72) m a k e s I insensitive to variations in ¡3 and could b e satisfied b y selecting R small. This in turn is achieved b y u s i n g l o w values for R and R . L o w e r values for R and R , h o w e v e r , will m e a n a h i g h e r current drain from the p o w e r supply, and will result in a l o w e r i n g of the input resistance of t h e amplifier (if the input signal is c o u p l e d to the base), w h i c h is t h e trade-off i n v o l v e d in this p a r t of t h e d e s i g n . It s h o u l d b e n o t e d that C o n d i t i o n (5.72) m e a n s that w e w a n t to m a k e the b a s e voltage i n d e p e n d e n t of t h e v a l u e of ¡3 and d e t e r m i n e d solely b y the voltage divider. T h i s will o b v i o u s l y b e satisfied if t h e current in the divider is m a d e m u c h larger than the b a s e current. T y p i c a l l y one selects R and R such that their current is in t h e r a n g e of I to 0 . 1 / .
R +R 1
= 2
H =
120 k Q
0.1
and
E
B
x
2
R
2
x
R
2
x
E
2
E
u
2
B
E
BE
E
V
= 4V
cc
2
E
nonzero base current. Using Eq. (5.70), I
F
= 3
E
R
x
2
E
+
Thus R = 4 0 k Q and R = 80 k Q . At this point, it is desirable to find a more accurate estimate for I , taking into account the
£
F u r t h e r insight regarding the m e c h a n i s m b y w h i c h t h e bias a r r a n g e m e n t of Fig. 5.44(a) stabilizes t h e dc emitter (and h e n c e collector) current is obtained b y c o n s i d e r i n g t h e feedb a c k action p r o v i d e d b y R . C o n s i d e r that for s o m e r e a s o n the emitter current increases. T h e v o l t a g e d r o p across R , and h e n c e V will increase correspondingly. N o w , if t h e b a s e voltage is d e t e r m i n e d primarily b y the v o l t a g e divider R R , w h i c h is t h e c a s e if R is small, it will r e m a i n constant, and the increase in V will result in a c o r r e s p o n d i n g decrease in V . This in turn reduces the collector (and emitter) current, a c h a n g e opposite to that originally a s s u m e d . T h u s R provides a negative feedback action that stabilizes t h e bias current. W e shall study n e g a t i v e feedback formally in C h a p t e r 8.
l
^-0J_ __ .3(kQ) + ( ^ H k Q )
=
0
9
^
3
This is quite a bit lower than the value w e are aiming for of 1 mA. It is easy to see from the above equation that a simple way to restore I to its nominal value would be to reduce R from 3.3 k Q by the magnitude of the second term in the denominator (0.267 kQ). Thus a more suitable value for R in this case would be R = 3 k Q , which results in I = 1.01 m A = 1 m A . It should be noted that if w e are willing to draw a higher current from the power supply and to accept a lower input resistance for the amplifier, then we may use a voltage-divider current equal, say, to 1 (i.e., 1 m A ) , resulting in R = 8 k Q and R = 4 k Q . W e shall refer to the circuit using these latter values as design 2, for which the actual value of I using the initial value of R of 3.3 k Q will be E
E
E
E
E
E
t
2
E
E
W e wish to design the bias network of the amplifier in Fig. 5.44 to establish a current I =1 E
using a power supply V
cc
4-0.7 3.3 + 0.027
=
a
9
9
^
l
^
mA
= +12 V. The transistor is specified to have a nominal ¡3 value of 100.
In this case, design 2, w e need not change the value of R . E
Finally, the value of R can be determined from c
Solution Rr = c
W e shall follow the rule of thumb mentioned above and allocate one-third of the supply voltage to the voltage drop across R and another one-third to the voltage drop across R , leaving one-third 2
1 2 - V ,c
J
c
Substituting I
c
Bias design seeks to stabilize either I or I since I = cd and a varies very little. That is, a stable I will result in an equally stable I , and vice versa. E
c
c
c
E
= cxI = 0.99 x 1 = 0.99 m A — 1 m A results, for both designs, in E
R
r
E
c
= ^—1
= 4 kQ
E
. 439
440
,
1
CHAPTER 5
5.5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
Vcc
Vcc
A
A
B I A S I N G IN B J T A M P L I F I E R C I R C U I T S
5.32 For design 1 in Example 5.13, calculate the expected range ofI if the transistor used has 8 in the range of 50 to 150. Express the range of I as a percentage of the nominal value (I — 1 m A ) obtained for 8= 100. Repeat for design 2. E
E
E
-°
Ans. For design 1: 0.94 m A to 1.04 m A a 10% range; for design 2: 0.984 m A to 0.995 m A , a 1.1%
Vc = VBE +
IBRB
range.
5.5.2 A Two-Power-Supply Version of the Classical Bias Arrangement
V
R
E
+ R /(B B
FIGURE 5 . 4 6 (a) A common-emitter transistor amplifier biased by a feedback resistor R . (b) Analysis of the circuit in (a). B
s h o w n in Fig. 5.45. W r i t i n g a loop equation for the loop labeled L gives
R
(b)
(a)
A s o m e w h a t simpler bias arrangement is possible if t w o p o w e r supplies are available, as
(5.73) + \)
T h i s e q u a t i o n is identical to Eq. (5.70) e x c e p t for V
EE
5.5.3 Biasing Using a Collector-to-Base Feedback Resistor
replacing V .
T h u s the t w o c o n
BB
Figure 5.46(a) s h o w s a s i m p l e b u t effective alternative b i a s i n g a r r a n g e m e n t suitable for
straints of E q s . (5.71) a n d (5.72) apply here as w e l l . N o t e that if t h e transistor is to b e u s e d
c o m m o n - e m i t t e r amplifiers. T h e circuit e m p l o y s a resistor R
w i t h t h e b a s e g r o u n d e d (i.e., in the c o m m o n - b a s e configuration), t h e n R
tor and t h e b a s e . R e s i s t o r R
B
can be eliminated
altogether. O n the other h a n d , if the input signal is to b e c o u p l e d to t h e b a s e , then R
B
is
n e e d e d . W e shall study t h e various B J T amplifier configurations in Section 5.7.
c o n n e c t e d b e t w e e n the collec
B
p r o v i d e s n e g a t i v e feedback, w h i c h h e l p s to stabilize the bias
B
point of the B J T . W e shall study feedback formally in C h a p t e r 8. A n a l y s i s of t h e circuit is s h o w n in Fig. 5.46(b), from w h i c h w e c a n w r i t e Vcc
= h c +h R
R
l R
V
B +
BE
E R
= hC
+ -p—^ B+V
BE
T h u s the emitter bias current is g i v e n by /
v
= E
cc-VBE + R /{L3+1)
R
C
{
5
M
)
B
It is interesting to n o t e that this e q u a t i o n is identical to E q . (5.70), w h i c h g o v e r n s the opera tion of the traditional b i a s circuit, e x c e p t that V
cc
replaces V
BB
and R
c
r e p l a c e s R . It follow E
that to obtain a v a l u e of I that is insensitive to variation of /3, w e select R /(B E
B
N o t e , h o w e v e r , that t h e v a l u e of R
B
FIGURE 5.45 Biasing the BJT using two power supplies. Resistor R is needed only if the signal is to be capacitively coupled to the base. Otherwise, the base can be connected directly to ground, or to a grounded signal source, resulting in almost total /3-independence of the bias current. B
+ 1)
R. c
d e t e r m i n e s t h e a l l o w a b l e signal s w i n g at t h e collector
since V
CB
= IR B
B
= h j ^
(5.75)
EXERCISE D5.33 The bias arrangement of Fig. 5.45 is to be used for a common-base amplifier. Design the circuit to establish a dc emitter current of 1 jrjA7?aadipo\aide-
0; R, - 4.3 k Q : A',
V4 kQ
D5.34 Design the circuit of Fig. 5.46 to nhi.un a dc emitter current ol" I m \ and in ensure a .'.2-\ signal swiiii: at the collector; that is, design for V - +2.3 V. Let V = 10 V and B = 100. CK
cc
Ans. R =\62 k O ; R = 7.7 k Q . Note that if standard 5 % resistor values are used (Appendix G) we select R = 160 k Q and R = 7.5 k Q . This results in I = 1.02 m A and V = +2.3 V. B
B
c
c
E
c
44
442
CHAPTER 5
BIPOLAR JUNCTION
TRANSISTORS
(BJTS)
5.6
5.6
O
SMALL-SIGNAL OPERATION A N D MODELS
SMALL-SIGNAL OPERATION AND MODELS
H a v i n g l e a r n e d h o w t o bias t h e B J T t o o p e r a t e as a n amplifier, w e n o w take a closer l o o k at t h e s m a l l - s i g n a l o p e r a t i o n of t h e transistor. T o w a r d that e n d , c o n s i d e r t h e conceptual circuit s h o w n i n F i g . 5.48(a). H e r e t h e b a s e - e m i t t e r j u n c t i o n is f o r w a r d b i a s e d b y a d c voltage V (battery). T h e r e v e r s e bias of t h e c o l l e c t o r - b a s e j u n c t i o n is e s t a b l i s h e d b y c o n n e c t i n g t h e c o l l e c t o r t o a n o t h e r p o w e r s u p p l y of v o l t a g e V t h r o u g h a resistor R . T h e input signal t o b e a m p l i f i e d is r e p r e s e n t e d b y t h e v o l t a g e s o u r c e v that is s u p e r i m p o s e d on V .
V
BE
CC
c
be
B E
W e consider first t h e dc bias conditions b y setting t h e signal v to zero. T h e circuit reduces to that in F i g . 5.48(b), a n d w e c a n write t h e following relationships for t h e d c cur rents a n d voltages: be
(a) 1
c =
I 1
(5.78) (5.79)
I /a c
(5.80)
B =
R
T h e B J T c a n b e biased using a constant-current source 7 as indicated in t h e circuit of F i g . 5.47(a). This circuit h a s t h e a d v a n t a g e that t h e emitter current is i n d e p e n d e n t of t h e val ues of / i and R . T h u s R c a n b e m a d e large, enabling an increase i n t h e input resistance at the b a s e without adversely affecting bias stability. Further, current-source biasing leads to significant design simplification, as will b e c o m e o b v i o u s in later sections a n d chapters. A simple implementation of t h e constant-current source I is s h o w n in F i g . 4.47(b). T h e circuit utilizes a pair of m a t c h e d transistors Q a n d Q , with Q c o n n e c t e d as a d i o d e b y shorting its collector t o its b a s e . If w e a s s u m e that Qi a n d Q h a v e h i g h /3 values, w e c a n neglect their b a s e currents. T h u s t h e current t h r o u g h Q , will b e a p p r o x i m a t e l y equal t o
• BE'
V
=
E
V
5.5.4 Biasing Using a Constant-Current Source
B
r
l
FIGURE 5 . 4 7 (a) A BJT biased using a constant-current source /. (b) Circuit for implementing the current source /.
V
(5.81)
cc ' h c
=
R F
R
V.
O b v i o u s l y , for a c t i v e - m o d e operation, V should b e greater than (V - 0.4) b y an a m o u n t that allows for a r e a s o n a b l e signal s w i n g at t h e collector. C
B
B
t
2
5.6.1 The Collector Current and the Transconductance If a signal v becomes
be
is applied as shown in Fig. 5.48(a), the total instantaneous base-emitter voltage v
BE
x
V
BE
2
(-v ) - v
Vr
EE
"be^ t
BE
\r
I r/ + V
V c C
+
BE
v )/V be
T
(v„/V )
T
T
e
5
-
(V
t
heE
BE
IREF
be
he (V /V )
N o w , since Q a n d Q h a v e t h e s a m e V , their collector currents will b e equal, resulting in 2
+ v
v
ic = he
R X
VBE
C o r r e s p o n d i n g l y , t h e collector current b e c o m e s
(5.76)
B
=
\r
E
E
- V
(5.77)
B
'1.
R
Neglecting t h e Early effect in Q , t h e collector current will r e m a i n constant at t h e value 2
given b y this equation as long as Q r e m a i n s in t h e active region. T h i s can b e g u a r a n t e e d by 2
k e e p i n g t h e voltage at t h e collector, V, greater t h a n that at t h e b a s e (-V
EE
-o
+ V ). T h e con BE
+
nection of Qi and Q in F i g . 4.47(b) is k n o w n as a c u r r e n t m i r r o r . W e will study current 2
V
mirrors in detail in C h a p t e r 6.
CE
v
BE
"
'cc
-
\ h
5.35 For the circuit in Fig."5.47(a) with V = 10 V, / ' = 1 m A , B = 100, R = 100 k Q , and R = 7.5 k Q . find Hie dc voltage at the base, the emitter, and the collector. F o r V = 10 V, find the required value of R in order for the circuit of Fig. 5.47(b) to implement the current-source I Ans. - 1 V; - 1 . 7 V; +2.6 V: 19.3 k Q CC
B
c
EE
(a)
(b)
FIGURE 5 . 4 8 (a) Conceptual circuit to illustrate the operation of the transistor as an amplifier, (b) The circuit of (a) with the signal source v eliminated for dc (bias) analysis. he
f &
4 4 3
444
CHAPTER 5
BIPOLAR J U N C T I O N TRANSISTORS
(BJTS)
5.6
SMALL-SIGNAL OPERATION AND MODELS
U s e of Eq. (5.78) yields Slope = g„ Vb /Vr
k N o w , if v
= Ice '
(5.82)
V , w e m a y a p p r o x i m a t e Eq. (5.82) as
be
T
* W c ( l
^ )
+
(5.83) Ic -
H e r e w e h a v e e x p a n d e d the exponential in E q . (5.82) in a series and retained only the first t w o terms. This approximation, w h i c h is valid only for v less t h a n approximately 10 m V , is referred to as the small-signal a p p r o x i m a t i o n . U n d e r this a p p r o x i m a t i o n the total collector current is given b y Eq. (5.83) and can b e rewritten be
i
= I +\fv
c
c
be
(5.84)
v
T
T h u s the collector current is c o m p o s e d of the dc bias v a l u e I and a signal c o m p o n e n t i , c
i
= ^ v
e
v
b
c
(5.85)
e
T
This equation relates the signal current in the collector to the c o r r e s p o n d i n g b a s e - e m i t t e r signal voltage. It can b e rewritten as h = 8rnV
(5-86)
be
FIGURE 5 . 4 9 Linear operation of the transistor under the small-signal condition: A small signal v with a triangular waveform is superimposed on the dc voltage V . It gives rise to a collector signal current i„ also of triangular waveform, superimposed on the dc current l . Here, i = g v , where g is the slope of the i -v curve at the bias point Q. be
where g
BE
is called the t r a n s c o n d u c t a n c e , and from Eq. (5.85), it is given b y
m
g
m
c
= jr
c
m
he
m
c
BE
(5.87)
v
T
W e o b s e r v e that the t r a n s c o n d u c t a n c e of the B J T is directly proportional to the collector bias current I . T h u s to obtain a constant predictable value for g , w e n e e d a constant pre dictable I . Finally, w e note that B J T s h a v e relatively h i g h t r a n s c o n d u c t a n c e (as compared to M O S F E T s , w h i c h w e studied in Chapter 4); for instance, at l = 1 m A , g — 4 0 m A / V . A graphical interpretation for g is given in Fig. 5.49, w h e r e it is s h o w n that g is equal to the slope of the i -v characteristic curve at i — I (i.e., at the bias p o i n t Q). T h u s , c
BJTs h a v e finite output resistance b e c a u s e of the Early effect. T h e effect of the output resis tance on amplifier p e r f o r m a n c e will b e considered later.
m
c
c
m
m
c
m
BE
c
5.36 L'^c l-.q. (5.88) to derive the expression for g in Eq. (5.87). m
c
dip
(5.88)
5.6.2 The Base Current and the input Resistance at the Base
dv
BE
T h e small-signal approximation implies k e e p i n g the signal a m p l i t u d e sufficiently small so that operation is restricted to an almost-linear segment of the i -v exponential curve. Increasing the signal amplitude will result in the collector current h a v i n g c o m p o n e n t s nonlinearly related to v . This, of course, is the s a m e a p p r o x i m a t i o n that w e discussed in the context of the amplifier transfer c u r v e in Section 5.3. c
To determine the resistance seen by v , Eq. (5.84), as follows: he
be
T h e analysis a b o v e suggests that for small signals (v
w e first evaluate the total b a s e current i
B
using
BE
B
~ B ~
+
Vbe
p pV
T
Thus,
T
h = h +h
(5.89)
where I is equal to 7 / / 3 and the signal c o m p o n e n t i is given by B
c
b
m
h = )±vu
(5.90)
Z^t:
445
CHAPTER 5
5.6
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTs)
Substituting for I /V C
by g
T
m
SMALL-SIGNAL OPERATION A N D MODELS
447
Thus,
gives
\
8
h = -fv
r
r
=
r
=iß+\)r
K
(i /ib) e e
(5.91)
be
which yields T h e small-signal i n p u t r e s i s t a n c e b e t w e e n b a s e a n d emitter, looking
into the base, is denoted
K
(5.100)
e
b y r a n d is defined as %
v, = ^
r
n
(5.92)
U s i n g E q . (5.91) gives
5.37 A B J T having / i = 100 is biased at a dc collector current of I mA. Find the value of,?,,,, r , and /\.al the bias point. e
= -£
(5.93)
T h u s r is directly d e p e n d e n t o n ¡3 a n d is inversely p r o p o r t i o n a l to t h e bias current I . n
c
tuting for g
m
in E q . (5.93) from E q . (5.87) a n d r e p l a c i n g I /B c
by I
B
Ans. 40 mA/V; 25 Q ; 2.5 k Q
Substi-
gives an alternative
e x p r e s s i o n for r„,
5.6.4 Voltage Gain In the preceding section w e h a v e established only that the transistor senses the b a s e - e m i t t e r
r
= ^
K
(5.94)
signal v
be
and causes a proportional current g v m
to flow in the collector lead at a high (ideally
be
infinite) i m p e d a n c e level. In this w a y the transistor is acting as a voltage-controlled current source. T o obtain an output voltage signal, w e m a y force this current to flow through a resistor,
5.6.3 The Emitter Current and the Input Resistance at the Emitter
as is d o n e in Fig. 5.48(a). T h e n the total collector voltage v will b e c
v
c
T h e total emitter current i c a n b e d e t e r m i n e d from
v
=
R
cc~ic c
E
= V l
l;
F
_— C
_ C —
a
a
7
, i-
c c
-(I
+
c
i )R c
c
(5 101)
h a =
V -i R c
c
c
Thus, H e r e the quantity V is t h e d c bias v o l t a g e at t h e collector, a n d the signal v o l t a g e is g i v e n b y c
i
= h +i
E
(5-95)
e
R
V
= ~i C
c
w h e r e I is e q u a l to I /a E
c
c
a n d t h e signal current i is g i v e n b y e
c
i
= - = — v a aV
e
h b
= ^ v V
(5.96)
-8mV C be
R
=
h
e
T
R
= (-8m c)v
be
Thus the v o l t a g e gain of this amplifier A
v
is
be T
If w e d e n o t e t h e small-signal resistance b e t w e e n b a s e a n d emitter, looking
into the
K=
emitter,
b y r , it c a n b e defined as e
H e r e again w e n o t e that b e c a u s e g
m
r. = ^ h
(5-97)
—
R
= ~g c
(5.103)
m
is directly p r o p o r t i o n a l to the collector bias current,
the g a i n will b e as s t a b l e as t h e c o l l e c t o r b i a s c u r r e n t is m a d e . S u b s t i t u t i n g for g
m
from
Eq. (5.87) e n a b l e s u s to express the gain in the f o r m
U s i n g E q . (5.96) w e find that r , called t h e e m i t t e r r e s i s t a n c e , is given b y e
r e
= ¥l h
(5.98) which is identical to t h e e x p r e s s i o n w e d e r i v e d in Section 5.3 (Eq. 5.56).
C o m p a r i s o n w i t h E q . (5.87) r e v e a l s that « 8m
~
1
(5.99)
8m
T h e relationship b e t w e e n r„ a n d r c a n b e f o u n d b y c o m b i n i n g their r e s p e c t i v e definitions in
5.38 In the circuit of Fig. 5.48(a), V
nr
is adjusted to yield a dc collector current of 1 mA. Ect V
cr
= 15 V .
e
E q s . (5.92) a n d (5.97) as
R = 10 k Q . and B = 100. Find the voltage gain i\./v .. c
Ans. - 4 0 0 V/V; 5 - 2 s'mwt volts: 10 + 2 sinew /jA
bl
If v,„ = 0 . 0 0 5 sin cot \ o l l s , find v,{t) and
i (f). n
4 4 8
iZï
CHAPTER 5
5.6
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
the base, r . T h e m o d e l obviously yields i = g v
5.6.5 Separating the Signal and the DC Quantities
K
T h e analysis a b o v e indicates that every current and v o l t a g e in t h e amplifier circuit of Fig. 5.48(a) is c o m p o s e d of t w o c o m p o n e n t s : a dc c o m p o n e n t a n d a signal c o m p o n e n t . F o r instance, v
BE
=V
BE
c
m
be
SMALL-SIGNAL OPERATION AND MODE
and i = v /r . b
be
%
N o t so obvious, however,
is the fact that the m o d e l also yields the correct expression for i . This can b e shown as follows: e
A t the emitter n o d e w e h a v e
+ v , 1 = I + i , and so on. T h e dc c o m p o n e n t s are d e t e r m i n e d from the be
C
C
c
d c circuit given in Fig. 5.48(b) and from the relationships i m p o s e d b y the transistor (Eqs. 5.78 t h r o u g h 5.81). O n t h e other h a n d , a r e p r e s e n t a t i o n of t h e s i g n a l o p e r a t i o n of t h e B J T c a n b e obtained b y eliminating the d c s o u r c e s , as s h o w n in Fig. 5.50. O b s e r v e that since the voltage of a n ideal dc supply does not c h a n g e , the signal v o l t a g e across it will b e zero. For this r e a s o n w e h a v e r e p l a c e d V
cc
and V
BE
=
w i t h short circuits. H a d t h e circuit c o n t a i n e d ideal
d c current sources, t h e s e w o u l d h a v e b e e n r e p l a c e d b y o p e n circuits. N o t e , h o w e v e r , that the circuit of Fig. 5.50 is useful only in so far as it s h o w s t h e v a r i o u s signal currents a n d volt-
v /r be
e
A slightly different e q u i v a l e n t circuit m o d e l can b e obtained b y e x p r e s s i n g the current of the controlled s o u r c e (g v ) m
be
in terms of the b a s e current i as follows: b
a g e s ; it is not an actual amplifier circuit s i n c e the dc bias circuit is n o t s h o w n . Figure 5.50 also shows the expressions for the current increments (i , i , and i ) obtained c
w h e n a small signal v
be
b
e
is applied. These relationships can b e represented b y a circuit. Such a cir-
cuit should have three terminals—C, B , and E — a n d should yield the same terminal currents indicated in Fig. 5.50. T h e resulting circuit is then equivalent
to the transistor
as far as
small-signal
= (g r„)h m
=
fii
b
This results in the alternative e q u i v a l e n t circuit m o d e l s h o w n in F i g . 5.51(b). H e r e t h e transistor is r e p r e s e n t e d as a current-controlled current source, with the control current b e i n g i . b
operation
is concerned,
and thus it can b e considered an equivalent small-signal circuit model.
T h e t w o m o d e l s of F i g . 5.51 are simplified versions of w h a t is k n o w n as the hybrid-TI model. This is t h e m o s t w i d e l y used m o d e l for the B J T .
5.6.6 The Hybrid-^ Model
It is i m p o r t a n t to n o t e that the small-signal e q u i v a l e n t circuits of Fig. 5.51 m o d e l the
A n equivalent circuit model for the B J T is s h o w n in Fig. 5.51(a). This m o d e l represents the B J T as a voltage-controlled current source and explicitly includes the input resistance looking into
operation of the B J T at a given bias point. T h i s should be o b v i o u s from the fact that the m o d e l p a r a m e t e r s g
m
and r d e p e n d on the v a l u e of the dc bias current I , as indicated in K
c
Fig. 5 . 5 1 . Finally, although the m o d e l s h a v e b e e n d e v e l o p e d for an npn transistor, they apply equally well to a pnp transistor with no change
of
polarities.
5.6.7 The T Model Although the h y b r i d - ^ m o d e l (in one of its two variants shown in Fig. 5.51) can b e used to c a n y out small-signal analysis of all transistor circuits, there are situations in which an alternative model, shown in Fig. 5.52, is m u c h m o r e convenient. This model, called the T m o d e l , is shown
Vbe
FIGURE 5 . 5 0 The amplifier circuit of Fig. 5.48(a) with the dc sources (V and V ) eliminated (short circuited). Thus only the signal components are present. Note that this is a representation of the signal operation of the BJT and not an actual amplifier circuit. BE
C
C
E
E
cc
(a)
FIGURE 5 . 5 1 Two slightly different versions of the simplified hybrid-jrmodel for the small-signal operation of the BJT. The equivalent circuit in (a) represents the BJT as a voltage-controlled current source (a transconductance amplifier), and that in Ob) represents the BJT as a current-controlled current source (a current amplifier).
(b)
FIGURE 5 . 5 2 Two slightly different versions of what is known as the Tmodel of the BJT. The circuit in (a) is a voltage-controlled current source representation and that in (b) is a current-controlled current source representation. These models explicitly show the emitter resistance r rather than the base resistance r featured in the hybrid-^: model. e
%
4 5 0
ïà£
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.6
V
in t w o versions in Fig. 5.52. T h e m o d e l of Fig. 5.52(a) represents the B J T as a voltage-controlled current source with the control voltage being v . Here, however, the resistance between base and emitter, looking into the emitter, is explicitly shown. F r o m Fig. 5.52(a) w e see clearly that the model yields the correct expressions for i and i . F o r i w e note that at the base node w e have
cc
SMALL-SIGNAL OPERATION A N D MODELS
= +10 V
+ 10 V
be
c
e
2.3 mA Rr = 3 kfl
b
+3 V R
= 100 k û
-vw—r
RR
Y O 03+IK
0.023 mA
±-V
r
2.323 mA
= 3V
BB
%
à +0.7 V
as should b e t h e c a s e . If in t h e m o d e l of Fig. 5.52(a) t h e current of t h e controlled source is e x p r e s s e d in terms (a)
of t h e emitter current as follows:
(b)
gm^be ~ gnSSe^e) = (g r )i m
e
e
=
R
«i
BB
e
= 100 k O i—AAA?—o—
O
v„
r
= 3 kfl
w e obtain t h e alternative T m o d e l s h o w n in F i g . 5.52(b). H e r e t h e B J T is represented as a current-controlled current source b u t w i t h t h e control signal b e i n g i . e
R
5.6.8 Application of the Small-Signal Equivalent Circuits T h e availability of t h e small-signal B J T circuit m o d e l s m a k e s t h e analysis of transistor amplifier circuits a systematic p r o c e s s . T h e p r o c e s s consists of t h e following steps: (C)
1. D e t e r m i n e t h e d c operating point of t h e B J T a n d in particular t h e d c collector current I . c
2. Calculate the values of the small-signal m o d e l parameters: g
m
r =V /I = e
T
= I /V , C
T
r = B/g , n
m
and
FIGURE 5 . 5 3 Example 5.14: (a) circuit; (b) dc analysis: (c) small-signal model. Mr
a/g .
E
m
3. E l i m i n a t e t h e d c sources b y r e p l a c i n g e a c h d c v o l t a g e source with a short circuit and
The dc collector current will be
each d c current source w i t h an o p e n circuit.
I
= PI
c
B
= 100 x 0.023 = 2.3 m A
4. R e p l a c e t h e B J T w i t h o n e of its small-signal e q u i v a l e n t circuit m o d e l s . A l t h o u g h any o n e of t h e m o d e l s can b e used, o n e m i g h t b e m o r e c o n v e n i e n t t h a n t h e others for the
The dc voltage at the collector will be
particular circuit b e i n g analyzed. This point will b e m a d e clearer later in this chapter. R
Vc = V
5. A n a l y z e t h e resulting circuit t o d e t e r m i n e t h e r e q u i r e d quantities (e.g., voltage gain,
c c
-Ic c
= + 1 0 - 2 . 3 x 3 =+3.1 V
input resistance). T h e p r o c e s s will b e illustrated b y t h e following e x a m p l e s .
Since V at +0.7 V is less than V , it follows that in the quiescent condition the transistor will be operating in the active mode. T h e dc analysis is illustrated in Fig. 5.53(b). B
c
Having determined the operating point, we m a y now proceed to determine the small-signal model parameters: W e wish to analyze the transistor amplifier shown in Fig. 5.53(a) to determine its voltage gain. V
Assume / J = 100.
T
I
E
25 m V = 10.8 Q (2.3/0.99) mA
Solution The first step in the analysis consists of determining the quiescent operating point. For this purpose
V
25 m V
T
we assume that v = 0. The dc base current will be t
,
_
VBE-VBE BB
3-07 = — — 100
r,=
£ gm
K
= 0.023 m A
= f
=1.09*0 y
z
To carry out the small-signal analysis it is equally convenient to employ either of the two hybrid-n equivalent circuit models of Fig. 5.51. Using the first results in the amplifier equivalent
.>
451
452
CHAPTER 5
BIPOLAR JUNCTION
TRANSISTORS
(BJTS)
5.6
SMALL-SIGNAL OPERATION AND MODELS
circuit given in Fig. 5.53(c). Note that no dc quantities are included in this equivalent circuit. It i most important to note that the dc supply voltage V has been replaced by a short circuit in the signal equivalent circuit because the circuit terminal connected to V will always have a con stant voltage; that is, the signal voltage at this terminal will be zero. In other words, a circuit terminal connected to a constant dc source can always be considered as a signal ground. Analysis of the equivalent circuit in Fig. 5.53(c) proceeds as follows:
s
cc
cc
'r„ + R
E
(5.105) 1.09 = 0.01 '101.09
\V:
The output voltage v is given by 0
v
R
-gm be C
-3.04w
-92x0.011u,x3
;
Thus the voltage gain will be A„ = — = - 3 . 0 4 V / V
(5.106)
where the minus sign indicates a phase reversal.
To gain more insight into the operation of transistor amplifiers, we wish to consider the waveforms at various points in the circuit analyzed in the previous example. For this purpose assume that v has a triangular waveform. First determine the maximum amplitude that is allowed to have. Then, With the amplitude of v set to this value, give the waveforms of i (t), v (t), i (t), and v (t). t
t
B
BE
c
c
A i (mA) A c
Solution
I = 2.3 mA 1
ic
c
One constraint on signal amplitude is the small-signal approximation, which stipulates that v should not exceed about 10 mV. If w e take the triangular waveform v to be 20 m V peak-to-peak and work backward, Eq. (5.105) can be used to determine the maximum possible peak of v
3
be
be
-
r
/
y
/ V -
it
Vbe
0.011
1
10 0.011
0.91V
' t ' 1
ic
1 = Q8. mA
1
0
To check whether or not the transistor remains in the active mode with v having a peak value Vi = 0.91 V, we have to evaluate the collector voltage. The voltage at the collector will consist of a triangular wave v superimposed on the dc value V = 3.1 V. The peak voltage of the triangu lar waveform will be
i
2
t
c
c
Vc
(d) % (V) A
V,-x gain = 0.91 x 3.04 = 2.77 V i'
It follows that when the output swings negative, the collector voltage reaches a minimum of 3.1 - 2.77 = 0.33 V, which is lower than the base voltage by less than 0.4 V. Thus the transistor will remain in the active mode with v having a peak value of 0.91 V. Nevertheless, we will use a somewhat lower value for V,- of approximately 0.8 V, as shown in Fig. 5.54(a), and complete the analysis of this problem. The signal current in the base will be triangular, with a peak value I of t
b
FIGURE 5 . 5 4 Signal waveforms in the circuit of Fig. 5.53.
V = 3.1V C
*»-
,1
453
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.6
This triangular-wave current will be superimposed on the quiescent base current I , as shown in Fig. 5.54(b). The base-emitter voltage will consist of a triangular-wave component superimposed on the dc V that is approximately 0.7 V. The peak value of the triangular waveform will be
SMALL-SIGNAL OPERATION A N D MODELS
B
Jh. re •ai Rc
BE
Vbe = Vi—\r +R K
The total v
BE
BB
e
= 0 . 8 — ^ — = 8.6 m V 100+1.09
-v,
is sketched in Fig. 5.54(c).
The signal current in the collector will b e triangular in waveform, with a peak value I given by c
I
c
= Bh = 100 x 0.008 = 0.8 m A
This current will b e superimposed on the quiescent collector current I (=2.3 m A ) , as shown in Fig. 5.54(d). c
Finally, the signal voltage at the collector can be obtained by multiplying v by the voltage gain; that is, t
V
c
= 3.04 x 0.8 = 2.43 V
Fi gure 5.54(e) shows a sketch of the total collector voltage v versus time. Note the phase reversal between the input signal v and the output signal v . c
t
(c)
(d)
c
FIGURE 5 . 5 5 (Continued) (c) small-signal model; (d) small-signal analysis performed directly on the circuit.
Solution We shall start by determining the dc operating point as follows (see Fig. 5.55b): W e need to analyze the circuit of Fig. 5.55(a) to determine the voltage gain and the signal waveforms at various points. T h e capacitor C is a coupling capacitor whose purpose is to couple the signal v to the emitter while blocking dc. In this way the dc bias established by V and V~ together with R and R will not be disturbed when the signal w, is connected. For the purpose of this example, C will b e assumed to be very large and ideally infinite—that is, acting as a perfect short circuit at signal frequencies of interest. Similarly, another very large capacitor is used to couple the output signal v to other parts of the system. +
h =
+10-V
E
+10-0.7
£
10
R*
{
= 0.93 m A
c
0
+
V
+ 10 V
A
R
F
J
= 10 kfl
I
= 0.997
c
= -10 + IrRc
V
c
E
= 0.92 m A
= - 1 0 + 0.92x5 = -5.4 V
+ 10 V 0.93 mA
Assuming ß= 100, then a = 0.99, and
10 kfl +0.7 V o -
C = oo
Thus the transistor is in the active mode. Furthermore, the collector signal can swing from - 5 . 4 V to +0.4 V (which is 0.4 V above the base voltage) without the transistor going into saturation. However, a negative 5.8-V swing in the collector voltage will (theoretically) cause the minimum collector voltage to be - 1 1 . 2 V, which is more negative than the power-supply voltage. It follows that if we attempt to apply an input that results in such an output signal, the transistor will cut off and the negative peaks of the output signal will be clipped off, as illustrated in Fig. 5.56. The waveform in Fig. 5.56, however, is shown to be linear (except for the clipped peaks); that is, the effect of the nonlinear i -v characteristic is not taken into account. This is not correct, since if we are driving the transistor into cutoff at the negative signal peaks, then we will surely be exceeding the small-signal limit, as will be shown later. c
R
oo
—
-° v„ R
r
=
= 0 . 9 2 mAJ
-o - 5 . 4 V
5m
V~ = • •10 V (a) FIGURE 5 . 5 5 Example 5.16: (a) circuit; (b) dc analysis;
5 kfl
T -10 V (b)
BE
Let us n o w proceed to determine the small-signal voltage gain. Toward that end, we eliminate the dc sources and replace the BJT with its T equivalent circuit of Fig. 5.52(b). Note that because the base is grounded, the T model is somewhat more convenient than the hybrid-;? model. Nevertheless, identical results can be obtained using the latter. Figure 5.55(c) shows the resulting small-signal equivalent circuit of the amplifier. The model parameters are a = 0.99 25 m V 0.93 m A
27 Q
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.6
SMALL-SIGNAL OPERATION A N D MODELS
' ^ V
4 5 7
"c ( V ) i >- t
5.39 To increase the voltage gain of the amplifier analyzed in Example 5.16, the collector resistance li is increased to 7.5 k £ l Find the new values of V , A,., and the peak amplitude of the output sine wave corresponding to an input sine wave w of 10 mV peak. Ans. - 3 . 1 \ : 27.s \ . \ 2 . 7 5 \
c
c
Negative peaks clipped owing to cutoff
:
FIGURE 5 . 5 6 Distortion in output signal due to transistor cutoff. Note that it is assumed that no distortion due to the transistor nonlinear characteristics is occurring.
Analysis of the circuit in Fig. 5.55(c) to determine the output voltage v and hence the voltage gain v /v is straightforward and is given in the figure. The result is a
0
t
A
v
= ^
= 183.3 V / V
Note that the voltage gain is positive, indicating that the output is in phase with the input signal. This property is due to the fact that the input signal is applied to the emitter rather than to the base, as was done in Example 5.14. W e should emphasize that the positive gain has nothing to do with the fact that the transistor used in this example is of the pnp type. Returning to the question of allowable signal magnitude, w e observe from Fig. 5.55(c) that v = Wj. Thus, if small-signal operation is desired (for linearity), then the peak of v should be lim ited to approximately 10 m V . With Vi set to this value, as shown for a sine-wave input in Fig. 5.57, eb
5.6.9 Performing Small-Signal Analysis Directly on the Circuit Diagram In most cases one should explicitly replace each B J T with its small-signal m o d e l and analyze the resulting circuit, as w e h a v e done in the examples above. This systematic procedure is par ticularly r e c o m m e n d e d for beginning students. Experienced circuit designers, however, often perform a first-order analysis directly on the circuit. Figure 5.55(d) illustrates this process for the circuit w e h a v e j u s t analyzed. T h e reader is urged to follow this direct analysis procedure (the steps are n u m b e r e d ) . Observe that the equivalent circuit m o d e l is implicitly utilized; w e are only saving the step of drawing the circuit with the B J T replaced with its model. Direct analysis, however, has an additional very important benefit: It provides insight regarding the signal transmission through the circuit. S u c h insight can p r o v e invaluable in design, particu larly at the stage of selecting a circuit configuration appropriate for a given application.
t
v, (mV)
5.6.10 Augmenting the Small-Signal Models to Account for the Early Effect T h e Early effect, discussed in Section 5.2, causes the collector current to depend not only o n v but also on v . T h e dependence on v can b e m o d e l e d by assigning a finite output resis tance to the controlled current-source in the h y b r i d - n m o d e l , as s h o w n in Fig. 5.58. T h e output resistance r w a s defined in Eq. (5.37); its value is given by r = (V + V )/I — V /I , where V is the Early voltage and V and I are the coordinates of t h e dc bias point. N o t e that in the m o d e l s of Fig. 5.58 w e h a v e r e n a m e d v as v„, in order to conform with the literature. BE
CE
CE
0
0
A
v
c
(V)A
CE
A
CE
C
A
C
c
be
-2 1.8 V
B o-
-o C
-o C
B o-
-4 'V
-6
<
r,
-8 -10 E FIGURE 5 . 5 7 Input and output waveforms for the circuit of Fig. 5.55. Observe that this amplifier is noninverting, a property of the common-base configuration.
E (a)
(b)
FIGURE 5 . 5 8 The hybrid-:? small-signal model, in its two versions, with the resistance r included. a
4 5 8
.„I
CHAPTERS
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
5.6
T h e question arises as to the effect of r o n t h e operation of t h e transistor as an amplifier. In amplifier circuits in w h i c h the emitter is g r o u n d e d (as in the circuit of F i g . 5.53), r simply appears in parallel w i t h R . T h u s , if w e i n c l u d e r in t h e equivalent circuit of F i g . 5.53(c), for e x a m p l e , t h e output v o l t a g e v b e c o m e s
SMALL-SIGNAL OPERATION A N D MODELS
a
TA8LÏ: .5.4
a
c
Smali-Signa! Models of t h e BJT
0
Hybrid-* Model
0
v
0
= -g v (R m
be
c
V r)
B
0
(g v ) Version m
K
(ßi ) Version b
T h u s the g a i n will b e s o m e w h a t r e d u c e d . O b v i o u s l y if r §> R , t h e r e d u c t i o n in gain will b e negligible, a n d o n e can ignore the effect of r . In general, in s u c h a configuration r c a n b e neglected if it is greater than 107? . W h e n t h e emitter of t h e transistor is n o t g r o u n d e d , i n c l u d i n g r in t h e m o d e l c a n c o m p l i cate the analysis. W e will m a k e c o m m e n t s r e g a r d i n g r a n d its inclusion or e x c l u s i o n o n frequent occasions t h r o u g h o u t t h e b o o k . W e should also n o t e that in integrated-circuit B J T amplifiers, r plays a d o m i n a n t role, as will b e seen in C h a p t e r 6. Of c o u r s e , if o n e is performing an accurate analysis of an almost-final design using c o m p u t e r - a i d e d analysis, then r can b e easily i n c l u d e d (see Section 5.11). 0
c
0
BO-
0
-oC
Bo-
4>
- o c
c
a
0
TP«..
0
0
Finally, it should b e noted that either of the T m o d e l s in Fig. 5.52 can b e a u g m e n t e d to account for the Early effect b y i n c l u d i n g r b e t w e e n collector and emitter. a
T Model
5.6.11 Summary
•
(g vJ
Version
m
(ai) Version
C o
T h e analysis and design of B J T amplifier circuits is greatly facilitated if t h e relationships b e t w e e n t h e various small-signal m o d e l .parameters are at y o u r fingertips. F o r easy reference, these are s u m m a r i z e d in T a b l e 5.4. O v e r time, h o w e v e r , w e expect t h e r e a d e r to b e able t o recall these from m e m o r y .
C Q
4> 5.40 T h e transistor in Fig. E5.40 is biased with a constant current source 7 = 1 m A and has /3 = 100 and V = 100 V. (a) Find the dc voltages at the base, emitter, and collector, (b) Find g , r , and r„. (c) If terminal Z is connected to ground, X to a signal source r», with a source resistance 7? = 2 k f l , and Y to an 8-kQ load resistance, use the hybrid-;: model of Fig. 5.58(a), to draw the small-signal equivalent circuit - . • " • of the amplifier. (Note that the current source / should be replaced with an open circuit.)-Calculate the overall voltage gain v /v . If r is neglected what is the error in estimating the gain magnitude? (Note: A n infinite capacitance is used to indicate that the capacitance is sufficiently large that it acts as a short circuit at all signal frequencies of interest. However, the capacitor still blocks dc.) A
m
lg
y
iig
Bo-
Be-
x
sig
'I
a
Model Parameters in Terms of DC Bias Currents
- PA
r
°~ o
Y In Terms of g
m
r = « 'e
- ß
r
f
5m
g
K
m
•O Z In Terms of r
e
om
T
FIGURE E5.40
Ans. (a) - 0 . 1 V, - 0 . 8 V, + 2 V; (b) 4 0 mA/V, 2.5
Ml, 100 k O ; (c) - 7 7
r =(ß+l)r K
Relationships Between A and /j V / V , +3.9%
e
g + i = ^m
Ic
'
4 5 9
4 6 0
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.7
SINGLE-STAGE BJT AMPLIFIERS
5.7 SINGLE-STAGE BJT AMPLIFIERS W e h a v e studied t h e l a r g e - s i g n a l o p e r a t i o n of B J T amplifiers in S e c t i o n 5.3 a n d identified t h e r e g i o n o v e r w h i c h a p r o p e r l y b i a s e d t r a n s i s t o r can b e o p e r a t e d as a linear amplifier for s m a l l signals. M e t h o d s for dc b i a s i n g t h e B J T w e r e studied in S e c t i o n 5.5, a n d a detailed s t u d y of s m a l l - s i g n a l amplifier o p e r a t i o n w a s p r e s e n t e d in S e c t i o n 5.6. W e are n o w r e a d y to c o n s i d e r p r a c t i c a l transistor amplifiers, a n d w e will d o so in this s e c t i o n for circuits suitable for discrete-circuit fabrication. T h e design of integrated-circuit B J T amplifiers will b e studied in C h a p t e r 6.
5.41 Consider (he circuit of Fig. 5.59 for the case: \ ' . - * ! r = 10 V. / = I mA, R = 100 k Q , R = 8 kQ, and ¡5= 100. Find all dc currents and voltages. W h a t aresthe allowable signal swings at the collector in both directions'.' How do these values change as B is changed to 50? T o 20Q? Find the values of the BJT small-signal parameters at the bias point (with B= 100). The Early voltage V = 100 V. f r
B
c
A
Ans. Sec Fig. E5.41. Signal swing: for B= 100. +8 V. -3.4 V; for B= 50, +8 V, - 4 . 4 V; for B= 200, + 8 V , - 2 . 9 V. •I-10 V
T h e r e are b a s i c a l l y t h r e e c o n f i g u r a t i o n s for i m p l e m e n t i n g s i n g l e - s t a g e B J T amplifiers: t h e c o m m o n - e m i t t e r , t h e c o m m o n - b a s e , a n d t h e c o m m o n - c o l l e c t o r c o n f i g u r a t i o n s . A l l t h r e e are s t u d i e d b e l o w , u t i l i z i n g t h e s a m e b a s i c s t r u c t u r e w i t h t h e s a m e b i a s i n g arrangement.
0.99 = 1 m A J
<
=0.01 mA
5.7.1 The Basic Structure
- 1 V o
F i g u r e 5.59 s h o w s the basic circuit that w e shall utilize to i m p l e m e n t the various configurations of B J T amplifiers. A m o n g the various biasing s c h e m e s possible for discrete B J T amplifiers (Section 5.5), w e h a v e selected, for simplicity and effectiveness, t h e o n e e m p l o y ing constant-current biasing. F i g u r e 5.59 indicates the dc currents in all b r a n c h e s and the dc voltages at all n o d e s . W e should n o t e that o n e w o u l d w a n t to select a large v a l u e for R in order to k e e p the input resistance at t h e b a s e large. H o w e v e r , w e also w a n t to limit the dc voltage d r o p across R and even m o r e importantly t h e variability of this dc v o l t a g e resulting from the variation in /3 values a m o n g transistors of the s a m e t y p e . T h e dc voltage V determ i n e s the a l l o w a b l e signal s w i n g at t h e collector.
f-
loo k n ^
:
-o=+2V
^
•• C
Bo-
B
-o -1.7 V
B
ß = 100 a = 0.99
B
V,I =
-10 v
1.00 V
g = 40 mA/V r = 25 Q m
r = 100 k.Q r = 2.5 k f l 0
v
B
(a)
(b)
FIGURE E5.41
Vcc
5.7.2 Characterizing BJT Amplifiers
À
-°V = C
IKg V = - „ , . oß+ 1
V
cc
-
aR I c
I = I/(ß + 1) > B
p
~®
IR„
yr
——ß
+
+V
1
BE
9
A s w e b e g i n o u r s t u d y of B J T amplifier circuits, it is i m p o r t a n t to k n o w h o w to c h a r a c t e r ize t h e p e r f o r m a n c e of amplifiers as circuit b u i l d i n g b l o c k s . A n i n t r o d u c t i o n to this s u b j e c t w a s p r e s e n t e d in S e c t i o n 1.5. H o w e v e r , t h e m a t e r i a l of S e c t i o n 1.5 w a s limited to unilateral a m p l i f i e r s . A n u m b e r of t h e amplifier circuits w e shall study in this b o o k are not unilateral; that is, t h e y h a v e internal f e e d b a c k that m a y c a u s e their i n p u t r e s i s t a n c e to d e p e n d o n t h e l o a d r e s i s t a n c e . Similarly, internal f e e d b a c k m a y c a u s e t h e o u t p u t r e s i s tance to d e p e n d o n t h e v a l u e of t h e r e s i s t a n c e of t h e signal s o u r c e feeding t h e amplifier. T o a c c o m m o d a t e n o n u n i l a t e r a l a m p l i f i e r s , w e p r e s e n t in T a b l e 5.5 a g e n e r a l set of p a r a m e t e r s a n d e q u i v a l e n t circuits that w e will e m p l o y in c h a r a c t e r i z i n g and c o m p a r i n g transistor a m p l i f i e r s . A n u m b e r of r e m a r k s are in order: 1. T h e amplifier in T a b l e 5.5 is s h o w n fed w i t h a signal s o u r c e h a v i n g an open-circuit v o l t a g e v a n d an internal r e s i s t a n c e i ? . T h e s e can b e t h e p a r a m e t e r s of an actual signal s o u r c e or t h e T h e v e n i n e q u i v a l e n t of the o u t p u t circuit of a n o t h e r amplifier stage p r e c e d i n g t h e o n e u n d e r study in a c a s c a d e amplifier. Similarly, R can b e an actual load resistance or the input resistance of a succeeding amplifier stage in a cascade amplifier.
0
sig
sig
L
FIGURE 5 . 5 9 Basic structure of the circuit used to realize single-stage, discrete-circuit BJT amplifier configurations.
9
This section is identical to Section 4.7.2. Readers who studied Section 4.7.2 can skip this section.
461
462
CHAPTER 5
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS) 5.7
S A B ä - i ; 5,5
Characteristic Parameters of Amplifiers
Circuit
SINGLE-STAGE BJT AMPLIFIERS
Equivalent Circuits
M
A:
S
C:
Definitions
S
Input resistance with no load:
Output resistance:
Input resistance:
•
Open-circuit voltage gain:
Voltage gain: WIP = o 5
K
=
- °
Short-circuit current gain: A
S
Open-circuit overall voltage gain:
= '° I;
Current gain:
Overall voltage gain:
Relationships
G„ = —2h R
Short-circuit transconductance: r
l
- "\
a
R
a„ = a„„——
Output resistance of amplifier proper:
V0
R
L
a
g
v o
+R
=
-—'—A. R +
0
R
T
SIS
+
Rl
m
A
v0
= GR M
m
0
G= v
G
2. P a r a m e t e r s R , R , A , A , a n d G pertain to t h e amplifier t
0
vo
is
proper;
m
that is, they d o not
d e p e n d o n t h e v a l u e s of R
a n d R . B y contrast, R , R ,
d e p e n d o n o n e or b o t h of R
a n d R . A l s o , o b s e r v e t h e relationships of related pairs
sig
v, = 0
Ro
—^~
vo
sig
L
in
out
A, A, G , v
{
vo
and G may v
L
of these p a r a m e t e r s ; for instance, R = R- \ ^ , t
m R
=co
and R = R \ a
3 . A s m e n t i o n e d a b o v e , for nonunilateral amplifiers, R
onl R
=
q -
m a y depend on R , and
in
L
R
out
m a y d e p e n d o n 7 \ . O n e s u c h amplifier circuit is studied in Section 5.7.6. N o such sig
d e p e n d e n c i e s exist for unilateral amplifiers, for w h i c h R
ia
= R and R t
out
= Ra
/
1
463
5.7 CHAPTER 5
SINGLE-STAGE BJT AMPLIFIERS
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
4. T h e loading of the amplifier o n the signal source is d e t e r m i n e d b y t h e input resis tance R . T h e value of R d e t e r m i n e s the current that the amplifier d r a w s from the signal source. It also d e t e r m i n e s t h e proportion of the signal v that appears at the input of the amplifier proper, that is, v . in
which gives R,. = 900 k Q
in
sig
t
5. W h e n evaluating the gain A from the open-circuit v a l u e A , R is the o u t p u t resis tance to u s e . This is b e c a u s e A,, is b a s e d o n feeding the amplifier w i t h an ideal voltage signal Vj. This should b e evident from E q u i v a l e n t Circuit A in T a b l e 5.5. O n the other hand, if w e are evaluating the overall v o l t a g e gain G from its open-circuit value G the output resistance to u s e is i ? . T h i s is b e c a u s e G is b a s e d o n feeding the ampli fier with v , w h i c h h a s an internal resistance i ? . T h i s should b e e v i d e n t from Equivalent Circuit C in T a b l e 5.5. v
vo
the data obtained when R = 10 k Q is connected to the amplifier output to determine L
0
v
out
Next, we use
A and
v
sis
= — = 8.75 V / V
G
= — = 7 V/V 10
0
sig
The values of A and A v
vo
can be used to determine R as follows: 0
6. W e u r g e t h e r e a d e r to carefully e x a m i n e a n d reflect o n t h e d e f i n i t i o n s a n d t h e six r e l a t i o n s h i p s p r e s e n t e d in T a b l e 5 . 5 . E x a m p l e 5.17 s h o u l d h e l p in this r e g a r d .
R
L
°r Tr
A
Av
* ~
l
1
0
0
8.75 = 1010 +
7?
O
which gives A transistor amplifier is fed with a signal source having an open-circuit voltage w of 10 m V and an internal resistance 7? of 100 k Q . The voltage v at the amplifier input and the output voltage v are measured both without and with a load resistance R = 10 k Q connected to the amplifier output. The measured results are as follows: sig
R
= 1.43 k Q
0
t
sig
0
L
Similarly, we use the values of G and G v
to determine R
v0
M
G„ = i/,(mV)
j Without R | With fl connected
9 8
L
L
RL
G„
+
'RL
v (mV)
from
R
oM
0
90 70
| j
7 = 9 ,
1
0
\0 +
R
ont
resulting in 7?
Find all the amplifier parameters.
t
= 2.86 k Q
The value of R can b e determined from in
Solution First, we use the data obtained for R = °° to determine
v,sig
90 Ko
= j
R;,
3 .
L
=
io v / v
R
m
+
R
sig
Thus,
and G
«
90 = ^ = 9 V/V
10
fl +100
R
= 400 k Q
in
which yields N o w , since
in
The short-circuit transconductance G can be found as follows: m
466
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS) 5.7
SINGLE-STAGE BJT AMPLIFIERS
and the current gain A, can be determined as follows: :
5.7,3 The Common-Emitter (CE) Amplifier A. =
=
V
-^L v/R
v
in
t
T h e C E configuration is t h e m o s t w i d e l y u s e d of all B J T amplifier circuits. F i g u r e 5.60(a)
hh> R
shows a C E amplifier i m p l e m e n t e d using t h e circuit of F i g . 5 . 5 9 . T o establish a s i g n a l
L
g r o u n d (or a n a c g r o u n d , as it is sometimes called) at the emitter, a large capacitor C , usually E
in t h e jjF o r t e n s of piF r a n g e , is c o n n e c t e d b e t w e e n e m i t t e r a n d g r o u n d . T h i s c a p a c i t o r
= A „ f s = 8 . 7 5 x ^ 5 = 3 5 0 AVA K 10
is required t o p r o v i d e a very l o w i m p e d a n c e t o g r o u n d (ideally, zero i m p e d a n c e ; i.e., in
L
effect, a short circuit) at all signal frequencies of interest. In this w a y , t h e emitter signal curFinally, w e determine the short-circuit current gain A,, as follows. F r o m Equivalent Circuit A the short-circuit output current is
rent passes t h r o u g h C
E
t o g r o u n d a n d thus bypasses
the output resistance of t h e current
source / ( a n d a n y other circuit c o m p o n e n t that m i g h t b e c o n n e c t e d t o t h e e m i t t e r ) ; h e n c e C is called a b y p a s s c a p a c i t o r . Obviously, t h e l o w e r the signal frequency, t h e less effective E
However, to determine
we need to know the value of R
iB
(5.107)
the b y p a s s capacitor b e c o m e s . T h i s issue will b e studied in S e c t i o n 5.9. F o r o u r p u r p o s e s
obtained with R = 0. Toward this
here w e shall a s s u m e that C is acting as a perfect short circuit and t h u s is establishing a zero
L
G
'ose =
v v 0
s i
/R
E
signal v o l t a g e at t h e emitter.
end, note that from Equivalent Circuit C, the output short-circuit current can be found as (5.108)
o u t
Vcc (0 V) Now, equating the two expressions for i
and substituting for G
osc
vo
by
R
;
R, + R
Slg
and for v, from R;
r
\R,=0
HA,=0
sig
results in
= 81.8 k ß W e m o w can use
A
hsc -
R
/
v ii m\ R O
RL=0
o
to obtain
A
= ^
is
= 10 x 8 1 . 8 / 1 . 4 3 = 5 7 2 A / A
EXERCISE
5 42 for R
f
' ^ ^7^l°
unchanged; i.e., 100 k O ) . (c) Repeat for both R and R doubled. T ; • ^ ' »> ™ Ans. (a) 400 k Q , 5.83 V/V. 4.03 k O ; (b) 538 k Q , 7.87 V/V, 2.86 k O ; (c) 538 k G , 6.8 ^VA^, 4.03ou, k O (b) - Repeat L
doubled (but R
sig
sig
E
X
P
l
e
5
1 7
( a )
ff
R
i
S d
o
u
W
e
d
f
m
d
fte
L
v a l u e s
f o r
R
G
d
R
(b)
FIGURE 5 . 6 0 (a) A common-emitter amplifier using the structure of Fig. 5.59. (b) Equivalent circuit obtained by replacing the transistor with its hybrid-7R model.
.
¿ 6 7
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
5.7
(BJTs)
In o r d e r n o t to d i s t u r b t h e d c b i a s c u r r e n t s a n d v o l t a g e s , t h e s i g n a l to b e amplified s h o w n as a v o l t a g e s o u r c e v
w i t h an i n t e r n a l r e s i s t a n c e R ,
sig
v
again w e s h a l l a s s u m e this to b e t h e c a s e a n d defer d i s c u s s i o n of i m p e r f e c t signal cou at l o w frequencies, to Section 5.9
Replacing v by
connect the source directly to the b a s e , thus d i s p e n s i n g with C
C1
as w e l l as R . Eliminating B
II R )
c
L
v w e can write for t h e voltage gain of the amplifier proper; that is, the voltage
K
t
A
= -g (r \\R \\R )
v
m
0
c
(5.116)
L
T h e voltage signal resulting at t h e collector, v , is c o u p l e d to the load resistance R c
via
L
C2
b y the total resistance b e t w e e n collector and ground. T h e open-circuit v o l t a g e gain
m
B
W e shall a s s u m e that C
This equation simply says that t h e v o l t a g e g a i n from b a s e to collector is found b y m u l t i p l y ing g
R has the a d d e d beneficial effect of raising the i n p u t resistance of t h e amplifier.
C2
II R
0
w i t h o u t significantly c h a n g i n g the bias point w e may
B
another coupling capacitor C .
m
gain from b a s e to collector,
A t this j u n c t u r e , w e s h o u l d p o i n t o u t that in s i t u a t i o n s w h e r e t h e s i g n a l s o u r c e c a n provide a dc path for the dc b a s e current I
= -g v„(r
0
C 1
to act as a perfect short circuit at all s i g n a l f r e q u e n c i e s of i n t e r e s t w h i l e b l o c k i n g dc. Here
C1
AMPLIFIERS
At the output of t h e amplifier w e h a v e
t h r o u g h a l a r g e c a p a c i t o r C . C a p a c i t o r C , k n o w n as a c o u p l i n g c a p a c i t o r , is required
pling, arising as a result of the rise of the i m p e d a n c e of C
BJT
is c o n n e c t e d to the base
sig
C 1
SINGLE-STAGE
A
can b e obtained b y setting R = °° in E q . ( 5 . 1 1 6 ) ; thus, L
also acts a perfect short circuit at
all signal frequencies of interest; thus t h e output voltage v = v . N o t e that R 0
c
A
can be an
L
actual load resistor to w h i c h the amplifier is r e q u i r e d to p r o v i d e its output voltage signal, or it can be the input resistance of a s u b s e q u e n t amplifier stage in cases w h e r e m o r e than one
m
0
(5.H7)
c
from w h i c h w e n o t e that the effect of r is s i m p l y to r e d u c e the gain, usually only slightly 0
since typically r > R ,
stage of amplification is needed. ( W e will study m u l t i s t a g e amplifiers in C h a p t e r 7).
= -g (r \\R )
V0
0
resulting in
c
T o d e t e r m i n e the terminal characteristics of t h e C E amplifier, that is, its i n p u t resistance,
A
= -g R
vo
m
(5.118)
c
voltage gain, and output resistance, w e r e p l a c e the B J T with its hybrid-7r small-signal model. T h e resulting small-signal equivalent circuit of the C E amplifier is s h o w n in Fig. 5.60(b). W e
T h e output resistance R
observe at the outset that this amplifier is unilateral and thus R
ing b a c k into the output t e r m i n a l w h i l e short-circuiting the source v .
ia
= R and R (
oal
= R . Analysis 0
of this circuit is straightforward and p r o c e e d s in a step-by-step m a n n e r , from the signal
m
c a n b e f o u n d f r o m t h e equivalent circuit of F i g . 5.60(b) b y look iig
n
source to the amplifier load. A t the amplifier input w e h a v e
*in = r =
R^RcWro
II
(5.109)
0
0
ib
(5-119)
T h u s r r e d u c e s the output r e s i s t a n c e of t h e amplifier, again usually only slightly since typi cally r > R
where R
Since this will result
in v = 0, w e see that
and
c
is the input resistance l o o k i n g into the b a s e . S i n c e t h e emitter is g r o u n d e d , R*
= r
(5.110)
K
j
Recalling that for this unilateral amplifier R = R , 0
Normally, w e select R
B
> r„, with the result that
w e c a n utilize A
out
m
and R to obtain t h e 0
voltage gain A c o r r e s p o n d i n g to a n y p a r t i c u l a r R , v
*in = r
L
(5.111)
K
l
'°R
Thus, w e note that t h e i n p u t resistance of the C E amplifier will typically b e a few k i l o h m s , which can b e thought of as l o w to m o d e r a t e . T h e fraction of s o u r c e signal v
sig
that appears
across the input terminals of the amplifier p r o p e r c a n b e found from
+
L
Ro
T h e reader can easily verify that this a p p r o a c h d o e s in fact l e a d to the e x p r e s s i o n for A
v
T h e overall voltage gain from source to load, G„, c a n b e obtained b y multiplying v
'
=
v
* 1 T T R -
(
(R Wr ) B
x
°>(R + r ) + B
which for R
B
> r
n
5
-
1
1
2
)
G
v
= -
(
r
)
8
ir
11
^ " " »' ° II r ) + Ri
p
R
g
(R
B
For the case R
B
(5.114) K
sig
n
c
"
R
l
)
( 5
-
1 2 1 )
ig
iig
becomes
r +
(v/v )
f r o m E q . (5.113) b y A ^ f r o m E q . ( 5 . 1 1 6 ) ,
(5.113)
R
n
in
Eq. (5.116), w h i c h w e h a v e d e r i v e d directly.
R
§> r , this e x p r e s s i o n simplifies to n
v
_ ~
jS(* ll*iHO r + R c
1
sig
Next w e note that
From this e x p r e s s i o n w e n o t e that if 7?
(5 122)
71 ' "* Slg
sig
§> r , t h e overall g a i n will b e highly d e p e n d e n t o n n
B. T h i s is not a d e s i r a b l e p r o p e r t y since /? varies c o n s i d e r a b l y b e t w e e n units of the s a m e (5.115)
transistor type. A t the other e x t r e m e , if R
sig
CHAPTER 5
If* 3
5.7
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTs)
SINGLE-STAGE BJT AMPLIFIERS
Vcc(OV)
voltage gain r e d u c e s to G =-g (R \\R \\r ) v
m
c
L
(5.123)
0
w h i c h is the gain A ; in other w o r d s , w h e n R is small, the overall voltage gain is almost equal to the gain of the C E circuit proper, w h i c h is i n d e p e n d e n t of /3. Typically a C E ampli fier c a n realize a voltage gain o n t h e order of a few hundred, w h i c h is very significant. It fol l o w s that t h e C E amplifier is u s e d to realize t h e b u l k of the v o l t a g e gain required in a usual amplifier design. Unfortunately, h o w e v e r , as w e shall s e e in Section 5.9, t h e high-frequency r e s p o n s e of the C E amplifier can b e rather limited. Before leaving t h e C E amplifier, w e wish to evaluate its short-circuit current gain, A . T h i s can b e easily d o n e b y referring to the amplifier equivalent circuit in F i g . 5.60(b). W h e n R is short circuited, t h e current through it will b e e q u a l to - g < ^ , v
sig
is
L
m
/
os
—o~ 7; &m K
=
u
S i n c e v is related to i b y n
t
v„ = v =
iR
t
t
in
the short-circuit current gain can b e found as 1
A
is
= ^ = -g R h m
(5.124)
in
Substituting R = R II r w e can see that i n the c a s e R > r , \A \ r e d u c e s to /3, w h i c h is to b e e x p e c t e d since /3 is, b y definition, t h e short-circuit current gain of the c o m m o n - e m i t t e r configuration. In conclusion, t h e c o m m o n - e m i t t e r configuration can p r o v i d e large v o l t a g e a n d current gains, but R is relatively low a n d R is relatively high. m
m
B
n
B
n
is
out
5.43 Consider the C E amplifier of Fig. 5.60(a) when biased as in Exercise 5 . 4 1 . In particular, refer to h g . 1-5.4 I furthe b i a s • e t i i r v i i l * a n d i h e v a l u e s o ! t h e c l e m c u i - .iftheBJ I m o d e l a t t h e bias p o i i i l . k v a l u a l e R ( w i t h o u t and with7? taken into account), A„„ (without andiwithr,, taken into account), R (without and with r„ taken into account), and / ^ / ( w i t h o u t and with R taken into account). For R, = 5 k Q , find A,.. If A\ = 5 kQ.; find the o v e r a l l voltage gain G,.. If the sineswave v is t o b e limited to 5 m V peak, what is the maximum allowed peak amplitude of v and the corresponding peak amplitude of v„. w
w
0M
u
i?
K
M
Ans. 2.5 ki>. 15 111V: 0.6 V
kli;
32n \ \ .
2')h V A ; s kt>. ".-I ki>:
100 A/A.
'is \ \ : • 119 \ . \ :
(b)
''.' \ \ :
FIGURE 5 . 6 1 (a) A common-emitter amplifier with an emitter resistance R . (b) Equivalent circuit obtained by replacing the transistor with its T model. e
5,7.4 The Common-Emitter Amplifier with an Emitter Resistance Including a resistance i n the signal path b e t w e e n emitter and ground, as s h o w n in F i g . 5.61(a), can lead to significant c h a n g e s in the amplifier characteristics. T h u s such a resistor c a n b e utilized b y t h e designer as an effective design tool for tailoring the amplifier characteristics to fit the design r e q u i r e m e n t s .
A n a l y s i s of t h e circuit i n F i g . 5.61(a) c a n b e p e r f o r m e d b y r e p l a c i n g the B J T with o n e of its small-signal m o d e l s . A l t h o u g h any o n e of t h e m o d e l s of Figs. 5.51 a n d 5.52 c a n b e used, the m o s t c o n v e n i e n t for this application is o n e of the t w o T m o d e l s . This is b e c a u s e a resis tance R in t h e emitter will appear in series with t h e emitter resistance r of the T m o d e l and can thus b e a d d e d to it, simplifying the analysis considerably. In fact, w h e n e v e r there is a e
e
CHAPTER 5
5.7
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
resistance in the emitter lead, the T m o d e l should p r o v e m o r e c o n v e n i e n t to u s e than the hybrid- n m o d e l . R e p l a c i n g t h e B J T w i t h the T m o d e l of F i g . 5.52(b) results in the amplifier small-signal equivalent-circuit m o d e l s h o w n in Fig. 5.61(b). N o t e that w e h a v e not i n c l u d e d t h e B J T output resistance r ; including r c o m p l i c a t e s t h e analysis considerably. S i n c e for the discrete amplifier at h a n d it turns out that the effect of r o n circuit p e r f o r m a n c e is small, w e shall not include it in the analysis here. This is not the case, h o w e v e r , for the I C v e r s i o n of this circuit, and w e shall indeed take r into account in t h e analysis in C h a p t e r 6. 0
0
S I N G L E - S T A G E BJT AMPLIFIERS
Substituting for i from E q . (5.126) gives e
Vo
A
_a(Rc\\RÙ r„ + R,
=
V:
Since a=
( 5
.
1 2 9 )
1,
0
A,s-M|£
(5.130)
r, + R,
0
T o d e t e r m i n e the amplifier input resistance R , w e n o t e from F i g . 5.61(b) that R parallel equivalent of R and the input resistance at t h e b a s e R , in
is the
in
B
T h i s s i m p l e r e l a t i o n s h i p is v e r y useful a n d is d e f i n i t e l y w o r t h r e m e m b e r i n g : The gain from
ib
the total R
= RB\\R
in
(5.125)
ib
base to collector resistance
is equal
in the emitter.
to the ratio of the total resistance
amplifier circuit. T h e o p e n - c i r c u i t v o l t a g e g a i n A
can be found b y setting R
L
= °° in
Eq. (5.129),
can b e found from
ib
to
T h i s s t a t e m e n t is a g e n e r a l o n e a n d a p p l i e s to a n y vo
T h e input resistance at the b a s e R
voltage
in the collector
A
= -
vo
V i
R ib = T h
-
^
(5.13D
K
which can b e e x p r e s s e d alternatively as
where a
A,.„ — i
=
t
(l-a)«.
=
^
a
and
_ _ w
= - f r + R
e
e
(5.126) e
c
g Rc l + (R /r )-
RJr, _, _
m
e
i
R
r„ 1 +
g Rc l+g R
! 22)
m
e
m
e
Including R t h u s r e d u c e s t h e v o l t a g e gain b y the factor (1 + g R ), w h i c h is the s a m e factor by w h i c h R is increased. This points out an interesting trade-off b e t w e e n gain and input resistance, a trade-off that the designer can exercise through t h e choice of an appropriate value for R . T h e output resistance R can b e found from the circuit in Fig. 5.61(b) b y inspection: c
m
e
ib
Thus,
e
R
= (B+l)(r
ib
+ R)
e
(5.127)
e
This is a very important result. It says that the input resistance looking into the base is (¡3+ 1) times the total resistance in the emitter. Multiplication b y t h e factor (B + 1) is k n o w n as the r e s i s t a n c e - r e f l e c t i o n r u l e . T h e factor (B+l) arises b e c a u s e the b a s e current is l/(B+l) times the emitter current. T h e expression for R in Eq. (5.127) s h o w s clearly that including a resistance R in the emitter can substantially i n c r e a s e R . I n d e e d t h e v a l u e of R is increased b y the ratio
oaX
R
= R
out
(5.133)
c
At this point w e should n o t e that for this amplifier, R = R and R - R. T h e short-circuit current gain A can b e found from the circuit in Fig. 5.61(b) as follows: in
t
oat
0
is
ib
e
ib
'as =
ib
U = R
ib
(with R included) e
R
ib
=
(L3+l)(r
e
(without R )
+ R)
Thus,
e
(P+l)r
e
V/Rin
_
e
aRJ
e
A D
= l + - s l + & R r
(5.128)
e
Substituting for i from Eq. (5.126) and f o r 7 ? from Eq. (5.125), e
T h u s the circuit designer can u s e the value of R to control the value of R and h e n c e R . Of course, for this control to b e effective, R m u s t b e m u c h larger t h a n R ; in other w o r d s , R m u s t d o m i n a t e t h e input resistance. T o d e t e r m i n e the v o l t a g e gain A , w e see from F i g . 5.61(b) that e
ib
B
is
ib
in
a(R
B
m
II R ) ib
(5.134)
r, + R
ib
c
w h i c h for t h e c a s e R
B
> R
ib
r e d u c e s to
v
_ -a(ß+l)(r
e
v
0
= -i (R c
II R )
c
= ~ai (R
L
e
c
r„ + R„
II R ) L
the s a m e value as for t h e C E circuit.
+ R) e
_
5.7 ER 5
475
S I N G L E - S T A G E BJT AMPLIFIERS
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
T h e overall v o l t a g e gain from s o u r c e to load c a n b e o b t a i n e d b y m u l t i p l y i n g A
by
V
O/^sig).
q
R
.a
3_
=
v
v
m
Ri
sig
a
(
R
+R
S g
c
5.44 Consider the emitter-degenerated C E circuit of Fig. 5.6! when biased as in Exercise 5.41. In particular refer to Fig. E5.41 for the bias currents and for the values of the elements of the B I T model at the bias point. Let the amplifier be fed from a source having R „ = 5 k Q , and let R = 5 kil. Find the value of R that results in R- equal to four limes the source resistance R „. For this value of R , find A,.,„ R , A,„ G.j, and A . If v is to b e limiled.to 5 m V , what is the maximum value r.t, can have with and without R , • included. Find the corresponding v , Ans. 225 12: 32 V-V: s !,(»: 12.3 V / V ; - 9 . S V / \ : -•«).: .V \ : f>2.5 mV; 15 n i \ : (>.
11
r + R
m
e
e
t[
Substituting for R
in
by R
B
II R ,
a s s u m i n g that R
ib
B
> R,
a n d substituting for R
ib
from
ib
L
m
E q . (5.127) results in
is
c
v
~
R
sig
L
(P+l)(r
+
t
c
n
ic
e
( = >
R)
+
e
U
- »
W e n o t e that t h e gain is l o w e r t h a n that of t h e C E a m p l i f i e r b e c a u s e of the a d d i t i o n a l t e r m (/3+ l)R
e
in the d e n o m i n a t o r . T h e gain, h o w e v e r , is less sensitive to the v a l u e of /3, a desir
5.7.5 The Common-Base (CB) Amplifier
able result. A n o t h e r i m p o r t a n t c o n s e q u e n c e of i n c l u d i n g the resistance R
e
in t h e emitter is that it
e n a b l e s t h e amplifier to h a n d l e larger i n p u t signals w i t h o u t incurring n o n l i n e a r distortion. T h i s is b e c a u s e only a fraction of t h e i n p u t signal at the b a s e , v , a p p e a r s b e t w e e n the base t
a n d t h e emitter. Specifically, from the circuit in F i g . 5.61(b), w e see that
B y establishing a signal g r o u n d o n the b a s e terminal of t h e B J T , a circuit configuration aptly n a m e d c o m m o n - b a s e or g r o u n d e d - b a s e a m p l i f i e r is obtained. T h e i n p u t signal is a p p l i e d to t h e emitter, a n d t h e o u t p u t is t a k e n at the collector, w i t h t h e b a s e f o r m i n g a c o m m o n ter m i n a l b e t w e e n t h e i n p u t a n d o u t p u t ports. F i g u r e 5.62(a) s h o w s a C B amplifier b a s e d o n the circuit of Fig. 5.59. O b s e r v e that since both t h e dc a n d ac v o l t a g e s at t h e b a s e are zero, w e
- = — ^ 7 r = T—^ v r +R 1+ R t
e
e
g m
(5-136)
B
e
capacitors C
T h u s , for the s a m e v„, t h e signal at t h e i n p u t t e r m i n a l of the amplifier, v
it
•for t h e C E amplifier b y the factor (1 +
c a n b e greater than
g R ). m
h a v e c o n n e c t e d t h e b a s e directly to g r o u n d , thus e l i m i n a t i n g resistor R C 1
and C
c 2
altogether. C o u p l i n g
p e r f o r m similar functions to t h o s e in the C E circuit.
T h e small-signal e q u i v a l e n t circuit m o d e l of t h e amplifier is s h o w n in Fig. 5.62(b). Since resistor R „ a p p e a r s in series with t h e emitter terminal, w e h a v e elected to u s e t h e
e
si
T o s u m m a r i z e , including a resistance R in the emitter of the C E amplifier results in the e
following characteristics:
T m o d e l for the transistor. A l t h o u g h the hybrid-7T m o d e l w o u l d yield identical results, the T m o d e l is m o r e c o n v e n i e n t in this case. W e h a v e not i n c l u d e d r . This is b e c a u s e including 0
1. T h e input resistance R
ib
is i n c r e a s e d b y the factor (1 +
r w o u l d c o m p l i c a t e t h e analysis c o n s i d e r a b l y , for it w o u l d a p p e a r b e t w e e n the output a n d
g R ). m
a
e
2. T h e v o l t a g e gain from b a s e to collector, A , is r e d u c e d b y the factor (1 + v
g R ). m
input of the amplifier. F o r t u n a t e l y , it turns out that the effect of r o n the p e r f o r m a n c e of a 0
e
discrete C B amplifier is very small. W e will consider t h e effect of r w h e n w e study the I C 0
3. F o r t h e s a m e n o n l i n e a r distortion, t h e i n p u t signal v c a n b e i n c r e a s e d b y the factor t
(1+gJU.
f o r m of t h e C B amplifier in C h a p t e r 6. F r o m i n s p e c t i o n of the equivalent circuit m o d e l in F i g . 5.62(b), w e see that the i n p u t
4. T h e overall v o l t a g e gain is less d e p e n d a n t on t h e v a l u e of /3.
resistance is
5. T h e h i g h - f r e q u e n c y r e s p o n s e is significantly i m p r o v e d (as w e shall see in C h a p t e r 6). R
= r
m
(5.137)
e
W i t h the e x c e p t i o n of gain reduction, t h e s e characteristics r e p r e s e n t p e r f o r m a n c e i m p r o v e m e n t s . I n d e e d , the r e d u c t i o n in gain is the p r i c e p a i d for o b t a i n i n g the other p e r f o r m a n c e
This should h a v e b e e n e x p e c t e d since w e are l o o k i n g into t h e emitter and the b a s e is
i m p r o v e m e n t s . In m a n y cases this is a g o o d b a r g a i n ; it is the u n d e r l y i n g m o t i v e for t h e use
g r o u n d e d . T y p i c a l l y r is a few o h m s to a few tens of o h m s ; thus the C B amplifier h a s a low
of n e g a t i v e feedback. T h a t the resistance R i n t r o d u c e s n e g a t i v e f e e d b a c k in the amplifier
input resistance.
e
circuit c a n b e seen b y reference to F i g . 5.61(a): If for s o m e r e a s o n the collector current
e
T o d e t e r m i n e the v o l t a g e gain, w e write at the collector n o d e
i n c r e a s e s , the emitter current also will increase, resulting in an i n c r e a s e d v o l t a g e d r o p across R. e
v = -ai (Rc 0
T h u s t h e emitter v o l t a g e rises, a n d t h e b a s e - e m i t t e r v o l t a g e d e c r e a s e s . T h e latter effect
causes the collector current to decrease, c o u n t e r a c t i n g t h e initially a s s u m e d c h a n g e , an indi
II RL)
e
and substitute for t h e emitter current from
cation of t h e p r e s e n c e of n e g a t i v e feedback. In C h a p t e r 8, w h e r e w e shall study n e g a t i v e f e e d b a c k formally, w e will find that t h e factor (1 + g„fi ) e
w h i c h appears r e p e a t e d l y , is the
" a m o u n t of n e g a t i v e f e e d b a c k " i n t r o d u c e d b y R . Finally, w e n o t e that the n e g a t i v e f e e d b a c k e
action of R gives it t h e n a m e e m i t t e r d e g e n e r a t i o n r e s i s t a n c e .
to obtain
e
Before leaving this circuit w e w i s h to p o i n t out that w e h a v e s h o w n a n u m b e r of t h e cir cuit analysis steps directly on the circuit d i a g r a m in F i g . 5.61(a). W i t h practice, the r e a d e r should b e able to d o all of the small-signal analysis directly on the circuit d i a g r a m , thus dis
A
v
= -° = 2(R
C
II R ) L
= g (R m
c
IIR )
(5.138)
L
w h i c h e x c e p t for its p o s i t i v e sign is identical to t h e e x p r e s s i o n for A for the C E amplifier. v
p e n s i n g with the task of d r a w i n g a c o m p l e t e s m a l l - s i g n a l equivalent-circuit m o d e l .
M
(
0
j3(R \\R ) U
si
CHAPTER 5
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
5.7
SINGLE-STAGE BJT AMPLIFIERS
Fig. 5.62(b) as R
r
^out =
which is similar t o t h e c a s e of the C E amplifier. H e r e w e should n o t e that t h e C B amplifier with r neglected is unilateral, w i t h the result that
7?
6
IN
=
R and R t
oat
= R. 0
T h e short-circuit current gain A is g i v e n b y is
A , - — h
e
e
= — -h
= a
(5.140)
which corresponds to o u r definition of a as the short-circuit current gain of the C B configuration. Although the gain of the C B amplifier proper h a s the same magnitude as that of the C E amplifier, this is usually not the case as far as t h e overall voltage gain is c o n c e r n e d . T h e l o w input r e s i s t a n c e of t h e C B amplifier c a n c a u s e t h e i n p u t s i g n a l to b e s e v e r e l y a t t e n u a t e d , specifically R
^sig
l
^sig
r
Ri
'
Rsig
(5.141) 1~e
from w h i c h w e s e e that e x c e p t for situations in w h i c h R
is o n t h e order of r , t h e signal
sig
transmission factor v /v t
e
c a n b e very small. It is useful at this p o i n t t o m e n t i o n that o n e of
Az
the applications of the C B circuit is to amplify high-frequency signals that appear o n a coaxial cable. T o p r e v e n t signal reflection o n t h e cable, t h e C B amplifier is r e q u i r e d t o h a v e a n i n p u t
(a)
resistance equal t o t h e characteristic resistance of the cable, w h i c h is u s u a l l y in t h e r a n g e of
C -o-
50 O t o 7 5 Q .
-ov
n
T h e overall voltage gain G of the C B amplifier c a n b e obtained b y m u l t i p l y i n g t h e ratio v
v/v
sig
of E q . (5.141) b y A,, from Eq. (5.138), G
v
l£
=
r —g (R \lR )
1
SIG
Tit
1
m
c
L
'e
=
(5.142) R
R• VW
+r SIG
h
e
Since a s 1, w e see that t h e overall v o l t a g e gain is simply t h e ratio of t h e total resistance in
o-
the collector circuit to t h e total resistance i n t h e emitter circuit. W e also n o t e that t h e overall
+
voltage gain is a l m o s t i n d e p e n d e n t of t h e v a l u e of B (except t h r o u g h t h e small d e p e n d e n c e of a o n B), a desirable property. O b s e r v e that for R
sig
of t h e s a m e o r d e r as R
and R , the
c
L
gain will b e very small. In s u m m a r y , t h e C B amplifier e x h i b i t s a very l o w i n p u t r e s i s t a n c e (r ), a short-circuit e
current g a i n that is n e a r l y unity ( a ) , a n o p e n - c i r c u i t v o l t a g e gain that is p o s i t i v e a n d e q u a l in m a g n i t u d e t o that of t h e C E amplifier (g Rr), m
(b)
a n d like t h e C E amplifier, a r e l a t i v e l y
h i g h o u t p u t r e s i s t a n c e ( i ? ) . B e c a u s e of its v e r y l o w i n p u t r e s i s t a n c e , t h e C B circuit c
alone
is n o t a t t r a c t i v e as a v o l t a g e amplifier e x c e p t in s p e c i a l i z e d a p p l i c a t i o n s , s u c h as t h e c a b l e FIGURE 5 . 6 2 (a) A common-base amplifier using the structure o f Fig. 5.59. (b) Equivalent circuit obtained by replacing the transistor with its T model.
amplifier m e n t i o n e d a b o v e . T h e C B amplifier h a s e x c e l l e n t h i g h - f r e q u e n c y p e r f o r m a n c e as w e l l , w h i c h as w e shall s e e in C h a p t e r 6 m a k e s it useful t o g e t h e r w i t h o t h e r circuits in the i m p l e m e n t a t i o n of h i g h - f r e q u e n c y a m p l i f i e r s . F i n a l l y , a v e r y significant a p p l i c a t i o n of
T h e open-circuit v o l t a g e gain A
vo
c a n b e found f r o m E q . (5.138) b y setting R =
t h e C B circuit is a s a u n i t y - g a i n c u r r e n t amplifier o r c u r r e n t b u f f e r : It a c c e p t s a n i n p u t
L
signal current at a l o w input resistance a n d delivers a nearly equal current at very high output A
vo
= gR m
c
(5.139)
resistance at t h e collector (the output resistance e x c l u d i n g R
c
A g a i n this is identical to A
vo
for t h e C E amplifier e x c e p t that t h e C B amplifier is n o n i n v e r t -
m g . T h e output resistance of t h e C B circuit c a n b e found b y inspection from t h e circuit in
a n d n e g l e c t i n g r is infinite). 0
W e shall study such an application i n t h e context of t h e I C v e r s i o n of t h e C B circuit in C h a p t e r 6.
+ Vcc 4 7 8
¿1^
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
EXERCISES 5.45 Consider the CB amplifier of Fig. 5.62(a) when designed using the BJT and component values specified in Exercise 5.41. Specifically, refer lo Fig. E5.41 for Ihe bias quantities and the values of the c o m ponents of the BJT small-signal model. Let A'„„ = R, = 5 k Q . Find the values of R , A , R , A , v/v , and G . To what value should R^„ be reduced to obtain an overall voltage gain equal to that found for the C E amplifier in Exercise 5.43, that is, - 3 9 V/V? m
m
0
v
s
v
Am. 25 O ; +320 V/V; 8 k O ; + 1 2 3 V/V; 0.005 V/V; 0.6 V/V; 54 Q
A
- V „
D5.46 It is required t o design a CB amplifier for a signal delivered by a 50-Q coaxial cable. T h e amplifier is to provide a "proper termination" for the cable and to provide an overall voltage gain of +100 V/V. Specify the value of the bias current I and the total resistance in the collector circuit.
OUT
(a) C
E
Arts. 0.5 mA: 10 k Q
5.7.6 The Common-Collector ( C O Amplifier or Emitter Follower T h e last of the basic B J T amplifier configurations is the c o m m o n - c o l l e c t o r ( C C ) circuit, a v e r y i m p o r t a n t circuit that finds frequent application in the design of b o t h small-signal and large-signal amplifiers (Chapter 14) a n d e v e n in digital circuits (Chapter 11). T h e circuit is m o r e c o m m o n l y k n o w n b y the alternate n a m e emitter follower, t h e r e a s o n for w h i c h will shortly b e c o m e apparent. A n emitter-follower circuit b a s e d on the structure of F i g . 5.59 is s h o w n in F i g . 5.63(a). O b s e r v e that since t h e collector is to b e at signal g r o u n d , w e h a v e eliminated the collector resistance R . T h e input signal is capacitively c o u p l e d to the base, and the output signal is capacitively c o u p l e d from t h e emitter to a load resistance R . Since, as far as signals are concerned, resistance R is c o n n e c t e d in series w i t h t h e emitter, t h e T m o d e l of t h e B J T w o u l d b e the m o r e c o n v e n i e n t o n e to u s e . F i g u r e 5.63(b) s h o w s t h e small-signal equivalent circuit of the emitter follower with the B J T r e p l a c e d b y its T m o d e l a u g m e n t e d to i n c l u d e r . H e r e it is relatively simple to take r into account, a n d w e shall d o so. Inspection of t h e circuit in F i g . 5.63(b) reveals that r appears in effect in parallel with R . T h e r e f o r e the circuit is r e d r a w n to e m p h a s i z e this point, and i n d e e d to simplify t h e analysis, in F i g . 5.63(c). c
L
L
B
0
0
L
U n l i k e t h e C E and C B circuits w e studied a b o v e , the emitter-follower circuit is not unilateral; that is, the input resistance d e p e n d s o n R , and the output resistance d e p e n d s o n R . C a r e therefore m u s t b e exercised in characterizing the emitter follower. In the following w e shall derive expressions for R^, G , G , a n d R . T h e expressions that w e derive will shed light o n the operation and characteristics of the emitter follower. M o r e important t h a n t h e actual expressions, h o w e v e r , are the m e t h o d s w e u s e to obtain t h e m . It is in these that w e h o p e the r e a d e r will b e c o m e proficient. L
v
vo
sig
out
R e f e r e n c e to Fig. 5.63(c) reveals that t h e B J T h a s a resistance (r IIR ) in series with the emitter resistance r . T h u s application of t h e resistance reflection rule results in the equivalent circuit s h o w n in Fig. 5.64(a). Recall that in reflecting resistances to the b a s e side, w e m u l t i p l y all resistances in the emitter b y (/3 + 1), t h e ratio of i to i . In this w a y the voltages r e m a i n u n c h a n g e d . Inspection of the circuit in Fig. 5.64(a) s h o w s that the input resistance at t h e b a s e , R , is 0
L
e
e
b
ib
R
ib
= (ß+l)[r
e
+
(r \\R )] 0
L
(5.143)
(C)
F I G U R E 5 . 6 3 (a) A n emitter-follower circuit based on the structure of Fig. 5.59. (b) Small-signal equivalent circuit of the emitter follower with the transistor replaced by its T model augmented with r„. (c) The circuit i n (b) redrawn to emphasize that r is i n parallel with R . This simplifies the analysis considerably. 0
L
4 7 9
4 8 0
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS (BJTs)
5.7
SINGLE-STAGE BJT AMPLIFIERS
481
(R jjR ) S
I—VA
o-^
Ä /(J3 + 1 ) W v
B
K
03+1)
sig
I—WV
:(ß + i K -o
E
+
(ß + I K
-o-
ß + 1
E -o-
-o
+
+
(J3 + i)Ri
tf
in
= Rj(ß
+ l)[r, +
r
(ß +
RR
( jR )] L
J
»
»dg
i?
+ Ä
sig
B
(R J/R ) S
lKrjRj)
+ (ß + l)[r
B
v„
e
+
(rjR )] L
v
(b)
(a)
si
B
L
II r
0
sig
+R
B
(a)
irjRÙ (R //R ) + r + ß + l sig
B
(b)
FIGURE 5 . 6 5 (a) An alternate equivalent circuit of the emitter follower obtained by reflecting all base-circuit resistances to the emitter side, (b) The circuit in (a) after application of Thevenin theorem to the input circuit composed of t; „, R /(B+ 1), and R /(B + 1 ) . B
sia
si
from w h i c h w e see that the emitter follower acts to raise the resistance level of R R
R
e
FIGURE 5 . 6 4 (a) An equivalent circuit of the emitter follower obtained from the circuit in Fig. 5.63(c) by reflecting all resistances in the emitter to the base side, (b) The circuit in (a) after application of Thevenin theorem to the input circuit composed of v „ S „, and R . A
^
(or
L
to b e exact) b y the factor (8 + 1) a n d p r e s e n t s to the s o u r c e t h e increased resistance. of the latter reveals that the oittput voltage and h e n c e vj
T h e total i n p u t resistance of the follower is
v
can b e found by a simple applica-
sig
tion of t h e v o l t a g e - d i v i d e r rule, with the result that R
in
= R
B
II R
jb
G from w h i c h w e see that to realize the full effect of the increased R , large a value for the bias resistance R
= - ^
v
w e h a v e to choose as
ib
„
R ^ R
(5.145)
R ^ R B
B
+
R E
+
{
R
J
R
L
)
as is practical (i.e., from a bias design point of v i e w ) .
B
A l s o , w h e n e v e r possible, w e should dispense with R
B
altogether and connect the signal source
directly to t h e b a s e (in w h i c h case w e also d i s p e n s e w i t h C ) . C 1
which, as e x p e c t e d , is identical to t h e e x p r e s s i o n in E q . (5.144) e x c e p t that both the n u m e r a tor a n d d e n o m i n a t o r of t h e second factor on the r i g h t - h a n d side h a v e b e e n d i v i d e d b y
T o find the overall v o l t a g e gain G , w e first apply T h e v e n i n t h e o r e m at the input side of v
t h e circuit in F i g . 5.64(a) to simplify it to t h e f o r m s h o w n in F i g . 5.64(b). F r o m t h e latter cir-
(B + 1). T o gain further insight r e g a r d i n g t h e o p e r a t i o n of the emitter follower, l e t ' s simplify this e x p r e s s i o n for the u s u a l case of R
B
> R
and r >
sig
R.
0
L
T h e result is
cuit w e see that v c a n b e found b y utilizing t h e v o l t a g e divider r u l e ; t h u s , 0
R
q
= v
_RB R
sig
(B+l)(rjR ) L
+ R (R \\R ) B
sig
B
+ (B+l)[
re
+
R
- ^ 8+1
(r \\R )] 0
L
±
(5.146)
+ r, + R
w h i c h clearly indicates that t h e gain a p p r o a c h e s u n i t y w h e n R /(B+ sig
W e o b s e r v e that the v o l t a g e gain is less than u n i t y ; h o w e v e r , for R
B
> R
sig
a n d (B + 1 )[r + e
smaller t h a n R
L
(r
0
II RL)] ^ ( ^ s i II RB)> it b e c o m e s very close to unity. T h u s t h e voltage at the emitter g
(v ) 0
f o l l o w s v e r y c l o s e l y t h e v o l t a g e at t h e i n p u t , w h i c h g i v e s t h e c i r c u i t t h e n a m e e m i t t e r follower. R a t h e r than reflecting the emitter r e s i s t a n c e n e t w o r k into the b a s e side, w e c a n d o the
or alternatively w h e n (B + l)R
sig
This is t h e
buffering a c t i o n of the emitter follower, w h i c h derives from the fact that the circuit h a s a short-circuit current gain that is a p p r o x i m a t e l y e q u a l to (/3 + 1). It is also useful to r e p r e s e n t the output of the emitter follower b y its T h e v e n i n e q u i v a l e n t circuit. T h e o p e n - c i r c u i t o u t p u t v o l t a g e will b e G „ t ; 0
c o n v e r s e : Reflect the b a s e resistance n e t w o r k i n t o the emitter side. T o k e e p t h e v o l t a g e s
1) b e c o m e s m u c h
b e c o m e s m u c h larger t h a n R .
L
where G
sig
v0
can be obtained
from
Eq. (5.145) b y setting R = °°, L
u n c h a n g e d , w e d i v i d e all the b a s e - s i d e r e s i s t a n c e s b y (B + 1). This is the dual of the resist a n c e reflection rule. D o i n g this for the circuit in Fig. 5.63(c) results in t h e alternate emitter-
G
v0
follower e q u i v a l e n t circuit, s h o w n in F i g . 5.65(a). H e r e also w e c a n simplify the circuit b y applying T h e v e n i n t h e o r e m at the input side, resulting in the circuit in Fig. 5.65(b). Inspection
= — ^
¡¡—^2 R
^sig + B
Rsig
IIR
B+l
(5.147)
B
+
r
^ ' °
(rJR ) L
4 8 2
)
CHAPTER 5 BIPOLAR JUNCTION TRANSISTORS (BJTs)
5.7
N o t e that r usually is large and the s e c o n d factor b e c o m e s a l m o s t unity. T h e first factor a p p r o a c h e s unity for R i> / ? . T h e T h e v e n i n resistance is the output resistance R . It can be d e t e r m i n e d b y inspection of the circuit in Fig. 5.65(b): R e d u c e v to zero, " g r a b h o l d " of the emitter terminal, and look back into the circuit. T h e result is a
B
s i g
om
sig
SINGLE-STAGE BJT AMPLIFIERS
.
the o u t p u t v w i l l also g o n e g a t i v e , a n d t h e c u r r e n t in R w i l l b e f l o w i n g f r o m g r o u n d i n t o the e m i t t e r t e r m i n a l . T h e t r a n s i s t o r will c u t off w h e n this c u r r e n t b e c o m e s e q u a l to t h e bias c u r r e n t I. T h u s t h e p e a k v a l u e of v c a n b e f o u n d f r o m 0
L
0
RL /C, = O l ( r
+ ^fn;
e
(5.148)
or Vo
Usually r is m u c h larger than the parallel c o m p o n e n t b e t w e e n the p a r e n t h e s e s and can be neglected, leaving
=
IR
L
a
R
wt
R
= r
e
+
^
si
(5.149)
T h u s t h e output resistance of the emitter follower is l o w , a g a i n a result of its i m p e d a n c e t r a n s f o r m a t i o n or buffering action, w h i c h leads to t h e division of (R II R ) b y (/3 + 1 ) . T h e T h e v e n i n e q u i v a l e n t circuit of the e m i t t e r follower is s h o w n t o g e t h e r w i t h t h e formulas for G and R in Fig. 5.66. This circuit c a n b e u s e d to find v and h e n c e G for any value of R . In s u m m a r y , t h e emitter follower exhibits a high input resistance, a l o w output resistance, a v o l t a g e gain that is smaller t h a n b u t close to unity, a n d a relatively large current gain. It is therefore ideally suited for applications in w h i c h a high-resistance source is to b e c o n n e c t e d to a low-resistance l o a d — n a m e l y , as the last stage or output stage in a multistage amplifier, w h e r e its purpose would be not to supply additional voltage gain b u t rather to give t h e c a s c a d e amplifier a low output resistance. W e shall study t h e d e s i g n of amplifier output stages in C h a p t e r 14. B e f o r e l e a v i n g t h e emitter follower, t h e q u e s t i o n of th£ m a x i m u m a l l o w e d signal s w i n g d e s e r v e s c o m m e n t . Since only a small fraction of t h e i n p u t signal a p p e a r s b e t w e e n t h e b a s e a n d t h e emitter, the emitter f o l l o w e r exhibits linear o p e r a t i o n for a w i d e r a n g e of i n p u t - s i g n a l a m p l i t u d e . There is, h o w e v e r , an a b s o l u t e u p p e r limit i m p o s e d o n t h e v a l u e of t h e o u t p u t - s i g n a l a m p l i t u d e by transistor cutoff. T o see h o w this c o m e s about, c o n s i d e r t h e circuit of F i g . 5.63(a) when the i n p u t signal is a sine w a v e . A s t h e i n p u t g o e s n e g a t i v e , sig
v0
T h e c o r r e s p o n d i n g value of v „ will b e
out
B
0
Vsig
=
IRr
Increasing t h e a m p l i t u d e of v a b o v e this value results in t h e transistor b e c o m i n g cut off and t h e n e g a t i v e p e a k s of t h e output-signal w a v e f o r m b e i n g clipped off. sig
v
L
L
H
ih
v
vo
L
Ans. W . 7 k Q : 28.3 k Q ; 0.735 V / V ; 0.8 V / V ; 8 4 Q ; 5 v
:
1.0 V n."6S :
V / V ; 0.685 V / V
5.7.7 Summary and Comparisons F o r e a s y r e f e r e n c e a n d to e n a b l e c o m p a r i s o n s , w e p r e s e n t in T a b l e 5.6 t h e f o r m u l a s for d e t e r m i n i n g t h e c h a r a c t e r i s t i c p a r a m e t e r s of d i s c r e t e s i n g l e - s t a g e B J T amplifiers. In a d d i tion to t h e r e m a r k s a l r e a d y m a d e t h r o u g h o u t this s e c t i o n a b o u t t h e characteristics a n d areas of a p p l i c a b i l i t y of t h e v a r i o u s c o n f i g u r a t i o n s , w e m a k e t h e f o l l o w i n g c o n c l u d i n g points:
E
^out
5.47 The emitter follower in Fig. 5.63(a) is used to connect a source with R^ = 10 k Q to a load R - I kQ. T h e transistowisbiased at /.= 5 m A , utilizes a resistance R = 4 0 k£i, a n d h a s B= lOOancfV^ = 100 V. bind R , RiSG > G , andR^. What is the largest peak amplitude of an output sinusoid that can be used without the transistor cutting off? If in order to limit nonlinear distortion ihe base-emitter signal voltage is limited to 10 m V peak, what is the corresponding amplitude at the output? What will the overall voltage gain become if R is changed to 2 k Q ? T o 500 Q ?
1. T h e C E configuration is t h e best suited for realizing t h e b u l k of t h e gain required in an amplifier. D e p e n d i n g on the m a g n i t u d e of t h e gain required, either a single stage or a c a s c a d e of t w o or three stages can be used. 2. Including a resistor R in the emitter lead of t h e C E stage p r o v i d e s a n u m b e r of perf o r m a n c e i m p r o v e m e n t s at the e x p e n s e of gain reduction. e
R^ + Ra
(R //R ) sig
B
03 + 1)
J
R
Rs\J B
ß + l
+ r, + r
n
FIGURE 5 . 6 6 Thevenin equivalent circuit of the output of the emitter follower of Fig. 5.63(a). This circuit can be used to find v and hence the overall voltage gain v / v for any desired R . 0
B
A%
L
3. T h e l o w i n p u t resistance of the C B amplifier m a k e s it useful only in specific applications. A s w e shall see in C h a p t e r 6, it has a m u c h better high-frequency r e s p o n s e than t h e C E amplifier. T h i s superiority will m a k e it useful as a high-frequency amplifier, especially w h e n c o m b i n e d with t h e C E circuit. W e shall see o n e such c o m b i n a t i o n in C h a p t e r 6.
^.33
484
CHAPTER 5
5.8
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
4. T h e emitter follower finds application as a v o l t a g e buffer for c o n n e c t i n g a high-
T H E B J T I N T E R N A L C A P A C I T A N C E S A N D H I G H - F R E Q U E N C Y M O D E L FR* Zi
Common Base
resistance source to a low-resistance load and as the o u t p u t stage in a m u l t i s t a g e amplifier. Finally, w e should point out that the Exercises in this section (except for that relating to the emitter follower) u s e d the s a m e c o m p o n e n t values to allow n u m e r i c a l c o m p a r i s o n s . Neglecting r : a
= r
R
,n
e
=
A
v
R
out
g (R \\R ) m
R
=
c
C
a(R
=
L
Ii R )
c
"
L
Ràg + r.
A,, S a
Common Collector or Emitter Follower
R
m
= R \\ {ß+l)[r B
A, =
+ (rj
e
(r \\R ) 0
a
e
sig
H r
r
= o
L
+ r
L
R
Ru
R )]
e
II
R
B~\
ß+l
Common Emitter with Emitter Resistance
(rjR ) ^ ^ L
R +R R U B
sig
É£
B
+
+
ß+l A
ü
=
ß+l
Neglecting r : 0
R
m
= R II (ß+l)(r B
+ R)
e
e
a(R \\R )_-g (R \\ r +R 1+ c
e
R
out
=
G„ = -
m
R) gR
c
L
m
R
ß(RcURi) + (ß+l)(r
R
sis
Vx„
L
e
e
1
Vi~l+g,„Re
+ R) e
e
1 5.8 THE BJT INTERNAL CAPACITANCES • * AND HIGH-FREQUENCY MODEL T h u s far w e h a v e a s s u m e d transistor action to b e i n s t a n t a n e o u s , and as a result t h e transistor m o d e l s w e h a v e d e v e l o p e d d o not include a n y e l e m e n t s (i.e., capacitors or inductors) that w o u l d c a u s e t i m e or frequency d e p e n d e n c e . A c t u a l transistors, h o w e v e r , exhibit c h a r g e storage p h e n o m e n a that limit t h e speed and frequency of their operation. W e h a v e already e n c o u n t e r e d s u c h effects in our study of the pn j u n c t i o n in C h a p t e r 3 and learned that they can b e m o d e l e d u s i n g c a p a c i t a n c e s . In t h e following w e study t h e c h a r g e - s t o r a g e effects that take p l a c e in t h e B J T and t a k e t h e m into a c c o u n t b y a d d i n g c a p a c i t a n c e s to the h y b r i d - ^
{
l ] R
^
485
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.8
m o d e l . T h e resulting a u g m e n t e d B J T m o d e l will b e able to predict the observed dependence of amplifier gain o n frequency and t h e t i m e delays that transistor switches and logic gates exhibit.
T H E BJT INTERNAL C A P A C I T A N C E S A N D H I G H - F R E Q U E N C Y M O D E L
5.8.3 The Collector-Base Junction Capacitance C
u
In a c t i v e - m o d e operation, the C B J is r e v e r s e biased, and its j u n c t i o n or d e p l e t i o n c a p a c i t a n c e , usually d e n o t e d C^, can b e found from
C„ =
5.8.1 The Base-Charging or Diffusion Capacitance C
C
.
; ° ^
(5-156)
de
(1 + —
W h e n t h e transistor is operating in t h e active or saturation m o d e s , minority-carrier charge is stored in the b a s e r e g i o n . In fact, w e h a v e already d e r i v e d an e x p r e s s i o n for this charge, Q , n
in t h e c a s e of an npn transistor operating in t h e active m o d e (Eq. 5.7). Using the result in
where
E q . (5.7) together with E q s . (5.3) and (5.4), w e c a n express Q in terms of the collector current
and m is its g r a d i n g coefficient (typically, 0 . 2 - 0 . 5 ) .
is the value of
at zero voltage, V
0c
is the C B J built-in voltage (typically, 0.75 V ) ,
n
i
as
c
2
r
Qn =
= r i F
(5.150)
c
5.8.4 The High-Frequency Hybrid-^ Model Figure 5.67 shows the hybrid-7F model of the B J T , including capacitive effects. Specifically, there are t w o capacitances: the emitter-base capacitance C„ = C
w h e r e z is a d e v i c e constant,
+ C
de
je
and the collector-base
F
capacitance C . Typically, C„ is in the range of a few picofarads to a few tens of picofarads, and M
2
W r
Cu is in the range of a fraction of a picofarad to a few picofarads. N o t e that w e have also added
=
(5.151)
a resistor r to m o d e l the resistance of the silicon material of the b a s e region b e t w e e n the base
with the d i m e n s i o n of time. It is k n o w n as t h e f o r w a r d b a s e - t r a n s i t t i m e and represents the
terminal B and a fictitious internal, or intrinsic, b a s e terminal B ' that is right under the emitter
a v e r a g e t i m e a c h a r g e carrier (electron) s p e n d s in crossing t h e b a s e . Typically, T is in the
region (refer to Fig. 5.6). Typically, r is a few tens of o h m s , and its value depends on the cur
r a n g e of 10 ps to 100 p s . F o r operation in t h e r e v e r s e active m o d e , a corresponding constant
rent level in a rather complicated manner. Since (usually) r < r„, its effect is negligible at l o w
T applies a n d is m a n y orders of m a g n i t u d e larger than r .
frequencies. Its presence is felt, however, at high frequencies, as will b e c o m e apparent later.
F
x
x
F
R
x
F
E q u a t i o n (5.150) applies for large signals and, since i
c
is exponentially related to
v ,
T h e v a l u e s of t h e h y b r i d - n equivalent circuit p a r a m e t e r s c a n b e d e t e r m i n e d at a g i v e n
BE
T h u s this c h a r g e - s t o r a g e m e c h a n i s m represents a nonlinear
bias p o i n t u s i n g t h e f o r m u l a s p r e s e n t e d in this chapter. T h e y c a n also be found from t h e
capacitive effect. H o w e v e r , for s m a l l signals w e c a n define t h e small-signal diffusion
terminal m e a s u r e m e n t s specified o n the B J T data sheets. F o r c o m p u t e r simulation, S P I C E
capacitance
uses t h e p a r a m e t e r s of t h e g i v e n I C t e c h n o l o g y to e v a l u a t e t h e B J T m o d e l p a r a m e t e r s
Q will similarly d e p e n d o n v . n
BE
C, de
(Section 5.11). C
=^
de
(5.152)
B e f o r e p r o c e e d i n g , a n o t e o n notation is in order. S i n c e w e are n o w dealing w i t h volt ages and currents that are functions of frequency, w e h a v e reverted to u s i n g s y m b o l s that are uppercase letters with l o w e r c a s e subscripts (e.g., V„, I ). This conforms to the notation system c
T,
=
used t h r o u g h o u t this b o o k .
F
dv
BE
resulting in
5.8.5 The Cutoff Frequency C
= T
= rg
de
F
m
F
£
(5.153)
T h e transistor data sheets d o not usually specify the v a l u e of C . Rather, t h e b e h a v i o r of /3 K
(or hf ) v e r s u s frequency is n o r m a l l y given. In o r d e r to d e t e r m i n e C„ a n d e
5.8.2 The Base-Emitter Junction Capacitance C
fe
Je
U s i n g t h e d e v e l o p m e n t in C h a p t e r 3, and in particular E q . (3.58), the b a s e - e m i t t e r junction or depletion-layer c a p a c i t a n c e C
je
c a n b e e x p r e s s e d as C
le
= —
^
—
(5.154)
(i-YmX where C
je0
is the v a l u e of C
je
at zero voltage, V
0e
is the E B J built-in voltage (typically, 0.9 V),
and m is t h e g r a d i n g coefficient of t h e E B J j u n c t i o n (typically, 0.5). It turns out, however, that b e c a u s e the E B J is forward b i a s e d in t h e active m o d e , E q . (5.154) does not provide an accurate p r e d i c t i o n of C . Alternatively, o n e typically u s e s an a p p r o x i m a t e value for C , Je
je
C
je
= 2C
Je0
w e shall d e r i v e
an e x p r e s s i o n for h , the C E short-circuit current gain, as a function of frequency in t e r m s of
(5.155)
6 E FIGURE S . 6 7 The high-frequency hybrid-7T model.
4 8 7
4 8 8
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
5.8 „ T H E B J T I N T E R N A L C A P A C I T A N C E S A N D H I G H - F R E Q U E N C Y M O D E L
\h \ (dB) A
-*
fe
I ßo
FIGURE 5 . 6 8 Circuit for deriving an expression for h (s) = fe
3 dB
I /l c
h
0 dB
1
- 6 dB/octave
i
\ i w
the h y b r i d - c o m p o n e n t s . F o r this p u r p o s e c o n s i d e r the circuit s h o w n in F i g . 5.68, in w h i c h the collector is shorted to the emitter. A n o d e equation at C provides the short-circuit collector current I as
r
(i) (log scale)
FIGURE 5 . 6 9 Bode plot for \h
c
I
= (g -sC )V
c
m
fl
(5.157)
n
A relationship b e t w e e n V„ a n d l can b e established b y m u l t i p l y i n g between B ' a n d E :
Thus,
b y the i m p e d a n c e seen
b
(5.162) C„+C„ and
V
n
= hirJICJI-CJ
=
- * ± Hr + sC n
Thus h
fe
(5.158) K
+ sC
tl
fx
(5.16-3)
=
2K(C +C ) K
can b e o b t a i n e d b y c o m b i n i n g E q s . (5.157) a n d (5,158): The unity-gain bandwidth f
T
some cases f
T
f e
~
h ~
\lr
n
+
s(C +C^ M
that g
m
A t the frequencies for w h i c h this m o d e l is valid, g in the n u m e r a t o r a n d w r i t e
> coC^ thus w e c a n neglect the sC^ t e r m
m
ß
is u s u a l l y specified on t h e d a t a s h e e t s of a transistor. In
is g i v e n as a function of I
and V .
c
CE
T o see h o w f
T
is directly p r o p o r t i o n a l to l , b u t only p a r t of C c
%
changes with I , c
recall
(the diffusion c a p a c i t a n c e C )
is
de
directly p r o p o r t i o n a l t o I . It follows t h a t / d e c r e a s e s at l o w currents, as s h o w n in Fig. 5.70. c
r
H o w e v e r , t h e d e c r e a s e in f
T
at h i g h c u r r e n t s , a l s o s h o w n in F i g . 5 . 7 0 , c a n n o t b e e x
p l a i n e d b y this a r g u m e n t ; r a t h e r it is d u e to t h e s a m e p h e n o m e n o n that c a u s e s / 3 to 0
d e c r e a s e at h i g h c u r r e n t s . In t h e r e g i o n w h e r e f
T
is a l m o s t c o n s t a n t , C„is d o m i n a t e d b y t h e
diffusion part. Typically, f
Thus,
T
T
n
<5l59) -
is in t h e r a n g e of 100 M H z to tens of G H z . T h e v a l u e oif
E q . (5.163) to d e t e r m i n e C + C^. T h e c a p a c i t a n c e
m e a s u r i n g the c a p a c i t a n c e b e t w e e n b a s e and collector at the desired reverse-bias voltage
I+*(C!v,
w h e r e / 3 is the l o w - f r e q u e n c y v a l u e of /3. T h u s h with a 3-dB frequency at co = w , w h e r e 0
fe
h a s a single-pole (or S T C ) r e s p o n s e
1 0
B
Figure 5.69 s h o w s a B o d e p l o t for \h \. fe
quency at w h i c h \h \ fe
F r o m t h e - 6 - d B / o c t a v e slope it follows that the fre
drops to unity, which is called the u n i t y - g a i n b a n d w i d t h (o
T
= /3 ®B 0
is given by -
can b e u s e d in
is usually d e t e r m i n e d separately b y
(5.161)
The frequency response of single-time-constant (STC) networks was reviewed in Section 1.6. Also, a more detailed discussion of this important topic can be found in Appendix D.
FIGURE 5.70
Variation
off
T
w i t h Ic
V . CB
" ..
4 8 9
490
J
5.9
CHAPTER 5 B I P O L A R J U N C T I O N T R A N S I S T O R S ( B J T s )
Before leaving this section, w e should m e n t i o n that the hybrid-?r m o d e l of Fig. 5.68 char acterizes transistor operation fairly accurately u p to a frequency of about 0.2f . A t higher fre T
FREQUENCY RESPONSE OF THE COMMON-EMITTER
AMPLIFIER
5.9 FREQUENCY RESPONSE OF THE , „ COMMON-EMITTER AMPLIFIER
q u e n c i e s o n e h a s t o a d d other parasitic e l e m e n t s to t h e m o d e l as w e l l as refine t h e m o d e l to a c c o u n t for t h e fact that t h e transistor is in fact a distributed-parameter n e t w o r k that w e are
In this section w e study t h e d e p e n d e n c e of the gain of t h e B J T c o m m o n - e m i t t e r amplifier of a
trying to m o d e l w i t h a l u m p e d - c o m p o n e n t circuit. O n e such refinement consists of splitting r
Fig- 5 - 7 1 ( )
o
n
t
n
e
frequency of the input signal.
into a n u m b e r of parts a n d replacing C b y a n u m b e r of capacitors, e a c h c o n n e c t e d between M
5.9.1 The Three Frequency Bands
the collector a n d o n e of the taps of r . This topic is b e y o n d t h e scope of this b o o k . x
A n important observation to m a k e from the high-frequency m o d e l of Fig. 5.68 is that at fre quencies above 5 to 10fy, o n e m a y ignore the resistance r„. It can b e seen then that r becomes x
W h e n t h e c o m m o n - e m i t t e r amplifier circuit of F i g . 5.71(a) w a s studied i n Section 5.7.3, it was a s s u m e d that t h e c o u p l i n g capacitors C
a
and C
c 2
and the bypass capacitor C
E
were
the only resistive part of the input i m p e d a n c e at high frequencies. T h u s r plays a n important x
role in determining t h e frequency response of transistor circuits at high frequencies. It follows that a n accurate deterrrrination of r should b e m a d e from a high-frequency measurement. x
5.4S Find ( ' . C . C-. ( ' . . and /;. for a H.I F opcraiinc al a dc eulkvioi curivM /, - i iii.\ ami a CHJ r c . c r v bias of 2 V. The 'device has T, = 20 ps. C = 20 f F, Q , = 20 f F, V , = 0.9 V, V , = 0.5 V, and m = 0.33. je0
0
n
CBJ
Ans. 0.8 pF; 4 0 IF; 0.84 p F ; 12 fF; 7.47 GHz 5.49 For a B J T operated at I = 1 mA, d e t e r m i n e / ^ and C if C = 2 p F and \h | = 10 at 5 0 M H z . c
Ans. 5H1I MHz: IC.7 p !
x
u
f f
;
5.50 If C„ of the BJT in Exercise 5.49 includes a relatively constant depletion-layer capacitance of 2:pF, find f of the BJT when operated at / , = 0.1 m A . T
Ans. 13«i.7 M i l /
5.8.6 Summary F o r c o n v e n i e n t reference, T a b l e 5.7 p r o v i d e s a s u m m a r y of the relationships u s e d t o deter m i n e t h e v a l u e s of the p a r a m e t e r s of t h e B J T h i g h - f r e q u e n c y m o d e l .
TABLE 5.7
li — V v V
The BJT High-Frequency M o d e l
*
—•
—
^ — • — I I —
* —
«
r
i
.V,
8 m = I /Vt
r
C
0
%
G-n+C^ =
C„ = C /(l jc0
^
+ ^T,
= \V \/I A
r
C
K
+
~ Cde Cj
e
m = 0.3-0.5
C
de
-(
=
ß /g 0
= Tg F
m
m
Cj = e
2Cj
e0
FIGURE 5 . 7 1 (a) Capacftively coupled common-emitter amplifier, (b) Sketch o f the magnitude of the gain of the CE amplifier versus frequency. The graph delineates the three frequency bands relevant to frequencyresponse determination.
492
:
CHAPTER 5
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
5.9
acting as perfect short circuits at all signal frequencies of interest. W e also neglected the inter nal capacitances of the BJT. That is, C and of the B J T high-frequency m o d e l (Fig. 5.67) w e r e assumed to be sufficiently small to act as open circuits at all signal frequencies of interest. A s a result of ignoring all capacitive effects, the gain expressions derived in Section 5.7.3 were independent of frequency. In reality, h o w e v e r , this situation only applies o v e r a limited, though usually w i d e , b a n d of frequencies. This is illustrated in F i g . 5.71(b), w h i c h shows a sketch of the m a g n i t u d e of the overall voltage gain, \G \, of the c o m m o n emitter amplifier versus frequency. W e o b s e r v e that the gain is a l m o s t constant o v e r a w i d e frequency band, called the m i d b a n d . T h e v a l u e of the m i d b a n d gain A c o r r e s p o n d s to t h e overall voltage gain G that w e derived in Section 5.7.3, n a m e l y ,
T h e e q u i v a l e n t circuit of F i g . , 5 . 7 2 ( a ) can b e simplified b y utilizing T h e v e n i n t h e o r e m at t h e i n p u t side a n d b y c o m b i n i n g t h e t h r e e parallel r e s i s t a n c e s at t h e o u t p u t side. Specif ically, t h e r e a d e r s h o u l d b e able to s h o w that a p p l y i n g T h e v e n i n t h e o r e m twice simplifies the resistive n e t w o r k at t h e input side to a signal g e n e r a t o r V ' a n d a r e s i s t a n c e R' ,
K
s ig
x
V
(
TT-
-
c2
B'
c -o +
©
R
-, M +P
G
g
"
(
R
° "
R
C
"
R
L
)
(
5
-
1
6
4
)
IT
Figure 5.71(b) shows that the gain falls off at signal frequencies b e l o w and a b o v e t h e m i d b a n d . T h e gain falloff in the l o w - f r e q u e n c y b a n d is d u e to the fact that e v e n t h o u g h C , C , and C are large capacitors (typically, in the /iF r a n g e ) , as t h e signal frequency is r e d u c e d their impedances increase and they n o longer b e h a v e as short circuits. O n the other h a n d , the gain falls off in the h i g h - f r e q u e n c y b a n d as a result of C and C , w h i c h t h o u g h v e r y small (in the fraction of a p F to t h e p F r a n g e ) , their i m p e d a n c e s at sufficiently h i g h fre quencies decrease; thus they can n o longer b e c o n s i d e r e d as open circuits. O u r objective in this section is to study the m e c h a n i s m s b y w h i c h these t w o sets of capacitances affect the amplifier gain in the low-frequency and the high-frequency b a n d s . In this w a y w e will b e able to determine the f r e q u e n c i e s / a n d / , w h i c h define the extent of the m i d b a n d , as s h o w n in Fig. 5.71(b). C1
C„
B
g
si
+
M
=
si
- V W
v
A-M
FREQUENCY RESPONSE O F THE C O M M O N - E M I T T E R AMPLIFIER
(a)
E
gs
L
X c
gd
"7, "
B'
L
W V -
+
X'
4>
f f
T h e m i d b a n d is obviously the useful frequency b a n d of the amplifier. Usually, f andf are the frequencies at which the gain drops b y 3 d B b e l o w its value at m i d b a n d ; that is, a t / a n d / , |gain| = \A \/Jl. T h e amplifier b a n d w i d t h or 3-dB b a n d w i d t h is defined as the difference b e t w e e n the l o w e r (f ) and u p p e r or h i g h e r (f ) 3-dB frequencies: L
H
L
H
M
L
7
*
V
* R + R B
sig
r„ + r + x
(R //R ) üg
R'L =
rjR //R c
L
B
H
BW = f -f H
(5.165)
L
Ki
g
= rj[r
z
+
(RjR )] sig
(b)
S i n c e usually f
L
<
f, H
BW =
f
H
A figure-of-merit for the amplifier is its g a i n - b a n d w i d t h product, defined as GB = \A \BW
(5.166)
M
It will b e s h o w n at a later stage that in amplifier design, it is usually possible to trade off gain for bandwidth. O n e w a y of a c c o m p l i s h i n g this, for instance, is b y including an emitterdegeneration resistance R , as w e h a v e d o n e in Section 5.7.4. e
5.9.2 The High-Frequency Response T o determine the gain, or the transfer function, of the amplifier of Fig. 5.71(a) at h i g h fre quencies, and in particular t h e u p p e r 3-dB frequency f , w e replace the B J T with t h e highf r e q u e n c y m o d e l of F i g . 5.67. A t t h e s e f r e q u e n c i e s C , C , a n d C will b e b e h a v i n g as perfect short circuits. T h e result is t h e high-frequency amplifier equivalent circuit s h o w n in F i g . 5.72(a). H
cl
C2
t
FIGURE 5 . 7 2 Determining the high-frequency response of the CE amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at both the input side and the output side; (c) equivalent circuit with C replaced at the input side w i t h the equivalent capacitance C ;
p
CHAPTER 5
5.9
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
FREQUENCY RESPONSE O F THE C O M M O N - E M I T T E R AMPLIFIER
w h i c h results in (dB) V
SIG
C
-6 dB/octave 20dB/decade
= C„(l + g R' )
eq
m
(5.170)
L
U s i n g C e n a b l e s u s t o simplify t h e e q u i v a l e n t circuit at t h e input side t o that s h o w n in Fig. 5.72(c), w h i c h w e r e c o g n i z e as a single-time-constant ( S T C ) n e t w o r k of the l o w - p a s s t y p e (see Section 1.6 a n d A p p e n d i x D ) . Therefore w e c a n express V ^ i n t e r m s of V' as eq
sig
V
^
=
-
V
(
' * T T 7 7 ^
5
-
1
7
1
)
w h e r e a> is the corner frequency of the S T C n e t w o r k c o m p o s e d of C and R^ 0
fn
j n
f (Hz, log scale) (o
= 1/C y?;
0
(d)
in
(5.172)
ig
w h e r e C is the total input capacitance at B ' ,
F I G U R E 5 . 7 2 (Continued) (d) sketch of the frequency-response plot, which is that of a low-pass
i n
STC circuit.
C
m
where
= C+ C n
= C + C (l + g R' )
eq
K
M
m
(5.173)
L
and 7? ' is t h e effective source resistance, given b y E q . (5.168). C o m b i n i n g E q s . (5.169), (5.171), a n d (5.167) give t h e voltage gain in the high-frequency b a n d as s ig
V'. = V • — — R + R r +r Slg
—
s l s
B
si$
n
+
x
(5.167) (R \\R ) sig
B
R
r •
B
RL
= rJ[r +(R \\R* )] x
B
Vug
(5.168)
s
LR + R B
m
r +r +
sig
E
f
g R'
K
L
(R
x
\
1
(5.174)
II R )j 1 + A
sig
B
(o J 0
O b s e r v e that R'
sig
is the resistance seen looking b a c k into t h e resistive n e t w o r k b e t w e e n nodes
B ' and E.
T h e quantity b e t w e e n the square brackets of E q . (5.174) is the m i d b a n d gain, a n d e x c e p t for the fact that h e r e r is t a k e n into account, this expression is t h e s a m e as that in E q . (5.164). Thus, x
T h e circuit in F i g . 5.72(b) can b e simplified further if w e c a n find a w a y t o deal with the bridging c a p a c i t a n c e that connects t h e output n o d e to t h e " i n p u t " n o d e , B ' . T o w a r d that e n d consider first the output n o d e . It can b e seen that t h e l o a d current is (g V - 1 ^ , w h e r e g,„V„ is t h e o u t p u t current of the transistor a n d I is t h e current supplied through t h e very small c a p a c i t a n c e C^. In t h e vicinity of f , w h i c h is close t o t h e e d g e of the m i d b a n d , it is r e a s o n a b l e t o a s s u m e that 7 is still m u c h s m a l l e r than g V„, with t h e result that V„ c a n b e given approximately by m
7 ^
n
=
(5.175) I _|
' sig
p
H
/(
m
V
0
a -g V R' m
n
L
= -g R' V m
L
ce
m
L
t h e s a m e value as
=
S
=
7
i
r
(
r p '
m
+
g R' )V m
L
K
x
sig
s ig
sig
n
sig
p
eq
M
eq
M
=
= sC„(l +
g R' )V m
L
n
7
6
)
s ig
B
H
%
n
H
eq
2. T h e input c a p a c i t a n c e C is usually d o m i n a t e d b y C , w h i c h in turn is m a d e large b y the multiplication effect that C undergoes. T h u s , although is usually very small, its effect o n t h e amplifier frequency r e s p o n s e c a n b e significant as a result of its i n
eq
M
sC V
in
sig
SIG
N o w , in F i g . 5.72(b), t h e left-hand-side of t h e circuit, at X X ' , k n o w s of t h e existence of C only t h r o u g h t h e current 1^. Therefore w e c a n r e p l a c e b y a n equivalent capacitance C b e t w e e n B ' a n d g r o u n d as long as C d r a w s a current equal t o 7 . T h a t is,
1
sig
sig
M
"
1. T h e u p p e r 3-dB frequency is d e t e r m i n e d b y t h e interaction of R' a n d C . If R §> R a n d r
= sC (l
5
T h u s w e s e e that the high-frequency r e s p o n s e will b e that of a low-pass S T C n e t w o r k w i t h a 3-dB frequency f d e t e r m i n e d b y t h e t i m e constant C- R' . F i g . 5.72(d) s h o w s a sketch of the m a g n i t u d e of t h e high-frequency gain. Before leaving this section w e w i s h t o m a k e a n u m b e r of observations: H
in the m i d b a n d . T h e current 1^ can n o w b e found from
must be
H
(5.169)
K
S i n c e V = V , E q . (5.169) indicates that the g a i n from B ' t o C is -g R' , 0
from w h i c h w e d e d u c e that the upper 3-dB frequency f
CHAPTER 5
BIPOLAR J U N C T I O N TRANSISTORS
5.9
(BJTS)
multiplication b y the factor (1 + g R' ), m
w h i c h is approximately equal to the m i d b a n d
L
gain of the amplifier.
L
g R' m
This effect is k n o w n as the M i l l e r effect, and (1 + g R' ) m
and
is k n o w n as the
L
A
Miller multiplier. It is the M i l l e r effect that c a u s e s the C E amplifier to h a v e a large input capacitance C
i n
= 40 x 3 = 120 V/V
L
u n d e r g o e s c o m e s a b o u t b e c a u s e it is c o n n e c t e d
b e t w e e n t w o n o d e s ( B ' and C ) w h o s e v o l t a g e s are related b y a large n e g a t i v e gain m
AMPLIFIER
Thus,
|
3. T h e multiplication effect that (-g R' ).
j
FREQUENCY RESPONSE OF THE COMMON-EMITTER
1
M
0
0
x
100 + 5
2
5
" xl20 2 . 5 + 0 . 0 5 + (100 II 5 )
and h e n c e a l o w f . H
= - 3 9 V/V
4 . T o extend the high-frequency r e s p o n s e of a B J T amplifier, w e h a v e to find configura tions in w h i c h t h e Miller effect is a b s e n t or at least r e d u c e d . W e shall return to this
and
subject at great length in C h a p t e r 6.
20 l o g \ A \ = 32 dB M
5. T h e a b o v e analysis, resulting in an S T C or a single-pole r e s p o n s e , is a simplified o n e . Specifically, it is b a s e d o n n e g l e c t i n g 1^ relative to g V , an a s s u m p t i o n that applies m
K
To determine f
H
we first find C , in
well at frequencies not too m u c h h i g h e r t h a n / . A m o r e e x a c t analysis of t h e circuit H
C
in Fig. 5.72(a) will b e c o n s i d e r e d in C h a p t e r 6. T h e results a b o v e , h o w e v e r , are m o r e
= C +C^l
f a
than sufficient for our current n e e d s .
R'
sig
It is required to find the midband gain and' the upper 3-dB frequency of the common-emitter , amplifier of Fig. 5.71(a) for the following case: V
cc
sig
= V =10V,I=1
0
m
L
B
c
T
sia
= rJ
[r + x
(R \\R )] B
sig
= 1.65 k Q
= 1 pF, f = 800 M H z , and r = 50 Q.
A
R' ,
= 2.5 II [ 0 . 0 5 + ( 1 0 0 II 5 ) ]
m A , R = 100 k Q , R =
EE
= 5 k Q , R = 5 k Q , B = 100, V = 100 V, L
g R' )
= 7 + 1(1 + 120) = 128 p F and the effective source resistance
8 kQ, i?
+
n
x
Thus,
Solution The transistor is biased a t /
c
= 1 m A . Thus the values of its hybrid-7T model parameters are
fn =
* , g
2 ? r C
-
-
A
-
g
m
1
0
0
40 m A / V
yA
LOO
I
V
= 2.5 k Q
\ p In
x
128 x 10
- = 754 k H z
:
x 1.65
x
10
EXERCISE
= 100 k Q
5.51 For the amplifier in Example 5.18. find (he value of R that reduces the midband gain to half the L
1 mA
c
=
in^sig
found. What value of , / results? Note the trade-off between gain and bandwidth. w
g
r n + u C
C
=
™ —
40 X 1 0 "
=
a
T
C
ß
27ZX
800
X
3 8
x
i
F
Ans.
W kQ: I
.J
2
Mil/
10
= 1 pF
5.9.3 The Low-Frequency Response
C* = 7 p F r
r
7 = » pr
To d e t e r m i n e t h e l o w - f r e q u e n c y gain (or transfer function) of the c o m m o n - e m i t t e r amplifier
= 50 Q
circuit, w e s h o w in F i g . 5.73(a) t h e circuit w i t h t h e d c s o u r c e s e l i m i n a t e d (current s o u r c e I open circuited a n d v o l t a g e s o u r c e V
cc
short c i r c u i t e d ) . W e shall p e r f o r m t h e s m a l l - s i g n a l
analysis d i r e c t l y o n this circuit. W e will, of c o u r s e , i g n o r e C
n
and
s i n c e at s u c h l o w
frequencies t h e i r i m p e d a n c e s w i l l b e v e r y h i g h a n d t h u s c a n b e c o n s i d e r e d as o p e n cir
The midband voltage gain is
cuits. A l s o , to k e e p t h e a n a l y s i s s i m p l e a n d t h u s focus a t t e n t i o n o n t h e m e c h a n i s m s t h a t limit t h e a m p l i f i e r g a i n at l o w f r e q u e n c i e s , w e will n e g l e c t r . a
t h r o u g h S P I C E s i m u l a t i o n that t h e effect of r
0
T h e r e a d e r c a n verify
o n t h e l o w - f r e q u e n c y amplifier g a i n is
small. F i n a l l y , w e shall also n e g l e c t r„ w h i c h is u s u a l l y m u c h s m a l l e r t h a n r , w i t h w h i c h n
where
it a p p e a r s in series. R' = r \\R \\R = (100 II 8 II 5) k Q = L
0
c
L
3kQ
5.9 FREQUENCY RESPONSE OF THE COMMON-EMITTER AMPLIFIER
ON
P
-VVSf o— V
>
R
b
(a)
(dB)
A r _ 3 dB_
T
R. "sig
/
C
C1
-wv-
HI
+
©
20 lo
6 dB / octave 20 dB/decade
| |
1
fpx
/„ = 1/217-eh
I
f (Hz, log scale) [(^/Ag + ^
s i g
]
(b)
(dB)
(e)
E—~3dB
FIGURE 5 . 7 3 (Continued) (d) the effect of C is determined with C and C assumed to be acting as perfect short circuits; (e) sketch of the low-frequency gain under the assumptions that C , C , and C do not interact and that their break (or pole) frequencies are widely separated. C2
~~T~
1^4
C1
C , and C E
c2
E
6 dB/octave 20 dB/decade
*
C , w e assume that C E
fp2 = 1 / 2 T 7 C
r, +
C 1
one at a time. T h a t i s , w h e n f i n d i n g t h e effect of C , C 1
are a c t i n g as p e r f e c t short c i r c u i t s , a n d w h e n c o n s i d e r i n g
C2
and C
C2
are perfect s h o r t c i r c u i t s , a n d so o n . T h i s is o b v i o u s l y
a m a j o r s i m p l i f y i n g a s s u m p t i o n — a n d o n e that m i g h t n o t b e j u s t i f i e d . H o w e v e r , it s h o u l d
i
fp2
/ (Hz, log scale)
s e r v e as a first c u t at the a n a l y s i s e n a b l i n g u s t o g a i n i n s i g h t i n t o t h e effect of t h e s e capacitances. F i g u r e 5.72(b) s h o w s t h e circuit with C a n d C E
£
r, +
/3+ 1
V
= V Slg
RB
(R \\r ) B
FIGURE 5 . 7 3 Analysis of the low-frequency response of the CE amplifier: (a) amplifier circuit with dc sources removed; (b) the effect of C is determined with C and C assumed to be acting as perfect short circuits; (c) the effect of C is determined with C and C assumed to be acting as perfect short circuits; C2
C 2
E
I!
r,
+ R
r[
sig
+-
and the output v o l t a g e is obtained as
c l
V
a
4 9 8
r e p l a c e d w i t h short circuits. T h e volt
C2
age V„ at t h e b a s e of the transistor c a n b e written as
(c)
E
C 2
O u r first c u t at t h e a n a l y s i s of t h e circuit in F i g . 5.72(a) is to c o n s i d e r t h e effect of t h e w e shall a s s u m e that C a n d C
C1
E
-ov„
three capacitors C ,
03+ 1)
E
C1
20 lo
©
ci
=
- g
m
V M \ R
L
)
j
J499
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
5.9
(BJTs)
T h e s e t w o equations can b e combined to obtain the voltage gain V / V 0
of C
s i g
including the effect
as
c l
(R (R
V Slg
x
m
II
B
C 2
(5.177)
-g (R \\R ) c
L
r,) + R
s
C1
R
= y B-
'
IT
' Sltr
A
r
«
CM r ) + R K
ag
C [ ( Ä I I rJ + R^X C 1
B
V
is to i n t r o d u c e the f r e q u e n c y - d e p e n d e n t factor
C 1
E
and
s +
from w h i c h w e o b s e r v e that the effect of C
AMPLIFIER
Finally, w e consider the effect of C . T h e circuit with C and C a s s u m e d to b e acting as perfect short circuits is s h o w n in Fig. 5.73(d), for w h i c h w e can write v
II r )
B
FREQUENCY RESPONSE OF THE COMMON-EMITTER
= -g
^
V
b e t w e e n the square brackets on the right-hand side of E q . (5.177). W e r e c o g n i z e this factor
Rr
Rc + -pr- + R
L
S
^C2
as t h e transfer fraction of a single-time-constant ( S T C ) n e t w o r k of t h e h i g h - p a s s t y p e (see
T h e s e t w o e q u a t i o n s c a n b e c o m b i n e d to o b t a i n the l o w - f r e q u e n c y gain i n c l u d i n g t h e effect
Section 1.6 a n d A p p e n d i x D) with a c o r n e r (or b r e a k ) frequency (0 , PL
of C fflp,
=
rr
P 1
N o t e that [(R II r„) +R ] B
as
(5.178)
CcdiRsMrj
is the resistance
sig
c 2
V _ R II r T T " ~ ~TET~\\—x , p ^sk (R II rf) + R 0
+ R^]
seen between
the terminals
of C
cl
when
V
sig
B
B
is
,. gmXRcWRh)
K
(5.181) s
sig
+
C2
set to zero. T h e S T C high-pass factor introduced by C
1
C {R
+ R)
C
L
will c a u s e the amplifier gain to roll
cl
off at l o w frequencies at the rate of 6 d B / o c t a v e ( 2 0 d B / d e c a d e ) with a 3-dB frequency at
W e o b s e r v e that C
f
w h i c h w e r e c o g n i z e as the transfer function of a h i g h - p a s s S T C n e t w o r k with a b r e a k fre
= (O /2K,
Pl
pi
as indicated in Fig. 5.73(b).
N e x t , w e c o n s i d e r t h e effect o f C . F o r this p u r p o s e w e a s s u m e that C E
C 1
and C
C2
are
inti-oduces the frequency-dependent factor b e t w e e n the square brackets,
C2
quency
co , P3
a c t i n g a s perfect s h o r t circuits a n d t h u s o b t a i n t h e c i r c u i t i n F i g . 5 . 7 3 ( c ) . R e f l e c t i n g r
e
a n d C i n t o t h e b a s e circuit a n d u t i l i z i n g , T h e v e n i n t h e o r e m e n a b l e s u s to o b t a i n t h e b a s e
F 3
E
c u r r e n t as
C (R C2
+R)
C
H e r e w e note that as e x p e c t e d , (R + R ) is the resistance c
when V
1
RR
sig
L
is set to zero. T h u s capacitor C
C2
^
L
seen between
= CD /2K,
P3
^(^ll R J
S
I
g
) + (/3+l)(r + ^ -
as illustrated b y
P3
N o w that w e h a v e d e t e r m i n e d the effects of e a c h of C , C , a n d C cl
=
c
L
B(R II R )
B
C
L
V • " Slg
+ R<; (R
II R
B
acting alone, t h e
T h e a n s w e r is that the amplifier low-frequency gain c a n b e e x p r e s s e d as
R RR
C2
h a s t w o parts: First, w h a t h a p p e n s w h e n all three capacitors are present but d o not interact?
-Bl (R \\R ) b
E
question b e c o m e s w h a t will h a p p e n w h e n all three are present at the s a m e time. This question
b
D
C2
the sketch in F i g . 5.73(d).
e
T h e collector current can then b e found as Bl a n d the o u t p u t v o l t a g e as V
ofC
c a u s e s t h e l o w - f r e q u e n c y gain of t h e amplifier to
d e c r e a s e at t h e rate of 6 d B / o c t a v e w i t h a 3-dB frequency at f S 1 S j R s +
the terminals
^
) + (ß+l)(r
V
+ 4 r sCi
e
is + G) As
sig
Pl
+ G) As P2
+
from w h i c h w e see that it acquires three b r e a k frequencies a t /
T h u s the v o l t a g e gain including the effect of C c a n b e e x p r e s s e d as
w j P3
P 1
,/
, a n d / , all in t h e l o w -
F 2
r a
frequency b a n d . If the t h r e e frequencies are w i d e l y separated, their effects will b e distinct,
E
as indicated b y the sketch in F i g . 5.73(e). T h e i m p o r t a n t p o i n t to n o t e h e r e is that t h e 3-dB ß(R
RR
c
Rs + R^iRsWR^
IIR ) + iß+iy,
(5.179)
L
R
1 / C Ü r„ +
s +
B
II
frequency f
L
is determined
by the highest
of the three break frequencies.
This is usually the
b r e a k frequency c a u s e d b y the b y p a s s capacitor C , s i m p l y b e c a u s e the r e s i s t a n c e that it sees
-^si
E
is u s u a l l y quite small. T h u s , e v e n if o n e uses a l a r g e v a l u e for C , f
J8+1
E
P2
is usually the h i g h e s t
of the t h r e e b r e a k frequencies. W e o b s e r v e that C introduces t h e S T C h i g h - p a s s factor o n t h e e x t r e m e r i g h t - h a n d side.
~Kfpi>fp2>
E
a n
d / p 3 are c l o s e together, n o n e of t h e three d o m i n a t e s , a n d to d e t e r m i n e f , L
T h u s C c a u s e s the gain to fall off at l o w frequency at t h e rate of 6 d B / o c t a v e w i t h a 3-dB
h a v e to e v a l u a t e | V / V
frequency e q u a l to the corner (or b r e a k ) frequency of t h e h i g h - p a s s S T C factor; that is,
\A \/j2.
E
0
M
s i g
we
| in E q . (5.183) a n d calculate the frequency at w h i c h it drops t o
T h e w o r k i n v o l v e d in d o i n g this, h o w e v e r , is usually t o o great a n d is rarely j u s t i
fied in p r a c t i c e , particularly b e c a u s e in any c a s e , E q . (5.183) is an a p p r o x i m a t i o n b a s e d on (5.180)
a> = P2
RB
C
r. + -
f
O b s e r v e that [r + ((R II R )/(P e
C
E
when V
sig
B
six
+ l))]is
II
R\
ß+i
the resistance
C seen between
the two terminals
of
is set to zero. T h e effect of C o n the amplifier frequency r e s p o n s e is illustrated
b y the sketch in F i g . 5.73(c).
E
the a s s u m p t i o n that t h e t h r e e capacitors d o not interact. This leads to the second p a r t of t h e question: W h a t h a p p e n s w h e n all three capacitors are p r e s e n t a n d interact? W e d o k n o w that
S
C 1
and C usually interact a n d that their c o m b i n e d effect is t w o p o l e s at frequencies that E
will differ s o m e w h a t from co
Pl
a n d co . Of c o u r s e , o n e c a n derive the overall transfer func P2
tion taking this interaction into a c c o u n t a n d find m o r e precisely the low-frequency r e s p o n s e . This, h o w e v e r , will b e too c o m p l i c a t e d to yield additional insight. A s an alternative, for h a n d
502
I
CHAPTER 5
5.10
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
calculations w e can obtain a reasonably g o o d estimate for f
using t h e following formula
L
( w h i c h w e will not derive h e r e )
Next, if C \ is to contribute 10% of f , C
L
1 1
1 1
h
~ 2 K
R
Ca ci
CR E
Cl
C
(5.184)
CR
E
R , and R E
= fp\ + fp2 + fps CI
E
C2
sig
1
is
= 0.1 x 2n x 100
Crn x 13 x 10
set to zero a n d the other t w o capacitances are replaced with short circuits. Equations (5.184) and (5.185) p r o v i d e insight regarding t h e relative contributions of the three capacitors
= 2.1 fjF
£
(5.185)
are the resistances seen b y C , C , a n d C , respectively, w h e n V
C2
C 1
is to contribute 10% of/ , its value should be selected as follows:
C2
cl
= 0.1 x 2n x 100
x 7 . 4 4 x 10 C
Similarly, if C A
c l
c
or equivalently,
where R ,
T H E BASIC BJT DIGITAL LOGIC INVERTER
C
C 2
= 1.2 fiF
tof . L
Finally, w e note that a far m o r e precise determination of the low-frequency gain a n d t h e 3-dB
In practice, w e would select the nearest standard values for the three capacitors while ensuring
f r e q u e n c y ^ c a n b e obtained using S P I C E (Section 5.11).
t h a t / i < 100 H z .
Selecting Values for C , C , and C C1
p r i a t e v a l u e s for C quency f
L
E
C . and C .
c u
E
W e n o w address the design issue of selecting appro-
C2
T h e d e s i g n o b j e c t i v e is t o p l a c e t h e l o w e r 3 - d B fre-
c2
EXERCI
at a specified location while m i m m i z i n g the capacitor values. Since as mentioned
a b o v e C usually sees the lowest of the three resistances, the total capacitance is m i n i m i z e d by E
5.52 A common-emitter amplifier has = C = C = 1 juF, R = 100 k Q , R^ = 5 k Q . g = 4 0 mA /V, r„ = 2.5 k Q . R = 8 kQs and R = 5 k Q . Assuming that the three capacitors d o not interact, find/p,,./,.,, and f , and hence, estimate f . E
selecting C so that its contribution tof E
is dominant. T h a t is, b y reference to E q . (5.184), w e
L
c
m a y select C such that l/(C R ) E
E
is, say, 8 0 % of co = 2nf , leaving each of the other capac-
E
L
L
n
itors t o contribute 10% to the value of co . E x a m p l e 5.19 should help to illustrate this process. L
cl
B
m
L
L
Ans. 21.4 Hz; 2.21 k H z ; 1.2.2 Hz; since f > J a n d / , / , ; ' S ' / . = 2.21 kHz; using Eq. (5.185), a somewhat belter estimate for/>, is obtained as 2.24 kHz P2
n
r o
r a
5.9.4 A Final Remark W e wish to select appropriate values for C
ch
C , and C for the common-emitter amplifier whose C2
E
T h e frequency r e s p o n s e of the other amplifier configurations will b e studied in C h a p t e r 6.
high-frequency response was analyzed in Example 5.18. The amplifier has R = 100 kQ, R = 8 kQ, B
R = 5 kQ, R L
sig
= 5 kQ, A, = 100, g = 4 0 mA/V, and
c
= 2.5 kQ. It is required to have f = 100 Hz.
m
L
-.10
Solution W e first determine the resistances seen by the three capacitors C , C , and C cl
E
C2
as follows:
THE BASIC BJT DIGITAL LOGIC INVERTER
T h e m o s t f u n d a m e n t a l c o m p o n e n t of a digital s y s t e m is t h e logic inverter. In Section 1.7, t h e logic inverter w a s studied at a conceptual level, and the realization of the inverter using voltage-
Rci
= {R \\r^
+ R^
B
controlled s w i t c h e s w a s presented. H a v i n g studied t h e B J T , w e c a n n o w consider its application i n t h e realization of a s i m p l e logic inverter. S u c h a circuit is s h o w n in Fig. 5.74. T h e
= (100 II 2 . 5 ) + 5 = 7.44 kQ
r e a d e r will n o t e that w e h a v e already studied this circuit in s o m e detail. In fact, w e u s e d it in Section 5.3.4 to illustrate t h e operation of the B J T as a switch. T h e operation of the circuit as a ^ ~
r
e
+
¡3+1
= 0.025 + M H J 101 R
C2
= r
c
+r
l
=
Q
0
?
2 K
Q
=
7
2
Q
= 8 + 5 = 13 kQ
Now, selecting C so that it contributes 8 0 % of the value of co gives E
L
o
l
— - — = 0.8 x 2n x 100 C x 72
v
0
E
C
E
= 27.6 juF
The interested reader can refer to Chapter 7 of the fourth edition of this book.
V[ o
V W
FIGURE 5 . 7 4 Basic BJT digital logic inverter.
5 0
CHAPTER 5
BIPOLAR JUNCTION
TRANSISTORS
(BJTS)
5.10
logic inverter m a k e s use of the cutoff and saturation m o d e s . In very simple terms, if the input voltage v, is "high," at a value close to the power-supply voltage V , (representing a logic 1 in a positive-logic system) the transistor will be conducting and, with appropriate choice of values for R and R , saturated. T h u s the output voltage will be V s 0.2 V , representing a " l o w " logic level or logic 0 in a positive logic system. Conversely, if the input voltage is "low," at a value close to ground (e.g., V ) , then the transistor will b e cut off, i will be zero, and v - V , which is " h i g h " or logic 1. cc
B
c
characteristic of Fig. 5.75 for a representative c a s e — R = 10 kQ., R =l 5 V — a s follows: B
1. A t v, = V
0L
= y
C £ s a t
= 0.2 V, v = V 0
= V
0H
k Q , p = 50, and V
c
cc
=
= 5 V.
cc
C £ s a t
C £ s a t
Q
THE BASIC BJT DIGITAL LOGIC INVERTER
2. A t vj = V , t h e transistor begins to turn on; thus, !L
V
c
s 0.7 V
lL
cc
T h e c h o i c e of cutoff and saturation as t h e t w o m o d e s of operation of t h e B J T in this inverter circuit is m o t i v a t e d b y t h e following t w o factors:
3. F o r V < Vj < V , t h e transistor is in t h e active region. It operates as an amplifier w h o s e small-signal gain is IL
m
1. T h e p o w e r dissipation in the circuit is relatively l o w in both cutoff and saturation: In cutoff all currents are zero (except for very small l e a k a g e currents), and in saturation the voltage across the transistor is very small (V Esat)C
Vi
r
R
+ w
B
T h e gain d e p e n d s o n the value of r„, w h i c h in turn is d e t e r m i n e d b y t h e collector current a n d h e n c e b y t h e value of v,. As t h e current through the transistor increases, r decreases and w e can neglect ^ r e l a t i v e to R , thus simplifying the gain expression to
x
2. T h e output v o l t a g e levels (V and V ) are well defined. In contrast, if t h e transistor is operated in t h e active region, v = V - iR = V - f3i R , w h i c h is highly d e p e n d e n t on the rather ill-controlled transistor p a r a m e t e r ¡5. cc
C £ s a t
a
cc
c
c
cc
B
B
c
A
v
= - 5 0 x - 1 = - 5 V/V 10
-p^
B
R
B
5.10.1 The Voltage Transfer Characteristic
4. A t Vj = V , the transistor enters t h e saturation region. T h u s V results in the transistor b e i n g at t h e e d g e of saturation, IH
A s m e n t i o n e d in Section 1.7, the m o s t useful characterization of an inverter circuit is in t e r m s of its v o l t a g e transfer characteristic, v versus v,. A sketch of the voltage transfer characteristic ( V T C ) of the inverter circuit-of Fig. 5.74 is presented in Fig. 5.75. T h e transfer characteristic is approximated by three straight-line segments corresponding to t h e operation of t h e B J T in t h e cutoff, active, a n d saturation r e g i o n s , as i n d i c a t e d . T h e actual transfer characteristic will obviously b e a s m o o t h c u r v e b u t will closely follow the straight-line asymptotes indicated. W e shall n o w c o m p u t e the coordinates of the breakpoints of the transfer
IH
is t h e value of v that r
0
I B
p
F o r t h e values w e are using, w e obtain I = 0.096 m A , w h i c h can b e u s e d to find B
V
= I R +V
!H
5. F o r V[ = V and
0H
B
B
0
V
V
( CC~ ( V
IH
= 1.66 V
BE
= 5 V, the transistor will b e deep into saturation with v
o _ /^forced
V,
= M
C £ s a t
= 0.2 V ,
/R
CE ax) C S
H - V
0
= V
B
) / R
E
B
N
=
0.43 6. T h e noise m a r g i n s can n o w be c o m p u t e d u s i n g the formulas from Section 1.7, NM
=
V
NM
=
V
H
L
I L
0
H
- V
- V
I
H
0 L
=
5-
1.66
=
3.34
V
= 0.7 - 0.2 = 0.5 V
O b v i o u s l y , t h e t w o noise m a r g i n s are vastly different, m a k i n g this inverter circuit less t h a n ideal. 7. T h e gain in the transition region can b e c o m p u t e d from the coordinates of the breakpoints X and Y, V o l t a g e gain = 6
5
0
2
~ = -5 1.66-0.7
V/V
w h i c h is e q u a l to the a p p r o x i m a t e value found a b o v e (the fact t h a t it is exactly the s a m e value is a coincidence).
5.10.2 Saturated Versus Nonsaturated BJT Digital Circuits FIGURE 5 . 7 5 Sketch of the voltage transfer characteristic of the inverter circuit of Fig. 5.74 for the case R = 10 kQ, R = IkQ, p= 50, and V = 5 V. For the calculation of the coordinates of X and Y, refer to the text. B
c
cc
T h e inverter circuit j u s t discussed b e l o n g s to the saturated variety of B J T digital circuits. A historically significant family of saturated B J T logic circuits is transistor-transistor logic
"
505
506
CHAPTER 5
N
P
5.11
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
T H E SPICE BJT M O D E L A N D S I M U L A T I O N EXAMPLES
i_ V
A
For N = 5, calculate V using the component values of the example circuit discussed earlier (i.e., R„ 10 k Q , R = 1 k Q , V = 5 V). Note that this arrangement is historically important, as a precursor the T T L logic form. It is called Resistor-Transistor Logic or RTL. 0H
C
cc
Vcc.
•o RB
F I G U R E 5 . 7 6 The minority-carrier charge stored in the base of a saturated transistor can be divided into two components: That in blue produces the gradient that gives rise to the diffusion current across the base, and that in gray results from driving the transistor deeper into saturation.
^, x
W
(TTL). A l t h o u g h s o m e versions of T T L remains in use, saturated bipolar digital circuits generally are n o longer t h e technology of choice in digital s y s t e m design. T h i s is b e c a u s e their speed of operation is severely limited by the relatively long t i m e delay required to turn off a saturated transistor, as w e will n o w explain, briefly. In our study of B J T saturation in Section 5.1.5, w e m a d e u s e of the minority-carrier dis tribution in t h e b a s e region (see Fig. 5.10). Such a distribution is s h o w n in F i g . 5.76, w h e r e the minority carrier charge stored in the base has b e e n divided into t w o c o m p o n e n t s : T h e c o m p o n e n t r e p r e s e n t e d by the blue triangle produces t h e gradient that gives rise to t h e diffu sion current across the b a s e ; the other c o m p o n e n t , represented b y t h e gray rectangle, c a u s e s the transistor to b e driven deeper into saturation. T h e deeper the transistor is driven into sat uration (i.e., t h e greater is the base overdrive factor), the greater the a m o u n t of the " g r a y " c o m p o n e n t of the stored charge will be. It is this "extra" stored b a s e c h a r g e that represents a serious p r o b l e m w h e n it c o m e s to turning off the transistor: Before the collector current can b e g i n to decrease, all of the extra stored charge m u s t first b e r e m o v e d . This a d d s a relatively large c o m p o n e n t to the turn-off time of a saturated transistor. F r o m the above w e conclude that to achieve high operating speeds, the B J T should not b e allowed to saturate. This is the case in c u r r e n t - m o d e logic in general and for the particular form called emitter-coupled logic (ECL), which will b e studied briefly in Chapter 1 1 . There, w e will s h o w w h y E C L is currently the highest-speed logic-circuit family available. It is b a s e d o n t h e current-switching a r r a n g e m e n t that w a s discussed conceptually in Section 1.7 (Fig. 1.33).
N VW
1
V
BE
= 0.7 V FIGURE E5.53
Ans. 3.Ô \
• 1 5.11 THE SPICE BJT MODEL AND SIMULATION I EXAMPLES A s w e did in C h a p t e r 4 for t h e M O S F E T , w e c o n c l u d e this chapter w i t h a discussion of t h e m o d e l s that S P I C E u s e s to simulate the B J T . W e will also illustrate t h e u s e of S P I C E in c o m p u t i n g t h e d e p e n d e n c e of B on the bias current and in simulating a C E amplifier.
5.11.1 The SPICE Ebers-Moll Model of the BJT In Section 5.1.4, w e studied t h e E b e r s - M o l l m o d e l of t h e B J T and s h o w e d a form of this model, k n o w n as the injection form, in Fig. 5.8. S P I C E uses an equivalent form of the EbersM o l l m o d e l , k n o w n as t h e transport form, w h i c h is s h o w n in Fig. 5.77. H e r e , the currents of
C
5.53 Consider the inverter of Fig. 5.74 when v is low. Let the output be connected to the input terminals otN identical/inverters. Convince yourself thai the output level V can be determined using the equivalent circuit shown in Fig. E5.53. Henee show that t
0H
OH
R.
:
+ R
B
/ \
F I G U R E 5 . 7 7 The transport form of the Ebers-Moll model for an npn BJT.
SOI
•
CHAPTER 5
5.11
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
the b a s e - e m i t t e r d i o d e (D ) BE
a n d the b a s e - c o l l e c t o r d i o d e (D ) BC
>BE ~ i ( e
B
E
T
THE SPICE BJT M O D E L A N D SIMULATION EXAMPLES
c
are given, respectively, by
-l)
(5.186)
-1)
(5.187)
PF
and V
hf
•BC -
/n
V
BC R T
7T(
e
PR
w h e r e % a n d n a r e t h e e m i s s i o n c o e f f i c i e n t s of t h e B E J a n d B C J , r e s p e c t i v e l y . T h e s e c o e f f i c i e n t s a r e g e n e r a l i z a t i o n s of t h e c o n s t a n t n of t h e / w - j u n c t i o n d i o d e . ( W e h a v e so far a s s u m e d n = n -1). T h e c o n t r o l l e d c u r r e n t - s o u r c e i i n t h e t r a n s p o r t m o d e l is defined as R
p
R
CE
,
T
v
/n
V
BE F T
v /n V BC
ICE = h(e
R
-e
/CMNX
T
)
(5.188)
O b s e r v e that i represents t h e current c o m p o n e n t of i a n d i that arises as a result of the minority-carrier diffusion across the b a s e , or c a r r i e r t r a n s p o r t across t h e b a s e (hence the n a m e transport m o d e l ) . T h e reader c a n easily s h o w that, for n = n = 1, the relations CE
c
E
E
F
FIGURE 5 . 7 8 The SPICE large-signal Ebers-Moll model for an npn BJT.
R
(5.189)
l R — IftF BE + IBC L
model includes a large resistance b e t w e e n t h e b a s e a n d c o l l e c t o r (in parallel w i t h C ) to a c c o u n t for t h e d e p e n d e n c e of i on v . T h i s d e p e n d e n c e c a n b e n o t e d from t h e C B c h a r acteristics of t h e B J T in F i g . 5.19(b), w h e r e i is o b s e r v e d to i n c r e a s e w i t h v : S i n c e e a c h i -v c u r v e i n F i g . 5.19(b) is m e a s u r e d at a c o n s t a n t i , a n i n c r e a s e in i w i t h v implies a c o r r e s p o n d i n g d e c r e a s e in i w i t h v . T h e r e s i s t a n c e r is v e r y large, t y p i c a l l y g r e a t e r t h a n 10j8r . A l t h o u g h F i g . 5.77 s h o w s t h e S P I C E m o d e l for t h e npn B J T , t h e c o r r e s p o n d i n g m o d e l for t h e pnp B J T c a n b e o b t a i n e d b y reversing t h e direction of the currents a n d t h e polarity of the diodes a n d t e r m i n a l v o l t a g e s . p
B
L
C
L
-
(5.190)
L
CE ~ BC
c
c
L
E
L
(5.191)
L
— CE + BE
CB
CB
CB
E
B
CB
c
CB
M
o
for t h e B J T currents i n the transport m o d e l result in expressions identical to those derived in E q s . (5.23), (5.26), a n d (5.27), respectively. T h u s , t h e transport form (Fig. 5.77) of the E b e r s - M o l l m o d e l is exactly equivalent to its injection form (Fig. 5.8). M o r e o v e r , it h a s the a d v a n t a g e of b e i n g simpler, requiring only a single controlled source from collector to emit ter. H e n c e , it is preferred for c o m p u t e r simulation. T h e t r a n s p o r t m o d e l c a n a c c o u n t for t h e E a r l y effect ( s t u d i e d i n S e c t i o n 5.2.3) i n a f o r w a r d - b i a s e d B J T b y including the factor ( 1 - v /V ) i n the expression for t h e transport current i as follows: BC
A
CE
5.11.2 The SPICE Gummel-Poon Model of the BJT T h e large-signal E b e r s - M o l l B J T m o d e l described in Section 5.11.1 lacks a representation of s o m e s e c o n d - o r d e r effects present i n actual devices. O n e of t h e m o s t important such effect is the variation of the current gains, /3 a n d f3 , w i t h t h e current i . T h e E b e r s - M o l l m o d e l a s s u m e s f3 a n d j3 to b e constant, thereby n e g l e c t i n g their current d e p e n d e n c e (as depicted in F i g . 5.23). T o a c c o u n t for this, a n d other second-order effects, S P I C E u s e s a m o r e accurate, y e t m o r e c o m p l e x , B J T m o d e l called t h e G u m m e l - P o o n m o d e l ( n a m e d after G u m m e l a n d P o o n , t w o p i o n e e r s in this field). T h i s m o d e l is b a s e d o n t h e relationship b e t w e e n the electrical t e r m i n a l characteristics of a B J T a n d its b a s e charge. It is b e y o n d t h e scope of this b o o k to d e l v e into the m o d e l details. H o w e v e r , it is i m p o r t a n t for the reader to b e a w a r e of t h e existence of such a m o d e l . F
i
C E
= h ( e
V
M
- e
v
M
) ( l
- ^ )
(5.192)
F ig u r e 5.78 s h o w s t h e large-signal E b e r s - M o l l B J T m o d e l u s e d in S P I C E . It is b a s e d o n the transport form of the E b e r s - M o l l m o d e l s h o w n in F i g . 5.77. H e r e , resistors r„ r , a n d r are a d d e d to r e p r e s e n t the o h m i c resistance of, respectively, t h e b a s e , emitter, a n d collector r e g i o n s . T h e d y n a m i c operation o f t h e B J T is m o d e l e d b y t w o nonlinear capacitors, C and C . E a c h of t h e s e capacitors generally i n c l u d e s a diffusion c o m p o n e n t (i.e., C and C ) and a depletion or j u n c t i o n c o m p o n e n t (i.e., C a n d C ) to a c c o u n t for the charge-storage effects within t h e B J T (as described in Section 5.8). F u r t h e r m o r e , t h e B J T m o d e l includes a depletion junction capacitance C to account for the collector-substrate junction in integratedcircuit B J T s , w h e r e a reverse-biased / m - j u n c t i o n is f o r m e d b e t w e e n t h e collector a n d t h e substrate ( w h i c h is c o m m o n to all c o m p o n e n t s of the I C ) . E
c
BC
BE
DC
JC
F o r s m a l l - s i g n a l (ac) a n a l y s i s , t h e S P I C E B J T m o d e l is e q u i v a l e n t to t h e hybrid-7T m o d e l of F i g . 5 . 6 7 , b u t a u g m e n t e d w i t h r , r , a n d (for I C B J T s ) C . F u r t h e r m o r e , t h e c
JS
R
c
R
DE
JE
JS
E
F
In S P I C E , t h e G u m m e l - P o o n m o d e l automatically simplifies to the E b e r s - M o l l m o d e l w h e n certain m o d e l p a r a m e t e r s are n o t specified. C o n s e q u e n t l y , t h e B J T m o d e l to b e u s e d b y S P I C E n e e d n o t b e explicitly specified b y t h e user (unlike the M O S F E T c a s e in w h i c h the m o d e l is specified b y the L E V E L p a r a m e t e r ) . F o r discrete B J T s , t h e values of the S P I C E m o d e l p a r a m e t e r s c a n b e d e t e r m i n e d from t h e d a t a specified o n t h e B J T data sheets, supple m e n t e d (if n e e d e d ) b y k e y m e a s u r e m e n t s . F o r instance, in E x a m p l e 5.20 (Section 5.11.4), w e will u s e t h e Q 2 N 3 9 0 4 npn B J T (from Fairchild S e m i c o n d u c t o r ) w h o s e S P I C E m o d e l is
509
51 O
f
I
CHAPTER 5
BIPOLAR J U N C T I O N T R A N S I S T O R S (BJTS)
5.11
available in P S p i c e . In fact, the P S p i c e library already includes the S P I C E m o d e l p a r a m e t e r s for m a n y of the c o m m e r c i a l l y available discrete B J T s . F o r I C B J T s , t h e values of t h e S P I C E m o d e l parameters are d e t e r m i n e d b y t h e I C manufacturer (using b o t h m e a s u r e m e n t s o n the fabricated devices and k n o w l e d g e of the details of the fabrication process) and are p r o v i d e d to the I C designers.
T H E SPICE BJT M O D E L A N D SIMULATION EXAMPLES
constant c u r r e n t - i n d e p e n d e n t p a r a m e t e r s B (B ) and B u s e d in the E b e r s - M o l l m o d e l (and throughout this chapter) for the forward and r e v e r s e dc current gains of t h e B J T . S P I C E u s e s a c u r r e n t - d e p e n d e n t m o d e l for B and j3 , and the user can specify other p a r a m e t e r s (not s h o w n in T a b l e 5.8) for this m o d e l . O n l y w h e n such p a r a m e t e r s are n o t specified, and the Early effect is neglected, will S P I C E a s s u m e that B and j 8 a r e constant and equal to B F a n d B R , respectively. F u r t h e r m o r e , S P I C E c o m p u t e s values for b o t h B and B , the t w o parameters that w e generally a s s u m e to b e a p p r o x i m a t e l y equal. S P I C E then uses / ? to p e r f o r m small-signal (ac) analysis. F
F
ic
R
R
F
s
dc
5.11.3 The SPICE BJT Model Parameters
511
K
ac
T a b l e 5.8 p r o v i d e s a listing of s o m e of t h e B I T m o d e l p a r a m e t e r s u s e d in S P I C E . T h e reader should b e already familiar w i t h these p a r a m e t e r s . In the a b s e n c e of a user-specified value for a p a r t i c u l a r p a r a m e t e r , S P I C E u s e s a default v a l u e t h a t t y p i c a l l y r e s u l t s in t h e c o r r e s p o n d i n g effect b e i n g i g n o r e d . F o r e x a m p l e , if n o v a l u e is specified for t h e f o r w a r d Early v o l t a g e V A F , S P I C E a s s u m e s that V A F = °° a n d d o e s n o t a c c o u n t for t h e E a r l y effect. A l t h o u g h ignoring the forward E a r l y v o l t a g e V A F can b e a serious issue in s o m e circuits, the same is not true, for e x a m p l e , for t h e v a l u e of the reverse E a r l y voltage V A R .
3MS
DEPENDENCE
O F ¡3 O N T H E
BIAS
CURRENT
In this example, we use PSpice to simulate the dependence of B on the collector bias current for the Q2N3904 discrete B J T (from Fairchild Semiconductor) whose model parameters are listed in Table 5.9 and are available in P S p i c e . As shown in the Capture s c h e m a t i c of Fig. 5.79, the V of the BJT is fixed using a constant voltage source (in this example, V = 2 V) and a dc current source I is applied at the base. To illustrate the dependence of B on the collector current I , we perform a dc-analysis simulation in which the sweep variable is the current source I . The B of the BJT, which corresponds to the ratio of the collector current I to the base current I , can then b e plotted versus I using Probe (the graphical interface of PSpice), as shown in Fig. 5.80. W e see that to operate at the m a x i m u m value of B (i.e., B = 163), at V = 2 V, the BJT must be biased at an I = 10 m A . Since increasing the bias current of a transistor increases the power dissipation, it is clear from Fig. 5.80 that the choice of current I is a trade-off between the current gain B and the power dissipation. Generally speaking, the optimum I depends on the application and technology in hand. For example, for the Q2N3904 B J T operating at V = 2 V, decreasing I by a factor of 20 (from 10 m A to 0.5 m A ) results in a drop in B of about 2 5 % (from 163 to 123). Ac
5.11.4 The BJT Model Parameters BFand BR in SPICE
12
Before leaving the S P I C E model, a c o m m e n t on ¡3 is in order. S P I C E interprets the userspecified model parameters B F and B R as the ideal maximum values of the forward and reverse dc current gains, repectively, versus the operating current. These parameters are not equal to the
13
CE
CE
dc
B
c
dc
B
c
TABLE 5.8
Parameters of the SPICE BJT Model (Partial Listing!
dc
SPICE Parameter
IS BF BR NF NR VAF VAR RB RC RE T F
TR CJC MJC VJC CJE MJE VJE CJS MJS VJS
Book Symbol
F
R
r* r c
r
E
?F ?R Cfio
v
0c
CjeO m
BES
CE
Description
Units
Saturation current Ideal maximum forward current gain Ideal maximum reverse current gain Forward current emission coefficient Reverse current emission coefficient Forward Early voltage Reverse Early voltage Zero-bias base ohmic resistance Collector ohmic resistance Emitter ohmic resistance Ideal forward transit time Ideal reverse transit time Zero-bias base-collector depletion (junction) capacitance Base-collector grading coefficient Base-collector built-in potential Zero-bias base-emitter depletion (junction) capacitance Base-emitter grading coefficient Base-emitter built-in potential Zero-bias collector-substrate depletion (junction) capacitance Collector-substrate grading coefficient Collector-substrate built-in potential
A
c
n n
A
ic
c
h
v
B
c
'
ic
c
CE
ic
c
V V n Q, Q s s F
TA&LE 5.9 IS=6.734f IKF=66.78m CJC=3.638p TR=239.5n
SPICE Model Parameters of the Q2N3904 Discrete BJT XTI =3 XTB=1.5 MJC=.3085 TF=301.2p
EG=1.11 BR=.7371 VJC=.75 ITF=.4
VAF=74.03 NC=2 FC=.5 VTF=4
BF=416.4 ISC=0 CJE=4.493p XTF=2
NE=1.259 IKR=0 MJE=.2593 RB=10
V F
V F
V
The Q2N3904 model is included in the evaluation (EVAL) library of PSpice (OrCad 9.2 Lite Edition) which is available on the CD accompanying this book. The reader is reminded that the Capture schematics and the corresponding PSpice simulation files of all SPICE examples in this book can be found on the text's CD as well as on its website (www.sedrasmith.org). In these schematics (as shown in Fig. 5.79), we use variable parameters to enter the values of the various circuit components. This allows one to investigate the effect of changing component values by simply changing the corresponding parameter values.
ISE=6.734f RC=1 VJE=.75
512
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
5.11
(BJTs)
PARAMETERS: IB = lOu VCE = 2V
T H E SPICE BJT M O D E L A N D S I M U L A T I O N
RAMETERS:
DC = {VCE} {IB}
RC RB RE ice RL :sig
© '0
vcc
CE = lOu X I = lOu CO = lOu
Q2N3904
'0
FIGURE 5 . 7 9 The PSpice testbench used to demonstrate the dependence of j5 on the collector bias cur rent/,, for the Q2N3904 discrete BJT (Example 5.20).
= = = = = =
{RC}. {CCO}
10K 340K 6K 130 10K 10K
OUT IN VCC
VEE
A
A
cc = 5 EE = - 5
ic
{CCI}
{Rsig}
lVac ( ~ ) AC Source OVdc
DC = {VCC}
{
R
B
}
IRE}
=
2V VEE
I = 10mA, ß c
I
c
= 0.5mA, ß
dc
dc
= 162.41
iURE 5 . 8 1
Capture schematic of the CE amplifier in Example 5.21.
= 122.9 I uF. To enable us to investigate the effect of including a resistance in the signal path of the Iter, a resistor R is connected in series with the emitter bypass capacitor C . Note that the :s of R and R are different. Resistor R is the dc emitter degeneration resistor because it ears in the dc path between the emitter and ground. It is therefore used to help stabilize the 5 point for the amplifier. The equivalent resistance R = R \ \ R is the small-signal emitter ;eneration resistance because it appears in the ac (small-signal) path between the emitter and und and helps stabilize the gain of the amplifier. In this example, we will investigate the sets of both R and R on the performance of the C E amplifier. However, as should always be case with computer simulation, w e will begin with an approximate pencil-and-paper design, his way, m a x i m u m advantage and insight can be obtained from simulation. Based on the plot of / 3 versus I in Fig. 5.80, a collector bias current I of 0.5 m A is selected the BJT, resulting in j8 = 1 2 3 . This choice of I is a reasonable compromise between power dissipation and current gain. Furthermore, a collector bias voltage V of 0 V (i.e., at the m i d supply rail) is selected to achieve a high signal swing at the amplifier output. For V = 2 V, the result is that V = - 2 V requires bias resistors with values c e
E
E
c e
E
e
50
E
25
10mA
15mA
20mA
25mA
30mA
E
c e
e
dc
0. OA 5mA v IC ( Q D / I B (Ql)
c
c
dc
c
c
IC (Ql)
CE
E
FIGURE 5 . 8 0 Dependence of /3 on I (at V = 2 V) in the Q2N3904 discrete BJT (Example 5.20). dc
c
CE
•V
r
= 10 k Q
Rr
and
v -v E
THE CE AMPLIFIER WITH EMITTER
A %
= 6 kQ
EE
RESISTANCE
In this example, we use PSpice to compute the frequency response of the C E amplifier and inves tigate its bias-point stability. A capture schematic of the C E amplifier is shown in Fig. 5.81. W e will use part Q2N3904 for the BJT and a ±5-V power supply. W e will also assume a signalsource resistor R = 10 k Q , a load resistor R = 10 k Q , and bypass and coupling capacitors of L
Assuming V
BE
_L {CE}
T
{Ree}
DC = { V E E }
175 VCF
5 1 3
EXAMPLES
= 0.7 V and using / 3 = 123, we can determine dc
y +v BE
Ic'ßä,
E
320 k Q
'0
514
;_
1
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS) 5.11
Next, the formulas of Section 5.7.4 can be used to determine the input resistance R
T H E SPICE BJT M O D E L A N D SIMULATION
EXAMPLES
and the mid-
in
band voltage gain \A \ of the CE amplifier: M
R
in
= R \\(B, +l)(r B
c
+ R)
e
(5.193)
e
(5.194) -^sig + ^ i n
For simplicity, we will assume B
nc
>"e
+
R
e
~ B . = 123, resulting in i(
Ac
Y
V
T
, = 49.6 Q
AC+IA/ ; C
Thus, with no small-signal emitter degeneration (i.e., R„ = 0), R
in
38.2 V / V . Using Eq. (5.194) and assuming R
= 6.1 k Q and \A \ M
is large enough to have a negligible effect on
B
= R, in
it can b e shown that the emitter degeneration resistor R decreases the voltage gain \A \ by a e
M
factor of R
R
T
V
1+^ii
Therefore, to limit the reduction in voltage gain to a factor of 2, w e will select * . - r . * j f c Thus, R "R ce
(5.1*3)
= 130 Q . Substituting this value in Eqs. (5.193) and (5.194) shows that
e
R
m
increases from 6.1 k Q to 20.9 k Q while \A \ drops from 38.2 V/V to 18.8 V/V. M
W e will now use PSpice to verify our design and investigate the performance of the CE
FIGURE 5 . 8 2 Frequency response of the CE amplifier in Example 5.21 with R
ce
= 0 and R
= 130 Q .
ce
amplifier. W e begin by performing a bias-point simulation to verify that the BJT is properly biased in the active region and that the dc voltages and currents are within the desired specifica tions. Based on this simulation, we have increased the value of R to 340 k Q in order to limit I B
c
forward current gain) in the SPICE model for part Q 2 N 3 9 0 4 by a factor of 2 and perform a bias-
to about 0.5 m A while using a standard 1% resistor value (Appendix G ) . Next, to measure the
point simulation. T h e corresponding change in B J T parameters (B
midband gain A
(including l and V ) are presented in Table 5.10 for the case of R
M
and the 3-dB f r e q u e n c i e s / a n d / , w e apply a 1-V ac voltage at the input, per L
ff
ic
c
CE
E
and B ) and bias-point ac
= 6 k Q . Note that / 3 is not ac
form an ac-analysis simulation, and plot the output voltage magnitude (in dB) versus frequency as shown in Fig. 5.82. This corresponds to the magnitude response of the C E amplifier because we chose a 1-V input s i g n a l .
14
Accordingly, with no emitter degeneration, the midband gain is
\A \ = 38.5 V/V = 31.7 dB and the 3-dB bandwidth is BW=f -f = M
R
ce
H
L
TABLE 5.10
Variations in the Bias Point of the CE Amplifier with the SPICE Model-Parameter BF of BJT
145.7 kHz. Using an
fl =6kQ
R =0
f
= 130 Q results in a drop in the midband gain 1A I by a factor of 2 (i.e., 6 dB). Interestingly,
E
M
however, S W h a s n o w increased by approximately the same factor as the drop in IA I. As w e will
BF (in SPICE)
learn in Chapter 8 w h e n w e study negative feedback, the emitter-degeneration resistor R
208 416.4 (nominal value) 832
M
ce
pro
vides negative feedback, which allows us to trade off gain for other desirable properties such as a larger input resistance, and a wider bandwidth.
106 143 173
Ac
l (mA)
94.9 123 144
0.452 0.494 0.518
Ac
c
0.484 0.062 -0.183
Ac
109 148 181
96.9 127 151
k (mA)
l/c(V)
0.377 0.494 0.588
1.227 0.060 -0.878
To conclude this example, we will demonstrate the improved bias-point (or dc operatingpoint) stability achieved when an emitter resistor R is used (see the discussion in Section 5.5.1). E
equal to B
ic
Specifically, we will increase/decrease the value of the parameter B F (i.e., the ideal m a x i m u m
will use R
E
as we assumed, but is slightly larger. For the case without emitter degeneration, we = 0 in the schematic of Fig. 5.81. Furthermore, to maintain the same I
c
both cases at the values obtained for nominal B F , w e use R =1A2 B
1 4
The reader should not be alarmed about the use of such a large signal amplitude. Recall (Section 2.9.1) that, in a small-signal (ac) simulation, SPICE first finds the small-signal equivalent circuit at the dc bias point, and then analyzes this linear circuit. Such ac analysis can, of course, be done with any ac signal amplitude. However, a 1-V ac input is convenient to use as the resulting ac output cor responds to the voltage gain of the circuit.
and V
c
in
M Q to limit 7 to approxi C
mately 0.5 m A . The corresponding variations in the B J T bias point are also shown in Table 5.10. Accordingly, w e see that emitter degeneration makes the bias point of the C E amplifier much less sensitive to changes in B. However, unless a large bypass capacitor C is used, this reduced bias E
sensitivity comes at the expense of a reduction in the midband gain (as w e observed in this exam ple when w e simulated the frequency response of the C E amplifier with an R = 130 Q ) . e
PROBLEMS j
516
CHAPTERS
BIPOLAR JUNCTION TRANSISTORS
multiplication of C by (1 + g R' ), known as the Miller effect, is the most significant factor limiting the highfrequency response of the CE amplifier. p
SUMMARY B
Depending on the bias conditions on its two junctions, the BJT can operate in one of four possible modes: cutoff (both junctions reverse biased), active (the EBJ forward biased and the CBJ reverse biased), saturation (both junctions forward biased), and reverse-active (the EBJ reverse biased and the CBJ forward biased).
S
To operate as a linear amplifier, the BJT is biased in the active region and the signal v is kept small (v
B
i
517
(BJTS)
be
B
S
L
The basic BJT logic inverter utilizes the cutoff and saturation modes of transistor operation. A saturated transistor has a large amount of minority-carrier charge stored in its base region and is thus slow to turn off.
For the analysis of the effect of C , C , and C on the low-frequency gain of the CE amplifier, refer to Section 5.9.3 and in particular to Fig. 5.73. c l
T
For small signals, the BJT functions as a linear voltagecontrolled current source with a transconductance g = (I /V ). The input resistance between base and emitter, looking into the base, is r„ = P/g . Simplified lowfrequency equivalent-circuit models for the BJT are shown in Figs. 5.51 and 5.52. These models can be augmented by including the output resistance r = | V \ / l between the collector and the emitter. Table 5.4 provides a summary of the equations for determining the model parameters.
m
C 2
E
m
C
T
m
•
B
For amplifier applications, the BJT is operated in the active mode. Switching applications make use of the cutoff and saturation modes. The reverse-active mode of operation is of conceptual interest only. A BJT operating in the active mode provides a collector current i = I e\ \ . The base current i = (i /B), and the emitter current i = i + i . Also, i = ai , and thus P = a/(\-a) and a = p/(P + 1). See Table 5.2. VBE IVT
c
s
B
E
B
B
c
B
c
A convenient and intuitively appealing model for the large-signal operation of the BJT is the Ebers-Moll model shown in Fig. 5.8. A fundamental relationship between its parameters is a I = a I = I . While a is close to unity, a is very small (0.01-0.2), and p is correspondingly small. Use of the EM model enables expressing the terminal currents in terms of the voltages v and v . The resulting relationships are given in Eqs. (5.26) to (5.30). SE
R
sc
s
R
BE
Bias design seeks to establish a dc collector current that is as independent of the value of P as possible.
fl
In the common-emitter configuration, the emitter is at signal ground, the input signal is applied to the base, and the output is taken at the collector. A high voltage gain and a reasonably high input resistance are obtained, but the high-frequency response is limited.
S
C£sat
c
B
BC
In a saturated transistor, | V j = 0.2 V and I = (V V )/R . The ratio of 7 to the base current is the forced P, which is lower than B- The collector-to-emitter resistance, i ? , is small (few tens of ohms). CEsA
Csnl
fl
At a constant collector current, the magnitude of the b a s e emitter voltage decreases by about 2 mV for every 1°C rise in temperature. B
H
The input resistance of the common-emitter amplifier can be increased by including an unbypassed resistance in the emitter lead. This emitter-degeneration resistance provides other performance improvements at the expense of reduced voltage gain. In the common-base configuration, the base is at signal ground, the input signal is applied to the emitter, and the output is taken at the collector. A high voltage gain (from emitter to collector) and an excellent high-frequency response are obtained, but the input resistance is very low. The CB amplifier is useful as a current buffer.
Csat
C£sat
B
c
F
R
cc
A
fl
E
To ensure operation in the active mode, the collector voltage of an npn transistor must be kept higher than approximately 0.4 V below the base voltage. For apnp transistor the collector voltage must be lower than approximately 0.4 V above the base voltage. Otherwise, the CBJ becomes forward biased, and the transistor enters the saturation region.
F
B
c
0
With the emitter open-circuited (i = 0), the CBJ breaks down at a reverse voltage BV that is typically >50 V. For i > 0, the breakdown voltage is less than BV . In the common-emitter configuration the breakdown voltage specified is BV which is about half BV . The emitterbase junction breaks down at a reverse bias of 6 V to 8 V. This breakdown usually has a permanent adverse effect on p. E
In the emitter follower the collector is at signal ground, the input signal is applied to the base, and the output taken at the emitter. Although the voltage gain is less than unity, the input resistance is very high and the output resistance is very low. The circuit is useful as a voltage buffer. Table 5.5 shows the parameters utilized to characterize amplifiers.
P R O B L E M S SECTION 5 . 1 : DEVICE STRUCTURE AND PHYSICAL OPERATION
5 . 5 Find the values of P that correspond to a values of 0.5, 0.8, 0.9, 0.95, 0.99, 0.995, and 0.999.
5.1 The terminal voltages of various npn transistors are measured during operation in their respective circuits with the following results:
5 . 6 Find the values of a that correspond to P values of 1, 2, 10, 20, 100, 200, 1000, and 2000.
0 0 -0.7 -0.7 0.7 -2.7 0 -0.10
1 2 3 4 5 6 7 8
B
C
0.7 0.8 0 0 0.7 -2.0 0 5.0
0.7 0.1 0.7 -0.6 0 0 5.0 5.0
Mode
s
Transistor
V (mV) I (mA) BE
c
CB0
CBCh
fl
CB0
A summary of the current-voltage characteristics and large-signal models of the BJTs in both the active and saturation modes of operation is presented in Table 5.3.
B
For a summary of the characteristics of discrete singlestage BJT amplifiers, refer to Table 5.6.
5 . 2 An npn transistor has an emitter area of 10 pm x 10 pm. The doping concentrations are as follows: in the emitter N = 10 /cm , in the base N = 1 0 / c m , and in the collector N = 1 0 / c m . The transistor is operating at T = 300 K, where n,- = 1.5 x 1 0 / c m . For electrons diffusing in the base, L„ = 19 pm and D = 21.3 cm /s. For holes diffusing in the emitter, L = 0.6 pm and D = 1.7 cm /s. Calculate I and P assuming that the base-width W is: D
19
3
15
3
17
3
A
10
D
2
n
2
p
p
s
•
Analysis of the high-frequency gain of the CE amplifier in Section 5.9 shows that the gain rolls off at a slope of - 6 dB/octave with the 3-dB frequency f = \/2nC R' . Here R' is a modified value of i? , approximately equal to R \\r„, and C = C + (T + g R' )C^. The H
B
The dc analysis of transistor circuits is greatly simplified by assuming that \ V \ = 0.7 V. BE
sig
lv
sig
sig
i n
K
m
E
Ag
B
C
CI
e
690 1.000 50
690 1.000
580
780 10.10 120
820
7 0.137
1.070
1050 75.00
5 . 8 Consider an npn transistor whose base-emitter drop is 0.76 V at a collector current of 10 mA. What current will it conduct at v = 0.70 V? What is its base-emitter voltage for i =10pA7 BE
c
5 . 9 Show that for a transistor with a close to unity, if a changes by a small per-unit amount (ha/a) the corresponding per-unit change in P is given approximately by A@
(a) 1 pm (b) 2 pm (c) 5 pm
~n(Aa Va
P
For case (b), if I = 1 mA, find I , I , V , and the minoritycarrier charge stored in the base. (Hint: i = L /D . Recall that the electron charge q = 1.6 x 10~ Coulomb.) c
B
E
BE
2
b
The high-frequency model of the BJT together with the formulas for determining its parameter values are shown in Table 5.7.
A
3
n
n
19
•
4(mA) a ß
In this table, where the entries are in volts, 0 indicates the reference terminal to which the black (negative) probe of the voltmeter is connected. For each case, identify the mode of operation of the transistor.
CB0
B
5 . 7 Measurement of V and two terminal currents taken on a number of npn transistors are tabulated below. For each, calculate the missing current value as well as a, P, and I as indicated by the table. BE
E
Case
5 . 3 Two transistors, fabricated with the same technology but having different junction areas, when operated at a base-emitter voltage of 0.72 V, have collector currents of 0.2 mA and 12 mA. Find I for each device. What are the relative junction areas? s
P
5 . 1 0 An npn transistor of a type whose P is specified to range from 60 to 300 is connected in a circuit with emitter grounded, collector at +9 V, and a current of 50 pA injected into the base. Calculate the range of collector and emitter currents that can result. What is the maximum power dissipated in the transistor? (Note: Perhaps you can see why this is a bad way to establish the operating current in the collector of a BJT.) 5 . 1 1 A particular BJT when conducting a collector current of 10 mA is known to have v = 0.70 V and i = 100 pA. Use these data to create specific transistor models of the form shown in Figs. 5.5(a) and (b). BE
5 . 4 In a particular BJT, the base current is 7.5 pA, and the collector current is 400 pA. Find P and a for this device.
B
518
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
(BJTs) PROBLEMS
5 . 1 2 Using the npn transistor model of Fig. 5.5(b), consider the case of a transistor for which the base is connected to ground, the collector is connected to a 10-V dc source through a 2-kQ resistor, and a 3-mA current source is connected to the emitter with the polarity so that current is drawn out of the emitter terminal. If B = 100 and I = 1 0 " A, find the voltages at the emitter and the collector and calculate the base current.
emitter is connected to ground, the base is connected to a current source that pulls 20 pA out of the base terminal, and the collector is connected to a negative supply o f - 1 0 V via a 10-kQ resistor, find the collector voltage, the emitter current, and the base voltage.
; 1 9
+ 10 V
15
s
5 . 1 7 A pnp transistor has v 1 A. What do you expect v i = 5A?
EB
EB
5 . 1 3 Consider an npn transistor for which B = 100, a = 0.1, a n d / = 1 0 A. F
s
= 0.8 V at a collector current of to become at i = 10 mA? At c
+ 4.3 V o -
c
+6.3 V o
-4.3 V
100 k Q
- 1 5
5
(a) If the transistor is operated in the forward active mode with I = 10 pA and V = 1 V, find V , I , and I . (b) Now, operate the transistor in the reverse active mode with a forward-bias voltage V equal to the value of V found in (a) and with V = 1 V. Find I , I , and I . B
CB
BE
c
E
c
B
E
BC
BE
EB
5 . 1 4 A transistor characterized by the Ebers-Moll model shown in Fig. 5.8 is operated with both emitter and collector grounded and a base current of 1 mA. If the collector junction is 10 times larger than the emitter junction and a = 1, find i and i . F
c
5 . 1 8 A pnp transistor modeled with the circuit in Fig. 5.12 is connected with its base at ground, collector at - 1 . 5 V, and a 10-mA current injected into its emitter. If it is said to have B = 10, what are its base and collector currents? In which direction do they flow? If I = 10~ A, what voltage results at the emitter? What does the collector current become if a transistor with B = 1000 is substituted? (Note: The fact that the collector current changes by less than 10% for a large change of B illustrates that this is a good way to establish a specific collector current.)
c
CB
1
5 . 1 9 A pnp power transistor operates with an emitter-tocollector voltage of 5 V, an emitter current of 10 A, and V = 0.85 V. For ¡3 = 15, what base current is required? What is 7s for this transistor? Compare the emitter-base junction area of this transistor with that of a small-signal transistor that conducts i = 1 mA with v = 0.70 V. How much larger is it?
F
BC
BE
R
CE
c
F
E
c
(a)
13
s
SECTION 5 . 2 :
CURRENT-VOLTAGE
CHARACTERISTICS 5 . 2 0 For the circuits in Fig. P5.20, assume that the transistors have very large B. Some measurements have been made
• 10.7 V
A
"I
10 k n
15 k Q
o +0.7 V
o Vf,
-2.7 V
V
4
o
o
-4V o 0V 10 k Q
10 k n
T
-10.7 V (a) FIGURE P 5 . 2 0
(c)
FIGURE P 5 . 2 1
on these circuits, with the results indicated in the figure. Find the values of the other labeled voltages and currents.
D 5 . 2 3 Redesign the circuit in Example 5.1 to provide V = +3 V and I = 5 mA.
5 . 2 1 Measurements on the circuits of Fig. P5.21 produce labeled voltages as indicated. Find the value of B for each transistor.
5 . 2 4 For each of the circuits shown in Fig. P5.24. find the emitter, base, and collector voltages and currents. Use B = 30, but assume \ V \ = 0.7 V independent of current level.
c
c
BE
D 5 . 2 2 Examination of the table of standard values for resistors with 5% tolerance in Appendix G reveals that the closest values to those found in the design of Example 5.1 are 5.1 kQ. and 6.8 kQ. For these values use approximate calculations (e.g., V — 0.7 V and a - 1) to determine the values of collector current and collector voltage that are likely to result. BE
5 . 1 6 Consider the pnp large-signal model of Fig. 5.12 applied to a transistor having I = 1CT A and B = 40. If the
(b)
EB
c
s
230 a
EB
- 1 5
E
+ 2.3 V
1 kQ
16
c
curves for a transistor for (b) Calculate and sketch i which I = 1 0 A, a —l, and a = 0.1. Sketch graphs for I = 0.1 mA, 0.5 mA, and 1 mA. For each, give the values of v , v , and v for which (a) i = 0.5a I and (b) i = 0.
200 k û
s
E
* 5 . 1 5 (a) Use the Ebers-Moll expressions in Eqs. (5.26) and (5.27) to show that the i -v relationship sketched in Fig. 5.9 can be described by
o +2 V
(c)
5-kiî
5 . 2 5 Repeat Problem 5.24 using transistors for which | V \ = 0.7 V a t 7 = 1 mA. BE
c
5 . 2 6 For the circuit shown in Fig. P5.26, measurement indicates that V = - 1 . 5 V. Assuming V = 0.7 V, calculate V , a, 8, and V . If a transistor with B = °° is used, what values of V , V , and V result? B
E
c
B
F
r
BE
520
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS) ;
PROBLEMS
graphs for I = 0.1 mA, 0.5 mA, and 1 mA. Use an expanded scale for the negative values of v in order to show the details of the saturation region. Neglect the Early effect.
521
E
BC
* 5 , 3 6 For the saturated transistor shown in Fig. P5.36, use the EM expressions to show that for a = 1, F
and v is increased from 8 Y to 10 V, what collector current results? Assume V = 100 V. CE
A
5 . 4 3 For a transistor whose ¡5 characteristic is sketched in Fig. 5.22, estimate values of P at -55°C, 25°C, and 125°C for l = 100 pA and 10 mA. For each current, estimate the temperature coefficient for temperatures above and below room temperature (four values needed). c
( 1 V«C-
CEsat
^CsaA
dp
y in r
110 k O For a BJT with
C£sat
for /
C s a t
./h
= 0.9,
5 . 4 4 Figure P5.44 shows a diode-connected npn transistor. Since v - 0 results in active mode operation, the BJT will internally operate in the active mode; that is, its base and collector cmrents will be related by d . Use the EM equations to show that the diode-connected transistor has the i-v characteristics,
BE
c
(a) Find a , a , and p . (b) For a collector current of 5 mA and nonsaturated operation, what is the base-emitter voltage and the base current? (c) For the situation in (b) but with double the calculated base current, what is the value of forced ¡31 What are the b a s e emitter and base-collector voltages? What are V and -R ? F
R
R
C£sat
I„ v/V v/V i = —(e - l ) = Ie T
+
* 5 . 5 1 A BJT with fixed base current has V = 60 mV with the emitter grounded and the collector open-circuited. When the collector is grounded and the emitter is opencircuited, V becomes - 1 mV. Estimate values for p and p for this transistor. C£sat
C£sat
T
T
s
R
c
CB0
c
©
F
R
R
CB0
FIGURE P 5 . 3 6
+ 50 V 5 . 3 7 Use Eq. (5.36) to plot i versus v for an npn transistor having I = 1 0 ~ A and V = 100 V. Provide curves for v = 0.65, 0.70, 0.72, 0.73, and 0.74 volts. Show the characteristics for v up to 15 V. c
15
s
A
BE
CE
5 . 3 8 For a particular npn transistor operating at a v of 670 mV and I = 3 mA, the i -v characteristic has a slope of 3 x 10 r j . To what value of output resistance does this con'espond? What is the value of the Early voltage for this transistor? For operation at 30 mA, what would the output resistance become? <; BE
c
c
5 . 3 1 A particular pnp transistor operating at an emitter current of 0.5 mA at 20°C has an emitter-base voltage of 692 mV. (a) What does v become if the junction temperature rises to 50°C? (b) If the transistor has n = 1 and is operated at a fixed emitter-base voltage of 700 mV, what emitter current flows at20°C?At50°C?
FIGURE P 5 . 4 4
CE
CE
5
5 . 3 © A BJT whose emitter current is fixed at 1 mA has a base-emitter voltage of 0.69 V at 25°C. What base-emitter voltage would you expect at 0°C? At 100°C?
R
5 . 5 3 A BJT for which BV is 30 V is connected as shown in Fig. P5.53. What voltages would you measure on the collector, base, and emitter?
E
5.2® An npn transistor is accidentally connected with collector and emitter leads interchanged. The resulting currents in the normal emitter and base leads are 0.5 mA and 1 mA, respectively. What are the values of a and p l
c
CEoS
CB0
B
C £ s a t
cfisat
C£sat
CB0
*5.28 Augment the model of the npn BIT shown in Fig. 5.20(a) by a current source representing I . Assume that r„ is very large and thus can be neglected. In terms of this addition, what do the terminal currents i , i , and i become? If the base lead is open-circuited while the emitter is connected to ground and the collector is connected to a positive supply, find the emitter and collector currents.
F
5 . 5 2 A BJT for which I = 0.5 m A has V = 140 mV at I = 10 mA and V = 170 mV at I = 20 mA. Estimate the values of its saturation resistance, i ? , and its offset voltage, V . Also, determine the values of P and P . B
5 . 2 7 The current I of a small transistor is measured to be 20 nA at 25°C. If the temperature of the device is raised to 85°C, what do you expect I to become?
C£sat
CB
F
FIGURE P 5 . 2 6
5 . 5 0 A particular npn BJT with v = 720 mV at i = 600 pA, and having B - 150, has a collector-base junction 20 times larger than the emitter-base junction.
5 . 4 5 A BJT for which a = 0.2 operates with a constant base current but with the collector open. What value of V would you measure? R
CEsnt
5 . 4 6 Find the saturation voltage V and the saturation resistance jR of an npn BJT operated at a constant base current of 0.1 mA and a forced p of 20. The transistor has /? = 5 0 a n d / 3 = 0.2. C£sat
CEsat
F
R
* 5 . 4 7 Use Eq. (5.47) to show that the saturation resistance RcEsm = dv /di of a transistor operated with a constant base current l is given by CE
5 . 3 9 For a BJT having an Early voltage of 200 V, what is its output resistance at 1 mA? At 100 pAI
10 kf2
20 m
c
1 mA
B
1
EB
5 . 4 0 Measurements of the i -v characteristic of a smallsignal transistor operating at v = 720 mV show that i = 1.8 mA at v = 2 V and that i = 2.4 m A at v = 14 V. What is the corresponding value of i near saturation? At what value of v is i = 2.0 mA? What is the value of the Early voltage for this transistor? What is the output resistance that corresponds to operation at v = 720 mV? c
BE
CE
BE
c
F B
c
where
FIGURE P 5 . 5 3
CE
x
_
J
/^forced
Csat
F
c
BE
Find i ?
C £ s a t
for/3
forced
= ß /2. F
5 . 4 8 For a transistor for which fi = 70 and B = 0.7, find an estimate of R and V for I = 2 mA by evaluating V at i = 3 mA and at i = 0.3 mA (using Eq. 5.49). (Note: Because here we are modeling operation at a very low forced p, the value of R will be much larger than that given by Eq. 5.48). F
5 . 3 3 In Problem 5.32, the stated voltages are measured at 25°C. What values correspond at -25°C? At 125°C? 5 . 3 4 Use the Ebers-Moll expressions in Eqs. (5.26) and (5.27) to derive Eq. (5.35). Note that the emitter current is set to a constant value J . Ignore the terms not involving exponentials. E
5 . 4 1 Give the pnp equivalent circuit models that correspond to those shown in Fig. 5.20 for the npn case. 5 . 4 2 A BJT operating at i = 8 pA and i = 1 . 2 mA undergoes a reduction in base current of 0.8 pA. It is found that when v is held constant, the corresponding reduction in collector current is 0.1 mA. What are the values of h and hfe that apply? If the base current is increased from 8 pA to 10 pA B
c
CE
* 5 . 3 5 UseEq. (5.35) to plot the i -v characteristics of an npn transistor having a = 1, a = 0.1, and I = 1 0 " A. Plot c
CB
15
F
R
s
SECTION 5 . 3 : THE BJT AS AN AMPLIFIER AND AS A SWITCH
ß
c
CE
5 . 3 2 Consider a transistor for which the base-emitter voltage drop is 0.7 V at 10 mA. What current flowsforV =0.5 V?
ß I x(l-x)
CE
FE
l
}
CEsat
c
C£off
R
B
C£sat
c
CEsa
5 . 5 4 A common-emitter amplifier circuit operated with V = +10 V is biased at V = +1 V. Find the voltage gain, the maximum allowed output negative swing without the transistor entering saturation, and the corresponding maximum input signal permitted. cc
CE
5.55 For the common-emitter circuit in Fig. 5.26(a) w i t h F = +10 V and R = 1 fmd V and the voltage gain at the following dc collector bias currents: 1 mA, 2 mA, 5 mA, 8 mA, and 9 mA. For each, give the maximum possible positive- and c c
5 . 4 9 A transistor has B,, = 150 and the collector junction is 10 times larger than the emitter junction. Evaluate V for C£sat
A b r c e c / A - = 0.99 , 0.95, 0.9, 0.5, 0.1, 0.01, and 0.
c
CE
^t-'
PROBLEMS 522
Ûjy
CHAPTER 5
523
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
negative-output signal swing as determined by the need to keep the transistor in the active region. Present your results in a table. D 5 . 5 6 Consider the CE amplifier circuit of Fig. 5.26(a) when operated with a dc supply V = +5 V. It is required to find the point at which the transistor should be biased; that is, find the value of V so that the output sine-wave signal v resulting from an input sine-wave signal v of 5-mV peak amplitude has the maximum possible magnitude. What is the peak amplitude of the output sine wave and the value of the gain obtained? Assume linear operation around the bias point. (Hint: To obtain the maximum possible output amplitude for a given input, you need to bias the transistor as close to the edge of saturation as possible without entering saturation at any time, that is, without v decreasing below 0.3 V.)
* 5 . 5 9 In deriving the expression for small-signal voltage gain A in Eq. (5.56) we neglected the Early effect. Derive this expression including the Early effect, by substituting v
c
c
BE
c
BE
BE
c
m
c
c
0
m
CE
ce
A
V
B
n
CC
+5 V
5 . 6 2 The essence of transistor operation is that a change in V E> ^ B E ' produces a change in i , Ai . By keeping Av small. Ai is approximately linearly related to Av , Ai = g Av , where g is known as the transistor transconductance. By passing Ai through R , an output voltage signal Av is obtained. Use the expression for the small-signal voltage gain in Eq. (5.56) to derive an expression for g . Find the value of g for a transistor biased at 7 = 1 mA.
in Eq. (5.50). Show that the gain expression changes to
m
C
be
CE
A
-I R /VT
=
C
N
L
C
,
(VCC-VCEWT
=
I Rc
1
C
[
v +v ] A
V
,
1
VCC- CE1 A
CE
For the case V = 5 V and V = 2.5 V, what is the gain without and with the Early effect taken into account? Let V = 100 V. CC
CE
A
C
5 . 6 0 When the common-emitter amplifier circuit of Fig. 5.26(a) is biased with a certain V , the dc voltage at the collector is found to be +2 V. For V = +5 V and R = lkQ., find I and the small-signal voltage gain. For a change Av = +5 mV, calculate the resulting Av . Calculate it two ways: by finding Ai using the transistor exponential characteristic and approximately using the small-signal voltage gain. Repeat for Av = - 5 mV. Summarize your results in a table. BE
CC
c
C
BE
+ 10 V
0
c
BE
l ka
c
B
CE
5 . 5 7 The transistor in the circuit of Fig. P5.57 is biased at a dc collector current of 0.5 mA. What is the voltage gain? (Hint: Use Thevenin theorem to convert the circuit to the form in Fig. 5.26a).
R
B
I ' v + v l
CE
5 . 6 3 Consider the characteristic curves shown in Fig. 5.29 with the following additional calibration data: Label, from the lowest colored line, i = 1 pA, 10 pA, 20 pA, 30 pA, and 40 pA. Assume the lines to be horizontal, and let B = 100. For V c = 5 V and R = 1 kQ., what peak-to-peak collector voltage swing will result for i varying over the range 10 pA to 40 ,uA? If, at a new bias point (not the one shown in the figure) V = i V , find the value of I and I . If at this current V • •- 0.7 V and if R = 100 kQ., find the required value of V . CC
C
Y
B
B
BE
5 V
BB
* 5 . 6 4 Sketch the i -v characteristics of an npn transistor having j8 = 100 and V = 100 V. Sketch characteristic curves for i = 20 pA, 50 pA, 80 pA, and 100 pA. For the purpose of this sketch, assume that i = Bi at v = 0. Also, sketch the load line obtained for V = 10 V and R = 1 kQ. If the dc bias current into the base is 50 pA, write the equation for the corresponding i ~VcE curve. Also, write the equation for the load line, and solve the two equations to obtain V and I . If the input signal causes a sinusoidal signal of 30-pA peak amplitude to be superimposed on I , find the corresponding signal components of i and v . c
FIGURE P 5 . 6 6
CE
A
B
c
B
5 . 6 7 For each of the saturated circuits in Fig. P5.67, find i , i , and i . Use \V \ = 0.7 V and | V | = 0.2 V. B
c
E
BE
C £ s a t
CE
CC
c
+5 V
+5 V
A
A
c
* 5 . 6 1 Consider the common-emitter amplifier circuit of Fig. 5.26(a) when operated with a supply voltage V = +5 V. CC
CE
C
lkQ
lkQ
B
(a) What is the theoretical maximum voltage gain that this amplifier can provide? (b) What value of V must this amplifier be biased at to provide a voltage gain o f - 1 0 0 V/V? (c) If the dc collector current I at the bias point in (b) is to be 0.5 mA, what value of R should be used? (d) What is the value of V required to provide the bias point mentioned above? Assume that the BJT has I = 10~ A. (e) If a sine-wave signal v having a 5-mV peak amplitude is superimposed on V , find the corresponding output voltage signal v that will be superimposed on V assuming linear operation around the bias point. (f) Characterize the signal current i that will be superimposed on the dc bias current 7 . (g) What is the value of the dc base current I at the bias point. Assume B = 1 0 0 . Characterize the signal current i that will be superimposed on the base current I . (h) Dividing the amplitude of v by the amplitude of i , evaluate the incremental (or small-signal) input resistance of the amplifier. (i) Sketch and clearly label correlated graphs for v , v , i , and i . Note that each graph consists of a dc or average value and a superimposed sine wave. Be careful of the phase relationships of the sine waves. CE
—
—
FIGURE P5.57
C
5 . 5 8 Sketch and label the voltage transfer characteristics of thepnp common-emitter amplifiers shown in Fig. P5.58.
c
D 5 . 6 5 For the circuit in Fig. P5.65 select a value f o r R so that the transistor saturates with an overdrive factor of 10. The BJT is specified to have a minimum B of 20 and Vcesat 0.2 V. What is the value of forced B achieved?
C C
=+5V
<
+4VO-
B
<
-1.8 V o -
=
1 kfl
lkQ
c
BE
+5 V
15
S
+ F
CE
A
be
A
BE
ce
(b)
(a)
CE
1 kCl
rA
FIGURE P 5 . 6 7
c
C
B
B
b
BE
B
be
-V
C
C
=-5V
-±
(a) FIGURE P 5 . 5 8
(b)
B
CE
c
BE
BC
b
BE
* 5 . 6 8 Consider the operation of the circuit shown in Fig. P5.68 as v rises slowly from zero. For this transistor, assume 8 = 50, v at which the transistor conducts is 0.5 V, v when fully conducting is 0.7 V, saturation begins at v = 0.4 V, and the transistor is deeply in saturation at v = 0.6 V. Sketch and label v and v versus TIG. For what range of v is i essentially zero? What are the values of v , i , i , and v for v = 1 V and 3 V? For what value of v does saturation begin? What is i at this point? For v = 4V and 6 V, what are the values of v , v , i , i , and i ? Augment your sketch by adding a plot of i . BC
E
FIGURE P5.65
c
B
E
D 5 . 6 6 For the circuit in Fig. P5.66 select a value for R so that the transistor saturates with a forced ß of 10. Assume V = 0.7 V and V = 0.2 V. E
EB
£Csat
E
c
c
c
B
B
B
B
c
E
c
B
E
B
S^.'
524
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTS)
525
PROBLEMS
values of V and V correspond? For what value of V does the transistor reach saturation (when the base-to-collector junction reaches 0.5 V of forward bias)? What values of V and V correspond? Find the value of V for which the tran sistor operates in saturation with a forced p of 2. E
c
B
E
B
5 . 7 4 A single measurement indicates the emitter voltage of the transistor in the circuit of Fig. P5.74 to be 1.0 V. Under the assumption that \V \ = 0.7 V, what are V , I , I , I , V , P, and a ? (Note: Isn't it surprising what a little measurement can lead to?) BE
B
B
E
c
c
5 . 7 7 In the circuit shown in Fig. P5.76, the transistor has p = 30. Find the values of V , V , and V , and verify that the transistor is operating in the active mode. What is the largest value that R can have while the transistor remains in the active mode? B
E
c
c
+6V
A
+5 V
5 . 7 8 For the circuit in Fig. P5.78, find V . R = 100 kQ, 10 kQ, and 1 kQ. Let ß = 100. B
, and V for r
B
2kfi -oV
+5 V
c
A
A
V on
VB°~
; l kn FIGURE P 5 . 6 8
•2kft SECTION 5 . 4 :
v
c
BJT CIRCUITS AT DC
5 . 6 9 The transistor in the circuit of Fig. P5.69 has a very high ß. Find V and V for V (a) +2 V, (b) +1 V, and (c) 0 V. Assume V = 0.7 V. E
c
t 3 V
-5 V
v
E
s
FIGURE P5.71
FIGURE P 5 . 7 4
5 . 7 2 For the transistor shown in Fig. P5.72, assume a s 1 and v = 0.5 V at the edge of conduction. What are the values of V and V for V = 0 V? For what value of V does the transistor cut off? Saturate? In each case, what values of V and V result?
0 5 . 7 5 Design a circuit using a pnp transistor for which a = 1 and V = 0.7 V using two resistors connected appropriately to ±9 V so that I = 2 mA and V = 4.5 V. What exact values of R and R would be needed? Now, consult a table of stan dard 5% resistor values (e.g., that provided in Appendix G) to select suitable practical values. What are the values of I and V that result?
BE
BE
E
c
B
B
E
c
l kn
EB
E
E
BC
c
FIGURE P 5 . 7 8
E
BC
5 . 7 6 In the circuit shown in Fig. P5.76, the transistor has P= 30. Find the values of V , V , and V . If R is raised to 270 kQ, what voltages result? With R = 270 kQ, what value of P would return the voltages to the values first calculated? B
E
c
B
5 . 7 9 For the circuits in Fig. P5.79, find values for the labeled node voltages and branch currents. Assume P to be very high and | V \ = 0.7 V. BE
B
+9 V
BE
FIGURE P 5 . 6 9 oV
E
5 . 7 0 The transistor in the circuit of Fig. P5.69 has a very high 0. Find the highest value of V for which the transistor still operates in the active mode. Also, find the value of V for which the transistor operates in saturation with a forced P of 1.
Vo
B
R
FIGURE P 5 . 7 2
B
5 . 7 1 Consider the operation of the circuit shown in Fig. P5.71 for V at - 1 V, 0 V, and +1 V. Assume that V is 0.7 V for usual currents and that P is very high. What values of V and V result? At what value of V does the emitter current reduce to one-tenth of its value for V = 0 V ? For what value of V is the transistor just at the edge of conduction? What B
BE
E
c
B
s
B
OV
D 5 . 7 3 Consider the circuit in Fig. P5.69 with the base volt age V obtained using a voltage divider across the 5-V sup ply. Assuming the transistor p to be very large (i.e., ignoring the base current), design the voltage divider to obtain V = 2 V. Design for a 0.2-mA current in the voltage divider. Now, if the BJT p = 100, analyze the circuit to detemrine the collector current and the collector voltage.
* 5 . 8 0 Repeat the analysis of the circuits in Problem 5.79 using P = 100. Find all the labeled node voltages and branch currents. Assume | V \ = 0.7 V.
r
* * D 5 . 8 1 It is required to design the circuit in Fig. P5.81 so that a current of 1 mA is established in the emitter and a volt age of +5 V appears at the collector. The transistor type used has a nominal P of 100. However, the P value can be as low as 50 and as high as 150. Your design should ensure that the specified emitter current is obtained when j3 = 100 and that at the extreme values of P the emitter current does not change by more than 10% of its nominal value. Also, design for as large a value for R as possible. Give the values of R , R , and R to the nearest kilohm. What is the expected range of col lector current and collector voltage corresponding to the full range of p values? B
B
E
c
B
2.7 Ml
B
-9 V
D 5 . 8 2 The pnp transistor in the circuit of Fig. P5.82 has P = 50. Find the value for R to obtain V = +5 V. What hap pens if the transistor is replaced with another having P = 100? c
FIGURE P 5 . 7 6
c
526
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
PROBLEMS
+5 V
* * 5 . 8 3 Consider the circuit shown in Fig. P5.83. It resembles that in Fig. 5.41 but includes other features. First, note diodes Di and D are included to make design (and analysis) easier and to provide temperature compensation for the emitter-base voltages of Q and Q . Second, note resistor R, whose propose is provide negative feedback (more on this later in the book!). Using \V \ and V = 0.7 V independent of current and B= °°, find the voltages V V , V , V , V , and V , initially with R open-circuited and then with R connected. Repeat for 3 = 100, initially with R open-circuited then connected.
+ 10V
2
x
-oV,
2
BE
D
BU
m
cl
B2
E2
c2
2.2 KN
-5 V (a)
(c) +5 V
100 Û
-10 V FIGURE P 5 . 8 4
+5 V
A
+ 10 V 3.3 kfi
3.3 K N •91 K N
-OY„
•+1.2V
<
—Ws,—[ 56 K N -OVq
-°v„
100 N
150 K N : 5.I K N
: 5.I K N
Y -5 V
-5 V
(d)
FIGURE P 5 . 8 3
(e) * 5 . 8 4 For the circuit shown in Fig. P5.84, find the labeled node voltages for:
-10 V FIGURE P5.85
(a) (b) j9= 100 * * D 5 . 8 5 Using /} = <*>, design the circuit shown in Fig. P5.85 so that the bias currents in Q , Q , and Q are 2 mA, 2 mA, and 4 mA, respectively, and V = 0, V = - 4 V, and V = 2 V. For each resistor, select the nearest standard value utilizing the table of standard values for 5% resistors in Appendix G. Now, for B = 100, find the values of V , V , V , V , and V . x
2
3
3
5
7
3
O
loo k n
-15 v FIGURE P 5 . 8 1
FIGURE P5.82
V
r
4
5
6
Vf O
o
7
5 . 8 6 For the circuit in Fig. P5.86, find V and V for B , = 0 V , +3 V, - 5 V, and - 1 0 V. The BJTs have B = 100. B
E
* * 5 . 8 7 Find approximate values for the collector voltages in the circuits of Fig. P5.87. Also, calculate forced B for each of the transistors. (Hint: Initially, assume all transistors are operating in saturation, and verify the assumption.)
-5 V FIGURE P 5 . 8 6
Vp
PROBLEMS CHAPTER 5
5 2 8
* D 5 . 9 4 Utilizing +5-V power supplies, it is required to design a version of the circuit in Fig. 5.45 in which the signal will be coupled to the emitter and thus R can be set to zero. Find values for R and R so that a dc emitter current of 1 mA is obtained and so that the gain is maximized while allowing +1 V of signal swing at the collector. If temperature increases from the nominal value of 25°C to 125°C, estimate the percentage change in collector bias current. In addition to the - 2 mV/°C change in V , assume that the transistor p changes over this temperature range from 50 to 150.
+10 V + 10 V
v.^.: 5 2 9
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
+10 V
é
values of / and R to bias the B JT at I = 3 mA and V = 1.5 V. Let/3 = 90. B
c
c
B
E
c
BE
0 5 . 9 5 Using a 5-V power supply, design a version of the circuit of Fig. 5.46 to provide a dc emitter current of 0.5 m A and to allow a ±1-V signal swing at the collector. The BJT has a nominal P = 100. Use standard 5%-resistor values (see Appendix G). If the actual BJT used has P = 50, what emitter current is obtained? Also, what is the allowable signal swing at the collector? Repeat for p= 150.
-10 V (a)
(b)
(c)
FIGURE P 5 . 8 7
FIGURE P 5 . 9 7
SECTION 5 . 5 : BIASING I N BJT AMPLIFIER CIRCUITS
0 5 . 9 1 Repeat Problem 5.90, but use a voltage-divider current which is I /2. Check your design at 8=90. If you have the data available, find how low B can be while the value of I does not fall below that obtained with the design of Problem 5.90 for p = 90. E
0 5 . 8 8 For the circuit in Fig. 5.43(a), neglect the base current I in comparison with the current in the voltage divider. It is required to bias the transistor at I = 1 mA, which requires selecting R and R so that V = 0.690 V. If V = 5 V, what must the ratio R /R be? Now, if R and R are 1% resistors, that is, each can be in the range of 0.99 to 1.01 of its nominal value, what is the range obtained for V 7 What is the corresponding range of I 7 If R = 3 k£2, what is the range obtained for V ? Comment on the efficacy of this biasing arrangement. B
c
B2
Bl
BB
cc
B2
m
B2
BE
c
c
C£
* * D 5 . 9 2 It is required to design the bias circuit of Fig. 5.44 for a BJT whose nominal P= 100.
c
c
c
CE
0 5 . 9 0 Consider the single-supply bias network shown in Fig. 5.44(a). Provide a design using a 9-V supply in which the supply voltage is equally split between R , V , and R with a collector current of 3 mA. The transistor Q is specified to have a minimum value of 90. Use a voltage-divider current of 7 / 1 0 . or slightly higher. Since a reasonable design should operate for the best transistors for which ¡3 is very high, do your initial design with /3 = =». Then choose suitable 5% resistors (see Appendix G), making the choice in a way that will result in a V that is slightly higher than the ideal value. Specify the values you have chosen for R , R . R^, and R . Now, find V , V , V , and I for your final design using j8=90. c
CB
E
BS
E
B
c
5 . 9 8 The circuit in Fig. P5.98 provides a constant current I as long as the circuit to which the collector is connected maintains the BJT in the active mode. Show that 0
c
=
y
c c
r,* /(* +* )]-y 2
1
2
M
c
0
R + (R IIR )/(P+\) E
l
2
B
E
E
(b) If the resistance ratio found in (a) is used, find an expression for the voltage V = V R /(Ri + R ) that will result in a voltage drop of V /3 across R . (c) For V = 10 V, find the required values of R R , and R to obtain l = 2 mA and to satisfy the requirement for stability of I in (a). cc
2
cc
B2
c
c
2
E
cc
lt
2
B
E
E
B
c
2
cc
B
(a) Find the largest ratio (R /R ) that will guarantee I remain within ± 5 % of its nominal value for p as low as 50 and as high as 150.
BB
D 5 . 8 9 It is required to bias the transistor in the circuit of Fig. 5.43(b) at I = 1 mA. The transistor Q is specified to be nominally 100, but it can fall in the range of 50 to 150. For Vcc = +5 V and R = 3 kQ, find the required value of R to achieve [ = 1 mA for the "nominal" ttansistor. What is the expected range for I and V 7 Comment on the efficacy of this bias design.
c
c
c
c
Bl
* D 5 . 9 6 (a) Using a 3-V power supply, design the.feedback bias circuit of Fig. 5.46 to provide I = 3 mA and V = V /2 for/3=90. (b) Select standard 5% resistor values, and reevaluate V and / forj8=90. (c) Find V and l for p = °°. (d) To improve the situation that obtains when high-/? transistors are used, we have to arrange for an additional current to flow through R . This can be achieved by connecting a resistor between base and emitter, as shown in Fig. P5.96. Design this circuit for P=90. Use a current through R equal to the base current. Now, what values of V and I result with p = <*,•}
E
c
c
c
(d) Find R so that V c
CE
= 3 V for P equal to its nominal value.
Check your design by evaluating the resulting range of I . E
* D 5 . 9 3 Consider the two-supply bias arrangement shown in Fig. 5.45 using ±3-V supplies. It is required to design the circuit so that I = 3 mA and V is placed midway between V and V . c
cc
FIGURE P 5 . 9 8
c
E
E
(a) For P = <*>, what values of R and R are required? (b) If the BJT is specified to have a minimum P of 90, find the largest value for R consistent with the need to limit the voltage drop across it to one-tenth the voltage drop across R . (c) What standard 5%-resistor values (see Appendix G) would you use for R , R , and R 7 In making your selection, use somewhat lower values in order to compensate for the low-/5 effects. (d) For the values you selected in (c), find I , V , V , and V for/j=°oandfor/j=90. E
c
]
E
E
c
c
B
E
c
B
l
B
B
* * D 5 . 9 9 The current-bias circuit shown in Fig. P5.99 provides bias current to Q that is independent of R and nearly independent of the value of p (as long as Q operates in the active mode). Prepare a design meeting the following specifications: Use +5-V supplies; I = 0.1 mA, V = 2V for p = °°; the voltage across R decreases by at most 5% for ¡3 = 50; V = 1.5 V for P = °o and 2.5 V for P = 50. Use standard 5%-resistor values (see Appendix G). What values for R R , R , R , and R do you choose? What values of I and V result for P = 50, 100, and 200? ci
2
RE
E
FIGURE P 5 . 9 6
CE1
h
0 5 . 9 7 A circuit that can provide a very large voltage gain for a high-resistance load is shown in Fig. P5.97. Find the
E
B
c
cl
2
C £ 1
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
CHAPTER 5
5 3 0
PROBLEMS
0.5 mA. What is the lowest voltage that can be applied to the collector of Q 1 3
D 5 . 1 0 1 For the circuit in Fig. P5.101 find the value of R that will result in I ~ 2 mA. What is the largest voltage that can be applied to the collector? Assume • 0.7 V.
'
5 3 1
the small-signal resistance seen looking into the emitter (/•<,)? Into the base (r^p. If the collector is connected to a 5-kQ. load, with a signal of 5-mV peak applied between base and emitter, what output signal voltage results?
5 . 1 1 1 A BJT is biased to operate in the active mode at a dc collector current of 1.0 mA. It has a B of 120. Give the four small-signal models (Figs. 5.51 and 5.52) of the BJT com plete with the values of their parameters.
D 5 . 1 0 6 A designer wishes to create a BJT amplifier with a g of 50 mA/V and a base input resistance of 2000 Q. or more. What emitter-bias current should he choose? What is the minimum B he can tolerate for the transistor used?
5 . 1 1 2 The transistor amplifier in Fig. P5.112 is biased with a current source / and has a very high B. Find the dc voltage at the collector, V . Also, find the value of g . Replace the transistor with the simplified hybrid-7T model of Fig. 5.51(a) (note that the dc current source / should be replaced with an open circuit). Hence find the voltage gain v /v .
0
+5 V
m
c
5 . 1 0 7 A transistor operating with nominal g of 60 mA/V has a B that ranges from 50 to 200. Also, the bias circuit, being less than ideal, allows a +20% variation in I . What are the extreme values found of the resistance looking into the base? m
<
R
m
c
t
+5 V
c
5 . 1 0 8 In the circuit of Fig. 5.48, V ^ i s adjusted"so that V = 2 V. If V = 5 V, R = 3 kQ, and a signal v = 0.005 sin cat volts is applied, find expressions for the total instantaneous quantities i (t), v (t), and i (t). The transistor has B = 100. What is the voltage gain? c
cc
-v
EE
FIGURE P 5 . 9 9
c
* D 5 . 1 0 0 For the circuit in Fig. P5.100, assuming all tran sistors to be identical with B infinite, derive an expression for the output current I , and show that by selecting 0
R
i = 2
0
j
_
aV
cc
which is independent of V . What must the relationship of R to R and R be? For V = 10 V and assuming a — 1 and V = 0.7 V, design the circuit to obtain an output current of
SECTION 5 . 6 : SMALL-SIGNAL OPERATION AND MODELS
2
BE
cc
c
B
cc
5 . 1 0 2 Consider a transistor biased to operate in the active mode at a dc collector current l . Calculate the collector sig nal current as a fraction of I (i.e., i /I ) for input signals v of +1 mV, - 1 mV, +2 mV, - 2 mV, +5 mV, - 5 mV, +8 mV, - 8 mV, +10 mV, - 1 0 mV, +12 mV, and - 1 2 mV. In each case do the calculation two ways: c
c
c
* D 5 . 1 0 9 We wish to design the amplifier circuit of Fig. 5.48 tmder the constraint that V is fixed. Let the input signal v = V sin ft)?, where V is the maximum value for acceptable linearity. For the design that results in the largest signal at the collector, without the BJT leaving the active region, show that be
c
be
be
Y
be
BE
1
be
FIGURE P 5 . 1 0 1
R
and keeping the current in each junction the same, the current I will be
E
c
(a) using the exponential characteristic, and (b) using the small-signal approximation.
RI C
C
= (V
c c
- 0.3
FIGURE P 5 . 1 1 2
-V )/(l+yf^j be
and find an expression for the voltage gain obtained. For V = 5 V and V = 5 mV, find the dc voltage at the collector, the amplitude of the output voltage signal, and the voltage gain.
5 . 1 1 3 For the conceptual circuit shown in Fig. 5.50, R = 2 kQ,, g = 50 mA/V, and B = 100. If a peak-to-peak output voltage of 1 V is measured at the collector, what ac input voltage and current must be associated with the base?
5 . 1 1 0 The following table summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various conditions. Provide the missing entries.
5 . 1 1 4 A biased BJT operates as a grounded-emitter amplifier between a signal source, with a source resistance of 10 kO, connected to the base and a 10-kQ load connected as a collector resistance R - In the corresponding model, g is 40 mA/V
c
cc
m
be
Present your results in the form of a table that includes a col umn for the error introduced by the small-signal approxima tion. Comment on the range of validity of the small-signal approximation. 5 . 1 0 3 An npn BJT with grounded emitter is operated with V = 0.700 V, at which the collector current is 1 mA. A 10-kQ resistor connects the collector to a +15-V supply. What is the resulting collector voltage V l Now, if a signal applied to the base raises v to 705 mV, find the resulting total collec tor current i and total collector voltage v using the expo nential i -v relationship. For this situation, what are v and v l Calculate the voltage gain v /v . Compare with the value obtained using the small-signal approximation, that is, -grrftc-
c
m
BE
c
Transistor
a
b
c
d
e
f
9
BE
c
c
c
BE
be
c
c
be
j
a
\ß J4(mA)
5 . 1 0 5 A pnp BJT is biased to operate at 7 = 2.0 mA. What is the associated value of g ? If B = 50, what is the value of
! r (Q)
K
e
j/ (mA) B
1.00
j
oo
1.00
j
1.00
5 0.020
! g (mA/V)
FIGURE P 5 . 1 0 0
m
e
' 25
(Note: \r (Q.) Isn't it remarkable how much two parameters can reveal?) n
I 1.10 j
m
C
j
0.90 100
/, imAi
5 . 1 0 4 A transistor with B = 120 is biased to operate at a dc collector current of 1.2 mA. Find the values of g , r , and r . Repeat for a bias current of 120 pA. m
1.000
100 10.1 kO
700
CHAPTER 5
5 3 2
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs) PROBLEMS
and r is 2.5 kQ. Draw the complete amplifier model using the hybrid-n BJT equivalent circuit. Calculate the overall voltage gain ( v / v ) . What is the value of BJT B implied by the val ues of the model parameters? To what value must B be increased to double the overall voltage gain? K
c
(v /v ). For an output signal of ±0.4 V, what values of i> and v are required? 0
sig
in
0
sig
+9 V A
5 . 1 1 7 Consider the augmented hybrid-TZ: model shown in Fig. 5.58(a). Disregarding how biasing is to be done, what is the largest possible voltage gain available for a signal source connected directly to the base and a very-high-resistance load? Calculate the value of the maximum possible gain for V = 25 V and V = 250 V. A
A
5 . 1 1 8 Reconsider the amplifier shown in Fig. 5.53 and analyzed in Example 5.14 under the condition that B is not well controlled. For what value of B does the circuit begin to saturate? We can conclude that large B is dangerous in this circuit. Now, consider the effect of reduced B, say, to B = 25. What values of r , g , and r result? What is the overall volt age gain? (Note: You can see that this circuit, using basecurrent control of bias, is very /^-sensitive and usually not recommended.) e
lOkQ. C,
m
n
-ov„
On
sig
10 kfl
o-
AAA
50
5 . 1 1 9 Reconsider the circuit shown in Fig. 5.55(a) under the condition that the signal source has an internal resistance of 100 Q. What does the overall voltage gain become? What is thé largest input signal voltage that can be used without output-signal clipping?
RL
a
incremental (small-signal) resistance of the resulting twoterminal device (known as a diode-connected transistor.)
amplifiers. This non-unilateral equivalent circuit is based on the ^-parameter two-port representation (see Appendix B).
* * D 5 . 1 2 3 Design an amplifier using the configuration of Fig. 5.55(a). The power supplies available are ±10 V. The input signal source has a resistance of 100 Q, and it is required that the amplifier input resistance match this value. (Note that R = r II R — r .) The amplifier is to have the greatest possible voltage gain and the largest possible output signal but retain small-signal linear operation (i.e., the signal component across the base-emitter junction should be limited to no more than 10 mV). Find appropriate values for R and R . What is the value of voltage gain realized?
(a) Using the values of R A , andj? found in Example 5.17 together with the measured value of R of 400 k Q obtained when a load R of 10 k Q is connected to the output, deter mine the value of the feedback factor/. (b) Now, use the equivalent circuit of Fig. P5.126 to deter mine the value of R obtained when the amplifier is fed with a signal generator having R = 100 kQ. Check your result against that found in Example 5.17.
in
e
E
e
©
©
D 5 . 1 2 0 Redesign the circuit of Fig. 5.55 by raising the resistor values by a factor n to increase the resistance seen by the input v to 75 Q. What value of voltage gain results? Grounded-base circuits of this kind are used in systems such as cable TV, in which, for highest-quality signaling, load resistances need to be "matched" to the equivalent resistances of the interconnecting cables. t
FIGURE P 5 . 1 1 5
h
vo
0
in
L
out
sig
E
c
* 5 . 1 2 4 The transistor in the circuit shown in Fig. P5.124 is biased to operate in the active mode. Assuming that P is very large, find the collector bias current I . Replace the transistor with the small-signal equivalent circuit model of Fig. 5.52(b) (remember to replace the dc power supply with a short circuit). Analyze the resulting amplifier equivalent circuit to show that c
Voi
RE
=
r
Vi
R +e
FIGURE P 5 . 1 2 6
E
=
Vj
0.5 mA
533
sig
b
s
S i l l S For the circuit shown in Fig. P5.115, draw a com plete small-signal equivalent circuit utilizing an appropriate T model for the BJT (use a= 0.99). Your circuit should show the values of all components, including the model parame ters. What is the input resistance i? ? Calculate the overall voltage gain (v /v ).
!
-aR R + r c
E
5 . 1 2 7 Refer to Table 5.5. By equating the expression for G obtained from Equivalent Circuit A to that obtained from Equivalent Circuit C with G = [R/(Rj + R )]A , show that v
e
Find the values of these voltage gains (for a — 1). Now, if the terminal labeled v is connected to ground, what does the voltage gain v /vi become? ol
v0
sig
vo
o2
^in ^sig +
+15 V
R
R
Rj _
R
R
L
+
R
o
R
i sig + m
L + ^out
Now, use this expression to:
5 . 1 1 6 In the circuit shown in Fig. P5.116, the transistor has a B of 200. What is the dc voltage at the collector? Find the input resistances R and R and the overall voltage gain ib
m
+5 V
\t
)
(a) Show that for R = <*>, R = R . (b) Show that for R = 0, R = R . (c) Find R when R = °° (i.e., the amplifier input is opencircuited), and evaluate its value for the amplifier specified in Example 5.17. L
10mA
E
(a) the voltage gain between base and emitter, that is, is given by
oul
0Ut
t
0
sig
5 . 1 2 8 A common-emitter amplifier of the type shown in Fig. 5.60(a) is biased to operate at I = 0.2 mA and has a col lector resistance R = 24 kQ. The transistor has P = 100 and a large V . The signal source is directly coupled to the base, and C and R are eliminated. Find R , the voltage gain A , and R . Use these results to determine the overall voltage gain when a 10-kQ load resistor is connected to the collector and the source resistance i? = 10 kQ. c
v /v , e
m
sig
b
A
+ 1.5 V
5 . 1 2 1 Using the BJT equivalent circuit model of Fig. 5.52(a), sketch the equivalent circuit of a transistor amplifier for which a resistance R is connected between the emitter and ground, the collector is grounded, and an input signal source v is connected between the base and ground. (It is assumed that the transistor is properly biased to operate in the active region.) Show that: b
c
A
v.
lOkfl
R.
cl
FIGURE P 5 . 1 2 4
v
•zr
b
A/VV
o-
lkfl
(b) the input resistance, R = ^ = (P+lXR h iB
-o»
e
FIGURE P 5 . 1 1 6
IN
E
E
o
SINGLE-STAGE BJT AMPLIFIERS
5 . 1 2 S An amplifier is measured to have A', = 10 kQ. A = 100 V/V, and R„ = 100 Q. Also, when a load resistance R of 1 kQ is connected between the output terminals, the input resistance is found to decrease to 8 kQ. If the amplifier is fed with a signal source having an internal resistance of 2 kQ, find G , A , G , G , R , and A . v0
Find the numerical values for (v /v ) a n d R for the case R = 1 kQ, P = 100, and the emitter bias current I = 1 mA. b
ia
vo
sig
t
0
e
Rc 100
SECTION 5 . 7 :
+ r)
B
a
5 . 1 2 2 When the collector of a transistor is connected to its base, the transistor still operates (internally) in the active region because the collector-base junction is still in effect reverse biased. Use the simplified hybrid-^: model to find the
L
m
v
v0
v
om
5 . 1 2 9 Repeat Problem 5.128 with a 125-Q resistance included in the signal path in the emitter. Furthermore, con trast the maximum'amplitude of the input sine wave that can be applied with and without R assuming that to limit distor tion the signal between base and emitter is not to exceed 5 mV. e
t
5 . 1 2 6 Figure P5.126 shows an alternative equivalent circuit for representing any linear two-port network including voltage
5 . 1 3 0 For the common-emitter amplifier shown in Fig. P5.130, let V = 9N,R = 27 kQ, R = 15 k Q , R = \ 2 kQ, and R = 2.2 kQ. The transistor has P = 100 and V = 100 V. cc
c
1
2
E
A
tgf
5 3 4
CHAPTER 5
Calculate the dc bias current I . If the amplifier operates between a source for which i ? = 10 k Q and a load of 2 kQ, replace the transistor with its hybrid-^: model, and find the values of R , the voltage gain v /v , and the current gain i /i . E
sig
in
0
PROBLEMS
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
0
sig
t
Stage 2
below the base voltage with the signal between base and emitter being as high as 5 mV.
I
L V
cc
5 3 5
Load
k
Assume that v is a sinusoidal source, the available supply V = 5 V, and the transistor has fl = 100 and a very large Early voltage. Use standard 5%-resistance values, and specify the value of I to one significant digit. What base-to-collector open-circuit voltage gain does your design provide? If R = R = 10 kQ, what is the overall voltage gain? sig
cc
-O
iitt
v„
L
D 5 . 1 3 4 In the circuit of Fig. P5.134, v is a small sinewave signal with zero average. The transistor B is 100. sig
(a) Find the value of R to establish a dc emitter current of about 0.5 mA. (b) Find R to establish a dc collector voltage of about +5 V. (c) For R = 10 k Q and the transistor r = 200 kQ, draw the small-signal equivalent circuit of the amplifier and determine its overall voltage gain. E
c
L
0
+ 15 V A
FIGURE P S . 1 3 5
5 . 1 3 ® In the circuit of Fig. P5.136, v is a small sine-wave signal. Find R and the gain vj v . Assume B = 100. If the amplitude of the signal v is to be limited to 5 mV, what is the largest signal at the input? What is the corresponding signal at the output? sig
in
FIGURE P 5 . 1 3 0
be
D 5 . 1 3 1 Using the topology of Fig. P5.130, design an amplifier to operate between a 10-kQ source and a 2-kQ load with a gain v /v o f - 8 V/V. The power supply available is 9 V. Use an emitter current of approximately 2 mA and a current of about one-tenth of that in the voltage divider that feeds the base, with the dc voltage at the base about one-third of the supply. The transistor available has B = 100 and V = 100 V. Use standard 5% resistor (see Appendix G). a
sig
0.5 mA
•
9V
sig
Q
? 300 k Q
CO
II
.,
-o
v„
30 k Q
A
5 . 1 3 2 A designer, having examined the situation described in Problem 5.130 and estimating the available gain to be approximately - 8 V/V, wishes to explore the possibility of improvement by reducing the loading of the source by the amplifier input. As an experiment, the designer varies the resistance levels by a factor of approximately 3:R to 82 kQ, R to 47 kQ, R to 3.6 kQ, and R to 6.8 kQ (standard values of 5%-tolerance resistors). With V = 9 V, R =WkQ,R = 2 kQ, B = 100, and V = 100 V, what does the gain become? Comment. l
2
E
c
cc
sig
L
Vi
20kft
-15 V FIGURE P 5 . 1 3 4
FIGURE P 5 . 1 3 7
* 5 . 1 35 The amplifier of Fig. P5.135 consists of two identical common-emitter amplifiers connected in cascade. Observe that the input resistance of the second stage, R , constitutes the load resistance of the first stage.
* 5 . 1 3 8 Refer to the voltage-gain expression (in terms of transistor B) given in Eq. (5.135) for the CE amplifier with a resistance R in the emitter. Let the BJT be biased at an emit ter current of 0.5 mA. The source resistance R is 10 kQ. The BJT B is specified to lie in the range of 50 to 150 with a nominal value of 100.
in2
e
A
D 5 . 1 33 Consider the CE amplifier circuit of Fig. 5.60(a). It is required to design the circuit (i.e., find values for 7, R , and R ) to meet the following specifications: B
c
(a) R s 5 kQ. (b) the dc voltage drop across R is approximately 0.5 V. (c) the open-circuit voltage gain from base to collector is the maximum possible, consistent with the requirement that the collector voltage never falls by more than approximately 0.5 V ia
B
250 Q
(a) For V = 15 V, R = 100 kQ, R = 47 kQ, R = 3.9 kQ, R = 6.8 kQ, and B= 100, determine the dc collector current and dc collector voltage of each transistor. (b) Draw the small-signal equivalent circuit of the entire amplifier and give the values of all its components. Neglect r„\ and r . cc
l
2
E
o2
(c) (d) (e) (f)
Find R and v /v for R = 5 kQ. Find R and v /v . For R = 2 kQ, find v /v . Find the overall voltage gain v /v . inl
in2
L
bl
sig
Ag
b2
bl
a
b2
a
sig
sig
c
FIGURE P 5 . 1 3 6
* 5 . 1 3 7 The B JT in the circuit of Fig. P5.137 has B = 100.
(a) What is the ratio of maximum to minimum voltage gain obtained without R ? (b) What value of R should be used to limit the ratio of max imum to minimum gain to 1.2? (c) If the R found in (b) is used, by what factor is the gain reduced (compared to the case without R ) for a BJT with a nominal Bl e
(a) Find the dc collector current and the dc voltage at the collector. (b) Replacing the transistor by its T model, draw the smallsignal equivalent circuit of the amplifier. Analyze the resulting circuit to determine the voltage gain v /v 0
r
e
e
e
5 3 7
PROBLEMS B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
CHAPTER 5
5 3 6
S. 1 3 9 Consider the CB amplifier of Fig. 5.62(a) with R = 10 kQ, R = 10 kQ, V = 10 V, and R = 100 Q. To what value must I be set in order that the input resistance at E is equal to that of the source (i.e., 100 £2)? What is the resulting voltage gain from the source to the load? Assume a — I. L
c
cc
sig
(a) I , V , and V . (b) the input resistance R . (c) the voltage gain v /v E
* * D 5 . 1 4 ® Consider the CB amplifier of Fig. 5.62(a) with the collector voltage signal coupled to a 1-kQ load resistance through a large capacitor. Let the power supplies be ±5 V. The source has a resistance of 50 Q. Design the circuit so that the amplifier input resistance is matched to that of the source and the output signal swing is as large as possible with rela-' tively low distortion (v limited to 10 mV). Find / and R and calculate the overall voltage gain obtained and the output signal swing. Assume a — I. be
E
in
a
Q , v /v , and find the input resistance R looking into the base of Q . (Hint: Consider Q as an emitter follower fed by a voltage v at its base.) (c) Replacing Q with its input resistance R found in (b), analyze the circuit of emitter follower Q to determine its input resistance R , and the gain from its base to its emitter, v /v . (d) If the circuit is fed with a source having a 100-kQ resistance, find the transmission to the base of Q v /v . (e) Find the overall voltage gain v /v . 2
0
b2
ib2
2
2
b2
2
ib2
x
in
5 . 1 4 6 The emitter follower of Fig. 5.63(a), when driven from a 10-kQ source, was found to have an open-circuit voltage gain of 0.99 and an output resistance of 200 Q. The output resistance increased to 300 Q when the source resistance was increased to 20 kQ. Find the overall voltage gain when the follower is driven by a 30-kQ source and loaded by a 1-kQ resistor. Assume r is very large.
A
+9 V
A
A
el
bl
u
0
bl
Ag
Ag
+9 V
A
0
* * 5 . 1 4 7 For the circuit in Fig. P5.147, called a bootstrapped follower:
5 . 1 4 1 For the circuit in Fig. P5.141, find the input resistance R and the voltage gain v /v . Assume that the source provides a small signal v and that B = 100. 0
sig
B
c
m
of the follower? Find the gain v /v with no load and with a load of 1 kQ. With the 1-kQ load connected, find the largest possible negative output signal. What is the largest possible positive output signal if operation is satisfactory up to the point that the base-collector junction is forward biased by 0.4 V? 0
5 . 1 4 3 For the emitter-follower circuit shown in Fig. P5.143 the BJT used is specified to have B values in the range of 40 to 200 (a distressing situation for the circuit designer). For the two extreme values of B (B = 40 and B = 200), find:
(a) Find the dc emitter current and g , r , and r . Use B = 100. (b) Replace the BJT with its T model (neglecting r ), and analyze the circuit to determine the input resistance R and the voltage gain v /v . (c) Repeat (b) for the case when capacitor C is open-circuited. Compare the results with those obtained in (b) to find the advantages of bootstrapping. m
sig
e
1 Mn
%
a
sig
in
0
sig
B
1 MO
FIGURE P 5 . 1 4 3
-o v
0
5 . 1 4 4 For the emitter follower in Fig. P5.144, the signal source is directly coupled to the transistor base. If the dc component of v is zero, find the dc emitter current. Assume B= 100. Neglecting r , find R , the voltage gain v /v , the current gain i /i„ and the output resistance R .
0
50yuA
0
sig
0
in
a
0
5 mA
sig
mt
FIGURE P 5 . 1 4 8
+5 V o v„
SECTION 5 . 8 :
THE BJT INTERNAL CAPACITANCES
AND HIGH-FREQUENCY MODEL 5 . 1 4 9 An npn transistor is operated at 7 = 0.5 mA and V = 2 V. It has B = 100, V = 50 V, x = 30 ps, C = 20 fF, C„ = 30 fF, V = 0.75 V, m = 0.5, and r = 100 Q. Sketch the complete hybrid-^: model, and specify the values of all its components. Also, find f . C
FIGURE P 5 . 1 4 1
0
2
kfi
A
0c
5 . 1 4 2 Consider the emitter follower of Fig. 5.63(a) for the case: / = 1 mA, B = 100, V = 100 V, R = 100 kQ, R „ = 20 kQ, and R = 1 kQ. A
B
L
n
b
sig
0
- ±
Ag
B
a
Ag
si
Slg
L
0
x
5 . 1 5 0 Measurement of h of an npn transistor at 500 MHz shows that \h \ = 2.5 at I = 0.2 mA and 11.6 at 7 = 1.0 mA Furthermore, C was measured and found to be 0.05 pF. Find f at each of the two collector currents used. What must x and C be? fi
fe
FIGURE P 5 . 1 4 7
sig
sig
CBJ
je0
T
si
(a) Findiq , v /v ,
CB
F
c
C
p
T
-5 V
* * 5 . 1 4 8 For the follower circuit in Fig. P5.148 let transistor Ö! have B = 50 and transistor Q have ß = 100, and neglect the effect of r . Use V = 0.7 V.
FIGURE P 5 . 1 4 4
2
0
5 . 1 4 5 In the emitter follower of Fig. 5.63(a), the signal source is directly coupled to the base. Thus, C and R are eliminated. The source has R = 10 kQ and a dc component of zero. The transistor has B = 100 and V = 125 V. The bias current / = 2.5 mA, and V = 3 V. What is the output resistance a
sig
A
cc
B
BE
E
ie
2 mA has C = 5 . 1 5 1 A particular -BJT operating at 7 1 pF, C = 10 pF, and B = 150. What a r e / and for this situation?
(a) Find the dc emitter currents of Q and Q . Also, find the dc voltages V and V . (b) If a load resistance R = 1 k Q is connected to the output terminal, find the voltage gain from the base to the emitter of x
B1
m
L
2
p
C
%
r
5 . 1 5 2 For the transistor described in Problem 5.151, C includes a relatively constant depletion-layer capacitance of 2 pF. n
538
)
CHAPTER 5
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs) PROBLEMS
V • 'f (mA)
Transistor
9m
:
T,
(mA/V)
(¿2)
C,
f
T
(kQ)
(MHz)
ß
0
Ç
(pF)
f„ (MHz)
(pF)
e 1 6 0 For a version of the CE amplifier circuit in Fig. P5.159, \ = 10 kQ, Ri = 68 kQ, R = 27 kQ, R = 2.2 kQ, R = 4.7 kQ, a = 10 kQ. The collector current is 0.8 mA, ß = 200, f = 1 GHz, and C = 0.8 pF. Neglecting the effect of r and r , find the midband voltage gain and the upper 3-dB frequency f„.
R
(a)
1
100
(b)
400
2
25 2.525
(d)
io.7
400
10
100
400
2
0.1
100
100
2
(f)
1
10
400
2
800
1
(g)
c
T
ß
4
13.84
(e)
E
L
2
c
()
2
x
B
* 5 1 6 1 The amplifier shown in Fig. P5.161 has R
sig
1 kQ, Rc = 1 600 MHz. 9
k ß
R
>B =
4
7
k ß
>ß=
1 0 0
C
8
F
and
' ß = ° - P > fr
=R = L
=
resulting from C , C , and C , respectively. Note that R has to be taken into account in evaluating/pj. Hence, estimate the value of the lower 3-dB frequency f . c l
(a) Find the dc collector current of the transistor. (b) Find g and r . (c) Neglecting r , find the midband voltage gain from base to collector (neglect the effect of R ). (d) Use the gain obtained in (c) to find the component ofR that arises as a result of R . Hence find R . (e) Find the overall gain at midband. (f) Find C . (g) Find//,.
5 . 1 5 3 A particular small-geometry BJT h a s / of 5 GHz and C„ = 0.1 pF when operated at l = 0.5 mA. What is C„ in this situation? Also, find g . For Q = 150, find r„ and/^. r
c
m
5 . 1 5 4 For a BJT whose unity-gain bandwidth is 1 GHz and Po = 200, at what frequency does the magnitude of h become 20? What isf ?
model and the analysis shown in Fig. 5.72. Let R > R r < R, R > , g R' > 1, and g R' C^ > C . sig
sig
r %
m
L
m
n
L
m
K
B
Under these conditions, show that: (a) the midband gain A = -0(R' (b) the upper 3-dB frequency f„ = (c) the gain-bandwidth product A f M
/R ). X/ilnC^Ri). s \ /(2izC^R^).
L
5 . 1 6 5 Consider the circuit of Fig. P5.159. For R = 10 kQ, R = R /IR =lO k Q , r = 100 Q , r = 1 k Q , ft = 100, and R = 1 k Q , what is the ratio C /C that makes their contributions to the determination off equal?
in
2
x
E
n
E
ci
L
* 0 5 . 1 6 6 For the common-emitter amplifier of Fig. P5.166, neglect r and r , and assume the current source to be ideal. x
a
Vcc
A
+ 1.5V n
fe
p
l
iB
sig
M H
a
B
B
x
E
0 5 . 1 6 4 For the amplifier described in Problem 5.163, design the coupling and bypass capacitors for a lower 3-dB frequency of 100 Hz. Design so that the contribution of each of C i and C to determining/i is only 5%. C
B
T
a
Ag
80
m
c
E
L
B
If the device is operated at I = 0.2 mA, what does its f become?
5 3 9
Evaluate this approximate value of the gain-bandwidth product for the case R = 25 k Q and = 1 pF. Now, if the transistor' is biased at I = 1 mA and has d = 100, find the midband gain and f for the two cases R' = 25 k Q and R' = 2.5 k Q . On the same coordinates, sketch Bode plots for the gain magnitude versus frequency for the two cases. W h a t / is obtained when the gain is unity? What value of R' corresponds? sig
* 5 . 1 5 5 For a sufficiently high frequency, measurement of the complex input impedance of a BJT having (ac) grounded emitter and collector yields a real part approximating r . For what frequency, defined in terms of co , is such an estimate of r good to within 10% under the condition that r
B
x
x
!t
p
* 5 . 1 5 6 Complete the table entries above fortransistors (a) through (g), under the conditions indicated. Neglect r . x
c
H
H
L
5 . 1 5 9 Consider the common-emitter amplifier of Fig. P5.159 under the following conditions: R „ = 5 kQ, R = 33 kQ, R = 22 kQ, R = 3.9 kQ, R = 4.7 kQ° R = 5.6 kQ, V = 5 V. The dc emitter current can be shown to be I = 0.3 mA, at which B = 120, r = 300 kQ, and r = 50 Q. Find the input resistance R and the midband gain A . If the transistor is specified to h a v e / = 700 MHz and = 1 pF, find the upper 3-dB frequency f . si
E
SECTION 5 . 9 : FREQUENCY RESPONSE
t
c
L
2
cc
FIGURE P 5 . 1 6 1
E
OF THE COMMON-EMITTER AMPLIFIER
0
5 . 1 5 7 A designer wishes to investigate the effect of changing the bias current I on the midband gain and high-frequency response of the CE amplifier considered in Example 5.18. Let I be doubled to 2 mA, and assume that fi and f remain unchanged at 100 and 800 MHz, respectively. To keep the node voltages nearly unchanged, the designer reduces R and R by a factor of 2, to 50 k Q and 4 k Q , respectively. Assume r = 50 Q, and recall that V = 100 V and that remains constant at 1 pF. As before, the amplifier is fed with a source having R = 5 kQ. and feeds a load R = 5 k Q . Find the new values of A , f„, and the gain-bandwidth product, \A \f . Comment on the results. Note that the price paid for whatever improvement in performance is achieved is an increase in power. By what factor does the power dissipation increase? 0
L
L
B
x
in
M
r
H
V
A
x
A
e
K
K
B
c
x
L
M
M
(a) Derive an expression for the midband gain. (b) Derive expressions for the break frequencies caused by C and C . (c) Give an expression for the amplifier voltage gainA(i). (d) For R = R = R = 10 kQ, B = 100, and / = 1 mA, find the value of the midband gain. (e) Select values for C and C to place the two break frequencies a decade apart and to obtain a lower 3-dB frequency of 100 Hz while minimizing the total capacitance. (f) Sketch a Bode plot for the gain magnitude, and estimate the frequency at which the gain becomes unity. (g) Find the phase shift at 100 Hz. E
c
sig
c
L
E
A
sig
FIGURE P 5 . 1 6 6
0
t
r
cc
T
» 5 . 1 6 2 Refer to Fig. P5.162. Utilizing the BJT highfrequency hybrid-^ model with r = 0 and r = °°, derive an expression for Z (s) as a function of r and C . Find the frequency at which the impedance has a phase angle of 45° for the case in which the BJT h a s / = 400 MHz and the bias current is relatively high. What is the frequency when the bias current is reduced so that C — C„? Assume cc= 1.
H
c
5 . 1 6 7 The BJT common-emitter amplifier of Fig. P5.167 includes an emitter degeneration resistance R . e
* 5 . 1 5 8 The purpose of this problem is to investigate the high-frequency response of the CE amplifier when it is fed with a relatively large source resistance R . Refer to the amplifier in Fig. 5.71(a) and to its high-frequency equivalent-circuit
FIGURE P 5 . 1 6 2
iig
FIGURE P 5 . 1 5 9
x
5 . 1 6 3 For the amplifier in Fig. P5.159, whose component values were specified in Problem 5.159, let C = C = 1 AiF, and C = 10 pF. Find the break frequencies f , f , a n d / c l
E
(a) Assuming a = 1, neglecting r and r , and assuming the current source to be ideal, derive an expression for the smallsignal voltage gain A{s)= V /V that applies in the midband and the low frequency band. Hence find the midband gain A and the lower 3-dB frequency f .
P1
C2
P2
P 3
0
M
0
sig
L
CHAPTER 5
(b) Show that including R reduces the magnitude of A by a certain factor. What is this factor? (c) Show that including R reduces f by the same factor as in (b) and thus one can use R to trade-off gain for bandwidth. (d) For / = 1 mA, R = 10 kQ, and C = 100 jiV, find |A | and f with R = 0. Now find the value of R that lowers f by a factor of 5. What will the gain become? e
M
e
L
e
c
L
PROBLEMS
B I P O L A R J U N C T I O N T R A N S I S T O R S (BJTs)
E
e
M
e
L
Vcc
(b) With the input high and the transistor saturated, find the power dissipated in the inverter, neglecting the power dissi pated in the base circuit. (c) Use the results of (a) and (b) to find the average power dissipation in the inverter. D 5 . 1 7 0 Design a transistor inverter to operate from a 1.5-V supply. With the input connected to the 1.5-V supply through a resistor equal to R , the total power dissipated should be 1 mW and forced B should be 10. Use V = 0.7 V and V = 0.2 V c
BE
C£sat
5 . 1 7 1 For the circuit in Fig. P5.171, consider the application of inputs of 5 V and 0.2 V to X and Fin any combination, and find the output voltage for each combination. Tabulate your results. How many input combinations are there? What happens when any input is high? What happens when both inputs are low? This is a logic gate that implements the NOR function: Z = X + Y. (This logic-gate structure is called, historically, Resistor-Transistor Logic (RTL)). +5 V
:ikQ -ov
z
10 k Q y / o-AA/SHôx
FIGURE P 5 . 1 6 7
10 k Q c—VW-Tßy
SECTION 5 . 1 0 : THE BASIC BJT DIGITAL LOGIC INVERTER 5 . 1 6 8 Consider the inverter circuit in Fig. 5.74. In Exercise 5.53, the following expression is given for V when the inverter is driving N identical inverters:
FIGURE P 5 . 1 7 1
0H
Vr>n =
V
Vr V -R 'R + R /N R
rr
r
C
B
5 . 1 7 2 Consider the inverter of Fig. 5.74 with a load capacitor C connected between the output node and ground. We wish to find the contribution of C to the low-to-high delay time of the inverter, t . (For the formal definition of inverter delays, refer to Fig. 1.35.) Toward that end, assume that prior to t = 0, the transistor is on and saturated and v = VOL VCESXL- Then, at t = 0, let the input fall to the low level, and assume that the transistor turns off instantaneously. Note that neglecting the turn-off time of a saturated transistor is an unrealistic assumption, but one that will help us concentrate on the effect of C. Now, with the transistor cut off, the capacitor will charge through R , and the output voltage will rise exponentially from V = V* to V = V . Find an expression for v (t). Calculate the value of t , which in this case is the time for v to rise to | ( V + V ). Use V = 5 V, F = 0.2 V, R = 1 k Q , and C = 10 pF. (Hint: The step response of RC circuits is reviewed in Section 1.7 and in greater detail in Appendix D.) PLH
For the same component values used in the analysis in the text (i.e., V = 5 V, R = 1 kQ, R = 10 kQ, and V = 0.7 V), find the maximum value of N that will still guarantee a high noise margin, NM , of at least 1 V. Assume B = 50 and V 0.2 V. cc
c
B
BE
H
CEs!&
5 . 1 6 9 The purpose of this problem is to find the power dissipation of the inverter circuit of Fig. 5.74 in each of its two states. Assume that the component values are as given in the text (i.e., V = 5 V, R = 1 kQ, R = 10 kQ, and V = 0.7 V). cc
c
B
BB
(a) With the input low at 0.2 V, the transistor is cut off. Let the inverter be driving 10 identical inverters. Find the total current supplied by the inverter and hence the power dissipated in R . c
0
=
c
0L
C£sat
0H
0
0
c
cc
PLH
0H
0L
cc
c £ s a t
# 5 , 1 7 3 Consider the inverter circuit of Fig. 5.74 with a load capacitor C connected between the output node and round. We wish to find the contribution of C to the high-tolow delay time of the inverter, t . (For the formal definition of the inverter delays, refer to Fig. 1.35.) Toward that end, assume that prior to t = 0, the transistor is off and v = V = V* . Then, at t = 0, let the input rise to the high level, and assume that the transistor turns on instantaneously. Note that neglecting the delay time of the transistor is unrealistic but will help us concentrate on the effect of the load capacitance C. Now, because C cannot discharge instantaneously, the transistor cannot saturate immediately. Rather, it will operate in the active mode, and its collector will supply a constant current PHL
0
cc
0H
o f
/R
•
i 5 4 1
F i n d
ß(Vcc~ V E) Bdie Thevenin equivalent circuit for discharging the capacitor, and show that the voltage will fall exponentially, starting at V and heading toward a large negative voltage of [V -ß(V -V )R /R ]. Find an expression for v (f). This exponential discharge will stop when v reaches V = V and the transistor saturates. Calculate the value of t , which in this case is the time for v to fall to \( V + V ). Use V = 5 V, VcEsat 0.2 V, V = 0.7 V, R = 10 kQ, R = 1 kQ, ß = 50, and C = 10 pF. If you have solved Problem 5.172, compare the value of t to that of t found there, and find the inverter delay, t . (Hint: The step response of RC circuits is reviewed in Section 1.7 and in greater detail in Appendix E). B
cc
cc
cc
BE
C
B
0
0
0L
C£sat
PHL
0H
0L
0
cc
BE
B
c
PHL
PLH
P
"•IS'
A N A L O G A N D DIGITAL INTEGRATED CIRCUITS CHAPTER 6
.
....
cyl
_
Single-Stage Integrated-Circuit Amplifiers 5 4 5
••••I
CHAPTER 7 Differential and Multistage Amplifiers 6 8 7
CHAPTER 8 Feedback 7 9 1
CHAPTER 9 fr
Op-Amp and Data-Converter Circuits 871
CHAPTER 10 CMOS Logic Circuits 9 4 9
INTRODUCTION Having studied the major electronic devices (the M O S F E T a n d the B J T ) and their basic circuit applications, w e are n o w r e a d y to consider t h e design of m o r e c o m p l e x analog and digital integrated circuits a n d s y s t e m s . T h e five chapters of Part TJ are intended for this p u r p o s e . T h e y p r o v i d e a carefully selected set of topics suitable for a second course in electronics. N e v e r t h e l e s s , t h e flexibility inherent in this b o o k should permit replacing s o m e of the topics i n c l u d e d with a selection from t h e special topics presented in Part III. A s well, if desired, C h a p t e r 10 on C M O S logic circuits can b e studied at the b e g i n n i n g of the course. Study of Part II assumes k n o w l e d g e of M O S F E T and B I T characteristics, models, and basic applications (Chapters 4 and 5 ) . T o r e v i e w a n d consolidate this material and differences b e t w e e n the t w o devices, Section 6.2 with its three tables ( 6 . 1 - 6 . 3 ) is a must read. T h e r e m a i n d e r of C h a p t e r 6 p r o v i d e s a systematic study of the circuit building b l o c k s utilized in the design of a n a l o g I C s . In each case, b o t h low-frequency and high-frequency operations are considered. C h a p t e r 7 continues this study, con centrating o n t h e m o s t w i d e l y u s e d configuration in a n a l o g I C design, the differential pair. It concludes w i t h a section on m u l t i s t a g e amplifiers. In b o t h chapters, M O S F E T circuits are p r e s e n t e d first, s i m p l y b e c a u s e the M O S F E T is n o w t h e device that is used in over 9 0 % of integrated circuits. B i p o l a r transistor circuits are p r e s e n t e d with the same d e p t h b u t p r e s e n t e d s e c o n d and, on occasion, m o r e briefly. A formal study of the pivotal topic of f e e d b a c k is p r e s e n t e d in C h a p t e r 8. S u c h a study is essential for the p r o p e r application of f e e d b a c k in the design of amplifiers, to effect desirable properties such as m o r e precise gain value, and to avoid p r o b l e m s such as instability. T h e analog material of Part II is integrated together in Chapter 9 in the study of o p - a m p circuits. Chapter 9 also presents an introduction to analog-to-digital and digital-to-analog converters, and thus acts as a bridge to the study of C M O S digital logic circuits in Chapter 10. H e r e again w e concentrate on C M O S because it represents the technology in w h i c h the vast majority of digital systems are implemented. T h e s e c o n d course, b a s e d on Part II, is i n t e n d e d to p r e p a r e t h e r e a d e r for the p r a c tice of electronic design, and, if desired, to p u r s u e m o r e a d v a n c e d courses o n analog and digital I C design.
•Hi
••111
Single-Stage IntegratedCircuit Amplifiers Introduction
545
6.8
6.1
IC Design Philosophy
6.2
C o m p a r i s o n of t h e M O S F E T and the BJT
The Cascode Amplifier
546 6.9
613
The C S a n d C E Amplifiers w i t h S o u r c e (Emitter)
547
Degeneration 6.3
Current Mirrors, and CurrentSteering Circuits 6.4
High-Frequency
Response571
6.7
H i g h - F r e q u e n c y R e s p o n s e of
The Common-Gate and C o m m o n - B a s e Amplifiers with Active Loads
Pairings
641
Performance
582
the C S a n d C E Amplifiers
6.11 S o m e Useful Transistor
with Improved
Common-Emitter Amplifiers
6.6
635
6.12 Current-Mirror Circuits
The Common-Source and
with Active Loads
6.10 T h e S o u r c e a n d Emitter Followers
562
General Considerations 6.5
629
IC Biasing—Current Sources,
588
649
6.13 S P I C E Simulation Examples
656
Summary
665
Problems
666
600
INTRODUCTION Having studied t h e t w o m a j o r t r a n s i s t o r t y p e s , t h e M O S F E T a n d t h e B J T , a n d their b a s i c discrete-circuit amplifier c o n f i g u r a t i o n s , w e are n o w r e a d y to b e g i n t h e s t u d y of i n t e g r a t e d circuit amplifiers. T h i s c h a p t e r a n d t h e n e x t a r e d e v o t e d to t h e d e s i g n of t h e basic b u i l d i n g blocks of I C a m p l i f i e r s . In this c h a p t e r , w e b e g i n w i t h a b r i e f s e c t i o n on t h e d e s i g n p h i l o s o p h y of i n t e g r a t e d circuits, and h o w it differs f r o m t h a t of d i s c r e t e circuits. T h r o u g h o u t this c h a p t e r , M O S a n d
CHAPTER 6
6.2
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
b i p o l a r circuits are p r e s e n t e d side-by-side, w h i c h allows a certain e c o n o m y in presentation
technology. A s m e n t i o n e d earlier, C M O S is currently t h e m o s t w i d e l y u s e d I C t e c h n o l o g y
and, m o r e importantly, provides an opportunity to c o m p a r e a n d contrast the t w o circuit types.
for b o t h a n a l o g a n d digital as w e l l as c o m b i n e d analog a n d digital (or m i x e d - s i g n a l ) applica
T o w a r d that end, Section 6.2 p r o v i d e s a c o m p r e h e n s i v e c o m p a r i s o n of the attributes of the
tions. N e v e r t h e l e s s , bipolar integrated circuits still offer m a n y exciting opportunities to t h e
t w o transistor types. This should serve b o t h as a r e v i e w as w e l l as a g u i d e to very interesting
analog design engineer. This is especially the case for general-propose circuit p a c k a g e s , such
similarities a n d differences b e t w e e n the t w o d e v i c e s .
547
as h i g h - q u a l i t y o p a m p s that are i n t e n d e d for a s s e m b l y on printed-circuit (pc) b o a r d s (as
Following the study of IC biasing, the various configurations of single-stage I C amplifiers
o p p o s e d to b e i n g part of a s y s t e m - o n - c h i p ) . A s well, bipolar circuits c a n p r o v i d e m u c h
are presented. This material builds o n t h e study of basic discrete-amplifier configurations in
higher o u t p u t currents a n d are favoured for certain applications, such as in the a u t o m o t i v e
Sections 4.7 a n d 5.7.
industry, for their h i g h reliability u n d e r severe e n v i r o n m e n t a l c o n d i t i o n s . Finally, b i p o l a r
In addition to classical single-stage amplifiers, w e also study s o m e configurations that
>'*':
circuits c a n b e c o m b i n e d with C M O S in i n n o v a t i v e and exciting w a y s .
utilize t w o amplifying transistors. T h e s e " c o m p o u n d c o n f i g u r a t i o n s " are u s u a l l y treated as single-stage amplifiers (for r e a s o n s that will b e c o m e clear later). Current mirrors and current-source circuits play a major role in the design of I C amplifiers,
6.2 COMPARISON OF THE MOSFET AND THE BJT
ff
w h e r e they serve both as biasing and load elements. For this reason, w e return to the subject of c u r r e n t m i r r o r s later in the c h a p t e r a n d c o n s i d e r s o m e of t h e i r a d v a n c e d ( a n d indeed, ingenious) forms. A l t h o u g h C M O S circuits are the m o s t w i d e l y u s e d at present, t h e r e are applications in
In this section w e p r e s e n t a c o m p a r i s o n of t h e characteristics of t h e t w o major electronic devices: t h e M O S F E T a n d the B J T . T o facilitate this c o m p a r i s o n , typical values for the important p a r a m e t e r s of the t w o devices are first presented.
w h i c h t h e a d d i t i o n of bipolar transistors c a n result in superior p e r f o r m a n c e . Circuits that c o m b i n e M O S a n d bipolar transistors, in a t e c h n o l o g y k n o w n as B i M O S or B i C M O S , are p r e s e n t e d at a p p r o p r i a t e locations t h r o u g h o u t the chapter. T h e c h a p t e r c o n c l u d e s with S P I C E simulation e x a m p l e s .
6.2.1 Typical Values of MOSFET Parameters Typical v a l u e s for t h e i m p o r t a n t p a r a m e t e r s of N M O S a n d P M O S transistors fabricated in a n u m b e r of C M O S p r o c e s s e s are s h o w n in T a b l e 6 . 1 . E a c h p r o c e s s is characterized by the miiiimum allowed channel length, L^;
6.1 IC DESIGN PHILOSOPHY v._
thus, for example, in a 0.18-/im process, the smallest
transistor h a s a c h a n n e l length L = 0.18 fjm. T h e technologies p r e s e n t e d in T a b l e 6.1 are in descending order of c h a n n e l length, w i t h that h a v i n g the shortest c h a n n e l length b e i n g the most m o d e r n . A l t h o u g h the 0.8-/im process is n o w obsolete, its data are i n c l u d e d to s h o w
Integrated-circuit fabrication t e c h n o l o g y ( A p p e n d i x A ) p o s e s constraints o n — a n d provides
trends in the values of various parameters. It should also b e m e n t i o n e d that although Table 6.1
o p p o r t u n i t i e s t o — t h e circuit designer. T h u s , w h i l e c h i p - a r e a c o n s i d e r a t i o n s dictate that
stops at the 0.18-/im process, at the time of this writing (2003), a 0.13-/im fabrication p r o c e s s is
large- a n d e v e n m o d e r a t e - v a l u e resistors are to b e avoided, c o n s t a n t - c u r r e n t s o u r c e s are
c o m m e r c i a l l y available a n d a 0 . 0 9 - ^ m p r o c e s s is in the a d v a n c e d stages of d e v e l o p m e n t .
readily available. L a r g e capacitors, s u c h as t h o s e w e u s e d in Sections 4 . 7 and 5.7 for signal
The 0.18-jUm p r o c e s s , however-fis-currently the m o s t p o p u l a r a n d the o n e for w h i c h data are
c o u p l i n g a n d b y p a s s , are not available to b e used, e x c e p t p e r h a p s as c o m p o n e n t s external to
widely available. A n important caution, however, is in order: T h e data presented in Table 6.1
t h e I C c h i p . E v e n then, the n u m b e r of s u c h capacitors h a s t o b e k e p t to a m i n i m u m ; other
do not pertain to any particular c o m m e r c i a l l y available p r o c e s s . A c c o r d i n g l y , t h e s e generic
w i s e the n u m b e r of chip terminals and h e n c e its cost increase. Vcr\ small capacitors, in the
data are not i n t e n d e d for u s e in an actual I C design; rather, they s h o w t r e n d s and, as w e shall
picofarad and fraction of a picofarad r a n g e , h o w e v e r , are e a s y to fabricate in I C M O S tech
see, help to illustrate d e s i g n trade-offs as w e l l as e n a b l e u s to w o r k out d e s i g n e x a m p l e s a n d
n o l o g y a n d c a n b e c o m b i n e d with M O S amplifiers a n d M O S switches to realize a w i d e
problems with p a r a m e t e r values that are as realistic as possible.
r a n g e of signal p r o c e s s i n g functions, b o t h a n a l o g ( C h a p t e r 12) a n d digital ( C h a p t e r 11). A s a general rule, in designing I C M O S circuits, o n e should strive to realize as m a n y of the functions required as possible using M O S transistors only and, w h e n needed, small M O S
TABLE 6.1
Typical Values of CMOS Device Parameters
capacitors. M O S transistors can b e sized; that is, their W a n d L values can b e selected, to fit a wide range of design requirements. Also, arrays of transistors can be.matched (or, m o r e generally, m a d e to h a v e desired size ratios) to realize such useful circuit building blocks as current mirrors. A t this j u n c t u r e , it is useful to m e n t i o n that t o p a c k a larger n u m b e r of d e v i c e s o n the
0.8/an Parameter
(nm)
s a m e I C c h i p , t h e trend h a s b e e n to r e d u c e the d e v i c e d i m e n s i o n s . A t t h e t i m e of this writing
tox
( 2 0 0 3 ) , C M O S p r o c e s s t e c h n o l o g i e s c a p a b l e of p r o d u c i n g d e v i c e s w i t h a 0.1 -jim m i n i m u m
C (fF/|mi )
c h a n n e l l e n g t h are in u s e . S u c h small d e v i c e s n e e d to o p e r a t e with d c v o l t a g e supplies close
^(cm /V>s)
2
m
2
c h a l l e n g e s to t h e circuit designer. F o r i n s t a n c e , s u c h M O S transistors m u s t b e o p e r a t e d with
Vio(V)
overdrive voltages of only 0.2 V or so. In our study of M O S amplifiers, w e will m a k e frequent
V (V)
c o m m e n t s o n such issues.
|V '|(V//im)
T h e M O S - a m p l i f i e r circuits that w e shall study will b e d e s i g n e d a l m o s t entirely u s i n g M O S F E T s of b o t h p o l a r i t i e s — t h a t is, N M O S a n d P M O S — a s are readily available in C M O S
Dfl
A
C (fVlLim) ov
0.25 urn
0.18 //.m
NMOS
PMOS
NMOS
PMOS
15
15
9
9
6
6
4
3.8
3.8
5.8
5.8
8.6
2.3 550 127
to 1 V . W h i l e l o w - v o l t a g e o p e r a t i o n c a n h e l p to r e d u c e p o w e r dissipation, it p o s e s a h o s t of
0.5 /jm
0.7
2.3 250
500
58
190
-0.7
5
5
25
20
0.2
0.2
0.7 3.3 20 0.4
NMOS
180
460
68
267
-0.8 3.3 10 0.4
PMOS
NMOS
160
450
93
387 0.48
PMOS
4 8.6 100 86 -0.45
0.43
-0.62
2.5
2.5
1.8
1.8
5
6
5
6
0.3
0.3
0.37
0.33
548
1
1
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.2
A s indicated in T a b l e 6 . 1 , t h e trend h a s b e e n t o r e d u c e t h e m i n i m u m allowable channel length. T h i s trend h a s b e e n m o t i v a t e d b y t h e desire t o p a c k m o r e transistors o n a chip as well as t o operate at higher speeds or, in analog terms, over w i d e r b a n d w i d t h s . O b s e r v e that the o x i d e t h i c k n e s s , t , scales d o w n with t h e c h a n n e l length, reaching 4 nm for t h e 0.18-/im process. S i n c e t h e o x i d e capacitance C is inversely proportional to t vve see that C increases as the t e c h n o l o g y scales d o w n . T h e surface mobility pi decreases as the t e c h n o l o g y m i n i m u m - f e a t u r e size is decreased, a n d p. decreases m u c h faster than pi . A s a result, t h e ratio of pi t o \i h a s b e e n decreasing with each generation of technology, falling from about 0.5 for older technologies t o 0.2 or so for the n e w e r ones. Despite the reduction of \x a n d /i , t h e transconductance parameters k' = fi C a n d k' = p~ C h a v e been steadily increasing. A s a result, m o d e m short-channel devices achieve required levels of bias currents at lower overdrive voltages. A s well, they achieve higher transconductance, a major advantage. A l t h o u g h t h e m a g n i t u d e s of t h e threshold voltages V a n d V h a v e b e e n decreasing with L from about 0 . 7 - 0 . 8 V to 0 . 4 - 0 . 5 V , t h e reduction h a s n o t b e e n as large as that of t h e p o w e r supply V - T h e latter h a s b e e n r e d u c e d dramatically, from 5 V for older technologies to 1.8 V for t h e 0.18-/im p r o c e s s . T h i s reduction h a s b e e n necessitated b y t h e need to keep the electric fields in the smaller devices from reaching very high values. Another reason for r e d u c i n g V is to k e e p p o w e r dissipation as l o w as p o s s i b l e g i v e n that t h e I C chip n o w h a s a m u c h larger n u m b e r of t r a n s i s t o r s . T h e fact that in m o d e r n short-channel C M O S processes'\V,\ h a s b e c o m e a m u c h larger proportion of the power-supply voltage poses a serious challenge to the circuit design engineer. R e c a l l i n g that | V | = |V,\ + \V \, w h e r e V is t h e overdrive voltage, t o k e e p \V \ r e a s o n a b l y small, [ V \ for m o d e r n t e c h n o l o g i e s is usually in t h e r a n g e of 0.2 V to 0.3 V. To appreciate this point further, recall that to operate a M O S F E T in the saturation region, \ V \ m u s t e x c e e d | V \; thus, to b e able t o h a v e a n u m b e r of devices stacked b e t w e e n the powersupply rails in a regime in which V is only 1.8 V or lower, w e need t o k e e p \ V \ as low as possible. W e will shortly see, however, that operating at a l o w \ V \ h a s s o m e drawbacks. Another significant though undesirable feature of modern submicron C M O S technologies is that the channel length modulation effect is very pronounced. A s a result, V has been steadily decreasing, w h i c h c o m b i n e d w i t h t h e decreasing values of L h a s caused t h e Early voltage V = V' L to b e c o m e very small. Correspondingly, short-channel M O S F E T s exhibit low output resistances. F r o m o u r study of the M O S F E T high-frequency equivalent circuit m o d e l in the saturation m o d e in Section 4.8 and the high-frequency response of the c o m m o n - s o u r c e amplifier in Section 4.9, w e k n o w that t w o major M O S F E T capacitances are C a n d C . W h i l e C has an overlap component, C is entirely an overlap capacitance. B o t h C and the overlap component of C are almost equal and are denoted C . T h e last line of T a b l e 6.1 provides the value of C per micron of gate width. Although t h e normalized C h a s been staying m o r e or less constant with the reduction in L , w e will shortly see that the shorter devices exhibit much higher operating speeds and w i d e r amplifier bandwidths than the longer devices. Specifically, w e will, for example, see that f for a 0 . 2 5 - p n N M O S transistor can b e as high as 10 GHz.
TABLE: O.JJ
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
Typical Parameter Values for BJTs' Standard High-Voltage Process
Advanced Low-Voltage Process
ox
ox
ox
p
p
n
n
H
0X
p
p
tn
"P"
A (pra)
500
(A)
5xl0~
E
n
n
p
Parameter
l
/{(A/A) (V)
v
Lateral pop
900 1 5
2xl0~
Lateral pnp
npn
2 1 5
6xl0~
.
2
1 8
6xl0"
1 8
200
50
100
50
130
50
35
30
30 ns
10 ps
650 ps
5fF
14 fF
ox
tp
T
0.35 ns
C.
IpF
e0
¿1,
m i n
r
0.3 pF
(Q)
200
0.3 pF IpF
5fF
300
15 fF
400
200
DD
'ADAPTED FROM GRAY ET AL. (2000); SEE BIBLIOGRAPHY.
DD
1
c s
0V
ov
GS
ov
DS
ov
DD
0V
0 V
A
A
A
gs
gd
gd
gs
gd
gs
ov
ov
standard, old p r o c e s s , k n o w n as t h e " h i g h - v o l t a g e p r o c e s s " ; a n d a n a d v a n c e d , m o d e r n p r o cess, referred to as a " l o w - v o l t a g e p r o c e s s . " F o r e a c h process w e s h o w the p a r a m e t e r s of t h e standard npn transistor a n d those of a special t y p e of pnp transistor k n o w n as a l a t e r a l (as opposed to v e r t i c a l as in the npn c a s e ) p n p (see A p p e n d i x A ) . In this r e g a r d w e should m e n tion that a major d r a w b a c k of standard bipolar integrated-circuit fabrication processes h a s been the lack of pnp transistors of a quality e q u a l t o that of the npn devices. Rather, there are a number of pnp i m p l e m e n t a t i o n s for w h i c h t h e lateral pnp is t h e m o s t e c o n o m i c a l to fabricate. Unfortunately, h o w e v e r ^ a s should b e e v i d e n t from T a b l e 6.2, t h e lateral pnp h a s characteristics that are m u c h inferior to those of the npn. N o t e in particular t h e l o w e r value of ¡3 and the m u c h larger value of the forward transit t i m e T that determines the e m i t t e r - b a s e diffusion capacitance C a n d , h e n c e , t h e transistor s p e e d of operation. T h e data in T a b l e 6.2 can b e used to s h o w that the unity-gain frequency of the lateral pnp is t w o orders of m a g n i t u d e lower than that of the npn transistor fabricated in t h e s a m e process. Another important difference between the lateral pnp and the corresponding npn transistor is the value of collector current at which t h e h ¡3 values reach their m a x i m u m s : F o r the high-voltage process, for example, this current is in t h e tens of microamperes r a n g e for the pnp a n d in the milliampere r a n g e for the npn. O n t h e positive side, t h e p r o b l e m of t h e lack of high-quality pnp transistors h a s spurred analog circuit designers t o c o m e u p with highly innovative circuit topologies that either m i n i m i z e the u s e of pnp transistors or m i n i m i z e t h e dependence of circuit performance on that of the pnp. W e shall encounter s o m e of these ingenious circuits later in this book. f
de
ov
m i n
T
6.2.2 Typical Values of IC BJT Parameters Table 6.2 provides typical values for the major parameters that characterize integrated-circuit bipolar transistors. D a t a are provided for devices fabricated in t w o different processes: the
T h e dramatic reduction in device size achieved in t h e a d v a n c e d low-voltage process should b e evident from Table 6.2. A s a result, the scale current I also h a s been reduced b y about three orders of magnitude. H e r e w e sfrbuld note that the b a s e width, W , achieved in the advanced process is o n the order of 0.1 pirn, as compared to a few microns in the standard highvoltage p r o c e s s . N o t e also t h e d r a m a t i c increase in speed; for the l o w - v o l t a g e npn transistor, ?F = 10 p s as o p p o s e d to 0.35 n s in the high-voltage process. A s a result, f for the m o d e r n npn transistor is 10 G H z to 2 5 G H z , as c o m p a r e d t o the 4 0 0 M H z to 6 0 0 M H z achieved in the high-voltage p r o c e s s . A l t h o u g h t h e Early voltage, V , for t h e m o d e r n process is l o w e r than its value in the old high-voltage process, it is still reasonably high at 3 5 V . Another feature of the advanced p r o c e s s — a n d one that is not obvious from Table 6.2—is that ¡3 for the npn peaks at a collector current of 5 0 piA or so. Finally, n o t e that as t h e n a m e implies, npn transistors s
B
T
A
1
At the present time, chip power dissipation has become a very serious issue, with some of the recently reported ICs dissipating as much as 100 W. As a result, an important current area of research concerns what is termed "power-aware design."
l'^
549
5 5 0
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.2
fabricated in t h e low-voltage process b r e a k d o w n at collector-emitter voltages of 8 V, as c o m p a r e d t o 5 0 V or so for the high-voltage process. T h u s , while circuits designed with the standard high-voltage process utilize p o w e r supplies of + 1 5 V (e.g., in commercially available op a m p s of the 7 4 1 type), the total power-supply voltage utilized with m o d e m bipolar devices is 5 V (or even 3.3 V to achieve compatibility with s o m e of the submicron C M O S processes)
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
NMOS
55'
npn
Low-Frequency T Model
1 XL
6.2.3 Comparison of Important Characteristics
Transconductance
TABLE 6.3
Comparison of
the
MOSFETand
the
Bo-
G<
T a b l e 6.3 p r o v i d e s a compilation of the important characteristics of the N M O S and the npn transistors. T h e material is presented in a m a n n e r that facilitates comparison. In the following, w e p r o v i d e c o m m e n t s o n the various items in T a b l e 6.3. A s well, a number of numerical e x a m p l e s and exercises are p r o v i d e d t o illustrate h o w the wealth of information in Table 6.3 c a n b e p u t to u s e . Before p r o c e e d i n g , note that t h e P M O S a n d the pnp transistors can be c o m p a r e d in a similar w a y .
em = V ( V y / 2 ) 0
9m
BJT
g =
(rlnC )(jßv V
m
NMOS
ox
Circuit Symbol
2(p Ç )[ n
Output Resistance
vs
r
G
a
Intrinsic Gain
(1) Forward-bias EBJ:
(1) Induce a channel:
GS
••
=
V /(V /2)
A
A
0
v E*V ; B
BEm
= 0.5V
A
V
Ar, = 0
(2) Reverse-bias CBJ:
(2) Pinch-off channel at drain:
r
a
A
0
0V
=
V /I
=
V /V
A
A
C
T
r
V
BEOA
D
^0 ^ 9m o
o v
T
ö
VÂ L
= V /I
2
GS > V„ V, = 0.5 - 0.7 V = V+ v
U
Let v
| ] /
ox
+
+
ta +
To Operate in the Active Mode, Two Conditions Have To Be Satisfied
0
npn
1
L
— v V1J2H„C WL 01C
A
n
VBC
v
GD < t
V
v
DS Z ov>
Current-Voltage Characteristics in the Active Region
V,ov
v >0.3
0.2-0.3 V
CE
D
JÏD
G S
-V )'[l +
V
Input Resistance with Source (Emitter) Grounded
V
CE
U
r'»C„?(W
1
BCOD
= 0AW
or equivalently,
or equivalently, V
V
DS
(
VY
High-Frequency Model
Go-
DS
-OD :C..
i
G
Low-Frequency Hybrid-^ Model
= 0
i = B
OD
Bo-VW
*
»
;
"*
•
~ °
c
< J
i /ß c
Bo
( Continued)
5 5 2
CHAPTER 6 S I N G L E - S T A G E I N T E G R A T E D - C I R C U I T A M P L I F I E R S
6.2
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
with its counterpart in the M O S F E T , the aspect ratio W/L. M O S F E T devices can b e designed Comparison of t h e MOSFET and t h e BJT
(Continued)
with W/L ratios i n a w i d e r a n g e , such a s 0.1 t o 100. A s a result W/L i s a very significant
NMOS Capacitances
C
gs
=
M O S design p a r a m e t e r . L i k e A , it is also u s e d in current scaling, as w e shall see in t h e n e x t E
npn
section. C o m b i n i n g t h e p o s s i b l e r a n g e o f variation o f v
ox
ov
0
Y
and W/L, o n e c a n design M O S
transistors to operate o v e r an i r a n g e of four d e c a d e s or so.
^WLC +WL C
D
ox
T h e c h a n n e l - l e n g t h m o d u l a t i o n in t h e M O S F E T a n d t h e b a s e - w i d t h m o d u l a t i o n in t h e Cgd =
WL C 0V
C
je
0X
BJT are similarly m o d e l e d a n d give rise t o the d e p e n d e n c e o f i (i ) D
2C
=
jeO
o n v (v )
c
DS
and,
CE
hence, to the finite o u t p u t r e s i s t a n c e r in the active region. T w o i m p o r t a n t differences, h o w 0
CB
1
ever, exist. In the B J T , V is solely a p r o c e s s - t e c h n o l o g y p a r a m e t e r a n d d o e s n o t d e p e n d o n A
the dimensions of the B J T . I n t h e M O S F E T , the situation is quite different: V '= V L, A
A
where V is a process-technology p a r a m e t e r and L is the channel length used. Also, in m o d e r n A
Transition Frequency
fr
8
fr= J
submicron p r o c e s s e s , V is very l o w , resulting in V values m u c h l o w e r than the c o r r e s p o n d -
m
A
Jt
T
2n{C
~2K(C +C^) !C
+ C )
GS
2 For C
GS
> C
and C
GD
GS
=
For C >
C y and
N
-WLC ,
A
ing values for the B J T .
GD
The last, and perhaps m o s t important, difference between the current-voltage characteristics
C =C , N
DE
OX
of the t w o devices c o n c e r n s the i n p u t current into the control terminal: W h i l e the gate current f
2
Z ^ ^ o v
J T—
„ VnV
f
of the M O S F E T is practically zero a n d t h e i n p u t r e s i s t a n c e l o o k i n g into t h e gate i s practi-
T
J T
o
o
cally infinite, t h e B J T d r a w s b a s e current i that is p r o p o r t i o n a l to the collector current; that
2KW
2%L
B
B
is, i = ic/P-
T
n
ef i m 1 : e
b
a
s
e
B
Design Parameters ?D>
W Vov, L, —
I> C
V
r
, E (° A
B
E
current a n d the c o r r e s p o n d i n g finite i n p u t r e s i s t a n c e l o o k i n g
into the b a s e is a definite d i s a d v a n t a g e of the B J T in c o m p a r i s o n to the M O S F E T . Indeed, it
h)
is the infinite input r e s i s t a n c e of the M O S F E T that h a s m a d e p o s s i b l e a n a l o g a n d digital cirGood Analog Switch?
Yes, because the device is symmetrical,, and thus the i -v characteristics pass directly through the origin. D
DS
Operating Conditions
No, because the device is asymmetrical with an offset voltage V . *
cuit applications that are not feasible with the B J T . E x a m p l e s include d y n a m i c digital m e m o r y (Chapter 11) a n d s w i t c h e d - c a p a c i t o r filters ( C h a p t e r 12).
CEoif
A t the outset, n o t e that w e shall u s e a c t i v e m o d e or a c t i v e region
to d e n o t e b o t h t h e active m o d e of o p e r a t i o n of t h e B J T a n d the s a t u r a t i o n - m o d e of operation of t h e M O S F E T . T h e c o n d i t i o n s for o p e r a t i n g i n t h e a c t i v e m o d e are v e r y similar for t h e t w o devices: T h e e x p l i c i t t h r e s h o l d V of the M O S F E T h a s V T
BETM
F u r t h e r m o r e , for m o d e r n p r o c e s s e s , V
BEon
as its i m p l i c i t c o u n t e r p a r t in the BJT.
a n d V are a l m o s t equal.
b i a s i n g t h e C B J of t h e B J T . N o t e , h o w e v e r , that t h e a s y m m e t r y of t h e B J T results in BEON
ov
GS
D
t
A l s o , p i n c h i n g off t h e c h a n n e l of t h e M O S F E T at t h e drain e n d is v e r y similar to reverse and V
(a) For an N M O S transistor with W/L = 10 fabricated in the 0.18-jUm process whose data are given in Table 6.1, find the values of V and V required to operate the device at I = 100 piA. Ignore channel-length modulation.
V
BCM
being unequal, while in the symmetrical M O S F E T the operative threshold voltages at
the source and the drain ends of the c h a n n e l are identical (V ). Finally, for both the M O S F E T
(b) Find V for an npn transistor fabricated in the low-voltage process specified in Table 6.2 and operated at I = 100 pA. Ignore base-width modulation. BE
c
Solution
T
a n d t h e B J T to o p e r a t e in the active m o d e , t h e v o l t a g e across t h e d e v i c e (v , v ) m u s t be DS
CE
(a)
Current-Voltage Characteristics
T h e s q u a r e - l a w control characteristic, i - v D
M O S F E T s h o u l d b e contrasted w i t h t h e e x p o n e n t i a l control characteristic, i ~ v c
G S
B E
, in the
2
ID =
at least 0.2 V to 0.3 V . Substituting I
D
\iri C ù{~)y ov n
n
, of the
v a r y over a v e r y w i d e r a n g e (five d e c a d e s or m o r e ) w i t h i n t h e s a m e B J T . In t h e M O S F E T , a c h i e v e d in t h e s a m e d e v i c e is m u c h m o r e limited. T o a p p r e c i a t e this point
further, c o n s i d e r t h e parabolic relationship b e t w e e n i a n d v D
sion a b o v e that v
o
v
o v
ox
= 387 pA/V
1, x 387 x 10 x V 2 0.23 V
100
c
c
D
2
= 100 pA, W/L = 10, and, from Table 6.1, p C
B J T . O b v i o u s l y , the latter is a m u c h m o r e sensitive relationship, w i t h the result that i can the range of i
0
V,
ov •
r
Thus,
, a n d recall f r o m our discus-
is u s u a l l y k e p t in a n a r r o w r a n g e (0.2 V to 0.4 V ) .
Vs = V + V G
TN
OV
= 0.48 + 0.23 = 0.71 V
N e x t w e c o n s i d e r t h e effect o f t h e d e v i c e d i m e n s i o n s o n its c u r r e n t . F o r t h e bipolar t r a n s i s t o r t h e control p a r a m e t e r i s the area of the e m i t t e r - b a s e j u n c t i o n ( E B J ) , A , which
(b)
E
determines the scale current I . It c a n b e varied over a relatively n a r r o w range, such as 10 to 1. S
T h u s , w h i l e t h e emitter area can b e u s e d to a c h i e v e current scaling in a n I C (as w e shall see
Substituting I = 100 pA and, from Table 6.2, I = 6 x 1 0 c
s
in the next section in connection with the design of current mirrors) its n a r r o w r a n g e of varia0.025 In
tion r e d u c e s its significance as a d e s i g n p a r a m e t e r . T h i s is particularly so if w e c o m p a r e A
E
100 x 10" 6 x 10"
-18
- 1 8
A gives,
= 0.76 V
results in
R.-iAPTER 6
6.2
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
is inversely p r o p o r t i o n a l to the bias current. T h e difference in nature a n d m a g n i t u d e of y
between the t w o devices has already b e e n discussed.
Intrinsic G a i n
(a) For N M O S transistors fabricated in the 0.18-jUm technology specified in Table 6.1, find the range of I J, obtained for V ranging from 0.2 V to 0.4 V and W/L = 0.1 to 100. Neglect channel-length modulation, (b) If a similar range of current is required in an npn transistor fabricated in the low-voltage process specified in Table 6.2. find the corresponding change in its V .
T h e intrinsic gain A
0
of t h e B J T is t h e ratio of V , w h i c h is solely a p r o A
cess parameter (35 V to 130 V ) , and V , T
w h i c h is a p h y s i c a l p a r a m e t e r (0.025 V at r o o m
ov
temperature). T h u s A
BE
Ans. (a) r „ = 0.8 uA and I 4000:1 range, AV = 207 mV Dmi
= 3.1 m A for a range of about 4 0 0 0 : 1 ; (b) For I
Dmax
of a B J T is i n d e p e n d e n t of t h e d e v i c e j u n c t i o n area and of the operat-
is very different: T a b l e 6.3 p r o v i d e s three different (but equivalent) f o r m u l a s for expressing
varying over a
c
0
ing current, and its v a l u e r a n g e s from 1000 V / V to 5 0 0 0 V / V . T h e situation in t h e M O S F E T the M O S F E T ' s intrinsic gain. T h e first formula is the o n e m o s t directly c o m p a r a b l e to that of
BE
the BJT. Here, h o w e v e r , w e n o t e the following:
LOW-Frequency
1. The quantity in the d e n o m i n a t o r is V /2,
it is b e c o m i n g smaller in designs u s i n g s h o r t - c h a n n e l t e c h n o l o g i e s , it is still m u c h
are v e r y similar except, of course, for t h e finite b a s e current (finite B) of the B J T , which gives rise to r
larger than V . T
in t h e hybrid-TT m o d e l a n d to t h e u n e q u a l currents in the emitter and collector
n
0
is the
;
been steadily decreasing.
F o r b o t h d e v i c e s , the h y b r i d - ^ m o d e l indicates that t h e o p e n - c i r c u i t v o l t a g e gain
0
. A
~g r . maximum gain available from a single transistor of
o b t a i n e d from gate t o drain (base to collector) with the source (emitter) grounded is m
v
2. The n u m e r a t o r quantity V is b o t h p r o c e s s - a n d d e v i c e - d e p e n d e n t , and it's v a l u e h a s
m o d e l s b e c o m e identical if o n e thinks of t h e M O S F E T as a B J T w i t h B = °° (a = 1).
gr
F u r t h e r m o r e , as w e h a v e seen earlier, there are r e a s o n s for selecting
larger values for V
in the T m o d e l s ( a < 1 ) . H e r e it is interesting to note that the low-frequency small-signal
It follows that
w h i c h is a design p a r a m e t e r , and a l t h o u g h
ov
T h e l o w - f r e q u e n c y m o d e l s for the t w o devices
SMALL-SIGNAL MODELS
m
a
As a result, the intrinsic gain realized in a single M O S F E T amplifier stage fabricated in either type. a modern short-channel t e c h n o l o g y is only 2 0 V / V to 4 0 V / V , almost t w o orders of m a g n i -
This i m p o r t a n t transistor p a r a m e t e r is given the n a m e i n t r i n s i c g a i n and is denoted A . We
tude lower than that for a B J T .
0
will h a v e m o r e to say about the intrinsic gain shortly.
The third formula g i v e n for A
A l t h o u g h n o t included in the M O S F E T l o w - f r e q u e n c y m o d e l s h o w n in Table 6.3, the
given process t e c h n o l o g y (V
b o d y effect can have a significant implication for the operation of the M O S F E T as an amplifier.
inversely proportional to JT . D
0
in T a b l e 6.3 p o i n t s out a very interesting fact: F o r a
and p„C )
A
ox
and a given d e v i c e (W/L), t h e intrinsic gain is
This is illustrated in Fig. 6 . 1 , w h i c h s h o w s a typical plot of
In s i m p l e t e r m s , if t h e b o d y (substrate) is not c o n n e c t e d to t h e source, it c a n act as a second
A
gate for t h e M O S F E T . T h e v o l t a g e signal that d e v e l o p s b e t w e e n the b o d y and the source,
lowered. T h e gain, h o w e v e r , levels off at very l o w currents. T h i s is b e c a u s e t h e M O S F E T
v , gives rise to a drain current c o m p o n e n t g v , w h e r e t h e b o d y bs
mb
p r o p o r t i o n a l to g ; that is, g
bs
0
g
transconductance
mb
is
versus the bias current I . T h e plot confirms that the gain increases as t h e bias current is D
enters the subthreshold r e g i o n of operation (Section 4.1.9), w h e r e it b e c o m e s very m u c h like
= %g , w h e r e t h e factor % is in t h e r a n g e of 0.1 to 0.2. We
a BJT with an e x p o n e n t i a l current-voltage characteristic. T h e intrinsic gain t h e n b e c o m e s
shall take the b o d y effect into account in the study of I C M O S amplifiers in the succeeding
constant, just like that of a B J T . N o t e , h o w e v e r , that a l t h o u g h a h i g h e r gain is a c h i e v e d at
m
mb
m
lower bias currents, the price paid is a l o w e r g
sections. T h e b o d y effect h a s n o counterpart in the B J T . T H E TRANSCONDUCTANCE
collector current I .
m
g
F o r the B J T , t h e t r a n s c o n d u c t a n c e
m
depends- only on the dc
(Recall that V
is a p h y s i c a l c o n s t a n t = 0 . 0 2 5 V at r o o m temperature).
It is interesting to o b s e r v e that g
does n o t d e p e n d o n the g e o m e t r y of the BJT, and its
c
T
m
;
d e p e n d e n c e on the E B J area is only through the effect of the area on the total collector current; I . Similarly, the d e p e n d e n c e of g
m
c
on V
is only t h r o u g h the fact that V
BE
total current in the collector. B y contrast, g
BE
m
of the M O S F E T d e p e n d s on I , D
Therefore, w e u s e three different (but equivalent) formulas to express g
m
T h e first formula given in Table 6.3 for the M O S F E T ' s g
m
ov
of the M O S F E T . ,
with the f o r m u l a for the B J T . It indicates that for t h e s a m e operating current, g
m
ov
m
is p r o p o r t i o n a l to V .
m
ov
1000
m
Strong inversion region •
100 Slope
V. T
indicates that for a given device (i.e., given
Thus a higher g
>1<
of the
is the range of 0.1 V to
0.2 V, which is four to eight times the corresponding term in the B J T ' s formula, namely T h e s e c o n d f o r m u l a for the M O S F E T ' s g
Subthreshold region
and W/L.,
is the m o s t directly comparable
M O S F E T is m u c h smaller than that of the B J T . This is because V /2
W/L), g
(log scale)
determines the. V,
and less ability to drive capacitive loads and
thus a decrease in b a n d w i d t h . This point will b e further illustrated shortly.
10 -
is obtained b y operating the M O S F E T at
a h i g h e r o v e r d r i v e voltage. H o w e v e r , w e should recall t h e limitations i m p o s e d on the magnitude of V
ov
g
b y the Umited value of V . DD
Put differently, the need to obtain a reasonably high
constrains the d e s i g n e r ' s interest in r e d u c i n g
m
10"
V. ov
T h e third g formula shows that for a given transistor (i.e., given W/L), g m
m
JT . This should b e contrasted with the bipolar case, w h e r e g D
m
10"
10"
10"
10"
b (A) (log scale)
is proportional in
is directly proportional to I
c
FIGURE 6.1 The intrinsic gain of the MOSFET versus bias current I . Outside the subthreshold region, this is a plot of A' = y ; j2p„C WL/I for the case: p C = 20 LLPJV , V' = 20 Ylpm, L = 2 pm,&n¿ D
O U T P U T RESISTANCE
T h e output resistance for b o t h d e v i c e s is d e t e r m i n e d by similar foi-
2
0
w
m u l a s , with r b e i n g the ratio of V to t h e bias current (I 0
A
D
or I ). c
T h u s , for both transistors,
= 2 0
m
.
ox
D
n
OI
a
5 5 5
CHAPTER 6
5 5 6
S I N G L E - S T A G E I N T E G RAT E D - C I R C U I T A M P L I F I E R S
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
6.2
l^jgh-Frequency Operation
T h e simplified h i g h - f r e q u e n c y e q u i v a l e n t circuits for t h e
M O S F E T and t h e B J T are very similar, a n d so are t h e f o r m u l a s for d e t e r m i n i n g t h e i r u n
W e wish to compare the values of g , input resistance at the gate (base), r , and A for an NMOS m
a
0
transistor fabricated in the 0.25-mn technology specified in Table 6.1 and an npn transistor fabri cated in the low-voltage technology specified in Table 6.2. Assume both devices are operating at a drain (collector) current of 100 fiA. For the M O S F E T , let L = 0.4 pm and W = 4 pm, and specify the required
i t y - g a i n frequency (also called t r a n s i t i o n f r e q u e n c y ) f . T
ov
T
is a m e a s u r e of
capacitive loads. W e shall address the issue of c a p a c i t i v e loads shortly. F o r the t i m e b e i n g , note the striking similarity b e t w e e n the a p p r o x i m a t e formulas given in T a b l e 6.3 for the value of f
T
V.
R e c a l l that f
the intrinsic b a n d w i d t h of the transistor itself and does not t a k e into a c c o u n t the effects of
of the t w o devices. In both cases f
IS inversely proportional to the square of the
T
critical dimension of the device: the channel length for the M O S F E T and the base width for 2
the BJT. T h e s e formulas also clearly indicate that shorter-channel M O S F E T s and narrower-
Solution
base BJTs are inherently capable of a wider b a n d w i d t h of operation. It IS also important TO
For the N M O S transistor,
note that while for t h e B J T the a p p r o x i m a t e e x p r e s s i o n for f
indicates that it is entirely
T
ID =
2
kp-nC,
process determined, the c o r r e s p o n d i n g e x p r e s s i o n for t h e M O S F E T s h o w s that f
W~\ 2
is p r o
T
portional to the overdrive voltage V .
T h u s w e h a v e conflicting r e q u i r e m e n t s on
ov
2
o
requires an increase in V .
involves, among
ov
0v v
ov
wider bandwidth
ov
100 = - x 267 x — x V 2 0.4
V:
While a h i g h e r low-frequency gain is achieved b y operating at a l o w V , Therefore the selection of a v a l u e for V
ov
other considerations, a trade-off b e t w e e n gain and b a n d w i d t h . For npn transistors fabricated in the m o d e r n l o w - v o l t a g e p r o c e s s , f
Thus,
is in t h e r a n g e of
T
10 GHz to 2 0 G H z as c o m p a r e d to the 4 0 0 M H z to 6 0 0 M H z obtained with the STANDARD highvoltage p r o c e s s . In t h e M O S c a s e , N M O S t r a n s i s t o r s , f a b r i c a t e d in a m o d e r n s u b m i c r o n
0.27 V
technology, such as the 0.18-^tm process, achieve f
T
2{p c )[ n
y . y
ox
values in the r a n g e of 5 G H z to 15 G H z .
Before l e a v i n g t h e subject of high-frequency operation, l e t ' S l o o k into the effect of a
D
capacitive load o n the b a n d w i d t h of the c o m m o n - s o u r c e ( c o m m o n - e m i t t e r ) amplifier. F o r = J2 x 267 x 10 x 100 = 0.73 m A / V
this purpose w e shall a s s u m e that the frequencies of interest are m u c h l o w e r than f
T
of t h e
transistor. H e n c e w e shall not take the transistor capacitances into account. F i g u r e 6.2(a) shows a c o m m o n - s o u r c e amplifier with a capacitive load C . T h e voltage gain from g a t e to
R;„ —
L
drain can b e found as follows: KL_
5x0.4
=
In
20 k Q
V =-g V ,(r \\C )
0.1
0
m
g
0
L
1
0.73 x 20 = 14.6 V/V
= _«
For the npn transistor,
s C l v
Sm
r
gs r0
+
^~ sC L
lç_ V T
=
0.1 m A = 4 mA/V 0.025 V 100
r
* in = iz = A A „
4mA/V
=
V
s r "
V
l+sC r
gs
25 k Q
L
0
Thus the gain h a s , as e x p e c t e d , a low-frequency v a l u e of g r m
r
n
=
35 I
0.1 m A
c
A
0
= gr m
0
= 350 k Q
0
—A
0
and a frequency
response of t h e s i n g l e - t i m e - c o n s t a n t ( S T C ) l o w - p a s s t y p e w i t h a b r e a k (pole) f r e q u e n c y at
= 4 x 350 = 1400 V/V
co =
-JCr
P
L
~
a
(6.2) .
Obviously this pole is formed by r and C . A sketch of the magnitude of gain versus fre 0
L
quency is s h o w n in Fig. 6.2(b). W e observe that the gain crosses the 0-dB line at frequency co , t
EXERCISE (0, = A (Q = 0
6.2
P
(g r )-J— m
a
For an N M O S transistor fabricated in the 0.5-uiu process specified in Table 6.1 with L = 0.5 ,um, finjl the transcouductance and the intrinsic gain obtained at 1 ••- 10 p.\. 100//A. and 1 mA. n
Ans. 0.2 m A / V , 200 V/V; 0.6 m A / V , 62 VA''; 2 m A / V , 20 V / V
;
Although the reason is beyond our capabilities at this stage, f channels varies inversely with L rather than with L .
T
of MOSFETs that have very short
5 5 7
558
;
-„- '
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.2
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
|Gain| A (dB)
FIGURE 6 . 3 Increasing I or W/L increases the bandwidth of a MOSFET amplifier loaded by a constant capacitance C . D
L
design p a r a m e t e r is rather limited b e c a u s e of t h e n a r r o w r a n g e o v e r w h i c h A c a n vary. It follows that for t h e B J T there is only o n e effective design p a r a m e t e r : the collector .current I . Finally, note that w e h a v e not considered V to b e a design parameter, since its effect o n I is only secondary. Of course, as w e learned i n Chapter 5, V affects the^output signal swing. F o r the M O S F E T there are four design p a r a m e t e r s — I , V , L, a n d W—of w h i c h a n y three c a n b e selected b y t h e designer. F o r analog circuit applications t h e trade-off i n select ing a value for L is b e t w e e n t h e h i g h e r speeds of operation (wider amplifier b a n d w i d t h ) obtained at l o w e r values of L a n d the higher intrinsic gain obtained at larger values of L . Usually o n e selects an L of about 2 5 % to 5 0 % greater than L ^ . T h e s e c o n d d e s i g n p a r a m e t e r is V . W e h a v e already m a d e n u m e r o u s r e m a r k s about the effect of t h e v a l u e of V o n p e r f o r m a n c e . Usually, for s u b m i c r o n t e c h n o l o g i e s , V is selected in t h e r a n g e of 0.2 V to 0.4 V . O n c e values for L a n d V are selected, the designer is left with the selection of t h e value of I or W (or, equivalently, W/L). F o r a g i v e n process a n d for t h e selected values of L and V , I is p r o p o r t i o n a l to W/L. It is i m p o r t a n t to n o t e that t h e c h o i c e of I or, e q u i v a lently, of W/L h a s n o b e a r i n g o n t h e v a l u e of intrinsic g a i n A a n d t h e transition fre quency f . H o w e v e r , it affects t h e v a l u e of g a n d h e n c e t h e g a i n - b a n d w i d t h p r o d u c t . F i g u r e 6.3 illustrates this point b y s h o w i n g h o w the gain of a c o m m o n - s o u r c e amplifier operated at a constant V varies with I (or, equivalently, W/L). N o t e that w h i l e the d c gain r e m a i n s unchanged, increasing W/L and, correspondingly, 1 increases the bandwidth proportionally. This, h o w e v e r , a s s u m e s that t h e l o a d c a p a c i t a n c e C is not affected b y t h e device size, an a s s u m p t i o n that m a y n o t b e entirely justified i n s o m e cases. E
c
CE
c
CE
D
(b)
ov
ov
FIGURE 6 . 2 Frequency response of a CS amplifier loaded with a capacitance C and fed with an ideal voltage source. It ts assumed that the transistor is operating at frequencies much lower t h a n / afd internal capacitances are not taken into account. L
r
ov
ov
ov
Thus,
D
ov
(6.3)
D
D
0
T
3
T h a t is, t h e u n i t y - g a i n f r e q u e n c y or, equivalently, the g a i n - b a n d w i d t h p r o d u c t co, is the ratio of g a n d C . W e thus clearly see that for a g i v e n capacitive load C , a larger g a i n b a n d w i d t h p r o d u c t is achieved by operating the M O S F E T as a higher g . Identical analysis a n d c o n c l u s i o n s a p p l y to the c a s e of the B J T . In e a c h case, b a n d w i d t h increases as bias cur rent is increased. m
L
L
m
Design Parameters F o r the B J T there are three design p a r a m e t e r s — I , V , a n d I (or, equivalently, t h e area of the e m i t t e r - b a s e j u n c t i o n ) — o f w h i c h a n y t w o can b e selected by the designer. H o w e v e r , since I is exponentially related to V a n d is v e r y sensitive to the v a l u e of V (V c h a n g e s b y only 6 0 m V for a factor of 10 c h a n g e i n I ), I i s m u c h m o r e useful than V a s a d e s i g n parameter. A s m e n t i o n e d earlier, t h e utility of t h e E B J a r e a as a c
c
BE
BE
BE
m
0Y
D
D
L
s
BE
c
c
BE
In this example w e investigate the gain and the high-frequency response of an npn transistor and an N M O S transistor. For the npn transistor, assume that it is fabricated in the low-voltage process specified in Table 6.2, and assume that ~ C^. For I = 10 /iA, 100 pA, and 1 m A , find g , r, A, C , C ,C, CJJ, and f . Also, for each value of I , find the gain-bandwidth product f of a common-emitter amplifier loaded by a 1-pF capacitance, neglecting the internal capacitances c
The unity-gain frequency and the gain-bandwidth product of an amplifier are the same when the fre quency response is of the single-pole type; otherwise the two parameters may differ
m
r
0
0
de
je
x
T
c
t
".
559
CHAPTER 6
6.2
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
of the transistor. For the N M O S transistor, assume that it is fabricated in the 0.25-mn C M O S process with L = 0.4 pirn. Let the transistor b e operated at V D
= |WZ.C
g J
0 I
.
+ C „ = i f f x 0.4 x 5.8 + 0.6W 0
= 0.25 V. Find W/L that is required to
ov
obtain I
C
C O M P A R I S O N O F T H E M O S F E T A N D T H E BJT
= 10 ,uA, 100 pA, and 1 m A . At each value of I ,
find g ,
D
r, A,
m
a
C,
0
gs
C, gd
and
f.
c
T
0.6 W
=c
gi
Also, for each value of I , determine the gain-bandwidth product / , of a common-source ampli-
0
D
fier loaded by a 1-pF capacitance, neglecting the internal capacitances of the transistor.
fr =
2n{C +C ) g5
Solution
f,=
For the npn transistor, L
=
#
=
o i 5
r
4
0
/
c
A
/
v
W.L
lr I
A
g
m
(mA/V)
r„ (kil)
A.. (V/V)
C.,. (fF)
C., (fF)
16 16 16
1.03 10.3 103
0.29 2.9 29
f
d
T
(GHz)
f. ( M H z )
9.7 9.7 9.7
12.7 127 1270
T
10 M 100 M 1mA
= --^ = -r^rz = 1400 V/V V 0.025
0
§ ¡71
2nC,
We thus obtain the following results:
LR
R
=
* -
gd
0.08 0.8
1.2 12 120
200 20 2
T
C
de
= Tg
= 10 x 1 0 '
= 2C
= 10fF
F
C
je
m
je0
=
C
K
C
1 2
9
x 40/
= 0.4 x 1 0 ~ / F
c
c
+ Cj
e
d e
= 5 fF
C/i —
6.3
Find 1 , g , r,„ A , C , C - , and f for an N M O S transistor fabricated in the 0.5-jUm C M O S technology specified in Table 6.1. L e t L - 0.5 fim, W,= 5 /.mi, and V = 0.3 V. D
ln
Q
Si
e d
T
ov
Ans. 85.5 pA: 0.57 m A / V ; 66.7 1
2n(C +C ) K
¡í
f,= 2
K
C
Inxlx
L
10"
1 2
6.2.4 Combining MOS and Bipolar Transistors-BiCMOS Circuits
W e thus obtain the following results:
F r o m t h e d i s c u s s i o n a b o v e it s h o u l d b e e v i d e n t that t h e B J T h a s t h e a d v a n t a g e o v e r l
c
g„ (mA/V) r
0
(kil)
A
0
(V/V) C
(fF) C
de
(fF)
C (fF)
C,, (fF)
T
f
T
(GHz)
f, (MHz)
the M O S F E T of a m u c h h i g h e r t r a n s c o n d u c t a n c e (g ) m
at t h e s a m e v a l u e of d c b i a s cur-
rent. T h u s , in a d d i t i o n t o r e a l i z i n g m u c h h i g h e r v o l t a g e g a i n s p e r a m p l i f i e r stage, b i p o l a r lOiiA 100/xA 1mA
0.4 4 40
3500 350 35
1400 1400 1400
4 40 400
10 10 10
14 50 410
5 5 5
3.4 11.6 15.3
64 640 6400
transistor a m p l i f i e r s h a v e s u p e r i o r h i g h - f r e q u e n c y p e r f o r m a n c e c o m p a r e d to their M O S counterparts. O n the other h a n d , the practically infinite i n p u t resistance at the gate of a M O S F E T makes it p o s s i b l e to d e s i g n amplifiers w i t h e x t r e m e l y h i g h i n p u t resistances a n d an a l m o s t
For the N M O S transistor,
zero input bias current. A l s o , as m e n t i o n e d earlier, t h e M O S F E T p r o v i d e s a n excellent o x
1
D ,
o
l
i m p l e m e n t a t i o n of a switch, a fact that h a s m a d e C M O S t e c h n o l o g y c a p a b l e of realizing a
v
host of a n a l o g circuit functions that are not p o s s i b l e wifh.bipolar transistors. It can thus b e seen that e a c h of the t w o transistor types h a s its o w n distinct a n d u n i q u e
1 X 2 6 7 X ^ X 1
2
¿ 1 6
advantages: B i p o l a r technology has b e e n extremely useful in the design of very-high-quality
Thus,
general-purpose circuit b u i l d i n g b l o c k s , such as o p a m p s . O n t h e other h a n d , C M O S , with W L
0.127
its very h i g h p a c k i n g density a n d its suitability for b o t h digital and analog circuits, h a s o
b e c o m e the t e c h n o l o g y of c h o i c e for the i m p l e m e n t a t i o n of v e r y - l a r g e - s c a l e integrated circuits. N e v e r t h e l e s s , t h e p e r f o r m a n c e of C M O S circuits c a n b e i m p r o v e d if the designer h a s
S
m
V /2
8/
0.25/2
ov
n D
AA/
available (on the s a m e chip) b i p o l a r transistors that c a n b e e m p l o y e d in functions that require their h i g h g
m
V ¡ L 0
=
5 x 0 4
1
I
L
L
D
¿ O = gr m
0
D
=16
V/V
-
=
a n d excellent current-driving capability. A t e c h n o l o g y that allows the
2
fabrication of h i g h - q u a l i t y b i p o l a r transistors on the s a m e chip as C M O S circuits is aptly
I
called B i C M O S . A t a p p r o p r i a t e locations t h r o u g h o u t this b o o k w e shall p r e s e n t interesting
D
and useful B i C M O S circuit b l o c k s .
56
HAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6 3 IC B I A S I N G — C U R R E N T S O U R C E S , C U R R E N T M I R R O R S , A N D C U R R E N T - S T E E R I N G C I R C U I T S
6.2.5 Validity of the Square-Law MOSFET Model W e c o n c l u d e this section with a c o m m e n t o n t h e validity of the simple square-law model we h a v e b e e n using to describe the operation of the M O S transistor. W h i l e this simple model w o r k s well for devices with relatively long channels (>1 Lira) it does not p r o v i d e an accurate representation of the operation of short-channel devices. This is b e c a u s e a n u m b e r of physi cal p h e n o m e n a c o m e into p l a y in t h e s e s u b m i c r o n d e v i c e s , r e s u l t i n g in w h a t are called s h o r t - c h a n n e l effects. A l t h o u g h the study of short-channel effects is b e y o n d the scope of this b o o k , it should b e mentioned that M O S F E T m o d e l s h a v e been d e v e l o p e d that take these effects into account. H o w e v e r , they are u n d e r s t a n d a b l y quite c o m p l e x and d o not lend t h e m s e l v e s to h a n d analysis of the type n e e d e d to d e v e l o p insight into circuit operation Rather, these m o d e l s are suitable for c o m p u t e r simulation and are indeed used in SPICE (Section 6.13). F o r quick, m a n u a l analysis, h o w e v e r , w e will continue to u s e the square-law m o d e l w h i c h is the basis for the c o m p a r i s o n of T a b l e 6.3.
/REF
R
\f
-oVn
+ Vos F I G U R E 6.4 Circuit for a basic MOSFET constantcurrent source. N o w consider transistor Q : It has the same V as'-Qi, thus, if w e a s s u m e that it is operat ing in saturation, its drain current, which is the output current I of the current source, will b e 2
'
6.3 IC B I A S I N G - C U R R E N T SOURCES, CURRENT MIRRORS, AND CURRENT-STEERING CIRCUITS
cs
0
B i a s i n g in integrated-circuit design is b a s e d o n the use of constant-current sources. O n an IC c h i p with a n u m b e r of amplifier stages, a constant dc current (called a r e f e r e n c e current) is g e n e r a t e d at one location and is then replicated at various other locations for biasing the var ious amplifier stages through a process k n o w n as c u r r e n t steering. This a p p r o a c h has the a d v a n t a g e that t h e effort expended on generating a predictable and stable reference current, usually utilizing a precision resistor external to t h e chip, n e e d not b e r e p e a t e d for every amplifier stage. Furthermore, the bias currents of t h e various stages track each other in case of c h a n g e s in power-supply voltage or in temperature. In this section w e study circuit building blocks and techniques e m p l o y e d in the bias design of I C amplifiers. These circuits are also utilized as amplifier load e l e m e n t s , as will be seen in Section 6.5 and beyond.
(6.6)
(v -v y
Io=h
GS
tn
where w e h a v e n e g l e c t e d channel-length m o d u l a t i o n . E q u a t i o n s (6.4) and (6.6) enable us to relate the o u t p u t current l
0
to the reference current 7 ^ as follows: I
0
I REF
_
(W/L)
2
(6.7)
(W/L),
This is a s i m p l e and attractive relationship: T h e special c o n n e c t i o n of Q and Q p r o v i d e s an output current 7 that is related to t h e reference current 7 ^ b y the ratio of t h e aspect ratios of the transistors. In other w o r d s , the relationship b e t w e e n I and 7 ^ is solely deter mined b y t h e g e o m e t r i e s of the transistors. In t h e special c a s e of identical transistors, [ = 7 , and t h e circuit simply replicates or m i r r o r s the reference current in the output ter minal. This has given the circuit c o m p o s e d of g , and Q the n a m e current mirror, a n a m e that is u s e d irrespective of t h e ratio of d e v i c e d i m e n s i o n s . l
2
0
Q
0
R E F
2
6.3.1 The Basic MOSFET Current Source F i g u r e 6.4 shows the circuit of a simple M O S constant-current source. T h e heart of the cir cuit is transistor Q the drain of which is shorted to its g a t e , thereby forcing it to operate in the saturation m o d e with 4
u
Figure 6.5 depicts t h e current m i r r o r circuit with the input reference current s h o w n as being supplied b y a current source for b o t h simplicity a n d generality. T h e c u r r e n t g a i n or current transfer ratio of t h e current m i r r o r is g i v e n b y Eq. (6.7).
Effect of V on
l
we assumed Q
to b e operating in saturation. T h i s is obviously essential if Q
0
r -lK[j)^v s-v„f D1
(6.4)
G
2
Q
In the description above for the operation of the current source of Fig. 6.4, 2
is to supply a
w h e r e w e have neglected channel-length modulation. T h e drain current of Q is supplied by V through resistor R, which in most cases w o u l d b e outside the I C chip. S i n c e the gate currents are zero, t
DD
l
T
-
Dl -
T REF -
V
V
DD ~ GS
(6.0)
rf
w h e r e the current through R is considered to be the reference current of the current source and is denoted 7 ^ . Equations (6.4) and (6.5) can b e used to d e t e r m i n e the v a l u e required for R.
4
Such a transistor is said to be diode connected.
+
02
V
0
FIGURE 6.5 Basic MOSFET current mirror.
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
B I A S I N G — C U R R E N T SOURCES, CURRENT MIRRORS, A N D CURRENT-STEERING CIRCUITS
constant-current output. T o e n s u r e that Q is saturated, t h e circuit to w h i c h the drain of Q j to b e c o n n e c t e d m u s t establish a drain v o l t a g e V that satisfies the relationship 2
2
565
s
0
V >V -V 0
GS
(6.8)
t
Given V = 3 V and using 7 = 100 JJLA, it is required to design the circuit of Fig. 6.4 to obtain an output current whose nominal value is 100 /lA. Find R if Q and Q are matched and have channel lengths of 1 /mi, channel widths of 10 / a n , V, = 0.7 V, and k' = 200 i i A / V . What is the lowest possible value of V ? Assuming that for this process technology the Early voltage y = 20 V / m n , find the output resistance of the current source. Also, find the change in output current resulting from a +1-V change in V . DD
R E F
x
or, equivalently, in t e r m s of the o v e r d r i v e v o l t a g e V
of Q a n d
OV
2
2
Q,
X
n
2
0
£ V
V
(6.9)
ov
0
0
In other w o r d s , t h e current source will o p e r a t e p r o p e r l y w i t h an output voltage V V , w h i c h is a few tenths of a volt.
0
as low as
Solution
ov
A l t h o u g h thus far neglected, c h a n n e l - l e n g t h m o d u l a t i o n can h a v e . a significant effect on the operation of t h e current source. C o n s i d e r , for simplicity, the case of identical devices Q and 0 . T h e drain current of Q , I , will e q u a l the current in Q, , I^p, at the value of V that causes t h e t w o devices to h a v e t h e s a m e V , that is, at V = V . A s V is increased a b o v e this v a l u e , I will increase a c c o r d i n g to the i n c r e m e n t a l output resistance r of Q . T h i s is illustrated in F i g . 6.6, w h i c h s h o w s I v e r s u s V . O b s e r v e that since Q is operating at a constant V (determined by passing t h r o u g h t h e m a t c h e d device £>,), the curve in Fig. 6.6 is simply the i -v characteristic c u r v e of Q for v equal to the particular value V .
2
x
2
2
0
t
DS
0
GS
o2
0
2
DS
2
2
x 2 0 0 x 10 v;
V
= 0.316 V
ov
and
GS
V + V=
0.7+ 0 . 3 1 6 s i V
VDD ~ VGS
3-1 = 20 k Q 0.1 m A
t
GS
In s u m m a r y , the current s o u r c e of F i g . 6.4 a n d t h e current m i r r o r of Fig. 6.5 h a v e a finite o u t p u t resistance R ,
ov
0
R
^
o
=
r
o
^
2
U A
Thus,
2
GS
D
100:
"
0
0
0
1
0
( 6
.
V
0 r a i n
= V v = 0.3 V 0
1 0 )
For the transistors used, L = 1 ftm. Thus, where I is g i v e n b y Eq. (6.6) a n d V is t h e E a r l y v o l t a g e of Q . g i v e n p r o c e s s t e c h n o l o g y , V is p r o p o r t i o n a l to t h e transistor c h a n n e l h i g h output-resistance v a l u e s , current s o u r c e s are u s u a l l y d e s i g n e d relatively long c h a n n e l s . Finally, n o t e that w e c a n e x p r e s s t h e current 0
A2
2
A
A l s o , recall that for a length; thus, to obtain using transistors with I Q as
V
A
= 20 x 1 = 20 V 20 V
0L
C/
The output current will be 100 piA at V = V 0
change in I
0
(W/L)
1
™ K
GS
= 1 V. If V changes by +1 V, the corresponding 0
will be
V, A7
loi
0.2 M Q
100 u A
AV = — = 0
0
1 V — = 0.2 M Q
5 LlA ^
i
Slope = -\-
/ 7ref
*
06.4 In the current source of Example 6.4, it is required to reduce the change in output current. AI , corre sponding to a change in output voltage. AV , of I V to 1% of What should die dimensions of Q and Q bt changed to? A s s u m e that and Q are to remain matched. : : ()
7
0
2
Ans. L = 5pm\
0
V
~ V
GS
V
GS
%
2
IV = 5 0 / m i
V
0
T Vv 0
FIGURE 6 . 6 Output characteristic of the current source in Fig. 6.4 and the current mirror of Fig. 6.5 for the case Q is matched to gj • 2
6.3.2 MOS Current-Steering Circuits As m e n t i o n e d earlier, o n c e a constant current is generated, it can b e replicated to p r o v i d e dc bias currents for the various amplifier stages in an I C . C u r r e n t mirrors can obviously be used to implement this current-steering function. Figure 6.7 shows a simple current-steering circuit.
566
I
CHAPTER 6
SINGLE-STAGE
INTEGRATED-CIRCUIT
AMPLIFIERS
A
V
DD
6.3 IC B I A S I N G — C U R R E N T
SOURCES, CURRENT MIRRORS, A N D CURRENT-STEERING
CIRCUITS
appropriately called a current source, whereas Q should m o r e properly b e called a c u r r e n t sink. In an I C , both current sources a n d current sinks a r e usually needed.
+
2
6.5
For the circuit of Fig. 6.7, let V = V = 1.5 V, V,„ = 0.6 V, V = - 0 . 6 V, all channel lengths = 1 urn, k' = 200 juA/V , k' = 80 t / A / V , and A = 0. For / = lO'u.A, find the widths of all transistors to obtain l = 60 pA, I = 20 pA. and 7 = 80 pA. It is further required that the voltage at the drain of Q-, be allowed to go down lo within 0.2 V of the negative supply and that the voltage al the drain of Q be allowed lo go up to within 0.2 V of the positive supply. m>
ss
2
2
H
p
R l ; l
2
5
3
5
OU
I-
.03
H
+
Ans. H-', = 2.5 pm: W2 = 15 pm: W3 = 5 t/m; l ¥ 4 = 12.5 u m ; W5 = 50 pm
Van
6.3.3 BJT Circuits FIGURE 6 . 7 A current-steering circuit.
H e r e Q, together w i t h R d e t e r m i n e t h e reference current 7 ^ . Transistors Q form a t w o - o u t p u t current mirror,
u
Q , and Q 2
3
T h e basic B J T current mirror is s h o w n in Fig. 6.8. It w o r k s in a fashion v e r y similar to that of the M O S mirror. H o w e v e r , there are t w o i m p o r t a n t differences: First, t h e n o n z e r o b a s e current of the B J T (or, equivalently, t h e finite ¡3) causes an error in t h e current transfer ratio of the bipolar mirror. Second, t h e current transfer ratio is d e t e r m i n e d b y t h e relative areas of the e m i t t e r - b a s e j u n c t i o n s of Q a n d Q . Let u s first consider t h e case w h e n B, is sufficiently h i g h s o that w e c a n n e g l e c t t h e b a s e currents. T h e reference current 7 ^ is^passed t h r o u g h the d i o d e - c o n n e c t e d transistor Q a n d thus establishes a c o r r e s p o n d i n g voltage V , w h i c h in turn is applied b e t w e e n b a s e a n d emitter of Q . N o w , if Q is m a t c h e d to Q.{ or, m o r e specifically, if t h e E B J area of Q is t h e same as that of Q, and thus Q h a s the same scale current I as Q , then t h e collector current of Q will b e equal t o that of Q ; that is, x
(W/L)
2
12
_
^REF
(6.12)
(W/L)
x
l
BE
(W/L)
3
^3
—
^REF
2
(6.13)
(W/L)
l
2
2
2
2
T o e n s u r e o p e r a t i o n i n t h e saturation r e g i o n , t h e v o l t a g e s at t h e drains of Q c o n s t r a i n e d as follows:
2
a n d Q are 3
2
s
x
x
lo = ' r e f V ,
V
D2
>-V +
D3
V
ss
- V
GS1
(6.14)
tn
(6-18)
For this t o h a p p e n , h o w e v e r , Q m u s t b e operating in t h e active m o d e , w h i c h in turn is achieved so long as t h e collector voltage V is 0.3 V or so h i g h e r than that of the emitter. T o obtain a current transfer ratio other than unity, say m, w e simply arrange that t h e area of the E B J of Q is m times that of Q . In this case, 2
or, equivalently,
0
V ,
V >-V
D2
D3
+V
SS
.
0V1
(6.15)
2
x
I
0
where V is t h e overdrive voltage at w h i c h Q Q , a n d Q are operating. I n other w o r d s , the drains of Q a n d Q will h a v e to r e m a i n higher than -V b y at least the overdrive voltage, w h i c h is usually a f e w tenths of a volt. 0V1
u
2
2
=
OT7REP
3
3
ss
A
C o n t i n u i n g o u r discussion of t h e circuit in F i g . 6.7, w e see that current I is fed t o the input side of a current mirror f o r m e d b y P M O S transistors Q a n d Q . T h i s m i r r o r provides 3
4
75
"
5
(6 16)
-
Iw/lJI
oV
0
w h e r e 7 = 7 . T o k e e p Q in saturation, its drain v o l t a g e should b e 4
3
5
VDS^V -\V \ DD
where V
0V5
(6.17)
0V5
is t h e overdrive voltage at w h i c h Q is operating. 5
- Finally, a n i m p o r t a n t p o i n t t o n o t e is that w h i l e Q pulls its current 7 from a l o a d (not s h o w n in Fig. 6.7), Q pushes its current 7 into a l o a d (not s h o w n i n Fig. 6.7). T h u s Q is 2
5
5
2
5
FIGURE 6 . 8 The basic BJT current mirror.
(6.19)
: 37
CHAPTER 6
6.3 IC B I A S I N G — C U R R E N T S O U R C E S , C U R R E N T M I R R O R S , A N D C U R R E N T - S T E E R I N G C I R C U I T S
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
.
A s V is n o m i n a l v a l u e only w h e n Q h a s t h e s a m e V as Q , n a m e l y at V = V . increased, hI will c o r r e s p o n d i n g l y i n c r e a s e . T a k i n g b o t h t h e finite /? a n d the finite R into 2
CE
0
x
BE
0
0
a
account, w e can e x p r e s s t h e o u t p u t current o f a B J T m i r r o r with a n o m i n a l c u r r e n t transfer ratio m as f
o V
h
\
0
\2I /ß
m
c
\ . Qi
J
p
^
hiß 'c/P —
1 +
^> 0 2
1 +
V -V n
R
(6.24)
m + 1 J
where w e n o t e that the error t e r m d u e to t h e E a r l y effect is e x p r e s s e d so that it r e d u c e s to zero for
T
FIGURE 6 . 9 Analysis of the current mirror taking into account the finite 8 of the BJTs.
V
0
V BE-
EXERCISE
In general, the current transfer ratio is g i v e n b y
6.6
Consider a BJT current mirror with a nominal current transfer ratio of unity. Let the transistors have / / s |() A, P= 100, and V, = 100 V . For / ^ f ' ^ l ^ m A . find l , when V = 5 V.,Also. find the output resistance. 1 5
lr
A r e a of E B J of Q
\si I si
(
2 < 6 2
AreaofEBJof Q
)
-'°
x
Alternatively, if t h e area ratio m is an integer, o n e can t h i n k of Q as equivalent to m transis^ tors, e a c h m a t c h e d to Q a n d c o n n e c t e d in parallel. N e x t w e consider the effect of finite transistor ¡5 o n the current transfer ratio. T h e analysis for the c a s e in w h i c h t h e current transfer ratio is n o m i n a l l y u n i t y — t h a t is, for t h e case in w h i c h < 2 is m a t c h e d to Q —is illustrated in F i g . 6 . 9 . T h e k e y point h e r e is that since Q and Q are m a t c h e d and h a v e the s a m e V , their collector currents will b e equal. T h e rest of the analysis is straightforward. A n o d e e q u a t i o n at the collector of Q yields
A
Ans. 1.02 mA; 100 kQ
2
x
2
x
x
2
BE
A Simple Current Source
In a m a n n e r a n a l o g o u s to that in the M O S case, t h e basic B J T
current m i r r o r can b e u s e d to i m p l e m e n t a simple current source, as s h o w n in F i g . 6.10. H e r e the reference current is
x
/ree = ^ 7 7 ^ l
= I
m F
c
+ 2I /p= c
l (l
+
c
where V
BE
Finally, since I =
I,
0
c
is the b a s e - e m i t t e r voltage corresponding to the desired value of output current 7
r
1
REF
1
(6.21)
1+:
0
Ref
(
1 + (2/0)
I
=
0
V
x
0
F
R =r o
o2
-
0
V \ BE
V
A
T h e output resistance of this current source is r of
N o t e that as /3 a p p r o a c h e s °o, / / / r e a p p r o a c h e s t h e n o m i n a l v a l u e of unity. F o r typical values of B, h o w e v e r , t h e error in the current transfer ratio can b e significant. F o r instance, ft = 100 results in a 2 % error in the current transfer ratio. F u r t h e r m o r e , the error d u e to the finite ft increases as t h e n o m i n a l current transfer ratio is increased. T h e r e a d e r is e n c o u r a g e d to s h o w that for a m i r r o r with a n o m i n a l current transfer ratio m—that is, o n e in w h i c h I = ml —the actual current transfer ratio is g i v e n b y
0
Q,
=f
= j ±
l
O
J
2
^REF
Vcc À
si
I REF
1 +
m m + 1
(6.22)
In c o m m o n with the M O S current mirror, the B J T mirror h a s a finite output resistance R„, R
0
°
Ya
^
M
0
(6.23)
In
where V and r a r e t h e E a r l y v o l t a g e a n d t h e o u t p u t r e s i s t a n c e , r e s p e c t i v e l y , of Q T h u s , e v e n if w e n e g l e c t t h e e r r o r d u e to finite t h e o u t p u t c u r r e n t I will b e at its A2
I,
the current transfer ratio can b e found as lr
s2
(6-25)
o2
+ VBE
2
0
FIGURE 6 . 1 0 A simple BJT current source.
(6.27)
5 6 9
70
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.4
HIGH-FREQUENCY RESPONSE—GENERAL CONSIDERATIONS
To generate a dc current twice the v a l u e of / ^ p , t w o transistors, Q and Q , each of which is m a t c h e d to Q , are c o n n e c t e d in parallel, and t h e c o m b i n a t i o n forms a m i r r o r w i t h g j T h u s I = 2 / r e f - N o t e that the parallel c o m b i n a t i o n of Q and Q is equivalent to a tran sistor with an E B J area double that of Q w h i c h is precisely w h a t is done w h e n this circuit is fabricated in I C form. Transistor Q forms a m i r r o r with Q ; thus Q p r o v i d e s a constant current I e q u a l to IKEF- ^ ^ ^ 3 sources its current to parts of the circuit w h o s e voltage should n o t exceed ( V - 0.3 V ) , Q sinks its current from parts of t h e circuit w h o s e voltage should not decrease below - V + 0.3 V . Finally, to generate a current three times I , three transistors, g , <2g, and ft* ° f which is matched to Q , are connected in parallel, and the combination is placed in a m i r r o r configuration with Q . A g a i n , in an I C i m p l e m e n t a t i o n , Q , Q , and Q would b e r e p l a c e d with a t r a n s i s f o r h a v i n g a j u n c t i o n area three t i m e s that of Q . s
6
x
D6J
15
Assuming the availability of BJTs with scale currents I = ICf A, ß -100, and V = 50 V , design the current-source circuit of Fig. 6.10 to provide an output current I = 0.5 m A at V = 2 V. T h e power supply F = 5 V. Give the values of 1^, R, and V . Also, find l at F = 5 V. Ans. 0.497 m A ; 8.71 k Q ; 0.3 V; 0.53 m A s
A
0
c c
0
0min
0
0
3
5
4
o t e
2
w
4
2
e
c c
4
EE
Current Steering T o generate bias currents for different amplifier stages in an IC, the c u r r e n t - s t e e r i n g a p p r o a c h d e s c r i b e d for M O S circuits c a n b e a p p l i e d in t h e b i p o l a r case. A s an example, consider the circuit s h o w n in Fig. 6 . 1 1 . T h e r i c reference current 1^ is gener ated in the b r a n c h that consists of the d i o d e - c o n n e c t e d transistor Q resistor R, and the d i o d e - c o n n e c t e d transistor Q :
6
u
m F
eacn
7
2
2
7
s
9
2
u
2
REF
V,CC '
•V»
EE
(6.28)
R
N o w , for simplicity, a s s u m e that all t h e transistors h a v e high B and thus that t h e b a s e cur rents are negligibly small. W e will also n e g l e c t the E a r l y effect. T h e d i o d e - c o n n e c t e d tran sistor Q forms a current mirror with Q ; thus Q will supply a constant current I equal to / r e p . Transistor Q can supply this current to any l o a d as long as the voltage that develops at the collector does not e x c e e d ( V - 0 . 3 V ) ; o t h e r w i s e Q w o u l d enter t h e saturation region. 1
3
f 6.fc=Figure E6.8 shows an /V-output current mirror. Assuming that all transistors are matched and have Finite B and ignoring the effect of finite output resistances, show that
3
l +
•1. (N+l)/B
3
c c
3
For B = 1 0 0 , find the maximum number of outputs for an error not exceeding 10%.
i
Qi ,
R
E
v ~
t -v
EE
F I G U R E E6.8
Ans. 9
5.4 HIGH-FREQUENCY RESPONSE-GENERAL . y CONSIDERATIONS
FIGURE 6 . 1 1
Generation of a number of constant currents of various magnitudes.
T h e amplifier circuits w e shall study in this chapter and the next are i n t e n d e d for fabrication using I C technology. Therefore they d o not employ b y p a s s capacitors. M o r e o v e r , the various stages in an integrated-circuit cascade amplifier are directly coupled; that is, they do not utilize
571
CHAPTER 6
6.4
S I N G L E - S T A G E I N T E G RAT E D - C I R C U I T A M P L I F I E R S
1
\A\ (dB),
HIGH-FREQUENCY RESPONSE—GENERAL CONSIDERATIONS
the gain a c q u i r e s t h e factor F (s),
w h i c h c a n b e e x p r e s s e d in t e r m s of its p o l e s a n d z e r o s ,
H
6
which are u s u a l l y real, as follows: p
20 log \A \
(
g
)
( 1 + S/CQ )(\
=
+ S/CQ )
ZI
\
• • . (1 + j / f f l z J
Z2
H
(l+s/m )(l+s/co )...(l+s/a> )
M
PX
3 dB where co , Pl
co , P2
poles a n d co , zl
. . . , co Z2
Pn
are positive n u m b e r s r e p r e s e n t i n g t h e frequencies of t h e n real
Pn
co ,.
F2
. . , co
Zn
a r e p o s i t i v e , n e g a t i v e , o r infinite n u m b e r s r e p r e s e n t i n g t h e
frequencies of t h e n real t r a n s m i s s i o n zeros. N o t e from E q . (6.30) that, as should b e expected, as s a p p r o a c h e s 0,F (s)
a p p r o a c h e s unity a n d t h e gain a p p r o a c h e s
H
A. M
6.4.2 Determining the 3-dB Frequency f
H
The amplifier d e s i g n e r usually is particularly interested in t h e p a r t of t h e h i g h - f r e q u e n c y
^»
0 (or /
3 d B
band that is c l o s e t o t h e m i d b a n d . T h i s is b e c a u s e t h e designer n e e d s t o e s t i m a t e — a n d if
)
need b e m o d i f y — t h e value of the upper 3-dB frequency f
(or oo ; f
H
F I G U R E 6 . 1 2 Frequency response of a direct-coupled (dc) amplifier. Observe that the gain does not fall off at low frequencies, and the midband gain A extends down to zero frequency. M
H
H
= co /2n).
Toward
H
that end it s h o u l d b e m e n t i o n e d that in m a n y cases t h e zeros a r e either at infinity o r s u c h high frequencies as t o b e of little significance t o t h e d e t e r m i n a t i o n of (0 . If in addition o n e H
of the p o l e s , s a y co , Pl
is of m u c h l o w e r frequency than a n y of t h e other p o l e s , then this p o l e
will h a v e t h e greatest effect on t h e v a l u e of t h e amplifier co . In other w o r d s , this p o l e will H
5
l a r g e c o u p l i n g capacitors, such as t h o s e w e e m p l o y e d in C h a p t e r s 4 a n d 5 . T h e frequency
dominate
response of these d i r e c t - c o u p l e d o r d c amplifiers takes the general form shown in Fig. 6.12,
d o m i n a n t - p o l e r e s p o n s e . I n such cases t h e function F (s)
from w h i c h w e n o t e that t h e gain r e m a i n s constant at its m i d b a n d value A
M
t h e h i g h - f r e q u e n c y r e s p o n s e of t h e amplifier, a n d t h e amplifier is said t o h a v e a can b e approximated by
H
d o w n to zero
frequency ( d c ) . T h a t is, c o m p a r e d to t h e capacitively c o u p l e d amplifiers that utilize bypass
l
F (s)
= l+s/(o
H
capacitors (Sections 4 . 9 a n d 5.9), direct-coupled I C amplifiers d o n o t suffer gain reduction
(6.31)
Pl
at l o w frequencies. T h e gain, however, falls off at t h e high-frequency e n d d u e to t h e internal c a p a c i t a n c e s of t h e transistor. T h e s e c a p a c i t a n c e s , w h i c h a r e i n c l u d e d in t h e high-frequency
which is t h e transfer function of a first-order (or S T C ) l o w - p a s s n e t w o r k ( A p p e n d i x D ) . It
d e v i c e m o d e l s in T a b l e 6 . 3 , r e p r e s e n t t h e c h a r g e storage p h e n o m e n a that t a k e p l a c e inside
follows that if a d o m i n a n t p o l e exists, then t h e d e t e r m i n a t i o n of <% is greatly simplified;
the transistors.
co
H
T h e h i g h - f r e q u e n c y r e s p o n s e s of t h e C S a n d C E amplifiers w e r e studied in Sections 4.9 a n d 5.9. In this chapter a n d t h e next, as w e study a variety of IC-amplifier configurations, we shall also c o n s i d e r their h i g h - f r e q u e n c y operation. S o m e of t h e tools n e e d e d for s u c h a study are p r e s e n t e d in this section.
= co
(6.32)
P1
This is t h e situation w e e n c o u n t e r e d in t h e c a s e of t h e c o m m o n - s o u r c e amplifier a n a l y z e d in Section 4 . 9 a n d t h e c o m m o n - e m i t t e r amplifier a n a l y z e d in Section 5.9. A s a rule of t h u m b , a dominant
pole exists if the lowest-frequency
pole is at least two octaves
(a factor
of 4)
away
from the nearest pole or zero. If a d o m i n a n t pole d o e s n o t exist, t h e 3-dB frequency co c a n b e determined from a plot of H
6.4.1 The High-Frequency Gain Function
\F (jco)\. H
T h e amplifier gain, taking into a c c o u n t t h e internal transistor c a p a c i t a n c e s , c a n b e expressed
Alternatively, an approximate formula for c% c a n b e derived as follows: Consider,
for simplicity, t h e c a s e of a circuit h a v i n g t w o p o l e s a n d t w o zeros i n t h e h i g h - f r e q u e n c y band; that is,
as a function of t h e c o m p l e x - f r e q u e n c y variable s i n t h e general f o r m
=
A(s) where A
M
= A F (s) M
H
(6.29)
is t h e m i d b a n d gain, w h i c h for t h e I C amplifiers w e are studying h e r e is equal to
the low-frequency or dc gain. T h e value of A
M
H (
'
(l
s/co )(l s/co )
+
zx
(l+s/co )(l
+
Pl
+
z2
s/co ) P2
Substituting s = jo) a n d t a k i n g t h e s q u a r e d m a g n i t u d e gives
c a n b e determined b y analyzing t h e amplifier I
equivalent circuit w h i l e n e g l e c t i n g t h e effect of t h e transistor internal c a p a c i t a n c e s — t h a t is,
P
H
by a s s u m i n g that they act as perfect o p e n circuits. B y taking t h e s e c a p a c i t a n c e s into account,
2
(l + co /co )(l zl
=
+
2
2
co /co ) z2
- - - - r — (I
6
In some cases there might be one or two'off-chip coupling capacitors to connect the entire IC amplifier to a signal source and/or a load.
2
, . . , 2
\F (jCO)\
+ (O /(0 ){\ PX
+ (0
/(0 ) P2
At this point we assume that the reader is familiar with the subject of s-plane analysis and the notions of transfer-function poles and zeros as well as Bode plots. A brief review of this material is presented in Appendix E.
5 7 4
CHAPTER 6
B y definition, at ft) = co , \F \ H
2
(1 + CO H/CO )(1 2
2
2
(l
2
+ a> /(o )(l H
+
<
°n\
_ 1
+
,
— V f f l
H
Z2
2
a) /a)l ) H
1 ^\
+ —
Zl
2
CO /CO )
+
Pl
2 ^ 1
1 , l
2
+
z1
=
CONSIDERATIONS
= 1 ; thus,
H
1
HIGH-FREQUENCY RESPONSE—GENERAL
6.4
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
2
4 , 2 2 (0 /(O O)
)+
H
zl
z2
^
... 2
°H[ — + — } + a /(o VFT) co J
C
H
PL
2
co
Pl
P2
P2
S i n c e t % is u s u a l l y smaller t h a n t h e frequencies of all t h e p o l e s and zeros, w e m a y neglect t h e t e r m s c o n t a i n i n g t % and solve for co to obtain H
CO , P
u
P l
COP-y
A> ,
U J
U J
P
2
A
7
Z
7
U J
I
Z
2
T h i s relationship can b e e x t e n d e d to any n u m b e r of p o l e s and zeros as
l^-(0
A
P1
J
P2
V
%
1
&
z
N o t e that if o n e of t h e p o l e s , say P , is d o m i n a n t , then co < x
J
2
a> ,
Pl
P2
a> ,..., P3
a> ,
co ,...,
zl
Z2
and E q . (6.36) r e d u c e s to E q . (6.32).
b.4.3 Using Open-Circuit Time Constants for the Approximate Determination of f
: high-frequency response of an amplifier is characterized by the transfer function
H
Z7 , ^
l-s/10
If the poles and zeros of the amplifier transfer function c a n b e d e t e r m i n e d easily, then w e
5
4
can determine F u s i n g t h e techniques above. In m a n y cases, h o w e v e r , it is not a simple matter
4
(l+5/10 )(l+^/4xl0 )
H
to d e t e r m i n e the p o l e s a n d zeros b y q u i c k h a n d analysis. In s u c h cases an a p p r o x i m a t e v a l u e Deiermine the 3-dB frequency approximately and exactly.
FORF c a n b e o b t a i n e d u s i n g t h e following m e t h o d . H
C o n s i d e r the function F (s)
(Eq. 6.30), w h i c h d e t e r m i n e s t h e high-frequency r e s p o n s e
H
Solution
of the amplifier. T h e n u m e r a t o r and d e n o m i n a t o r factors c a n b e m u l t i p l i e d out and 4
\.>iing that the lowest-frequency pole at 1 0 rad/s is two octaves lower than the second pole and a
F (s) H
expressed in t h e alternative f o r m
4
ade lower than the zero, we find that a dominant-pole situation almost exists and <% = 1 0 rad/s. etter estimate of <% can be obtained using Eq. (6.35), as follows:
/A/10
h
(
s
)
=
l+A^
+ A^
+ . - . + AY
l + b1s
+ bs
+ ••• +
2
^
b s" n
w h e r e t h e coefficients A and b are related to t h e frequencies of the zeros a n d poles, r e s p e c
+ 8
F
16X 1 0
8
10
1 0
= 9800 rad/s T h e exact value of co can be determined from the given transfer function as 9537 rad/s.
tively. Specifically, the coefficient b
x
is given b y
' / > ! = — + — (0
PL
(0
P2
+ ••• + —
(6.38)
CO
PN
H
Finally, w e show in Fig. 6.13 a B o d e plot and an exact plot for the given transfer function.
It can b e s h o w n [see G r a y and Searle (1969)] that t h e v a l u e of b can b e obtained b y consid
N o t e that this is a plot of the high-frequency response of the amplifier normalized relative to its
ering t h e v a r i o u s c a p a c i t a n c e s in t h e high-frequency e q u i v a l e n t circuit o n e at a t i m e w h i l e
midband gain. That is, if the midband gain is, say, 100 d B , then the entire plot should be shifted
reducing all other capacitors to zero (or, equivalently, r e p l a c i n g t h e m w i t h o p e n circuits).
upward by 100 d B .
That is, to o b t a i n t h e contribution of c a p a c i t a n c e Q w e r e d u c e all other capacitances to z e r o ,
x
5 7 5
CHAPTER 6
HIGH-FREQUENCY RESPONSE—GENERAL
6.4
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
r e d u c e t h e i n p u t signal source to zero, a n d d e t e r m i n e t h e resistance R
io
seen b y Q. This pro-
-gd
CONSIDERATIONS
D
cess is then r e p e a t e d for all other capacitors in t h e circuit. T h e v a l u e of b is c o m p u t e d by x
s u m m i n g t h e individual t i m e constants, called o p e n - c i r c u i t t i m e c o n s t a n t s ,
+
n = £Q/v
b
x
(6.39)
/ o
VY.)©
-i
R'L
gs
gs
+
I
c J=v
R
V {S) 0
¡=1
w h e r e w e h a v e a s s u m e d that there a r e n capacitors in t h e high-frequency e q u i v a l e n t circuit. This m e t h o d for d e t e r m i n i n g b is exact;
t h e a p p r o x i m a t i o n c o m e s a b o u t in u s i n g the
x
(a)
v a l u e of b to d e t e r m i n e 0) . Specifically, if t h e zeros are n o t d o m i n a n t a n d if o n e of the x
H
p o l e s , say P , is d o m i n a n t , then from E q . (6.38),
R
si% I — W V -
x
b =* —
"
x
G
+
+
(6.40)
G -o
/ • -"-sig
D
Ri,
:r't
B u t , also, t h e u p p e r 3 - d B frequency will b e a p p r o x i m a t e l y e q u a l t o co , l e a d i n g to the approximation PX
R„ ®* =
r
=
R
bi
Y
<
I
[?
P
(6-41)
1
(c)
(b)
C-,R \ i0
H e r e it s h o u l d b e p o i n t e d o u t that in c o m p l e x circuits w e u s u a l l y d o n o t k n o w w h e t h e r or not-
X
a d o m i n a n t p o l e exists. N e v e r t h e l e s s , u s i n g E q . (6.41) to d e t e r m i n e co n o r m a l l y yields
V
H
7
r e m a r k a b l y g o o d r e s u l t s even if a dominant p o l e does n o t exist. T h e m e t h o d will b e illustrated R
*Ü
b y an e x a m p l e .
-
R™
K
+
D
(Vgs + V ) x
V
- W V — T
+ R„ ;
>
m
I
Rgd—
Figure 6.14(a) shows the high-frequency equivalent circuit of a common-source M O S F E T mplifier. The amplifier is fed with a signal generator F
s i g
having a resistance R „. Resistance R is si
in
L
rain bias resistance R , and the FET output resistance r . Capacitors C and C D
0
iternal capacitances. For R
sig
, (d)
due to the biasing network. Resistance R' is the parallel equivalent of the load resistance R , the L
R',
Sm Vg.
g s
+ V R'L
gs
= 100 kQ, R = 4 2 0 kQ, C = C m
gs
.33 k Q , find the midband voltage gain, A
= VJV
M
sig
gd
gd
are the M O S F E T
= l pF, g = 4 mA/V, and R' = m
and the upper 3-dB frequency,
L
f.
FIGURE 6 - 1 4 Circuits for Example 6.6: (a) high-frequency equivalent circuit of a MOSFET amplifier; (b) the equivalent circuit at midband frequencies; (c) circuit for determining the resistance seen by C ; and (d) circuit for determining the resistance seen by C . gs
gd
H
Solution
of Fig. 6.14(c), from which w e find that
The midband voltage gain is determined by assuming that the capacitors in the M O S F E T model re perfect open circuits. This results in the midband equivalent circuit shown in Fig. 6.14(b), I rom which w e find
R
R
gs
R
= in\\
sii
= 420 k Q | | 1 0 0 k O = 80.8 kQ.
Thus the open-circuit time constant of C is gs
V M = Tf~ 0
A
sig
R 'P ia
=
~
R
"in "sig
R
(Sm D
T
gs
The resistance R
420 420 + 100. x 4 x 3.33 = - 1 0 . 8 V / V
gd
H
gs
gs
gd
seen by C
gs
gd
gs
= 1 x 10"
12
3
x 80.8 x 1Q = 80.8 ns
is found by setting C
gs
= 0 and short-circuiting V . T h e result-is sig
the circuit in Fig. 6.14(d), to which w e apply a test c u r r e n t / , . Writing a node equation at G gives
We shall determine co using the method of open-circuit time constants. The resistance R C is found by setting C
=CR
seen by
X
sig
V
V
R,„
R^,„
— _ ZM _ 111
j
= 0 and short-circuiting the signal generator V . This results in the circuit I Thus,
I The method of open-circuit time constants yields good results only when all the poles are real, as is the case in this chapter.
V
gs
= -IJi'
(6.42)
ER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.4
where R' = i ? | | i ? . A node equation at D provides in
sig
.1, V +V I X = Oaf f lV' M + ^ /
z
/
HIGH-FREQUENCY RESPONSE—GENERAL CONSIDERATIONS
h
.2,
+
D
L
+ V
Substituting for V from Eq. (6.42) and rearranging terms yields
2
Zl
1
X
1
h
Zl
. 1 ,
= KV
I Z
Vi
X
,2,
2
V = KV 2
1
gs
Yi
R
= R'+R[+
s
gd
R'
gm
R' = 1.16 M Q
L
X
Thus the open-circuit time constant of C
gd
is Z =Z/a-K),
Z = Z/\\-^
1
T
gd
C
=
(a)
R
gd d g
= Ixl0"
1 2
xl.l6xl0
6
= 1160 ns
2
(b)
FIGURE 6 . 1 5 The Miller equivalent circuit.
The upper 3-dB frequency co can n o w be determined from H
In typical situations Kis a gain factor that can b e positive or negative and that has a m a g n i t u d e usually larger than unity. This, however, is not an assumption for M i l l e r ' s t h e o r e m . M i l l e r ' s t h e o r e m states that i m p e d a n c e Z can b e replaced by t w o i m p e d a n c e s : Z con nected b e t w e e n n o d e 1 a n d ground and Z c o n n e c t e d b e t w e e n n o d e 2 a n d ground, w h e r e
1 0
3
»
~
+ r
T T
+
gs
T
gd
1
x
= 806 krad/s
2
( 8 0 . 8 + 1160) x 10
Z = Z/{l-K)
Thus,
(6.44a)
x
f
H
= ^ = 128.3 k H z In
and
Z =z/[l-^j
.
2
T h e m e t h o d of open-circuit time constants h a s a n important a d v a n t a g e i n that it tells the circuit d e s i g n e r which of the various capacitances is significant in determining the amplifier frequency r e s p o n s e . Specifically, the relative contribution of the various capacitances to the effective t i m e constant b is i m m e d i a t e l y o b v i o u s . F o r instance, i n the a b o v e e x a m p l e w e see that C is the d o m i n a n t capacitance i n d e t e r m i n i n g f . W e also note that, in effect to increase f either w e u s e a M O S F E T with smaller C or, for a given M O S F E T , w e reduce R b y using a smaller R' or R' . If R' is fixed, then for a given M O S F E T the only w a y to increase b a n d w i d t h is b y r e d u c i n g the load resistance. Unfortunately, this also decreases t h e m i d b a n d gain. This is a n e x a m p l e of the u s u a l trade-off b e t w e e n gain a n d b a n d w i d t h , a c o m m o n c i r c u m s t a n c e w h i c h w a s m e n t i o n e d earlier. x
gd
H
H
gd
gd
L
(6.44b)
to obtain the equivalent circuit s h o w n in F i g . 6.15(b). The proof of M i l l e r ' s theorem is achieved b y deriving E q . (6.44) as follows: In the original circuit of F i g . 6.15(a), the only w a y that n o d e 1 "feels the e x i s t e n c e " of i m p e d a n c e Z is through the current / that Z d r a w s a w a y from n o d e 1. Therefore, to k e e p this current unchanged in the equivalent circuit, w e m u s t c h o o s e the value of Z so that it d r a w s an equal current, x
which yields t h e value of Z in E q . (6.44a). Similarly, to k e e p the current into n o d e 2 unchanged, w e m u s t c h o o s e the value of Z so that x
6.4.4 Miller's Theorem
2
In o u r analysis of the high-frequency response of the c o m m o n - s o u r c e amplifier (Section 4.9), and of t h e c o m m o n - e m i t t e r amplifier (Section 5.9), w e e m p l o y e d a t e c h n i q u e for replacing the bridging capacitance (C or C^) b y an equivalent input capacitance. This very useful and effective t e c h n i q u e is based o n a general t h e o r e m k n o w n as M i l l e r ' s t h e o r e m , w h i c h w e n o w present. Consider the situation in Fig. 6.15(a). A s part of a larger circuit that is not shown, w e have isolated t w o circuit nodes, labeled 1 and 2, b e t w e e n which an i m p e d a n c e Z is connected. N o d e s 1 a n d 2 are also connected to other parts of the circuit, as signified b y the broken lines emanating from the t w o nodes. Furthermore, it is assumed that s o m e h o w it has been determined that the voltage at n o d e 2 is related to that at n o d e 1 b y gs
y
2
=
KV
X
(6.43)
_ 0-V Z
2
2
_ 0-KV
x
Z
2
_
_
V -KV 1
l
Z
which yields the expression for Z in E q . (6.44b). A l t h o u g h n o t highlighted, the Miller equivalent circuit derived a b o v e is valid only as long as the rest of the circuit r e m a i n s u n c h a n g e d ; otherwise t h e ratio of ,V to V m i g h t change. It follows that the Miller equivalent circuit cannot b e used directly to determine the output resistance of an amplifier. This is b e c a u s e in d e t e r m i n i n g output resistances it is implicitly a s s u m e d that the source signal is r e d u c e d to zero a n d that a test-signal source (voltage or current) is applied to the output terminals—obviously a major change in the circuit, rendering the Miller equivalent circuit n o longer valid. 2
2
x
;
„
579
SSO
;
.
.
;
CHAPTER 6
SINGLE-STAGE INTEGRATED-ClRCUIT AMPLIFIERS
HIGH-FREQUENCY RESPONSE—GENERAL CONSIDERATIONS
6.4
The voltage gain can be found as follows: V Figure 6.16(a) shows an ideal voltage amplifier having a gain of - 1 0 0 V/V with an impedance Z connected between its output and input terminals. Find the Miller equivalent circuit when Z is (a) a 1-MQ resistance, and (b) a 1-pF capacitance. In each case, use the equivalent circuit to determine V „ / V „ .
v
0
V
V' - -100 x v,.y z
s i g
sig
m
Z,
0
-
9 , 9
= _100 x
1
l
R
+
dg
= -49.7 V/V
9.9+10
-12
oi
(b) For Z as a 1 -pF capacitance—that is, Z = 1 A C = 1 A x 1 x 10
—applying Miller's theorem
allows us to replace Z by Z j and Z , where 2
Z, = — = 1-X Z _ l K It follows that Z j is a capacitance 101C = The resulting equivalent circuit is shown found as follows: 1
z
=
=
2
l
(a)
y
« -
=
y
*
v
l
/
s
C
=
1A(101C)
1 + 100 J 1_ 1.01
1 i-(l.OlC)
=
^ 101 p F and that Z is a capacitance 1.01C = 1.01 pF. in Fig. 6.16(c), from which the voltage gain can be - 2
-
-100-
' ' ^
-
-100
-100
=
12
1 + 5 x 101 x 1 x 1 0 " x 10 x 1 0
3
-100 1 + s x 1.01 x 10
6
This is the transfer function of a first-order low-pass network with a dc gain o f - 1 0 0 and a 3-dB frequency /
3 d B
of
/ =
1
3dB
= 1 5 7 . 6 kHz
2^x1.01x10
F r o m E x a m p l e 6.7, w e o b s e r v e that t h e M i l l e r r e p l a c e m e n t of a f e e d b a c k or bridging resistance results, for a n e g a t i v e K, in a smaller resistance [by a factor (l-K)] at the input. If the feedback e l e m e n t is a capacitance, its v a l u e is multiplied b y (l-K) to obtain the equivalent c a p a c i t a n c e at t h e input side. T h e multiplication of a f e e d b a c k c a p a c i t a n c e b y (l-K) is referred to as Miller multiplication or Miller effect. W e h a v e encountered the Miller effect in the analysis of the C S and C E amplifiers in Sections 4.9 and 5.9, respectively.
(c) FIGURE 6 . 1 6 Circuit for Example 6.7.
Solution (a) For Z = 1 M O , employing Miller's theorem results in the equivalent circuit in Fig. 6.16(b), where Z, = - £ - = ' l-K Z
2
1
0
0
0
6.9
A direct-coupled amplifier has a dc gain of 1000 V/V and an upper 3-dB frequency of 100 kHz. Find the transfer function and the gain-bandwidth product in hertz.
k
° = 9.9 k Q 1 + 100,.
= — — = _LMR = o.99 M f l 1 - 1+ — K 100
Ans.
1
0
0
0
:10
s
Hz
"¡81
582
1-5
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6 5 THE C O M M O N - S O U R C E A N D C O M M O N - E M I T T E R AMPLIFIERS W I T H ACTIVE L O A D S
6.10 The high-frequency response of an amplifier is characterized by two zeros at s = °° and two poles at Op i and OJ . For m = kco , find the value of A: that results in the exact value of a„ being 0 . 9 ® ^ . Repeat for co = 0 . 9 9 c o . P2
P2
„,„.1
A
Pl
1
H
1—ov„
Pl
Ans. 2 . ~ v o.s.s
6.11 For the amplifier described in Exercise 6.10, find the exact and approximate values (using Eq. 6.36) of co (as a function of co {) for the cases /c = 1,2, and 4. H
- o v„
P
Ans. 0.64, 0 . 7 1 : 0.84, 0.89; 0.95, 0.97
OA
Vj o—
6.12 For the amplifier in Example 6.6, find the gain-bandwidlh product in megahertz. Find the value of R' that will result in f = 180 kHz. Find the new values of the midband gain and of the gain-bandwidth product. (
H
Ans.
M i l / : 2.23 k i i :
".2 \
\ : i.3u M i l /
m
h
(b)
(a)
6.13 Use Miller's theorem to investigate the performance of the inverting op-amp circuit shown in Fig. E6.13. Assume (he op amp to be ideal except for having a finite differential gain, A. Without using any knowl edge of op-amp circuit analysis, find R- , V V , and V „ / % . for each of the following V a l u e s of A « 10 V/V. 100 V/V. 1000 V/V. and 10.000 V/V. Assume = " I V. a
FIGURE 6 . 1 7 ( ) Active-loaded common-source amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit diagram and using the small-signal model explicitly. a
0
VvV
examples of such circuits in later chapters. For the time-being, howeyef, we shall assume that the MOSFET is biased to operate in the saturation region. Small-signal analysis of t h e current-source-loaded C S amplifier is straightforward and is illustrated in Fig. 6.17(b). H e r e , along with t h e e q u i v a l e n t circuit m o d e l , w e s h o w the tran sistor with its r extracted and displayed separately and with the analysis performed directly on the circuit. F r o m F i g . 6.17(b) w e see that for this C S amplifier, 0
J
8
R = co
(6.45a)
t
A
= -g r
w
m
(6.45b)
0
R =r 0
W e note that | A \ vo
Ans.
(6.45c)
0
in Eq. (6.45b) is the m a x i m u m voltage gain available from a c o m m o n -
source amplifier, n a m e l y the intrinsic g a i n of t h e M O S F E T , ^
10 V/V 100 V/V 1000 V/V 10.000 V/V
.1(1" i > .).""(>
1
LI
476 90 9.9 0.999
mV mV mV mV
-4.76 V -9 V
•
V
A
q
0
= gr m
(6-46)
0
- -."(I \
\
Recall that in Section 6.2 w e discussed in s o m e detail t h e intrinsic gain A
'A
\
\
Table 6.3 formulas for its determination.
\
.;.-\
0
a n d presented in
-9.99 V
2
6.14 Find A,, for an N M O S transistor fabricated in a 0.4-um C M O S process for which k' = 200 , u A / V and V' = 20 V/,um. The transistor has a 0.4-,um channel length and is operated with an overdrive voltage of 0.25 V. What must W be for the N M O S transistor to operate at I = 100 jitA? Also, find the values of g, and r . Repeat for L = 0.8 pirn. n
A
>.5 THE COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS WITH ACTIVE LOADS
D
::
n
Ans. 64 V / V ; 6.4 fim; 0.8 m A / V ; 80 k Q ; 128 V / V ; 12.8 ,um; 0.8 m A / V ; 160 k Q
6.5.1 The Common-Source Circuit Figure 6.17(a) s h o w s the m o s t basic IC M O S amplifier. It consists of a grounded-source M O S transistor with t h e drain resistor R r e p l a c e d b y a constant-current source I. A s w e shall see shortly, the current-source load can be i m p l e m e n t e d using a P M O S transistor and is there fore called an active load, and the C S amplifier of F i g . 6.17(a) is said to b e active-loaded. D
Before c o n s i d e r i n g the small-signal operation of t h e active-loaded C S amplifier, a word on its dc bias design is in order. Obviously, Qi is biased,at I = I, but what determines the de voltages at the drain and at the gate? Usually, this circuit will b e part of a larger circuit in which negative feedback is utilized to fix t h e values of V and V . W e shall encounter D
DS
rs
6.5.2 CMOS Implementation of the Common-Source Amplifier A C M O S circuit i m p l e m e n t a t i o n of t h e c o m m o n - s o u r c e amplifier is s h o w n in Fig. 6.18(a). This circuit is based on that s h o w n in Fig. 6.17(a) with the load current-source I implemented using transistor Q . T h e latter is t h e output transistor of the current mirror f o r m e d b y Q and Q and fed with t h e bias current /^gp. W e shall a s s u m e that Q and Q are m a t c h e d ; thus the 2
3
2
2
3
For the definition of the parameters used to characterize amplifiers, the reader should consult Table 4.3.
583
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.5
THE C O M M O N - S O U R C E A N D C O M M O N - E M I T T E R AMPLIFIERS WITH ACTIVE
characteristic of the load device will b e that s h o w n in Fig. 6.18(b). T h i s is simply t h e i -v characteristic curve of t h e p - c h a n n e l transistor Q for a constant source-gate voltage V . T h e v a l u e of V is set b y p a s s i n g t h e reference bias current I through Q . Observe that, as expected, Q b e h a v e s as a current source w h e n it operates in saturation, w h i c h in turn is obtained w h e n v = v e x c e e d s ( V - | V | ) , w h i c h is the m a g n i t u d e of the overdrive voltage at w h i c h Q and Q are operating. W h e n Q is in saturation, it exhibits a finite incre mental resistance r , D
SD
2
SG
SG
mF
3
2
SD
2
SG
lp
3
2
o 2
(6.47) where V
A2
is the E a r l y v o l t a g e of Q . In other w o r d s , the current-source load is n o t ideal b u t 2
has a finite output resistance equal to the transistor
r. 0
Before p r o c e e d i n g to determine the small-signal voltage gain of the amplifier, it is instructive to e x a m i n e its transfer characteristic, v
versus v,. This can b e d e t e r m i n e d using
0
the graphical construction s h o w n in Fig. 6.18(c). H e r e w e h a v e sketched the i ~v D
charac
DS
teristics of the amplifying transistor Q and s u p e r i m p o s e d the load c u r v e o n them. T h e latter x
is simply the i-v c u r v e in F i g . 6.18(b) "flipped a r o u n d " and shifted V
DD
zontal axis. N o w , since v
G s l
= v , each of the i - v 7
D
volts along the hori
curves corresponds to a particular value
D S
of V[. T h e intersection of e a c h particular c u r v e with the load c u r v e gives the corresponding value of v
D S l
, w h i c h is equal to v . T h u s , in this w a y , w e can obtain the v -v 0
0
characteris
l
tic, point b y point. T h e resulting transfer characteristic is sketched in Fig. 6.18(d). A s indi cated, it has four distinct s e g m e n t s , labeled I, II, III, and IV, each of w h i c h is obtained for o n e of the four c o m b i n a t i o n s of the m o d e s of operation of Q and Q , w h i c h are also indicated in x
2
the diagram. N o t e also that w e h a v e labeled t w o important breakpoints on the transfer charac teristic (A and B ) in c o r r e s p o n d e n c e with the intersection points (A and B ) in Fig. 6.18(c). W e urge the r e a d e r to carefully study the transfer characteristic and its various details. N o t surprisingly, for amplifier operation s e g m e n t III is t h e o n e of interest. O b s e r v e that in region III the transfer c u r v e is a l m o s t linear and is very steep, indicating large voltage gain. In regi on III b o t h t h e amplifying transistor Q and the l o a d transistor Q are operating x
2
in saturation. T h e e n d points of region III are A and B : At A, defined b y v
0
Q enters the triode r e g i o n , and at B , defined b y v 2
= v - V,
0
I
=V
DD
-
V , 0V2
Q enters t h e triode region.
tn
x
W h e n the amplifier is biased at a point in regi on III, the small-signal voltage gain can b e determined b y r e p l a c i n g Q with its small-signal m o d e l and Q x
r. o2
2
T h e output r e s i s t a n c e of Q
2
with its output resistance,
constitutes t h e l o a d resistance of Q,. T h e v o l t a g e gain
A
v
can be found by substituting the results from E q s . (6.45) into ßi
Cutoff Saturation Triode Saturation Saturation Triode Saturation
A
»
s
=
-
A
( 6
» F T i r
K
=
=-g
-(8,nir„y)-^r
+
B l
(r
0 l
II
r ) o2
(6.49)
r
ol
indicating that, as expected, A will be l o w e r in m a g n i t u d e than t h e intrinsic 'gain of Q 8mir - F o r the case r = r , A will b e g r /2. T h e result in Eq, (6.49) could, of course, h a v e b e e n o b t a i n e d directly b y multiplying g V; b y the total resistance b e t w e e n the output n o d e a n d g r o u n d , r \\ r. v
m
4 8 )
to obtain
< o2
V
-
Vr, V,„ = Vnn + K,
ol
(d)
o2
u
o l
v
ml ol
m
oX
FIGURE 6 . 1 8 The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q , (c) graphical construction to determine the transfer characteristic; and (d) transfer characteristic. 2
l
o2
T h e C M O S c o m m o n - s o u r c e amplifier can b e d e s i g n e d to p r o v i d e voltage gains of 15 to 100. It exhibits a v e r y h i g h input resistance; h o w e v e r , its output resistance is also high.
5
CHAPTER 6 S I N G L E - S T A G E I N T E G R A T E D - C I R C U I T A M P L I F I E R S
THE C O M M O N - S O U R C E A N D C O M M O N - E M I T T E R AMPLIFIERS WITH ACTIVE LOADS
•.87
which by trial-and-error yields
T w o final c o m m e n t s need to b e m a d e before l e a v i n g the c o m m o n - s o u r c e amplifier: 1. T h e circuit is n o t affected b y t h e b o d y effect since t h e s o u r c e terminals of both Q and Q are at signal g r o u n d .
\V \
= 0.53 V
0V3
1
2
2. T h e circuit is usually part of a larger amplifier circuit (as will b e s h o w n in Chapters 7 a n d 9), and n e g a t i v e f e e d b a c k is utilized to e n s u r e that t h e circuit in fact operates in r e g i o n III of the amplifier transfer characteristic.
Thus, V
= 0.6 + 0.53 = 1.13 V
V
=V -
SG
and 0A
V
DD
= 2.47 V
0V3
\
.
To find t h e corresponding value of v , V , w e derive an expression for v versus v, i n t
IA
0
l
region III. Noting that in region III Q and Q are in saturation and obviously ebnduct equal cur x
2
rents, we can write Consider the C M O S common-source amplifier in Fig. 6.18(a) for the case V = 3 V, V = \V \ = 0.6 V , p C = 200 pAIV , and p C = 65 pA/V . For all transistors, L = 0.4 /im'and W= 4 /im. Also, V = 20 V,\V \ = 1 0 V, and 7 = 100 pA. Find the small-signal voltage gain. Also, find the coordinates of the extremities of the amplifier region of the transfer characteristic— that is, points A and B . DD
2
tp
n
p
An
l
D\
2
0X
=
l
D2
0X
R E F
Ap
s H i J ^ ' ^ l ^ r a r r " \ j )
K
y
s
c
\v \
2
Ap
Substituting numerical values, w e obtain
Solution im\
-
,|2£«
j
ch can be manipulated to the form
,-JREF
w =7.69-65.77(w -0.6) o
2 x 200 x ~ x 100 = 0.63 m A / V 0.4
2
(6.51)
7
I h is the equation of segment III of the transfer characteristic. Although it includes v , the reader s
1
should not be alarmed: Because region III is very narrow, v changes very little, and the charac l
^
_2Cy_V_
=
=
2
0
0
k
teristic is nearly linear. Substituting v
n
= 2.47 V gives the corresponding value of v ; that is, V, =
0
I
0.1 m A
m
;
0.88 V. To determine the coordinates of B, w e note that they are related by V
0B
Xas
io v
=
Im
stituting in Eq. (6.51) and solving gives V
IB
= 100 k Q
= 0.93 V and V
0B
0.1 m A
Av =V -V I
v
=
ol
[n
= 0.33 V. T h e width of the
IB
= 0.05 V
IA
and the corresponding output range is
-S ii.r \\r ) m
IB
amplifier region is therefore
Thus, A
A
= V - V . Sub
o2
Av
= - 0 . 6 3 ( m A / V ) x ( 2 0 0 | | 100)(kQ) = - 4 2 V/V
=V
0
0 B
-V
0 A
= -2.14 V
Thus the "large-signal" voltage gain is The extremities of the amplifier region of the transfer characteristic (region III) are found as follows (refer to Fig. 6.18): First, w e determine V of Q and Q corresponding to I = I -p = 100 pA using SG
2
3
D
^ 2 Apj
w
=
_2^4 0.05
=
4
2
.
8
V
/
v
which is very close to the small-signal value of - 4 2 , indicating that segment III of the transfer characteristic is quite linear.
Thus, i „ « C4V , i
where j V
0V3
o
o
=
^
n
^
j
!
af, . 0.6 + [ y y
o l / 3 |
^
^
[ is the magnitude of the overdrive voltage at which Q and Q are operating, and we 3
have used the fact that, for g , V 3
SD
2
= V . Equation (6.50) can b e manipulated to the f o r m SG
615 A C M O S c o m m o n - s o u r c e amplifier fabricated in a 0.18-mn technology has W/L = 7.2 tmi/0.36 / a n kp = 86 u A / V ' REF = 100 pA, V' „ = 5 V / / t m . and \V \ = for all transistors, k'„ = 387 u A / V A
6 V/pm. Find g„,,, r„ „ r . and the voltage gain o2
Ans. 1.25 mA/V; 1 8 k Q : 2 1 . 6 k Q ; - 1 2 . 3 V/V 0.29 = | V
i (l+0.09|y ^|) 2
O F 3
o
Ap
588
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.6
H I G H - F R E Q U E N C Y RESPONSE OF T H E CS A N D CE A M P L I F I E R S
v
cc
-o u„
+ '.r„
Vj O -
v„ :
Y
R'L
T
FIGURE 6 . 2 0 High-frequency equivalent-circuit model of the common-source amplifier. For the commonemitter amplifier, the values of V and R are modified to include the effects of r aijtd r,; C is replaced by C , V by V„, and C by C . sig
(a)
(b)
x
FIGURE 6 . 1 9 (a) Active-loaded common-emitter amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit and using the hybrid-^ model explicitly.
gs
gd
Ag
K
gs
u
T h e input-signal source is represented b y V and R . In s o m e cases, h o w e v e r , V and R w o u l d b e modified values of t h e signal-source v o l t a g e and internal resistance, t a k i n g into account other resistive c o m p o n e n t s such as a bias resistor R or R , t h e B J T resistances r and r„, etc. W e h a v e seen e x a m p l e s of this k i n d of circuit simplification in Sections 4.9 and 5.9. T h e l o a d resistance R represents t h e c o m b i n a t i o n of an actual l o a d resistance (if one is c o n n e c t e d ) and t h e output resistance of t h e current-source load. T o avoid loss of gain, R is usually o n t h e s a m e order as r . W e c o m b i n e R with r and d e n o t e their parallel equivalent R[. T h e load c a p a c i t a n c e C represents the total c a p a c i t a n c e b e t w e e n drain (or collector) and g r o u n d ; it i n c l u d e s the drain-to-body capacitance C (collector-to-substrate capacitance), the input c a p a c i t a n c e of a succeeding amplifier stage, and in s o m e cases, as w e shall see in later chapters, a deliberately i n t r o d u c e d capacitance. In I C M O S amplifiers, C can be relatively substantial. sig
sig
sig
sia
6.5.3 The Common-Emitter Circuit
G
T h e active-loaded c o m m o n - e m i t t e r amplifier, s h o w n in F i g . 6.19(a), is similar to t h e activeloaded c o m m o n - s o u r c e circuit studied a b o v e . H e r e also, the bias-stabilizing circuit is not shown. Small-signal analysis is similar to that for the M O S case and is illustrated in Fig. 6.19(b). T h e results are
B
x
L
L
0
L
a
L
Ri = r
(6.52a)
n
db
Av„ = S r m
R
0
(6.52b)
0
= r
(6.52c)
a
w h i c h e x c e p t for the rather l o w input resistance r are similar to the M O S F E T case. Recall, h o w e v e r , from t h e c o m p a r i s o n of Section 6.2 that t h e intrinsic gain g r of t h e B J T is m u c h h i g h e r t h a n that for t h e M O S F E T . T h i s a d v a n t a g e , h o w e v e r , is c o u n t e r b a l a n c e d b y the p r a c t i c a l l y infinite input resistance of the c o m m o n - s o u r c e amplifier. F u r t h e r c o m p a r i s o n s of t h e t w o amplifier types w e r e p r e s e n t e d in Section 6.2.
L
n
m
0
6.6.1 Analysis Using Miller's Theorem In situations w h e n R is relatively large and C is relatively small, M i l l e r ' s t h e o r e m can b e used to obtain a q u i c k but a p p r o x i m a t e estimate of t h e 3-dB frequency f . W e h a v e already done this in Section 4.9 for t h e C S amplifier a n d in Section 5.9 for the C E amplifier. T h e r e fore, here w e will only state the results. Figure 6.21 s h o w s t h e a p p r o x i m a t e equivalent circuit obtained for the C S case, from w h i c h w e see that t h e amplifier has a d o m i n a n t p o l e f o r m e d sig
L
H
i.16 Consider the active-loaded C E amplifier when the constant-current source / i s implemented with npnp transistor. Let / = 0.1 niA, \V \ = 50 V (for both the npn and thepnp transistors), and B = 100. F i n e i?,, »',, (for each transistor), g , A , and the amplifier voltage gain. Ans. 25 kit 0.5 Mil: 4 m . \ / V : 2000 V/V: 1000 Y ' Y A
m
0
,6 HIGH-FREQUENCY RESPONSE OF THE CS AND CE AMPLIFIERS W e n o w consider the high-frequency r e s p o n s e of thecactive-loaded c o m m o n - s o u r c e and ' c o m m o n - e m i t t e r amplifiers. Figure 6.20 s h o w s t h e high-frequency equivalent circuit of the c o m m o n - s o u r c e amplifier. This equivalent circuit applies equally well to t h e C E amplifier with a simple relabeling of components: C w o u l d b e replaced b y C , C by C and obviously V ^ vx. gs
gs
n
gd
/ r
Cn FIGURE 6 . 2 1 Approximate equivalent circuit obtained by applying Miller's theorem while neglecting C and the load current component supplied by C . This model works reasonably well when ^ is large and the amplifier high-frequency response is dominated by the pole formed by R and C .
L
gd
s i g
sig
m
5 9 0
i'c^i
CHAPTER 6
S I N G L E - S T A G E IN TEG RATE D - C I R C U IT A M P L I F I E R S
by R
ii$
H I G H - F R E Q U E N C Y RESPONSE O F T H E CS A N D CE A M P L I F I E R S
6.6
and C . Thus,
Thus the effective t i m e - c o n s t a n t b or % c a n b e found a s
i n
x
1
M
V •
=
%
(6.53)
s
CgsRgs
+ CR gd
= C R^ sig
1+
and the 3-dB frequency f =
gd
+ g R' )
sig
m
H
(6.57)
C R'
L
L
L
(6.58)
2KT
H
1
(6.54)
2KC R in
+ R' } +
L
1
R
~8m L is given b y
= (0 /2n
l
is
H
H
C
_
where
a n d t h e 3-dB frequency f
l
+ C [R (l
gs
v
+ c r
gd
m-
Por situations in w h i c h C is substantial, this a p p r o a c h yields a better estimate of f L
•¿3
sig
where
than
H
that obtained u s i n g t h e Miller e q u i v a l e n c e ( s i m p l y b e c a u s e in t h e latter c a s e w e c o m p l e t e l y v
neglected C ). L
Ci„ =
C +C (l+g R' ) g5
gd
m
(6.55)
L
"if
6.6.3 Exact Analysis
„
6.6.2 Analysis Using Open-Circuit Time Constants
The a p p r o x i m a t e analysis p r e s e n t e d a b o v e p r o v i d e s insight r e g a r d i n g t h e m e c h a n i s m b y
T h e m e t h o d of open-circuit t i m e constants p r e s e n t e d in Section 6.4.3 c a n b e directly applied
which and t h e extent to w h i c h t h e v a r i o u s c a p a c i t a n c e s limit t h e high-frequency gain of t h e
to t h e C S equivalent circuit of F i g . 6 . 2 0 , a s illustrated in F i g . 6.22, from w h i c h w e see that
CS (and C E ) amplifiers. N e v e r t h e l e s s , given that t h e circuit of F i g . 6 . 2 0 is relatively s i m p l e ,
t h e resistance seen b y C , R
it is instructive t o also p e r f o r m a n e x a c t a n a l y s i s . T h i s is i l l u s t r a t e d i n F i g . 6 . 2 3 . A n o d e
9
gs
by C
gd
gs
= R
a n d that seen b y C
sig
L
is R' . T h e resistance R L
d
seen
equation at t h e d r a i n p r o v i d e s
c a n b e found b y a n a l y z i n g t h e circuit i n F i g . 6.22(b) w i t h t h e result that R
gd
=
R Jl+g R' )+Rl si
m
L
sCgdWg,
(6.56)
~ V„) = g Vg + m
fr L
S
+
1
sC V L
0
K
which c a n b e m a n i p u l a t e d to t h e f o r m v
= S S
-V
l+s(C +C )R'
a
L
gd
L
(6.59)
l
gmK
~sC /g gd
m
A loop equation at t h e i n p u t yields G -o
y. v
in which w e c a n substitute for
= IR . + V
Slg
= sC V gs
R„
1
* l**Slg
Y
gs
from a n o d e e q u a t i o n at G , gs
+ sC (V gd
-
gs
V) 0
— R
sie
>
sc (v -v )
Cx
gi
gs
0
Q
D
-AAA
(b)
(a)
i<
R •"-sig
- W r
G -o
D
Iii ,
+
v
öm* gs
4
>
r\
+
\sC V
4 4= I
L
Q
p
v
0
WmBm
V„ = 0
FIGURE 6 . 2 3 Analysis of the CS high-frequency equivalent circuit.
(c) FIGURE 6 . 2 2 Application of the open-circuit time-constants method to the CS equivalent circuit of Fig. 6.20.
'Exact" only in the sense that we are not making approximations in the circuit-analysis process. The reader is reminded, however, that the high-frequency model itself represents an approximation of the device performance.
'91
592
k
„
H I G H - F R E Q U E N C Y RESPONSE O F T H E CS A N D CE A M P L I F I E R S
6.6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
CHAPTER 6
time-constants m e t h o d (Section 6.4.3). N e x t , d e n o t i n g t h e frequencies of the t w o poles co
to obtain
Pl
and (O , w e c a n express t h e d e n o m i n a t o r p o l y n o m i a l D(s) as n
F
sig
=V [l+
s(C
ss
+ C )R ]
gs
gd
-
slg
sC R V gd
sig
0
f 1 + — Yl + —
D(s)=
W e c a n n o w substitute in this equation for V from E q . (6.59) t o obtain a n equation in V and V that can b e arranged to yield the amplifier g a i n as gs
0
sig
1 K_
/ J _ + J_V^— ^.(Dpi (o J (o a>
+
=
v
»s
1 + s{[C
+C
gs
gd
(1 + g R' )]R m
L
d
+ (C + C )R }
$lg
L
P1
gd
+ s\(C
L
L
+ C )C gd
+
gs
Now, if (0
C C ^~ [J L
gd
P2
R
S> G)pi—that is, the pole at co
D
{
s
P1
Equating the coefficients of the s t e r m in d e n o m i n a t o r p o l y n o m i a l of Eq. (6.60) to that of the s term in Eq. (6.65) gives
a
(6.61)
P 1
f
gd
m
sis
Since g is usually large a n d C is usually small, f thus h a s negligible effect o n the v a l u e of f .
C )R'
L
gd
is n o r m a l l y a very h i g h frequency and
z
It is useful at this point t o s h o w a s i m p l e m e t h o d for finding t h e v a l u e of s at which o = 0 — t h a t i s , s . F i g u r e 6.24 s h o w s t h e circuit at s = s . B y definition, V = 0 and a n o d e equation at D yields z
z
0
ic + Cg d + g Rp]R*,+
n
gs
d
(CL
m
[{C +C )C L
is not zero ( w h y not?), w e c a n d i v i d e b o t h sides b y V
(6.63)
gd
+
gs
+ Cg )R' S
2
n
0X
L
gd
L
lt
0X
R
gs
gd
6
6
7
)
P2
An
F
L
L
P1
E
S I G
2
z
H
H
Solution
m
D
jo
1D = ' R E F = 100 M = l^nC [j
'• • I
R
: 'L
ox
I Thus, ioo
=l
x 3 8 7 x
(olK
which results in The CS circuit at s = s . The output voltage V„ = 0, enabling us to determine s from a node z
(
si%
2
p
Ap
L
D
©
L
C C \R' R
A CMOS common-source amplifier of the type shown in Fig. 6.18(a) has W/L = 7.2 ^m/0.36 pm for all transistors, p C = 387 pAJY , Li C = 86 pA/V , 7 = 100 pA, V' = 5 V/pm, and \V' \ = 6 V/pm. For Q C = 2 0 f F , C = 5 f F , C = 25 f F , and 7 ? = l O k Q . Assume that C includes all the capacitances introduced b y Q at the output node. Find f using both the Miller equivalence and the open-circuit time constants. Also, determine the exact values of f , f , and f and hence provide another estimate for f .
Before considering t h e poles, w e should n o t e that i n E q . (6.60), as s g o e s t o w a r d zero, K/Vsig a p p r o a c h e s t h e dc gain (-g R' ), as should b e t h e case. L e t ' s n o w take a closer look at the denominator polynomial. First, w e observe that the coefficient of the s term is equal to the effective time-constant % obtained using the open-circuit time-constants method as given b y Eq. (6.57). A g a i n , this should h a v e b e e n e x p e c t e d since it is t h e basis for t h e open-circuit
AAA
L
to obtain
C gd
sig
gd
2
V
+
L
L
H
m
(6.66) (C +
where the approximation is that involved in Eq. (6.65). Note that the expression in Eq. (6.66) is identical to the result obtained using open-circuit time constants and a little different from the result obtained using the Miller equivalence, t h e difference being t h e term (C +C )R' related to t h e capacitance at the output, which w a s ignored in the original (simple) Miller deri vation. Equating the coefficients of s in Eqs. (6.60) and (6.65) and using Eq. (6.66) gives the frequency of the second pole:
(6.62) gd
1 + g R[)]R +
+ C {\
d
z
m
= ~ [C
gs
T h a t is, it is on the positive real axis of the s-plane a n d h a s a frequency co ,
FIGURE 6 . 2 4 equation at D.
(6.65)
CO (Op2
Pi
sig
C „
gs
+ -^1—
)
CO
T h e transfer function in Eq. (6.60) indicates that the amplifier has a second-order denominator, a n d h e n c e t w o poles. N o w , since the n u m e r a t o r is of the first order, it follows that one of the t w o transmission zeros is at infinite frequency. T h i s is readily verifiable b y noting that as s a p p r o a c h e s °°, (V / V ) approaches zero. T h e s e c o n d zero is at
N o w , since V
(6-64) P2
is d o m i n a n t — w e c a n a p p r o x i m a t e D(s) as
Pl
(6.60)
0
Pl
m
z
M
V =0A6V ov
2
)V
0V
*^±Z
5 9 3
SINGLE-STAGE
CHAPTER 6
INTEGRATED-CIRCUIT
AMPLIFIERS 6.6
HIGH-FREQUENCY
RESPONSE O F T H E CS A N D CE A M P L I F I E R S
£ • "J
Thus, To determine the exact locations of the zero and the poles, w e use the transfer function in J o _ V /2
=
ov
100 HA (0.16/2) V
=
L
2
Eq- (6-60). T h e frequency of the zero is given by Eq. (6.62):
^
5
3
g = _i_ 1 1.25 x l O " = 4 0 G H z f_ = J 1- £™ m
5x0.36 0.1
=
Z
fl
=
1
2
D
J
Q
z
2KC
2 * 5 x 1 0 - ' *
gd
F1
P1
are found as the roots of the equation obtained b y equating the
denominator polynomial of Eq. (6.60) to zero:
= 21.6 k Q
0.1
I
k
The frequencies c o and (o
V sx v 0.36 n -if. I AP\I _ 6
'°
8
1 + 1.16 x 10" 5 + 0.0712 x 1 0 " ' V = 0 9
r
* i = oi H ^ 2 = 1 8 1 1 2 1 . 6 = 9.82 k Q = -g R[
A
M
The result is
= - 1 - 2 5 x 9.82 = - 1 2 . 3 V / V
M
fpi = 145.3 M H z Using the Miller equivalence: and C=
C
IN
+
GS
f
C (\+ R[) GD
8M
Since f ,
= 20 + 5 ( 1 + 12.3)
z
f
P2
> fpi, a good estimate for /
1
Finally, w e note that the estimate of f exact value. Similarly, t h e estimate of f
SIS
H
1 2TCX
is
obtained using Eq. (6.66) is about 5 % lower than the
Pl
2xC R ^ s i g IN
; /
. / / / = . / > ! - 145.3 M H z
= 86.5 fF fn =
= 2.45 G H z
P2
than the estimate found using the exact value of
= 184 M H z
86.5xlO~
1 5
xlOxl0
obtained using open-circuit time constants is 5 % lower f. Pl
3
Using the open-circuit time-constants method: R
GS
R
= R
= 10 k Q
SIG
»
v ^ 1 7 For the C S amplifier in Example 6.9, using the value of f determined by the exact analysis, find the = > ;*f gain-bandwidth product. Also, convince yourself that this is the frequency at which the gain magnitude *s --.f--'. reduces to ttni ly.
,
d=R* a+g R¿)+R
S
g
m
L
= 10(1 + 12.3) + 9.82= 142.8 k Q R
H
Ans. G B W = 1.79 G H z ; since this is lower than f ,
c = R'L = 9.82 k Q
P2
then f = 1.79 G H z t
6.18 A s a w a y t o trade gain for bandwidth, the designer of the CS amplifier in Example 6.9 connects a load resistor at the output that results in halving the value of R[. Find the n e w values of \A \, f (using ff/S: f . of Eq. 6.66). and ./,.
Thus,
M
a
r
r
g s
z
gd
= C R
= 20 x 10~
= C R
- 1 5
GS
GD
GS
= 5 x 10
GD
15
3
x 10 x 1 0 = 2 0 0 ps
Ans. 6.15 V/V: 226 M H z : 1.39 GHz 6.19 As another way to trade do gain for bandwidth, t h e designer of the C S a m p l i f i e r in Example 6.9 decides to operate the amplifying transistor at double the value of V by increasing the bias current fourfold (i.e.,to 4 0 0 piA), Find t h e n e w values of g , Ri,\A^ f ,f , a n d . / , . U s e t h e approximate formula for fpi given in Eq. (6.66).
3
x 142.8 x 1 0 = 7 1 4 p s
ov
T= C
CR L
= 25 x 1 0 ~
CL
which can b e summed to obtain x
H
3
x 9.82 x 1 0 = 246 ps
m
as
% = from which w e find the 3-dB frequency
f n = ^ - = H 2nr
15
Pl
H
Ans. 2.5 m A / V ; 2.46 k Q ; 6.15 V/V; 252 M H z ; 252 M H z ; 1.55 G H z +V+T
C
= 1160 p s
i
f,
6.6.4 Adapting the Formulas for the Case of the CE Amplifier
H
Adapting the f o r m u l a s p r e s e n t e d a b o v e t o t h e c a s e o f t h e C E amplifier is straightforward. First, note from F i g . 6.25 h o w V a n d i ? are modified t o take into a c c o u n t t h e effect of r and r „
r =137 MHz 2
sig
2K x 1 1 6 0 x 1 0
W e note that this is about 2 5 % lower than the estimate obtained using the Miller equivalence. T h e discrepancy is mostly a result of neglecting C in the Miller approach. Note that C here has a substantial magnitude and that its contribution to T is significant (246 ps of the total 1160 ps, or 21%). L
L
sig
V". 5 , 8
H
x
r
= V.
JL + r
S g
'«
slg
(6.68) x +
r.
:
R'
SI$
= r j l (R
SIG
+
r) x
(6.69)
595
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS H I G H - F R E Q U E N C Y RESPONSE O F T H E CS A N D CE A M P L I F I E R S
6.6
5
;•
and, assuming that a d o m i n a n t p o l e exists,
1 2K[C + K
m
, 1 [C +C,(l
For f > fp2 ^
2K
L
+ {C +
sig
L
+ g RDlRk,+
x
IP2 '•
(6.76)
(1 + g R' )]R'
(CL +
m
[CJ.CL+CJ
+
CJR'
L
CJR'L
(6.77)
CLCJR^RI
fpu
z
fn = fp\
(a)
\.
EXERCISE 6;20 Consider a bipolar active-loaded C E amplifier having the load current-source implemented with a mmpnp transistor. Let the circuit be operating at a 1-mA bias current. The transistors are specified as mfollows: B(npn) = 200, V „ = 130 V, j V ^ j = 5 0 V, C = 16 p F , C = 0.3 p F , C = 5 p F , and i\ = 200 Q . T h e amplifier is fed with a signal source having a resistance of 36 kd. Determine: •;: (a) A ; (b) C and f using die Miller equivalence; (c) f using open-circuit time constants; (d) f , A
M
i n
dn
fp\> fpt- ' d
n
e
K
H
n
c
e
In (
L
H
u s e m
e
7
approximate expressions in Eqs. 6.76 and 6.77): and (e) f
r
;
- 1 7 5 V A ; 0 v 4 4 s p l . sl.h k l l / : (e) 13.1 M H z Aris. W
(b)
U
"5.1 kHz; id.. 21.2 Cill/. 75.i k l l / . 25.2 M H z . 75.1 k H z :
(ci
F I G U R E 6 . 2 5 (a) High-frequency equivalent circuit o f the common-emitter amplifier, (b) Equivalent ctrcutt obtamed after the Thevenin theorem is employed to simplify the resistive circuit at the input
6.6.5 The Situation When R
s i g
Is Low
There are applications i n w h i c h t h e C S amplifier is fed with a low-resistance signal source.
T h u s t h e d c gain is n o w g i v e n b y (6.70) 'SIG ' ' x ' ' n
Obviously, in such a c a s e , t h e high-frequency gain will n o l o n g e r b e limited b y t h e interac tion of the s o u r c e r e s i s t a n c e a n d t h e input c a p a c i t a n c e . Rather, t h e high-frequency limitation happens at t h e amplifier output, as w e shall n o w s h o w . Figure 6.26(a) s h o w s the high-frequency equivalent circuit of the c o m m o n - s o u r c e amplifier
U s i n g M i l l e r ' s t h e o r e m w e obtain I N = C*+C^l+g R ) C
m
Coixespondingly, t h e 3-dB frequency f
.
L
(6.71)
sig
found b y setting
c a n b e e s t i m a t e d from
H
in the limiting c a s e w h e n R 7?
S I G
(6.72)
H -
CR N
K
+ C^R^
V
«
Alternatively, u s i n g t h e m e t h o d of open-circuit t i m e constants yields X
+
i-gmRpll
=
s i g
= V /V a
gs
can be
-s(C /g )] gd
m
l+s(C +C )R'
sig
L
GD
L
Thus, while t h e d c gain a n d t h e frequency of t h e zero d o n o t c h a n g e , t h e high-frequency response is n o w d e t e r m i n e d b y a p o l e f o r m e d b y C + C
CC L
0
Vp
1 2
is zero. T h e voltage transfer function V / V
= 0 in E q . (6.60). T h e result is
L
CL
gd
t o g e t h e r w i t h R' . T h u s t h e 3-dB L
frequency is n o w g i v e n b y = CX + ig
from w h i c h f
H
C [(l
+ g R )R'
M
M
L
SIG
+
R> ] + L
C L
R'
L
(6.73)
c a n b e estimated as
J
H
2n(C +C )R' L
1 f
H
=
(6.74)
2nx
H
T h e e x a c t analysis yields t h e following z e r o frequency:
gd
L
To see h o w this p o l e is formed, refer t o F i g . 6.26(b), w h i c h s h o w s t h e e q u i v a l e n t circuit w i t h the input signal s o u r c e r e d u c e d to zero. O b s e r v e that the circuit r e d u c e s to a c a p a c i t a n c e (C
L
+C ) gd
in parallel w i t h a resistance R' . L
A s w e h a v e s e e n a b o v e , t h e transfer-function zero is u s u a l l y at a very high frequency and thus does n o t p l a y a significant r o l e in shaping t h e h i g h - f r e q u e n c y r e s p o n s e . T h e gain of the C S amplifier will therefore fall off at a rate o f - 6 d B / o c t a v e ( - 2 0 d B / d e c a d e ) a n d r e a c h e s
CHAPTER 6
SINGLE-STAGE
INTEGRATED-CIRCUIT
HIGH-FREQUENCY
6.6
AMPLIFIERS
RESPONSE OF T H E CS A N D CE A M P L I F I E R S
lifier specified in Example 6.9 when fed with a signal source having a neg ligible resistance (i.e., R
= 0 ) . Find A
sig
M
, /
, f,
3 d B
t
and f .
If the amplifying transistor is to be
z
operated at twice the original overdrive voltage while W and L remain unchanged, what value of 7REF
i
s n e e
d e d ? W h a t are the new values of A
, / 3 d B , ft,
M
and / ? z
Solution In Example 6.9 w e found that = - 1 2 . 3 V/V
A
M
The 3-dB frequency can be found using Eq. (6.79), 1 2n(C +C Ri
fn
h
gd)
1 1 5
2 ^ ( 2 5 + 5) x 10
x 9.82xl0
3
= 540 M H z and the unity-gain frequency, which is equal to the g a i n - b a n d w i d t h product, can be deter mined as A
ft = \ M\fn =
1 2 3 x 540
6 6
=
GHz
The frequency of the zero is /* _
1
Sm
z
2
~
*c
gd
± E 2 5 x l O -
=
l 7 Z
Now, to increase V
OV
5xl0"
from 0.16 V to 0.32 V, I
D
7 ^ = F I G U R E 6 . 2 6 (a) High-frequency equivalent circuit of a CS amplifier fed with a signal source having a very low (effectively zero) resistance, (b) The circuit with V reduced to zero, (c) Bode plot for the gain of the circuit in (a).
The new values of g
m
, r,
r,
ol
o2
3 s
4
0
G
H
2
1 5
must be quadrupled by changing I 400
M
and R[ can be found as follows:
sig
400 0.32/2
I
D
V /2 ov
unity (0 d B ) at a frequency f , t
2.5 m A / V
which is equal to the g a i n - b a n d w i d t h p r o d u c t , 5
x
0
3
6
= 4.5 k Q 0.4 m A
ft
=
\AM\/H 6
=
R
1
8m L
2n{C
L
+
0 /
C )R[
x
0
R[ = (4.5 Thus the new value of A
2n(C +C )R gd
6
-
5.4kO
gd
Thus,
L
3
0.4 m A II
5.4) = 2.45 k O
becomes
M
L
F i g u r e 6.26(e) s h o w s a sketch of the h i g h - f r e q u e n c y gain of the C S amplifier.
A
M
= -g R' m
L
= - 2 . 5 x 2.45 = - 6 . 1 5 V/V
M
F
to
j/V
599
6 0 0
§
CHAPTER 6
SINGLE-STAGE
That of f
H
INTEGRATED-CIRCUIT
6.7
AMPLIFIERS
THE C O M M O N - G A T E
becomes
AND COMMON-BASE
AMPLIFIERS WITH ACTIVE LOADS
VDD f J
A
1
= H
2K{C +C )R' L
gd
©
L
1
=
2^(25 + 5 ) x l 0 " = 2.16 G H z
1 5
x 2.45 x l O
D
3
- O v0
and the unity-gain frequency (i.e., the gain-bandwidth product) becomes G,B
/ , = 6.15 x 2.16 = 13.3 GHz W e note that doubling V results in reducing the dc gain by a factor of 2 and increasing the bandwidth by a factor of 4. Thus, the gain-bandwidth product is doubled—a good bargain! OV
—VA
o-
©
EXERCISES OV
OV
D
/ ;
L
Ans. 4 4 . 4 II•'
v
o
6.22 Show that the CS amplifier when fed with R^ = 0 has a transfer-function zero whose frequency is related lo /; bv Jl
-
i J- £_k 1
./;
V m
(b)
(a)
D6.21 For the CS amplifier considered in Example 6.10 operating at the original values of V and / (i.e., V - 0.16 V and I = 100 ,t;A), find the value lo which C should be increased to place / . at 2 GHz.
c
i >•
V„ = O
v -o
R
iL 0
0
V
Ï = (gm + gmb) ,
0
d
6.7 THE COMMON-GATE AND COMMON-BASE f AMPLIFIERS WITH ACTIVE LOADS
jt'"
t' l/(GM + gmb) •
0
R
6.7.1 The Common-Gate Amplifier
AAA?
F i g u r e 6.27(a) s h o w s the basic I C M O S c o m m o n - g a t e amplifier. T h e transistor has its gate g r o u n d e d and its drain c o n n e c t e d to an active load, s h o w n as an ideal constant-current source / . T h e input signal source v with a g e n e r a t o r resistance R is c o n n e c t e d to the source t e r m i n a l . S i n c e the M O S F E T s o u r c e is not c o n n e c t e d to t h e substrate, w e show t h e substrate t e r m i n a l , B , explicitly a n d i n d i c a t e that it is c o n n e c t e d to t h e l o w e s t voltage in t h e circuit, in this c a s e ground. Finally, o b s e r v e that e x c e p t for s h o w i n g t h e current-source /, w h i c h d e t e r m i n e s t h e dc bias current I of the transistor, w e h a v e n o t s h o w n any other bias detail. H o w the dc voltage V will b e established and h o w V is d e t e r m i n e d are not of c o n c e r n to us h e r e . A s m e n t i o n e d before, h o w e v e r , bias stability is usually assured through t h e application of n e g a t i v e feedback to the larger circuit of-which the C G amplifier is a part. F o r o u r p u r p o s e s h e r e , w e shall a s s u m e that t h e M O S F E T is operating in t h e saturation r e g i o n and c o n c e n t r a t e exclusively, on its small-signal operation. sig
1^
*—*l
-AAA
o-
o
+ Vi
s
10
DS
T h e B o d y E f f e c t S i n c e the substrate (i.e., b o d y ) is not c o n n e c t e d to the source, the body effect plays a r o l e in t h e operation of t h e c o m m o n - g a t e amplifier. It turns out, h o w e v e r , that
FIGURE 6 . 2 7 (a) Active-loaded common-gate amplifier, (b) MOSFET equivalent circuit for the CG case in which the body and gate terminals are connected to ground, (c) Small-signal analysis performed direcdy on the circuit diagram with the T model of (b) used implicitly, (d) Operation with the output open-circuited.
taking the b o d y effect into a c c o u n t in the analysis of t h e C G circuit is a v e r y simple matter. To see h o w this can b e d o n e , recall that t h e b o d y terminal acts, in effect, as a s e c o n d gate for the M O S F E T . T h u s , j u s t as a signal voltage v b e t w e e n the gate and the source gives rise to a drain current signal g v , a signal voltage v b e t w e e n the b o d y and the source gives rise to a drain current signal g v . T h u s t h e drain signal current b e c o m e s (g v + g v ), where the b o d y t r a n s c o n d u c t a n c e g is a small fraction % of g \ g = %g and % = 0.1 to 0.2. gs
m
Rather than using 7? to denote the resistance of the signal source, we use R since the resistance is in series with the source terminal of the MOSFET. sig
(d)
(c)
D
GS
s
gs
mb
bs
bs
m
mb
m
mb
m
gs
mb
bs
6 0 1
6.7 602
.
CHAPTER 6
THE C O M M O N - G A T E A N D C O M M O N - B A S E AMPLIFIERS W I T H ACTIVE L O A D S
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
note that since i = 0 , i 0
N o w , since in t h e C G circuit of Fig. 6.27(a) b o t h the g a t e a n d t h e b o d y terminals are c o n n e c t e d to g r o u n d , v = v , a n d the signal c u r r e n t in t h e drain b e c o m e s (g + g ) It f o l l o w s that the body effect in the common-gate circuit can be fully accounted for by simply replacing g of the MOSFET by (g + g ). A s an e x a m p l e , F i g . 6.27(b) shows the M O S F E T T m o d e l modified in this fashion. bs
gs
m
m
m
^
4. g )
m u s t also b e zero; t h e current i in the source terminal, i =
t
simply flows v i a the d r a i n t h r o u g h r
mb
a n d b a c k t o t h e s o u r c e n o d e . I t follows
0
mb v
that the i n p u t r e s i s t a n c e w i t h n o load, R , is infinite: t
mb
W e can also u s e t h e circuit in F i g . 6.27(d) to d e t e r m i n e the o p e n - c i r c u i t v o l t a g e gain Small-Signal Analysis
T h e small-signal analysis of the C G amplifier c a n b e performed
A
v0
between t h e i n p u t (source) a n d o u t p u t (drain) t e r m i n a l s as follows:
e i t h e r o n a n e q u i v a l e n t c i r c u i t o b t a i n e d b y r e p l a c i n g t h e M O S F E T w i t h its T m o d e l of F i g . 6.27(b) or directly on t h e circuit d i a g r a m w i t h the m o d e l used implicitly. W e shall opt r
= (g,n+gmb) oVi+Vi
for the latter a p p r o a c h in order to gain greater insight into circuit operation. F i g u r e 6.27(c) s h o w s the C G circuit p r e p a r e d for small-signal analysis. N o t e that w e h a v e "extracted" r
t h e M O S F E T a n d s h o w n it separately from the device. A s well, w e h a v e indicated the resis tance l/(g
+ g ),
m
Thus,
which appears in effect b e t w e e n gate and source looking into the source.
mb
Finally, note that a resistance R
(6.84)
of
Ko
= l + (gm + gmb)r
(6-85)
0
is s h o w n at the output; it is a s s u m e d to include the output
L
resistance of the current-source load I as well as any load resistance if o n e is connected.
This is a very i m p o r t a n t q u a n t i t y that a p p e a r s in a l m o s t all f o r m u l a s that c h a r a c t e r i z e t h e C G
W e n o w p r o c e e d to analyze the circuit of Fig. 6.27(c) to determine the various parameters
amplifier. W e o b s e r v e that A
vo
differs from t h e intrinsic gain of the M O S F E T in t w o m i n o r
that characterize the C G amplifier. A t this point w e strongly urge the reader to consult Table 4.3
respects: First, there is an additional t e r m of unity, and second, g
for a review of the definitions of amplifier characteristic parameters. This is especially useful
A
0
0
amplifier input resistance R
to depend on R
ia
L
a n d the output resistance R
om
to depend on /?>..
amplifier, t h e C G amplifier is n o n i n v e r t i n g . Utilizing E q s . (6.83) a n d ( 6 . 8 5 ) , w e c a n e x p r e s s t h e i n p u t r e s i s t a n c e of t h e C G amplifier in the c o m p a c t a n d attractive f o r m
Input Resistance
T o determine the input resistance R ,
w e m u s t find a way to express i
in
t
in terms of v . Inspection of the circuit in Fig. 6.27(c) reveals a key observation. T h e input cur
R
{
rent ii splits at the source n o d e into t w o c o m p o n e n t s : the source current i = (g
m
+ g )Vi
0
0
ra
supplied to R ; thus i = i and v L
0
i
0
= iR 0
L
= iR . t
N o w w e can write at the source node
L
= ^
m
(6.86)
and
mb
t h e current through r , i . T h e s e t w o c o m p o n e n t s c o m b i n e at t h e drain to constitute t h e current i
Typically
m
is 1 0 % to 2 0 % larger t h a n A . W e s h o u l d a l s o n o t e that the gain of t h e C G circuit is p o s i t i v e . T h a t i s , u n l i k e t h e C S
m
here b e c a u s e t h e C G amplifier is not a unilateral circuit; t h e resistance r connects the output n o d e to the i n p u t n o d e , thus d e s t r o y i n g unilateralism. A s a result w e s h o u l d expect the
is a d d e d to g .
mb
That i s , the C G circuit d i v i d e s t h e total resistance ( r + R ) b y t h e o p e n - c i r c u i t v o l t a g e gain, 0
L
w h i c h is a p p r o x i m a t e l y e q u a l t o t h e intrinsic g a i n of t h e M O S F E T . F u r t h e r m o r e , since 6
U = (gm + Smb)Vi + i o
( -81)
r
a n d express i
ro
A
v0
= (g
m
+ g )r mb
s. A , t h e e x p r e s s i o n for i ?
0
0
as
can b e simplified to
in
R = —_+ r
gm
(6.82)
r
T h i s e x p r e s s i o n s i m p l y says that taking
E q u a t i o n s (6.81) a n d (6.82) can b e c o m b i n e d to yield
input resistance.
(6 87)
Y
m
gmb
-
0
r into account 0
adds a component
(R /A ) L
T h i s additional c o m p o n e n t b e c o m e s significant o n l y w h e n R
L
to the
0
is large.
A n o t h e r i n t e r e s t i n g r e s u l t f o l l o w s d i r e c t l y f r o m t h e fact that i = 0 i n t h e c i r c u i t of i
v
+
h = [gm + gmb + ~) ij{}
from w h i c h the input resistance R
in
-
°=, R
irt
s
overall voltage gain, v /v , 0
0
L
r—
reduces to l/(g
l + (gm + m
0
Voltage Gain
w h i c h is indeed the input resistance that
mb
w e found for the discrete C G amplifier analyzed in Section 4.7.5 with r
neglected (there w e
a
also neglected g ).
When r
mb
0
a p p r o x i m a t e l y only for R
is taken into account, this value of input resistance is obtained
- 0. F o r the u s u a l c a s e of R
L
L
ingly, for large values of R
L
approaching infinity, R
i
n
t
= Ko
r
+ (gm + gmb) o
= r , R = 2/{g 0
t
m
+ g ). mb
Interest
T h e voltage gains A
and G
v
L
with R
:
- «>
of t h e loaded C G amplifier of Fig. 6.27(c)
v
c a n b e o b t a i n e d in a n u m b e r of w a y s . T h e m o s t direct a p p r o a c h is t o m a k e u s e , o n c e m o r e , of the fact that i = £,• a n d e x p r e s s v a
0
as v = iR 0
0
= iR
L
t
T h e v o l t a g e v, c a n b e e x p r e s s e d in t e r m s of i
i
is, R
(6-88)
L
'
(6.89)
- ° o . This s o m e w h a t surprising result
will b e illustrated next. Operation
and the open-circuit
v0
1
=
s i p
A,
(6.83)
8mb)r
+ g ),
si$
will b e z e r o . T h u s v ~ v
will b e e q u a l to Gvo
r + R 7—7
h 0
F i g . 6 . 2 7 ( d ) : T h e v o l t a g e d r o p across R
c a n b e found as
_v,_ R\n = r Observe that for r
~T
F i g u r e 6.27(d) s h o w s the C G amplifier w i t h R,
r e m o v e d ; that
= ° o and the amplifier is operating with the output open-circuited. W e immediately
as
,;,= i R ;
i n
(6.90)
6
0
3
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
6.7
AMPLIFIERS
D i v i d i n g E q . (6.89) b y E q . (6.90) y i e l d s , for t h e v o l t a g e gain A.=
T H E C O M M O N - G A T E A N D C O M M O N - B A S E AMPLIFIERS WITH ACTIVE
A, v
^ = £ v R
(6.91)
t
Substituting for R
ia
4
from E q . (6.86) p r o v i d e s
+ gmb)
R
©
(6.92) In a similar w a y w e c a n d e r i v e an e x p r e s s i o n for the overall voltage gain, G =
v /v ,
v
R
o = hL
V
«si
R
=
g
=
h( s
~ i
a
sig
T
R
UL R
+
(gm + gmb)
A
J
-VW
c
+
Thus, V,
in w h i c h w e c a n substitute for R
(6.94) v
"°R r L+
R e c a l l i n g that G
vo
= A, vo
0
we can express G
AR
+
vo
FIGURE 6 . 2 8 (a) The output resistance R is found by setting v = 0. (b) The output resistance R obtained by setting t/ = 0. 0
t
out
is
sig
s
as
v
(b)
(a)
from E q . (6.86) to o b t a i n
in
= 0
end n o t e that the current t h r o u g h R
is e q u a l to i ; thus w e c a n express t h e v o l t a g e v at t h e
s
x
M O S F E T s o u r c e as G
= G
v
Output Resistance
^
vo V0
"
R +r L
(6.95) +
0
AR m
v = iR
s
x
(6.99)
s
T o c o m p l e t e o u r c h a r a c t e r i z a t i o n of t h e C G amplifier, w e find its
output resistance. F r o m the study of amplifier c h a r a c t e r i z a t i o n in Section 4.7.2 ( T a b l e 4.3), w e recall that t h e r e are t w o different output r e s i s t a n c e s : R , 0
w h e n v- is set to z e r o , and i ? t
o u t
sig
0
s
0
a n d of R . oat
t h e output resistance w h e n t h e amplifier is fed w i t h an ideal source v
it
from
v
v= x
is set to z e r o . B o t h
c a n b e o b t a i n e d from the e x p r e s s i o n for i ?
setting R = 0. It is important to be clear o n the application of R applicable output resistance for d e t e r m i n i n g A
x
w h i c h is the output resistance
, w h i c h is the output resistance w h e n v
are illustrated in Fig. 6.28. O b v i o u s l y R
Utilizing the analysis i n d i c a t e d on the circuit d i a g r a m in F i g . 6.28(b), w e c a n write for v
o u t
by
Since R
is
a
it follows that it is the
[L+{g
mt
=
x
v0
is the output resistance w h e n the amplifier is fed with v
and its
sig
s
v
= r + [l+(g 0
m
R
l
L
+
r +
0
a
s
thus i ?
o u t
can b e
(6.102)
AR vo
s
in E q . (6.102) c a n b e o b t a i n e d b y substituting it
in E q . (6.97). T h e result will b e seen to b e identical to the gain e x p r e s s i o n in E q . (6.95),
R e t u r n i n g to the circuit in Fig. 6.28(a), w e see b y i n s p e c t i o n that R
A q u i c k verification of t h e f o r m u l a for R
wt
out
mb
v0
vo
R
(6.101)
g )r ]R
as the open-circuit v o l t a g e gain A ;
G, (6.97)
v0
+
e x p r e s s e d in an alternative, m o r e c o m p a c t f o r m as 0
R
x
A,
resistance R ; thus it is the applicable output r e s i s t a n c e for d e t e r m i n i n g G from = G
in terms of i
x
s
v
(6.100)
v /i ,
W e recognize the term multiplying R
G
+ v
x
and h e n c e R
out
om
0
E q u a t i o n s (6.99) and (6.100) c a n b e c o m b i n e d to e l i m i n a t e v and obtain v
R
O n the other h a n d , R
+ gmb)v]r
m
w h i c h w e d e r i v e d b y direct circuit analysis.
= r
(6.98)
a
T h e e x p r e s s i o n s for tf
out
in E q s . (6.101) and (6.102) are very useful results that w e will
employ frequently throughout the rest of this book. These formulas give the output resistance A q u i c k verification of this result is a c h i e v e d by substituting R
0
o b s e r v i n g that the resulting expression for A
v
= r in E q . (6.96) a n d then a
is identical to that in E q . (6.92), w h i c h w e
out
age v
x
s
in the emitter.
E q s . (6.101) and (6.102). A first interpretation, i m m e d i a t e l y available from E q . (6.102), is
d e r i v e d directly from circuit analysis. A n e x p r e s s i o n for R
not only of the C G amplifier b u t also of a C S amplifier with a resistance R
W e will h a v e m o r e to say a b o u t this shortly. A t this point, h o w e v e r , it is useful to interpret
can b e d e r i v e d u s i n g t h e circuit in F i g . 6.28(b) w h e r e a test volt
is applied at t h e output. O u r goal to find t h e c u r r e n t i d r a w n from v . T o w a r d that x
x
that the C G transistor increases the output resistance b y a d d i n g to r a c o m p o n e n t A R . 0
V0
S
In
m a n y cases t h e latter c o m p o n e n t w o u l d d o m i n a t e , and o n e c a n t h i n k of the C G M O S F E T
LOADS
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIE
6.7
as multiplying the resistance R in its source b y A , w h i c h is approximately equal to g r _ N o t e t h a t t h i s action is t h e c o m p l e m e n t of w h a t w e s a w earlier in r e g a r d t o R where the M O S F E T acts to divide R b y A . This i m p e d a n c e transformation action of the C G M O S F E T is illustrated in Fig. 6.29 a n d is k e y to a n u m b e r of applications of the C G circuit. O n e such a p p l i c a t i o n i n v o l v e s t h e u s e of t h e C G amplifier as a c u r r e n t buffer. F i g u r e 6.30 shows an equivalent circuit that is suitable for s u c h a n application. T h e r e a d e r is u r g e d to show that the overall s h o r t - c i r c u i t c u r r e n t g a i n G is g i v e n b y s
v0
m
THE C O M M O N - G A T E A N D C O M M O N - B A S E AMPLIFIERS WITH ACTIVE LOADS
In this e x p r e s s i o n the s e c o n d t e r m often d o m i n a t e s , enabling t h e following a p p r o x i m a t i o n :
iB
L
^ o u t = [1 + ( g
v0
is
+
m
g b)Rs\r m
0
^(l+g R )r m
Thus placing a r e s i s t a n c e R
s
s
(6.104)
0
in the source l e a d results in m u l t i p l y i n g the transistor o u t p u t
resistance r„ by a factor that w e r e c o g n i z e from our discussion of t h e effect of s o u r c e d e g e n eration in Section 4 . 7 . 4 . W e will h a v e m o r e to say a b o u t E q . (6.104) later.
High-Frequency Response
K
out
T h e n e a r - u n i t y c u r r e n t gain t o g e t h e r w i t h t h e l o w i n p u t r e s i s t a n c e a n d h i g h o u t p u t resistance are all characteristics of a g o o d current buffer. Y e t another interpretation of the formula for R in t h e f o r m
can b e obtained by expressing Eq. (6.101)
ont
internal c a p a c i t a n c e s C
gs
F i g u r e 6.31(a) s h o w s the C G amplifier w i t h the M O S F E T
and C
indicated. F o r generality, a c a p a c i t a n c e C
gd
L
is i n c l u d e d at
the output n o d e to represent the input capacitance of a succeeding amplifier stage. Capacitance C
L
also i n c l u d e s the M O S F E T c a p a c i t a n c e C .
N o t e the C
db
with C ; gd
L
appears in effect in parallel
therefore, in t h e following discussion w e will l u m p the t w o c a p a c i t a n c e s together.
It is i m p o r t a n t to n o t e at the outset that e a c h of the three c a p a c i t a n c e s in the circuit of g )R ]r mb
s
(6.103)
0
Fig. 6.31(a) h a s a g r o u n d e d n o d e . Therefore n o n e of the c a p a c i t a n c e s u n d e r g o e s the Millermultiplication effect o b s e r v e d in t h e C S stage. It follows that t h e C G circuit c a n b e d e s i g n e d to have a m u c h w i d e r b a n d w i d t h than that of the C S circuit, especially w h e n the r e s i s t a n c e of the signal g e n e r a t o r is large.
•
gmbWi
D -o V
0
• ^out = r +
AR
0
V0
=
S
g rR m
0
s
c.gd •
\
R
L
:C
r
Cg, Sm
+~
A
8mb
+
Rs
gmb)
+ A~
1 + (g
m
m
+ g mb> )r mb
0
}
o
=
r
gm o
FIGURE 6 . 2 9 The impedance transformation property of the CG configurât»
(a) (C?M
8mb)Vi -o V„
-AAAr-
' \ Z Y
gm +
Smb >
:C„ ~[~
v.
(b)
"
' o mu <"c - e gii /en ; ?i n„ tig. F Ï ^b.Z9. C Tand G I G
Jl
R E
6
3
i
f
° f ?° r
= A
(R
/R
Plifkr \ ~
l
I
U
U
S
T
R
A
T
I
N
G
K
S
A
PP
L I C A T I 0
"
a s
a
™
buffer. R and in
FIGURE 6 . 3 1 (a) The common-gate amplifier with the transistor internal capacitances shown. A load capacitance C is also included, (b) Equivalent circuit for the case in which r is neglected. L
0
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS
6.7
A n a l y s i s of the circuit in F i g . 6.31(a) is greatly simplified if r can b e neglected. In such a case the input side is isolated from the output side, and the high-frequency equivalent circuit takes t h e f o r m s h o w n in F i g . 6.31(b). W e i m m e d i a t e l y observe that there are t w o poles: one at the input side with a frequency f ,
T H EC O M M O N - G A T E A N D C O M M O N - B A S E A M P L I F I E R S W I T H A C T I V E L O A D S
'J^f
0
P1
Consider a c o m m o n - g a t e amplifier specified as follows: W/L = 1.2 / a n / 0 . 3 6 / a n , fi„C 387 //A/V , r = 18 k Q , l = 100 fjA, g = 1.25 mA/V, % = 0.2, R = 10 k Q , R = 100 k Q , C , = 20 f F , C = 5 fF, and C = 0. Find A , R- , R , G , G , G , and f . 0X
2
a
(6.105)
fpi 2nC \R \ gs
s
D
gd
L
f
-g =
p:
m
M
out
v
is
t
L
H
1.25 + 0 . 2 x 1.25 = 1.5 mA/V
mb
A
1 ~
s
Solution
and the other at t h e output side w i t h a frequency
fp2
m
2n(C
+
gd
= 1 + ( g + g )r
vo
C )R L
m
(6.106)
mb
r„ + R
L
18+100 28
r
R
i„
T h e relative locations of the t w o poles will d e p e n d o n the specific situation. H o w e v e r , f is usually l o w e r than f ; thus f c a n b e d o m i n a n t . T h e important point t o n o t e is that both f and f are usually m u c h h i g h e r than t h e frequency of the d o m i n a n t input p o l e in the C S stage.
= 1 + 1.5 x 18 = 28 V / V
0
4.2 kQ.
P2
Pl
P1
R
out
P1
=
r +AR o
m
= 18 + 28 x 10 = 298 kQ
s
P2
RT
G = v
In situations w h e n r h a s t o b e t a k e n into a c c o u n t ( b e c a u s e R a n d R a r e large), the m e t h o d of open-circuit t i m e constants c a n b e e m p l o y e d t o obtain a n estimate for t h e 3-dB frequency f . Figure 6.32 shows the circuits for determining the resistances R and R seen b y C a n d (C + C ), respectively.,By inspection w e obtain 0
s
H
gd
°L
L
g s
gs
R
G:, =
V0
R
°L
+ ^out
28 x 10 298
AR
S
g d
L
-0.94
G; = G: R g
s
(6.107)
R
-
s
R ,=
R,\\R. =
R=
RT WR,
G
and R
L
II
f, H
0.94 A/A 298 = 0.7 A/A 298 + 100 3 kQ
100 II 298 = 75 k Q
-
R
Cgs gs
+
R
Cgd gd
= 20 x 3 + 5 x 75 1
fu
+ ^out
(6.108)
Rout
%
w h i c h can b e u s e d t o obtain
10114.2
M
gd
R„
-R,
100 = 7 V/V 100 + 298
R,
= A.
2n[C R gs
gs
+
(C +C )R ] gd
L
= 60 + 375 = 435 ps
(6.109)
1
?d
1 .-12
366 M H z
2 t t x 435 x 10
D
W e note that this circuit performs well as a current buffer, raising the resistance level from R = 4 k Q to R = 300 k Q and having an overall short-circuit current gain of 0.94 A/A. Because of the high output resistance, the amplifier bandwidth is determined primarily b y the capacitance at the output node. Thus additional load capacitance can lower the bandwidth significantly. in
oat
X"
6.23 For the CG amplifier considered in Example 6.11, find the value of J' when a capacitance C, = 5 f F is connected at the output. H
-
Ans.ior. M i l /
Riv,
6.24 Repeal the problem in Example 6.11 for the case R, = 1 k Q and R, = 10 k Q . (a) FIGURE 6 . 3 2
Circuits for determining R„ and R„
(b)
Ans. \
- 2S Y / Y : A*
! ki>: R. • - U» kQ: (i
5\\:f,
n.^l .V \ : G, - " . 5 .V \ : / . •
I (¡1 \ '
CHAPTER 6
SINGLE-STAGE
INTEGRATED-CIRCUIT
A
MPLIFIERS
6.7
6.7.2 The Common-Base Amplifier
THE C O M M O N - G A T E
AND COMMON-BASE
AMPLIFIERS WITH ACTIVE LOAI
amplifier w i t h o u t t h e b i a s d e t a i l s . N o t e that r e s i s t a n c e R r e p r e s e n t s t h e c o m b i n a t i o n of a l o a d r e s i s t a n c e , if a n y , a n d t h e o u t p u t r e s i s t a n c e of t h e c u r r e n t s o u r c e t h a t r e a l i z e s t h e active l o a d / . L
A n a l y s i s of t h e c o m m o n - b a s e a m p l i f i e r NARALLPIC
the*
~f<-u
F i g u r e 6.33(b) s h o w s t h e small-signal analysis p e r f o r m e d directly on t h e circuit w i t h t h e T m o d e l of t h e B J T u s e d implicitly. T h e analysis is very similar to that for the M O S c a s e except that, as a result of the finite b a s e current, v/r , t h e current i is related to i b y n
a
t
K = h-v/r*; —-O »„
T h e reader c a n s h o w that, neglecting r ,
the input resistance at t h e emitter R
x
in
- ^ ~ 1 + ^ + r (P+l)r
11
V f
K
(6-llD
l
e
e
W e immediately observe that setting B = °° reduces this expression to that for the M O S case (Eq. 6.83) except that here g = 0. N o t e that for ¡3 = °°, a = 1, and r = a/g = l/g . W i t h a slight a p p r o x i m a t i o n , the expression in Eq. (6.111) can b e written as mb
-AAA,
e
6=^1
0
is g i v e n b y
r
Rin=
If.
I
(6.110)
m
m
6112)
<
^•••r~^TT>
N o t e that setting r = °° yields R = r , w h i c h is consistent with w h a t w e found in S e c tion 5.7.5. A l s o , for R = 0, R = r . T h e value of R increases as R is raised, reaching a m a x i m u m of (B + l ) r = r for R = » , that is, with the amplifier operating open-circuited (see F i g . 6.33c). F o r R /(B+ 1) < r , E q / ( 6 . 1 1 2 ) can b e a p p r o x i m a t e d as 0
in
L
e
in
e
K
e
ia
L
L
L
0
(a) (b)
R
= r
iD
e
^
+
(6.113) 0
- o «,
w h e r e A is t h e intrinsic g a i n g r . T h i s e q u a t i o n is v e r y s i m i l a r to E q . (6.87) in t h e M O S F E T case. T h e open-circuit v o l t a g e gain and input resistance can b e easily found from the circuit in Fig. 6.33(c) as 0
m
0
A= m
l+g r = m
l+^o
0
(6-114)
w h i c h is identical to Eq. (6.85) for the M O S F E T e x c e p t for the a b s e n c e of g .
T h e input
mb
resistance w i t h n o load, R,, is R,=
r
.
x
as w e h a v e already f o u n d out from Eq. (6.112). A s in t h e M O S F E T case, the output resistance R
(6.115)
is given b y
0
R„ = r„
^
The output resistance including the source resistance R
e
(6.116)
can b e f o u n d b y analysis of t h e
circuit in F i g . 6.34 to b e R=
(c) FIGURE 6.33 circuit
(a) Active-
mt
r + {l+g r )R' 0
m
0
(6.117a)
e
w h e r e R' = R \\ r„. N o t e that t h e f o r m u l a in E q . (6.117a) is very similar to that for the M O S case, n a m e l y Eq. (6.101). However, there are two differences: First, 8mb ^ missing, £tnd second, R R 11 T^ e
e
e
e
:
©11
612
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS
6 1 3
• ^out = r (1 +
g R' )
a
|
m
e
gV m
•<—
_L7 •R
+
^ \r + R /(B + 1) 0
F I G U R E 6 . 3 4 Analysis of the CB circuit to determine i ? . Observe that the current i that enters the transistor must equal the sum of the two currents v/r and v/R that leave the transistor; that is, L = v/r- + v/R„.
Re
x
o u t
v_ R.
%
replaces R . The reason r s
n
a p p e a r s in t h e B J T f o r m u l a is t h e finite /? of the B J T . T h e expres-
?o ~^
A
R
v 0
K = Re\\r„ FIGURE 6.35 CB amplifier.
Input and output resistances of the
The high-frequency r e s p o n s e of the c o m m o n - b a s e circuit can b e evaluated in a m a n n e r similar to that used for t h e M O S F E T .
as
vo
oat
Re
e
sion in E q . (6.117a) can also b e written in terms of the open-circuit voltage gain A R
L
(6.117b)
e
w h i c h is the B J T counterpart of the M O S e x p r e s s i o n in E q . (6.102). A n o t h e r useful form for 6.25 Consider/the C B amplifier of Fig. 6.33(a) for the case 7 = 1 m A , f3 = 1 0 0 , V
R „, c a n b e o b t a i n e d from (6.117a),
100 V. R, = 1 M Q . a n d
A
a
R,, = 1 k i l . find /?,„, A , vo
R
= R'
aa
e
+
(6.117c)
{l+g R' )r m
e
0
R, A, 0
v
R
m
v
and G... Also, find v , if t / (
sie
i s a 5-mV peak sine wave.
Ans. 2 5 0 Q : 4001 V/V; 1 0 0 k Q ; 3637 V/V; 2.97 M Q ; 722 V/V; 3.61 V p e a k
w h i c h is the B J T counterpart of the M O S expression in E q . (6.103). In Eq. (6.117c) the second t e r m is m u c h larger t h a n t h e first, resulting in the a p p r o x i m a t e expression R
s {l +
om
(6.118)
g R' )r m
e
0
6.7.3 A Concluding Remark The c o m m o n - g a t e a n d c o m m o n - b a s e circuits h a v e open-circuit v o l t a g e gains A
v0
increases
h o w e v e r , is m u c h smaller and their output resistance m u c h larger t h a n the c o r r e s p o n d i n g
is increased f r o m 0 to °=, the
values for the C S and C E amplifiers. T h e s e t w o properties, t h o u g h n o t usually desirable in
Equation (6.-118) clearly indicates that the inclusion of an emitter resistance R
e
t h e C B output resistance b y t h e factor (1 + g R' ). m
voltage amplifiers, m a k e the C G and C B circuits suitable as current buffers. T h e a b s e n c e of
dictated b y the finite ¡3 of the B J T , has no counterpart in the M O S case
the Miller effect m a k e s t h e high-frequency r e s p o n s e of the C G and C B circuits far superior
a
mt
e
This u p p e r limit on
o u t p u t resistance increases from r the v a l u e of R ,
T h u s , as R
e
almost
equal to t h o s e of the c o m m o n - s o u r c e and c o m m o n - e m i t t e r circuits. T h e i r input resistance,
w h i c h c o r r e s p o n d s to E q . (6.104) for t h e M O S c a s e .
to ( 1 + g r„)r m
= ( 1 + p)r
0
0
= pr . 0
and, as will b e seen later, h a s i m p o r t a n t i m p l i c a t i o n s for circuit design. Finally, w e note that
to that of the C S and C E amplifiers. T h e m o s t significant application of the C G and C B circuits
for R
is in a configuration k n o w n as the cascode
e
amplifier,
w h i c h w e shall study next.
(6.119) A useful s u m m a r y of t h e f o r m u l a s for R
in
and R
out
If 6.8 THE CASCODE AMPLIFIER
is p r o v i d e d in F i g . 6.35.
T h e results a b o v e c a n b e u s e d to o b t a i n t h e overall v o l t a g e gain G
v
as By placing a c o m m o n - g a t e (common-base) amplifier stage in cascade with a c o m m o n - s o u r c e
Rr
(6.120)
3
R,+R«
( c o m m o n - e m i t t e r ) amplifier stage, a very useful a n d versatile amplifier circuit results. It is k n o w n as t h e c a s c o d e c o n f i g u r a t i o n " and has b e e n in u s e for nearly three quarters of a century, o b v i o u s l y in a w i d e variety of t e c h n o l o g i e s .
where G„
Rj Ri + R„
(6.121) r„ + R„
The name cascode dates back to the days of vacuum tubes and is a shortened version of "cascaded cathode" since, in the tube version, the output (anode) of the first tube feeds the cathode of the second.
CHAPTER 6
THE CASCODE AMPLIFIER
6.8
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
r
# o u t = o2 + A
T h e b a s i c i d e a b e h i n d t h e c a s c o d e amplifier is t o c o m b i n e t h e h i g h input resistance and large t r a n s c o n d u c t a n c e a c h i e v e d in a c o m m o n - s o u r c e ( c o m m o n - e m i t t e r ) amplifier with the current-buffering property a n d t h e superior high-frequency r e s p o n s e of t h e c o m m o n - g a t e ( c o m m o n - b a s e ) circuit. A s will b e seen shortly, t h e c a s c o d e amplifier c a n b e designed to obtain a w i d e r b a n d w i d t h b u t equal dc gain as c o m p a r e d t o t h e c o m m o n - s o u r c e ( c o m m o n emitter) amplifier. Alternatively, it c a n b e d e s i g n e d to increase the d c gain w h i l e leaving the g a i n - b a n d w i d t h product unchanged. Of course, there is a c o n t i n u u m of possibilities between these t w o extremes. A l t h o u g h t h e c a s c o d e amplifier is f o r m e d b y c a s c a d i n g t w o amplifier stages, in many applications it is t h o u g h t of a n d treated as a single-stage amplifier. Therefore it belongs in this chapter.
J2l
<
r
w 2
r l 0
r
=
r
(gm2 o2> o
a .
©
1 R
'
- o v„
V„\
i
n
2
gm2 +
gmb2
'
Avo2
o' Roatl
r
~
ol
VRIAS ° ~
6.8.1 The MOS Cascode F i g u r e 6.36(a) s h o w s t h e M O S c a s c o d e amplifier. H e r e transistor Q is c o n n e c t e d in the c o m m o n - s o u r c e configuration a n d p r o v i d e s its output t o t h e input t e r m i n a l (i.e., source) of transistor Q . Transistor Q h a s a constant d c voltage, V s > applied to its gate. T h u s the signal voltage at the gate of Q is zero, and Q is operating as a C G amplifier with a constantcurrent load, / . O b v i o u s l y b o t h Q a n d Q will b e operating at d c drain currents equal to /. A s in p r e v i o u s cases, feedback i n t h e overall circuit that incorporates t h e c a s c o d e amplifier establishes an appropriate d c voltage at t h e gate of Q so that its drain current is equal to /. A l s o , t h e v a l u e of V s b e c h o s e n so that b o t h Q a n d Q operate in t h e saturation r e g i o n at all t i m e s . x
2
2
o
1
O
Vi
_ J 2 l
<
r
ol
4.
BIA
2
+
2
x
A
R
2
=
0
vo2
0
=
1
+
fem2
+
r
8mb2) o2
t
n
a
s
t
0
B I A
x
2
(b)
(a)
Small-Signal Analysis
W e begin with a qualitative description of the operation of the cascode circuit. In response to the input signal voltage v , the common-source transistor Q con ducts a current signal g v in its drain terminal a n d feeds it to t h e source terminal of the c o m m o n - g a t e transistor Q , called t h e c a s c o d e t r a n s i s t o r . Transistor Q p a s s e s t h e signal current g v o n t o its drain, w h e r e it is s u p p l i e d t o a l o a d r e s i s t a n c e R (not s h o w n in Fig. 6.36) at a very high output resistance, R . T h e c a s c o d e transistor Q acts in effect as a buffer, presenting a l o w input resistance t o t h e drain of Q a n d providing a h i g h resistance at t h e amplifier output. N e x t w e a n a l y z e t h e c a s c o d e amplifier circuit t o d e t e r m i n e its characteristic p a r a m e t e r s . T o w a r d that e n d F i g . 6.36(b) s h o w s t h e c a s c o d e circuit p r e p a r e d for small-signal analysis and w i t h a resistance R s h o w n at t h e output. R is a s s u m e d t o i n c l u d e t h e output resistance of current source / as well as a n actual l o a d resistance, if any. T h e d i a g r a m also indicates various i n p u t a n d output resistances o b t a i n e d u s i n g t h e results of t h e analysis of t h e C S a n d C G amplifiers in p r e v i o u s sections. N o t e in particular that t h e C S transistor Q p r o v i d e s t h e c a s c o d e amplifier with an infinite input resistance. A l s o , at t h e drain of Q l o o k i n g " d o w n w a r d , " w e s e e t h e output resistance of t h e C S transistor Q r . L o o k i n g " u p w a r d , " w e see the input resistance of t h e C G transistor Q , {
ml
0
=
A (~A v^ m2
0l
i
2
ml
-ov
l
2
t
.22
L
o
u
t
r
: o2
2
x
L
- O Vol ~
=
r
v
-8m\ ol i
-A Vi 01
L
1
ViO
x
R,
=
°°
x
u
0 l
A
—
m
2
r
AA ox
m2
(gm o) (c)
R
m
2
=
—
8m2
+ -^-
^ +
(6.122)
A
8mb2
vo2
FIGURE 6 . 3 6 (a) The MOS cascode amplifier, (b) The circuit prepared for small-signal analysis with vari ous input and output resistances indicated, (c) The cascode with the output open-ctrcmted.
where r
Ko2
= 1 + (gm2 + 8mb2) o2
T h u s t h e total resistance b e t w e e n t h e drain of Q
x
F i g u r e 6.36(b) also indicates that t h e output resistance of t h e c a s c o d e arnplifier, R
(6.123)
a n d g r o u n d is
§
i
V
e
n
b
y
v
r
flout R
r
— ol
(6.124)
• ~T~
mhi
=
>o2
A +
+
r A l\
o u t
, is
(6-125)
vo2 0
w h i c h h a s b e e n o b t a i n e d u s i n g t h e formula i n E q . (6.102) a n d noting that t h e resistonce R in t h e s o u r c e of t h e C G transistor Q
2
is t h e o u t p u t resistance r
ol
of Q . Substituting x
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
A
AMPLIFIERS
6.8
f r o m E q . (6.123) into E q . ( 6 . 1 2 5 ) y i e l d s
vo2
t
ml
+ [l+
o2
(g
+ g )r ]r
m2
mbl
ol
(6.126)
ol
w h i c h the C G transistor p a s s e s o n to R
w h i c h c a n b e a p p r o x i m a t e d as
the p r o c e s s , increases the o u t p u t resistance b y A . It is the i n c r e a s e in R M
out = (Sm2r )r
= Ar
ol
Q
(6.127)
oi
0
summary of t h e o p e r a t i o n : T w o o u t p u t e q u i v a l e n t circuits are s h o w n in Fig. 6.37(a) a n d (b), x
oi
0
o l
Fig- 6.37(c). T h e v o l t a g e gain A
is p r e s e n t e d in
c a n b e found from either of the t w o e q u i v a l e n t circuits in
V
Fig- 6.37(a) a n d (b). U s i n g that in Fig. 6.37(a) g i v e s
A n o t h e r o b s e r v a t i o n to m a k e o n t h e c a s c o d e amplifier circuit in Fig. 6.36(b) is that when a signal s o u r c e v w i t h a n internal r e s i s t a n c e R is c o n n e c t e d to the input, the infinite i n p u t r e s i s t a n c e of the amplifier c a u s e s sig
that
0 o
= AQ. F i g u r e 6.37 p r o v i d e s a useful
o
and an e q u i v a l e n t circuit for d e t e r m i n i n g the v o l t a g e gain of the C S stage Q T h u s the cascode transistor raises the level of output resistance b y a factor equal to its intrinsic gain, f r o m r of t h e C S amplifier to A r .
to A r
Qat
increases t h e o p e n - c i r c u i t v o l t a g e gain to (g )(A r ) R
a n d , in
L
0
o2
AMPLIFIER
T h e o p e r a t i o n of the c a s c o d e amplifier s h o u l d n o w b e apparent: In r e s p o n s e to v the C S transistor p r o v i d e s a drain c u r r e n t g Vi,
^out = r
THE CASCODE
A„
sig
Rr
-An R 10
L
(6.131)
+
Ar 0
o
W e i m m e d i a t e l y see that if w e are to realize the l a r g e gain of w h i c h the c a s c o d e is c a p a b l e , resistance R
s h o u l d b e large. A t the v e r y least, R
L
Thus,
R
L
G=
0
o
should b e of t h e o r d e r of A r .
L
A
=
v
0
o
For
-Al/2.
T h e gain of the C S stage is i m p o r t a n t b e c a u s e its v a l u e d e t e r m i n e s t h e M i l l e r effect in
A
v
= Ar,
v
that stage. F r o m the e q u i v a l e n t circuit in Fig. 6.37(c),
A l s o , n o t e t h a t t h e amplifier is unilateral; thus,
v
o\
1
—
V;
T h e open-circuit voltage gain A of the cascode amplifier can b e easily determined from the circuit in Fig. 6.36(c), w h i c h s h o w s the amplifier operating with the output open-circuited. Since R will b e infinite, t h e g a i n of t h e C S s t a g e Q will b e vo
in2
For R
L
=
R,
(6.132)
+ "
A
0
Ar, 0
o
Vol
• + r.
x
V;
" T h e signal v Q to obtain
ol
=
r
~%m\ o\
~ ~A
(6.133)
0 1
w i l l b e amplified b y the o p e n - c i r c u i t v o l t a g e gain A
of the C G transistor
vo2
2
V
A
o ~
V
vo2 o\
Thus, A
= -A A
vo
01
=
—
A
(6.128)
vo2
0 1
A
0 2
w h i c h for t h e u s u a l c a s e of equal intrinsic gains b e c o m e s Ko
= - A o = ~(g r f m
(6.129)
0
W e c o n c l u d e that c a s c o d i n g increases the m a g n i t u d e of the open-circuit v o l t a g e gain from A of the C S amplifier to A . 2
0
0
W e are n o w in a position to derive an expression for the short-circuit transconductance G„, of the c a s c o d e amplifier. F r o m the definitions a n d the equivalent circuits in T a b l e 4 . 3 , A
Substituting for A
v0
= —G R vo mo f r o m E q . ( 6 . 1 2 8 ) a n d for R = R 0
q
_
out
A A m
v
A
r
r
o
f r o m E q . (6.125) g i v e s , for G„ m> J
2
o2 + vo2 o\
-
Smir dl+(g 2 0
+
m
r
o2 + V^+(g i m
+
Rdi g )r ] mb2
o2
g )r \r mbl
— 5 ml
o2
(c)
oX
FIGURE 6 . 3 7 (a and b) Two equivalent circuits for the output of the cascode amplifier. Either circuit can be used to determine the gain A = v / v , which is equal to G because R = °O and thus v = v . (c) Equivalent circuit for determining the voltage gain of the CS stage, Q . v
w h i c h confirms the v a l u e o b t a i n e d earlier in t h e qualitative analysis.
0
t
v
x
in
L
Ag
6 1 8
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.8
T h u s w e s e e that w h e n R is large a n d t h e c a s c o d e amplifier is realizing a substantial gain, a g o o d part of t h e gain is obtained in t h e C S stage. This is n o t g o o d n e w s considering the M i l l e r effect, as w e shall see shortly. T o k e e p t h e gain of the C S stage relatively l o w , R has to b e lowered. F o r instance, for R = r , E q . (6.132) indicates that
3. C a p a c i t a n c e (C
L
+C )
dbl
sees a resistance
gs2
4. C a p a c i t a n c e (C + R ) L
R. dl
sees a resistance (R
gd2
T H ECASCODE AMPLIFIER
\\
L
R ). mt
L
L
W i t h t h e resistances determined, the effective time constant r
0
% = C R gsl
V;
L
sig
dbl
and t h e 3-dB frequency f
+ C [(l
+ g iR i)R i
+ C )R
+ (C + C )(R
gdl
+ (C
-2 V / V Unfortunately, h o w e v e r , in this case t h e dc gain of the c a s c o d e is drastically r e d u c e d , as can b e seen b y substituting R = r i n Eq. (6.131),
c a n b e c o m p u t e d as
H
gs2
m
dl
d
+ R i]
S g
L
d
gd2
\\ R J
L
(6.136)
0
as
H
0
1
/.A„ =
-A
S
n
-An
2WT
H
(6.134) T o gain insight regarding w h a t limits the high-frequency gain of the M O S cascode ampli
That is, t h e gain of the cascode b e c o m e s equal to that realized in a single C S stage! D o e s this m e a n that the cascode configuration (in this case) is not useful? N o t at all, as w e shall n o w see.
fier, w e rewrite E q . (6.136) i n t h e form % - R [C sig
6.8.2 Frequency Response of the MOS Cascode
L
dhl
db2
gs2
L
gd2
T h e easiest and, in fact, quite insightful a p p r o a c h to d e t e r m i n i n g t h e 3-dB frequency f is t o employ the open-circuit time-constants method. W e shall d o so and, in the process, utilize t h e formulas d e r i v e d in Sections 6.6.2 a n d 6.7.1 for t h e various resistances: H
1. C a p a c i t a n c e C
gsl
2. Capacitance C in E q . (6.56) t o
gdl
sees a resistance
R. sig
sees a resistance R , gdl
gdl
ml
+ R (C
dl
dl
+C
gdl
dbl
+
C ) gs2
+ (R \\R )(C +C )
F i g u r e 6.38 s h o w s t h e c a s c o d e amplifier w i t h all transistor internal capacitances indicated. A l s o included is a capacitance C at the output n o d e to represent the combination of C , the input capacitance of a succeeding amplifier stage (if any), a n d a load capacitance (if any). Note that C and C appear in parallel, a n d w e shall c o m b i n e t h e m in t h e following analysis. Similarly, C a n d C appear i n parallel a n d will b e c o m b i n e d . L
+ C (l+g R )]
gsl
which can b e obtained b y adapting the formula
0Ut
L
(6.137)
gd2
In t h e c a s e of a large i ? , t h e first t e r m c a n d o m i n a t e , especially if t h e Miller multiplier (1 + g iR i)is large. This in turn h a p p e n s w h e n t h e load resistance R is large (on the order of A r ) , c a u s i n g R t o b e large and requiring t h e first stage, Q t o provide a large propor tion of the gain. It follows that w h e n jR is large, to extend t h e b a n d w i d t h w e h a v e to l o w e r R to t h e order of r . This in turn lowers R a n d h e n c e R a n d renders t h e Miller effect insignificant. N o t e , h o w e v e r , that the dc gain of the c a s c o d e will then b e A . T h u s , while t h e dc gain will b e t h e s a m e as (or a little h i g h e r than) that achieved in a C S amplifier, t h e b a n d width will b e greater. In t h e c a s e w h e n R is small, t h e Miller effect in Q will n o t b e of concern. A large value of R (on t h e order of A r ) c a n then b e u s e d t o realize t h e large d c gain possible with a cascode a m p l i f i e r — t h a t is, a d c gain o n t h e order of A . E q u a t i o n (6.137) indicates that in this case t h e third t e r m will usually b e d o m i n a n t . T o p u r s u e this point a little further, con sider t h e c a s e R = 0 , a n d a s s u m e that t h e m i d d l e t e r m is m u c h smaller than t h e third term. It follows that sig
m
0
d
L
o
in2
u
sig
0
L
m2
di
0
sig
L
1
0
o
0
R
gdl
where R , dl
- ( 1 + SmA^Rsig
+ R
dl
(6.135)
t h e total resistance at D , is g i v e n b y E q . (6.124). x
sig
% = ( Q + C ){R gd2
II
L
R ) 0Vlt
and the 3-dB frequency b e c o m e s
fn= J
6
n 2n(C +C )(R \\R )
H
L
gd2
L
( -
1 3 8
)
wt
which is of t h e s a m e f o r m as the formula for t h e C S amplifier with R = 0 (Eq. 6.79). Here, h o w e v e r , (R II R ) is larger that R' b y a factor of about A„. T h u s t h e f of the cas code will b e l o w e r t h a n that of the C S amplifier b y t h e s a m e factor A . F i g u r e 6.39 s h o w s a sketch of t h e frequency r e s p o n s e of t h e c a s c o d e a n d of t h e corresponding c o m m o n - s o u r c e amplifier. W e o b s e r v e that in this case c a s c o d i n g increases t h e d c gain b y a factor A w h i l e k e e p i n g t h e u n i t y - g a i n frequency u n c h a n g e d at sig
L
om
L
H
0
0
FIGURE 6 . 3 8 The cascode circuit with the various transistor capacitances indicated.
f
t
^ l 2nC
L
im— + C
(6.139) gd2
6 2 0
1
CHAPTER 6
SINGLE-STAGE
INTEGRATED-CIRCUIT
6.8
AMPLIFIERS
T H EC A S C O D E
Solution Common Source
Cascode (a) For the CS amplifier: 1
-oV c
>
n
C
r
? m
= 1.25 x 2 0 = 25 W V
0
-*1 -g (R
= c
m
\a RL
L
II r ) = -g (r
L
a
m
II r )
0
0
=
0
- | A = - 1 2 . 5 VA^
Circuit
0
R'L =
Vi
R \\r L
o—l I
Tu
CR
=
gs
+ C [{\
sig
+ g R[)R
gd
m
+R[]+(C +
sig
C )R[
L
db
0
where DC Gain
R'L
At)g R'i
=
r II r = 10 kQ
rARr
0
0
m
20 x 10 + 5 [ ( 1 + 12.5) 10 + 10] + (5 + 5 ) 1 0 1 2n(C
+
L
C )R' GD
2ir(Q +
L
200 + 725 + 100 = 1025 ps
C )A R' gd
0
L
Thus,
f,
2ir(C •
2TT(C
L
L
+
1
fu
155 M H z
2 t t x 1 0 2 5 x 10" Gain (dB),
\A \f
ît
• Cascode
v
= 1 2 . 5 x 155 = 1.94 G H z
H
A
Og,„R'L For the cascode amplifier: A
m
=g
m
A =
o
=
l
1 . 2 5 x 2 0 = 25 V / V
l + (g,„ + g 2)r
vo2
gmR'l
ir
2
mb
= 1 + (1.25 + 0.2 x 1.25) x 20
o2
= 1 + 1 . 5 x 2 0 = 31 V / V Kouti = r R
m2
o l
f (log scale)
R
o 2
/±
gmb2
vo2
I' m2
+A
r
v o 2
+
™ = 1.3 kQ 31
2011 1.3 = 1.22 kQ
R
~ oat\
Acut = r
FIGURE 6 . 3 9 Effect of cascoding on gain and bandwidth in the case R = 0. Cascoding can increase the dc gain by the factor A while keeping the unity-gain frequency constant. Note that to achieve the high gain, the load resistance must be increased by the factor A .
+
R
di
± 1.5
~ gm2
f,
= 2 0 kQ
= 20 + 31 x 20 = 640 kQ
o l
sig
R
0
=
• mi di Vi
0
R
A ., = A
l
% = R iC siB
(a) T h e resistance of the signal source is significant, R
sig
(b) R
sig
6
L
r
H
gdl
0Ut
L
db2
= -23.5 V/V
0
2
0
+ R (C
dl
dl
+
1.25 m A / V , x = 0.2 , r = 20 kQ , C 0
= 2 0 fF , C
gs
= 5 fF. For case (a), let R = L
r= a
amplifier. For all cases, determine A , v
gd
= 5 fF , C
db
m
= 5 fF , and C
L
2 0 kQ for the CS amplifier and R = R L
f, H
and f . t
oM
=
(excluding
for the cascode
f
H
+
C +C ) dbl
gs2
gd2
= 10[20 + 5 ( 1 + 1.5)] + 1.22(5 + 5 + 2 0 ) + ( 2 0 II 6 4 0 ) ( 5 + 5 + 5)
1 = 100 pA, g
gdl
C )
= 653 ps
is negligibly small. D
db
ml
+
0
= 325 + 36.6 + 290.9
= 1 0 kQ. -
A s s u m e all M O S F E T s have W/L of 7.2 zirn/0.36 fun and are operating at I C)
4
+ C (l+g R )l
gsl
+ (R \\R )(C +C
This example illustrates the advantages of cascoding b y comparing the performance of a cascode
2
=-25x31x
'RL + R™
JC-V
amplifier with that of a common-source amplifier in two cases:
- E 2 5 x 1.22 = - 1 . 5 V / V
[
= 244 M H z
= 2n x 653 x 10"
/ , = 23.5 x 244 = 5.73 G H z Thus cascoding has increased f by a factor of about 3. t
AMPLIFIER
621
-
2
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
6.8
AMPLIFIERS
(b) For the CS amplifier: A
%=
(C
+C +
gd
Figure 6.40(a) shows the B J T cascode amplifier. T h e circuit is very similar to the M O S cas code, a n d t h e small-signal analysis follows in a similar fashion, as indicated in Fig. 6.40(b). H e r e w e h a v e s h o w n t h e v a r i o u s i n p u t a n d o u t p u t r e s i s t a n c e s . O b s e r v e that u n l i k e t h e M O S F E T c a s c o d e , w h i c h h a s a n infinite i n p u t r e s i s t a n c e , t h e B J T c a s c o d e h a s a n i n p u t r e s i s t a n c e of r ( n e g l e c t i n g r ). T h e f o r m u l a for R is t h e o n e w e f o u n d in t h e analysis
C )R[
L
db
= (5 + 5 + 5 ) 1 0 = 150 ps
Kl
f
H
AMPLIFIER
6.8.3 The BJT Cascode
= - 1 2 . 5 V/V
v
T H EC A S C O D E
=
P
=
L
0
x
m2
6
150 x 10
2KX
/ , = 12.5 x 1.06 = 13.3 G H z For the cascode amplifier: R
'
A„ = A,.°
R
L +
flout 6
4
= - 2 5 x 31 x ^ ° = -388 640 + 640 » in2 -
1 L 7 r~ Smb2 vo2 R
K
+
Sm2
A
V/V
1 ^640 ~7~c 31
_
—
A
= 21.3 kQ R
= 21.3 II 20 = 10.3 k Q
dl
R
% = di(C
+C
sdl
dbl
+ C )-
+ (R || R )(C
gs2
L
om
+C
L
+
gd2
C ) db2
= 10.3(5 + 5 + 20) + (640 II 6 4 0 ) ( 5 + 5 + 5) = 309 + 4800 = 5109 ps fa
=
f= t
T-2 =
3
L
2
M
H
z
In x 5109 x 10 388 x 3 1 . 2 = 12.1 G H z
Thus cascoding increases the dc gain from 12.5 to 388 V/V. The unity-gain frequency (i. gain-bandwidth product), however, remains nearly constant.
6.26 What K the minimum value ol F,., ,„ required I'nr a cascade amplifier upc-rami:: al / - l u u LLA.' I.CI LL„C
OX
=
2
300 ,uA/ V ,
W/L = 10. and
V,„ =
0.6
V.
6.27 Consider a cascode amplifier operating al a bias current / = 100 /JA and for which all transistors have « W/L = 5 //m/0.5 /mi, V\ = 20 V///m, , u „ C , = 190 t / A / V , / = 0 . 2 . C „ = 2 f F , and C - $ m l o r R^ - (j. A', - R . and C = 5 fF (excluding C ), find A . A . A, , ft , R- jR , R , A , / , , and j . {Hint: Use the approximate formula for / ; in Eq. 6.139, but remember to add C._..,.) 2
u
mt
v
Ans.
L
D
DH
0 1
vil2
DB
v
omi
m
dl
ont
H
62
4.2 Ml
\/V: 1/
"5\/V;
~«on \7\ :
IIKI k«2:
i m k i i :
«r
k i 2 : " . ( . M<2-
- ^ ^
\
\
') 8
GHz
(c)
-
FIGURE 6 . 4 0 (a) The BJT cascode amplifier, (b) The circuit prepared for small-signal analysis with various input and output resistances indicated. Note that r is neglected, (c) The cascode with the output open-circuited. x
5 2 3
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
6.8
AMPLIFIERS
of t h e c o m m o n - b a s e circuit (Eq. 6 . 1 1 2 ) . T h e o u t p u t r e s i s t a n c e R - Pr is found by s u b s t i t u t i n g R = r in Eq. (6.119) and m a k i n g t h e approximation that g r 9> ¡3. Recall that Br is the largest output r e s i s t a n c e that a C B transistor can provide. The open-circuit voltage gain A and t h e n o - l o a d i n p u t r e s i s t a n c e R c a n b e found from t h e circuit in F i g . 6.40(c), in w h i c h t h e o u t p u t is o p e n - c i r c u i t e d . O b s e r v e that R = r , w h i c h is u s u a l l y m u c h s m a l l e r t h a n r . A s a result t h e total r e s i s t a n c e between the collector of Q and ground is approximately r ; thus the voltage gain realized in t h e C E t r a n s i s t o r Q is - g r - - / 3 • Recalling that the open-circuit voltage gain of a C B amplifier is ( 1 + g r ) = An, w e see that the voltage gain A is out
e
gX
2
o2
m
0
*
THE CASCODE AMPLIFIER
»
625
-oV„
•
- Kig
R~tt\
0
vo
in2
n2
X
oX
x
x
m
V
r
t
< RL
n
f
A
L
+
—T—
Slg'
Ca
T
' \r
e2
vX
+ Rj{fa
+ C^Rn
nl
K l
m l
r
o2
CR
+
+ (C
+ (C +C L
+
al
+
cs2
C )R M
cX
C , )(R \\R J IJ 2
L
0
Kl
0
v0
A
= -BA
v0
(6.140)
0
AM
• + r + R,
-g (Pr \\R ) m
0
L
v
Putting all of these results together w e obtain for the B J T c a s c o d e amplifier t h e equivalent circuit s h o w n in Fig. 6.41(a). W e n o t e that c o m p a r e d to the c o m m o n - e m i t t e r amplifier, c a s c o d i n g increases b o t h the open-circuit v o l t a g e gain a n d t h e o u t p u t resistance b y a factor equal to t h e transistor /?. This should b e contrasted with the factor A e n c o u n t e r e d in the M O S c a s c o d e . T h e equivalent circuit can be easily c o n v e r t e d to the t r a n s c o n d u c t a n c e form s h o w n in Fig. 6.41(b). It shows that the short-circuit t r a n s c o n d u c t a n c e G of the cascode amplifier is equal to the t r a n s c o n d u c t a n c e g of the B J T s . T h i s should h a v e b e e n expected since Qi p r o v i d e s a current g v to the emitter of the c a s c o d e transistor Q , w h i c h in turn p a s s e s t h e current o n ( a s s u m i n g a = 1) to its collector and to the load resistance R . In the p r o c e s s t h e c a s c o d e transistor r a i s e s t h e r e s i s t a n c e l e v e l from r at t h e c o l l e c t o r of Q to / J r at t h e c o l l e c t o r of Q . T h i s is t h e b y - n o w - f a m i l i a r current-buffering a c t i o n of the c o m m o n - b a s e transistor.
C i cs
0
m
m
mX
t
2
2
K
p
cs
L
0
0
F I G U R E 6 . 4 2 Detenrrining the frequency response of the BJT cascode amplifier. Note that in addition to the BJT capacitances C and C the capacitance between the collector and the substrate C for each transistor are also included.
x
2
T h e voltage gain of the C E transistor Q can b e determined from the equivalent circuit in Fig. 6.41(c). T h e resistance b e t w e e n the collector of Q and ground is the parallel equivalent x
x
of the output resistance of Q , r , and the i n p u t resistance of t h e C B transistor, Q , n a m e l y R . N o t e t h a t for R < r t h e latter r e d u c e s to r , as e x p e c t e d . H o w e v e r , R increases as R is increased. Of particular interest is the value of R obtained for R = Br„, n a m e l y R a r /2. It follows that for this value of R t h e C E stage h a s a v o l t a g e gain o f -8/2 . x
in2
L
a
2
0
e
in2
L
m2
in2
n
L
L
Finally, w e p r e s e n t in F i g . 6 . 4 2 the circuit a n d t h e f o r m u l a s for d e t e r m i n i n g t h e h i g h f r e q u e n c y r e s p o n s e of t h e b i p o l a r c a s c o d e . T h e a n a l y s i s p a r a l l e l s t h a t s t u d i e d in t h e M O S F E T case.
EXERCISE oT^Fx^rcrse 6 ^ 0 ^ " I
T 1
rc S
1S
'T , o S P
e
C 1
*° ? '° a t
u a t e
n S
8 8
^
f
effect of cascoding on the performance of the C E arriphfier ° = > 200, r „ = 1 3 0 k Q , C = 16 p . U
o
w
s
:
/
1
r
F a c i e i 2 0 funl^^^V'l-r' l ' ^ ' * « ' ' ^ P O . K l i n g values obtained Exercise 6.20 for (he C E amphfier. W h a t should C be reduced to in order to have f = 1 MHz-? B
:
m A
f
L
W
i
^ ^ ^ ^ M H zt o
6.8.4 A Cascode Current Source A s mentioned above, to realize the high voltage gain of which t h e cascode amplifier is capable, the load resistance R m u s t be at least o n the order of A r for the M O S F E T cascode or /3r for the bipolar c a s c o d e . R e c a l l , h o w e v e r , that R includes t h e output resistance of the circuit that i m p l e m e n t s t h e current-source load I. It follows that the current-source m u s t h a v e an output r e s i s t a n c e that is at least A r for t h e M O S c a s e (j3r for the B J T case). T h i s rules out u s i n g t h e s i m p l e c u r r e n t - s o u r c e circuits of Section 6.2 since their o u t p u t resistances are 0
o
0
L
FIGURE 6 . 4 1 (a) Equivalent circuit for the cascode amplifier in terms of the open-circuit voltage gain A = -j8A . (b) Equivalent circuit in terms of the overall short-circuit transconductance G — -g . (c) Equivalent circuit for determining the gain of the CE stage, Q . v0
0
m
x
m
0
o
,
B
:^ ^ ^ M ^ ^ ^ ^
L
F
0
626
CHAPTER 6
SINGLE-STAGE
INTEGRATED-CIRCUIT
AMPLIFIERS 6.8
THE CASCODE
AMPLIFIER
"DD
transistor Q is added, with the result that t h e output resistance is increased by the factor A . 3
0 3
T h u s the o u t p u t r e s i s t a n c e of this d o u b l e - c a s c o d e amplifier is A\r . Q
N o t e that an additional
bias v o l t a g e h a s to b e g e n e r a t e d for the additional c a s c o d e transistor BIASI O -
Qi
Q. 3
A d r a w b a c k of d o u b l e c a s c o d i n g is that an additional transistor is n o w stacked b e t w e e n
f
the p o w e r supply rails. F u r t h e r m o r e , since w e are n o w dealing with output resistances on t h e 2
order of A r , n
0
t h e current s o u r c e / will also n e e d to b e i m p l e m e n t e d u s i n g a d o u b l e c a s c o d e ,
which a d d s y e t o n e m o r e transistor to the stack. T h e difficulty p o s e d by_ stacking additional
^BIAS2 ° -
transistors is a p p r e c i a t e d b y recalling that in m o d e r n C M O S p r o c e s s t e c h n o l o g i e s V
DD
is
only a little m o r e than 1 V. 1
Finally, n o t e that since the largest o u t p u t r e s i s t a n c e p o s s i b l e in a bipolar c a s c o d e is
R„^> ?m2r„ )r -i 2
0
Br , 0
adding a n o t h e r level of c a s c o d i n g d o e s not p r o v i d e any a d v a n t a g e .
F I G U R E 6 . 4 3 A cascode current-source.
equal to r . F o r t u n a t e l y , t h e r e i s a c o n c e p t u a l l y s i m p l e a n d effective s o l u t i o n — n a m e l y , applying the cascoding principle to the current-source implementation. T h e idea is illustrated in Fig. 6 . 4 3 , w h e r e <2i is t h e c u r r e n t - s o u r c e transistor a n d Q is t h e c a s c o d e transistor. T h e dc voltage V is c h o s e n so that Q provides the required value of/. V * is chosen t o k e e p Q and £>! in saturation at all times. W h i l e the resistance looking into the drain of Q is r , the cas c o d e transistor Q multiplies this resistance b y (g r ) a n d provides an output resistance for the current s o u r c e g i v e n a p p r o x i m a t e l y b y 0
2
B I A S 1
x
BIAS2
2
y
2
m2
o l
6.8.6 The Folded Cascode T o avoid t h e p r o b l e m of stacking a large n u m b e r of transistors across a l o w - v o l t a g e p o w e r supply, one can u s e a P M O S transistor for the cascode device, as s h o w n in Fig. 6.45. Here, as before, the N M O S transistor Q, is operating in the C S configuration, but the C G stage is
o2
implemented using the P M O S transistor Q . A n additional current-source / 2
Q
2
R
r
o =
(gm2 o2)r l
(6.141)
o
A similar a r r a n g e m e n t can b e used in the bipolar case. W e will study a greater variety of cur rent s o u r c e s a n d c u r r e n t m i r r o r s with i m p r o v e d p e r f o r m a n c e in S e c t i o n 6.12.
and p r o v i d e it with its active load. N o t e that <2i is
(I, - / ) . Finally, a d c voltage V 2
is n e e d e d to bias
2
T h e small-signal o p e r a t i o n of t h e circuit in F i g . 6.45 is similar to that of the N M O S c a s m
2
2
operating at a bias current of
region.
2
Q
w
is needed to provide an appropriate d c level for the gate of
niAS
2
into t h e s o u r c e t e r m i n a l of Q ,
T h e e s s e n c e o f t h e o p e r a t i o n of t h e M O S c a s c o d e is t h a t t h e C G c a s c o d e t r a n s i s t o r
o
the cascode transistor Q . Its value h a s to b e selected so that Q a n d Q, operate in t h e saturation
code. T h e difference h e r e is that t h e signal current g v
6.8.5 Double Cascoding
n
{
is folded
down a n d m a d e to flow 12 T h e
w h i c h g i v e s t h e circuit the n a m e f o l d e d c a s c o d e ,
folded c a s c o d e is a very p o p u l a r b u i l d i n g b l o c k in C M O S amplifiers.
m u l t i p l i e s t h e resistance in its source, w h i c h is r of the C S transistor Q , b y its intrinsic gain 0
A
02
to p r o v i d e an output resistance A r . 02
y
It follows that w e c a n increase the output resistance
ol
further b y a d d i n g a n o t h e r level of c a s c o d i n g , as illustrated in Fig. 6.44. H e r e a n o t h e r C G
-o
V,
*1
^BIASI O -
v o1' i
3 (8m3>-a3Xg r )r m2 o2
oi
=
0
Ql
^ F
0 2
B
o
- o v„
r
(gm2 olK\ ^B!AS2 ° ~
1
1
2
Ar
. 0 2
I
r
ol
FIGURE 6 . 4 5 The folded cascode.
1 2
F I G U R E 6 . 4 4 Double cascodim
The circuit itself can be thought of as having been folded. In this same vein, the regular cascode is sometimes referred to as a telescopic cascode because the stacking of transistors resembles the extension of a telescope.
627
;!
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS 6.9
T H E CS A N D CE A M P L I F I E R S W I T H S O U R C E (EMITTER) D E G E N E R A T I O N
V ' v'
possible with a M O S F E T c a s c o d e . This is b e c a u s e /3 of the B J T is usually larger than A of the M O S F E T and, m o r e importantly, because r of the B J T is m u c h larger than r of m o d e r n submicron M O S F E T s . A l s o , the bipolar C B transistor p r o v i d e s a l o w e r input resistance R than is usually obtained with a C G transistor, especially w h e n R is low. T h e result is a lower total resistance between the drain of g and ground and hence a reduced Miller effect in Q . T h e circuit in Fig. 6.46(b) utilizes a M O S F E T to implement the second level of cascoding in a bipolar c a s c o d e amplifier. T h e need for a M O S F E T stems from the fact that w h i l e t h e m a x i m u m p o s s i b l e output resistance obtained w i t h a B J T is Br , there is n o such limit w i t h the M O S F E T , and indeed, Q raises the output resistance b y the factor A . 0
0
6.29 Consider the folded-eascode amplifier of Fig. 6.45 for the ease: V - 1.8 V, k' - \k' , and V = ••}~V - 0.5 V. T o operme Q and £> at equal bias currents /. / , -21 and I, -- /. While current source /', is implemented using the simple circuit studied in Section 6.2, current source l is realized iisiae a ca«eoded circuit fi.e.. the N M O S version of" the circuit in Fig. 6.43). The transistor \ML ratios are selected so that each operates at an overdrive voltage of 0>2 V. (a) W h a t must the relationship of (W/L) to ( T O ) , be? DD
t
x
p
n
m
2
2
2
(b)" W h a t is the minimum dc voltage required for the proper operation of current-source / , ? N o w , if a 0.1-V peak-to-peak signal swing is to be allowed at the drain of £>,. what is the highest dc bias voltage that can be used at that node? (c) W h a t is the value of V . of 0 , and hence what is the largest value to which V S(
2
B 1 A S
(d) What is the minimum dc voltage required for the proper operation of current-source
0
m2
L
2
Y
0
3
0 3
can be set? I! 2
6.30 For / = 100 p:A find G , R , and the open-circuit voltage gain A „ of the B i C M O S cascode ampli fiers in Fig. 6.46. F o r ' t h e BJTs, V = 50 V and B = 100. For the M O S F E T s , V = 5 V, ,u C = 2 0 0 , u A / V , a n d W / L = 25. m
(e) Given the results of (c) and (d), what is the allowable range of signal swing at (he output?
mv
v
A
Ans. fa) (VV7L), = 4(YV7/_),; (b) 0.2 V, 1.55 V: (c) 0.7 V, 0.85 V: (d) 0.4 V; (c) 0.4 V to 1.35 V
A
Ans. For the circuit in Fig. 6.46(a): 1 mA/V, 50 M Q , - 5 x If) 4 m A A ' . 2500 M Q . - 1 0 ' V7V.
4
^ f ? 6.9 THE CS AND CE AMPLIFIERS WITH SOURCE (EMITTER) DEGENERATION Inserting a relatively small resistance (i.e., a small multiple of l/g ) in t h e source of a C S amplifier (the emitter of a c o m m o n - e m i t t e r amplifier) introduces n e g a t i v e feedback into the amplifier stage. A s a result this resistance p r o v i d e s t h e circuit designer w i t h an additional p a r a m e t e r that can b e effectively utilized to obtain certain desirable properties as a trade-off for the g a i n r e d u c t i o n that source (emitter) degeneration c a u s e s . W e h a v e already seen s o m e of this in Sections 4.7 a n d 5.7. In this section w e consider source and emitter degeneration in I C amplifiers w h e r e r and g h a v e to b e taken into account. W e also d e m o n s t r a t e the u s e of source (emitter) d e g e n e r a t i o n to extend t h e amplifier b a n d w i d t h . m
B
mb
6.9.1 The CS Amplifier with a Source Resistance Figure 6.47(a) s h o w s an active-loaded C S amplifier w i t h a source resistance R . N o t e that a signal v will develop between b o d y and source, and hence the b o d y effect should be taken into account in t h e analysis. T h e circuit, p r e p a r e d for small-signal analysis and w i t h a resistance R s h o w n at t h e output, is presented in Fig. 6.47(b). T o d e t e r m i n e t h e output resistance i ? , we r e d u c e v to zero, w h i c h m a k e s t h e circuit identical to that of a C G amplifier. Therefore w e can obtain i ? b y u s i n g Eq. (6.101) as s
bs
L
o u t
t
o u t
A c t = r +[l
+ (g
0
which for the usual situation (g
+ g )r
m
mb
R
oa
( a )
(b)
m
+ g )r ]R mb
0
(6.142)
s
> 1 r e d u c e s to
0
= r [l+(g 0
m
+ g )R ] mb
s
•
(6.143)
T h e open-circuit v o l t a g e gain can b e found from t h e circuit in Fig. 6.47(c). N o t i n g that the current in R m u s t b e zero, the voltage at the source, v , will b e z e r o and thus v - v a n d v = 0, resulting in s
bs
FIGURE 6 . 4 6 BiCMOS cascodes.
0J!
V / V ; for the circuit in Fig. 6.46(b):
6.8.7 BiCMOS Cascodes As m e n t i o n e d before, if t h e t e c h n o l o g y p e r m i t s , t h e circuit d e s i g n e r c a n c o m b i n e bipolar a n d M O S transistors in circuit configurations that take a d v a n t a g e of t h e u n i q u e features of each. A s an e x a m p l e , F i g . 6.46 s h o w s t w o possibilities for the B i C M O S i m p l e m e n t a t i o n of the c a s c o d e amplifier. In t h e circuit of Fig. 6.46(a) a M O S F E T is u s e d for t h e input device, t h u s p r o v i d i n g the c a s c o d e with an infinite input resistance. O n t h e o t h e r hand, a bipolar transistor is u s e d for t h e c a s c o d e device, t h u s p r o v i d i n g a larger output resistance than is
n
2
s
gs
t
6 3 0
CHAPTER 6
SINGLE-STAGE
INTEGRATED-CIRCUIT
AMPLIFIE 6.9
T H ECS A N DCE AMPLIFIERS WITH SOURCE
The effect of R is thus obvious: R reduces S
output
S
resistance
by the same factor:
the amplifier
[1 + (g
transconductance
+ g )R ].
m
MB
(EMITTER)
DEGENERATION
and increases
its
W e will find in C h a p t e r 8 w h e n
S
w e study n e g a t i v e f e e d b a c k formally that this factor is t h e amount
of negative
feedback
introduced b y R . S
j
vo t
VjO-
a—j
Vi
1
f
T h e v o l t a g e g a i n A c a n b e found as v
A
v
-Avoy^r
=
K
L
0V<
Thus, if R
is k e p t u n c h a n g e d , A
L
Vhs =
0
(6-145)
+ "out
will decrease, w h i c h is t h e p r i c e p a i d for t h e p e r f o r m a n c e
v
improvements obtained when R
is introduced. O n e such i m p r o v e m e n t is in t h e linearity of
S
the amplifier. T h i s c o m e s a b o u t b e c a u s e only a fraction v
' 8mb)R-s\
of t h e i n p u t signal v n o w
gs
t
appears b e t w e e n gate a n d source. Derivation of an expression for v /v gs
is significantly c o m -
i
plicated b y the inclusion of r . T h e derivation should b e d o n e with t h e M O S F E T equivalent0
circuit m o d e l explicitly used. T h e result is (a)
(b)
(c) v
gs
A L II
1
w h i c h for r > R 0
O -
o
L
L
r e d u c e s t o t h e familiar relationship
=
1
Vi
_
flout
R
Vi ~ 1 + (gm + gmbWs
R •
-V\Ar
_
T h u s t h e v a l u e of R
l + (g
(6.147) R
+
m
gmb) s
c a n b e u s e d t o c o n t r o l t h e m a g n i t u d e of v
S
gs
s o as t o o b t a i n t h e
d e s i r e d l i n e a r i t y — a t t h e e x p e n s e , of course, of gain r e d u c t i o n .
Frequency Response
GL
A n o t h e r a d v a n t a g e of s o u r c e d e g e n e r a t i o n is t h e ability t o
b r o a d e n t h e amplifier b a n d w i d t h . F i g u r e 6.48(a) s h o w s t h e amplifier w i t h t h e internal
1
I + fe, + £ )flJ m6
capacitances C
gs
( d )
(e)
tance C
db
and C
gd
indicated. A c a p a c i t a n c e C
L
that includes
the M O S F E T capaci-
is also s h o w n at t h e output. T h e m e t h o d of open-circuit t i m e constants c a n b e
e m p l o y e d t o o b t a i n an e s t i m a t e of t h e 3 - d B f r e q u e n c y f .
T o w a r d t h a t e n d w e s h o w in
H
Fig. 6 . 4 8 ( b ) t h e circuit for d e t e r m i n i n g R ,
w h i c h is t h e r e s i s t a n c e seen b y C .
GD
o b s e r v e that R
GD
We
GD
c a n b e d e t e r m i n e d b y s i m p l y a d a p t i n g t h e f o r m u l a i n E q . (6.56) t o t h e c a s e
with s o u r c e d e g e n e r a t i o n as follows: and
R =
R (l
GD
ö
Thus,
17 '
u
m' o gs
n
w
+ G R[)+R[
(6.148)
aat
(6-149)
sig
M
where
i
Ri=RjR r
A
8m o ~ -~AQ
V0
In o t h e r w o r d s , the resistance Utilizing A
= -A
0
R
T h e f o r m u l a for R
CL
c a n b e seen to b e s i m p l y
has no effect on A J
S
a n d tf
e q u i v a l e n t exreuxt s h o w n in F i g . 6.47(d). A n alternative e q u i v a l e n t circuit in short-cnxmt transconductance G
M
R=
is s h o w n in F i g . 6.47(e), where G
M
term7ofte
c a n b e founcl from
T h e formula for R
GS
is the m o s t difficult to derive, a n d the derivation should b e performed
GS
Thus,
n
0
+
=
R ^
+
R
_
S
(
6
1
5
1
)
{g + )R ] M
GMB
S
i+(g
m
G
M
' + (g„, +
(6-150)
with t h e h y b r i d - n m o d e l explicitly utilized. T h e result is R
r
R J FLOM = RL
CL
from E q . (6.143) e n a b l e s u s to obtain t h e amplifier o u t o u t
out
(6.144)
g )R MB
S
When R
SIG
+
gmb)R
!
r„ + R,
is relatively large, t h e frequency r e s p o n s e will b e d o m i n a t e d b y t h e M i l l e r
multiplication of C . GD
A n o t h e r w a y for s a y i n g this is that C R GD
GD
will b e t h e largest of t h e
.
J
631
CHAPTER
6
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS 6.9
•f
f
+•
T H E CS A N D CE AMPLIFIERS W I T H S O U R C E (EMITTER)
DEGENERATION
633
which can b e substituted in E q . (6.154) to obtain
-gd
wv <•
/ H =
^—; 2nC R \A \ gd
sig
1
(6.155)
M
which very clearly shows the g a i n - b a n d w i d t h trade-off. T h e g a i n - b a n d w i d t h product r e m a i n s
4>
constant at G a i n - b a n d w i d t h product, / , = \A \f M
r
H
=
* 2%C R gd
(6.156) Ag
In practice, h o w e v e r , the other capacitances will p l a y a role in d e t e r m i n i n g f , H
decrease s o m e w h a t as R
s
(a) D o-
and / , will
is increased.
.D
Vx
GO
0 #!T"
6.31 Consider a CS amplifier having g„,= 2 m A 7 V , r„ = 20 k Q , R = 20 k Q , # = 20 k Q , C = 20 IE, C = 5 IE, and C = 5 fF. (a) Find the voltage gain A and the 3-dB frequency f (using the method of open-circuit time constants) and hence the gain-bandwidth product, (b) Repeat (a) for the case in which a resistance R is connected in series with the source terminal with a value selected so that (g, + g )R = 2. L
d
YG.V:
T
L
i i g
gs
M
H
s
n
Ans.
mb
s
(a) - 2 0 V/V, 61.2 M H z , 1.22 GHz; (b) - 1 0 V/V, 109.1 MHz, 1.1 GHz
6.9.2 The CE Amplifier with an Emitter Resistance (b) FIGURE 6 . 4 8 (a) The CS amplifier circuit, with a source resistant P ™ analysis, (b) Determining the resistance seen b y T ^ ^ T c ^ ' "
^ ?
r "
^
™
—
Emitter d e g e n e r a t i o n is e v e n m o r e useful in the C E amplifier than source degeneration is in the C S amplifier. T h i s is b e c a u s e emitter d e g e n e r a t i o n increases the input resistance of the C E amplifier. T h e input resistance of the C S amplifier is, of c o u r s e , practically infinite to start with. F i g u r e 6.49(a) s h o w s an active-loaded C E amplifier with an emitter resistance R , usually in t h e r a n g e of 1 to 5 times r . F i g u r e 6.49(b) s h o w s t h e circuit for determining the e
e
r,
three open-circuit t i m e constants that m a k e u p T
=
H
enabling u s t o a p p r o x i m a t e x
C
R
G S
G S
+ C
H
R
G D
G
D
+
C
L
R
C
(6.152)
L
as
H
T
H
a n d c o r r e s p o n d i n g l y to obtain f
=
C
gd
Rgd
(6.153)
as
H
flj o-
_1 (6.154) N o w , as R »
decease
sron ror
(E,.
cT^i^^^^fc
is increased, the gain m a g n i t u d e ,
M
8
)
,
8 w
h
i
c
h
i
n
t
l
m
U
m Eq. (6.148) b y a s s u m i n g that G R[ m
R
gJ
=
I-
r
§> \ and G R m
G RlR =\A \R m
»'
sig
u
&ig
sig
> 1,
(a)
(b)
(c)
FIGURE 6 . 4 9 A CE amplifier with emitter degeneration: (a) circuit; (b) analysis to determine R ; and (c) analysis to determine A . in
v 0
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
input resistance R , which due to the presence of r will depend on the value of R, aid of the analysis shown in Fig. 6.49(b), w e can express the output voltage v as in
THE SOURCE A N D EMITTER FOLLOWERS
6.10
W i t h the
D
T h e high-frequency r e s p o n s e of the C E amplifier with emitter d e g e n e r a t i o n can b e found in a m a n n e r similar to that presented a b o v e for the C S amplifier.
0
In s u m m a r y , including a relatively small resistance R
(i.e., a small multiple of r )
e
(l~a)i
in the
e
emitter of the active-loaded C E amplifier reduces its effective transconductance b y the factor (1 + g R )
Alternatively, w e c a n express v as
m
and increases its output resistance b y the s a m e factor, thus leaving the open-circuit
e
0
voltage gain approximately unchanged. T h e input resistance R
in
V; -
(Vi-ir )-r e
ir„
depends o n R
and that is s o m e w h a t lower than ( 1 + g R ).
L
m
e
is increased b y a factor that
A l s o , including R
e
reduces the
B
severity of the Miller effect and correspondingly increases the amplifier bandwidth. Finally,
R„
an e m i t t e r - d e g e n e r a t i o n resistance R increases t h e linearity of t h e amplifier. e
t
foMn
h
6
S
e
e
X
p
r
e
S
S
i
0
n
S
°
f
V
°
y
i
e
M
s
a
n
e
u
1
a
t
i
o
n
i n
*i
a
r + n
= (P + \)r
n
d
w h i c h c a n b e rearranged
——
6.32 Consider the active-loaded C E amplifier with emitter degeneration. Let / = 1 mA, V = 100 V B = 100. Find R , R„. A. , G„„ and the overall voltage gain v /v when R = 75 Q , K „ = 5 atid/?/^ = 2r . A
+ {P+l)R
e
(6.157)
e
m
M
a
s;g
e
n
Ans. 5 kSl: 400 k Q ; - 4 0 0 0 V/V; 10 mA/V; - 6 6 7 V/V
U s u a l l y R is o n t h e o r d e r of r ; t h u s R /(B + 1 )
0
L
0
e
0
in
^
= (0+1)^ + 0 8 + 1 ) * , — 1 —
(6.158)
| 6.10 THE SOURCE AND EMITTER FOLLOWERS This e x p r e s s i o n indicates that t h e p r e s e n c e of r r e d u c e s t h e effect of R o n i n c r e a s i n g R . T h i s is b e c a u s e r„ s h u n t s a w a y s o m e of t h e c u r r e n t that w o u l d h a v e f l o w e d t h r o u g h R . F o r e x a m p l e , f o r K = r , R = (B +l)(r + 0.5R ). 0
e
m
e
L
0
t
e
e
T o detenrrine the open-circuit voltage gain A , w e utihze the circuit shown in Fig. 6.49(c). A n a l y s i s of this circuit is straightforward a n d can b e s h o w n to yield u o
Ko
= -g r m
(6.159)
0
T h a t is, t h e o p e n - c i r c u i t v o l t a g e g a i n obtained w i t h a relatively s m a l l R (i.e., on t h e o r d e r of
T h e discrete-circuit s o u r c e follower w a s p r e s e n t e d in S e c t i o n 4.7.6 and t h e discrete-circuit emitter follower in S e c t i o n 5.7-6. In t h e following discussion w e c o n s i d e r their I C versions, p a y i n g special attention to their high-frequency r e s p o n s e .
6.10.1 The Source Follower F i g u r e 6.50(a) s h o w s a n I C s o u r c e follower b i a s e d b y a c o n s t a n t - c u r r e n t s o u r c e / , w h i c h is
e
r) e
r e m a i n s v e r y c l o s e to the value w i t h o u t
T h e output resistance R (Eq. 6.118),
usually i m p l e m e n t e d u s i n g an N M O S current mirror. T h e source follower w o u l d generally be
R. e
is identical to the value of i ?
0
o u t
that w e derived for the C B circuit
part of a larger circuit that d e t e r m i n e s t h e dc voltage at t h e transistor gate. W e will e n c o u n t e r such circuits in the following chapters. H e r e w e note that v is the input signal appearing at the t
gate and that R
L
R
D
w h e r e R' = R II r . Since R Thus, e
e
K
e
= r (l
+ g R' )
0
m
is on the order of r , R e
,
e
e
(6.160)
is m u c h smaller than r
n
and R'
=
e
represents the combination of a load resistance and the output resistance of
the current-source I. T h e l o w - f r e q u e n c y small-signal m o d e l of the source follower is s h o w n in F i g . 6.50(b).
R. e
O b s e r v e that r a p p e a r s in parallel with R a
R
0
= r (l+g R ) 0
m
(6.161)
e
mb
-v . bs
T h e expressions for *
i n
, A, v0
and R
0
in E q s . (6.158), (6.159),-and (6.161), respectively, c a n
T h u s w e c a n u s e t h e source-absorption t h e o r e m ( A p p e n d i x C ) to replace t h e current mb
with R
resistance. Finally, w e should m e n t i o n that- A
in Fig. 6.50(c), w h e r e
v0
m
and R
a
c a n b e u s e d t o find t h e effective-
L
~
b e t w e e n t h e s o u r c e and g r o u n d , this c a n then be c o m b i n e d
a n d r . W i t h t h e s e t w o simplifications, the e q u i v a l e n t circuit takes t h e form s h o w n 0
of t h e e m i t t e r - d e g e n e r a t e d C E amplifier as f o l l o w s : 4 m
feeds its current into t h e s o u r c e terminal, w h e r e the voltage is
bs
source with a r e s i s t a n c e l/g
b e u s e d to d e t e r m i n e t h e overall voltage gain for g i v e n v a l u e s o f s o u r c e r e s i s t a n c e a n d load short-circuit t r a n s c o n d u c t a n c e G
and thus c a n b e c o m b i n e d with it. A l s o , the c o n
L
trolled c u r r e n t - s o u r c e g v
R> =
R \\r \\±gmb
L
L
(6.163)
R„ W e n o w c a n w r i t e for t h e output voltage
Thus,
v,
V = 0
1 +
0
g Re m
w h i c h is identical to t h e expression w e f o u n d for t h e d i s c r e t e c a s e in S e c t i o n 5.7.
and for
0
(6.164)
gmV R gs
L
v, gs
(6.165)
si
636
fg|/
CHAPTER 6
SINGLE-STAGE INTEGRA TED-CI RCUIT
AMPLIFIERS 6.10
D DD
A G
THE SOURCE A N D EMITTER FOLLOWERS
63
Finally, w e can find the output resistance R of the source follower either u s i n g t h e equivalent circuit of F i g . 6.50(c) or b y inspection of the circuit in F i g . 6.50(d) as 0
,1—J B
R
= —j gm
0
II r
(6.169)
B
gmb
which can b e a p p r o x i m a t e d as i? =l/[(l+*)g ]
- o v„
0
©k
(6-170)
m
Similar to the discrete source follower, the I C source follower can b e u s e d as the output stage of a m u l t i s t a g e amplifier to p r o v i d e a l o w output resistance for driving l o w - i m p e d a n c e loads. It is also u s e d to shift the dc level of the signal b y an a m o u n t equal to V . GS
(a)
(b)
L
06.33 A source follower for which k' = 200 u A / V , V = 20 V/,i
n
u
2
u
5
ü m
A
t
mb
.1—
1
B
m
0
Ans. 360 u A ; 2.4 m A / V ; 0.48 mA/V: 27.8 k Q ; 0.82 V/V; 343 Q ; 0.61 V/V ?m 8mb
6.10.2 Frequency Response of the Source Follower
1 (c)
A major advantage of the source follower is its excellent high-frequency response. This c o m e s about because, as w e shall n o w see, none of the internal capacitances suffers from the Miller effect. Figure 6.51 (a) shows the high-frequency equivalent circuit of a source follower fed with a signal V from a source having a resistance R . In addition to the M O S F E T capacitances C and C , a capacitance C is included b e t w e e n the output n o d e and ground to account for the source-to-body capacitance C as well as any actual load capacitance. sig
(d)
sig
gd
FIGURE 6 5 0 (a) An IC source follower, (b) Small-signal equivalent-circuit model of the source follower
folloteT
V e l
'
S I O n
1116
e q U 1 V a l e n t
C k c u i t
( d )
Determining the output resistance of the source
Equations (6.164) and (6.165) can be c o m b i n e d to obtain the v o l t a g e gai am
= —=
A
R
8m L
m L
(6.166) w h i c h , as expected, is less t h a n unity. T o o b t a i n t h e o p e n - c i r c u i t v o l t a g e g a i n w e set R, in E q (6.163) to w h i c h r e d u c e s R' to r \\ (\/g ). S u b s t i t u t i n g this v a l u e for R[ in E q . ( 6 . 1 6 6 ) gives L
a
mb
L
gs
L
sb
T h e simplifications performed a b o v e o n t h e low-frequency equivalent circuit can b e a p p l i e d to t h e h i g h - f r e q u e n c y m o d e l of F i g . 6.51(a) to o b t a i n t h e e q u i v a l e n t c i r c u i t in F i g . 6.51(b), w h e r e R[ is given b y Eq. (6.163). A l t h o u g h o n e can derive an expression for t h e transfer function of this circuit, the resulting expression will b e too complicated to yield insight regarding the role that each of the three capacitances plays. Rather, w e shall first deter m i n e the location of the transmission zeros and then use the method of open-cncuit time con stants to estimate t h e 3-dB frequency, / . A l t h o u g h there are three capacitances in t h e circuit of F i g . 6.51(b), the transfer function is of the s e c o n d order. This is b e c a u s e the three capacitances f o r m a c o n t i n u o u s l o o p . T o d e t e r m i n e t h e location of t h e t w o transmission zeros, refer to t h e circuit in Fig. 6.51(b), and n o t e that V is z e r o at t h e frequency at w h i c h C h a s a zero i m p e d a n c e a n d thus acts as a short circuit across the output, w h i c h is co or s — °°. Also, V will b e zero at the value of s that causes the current into the impedance R[ II C to be zero. Since this current is (g + sC )V , the t r a n s m i s s i o n z e r o will b e at s = s , w h e r e 3 d B
0
L
0
§m^"o
A„„ — l
which, for the usual case w h e r e (g
m
+g r mb)
A„„ =
o
+
(gm +
L
(6.167)
g )r mb
> l, simplifies to
gs
gs
(6.171)
1 (6.168)
T h u s the highest value possible for the v o l t a g e gain of t h e source follower is limited to ( 1 +X), which is typically 0.8 V / V to 0.9 V / V . 1 7
m
z
0
T h a t is, the zero will b e o n t h e negative real-axis of the s-plane w i t h a frequency co = ^ z
(6.172)
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS THE SOURCE A N D EMITTER FOLLOWERS
6.10
W e note that the factor (1 + g R' ) in the d e n o m i n a t o r will result in r e d u c i n g the effective resistance with which C interacts. In the absence of the two other capacitances, C together with R i n t r o d u c e a pole with frequency l/2nC R. Finally, it is easy to see from the circuit in Fig. 6.51(b) that C interacts with R II R ; that is, M
L
gs
gs
gs
gs
gs
L
RC
=
L
0
RLWRO
Usually, R (Eq. 6.169) is low. T h u s R will b e low, a n d the effect of C will b e small. Nevertheless, all three time constants can b e a d d e d to obtain % and h e n c e f , 0
c
L
H
AAA,
^ T J - = l/2n(C R
fn=
(a)
gd
+CR
sig
gs
+ CRJ
gs
L
(6.176)
C
• o-
AAAy
-d g
6.34 Consider a source follower specified as follows: W/L = 7.2 /im/0.36 um. I = 100 fiA, g = 1.25 mAyV. X = 0 . 2 . /•„ = 20 k Q . R „ = 20 k Q , R = 10 k Q , C., = 2 0 t F . C\, = 5 fF, and c' = 15 fF. Find A , fyi and f . Also, find R , R^. R $:and hence t h e t i m e constant associated with each of the three capacitances G , C , md € . Find and the percentage contribution to it from each of three capacitances. Find;/},.
•
n
e V
4
S
T
v
y
5/r/ gs
z
gd
gd
v
(c)
T
m
+ C
gs
g r f
) and that C
gd
es
L
6.10.3 The Emitter Follower
< C,
w e see that % will
gs
T
fz=
fr
(6-173)
Next, w e turn o u r attention to the p o l e s . Specifically, w e w i l l find the resistance s e e n b y each of three capacitances C , C , and C a n d t h e n c o m p u t e the time constant associated w i t h each. W i t h V set to zero a n d C a n d C a s s u m e d to b e o p e n circuited, w e find by inspection that the resistance R seen by C is given by gd
gs
L
sig
gs
L
gd
gd
Figure 6.52(a) s h o w s an emitter follower suitable for IC fabrication. It is biased by a constantcurrent source /. H o w e v e r , the circuit that sets the dc voltage at the base is not s h o w n . T h e emitter follower is fed with a signal V from a source with resistance R . The resistance R , s h o w n at the output, includes the output resistance of current source / as well as any actual load resistance. A n a l y s i s of the emitter follower of Fig. 6.52(a) to d e t e r m i n e its low-frequency gain, input resistance, a n d output resistance is identical to that performed on the capacitively cou pled version in Section 5.7.6. Indeed, the formulas given in T a b l e 5.6 can b e easily adapted for the circuit in Fig. 6.52(a). Therefore w e shall concentrate h e r e on the analysis of the high-frequency r e s p o n s e of the circuit. F i g u r e 6.52(b) s h o w s the high-frequency equivalent circuit. L u m p i n g r together w i t h R and r together w i t h R and m a k i n g a slight c h a n g e in the w a y the circuit is d r a w n results in the simplified equivalent circuit s h o w n in Fig. 6.52(c). W e will follow a p r o c e d u r e for the analysis of this circuit similar to that u s e d a b o v e for the s o u r c e follower. Specifically, to obtain the location of the transmission zero, note that V will b e zero at the frequency s for w h i c h the current fed to R[ is zero:
]
• R
gd
slg
(6.174)
T h i s is intuitively o b v i o u s : B e c a u s e of the g r o u n d at the drain terminal, the input capaci tance of the source follower, in the a b s e n c e of C
gs
a n d C , is e q u a l to C . L
form a high-frequency pole. Next, w e consider t h e effect of C . T h e resistance R seen by C straightforward analysis of the circuit in Fig. 6.51(c) to o b t a i n
gd
Thus, R
si$
and
sig
L
0
L
R
L
c
sig
Recalling that t h e M O S F E T ' s co = g /(C be v e r y close to co ,
m
d
Arts. 0.76 V/V-WGHz; 10 GHz; 20 k Q ; 5.45 k Q : 0.61 k Q ; 100 ps; 109 ps; 9 ps; 218 ps; 4 6 % ; 50%: 4 % ; 73u M l ! /
•R'r
(b)
L
x
sig
0
z
C
gd
gs
gs
gs
can be determined by
8V +
— +
g
+ (l/r )
1
r
C r
m
JC
s C =0 z
7t
Thus, n
_ g s
~
R
-"-sis sig
"L + R[ 1 + oRC ^+g R' M
T
L
(6-175)
m
n
(6.177)
639
640
•
•/
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS
6.11
"cc
W e observe that the t e r m R[ /r
ft
-VW—o-
IE
-vw
¡I
<
sig
thus rendering R
M
X
will b e small. T h e end result is'
of t h e emitter follower,
H
4> -AAA-
N
rather low. T h u s , the t i m e constant C R
that the 3-dB frequency f
USEFUL TRANSISTOR PAIRINGS
will usually m a k e the d e n o m i n a t o r m u c h greater than unity,
e
A
SOME
f
H
= l/lTtlC^+C^]
(6.181)
will usually be very high. W e urge the reader to solve the following exercise to gain famiharity with typical values o f the various p a r a m e t e r s that d e t e r m i n e
f. H
-o
6.35 For an emitter follower biased at I = 1 m A and having R = R = 1 k O , r ~ 100 k O , B~ 100, 0^ = 2 pF, and f = 400 M H z , find the low-frequency gain, f , R^, R , and -f . C
(a)
SIG
T
(b)
L
0
z
M
H
Ans. 0.965 V/V; 458 MHz; 1.09 k Q ; 51 Q ; 55 M H z
B'
0
J=c,
c ±
r
T h e cascode configuration studied in Section 6.8 c o m b i n e s C S a n d C G M O S transistors ( C E and C B bipolar transistors) to great a d v a n t a g e . T h e key to t h e superior p e r f o r m a n c e of the resulting c o m b i n a t i o n is that the transistor p a i r i n g is d o n e in a way that m a x i m i z e s the advantages a n d m i n i m i z e s the s h o r t c o m i n g s of each of the t w o individual configurations. In this section w e study a n u m b e r of other such transistor pairings. In e a c h case the transistor pair can b e t h o u g h t of as a c o m p o u n d device; thus the resulting amplifier m a y be considered as a single stage.
R'L-
R'L =
\ 6.11 SOME USEFUL TRANSISTOR PAIRINGS
Rdr
0
(c) FIGURE 6 . 5 2 (a) Emitter follower, (b) High-frequency equivalent circuit (c) Simplified equivalent circuit.
6.11.1 The CD-CS, CC-CE and CD-CE Configurations w h i c h is on the n e g a t i v e real-axis of the s-plane a n d h a s a frequency 1
co
Figure 6.53(a) s h o w s an amplifier formed b y c a s c a d i n g a c o m m o n - d r a i n (source-follower) transistor Q w i t h a c o m m o n - s o u r c e transistor Q - A s should b e expected, the voltage gain of the circuit will b e a little l o w e r than that of t h e C S amplifier. T h e a d v a n t a g e of this circuit Y
(6.178)
7
2
This frequency is very close to the unity-gain frequency co of the transistor. T h e other transmission zero is at s - °°. This is because at this frequency, acts as a short circuit, making V zero, a n d h e n c e V will b e zero. T
K
0
Next, w e detenriine the resistances seen b y a n d C . For the reader should be able to s h o w that the resistance it sees, R , is the parallel equivalent of # ' and the input resistance l o o k i n g into B ' ; that is, %
M
s
ig
(6.179) E q u a t i o n (6.179) indicates that will b e smaller than R' , and s m c e C is usually very small, t h e t u n e constant C R will be c o r r e s p o n d i n g l y small " R f l
SIG
U
Y
M
M
e m o W ^ T H f" ^ f * e m p l o y e d for the d e t e r m i n a t i o n of R
GS
D E T E R M I N E D
U S I
^ » S » analysis similar to that in t h e M O S F E T c a s e . T h e result is R' +R'
R
SIG
1 +
R~ke
L
.
R'l
(6.180)
(a)
(b)
FIGURE 6 . 5 3 (a) CD-CS amplifier, (b) CC-CE amplifier, (c) CD-CE amplifier.
(c)
6 4 1
HARTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
6.11
AMPLIFIERS
configuration, h o w e v e r , lies in its b a n d w i d t h , w h i c h is m u c h w i d e r than that o b t a i n e d in a C S amplifier. T o see h o w this c o m e s about, n o t e that the C S transistor Q will still exhibit a M i l l e r effect that results in a large input capacitance, C , b e t w e e n its gate and ground. H o w e v e r , t h e resistance that this c a p a c i t a n c e interacts w i t h will b e m u c h l o w e r than R ; the buffering action of the source follower causes a relatively l o w resistance, a p p r o x i m a t e l y equal to a l/(g + gmbi), to appear b e t w e e n t h e source of Q and g r o u n d across C .
^
USEFUL TRANSISTOR PAIRINGS
= - 8 ^ = - 4 0 x 4 = - 1 6 0 V/V
'¿2
2
i n 2
SOME
Thus,
sig
ml
Y
A „
=
-^2- = - 1 6 0 x 0.99 x 0.98 = - 1 5 5 V/V V Slg
i n 2
T h e bipolar counterpart of the C D - C S circuit is s h o w n in Fig. 6.53(b). B e s i d e achieving a w i d e r b a n d w i d t h than that obtained w i t h a C E amplifier, the C C - C E configuration h a s an i m p o r t a n t additional advantage: T h e input resistance is increased b y a factor e q u a l to (Pi + 1). Finally, w e s h o w in Fig. 6.53(c) the B i C M O S version of this circuit type. Observe that Qi provides the amplifier with an infinite input resistance. Also, note that Q provides the amplifier with a high g as compared to that obtained in the M O S F E T circuit in F i g . 6.53(a) and h e n c e high gain.
To determine f
H
circuit with V
slo
w e use the method of open-circuit time constants. Figure 6.54(b) shows the
set to zero and the four capacitances indicated. Capacitance
sees a resis-
tance R MI' Ä„l
=
A s i g II A i n
= 4 II 255 = 3.94 k Q
2
m
Consider a C C - C E amplifier such as that in Fig. 6.53(b) with the following specifications: I = I = 1 mA and identical transistors with 6 = 100, f = 4 0 0 M H z , and = 2 p F . Let the amplifier be fed with a source having a resistance R :„ = 4 k Q , and assume a load resistance of 4 k Q . Find the voltage gain A , and estimate the 3-dB frequency, f . Compare the results with those obtained with a C E amplifier operating under the same conditions. For simplicity, neglect r and r . x
2
T
K
M
H
D
x
(a)
Solution At an emitter bias current of 1 mA, Q
and Q
x
1
have
2
40mA/V
8m
flsig
I—w*-
= 25 Q
r
e
r
K =
ß_
=
8m
c +c =
100 r, r , P . — = 2.5 k Q 40 8
8m
ffl
->1 •
m
2nf
r
T
(b) In
x 400 x 1 0
6
C„ = 2 p F C„ = 13.9 p F The voltage gain A
M
can be determined from the circuit shown in Fig. 6.54(a) as follows:
R
sig
Rim = r*i = 2-5 k Q R= ia
( A + l)(r +i? e l
i n 2
)
= 101(0.025 + 2.5) = 255 k Q (c) FIGURE 6 . 5 4 Circuits for Example 6.13: (a) The CC-CE circuit prepared for low-frequency analysis; (b) the circuit at high frequencies, with V set to zero to enable determination of the open-circuit time constants; and (c) a CE amplifier for comparison. sig
'__5>
643
644
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS
w e refer to the analysis of the high-
R=
rjR =
frequency response of the emitter follower in Section 6.10.3. Specifically, w e adapt Eq. (6.180) to
R^=
(l+g R )(R \\r )
T o find the resistance R
seen b y c a p a c i t a n c e C
nl
Kl
SOME
6.11
M
2.5 II 4 = 1.54 k Q
sig
m
USEFUL TRANSISTOR PAIRINGS
L
sig
+ R
w
L
the situation here as follows: R.¡
= (l+40x4)(4||2.5) + 4
R,in2
R~ 1 +-
= 251.7 k Q
Mn2 Thus,
4000 + 2500 1
4000
¡
2500 Capacitance C
sees a resistance
K2
: 63.4 Q
T
H =
2500
|
25
C
n
R
n
+
C
R
n [i
= 1 3 . 9 x 1.54 + 2 x 2 5 1 . 7
R , n2
= 2 1 . 4 + 503.4 = 524.8 ns R
R
=
n2
in2
11
floutl
Observe the dominant role played b y C^. T h e 3-dB frequency f
is
H
R<
= 2500 I 25 +
f
+ l.
A
H
= — i -= ^ ^H 2 ^ x 5 2 4 . 8 x 10
= 303 k H z
2
4000
63 Q
101
Thus, including the buffering transistor Q increases the gain, \A \, from 61.5 V/V to 155 V / V — x
M
a factor of 2.5—and increases the bandwidth from 303 k H z to 4.2 M H z — a factor of 13.9! T h e Capacitance C ^ sees a resistance R^ . T o determine R^ 2
2
2
w e refer to the analysis of the fre-
gain-bandwidth product is increased from 18.63 M H z to 651 M H z — a factor of 35!
quency response of the C E amplifier in Section 6.6 to obtain R H2
(í+g
m
R
2
R
R
)( in2
L
II A o û t ! ) + L
( 1 + 4 0 x 4 ) 2500 II 25 +
6.11.2 The Darlington Configuration
4000Y 101
+ 4000
Figure 6.55(a) s h o w s a p o p u l a r B J T circuit k n o w n as t h e D a r l i n g t o n c o n f i g u r a t i o n . It c a n
J.
be t h o u g h t of as a variation of t h e C C - C E circuit with t h e collector of Q c o n n e c t e d to that x
14,143 Q = 14.1 k Q
of Q - Alternatively, t h e D a r l i n g t o n pair c a n b e t h o u g h t of as a c o m p o s i t e transistor with 2
B = PiB 2
W e n o w can determine % from T
H
=
C^R^i
It c a n therefore b e u s e d t o i m p l e m e n t a h i g h - p e r f o r m a n c e voltage follower, as
illustrated in F i g . 6.55(b). N o t e that in this application t h e circuit c a n b e c o n s i d e r e d as t h e +CR nl
+ C^iR^i
Kl
+
cascade c o n n e c t i o n of t w o c o m m o n - c o l l e c t o r transistors (i.e., a C C - C C configuration).
CR n2
n2
= 2 x 3.94 + 13.9 x 0.0634 + 2 x 14.1 + 13.9 x 0.063 = 7.88 + 0.88 + 28.2 + 0.88 = 37.8 ns W e observe that C
Kl
and C
Kl
play a very minor role in determining the high-frequency response.
As expected, C ^ through the Miller effect plays the most significant role. Also, C ^ , which inter2
acts directly with (R
sig
II R ), also plays an important role. T h e 3-dB frequency f in
H
can b e found
as follows: 1 fn = 2TTT, 'H For comparison, w e evaluate A
M
1
= 4.2 M H z
2n x 37.8 x 10 and f
H
of a C E amplifier operating under the same condi-
tions. Refer to Fig. 6.54(c). T h e voltage gain A
is given by
M
Ru R
R:„ + R„
<-gm D
r + RSlg
i - g
R m
ô
K
2.5 (-40 x 4) 2.5 + 4, = -61.5 V/V
FIGURE 6 . 5 5 (a) The Darlington configuration; (b) voltage follower using the Darlington configuration; and (c) the Darlington follower with a bias current / applied to Q to ensure that its ¡5 remains high. x
Ol
645
6 4 6
t
í
;
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
SOME USEFUL TRANSISTOR
6.11
AMPLIFIERS
S i n c e t h e t r a n s i s t o r ¡3 d e p e n d s o n t h e d c bias current, it is p o s s i b l e that Q will be o p e r a t i n g at a very l o w ¡3, r e n d e r i n g t h e /^-multiplication effect of t h e D a r l i n g t o n pair r a t h e r ineffective. A s i m p l e solution t o this p r o b l e m is t o p r o v i d e a bias current for Q as s h o w n in F i g . 6.55(c). x
b
PAIRINGS
configuration h a s excellent high-frequency p e r f o r m a n c e . N o t e that t h e biasing current sources s h o w n in F i g . 6.56(a) e n s u r e that e a c h of Q and Q is operating at a bias current I. "We are n o t s h o w i n g , h o w e v e r , h o w t h e d c v o l t a g e at t h e b a s e of Q is set or t h e circuit that determines t h e d c v o l t a g e at t h e collector of Q . B o t h issues a r e usually l o o k e d after in t h e larger circuit of w h i c h t h e C C - C B amplifier is part. A n interesting version of t h e C C - C B configuration is s h o w n in F i g . 6.56(b). H e r e t h e CB stage is i m p l e m e n t e d with a pnp transistor. A l t h o u g h only o n e current source is n o w needed, o b s e r v e that w e also n e e d to establish an appropriate v o l t a g e at t h e b a s e of Q . This circuit is part of t h e internal circuit of the p o p u l a r 7 4 1 o p a m p , w h i c h will b e studied in Chapter 9. x
2
x
2
2
6.36 For the Darlington voltage follower in Fig. 6.55(b). show that: «iu= ( A + l ) K . . + ( & + l ) ( r
! 2
+ /< -)]
T h e M O S F E T version of t h e circuit in F i g . 6.56(a) is the C D - C G amplifier s h o w n i n
£
Fig. 6.56(c). flout
=
R
E I
A + i
RE + r + [r„ + ^ / ( f t + l)V(B Evaluate R^, R , 100 k£X
and V / V
mi
0
s i g
+ 1)
2
e2
x
= 5 m A , B¡ = B = 100, #
for t h e case I
2
E2
W e n o w briefly a n a l y z e the circuit in F i g . 6.56(a) to d e t e r m i n e its gain A a n d its h i g h frequency r e s p o n s e . T h e analysis applies directly t o t h e circuit in F i g . 6.56(b) and, with a p p r o p r i a t e c h a n g e of c o m p o n e n t a n d p a r a m e t e r n a m e s , t o t h e M O S F E T v e r s i o n in Fig. 6.56(c). F o r simplicity w e shall neglect r and r of both transistors. T h e input resistance R is given b y M
.
£
= 1 k£2, and *
s i g
=
R=
(A + l ) ( r + r
m
Ans. 10.3 M£2; 20 Q : 0.98 V/V
0
m
r
which for ei
=
r
e2
e ]
e and B = B =
=
x
e 2
)
(6.182)
B becomes
r
2
fl
= 2r,
in
(6.183)
If a load resistance R is c o n n e c t e d at the output, the voltage gain V /V,- will b e
6.11.3 The CC-CB and CD-CG Configurations
L
C a s c a d i n g an emitter follower with a c o m m o n - b a s e amplifier, as s h o w n in F i g . 6.56(a), results in a circuit with a low-frequency gain a p p r o x i m a t e l y equal to that of t h e C B b u t with the p r o b l e m of t h e l o w input resistance of t h e C B solved b y t h e buffering action of the C C stage. S i n c e neither t h e C C n o r the C B amplifier suffers from the M i l l e r effect, t h e C C - C B
0
V
=
1
=
Now, if the amplifier is fed with a voltage signal V overall v o l t a g e g a i n will b e V
If
R
Ki
2Vfl
+
0
sig
m
(
i t l
Ci
r
Qi E y i
(gmR )
(6-185)
2
O—¡
nX
PX
1
=
~
and t h e p o l e at t h e output, w i t h a frequency f , P2
P
sig
r
fpi
-V .
-VV;
)
sig
n2
" O ^BIAS
4
fl .
x
Q:
8
T h e high-frequency analysis is illustrated in F i g . 6.57(a). H e r e w e h a v e d r a w n t h e hybrid-7T e q u i v a l e n t circuit for e a c h of Q a n d Q . R e c a l l i n g that t h e t w o transistors a r e operating at e q u a l bias currents, their c o r r e s p o n d i n g m o d e l c o m p o n e n t s will b e equal (i.e., m - rc2' Cm ~ C , etc.). W i t h this in m i n d t h e r e a d e r should b e able t o s e e that V = -Vt2 a n d t h e horizontal line through t h e n o d e labeled E in F i g . 6.57(a) c a n b e deleted. T h u s the circuit r e d u c e s t o that in F i g . 6 . 5 7 ( b ) . T h i s is a v e r y a t t r a c t i v e o u t c o m e b e c a u s e t h e circuit s h o w s clearly t h e t w o p o l e s that d e t e r m i n e t h e high-frequency r e s p o n s e : T h e p o l e at the input, with a frequency f , is
A
oV„
g
1
from a source with a resistance i ? , t h e
L
V, cc
6
i
-Fe
,
-
(6-186)
is
7 T 2nC^R
*
'6-187)
L
(a)
(b)
(c)
FIGURE 6 . 5 6 (a) A CC-CB amplifier, (b) Another version of the CC-CB circuit with Q implemented using a pnp transistor, (c) The MOSFET version of the circuit in (a). 2
This result is also intuitively obvious: T h e input i m p e d a n c e at B j of the circuit in Fig. 6.57(a) consists of t h e series c o n n e c t i o n of r a n d r i n parallel with t h e series c o n n e c t i o n of C and C . T h e n there is i n parallel. A t t h e output, w e simply h a v e R in parallel with C^. nX
n2
M
KX
L
6 4 7
6 4 8
Slvi
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS 6.12
o
1
+
II
+
<
r«
sig
As w e h a v e seen t h r o u g h o u t this chapter, current sources play a m a j o r r o l e in t h e design of
^
w
IMPROVED PERFORMANCE
; - 6.12 CURRENT-MIRROR CIRCUITS I *> WITH IMPROVED PERFORMANCE
"1
W v
CURRENT-MIRROR CIRCUITS WITH
gm Ki
IC amplifiers: T h e c o n s t a n t - c u r r e n t s o u r c e is u s e d b o t h in b i a s i n g a n d as active load. S i m p l e forms of b o t h M O S a n d b i p o l a r current sources and, m o r e generally, current mirrors w e r e
E
-
+
studied i n S e c t i o n 6 . 3 . T h e n e e d to i m p r o v e t h e characteristics o f the s i m p l e sources a n d mirrors h a s already b e e n d e m o n s t r a t e d . Specifically, t w o p e r f o r m a n c e p a r a m e t e r s n e e d t o b e
<
addressed: t h e accuracy
^gmKl
1
of the current
—•
V W
of the current
transfer
ratio of the mirror
a n d t h e output
resistance
source.
T h e reader will recall from Section 6.3 that the accuracy of the current transfer ratio suffers
1
particularly from the finite B of the B J T . T h e output resistance, w h i c h in t h e simple circuits is limited to r of t h e M O S F E T a n d t h e B J T , also reduces accuracy and, m u c h m o r e seriously, 0
—°v-
severely limits t h e gain available from cascode amplifiers. In this section w e study M O S a n d
0
bipolar current rrrirrors with m o r e accurate current transfer ratios and higher output resistances.
(a) sig
o—WV-
6.12.1 Cascode MOS Mirrors
+
A brief i n t r o d u c t i o n t o t h e u s e of t h e c a s c o d i n g p r i n c i p l e i n t h e d e s i g n of current sources
+
g K R $ c
f C==
•Çjl ' 2
ß
m
L
+ M=
was p r e s e n t e d in S e c t i o n 6.8.4. F i g u r e 6.58 s h o w s t h e b a s i c c a s c o d e current mirror. O b s e r v e
=
that in addition t o t h e d i o d e - c o n n e c t e d transistor Q , w h i c h forms t h e basic m i r r o r x
Q -Q , x
2
another d i o d e - c o n n e c t e d transistor, ( 2 , is u s e d t o p r o v i d e a suitable bias v o l t a g e for t h e gate 4
of the c a s c o d e transistor g . T o d e t e r m i n e t h e o u t p u t resistance of t h e c a s c o d e m i r r o r at t h e 3
drain of Q , w e set 7 ^ to zero. A l s o , since Q a n d Q h a v e a relatively s m a l l i n c r e m e n t a l z
(b)
x
resistance, each of approximately 1 /g ,
FIGURE 6 . 5 7 (a) Equivalent circuit for the amplifier in Fig. 6.56(a). (b) Simplified equivalent circuit Note that the equivalent circuits in (a) and (b) also apply to the circuit shown in Fig. 6.56(b). In addition they can be easily adapted for the MOSFET circuit in Fig. 6.56(c), with 2r eliminated, C replaced with C ' C replaced with C , and V replaced with V . •. '" %
K
s
M
gd
n
A
the incremental voltages across t h e m will b e small, a n d
m
w e c a n a s s u m e that the gates of Q a n d Q 3
2
are both grounded. T h u s the output resistance R
0
will b e that of t h e C G transistor Q , w h i c h h a s a r e s i s t a n c e r 3
oX
in its source. E q u a t i o n (6.101)
can b e a d a p t e d t o o b t a i n
gs
R
0
W h e t h e r o n e of t h e t w o p o l e s is d o m i n a n t will d e p e n d o n t h e relative values of R a n d R . If the t w o p o l e s a r e close t o each other, then t h e 3 - d B frequency f can be determined either b y e x a c t a n a l y s i s — t h a t is, finding t h e frequency at w h i c h t h e gain is d o w n b y 3 d B — or b y u s i n g t h e a p p r o x i m a t e formula in E q . (6.36),
+ [ 1 + (g
o3
m3
+ g 3)r i]r 2 mb
0
0
= gm^ r
si
L
= r
oi
ol
T h u s , as e x p e c t e d , c a s c o d i n g raises t h e output resistance of t h e current s o u r c e b y t h e factor g r, m3
o3
w h i c h is t h e intrinsic gain of the c a s c o d e transistor.
(6.188) fp2
Finally, w e n o t e that the circuits in Fig. 6.56(a) a n d (c) a r e special forms of t h e differential amplifier, p e r h a p s t h e m o s t i m p o r t a n t circuit b u i l d i n g b l o c k in a n a l o g I C d e s i g n a n d t h e major topic of study in C h a p t e r 7 .
-oV„
H
" 1
EXERCISE 6.37 For the C C - C B amplifier of Fig. 6.56(a), l e t / = 0.5 mA. B = 100. C = n
1
0
k
Q
(6.190)
H
fPI
=
(6-189)
H
n
d
t
h
e
l o w
f r e c
6 p F , C = 2 p F . fl , = 1 0 k Q . u
si
u e n c
' l y overall voltage gain A , the frequencies of t h e p o l e s , and the .'-JI3 livqnenc\ ; ,. bind /,.. b o t h o \ a c l l \ and using the a p p n . x i n i M t e f.inmila in Cq. i r t . l s s , . M
Ans.5(iV'\:h.-t\ll!/. JsMH/: m
,
: (
b> exact c\ alualion = 4.b \ 1 1 1 / : / . . U M I I » l-.q. ifi. I S S , = S M I \ , .
FIGURE 6 . 5 8 A cascode MOS current mirror.
*>
6 4 9
650
1
I
CHAPTER 6
6.12
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
A d r a w b a c k of t h e c a s c o d e current m i r r o r is that it c o n s u m e s a relatively large portion of t h e steadily shrinking supply v o l t a g e V . W h i l e t h e simple M O S mirror operates properly with a v o l t a g e as l o w as V across its output transistor, t h e c a s c o d e circuit of F i g . g 53 requires a m i n i m u m voltage of V + 2V . T h i s is b e c a u s e t h e gate of Q is at 2V 2V, + 2V . T h u s t h e m i n i m u m v o l t a g e r e q u i r e d across t h e output of t h e c a s c o d e mirror is 1 V or so. This obviously limits t h e signal s w i n g at t h e output of t h e mirror (i.e., at the outp u t of t h e amplifier that utilizes this current source as a load). I n C h a p t e r 9 w e shall study a w i d e - s w i n g c a s c o d e mirror.
CURRENT-MIRROR
CIRCUITS WITH
IMPROVED
PERFORMANCE
the current transfer ratio of t h e mirror will b e
DD
*o
_
1
ov
t
0V
3
4EF
GS
2
l+2/(ß
+ ß)
0V
1
(6.191) 2
l+2/ß
which m e a n s that t h e e r r o r d u e t o finite B h a s b e e n r e d u c e d f r o m 2/B in t h e s i m p l e m i r r o r to 2/B , a t r e m e n d o u s i m p r o v e m e n t . Unfortunately, h o w e v e r , t h e output resistance r e m a i n s approximately e q u a l to that of t h e simple mirror, n a m e l y r . Finally, note that if a reference current is n o t available, w e simply c o n n e c t n o d e x t o t h e p o w e r supply V through a resistance R. T h e result is a reference current given b y 2
0
cc
2
6.38 For a cascode M O S mirror utilizing devices with V, = 0.5 V , _u C = 387 flA/\ , V' ~ 5 V/fim, W/L = 3.6 jUm/0.36 um. and / : = 100 uA, find the minimum dc voltage required at the output and the output resistance. n
ox
A
Vcc - V
BE
R [ ; F
(ß 192)
[- V
BE3
R
Ans. 0.95 V: 285 k Q
6.12.3 The Wilson Current Mirror 6.12.2 A Bipolar Mirror with Base-Current Compensation F i g u r e 6.59 s h o w s a bipolar current m i r r o r with a current transfer ratio that is m u c h less d e p e n d e n t o n fi t h a n that of t h e s i m p l e c u r r e n t m i r r o r . T h e r e d u c e d d e p e n d e n c e o n B is a c h i e v e d b y i n c l u d i n g transistor Q , t h e emitter of w h i c h supplies t h e b a s e currents of Q and Q . T h e s u m of t h e b a s e currents is then divided b y {j5 + 1), resulting in a m u c h smaller error current that h a s to b e supplied b y 7 ^ . D e t a i l e d analysis is s h o w n o n t h e circuit d i a g r a m ; it is b a s e d on t h e a s s u m p t i o n that Q a n d Q a r e m a t c h e d a n d thus h a v e equal collector currents, I . A n o d e equation at t h e n o d e labeled x gives 3
A simple b u t ingenious modification of the basic bipolar mirror results iri both reducing t h e B dependence a n d increasing the output resistance. T h e resulting circuit, k n o w n as the W i l s o n mirror after its inventor, G e o r g e Wilson, an I C design engineer working for Tektronix, is shown in F i g . 6.60(a). T h e analysis to determine the effect of finite B on the current transfer
x
2
3
x
2
c
, If'o-ic
0
(1 + 2/ß)ß ß + i
*1 R„ =
1 +
1 +2/J3 ß +1
-Ci
1+2//3 ß +1
l c
|I/3
iß +
2+ +
7J>
1+
Ic\
2/
¥Í 1
c
2i
02 Ic/ß
]
c/ß
¥
J4
Ô1
Ö2
i\
I
+
v= i|l +
V
-ßjr
e
v = [ß + 2+^)ir x
0
R = vji 0
(b)
(a)
FIGURE 6 . 6 0 The Wilson bipolar current mirror: (a) circuit showing analysis to determine the current transfer ratio; and (b) determining the output resistance. Note that the current i that enters Q must equal the sum of the currents that leave it, 21 x
FIGURE 6 . 5 9 compensation.
A current mirror with base-current
x
3
=
ßr /2 0
+
6 5 2
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6.12
CURRENT-MIRROR CIRCUITS W I T H I M P R O V E D PERFORMANCE
ratio is s h o w n in F i g . 6.60(a), from w h i c h w e can write
/
(
c
i
1
)
©
/ [ l + ( l + |)/(/?+l)~ c
r
id = 8m3(-h o2 I
B+2
=
B+l+Pj^
-°v„
B+ 2
+
B+ 2+ j
(~ Vo2 -
1
'4 I )
^i
A 2
1+
~ V'i'ml)
0
£06 + 2 )
02
2i
Jh
x
r 2' 0
"ßt
\ r
v = (i - i )r
ol
x
x
d
+ • — , 1+2/0*
lx
(6-193)
This analysis a s s u m e s that Q a n d Q c o n d u c t e q u a l collector currents. T h e r e is, h o w e v e r , a x
2
slight p r o b l e m w i t h this a s s u m p t i o n : T h e collector-to-emitter voltages of
is i
V
(b)
(a)
a n d Q are n o t
m
2
equal, w h i c h i n t r o d u c e s a current offset or a s y s t e m a t i c error. T h e p r o b l e m can b e solved b y a d d i n g a d i o d e - c o n n e c t e d transistor in series w i t h t h e collector of Q , as w e shall shortly 2
s h o w for the M O S version. ,
Analysis to determine the output resistance of the W i l s o n mirror is illustrated in Fig. 6.60(b), REF
from w h i c h w e s e e that R„ = fir /2 0
•
(6.194)
Finally, w e note that t h e W i l s o n mirror is preferred over t h e cascode circuit because the latter
"lLß3
h a s t h e s a m e d e p e n d e n c e on B as t h e s i m p l e m i r r o r . H o w e v e r , l i k e t h e c a s c o d e m i r r o r , t h e W i l s o n m i r r o r r e q u i r e s an additional V
BE
drop for its operation; t h a t is, for p r o p e r operation
w e m u s t a l l o w for 1 V or so across the W i l s o n - m i r r o r output.
<0 EXERCISE 6.39 For B = 100 and r„ = 100 k Q . contrast the Wilson mirror and the simple mirror by evaluating the transfer-ratio error due to finite B and the output resistance. Ans. Transfer-ratio error: 0.02% for Wilson as opposed to 2 % for the simple circuit: R = 5 M Q for Wilson compared to 100 k£2 for the simple circuit.
(C)
a
FIGURE 6 . 6 1 The Wilson MOS mirror: (a) circuit; (b) analysis to determine output resistance; and (c) modified circuit. the t w o b r a n c h e s of t h e m i r r o r a n d thus avoid t h e systematic current error resulting from t h e
6.12.4 The Wilson MOS Mirror F i g u r e 6.61(a) s h o w s t h e M O S version of t h e W i l s o n mirror. O b v i o u s l y there is n o B error to
difference in V
DS
b e t w e e n Q and Q , the circuit can b e modified as s h o w n in Fig. 6.61(c). x
2
r e d u c e here, and t h e a d v a n t a g e of t h e M O S W i l s o n lies in its e n h a n c e d output resistance.
6.12.5 The Widlar Current Source
T h e analysis s h o w n in F i g . 6.61(b) p r o v i d e s
Our final current-source circuit, k n o w n as the W i d l a r c u r r e n t s o u r c e , is s h o w n in Fig. 6.62. It differs f r o m t h e b a s i c current m i r r o r circuit in an i m p o r t a n t w a y : A resistor R is included in E
—
r
r
8m3 o3 o2
the emitter lead of Q . N e g l e c t i n g b a s e currents w e c a n w r i t e 2
w h e r e w e h a v e neglected, for simplicity, t h e b o d y effect in Q . W e o b s e r v e that t h e output 3
resistance is approximately the s a m e as that achieved in the c a s c o d e circuit. Finally, to balance
(6.195)
o3
+ v
.
6 5 3
654
:
CHAPTER 6
SINGLE-STAGE INTEGRATED-CIRCUIT
6.12
AMPLIFIERS
CURRENT-MIRROR
CIRCUITS WITH
IMPROVED
PERFORMANCE
©
FIGURE 6 . 6 2 The Widlar current source.
and Thus, V
= Win
RF7
(6.196) 10-0.58
= 1
w h e r e w e h a v e a s s u m e d that Q and Q are m a t c h e d d e v i c e s . C o m b i n i n g E q s . (6.195) and x
=
9
4
2
k
Q
0.01
2
(6.196) gives
For the Widlar circuit in Fig. 6.63(b) we must first decide on a suitable value for I . MF
/ R E F = 1 m A , then V
BE1
V
y
VBE\ - BE2 =
If we select
= 0.7 V and R is given by 2
(6.197)
rln
R
2
=
1
0
~ °'
7
= 9.3 k Q
B u t from the circuit w e see that (6.198)
R
V~BEl ~ VBE2 +
^0 E
The value of R can be determined using Eq. (6.199) as follows: 3
Thus,
6
10xl0" i? IQRE
=
V ln
_REF
(6.199)
T
= 0.025 l n f
3
3
1 1 x 4
^ ßAj
11.5 k Q
=
R
1
10
Ir T h e d e s i g n and a d v a n t a g e s of t h e W i d l a r current s o u r c e are illustrated in the following example. F r o m t h e a b o v e e x a m p l e w e o b s e r v e that u s i n g t h e W i d l a r circuit allows t h e generation of a small constant current using relatively small resistors. This is an important advantage that results in c o n s i d e r a b l e savings in chip area. In fact the circuit of F i g . 6.63(a), r e q u i r i n g a 9 4 2 - k Q resistance, is totally impractical for i m p l e m e n t a t i o n in I C form. A n o t h e r i m p o r t a n t characteristic of the W i d l a r current source is that its output resisFigure 6.63 shows two circuits for generating a constant current I = 10 jiA which operate from
tance, is high. T h e i n c r e a s e in t h e output resistance, a b o v e that a c h i e v e d in t h e basic current
a 10-V supply. Determine the values of the required resistors assuming that V
source, is d u e to the emitter degeneration resistance Rg T o determine the output resistance of
0
BE
is 0.7 V at a
current of 1 m A and neglecting the effect of finite ¡3.
Q , w e a s s u m e that since the b a s e of Q is c o n n e c t e d to g r o u n d v i a t h e small resistance r 2
2
e
of
< 2 the i n c r e m e n t a l v o l t a g e at the b a s e will b e small. T h u s w e c a n u s e t h e formula derived b
Solution
in Section 6.7.2 for t h e C B amplifier, n a m e l y Eq. (6.118), and adapt it for our p u r p o s e s h e r e
For the basic current-source circuit in Fig. 6.63(a) we choose a value f o r ^ j to result in 1^
=
as follows:
10 /J.A. At this current, die voltage drop across Q will be X
R =[\+g (R \\r )\r B
V
BEI •
0.7 + V l n T
10 ßA 1 mA
M
E
n
(6.200)
0
0.58 V T h u s t h e o u t p u t r e s i s t a n c e is increased a b o v e r b y a factor that can b e significant. a
_'!
655
6
5
6
CHAPTER 6 S I N G L E - S T A G E I N T E G R A T E D - C I R C U I T A M P L I F I E R S
6.13
SPICE S I M U L A T I O N E X A M P L E S
EXERCISE resislance feach
6 40
'
d
th
Zd B = Ans.
in
Too *
fthetwocurrentS0Lircesdesigned 111Example
° °
6
M
-
L
c
t
K. =
100 V
54 M i >
\ *
6.13 SPICE SIMULATION EXAMPLES
W e c o n c l u d e this c h a p t e r b y presenting t w o S P I C E simulation e x a m p l e s . In t h e first exam ple, w e will u s e S P I C E to investigate t h e operation of t h e C S amplifier circuit (studied in Section 6.5.2). In t h e second e x a m p l e , w e will u s e S P I C E t o c o m p a r e t h e high-frequency r e s p o n s e of the C S amplifier (studied in Section 6.6) to that of t h e f o l d e d - c a s c o d e amplifier (studied in Section 6.8.6).
THE
CMOS CS
In this example, w e will use PSpice to compute the dc transfer characteristic of the CS amplifier whose Capture schematic is shown in Fig. 6.64. W e will assume a 5-jUm C M O S technology for the MOSFETs and use parts N M O S 5 P 0 and PMOS5P0 whose SPICE level-1 parameters are listed in Table 4.8. To specify the dimensions of the M O S F E T s in PSpice, w e will use the multiplicative factor m together with the channel length L and the channel width W. The M O S F E T parameter m,
M =2 M l = 10 VDD = 10
S
Aspect ratio = ^
Aspect ratio of each MOSFET = -jj
FIGURE 6 . 6 5 Transistor equivalency. whose default value is 1, is used in SPICE to specify the number of MOSFETs connected in paral lel. As depicted in Fig. 6.65, a wide transistor with channel length L and channel width m x W can be implemented using m narrower transistors in parallel, each having a channel length L and a chan nel width W. Thus, neglecting the channel-length modulation effect, the drain current of a M O S F E T operating in the saturation region can be expressed as
AMPLIFIER
PARAMETERS: Iref = lOOu
S
VDD
VDD
= \yiC m^V
D
ox
(6.201)
m
where L rather than L is used to m o r e accurately estimate the drain current (refer to S e c tion 4.12.2). The CS amplifier in Fig. 6.64 is designed for a bias current of 100 jiA assuming a reference cur rent 7 = 100 jiA and V = 10 V. The current-mirror transistors M and M are sized for V = V = 1 V, while the input transistor M is sized for V = 0.5 V. Note that a smaller overdrive voltage is selected for M to achieve a larger voltage gain G for the CS amplifier, since e f f
ref
A
2
I
DD
2
0V3
x
l
M = {M} L f c | . M3 W = 37.5u ^ | ft L = 6u
M2
IE
M = {M} W = 37.5u L = 6u
G
v
0
OUT
= -g R' ml
II r )
= -g dr
L
m
el
o2
IN
1.5Vdc
-T^f W
)
P
v
OV\
V
V
An
+
v
Ap
(6.202)
J
where V and V are the magnitudes of the Early voltages of, respectively, the N M O S and PMOS transistors. Unit-size transistors are used with W/L = 12.5 jim/6 /im for the N M O S devices and W/L = 37.5 Lim/6 jim for the P M O S devices. Thus, using Eq. (6.201) together with the 5-Lim C M O S process parameters in Table 4.8, w e find m = 10 and m = m = 2 (rounded to the nearest integer). Furthermore, Eq. (6.202) gives G = - 1 0 0 V / V . Ap
1
2
3
To compute the dc transfer characteristic of the CS amplifier, w e perform a dc analysis in PSpice with V swept over the range 0 to V and plot the corresponding output voltage VQUTFigure 6.66(a) shows the resulting transfer characteristic. The slope of this characteristic (i.e., dV /a"V ) corresponds to the gain of the amplifier. The high-gain segment is clearly visible for V around 1.5 V. This corresponds to an ovefdriye voltage f o r M ! of V = V - V = 0.5 V, as desired. T o examine the high-gain region more closely, w e repeat the dc sweep for V between 1.3 V and 1.7 V. The resulting transfer characteristic is plotted in Fig. 6.66 (b, middle curve). Using the Probe graphical interface of PSpice, we find that the linear region of this dc transfer characteristic is bounded approximately by V = 1.465 V and = 1.539 V. The corre sponding values of V are 8.838 V and 0.573 V. These results are close to the expected values. Specifically, transistors M and M will remain in the saturation region and, hence, the amplifier will operate in its linear region if V < V < V - V or 0.5 V < V U T ^ 9 V. From the results above, w
A VIN
=
v
VDD
DC = {VDD}
0V2
v
V
An
{Iref}
3
OVL
Ml
M = {Ml} W = 12.5u L = 6u
0
om
DD
m
m
ovl
tn
m
m
0VT
FIGURE 6 . 6 4 Capture schematic of the CS amplifier in Example 6.15.
m
x
2
ovl
o m
DD
0V2
0
1
if -*; 6 5 7
658
|
CHAPTER 6
S I N G L E - S T A G E I NT EG R A T E D - C I R C U I T
AMPLIFIERS
SPICE S I M U L A T I O N
6.13
10V
EXAMPLES
However, because of the high resistance at the output node (or, equivalently, because of the high voltage gain), this value of V is highly sensitive to the effect of process and temperature vari ations on the characteristics of the transistors. T o illustrate this point, consider what happens when the width of M (i.e., W which is normally 12.5 pm) changes by ± 1 5 % . The correspond ing dc transfer characteristics are shown in Fig. 6.66(b). Accordingly, when V = 1.5 V, V will drop to 0.84 V if W increases by 15% and will rise to 9.0 V if W decreases by 15%. In prac tical circuit implementations, this problem is circumvented by using negative feedback to accu rately set the dc bias voltage at the output of the amplifier and, hence, to reduce the sensitivity of the circuit to process variations. The topic of negative feedback will be studied in Chapter 8. 0 U T
x
u
m
x
O U T
x
FREQUENCY RESPONSE OF THE CS AND THE FOLDED-CASCODE
OV • V(OUT)
10V
. ;
•
'
1
2V
^
•
AMPLIFIERS
10V
1
•
i
:
•
1
:
!
!
!
1
~
•
,
.
!
.
,
,
1
,
•
,
,
1
,
,
,
In this example, w e will use PSpice to compute the frequency response of both the CS and the folded-cascode amplifiers whose Capture schematics are shown in Figs. 6.67 and 6.69, respec tively. W e will assume that the dc bias levels at the output of the amplifiers are stabilized using negative feedback. However, before performing a small-signal analysis (an ac-analysis simula tion) in SPICE to measure the frequency response, w e will perform a dc analysis (a bias-point simulation) to verify that all M O S F E T s are operating in the saturation region and, hence, ensure that the amplifier is operating in its linear region.
,
(1.5V, 9.0V) for W = 12.5u - 15% X
8V
V
6V
\
PARAMETERS: Cload = 0.5p CS = 1
'.. O L ( 1 . 5 V . 4.88V) for W = 12.5u X
Iref = • lOOu M = 4 M l = 18
4V
VDD
VDD
A
A
M = {M} W = 5u L = 0.6u
M3
M2
M = {M} W = 5u L = 0.6u
Rsig = 100 2V-
V
VDD = 3.3
V
1
•—i • • • i • • ov — 1.30V 1.35V 1.40V • • v V(OUT)
OUT
{Iref}
(1.5V, 0.836V) s \ forlVj = 12.5u + 15%
: {Cload}
1
1—j
1.45 V
:
\
1.50V
1.55 V
1.60V
1.65V
1.70V {Rsig}
V_VIN VDD
(b) FIGURE 6 . 6 6 (a) Voltage transfer characteristic of the CS amplifier in Example 6.15. (b) Expanded view of the transfer characteristic in the high-gain region. Also shown are the transfer characteristics where process vari ations cause the width of transistor M to change by +15% and - 1 5 % from its nominal value of W = 12.5 pm. t
Ml IN
x
M = {Ml} W = 1.25u L = 0.6u
A - = - DC = {VDD}
lVac 2.45Vdc \ _
Vsig
{Iref}
:{CS}
the voltage gain G (i.e., the slope of the linear segment of the dc transfer characteristic) is approxi mately - 1 1 2 V / V , which is reasonably close to the value obtained by hand analysis. v
Note, from the dc transfer characteristic in Fig. 6.66(b), that for an input dc bias of V = 1.5 V, the output dc bias is V = 4.88 V. This choice of maximizes the available signal swing at the out-put by setting V at the middle of the linear segment of the dc transfer characteristic. m
=" 0
0 U T
0 U T
FIGURE 6 . 6 7 Capture schematic of the CS amplifier in Example 6.16.
~
0
6.13 660
.'V
1
CHAPTER 6 S I N G L E - S T A G E I N T E G R A T E D - C I R C U I T
SPICE S I M U L A T I O N E X A M P L E S
^
661
AMPLIFIERS
In the following, w e will assume a 0.5-zmi C M O S technology for the M O S F E T s and u parts N M 0 S 0 P 5 and P M O S O P 5 whose SPICE level-1 model parameters are listed in Table 4.8 To specify the dimensions of the M O S F E T s in PSpice, w e will use the multiplicative factor m together with the channel length L and channel width W (as we did in Example 6.15).
S e
THE CS
AMPLIFIER
The CS amplifier circuit in Fig. 6.67 is identical to the one shown in Fig. 6.18, except that a current source is connected to the source of the input transistor M , to set its drain current I indepen dently of its drain voltage V . Furthermore, in our PSpice simulations, w e used an impractically large bypass capacitor C of 1 F. This sets the source of M, at approximately signal ground during the ac-analysis simulation. Accordingly, the CS amplifier circuits in Figs. 6.18 and 6.67 are equiva lent for the purpose of frequency-response analysis. In Chapter 7, w e will find out, in the context of studying the differential pair, h o w the goals of this biasing approach for the C S amplifier are realized in practical IC implementations. m
m
s
The CS amplifier in Fig. 6.67 is designed assuming a reference current 7 = 100 /.(A and V = 3.3 V. T h e current-mirror transistors, M and M , are sized for V =V = 0.3 V, while the input transistor M, is sized for V = 0.15 V. Unit-size transistors are used with W/L = 1.25 jum/ 0.6 fim for the N M O S devices and W/L = 5 / i m / 0 . 6 /xm for the P M O S devices. Thus, using Eq. (6.201) together with the 0.5-zmi CMOS process parameters in Table 4.8, we find m = 18 and m = m = 4. Furthermore, Eq. (6.202) gives G„ = - 4 4 . 4 V/V for the C S amplifier. In the PSpice simulations of the CS amplifier in Fig. 6.67, the dc bias voltage of the signal source is set such that the voltage at the source terminal of M is V = 1.3 V. This requires the dc level of V to be V + V + V = 2.45 V because V = 1 V as a result of the body effect on M . T h e reasoning behind this choice of V is that, in a practical circuit implementation, the current source that feeds the source of M is realized using a cascode current mirror such as the one in Fig. 6.58. In this case, the minimum voltage required across the current source (i.e., the min imum V ) is V, + 2V = 1.3 V, assuming V = 0.3 V for the current-mirror transistors. ref
2
3
OV2
DD
ov3
0Vl
l
2
3
x
sig
ovi
m l
si
S1
tnl
x
S1
x
S1
0V
LOG
1.0 10 v A dB (V(OUT))
ov
A bias-point simulation is performed in PSpice to verify that all M O S F E T s are biased in the saturation region. Next, to compute the frequency response of the amplifier, w e set the ac voltage of the signal source to 1 V, perform an ac-analysis simulation, and plot the output voltage magni tude versus frequency. Figure 6.68(a) shows the resulting frequency response for R = 100 O and R = 1 M O . In both cases, a load capacitance of C = 0.5 p F is used. T h e corresponding values of the 3-dB frequency f of the amplifier are given in Table 6.4. , Observe t h a t / drops when R is increased. This is anticipated from our study of the highfrequency response of the CS amplifier in Section 6.6. Specifically, as R increases, the pole
0
1.0K
0
10K
100K
Frequency (Hz) (b)
„f the CS amplifier and (b) the folded-cascode amplifier in FIGURE 6 . 6 8 Frequency response of (a) the Cb ampimei Example 6.16, with fl = 100 Q and R = 1 MCI.
iig
sig
1
I o a d
sig
sig
H
H
Ag
M
sig
fp,
^
T^TTV
m =
(6 203)
'
Folded-Cascode Amplifier
CS Amplifier
formed at the amplifier input will have an increasingly significant effect on the overall frequency response of the amplifier. A s a result, the effective time constant % in Eq. (6.57) increases and f decreases. W h e n R becomes very large, as it is w h e n R = 1 M Q , a dominant pole is formed by R and C . This results in H
sig
sig
sig
m
IH = 1
(6-204)
pM
•
2.93 MHz 1.44 MHz
7.49 MHz 293.2 kHz
ioo a 1 MQ
*~4 where
(6.206)
T o estimate f , w e need to calculate the input capacitance C of the amplifier. Using Miller's theorem, w e have pin
i n
Thus, C can b e calculated using the v a l ^ s of C can b e found in the output file of the bias-pomt stmulauom » v e l y , C Eq. (6.205) with the values of the overlap capacitances C and C , i n
C
m=
C
C
l
R
g s l + gd\(
+gm\ l)
= (|m W L C 1
I
1
< w
+C^ „ ) + C^ ,„ (l+^ 0
1
<
1
I B l
^)
(6.205)
ssl
gS:0vl
g ( i
o y l
^
^
^
^
X ^
6.13
SPICE S I M U L A T I O N E X A M P L E S
process parameters in Table 4.8 (as described in Eqs. 4.170 and 4.171), that is: S
3 O.
3
•— m o ||
||
5
a o • >
||
£ -J
^
C,i
ii
ii ii
s^J
C ,ovi=
o
T
and (6.204), f
o
ITT 3
= 0.53 p F when \G \ = g R' V
THE
FOLDED-CASCODE
AMPLIFIER
a current source is placed in the source of the input transistor M , (for the same dc-biasing purpose as in the case of the CS amplifier). Note that, in Fig. 6.69, the P M O S current mirror M -M 3
- >o o
the N M O S current mirror M -M 5
s £J i
Hi'
>
4
= 2 ) . This results in I
CO
!S ^
s£J
2
is set to 2 (i.e., =I
D3
- I
Dl
=7 . ref
2
7
2
where V
0Vp
= V -V
G 2
DD
- V
SG7
= V -2(\V \
S G 8
DD
+
tp
HI—I"
configuration results in V
SG2
I X
Hi'
w
0Yp
= \V \+ \V tp
is the same. Thus, such a biasing
\ as desired, while setting V
0Vp
SD3
= \V \ + \ V tp
0Vp
\ to
improve the bias matching between M and M . 3
A
T h e folded-cascode amplifier in Fig. 6.69 is designed assuming a reference current 7 100 pA and V
DD
o
\V \)
is the overdrive voltage of the P M O S transistors in the amplifier circuit. These tran
sistors have the same overdrive voltage because their I /m D
S £ -J
D2
8
U
'—^ o
4
. Hence, transistor M is biased at I
The gate bias voltage of transistor M is generated using the diode-connected transistors M and
V
3
r r f
ignoring the body effect,
—«©
—,
= 2/
D3
M . T h e size and drain current of these transistors are set equal to those of transistor M . Therefore,
S ^ ^
>
2
3
3
and
4
are used to realize, respectively, current sources 7j and I in the
6
circuit of Fig. 6.45. Furthermore, the current transfer ratio of mirror M -M m /m
Q Q - *
= 53.2 V / V . Accordingly, using Eqs. (6.203)
L
= 1 M Q , which is close to the value computed by PSpice.
sig
The folded-cascode amplifier circuit in Fig. 6.69 is equivalent to the one in Fig. 6.45, except that
o
^
^
ml
(6.208)
3
c r >o 3 S ^ « ~ « o
-o o U
i n
= 300.3 k H z when R
H
(6.207)
m.W.CGDO
gd
This results in C
3
= m^CGSO
gs ov
ref
=
= 3.3 V (similar to the case of the CS amplifier). All transistors are sized for an
overdrive voltage of 0.3 V, except for the input transistor M which is sized for V h
0Vl
= 0.15 V.
Thus, using Eq. (6.201), all the M O S F E T s in the amplifier circuit are designed using m = 4, except for m = 18. x
The midband voltage gain of the folded-cascode amplifier in Fig. 6.69 can b e expressed using T3
o
a Q • >
£T
S
Hi-
3 3 «
- Q
II'
Eq. (6.130) as
•a "o
G = -g v
R
(6.209)
w l
where
o o cs -a > > I-H IN
§ £ ^
m l
R =
Roua II ^
oat
is the output resistance of the amplifier. Here, R 2
oatS
(6-210)
is the resistance seen looking into the drain of
0M2
the cascode transistor M , while R
5
is the resistance seen looking into the drain of the current-
mirror transistor M . Using Eq. (6.127), w e have 5
3
S o
K H
< ZS
TJ CO
§ U
u
g ^
Q Q >
o OO o «
* Q
Q Q Q - *
>
(6.211)
r
(6.212)
s
where Rs2-r \\
Ul
O
(gm2 o2)R 2
r
• Aout2 -
0l
o3
is the effective resistance at the source of M . Furthermore, 2
;
Aout5
=
r
o5
(6.213)
Thus, for the folded-cascoded amplifier in Fig. 6.69, flout
662
r
= oS
(6.214)
CHAPTER 6
SUMMARY
S I N G L E - S T A G E I N T E G RAT E D - C I R C U I T A M P L I F I E R S
and
SUMMARY G _
An
r\ A
v = ~Sm\'o5
~ ~ Tt
(6.215") '
V
0V1
Using the 0.5-/im C M O S parameters, this gives R = 100 k Q a n d G = - 1 3 3 V / V . Therefore 7 \ and, hence, \G \ of the folded-cascode amplifier in Fig. 6.69 are larger than those of the cs' amplifier in Fig. 6.67 by a factor of 3. mt
out
v
V
Figure 6.68(b) shows the frequency response of the folded-cascode amplifier as computed by PSpice for the cases of R = 100 Q and R = 1 M f l . T h e corresponding values of the 3-dB fre quency f of the amplifier are given in Table 6.4. Observe that, when R is small, f of the folded-cascode amplifier is lower than that of the C S amplifier b y a factor of approximately 2 6 approximately equal to the factor by which the gain is increased. This is because, when R [ small, the frequency response of both amplifiers is dominated by the pole formed at the output node, that is, sig
sig
H
Ag
B
&
G
1
t 1 JH = Jp.oat — o _ N
(6.216)
n
Since the output resistance of the folded-cascode amplifier is larger than that of the CS amplifier (by a factor of approximately 3 , as found through t h e h a n d analysis above) while their output capacitances are approximately equal, the folded-cascode amplifier has a lower f in this case. H
On the other hand, when R is large, f of the folded-cascode amplifier is much higher than that of CS amplifier. This is because, in this case, t h e effect of the pole at f on the overall fre quency response of the amplifier becomes significant. Since, due to the Miller effect, C of the CS amplifier is much larger than that of the folded-cascode amplifier itsf is much lower in this case. T o confirm this point, observe that C of the folded-cascode amplifier can b e estimated b y replac ing R' in Eq. (6.205) with the total resistance R between the drain of M and ground. Here, slg
H
p
where C, is a capacitance that determines the highfrequency response of the amplifier and R is the resistance that capacitance C, "sees". To determine R set V „ and all capacitances to zero. Then apply a signal v between the terminals to which C was connected, determine the current i that the circuit draws from v , and calculate
m integrated-circuit fabrication technology offers the circuit designer many exciting opportunities, the most important of which is large numbers of inexpensive small-area MOS transistors. An overriding concern for IC designers, how ever, is the minimization of chip area or "silicon real estate." As a result, large-valued resistors and capacitors are virtually absent.
t
it
i n
t
x
A review and comparison of the characteristics of the MOSFET and the BJT is presented in Section 6.2. Of par ticular interest is the summary provided in Table 6.3. Biasing in integrated circuits utilizes current sources. Typically an accurate and stable reference current is gen erated and then replicated to provide bias currents for the various amplifier stages on the chip. The heart of the current-steering circuitry utilized to perform this function is the current mirror. The basic MOS and bipolar mirrors are studied in Section 6.3. Improved mirror circuits with more precise current nansfer ratios, reduced dependence on the 6 value of the BJT, and higher output resistances are studied in Section 6.12.
dl
IC amplifiers are usually direct-coupled; thus their midband gain A extends to zero frequency (dc). Their highfrequency response is limited by the transistor internal capacitances, mainly C and C in the MOSFET and C and in the BJT. There usually is also a capacitance C between the output node and ground. These capacitances cause the amplifier gain (or transfer function) to acquire a number of poles on the negative real-axis of the j-plane. In addition, there may be one transmission zero on the negative or positive real-axis, with the remaining trans mission zeros at infinite frequency.
x
gs
r
Rdi = ax II r
o3
where R
in2
II R
(6.217)
ia2
2
approximation of the relationship in Eq. (6.83) as r
R.^ J*±L*
(6.218)
=
r
Sm2 o2
Thus, S R
=r
dl
o l
\\r
r
o i
\\ -f^
== A
8m2'o2
(6.219)
8nl2
2
•
D
K
di
L
H
ia
5
•
ia2
0
du
H
Finally, it is interesting to observe that tire frequency response of the folded-cascode amplifier, shown in Fig. 6.68(h), drops beyond f at approximately - 2 0 dB/decade when R = 100 Q and at approximately - 4 0 dB/dccade when R - 1 MIX This is because, when R is small, the frequency response is dominated by the pole at f . However, when R is increased, f - is moved closer to f and both poles, contribute to the gain falloff. H
sis
sig
pavl
o u t
iie
sig
p
m
The high-frequency response of the CS amplifier is usually limited by the Miller multiplication of C , which results in an input capacitance C of gd
j n
C- = C + w
gs
VZI /
Z 2
/
H
,
L
sig
+ C [R*g( 1 + g R[) gd
m
H
+ R' ] + C R' L
L
L
Exact analysis of the high-frequency response of the CS amplifier yields the second-order transfer function given by Eq. (6.60), which can be used to determine the poles and zeros and hence
m
/ / ( S L / 2 %
where m
f. H
The high-frequency response of the CE amplifier can be found by adapting the CS equations as follows: Replace R, by R; = R II r„, C by C , and C by C . lg
n
m
H
% =C R f'p2
gd
sig
S W/PL
C (\+g R' )
H
Pl
$8 If the poles and Zeros cannot be easily determined, one , can use the open-circuit time constants to obtain an esti mate o f / as follows:
gs
which interacts with the resistance R of the signal source to form a dominant pole; thus f = l/litC^R^. Alternatively, the method of open-circuit time constants c a n b e u s e d t o obtain an estimate of f as s 1 / 2 nt , where
6
m
0
0
Ag
The midband gain of the folded cascode amplifier can b e significantly increased b y replacing the current mirror M -M with a current mirror having a larger output resistance, such as the cascode current mirror in Fig. 6.58 whose output resistance is approximately g r' . In this case, however, R md, hence R increase, causing an increased Miller effect and a corresponding reduction in f .
m
%
If the lowest-frequency pole is at least two octaves away from the nearest pole or zero, this pole, say at frequency f , will play a dominant role in determining the highfrequency response, and the 3-dB frequency f = f . If, on the other hand, none of the poles is dominant, an estimate of fa can be obtained from H
C
The largest voltage gain available from a CS or a CE , amplifier is equal to the intrinsic gain of the transistor A = g r , which for a BJT is 2000 to 4000 V/V and for a MOSFET is 20 to 100 V/V. Recall, however, that the CS amplifier has an infinite input resistance while the input resistance of the CE amplifier is limited by the finite 8 to r . Both CS and CE amplifiers have output resistances equal to the transistor r . 0
P1
Therefore, R is m u c h smaller than R' in Eq. (6.206). H e n c e , C of the folded-cascode amplifier in Fig. 6.69 is indeed much smaller than that of the C S amplifier in Fig. 6.67. This confirms that the folded-cascode amplifier is much less impacted by the Miller effect and, therefore, can achieve a much higher f when R is large.
2
IC amplifiers employ constant-current sources in place of the resistances R (R ) that connect the drain (collector) to the power supply. These active loads enable the realiza tion of reasonably large voltage gains while using lowvoltage supplies (as low as 1 V or so).
L
is the input resistance of the common-gate transistor M and can be obtained using an
^
gd
Miller's theorem states that an impedance Z connected between two circuit nodes 1 and 2, whose voltages are re lated by V = K can be replaced by two impedances: Z = Z/(\-K) between node 1 and ground and Z = Z / ( 1 - ( 1 / K ) ) between node 2 and ground. Miller's the orem is very useful in the analysis of the high-frequency response of the CS and CE amplifiers. l
u
i n
L
M
ft •
x
R< =
in
H
si
x
H
si
p
6 6 5
ig
sig
gs
K
gd
p
When the CS amplifier is fed with a low-resistance signal source, it has the frequency response shown in Fig. 6.26(c).
1
666
ii
CHAPTER 6
The CG and CB amplifiers act as current buffers. Their impedance transformation properties are displayed in Fig. 6.29 (CG) and Fig. 6.35 (CB).
ffi The CG and CB amplifiers do not suffer from the Miller capacitance-multiplication effect and as a result have excellent high-frequency response. In situations when r can be neglected, the CG amplifier has two poles: one produced at the input node with a frequency f = \/2nC {R II (l/(g + g ))) and the other formed at the output node with a frequency f = l/2n(C +C )R . The 3-dB frequency f can be determined using f and f . When r is taken into account, an estimate of f can be obtained from
*
A summary of the characteristics of the MOS cascode for the case of low signal-source resistance is provided in Fig. 6.39
transistor operated at 7 = 0.1 mA. What must I be? What
•3
A summary of the frequency-response analysis of the BJT cascode is provided in Fig. 6.42.
6.9 It is required to find the incremental (i.e., small-signal) resistance of each of the diode-connected transistors shown in Fig. P6.9. Assume that the dc bias current 1 = 0.1 mA. For the MOSFET, let p C = 200 pAN and W/L = 10.
*
pl
s
m
mb
P2
L
gd
H
P2
H
S
H
H
f = l/27t[C (R gs
II R.J + ( C + C )(R
s
£
gd
II
L
R J]
m2
2
o2
•
0
In the cascode amplifier the CG (CB) transistor buffers the drain (collector) of 2, from the load. The result is a smaller signal at the drain (collector) of g , and hence a re duced Miller effect and a wider bandwidth. Alternatively, we can think of the CG (CB) transistor as raising the out put resistance and hence the open-circuit voltage gain by a factor of g r (B for the BIT). Refer to the output equivalent circuits shown in Fig. 6.37(a) and (b) for the MOS cascode and in Fig. 6.41(a) and (b) for the bipolar cascode.
6 6 7
6 . 1 4 An NMOS transistor fabricated in the 0.18-^im process specified in Table 6.1 and having L = 0.3 pm and W = 6 pm is operated at V = 0.2 V and used to drive a capacitive load of 100 fF. Find A , f (or / ) , and / , . At what I value is the transistor operating? If it is required to double / , what must l become? What happens to A and f in this case?
D
value of g is realized? m
Including a small resistance in the source (emitter) of a CS (CE) amplifier provides the designer with a tool to effect some performance improvements (e.g., wider bandwidth), in return for gain reduction (a trade-off characteristic of negative feedback).
M
B
3 d B
D
(
D
0
p
0X
6 . 1 5 For an npn transistor fabricated in the high-voltage process specified in Table 6.2, evaluate f at 7 = 10 pA, 100 pA, and 1 mA. Assume C = C . Repeat for the lowvoltage process. T
CD-
CD-
C
p0
6 . 1 6 Consider an NMOS transistor fabricated in the 0.8-|im process specified in Table 6.1. Let the transistor have L = 1 /an, and assume it is operated at I = 100 pA. D
Combining a source (or emitter) follower with a CS (or CE) amplifier results in amplifiers with gains equal to (or greater than) that of the CS (or CE) amplifier alone and, most importantly, wider bandwidth. The latter is a result of the buffering action of the input follower and the atten dant reduction in the Miller effect that takes place at the input of the CS (or CE) stage.
m
P
p
The source and emitter followers are free of the negative effects of Miller capacitance multiplication and thus achieve very wide bandwidths.
Both the cascode and the Wilson MOS current mirrors achieve an increase in output resistance by a factor of g r . The Wilson bipolar mirror increases the output re sistance by a factor of B/2 and dramatically reduces the current transfer-ratio error due to finite B.
0
2
n
L
Pl
0
C
,
ov
0
gs
PROBLEMS
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
C C , and fj (a) For V = 0.25 V, find W, g„ (b) To what must V be changed to double / ? Find the An, C„„, and C„ new values of W, g„ ov
ov
(a)
r
6 . 1 7 For a lateral pnp transistor fabricated in the highvoltage process specified in Table 6.2, find f if the device is operated at a collector bias current of 1 mA. Compare to the value obtained for a vertical npn.
(b)
T
FIGURE P 6 . 9
6 . 1 0 For an NMOS transistor with /. = 1 pm fabricated in the 0.8-/mi process specified in Table 6.1, find g , r , and A if the device is operated with V = 0.5 V and I = 100 pA. Also, find the required device width W. m
ov
0
0
D
6 . 1 1 For an NMOS transistor with I = 0.3 ,mn fabricated in the 0.18-JUM process specified in Table 6.1, find g , r , and A obtained when the device is operated at I = 100 pA with V = 0.2 V. Also, find W. m
0
0
D
6 . 1 8 Show that for a MOSFET the selection of L and V determines A and f . In other words, show that A and f will not depend on 1 and W.
ov
0
T
0
T
D
6 . 1 9 Consider an NMOS transistor fabricated in the 0.18-pm technology specified in Table 6.1. Let the transistor be oper ated at V = 0.2 V. Find A and f for L = 0.2 pm, 0.3 pm, and 0.4 pm. ov
0
T
ov
6 . 1 2 Fill in the table below. For the BJT, let B = 100 and V = 100 V. For the MOSFET, let p C = 200 pA/Y , W/L = 40, and V = 10 V. Note that R refers to the input resistance at the control input terminal (gate, base) with the (source, emitter) grounded. A
2
P R O B L E M S
n
A
SECTION 6 . 2 : AND THE BJT
COMPARISON OF THE MOSFET
operate at [ F j = 0.25 V and 1 = 100 pA, what must their W/L ratios be? 0 F
D
6 . 1 Find the range of I obtained in a particular NMOS transistor as its overdrive voltage is increased from 0.15 V to 0.4 V. If the same current range is required in 7 of a BJT, what is the corresponding change in V 1
6 . S Consider NMOS and PMOS transistors fabricated in the 0.25-tan process specified in Table 6.1. If the two devices are to be operated at equal drain currents, what must the ratio of (W/L) to (W/L) be to achieve equal values of g 7
6 . 2 What range of I is obtained in an npn transistor as a result of changing the area of the emitter-base junction by a factor of 10 while keeping V constant? If I is to be kept constant, by what amount must V change?
6 . 6 An NMOS transistor fabricated in the 0.18-,um CMOS process specified in Table 6.1 is operated at V = 0.2 V. Find the required W/L and I to obtain a g of 10 mA/V. At what value of 7 must an npn transistor be operated to achieve this value of g 7
D
C
BE
c
BE
c
BE
6.3 For each of the CMOS technologies specified in Table 6.1, find the | V \ and hence the | V \ required to operate a device with a W/L of 10 at a drain current I =W0 pA. Ignore channellength modulation. ov
GS
D
p
n
t
ov
L
D
0
Davice Bias Current
BIT
SECTION 6 . 3 :
MOSFET
3 d B
IC BIASING — CURRENT
SOURCES, CURRENT M I R R O R S , AND /, = 0 . 1 m A
/, = 1 m A
i., = 0.1 m A
CURRENT-STEERING CIRCUITS
/..= 1 mA
m
ov
D
m
D 6 . 2 1 For V = 1.8 V and using 7 = 50 pA. it is required to design the circuit of Fig. 6.4 to obtain an output current whose nominal value is 50 pA. Find R if Q and Q are matched with channel lengths of Q ^ / m i , channel widths of 5 pm, V, = 0.5 V, and k' = 250 pAJV . What is the low est possible value of V 7 Assuming that for this process tech nology the Early voltage V = 20Vlpm, find the output resistance of the current source. Also, find the change in out put current resulting from a +1-V change in V . DD
g™ (mA/V) r '•">! V(V7V) R:(kill
R t F
t
2
2
C
n
m
0
6 . 7 For each of the CMOS process technologies specified in Table 6.1, find the g,„ of an NMOS and a PMOS transistor with W/L = 10 operated at I = 100 pA. D
6 . 1 3 For an NMOS transistor fabricated in the 0.18-Afln process specified in Table 6.1 with L = 0.3 pm and W= 6 pm, find the value of f obtained when the transistor is operated at V = 0.2 V. Use both the formula in terms of C and C and the approximate formula. Why does the approximate for mula overestimate f 1 T
ov
6 . 4 Consider NMOS and PMOS devices fabricated in the 0.25-^m process specified in Table 6.1. If both devices are to
0X
D 6 . 2 0 Consider an NMOS toansistor fabricated in the 0.5-,um process specified in Table 6.1. Let L = 0.5 pm and V = 0.3 V. If the MOSFET is connected as a common-source amplifier with a load capacitance C = 1 pF (as in Fig. 6.2a), find the required transistor width W and bias current I to obtain a unity-gain bandwidth of 100 MHz. Also, find A and / .
6 . 8 An NMOS transistor operated with an overdrive volt age of 0.25 V is required to have a g equal to that of an npn m
gs
T
gd
A
0
D 6 . 2 2 Using V = 1.8 V and a pair of matched MOSFETs, design the current-source circuit of Fig. 6.4 to provide an output DD
!
668
,
:
CHAPTER 6
current of 100-zxA nominal value. To simplify matters, assume that the nominal value of the output current is obtained at V s V . It is further required that the circuit operate for V in the range of 0.25 V to V and that the change in I over this range be limited to 5% of the nominal value of I . Find the required value of R and the device dimensions. For the fabrication-process technology utilized, li C = 250 pAN , V' = 20 W/pm, and V, = 0.6 V. 0
GS
0
DD
the value of R. Find the output resistance of the current source Q and the output resistance of the current sink Q . + 1.5 V A i 2
s
0
G
03
2
2
0X
(a)
Assuming the transistor 8 is very high, find the range of
A
0
M
2
m v
c
6 . 2 3 Sketch the p-channel counterpart of the current-source circuit of Fig. 6.4. Note that while the circuit of Fig. 6.4 should more appropriately be called a current sink, the corresponding PMOS circuit is a current source. Let V = 1.8 V, \V,\ = 0.6 V, fit and Q be matched, and p C = 100 pATV . Find the device (W/L) ratios and the value of the resistor that sets the value of 7 ^ so that a nominally 80-/iA output current is obtained. The current source is required to operate for V as high as 1.6 V. Neglect channel-length modulation. DD
2
2
p
ox
1
04
W
6 . 2 4 Consider the current-mirror circuit of Fig. 6.5 with two transistors having equal channel lengths but with Q having a width four times that of Gi- If I KEF is 20 pA and the transistors are operating at an overdrive voltage of 0.3 V, what 1 results? What is the minimum allowable value of V for proper operation of the current source? If V, = 0.5 V, at what value of V will the nominal value of I be obtained? If V increases by 1 V, what is the corresponding increase i n / ? Let V = 25 V. 2
0
0
0
0
0
0
A
6 . 2 5 For the current-steering circuit of Fig. P6.25, find I in terms of and device (W/L) ratios.
0
* 6 . 2 7 A PMOS current mirror consists of three PMOS transistors, one diode-connected and two used as current outputs. All transistors have |V*,| = 0.7 V, k' = 80 pAN , and L = 1.0 pm but three different widths, namely 10 pm, 20 pm, and 40 pm. When the diode-connected transistor is supplied from a lOO-^A source, how many different output currents are available? Repeat with two of the transistors diodeconnected and the third used to provide current output. For each possible input-diode combination, give the values of the output currents and of the V that results.
0
0
SG
-OV
0
7REF{
t
FIGURE P6.33
f f i F
6 . 3 4 Find the voltages at all nodes and the currents through all branches in the circuit of Fig. P6.34. Assume | V \ = 0.7 V and 8 = •*>•
0
BE
0
+10 V
+5 V
03
r —^ 1 kfî
R
2
=
2 kfl ;
t
+5 V ^02
FIGURE P6.25
kO R
3
- o vn
2
0X
VjO—I
Î
Qi
6 . 2 9 Consider the basic bipolar current mirror of Fig. 6.8 for the case in which Gi and G2 are identical devices having / , = 10" A.
-10 v
m v
5
2
s
FIGURE P 6 . 2 8
15
1
1
GS
r, = 10 k o :
An
••
R!
6 . 3 2 Consider the basic BJT current mirror of Fig. 6.8 when Gi and G2 are matched and / = 2 mA. Neglecting the effect of finite /3, find the change in I , both as an absolute value and as a percentage, corresponding to V changing from 1 V to 10 V. The Early voltage is 90 V.
6 . 2 8 Although thus far we have focussed only on the application of current mirrors in dc biasing, they can also be used as signal-current amplifiers. One such application is illustrated in Fig. P6.28. Here Gi is a common-source amplifier fed with v, = V + v , where V is the gate-to-source dc bias voltage of Gi and v is a small signal to be amplified. Find the signal component of the output voltage v and hence the small-signal voltage gain v /v . 0
p
= 5V
mP
0
n
C C
A
6.31 Give the circuit for the pnp version of the basic current mirror of Fig. 6.8. If 8 of the pnp transistor is 20, what is the current gain (or transfer ratio) I /I , neglecting the Early effect?
t
a
0
2
p
GS
n
mF
0
V
FIGURE P 6 . 2 6
0
D 6 . 2 6 The current-steering circuit of Fig. P6.26 is fabricated in a CMOS technology for which p C = 200 iiA/V , pAJV , V, = 0.6 V, V, = - 0 . 6 V, V' = 10 Y/pm, HpC andlV = 12 V/pm. If all devices have L = 0.8 /an, design Ap the circuit so that I = 20 pA, I, • 100 /J.A, I j. 20 fiA, and I = 50 pA. Use the minimum possible device widths while achieving proper operation of the current source Q for voltages at its drain as high at +1.3 V and proper operation of the current sink Q with voltages at its drain as low as -1.3 V. Specify the widths of all devices and
0
2
-1.5 V
0
A
0.1 mA, 1 mA, and 10 mA. Note that 8
variation with current causes the current transfer ratio to vary with current. 6 . 3 0 Consider the basic BJT current mirror of Fig. 6.8 for the case in which Q has m times the area of Gj • Show that the current transfer ratio is given by Eq. (6.19). If 8 is specified to be a minimum of 80, what is the largest current transfer ratio possible while keeping the error introduced by the finite 8 limited to 5%?
M
s
0
ing to ZREF = 10 pA,
ï h
D 6 . 3 3 The current-source circuit of Fig. P6.33 utilizes a pair of matched pnp transistors having I = 10~ A, 8 = 50, and I V | = 50 V. It is required to design the circuit to provide an output current I = 1 mA at V = 2 V. What values of I and R are needed? What is the maximum allowed value of V while the current source continues to operate properly? What change occurs in I corresponding to V changing from the maximum positive value to - 5 V? 15
y and l corresponding to / increasing from 10 pA to 10 mA. Assume that Q remains in the active mode, and neglect the Early effect. (b) Find the range of I corresponding to l in the range of 10 pA to 10 mA, taking into account the finite ¡5. Assume that Q remains constant at 100 over the current range 0.1 m A to 5 mA but that at I = 10 mA, 8 = 70. Specify I correspond0
0
n
669
PROBLEMS
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
FIGURE P 6 . 3 4
=
1 kfl :
•
CHAPTER 6
670
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
6 . 3 5 For the circuit in Fig. P6.35, let \ V \ = 0.7 V and /} = «>. Find I, V V , V , V , and V for (a) R = 10 k Q and (b)R= 100 k Q . BE
lt
2
3
4
5
PROBLEMS
(a) Assuming that Y is connected to a voltage V, a current I is forced into X, and terminal Z is connected to a voltage that keeps Q in the active region show that a current equal to 7 flows through terminal Y, that a voltage equal to V appears at terminal X, and that a current equal to I flows through termi nal Z. Assume /3 to be large. Corresponding transistors are matched, and all transistors are operating in the active region. 5
(b) With Y connected to ground, show that a virtual ground appears at X. Now, if X is connected to a +5-V supply through a 10-kQ resistor, what current flows through Z? SECTION 6 . 4 : 1
HIGH-FREQUENCY R E S P O N S E -
GENERAL CONSIDERATIONS I
6 . 3 8 A direct-coupled amplifier has a low-frequency gain of 40 dB, poles at 1 MHz and 10 MHz, a zero on the negative real-axis at 100 MHz, and another zero at infinite frequency. Express the amplifier gain function in the form of Eqs. (6.29) and (6.30), and sketch a Bode plot for the gain magnitude. What do you estimate the 3-dB frequency f to be? H
7?:
7?.
R_.
2:
y -10.7 V FIGURE P6.35
D 6 . 3 6 Using the ideas embodied in Fig. 6.11, design a multiple-mirror circuit using power supplies of +5 V to create source currents of 0.2 mA, 0.4 mA, and 0.8 mA and sink currents of 0.5 mA, 1 mA, and 2 mA. Assume that the BJTs have V = 0.7 V and large B.
6
D 6 . 4 3 Refer to Example 6.6. Give an expression for a> in terms of C , R' (note that R' = R II R ), C , R' , and g . If all component values except for the generator resistance R „ are left unchanged, to what value must7? be reduced in order to raise f to 150 kHz? H
gs
m
slg
gd
si
L
m
sig
6 . 3 9 An amplifier with a dc gain of 60 dB has a single-pole high-frequency response with a 3-dB frequency of 10 kHz. (a) Give an expression for the gain functionA(s). (b) Sketch Bode diagrams for the gain magnitude and phase. (c) What is the gain-bandwidth product? (d) What is the unity-gain frequency? (e) If a change in the amplifier circuit causes its transfer function to acquire another pole at 100 kHz, sketch the result ing gain magnitude and specify the unity-gain frequency. Note that this is an example of an amplifier with a unity-gain bandwidth that is different from its gain-bandwidth product.
BE
6 . 4 4 In a particular amplifier design, two internal nodes having Thevenin equivalent resistances of 10 kQ and 20 kQ are expected to have node capacitances (to ground) of 5 pF and 2 pF, respectively, due to component and wiring capaci tances. However, when the circuit is manufactured in a modular form, connections associated with each node add capacitances of 10 pF to each. What are the associated pole frequencies and overall 3-dB frequency in Hz for both the original and the manufactured designs? 6 . 4 5 A FET amplifier resembling that in Example 6.6, when operated at lower currents in a higher-impedance appli cation, has R = 100 k Q , R = 1.2 M Q , g,„ = 2 mA/V, R[ = 12 k Q , and C = C = 1 pF. Find the midband volt age gain A and the 3-dB frequency f . Sig
in
gs
gd
u
H
Y Q
6.40
Consider an amplifier whose F (s) 1 1+ —
X o
is given by
H
1+
(Op
s
s
(a) Derive an expression for the low-frequency voltage gain (set C and C to zero). (b) To be able to determine (0 using the open-circuit timeconstants method, derive expressions for R and R . (c) Let R = 100 k Q , g = 4 mA/V, R' = 5 k Q , and C = C = 1 pF. Use the expressions found in (a) and (b) to gs
(Op.
gd
H
with Cup, < (Op Find the ratio (0 / (O for which the value of the 3-dB frequency (0 calculated using the dominant-pole approximation differs from that calculated using the rootsum-of-squares formula (Eq. 6.36) by: P2
PI
H
z p
gs
sig
gd
(a) 10%. (b) 1%. 6 . 4 1 The high-frequency response of a direct-coupled amplifier having a dc gain o f - 1 0 0 V/V incorporates zeros at oo and 10 rad/s (one at each frequency) and poles at 10 rad/s and 10 rad/s (one at each frequency). Write an expression for the amplifier transfer function. Find (0 using: 6
5
7
H
(a) the dominant-pole approximation. (b) the root-sum-of-squares approximation (Eq. 6.36). -yEE
If a way is found to lower the frequency of the finite zero to 10 rad/s, what does the transfer function become? What is the 3-dB frequency of the resulting amplifier? 5
FIGURE P6.37
H
s
6 . 4 7 A common-source MOS amplifier, whose equivalent circuit resembles that in Fig. 6.14(a), is to be evaluated for its high-frequency response. For this particular design, 7? „ = 1 MQ,R = 5 MQ,R' = 100 k Q , C = 0.2 pF, C = 0.1pF, and g = 0.3 mA/V. Estimate the midband gain and the 3-dB frequency. si
L
gs
gd
m
6 . 4 8 For a particular amplifier modeled by the circuit of Fig. 6.14(a), g = 5 mA/V, R = 150 k Q , R = 0.65 MQ, R' = 10 k Q , C = 2 pF, and C = 0.5 pF. There is also an output wiring capacitance of 3 pF. Find the corresponding midband voltage gain, the open-circuit time constants, and an estimate of the 3-dB frequency. m
L
sig
gs
in
gd
6 . 4 9 Consider the high-frequency response of an amplifier consisting of two identical stages, each with an input resis tance of 10 kQ and an output resistance of 2 kQ. The twostage amplifier is driven from a 5-kQ source and drives a 1-kQ load. Associated with each stage is a parasitic input capacitance (to ground) of 10 pF and a parasitic output capac itance (to ground) of 2 pF. Parasitic capacitances of 5 pF and 7 pF also are associated with the signal-source and load con nections, respectively. For this arrangement, find the three poles and estimate the 3-dB frequency f . H
* 6 . 4 6 Figure P6.46 shows the high-frequency equivalent circuit of a MOSFET amplifier with a resistance R connected in the source lead. The purpose of this problem is to show that the value of R can be used to control the gain and band width of the amplifier, specifically to allow the designer to trade gain for increased bandwidth. s
* 6 . 3 7 The circuit shown in Fig. P6.37 is known as a current conveyor.
671
determine the low-frequency gain and the 3-dB frequency f for three cases: R = 0 Q , 100 Q, and 250 Q. In each case also evaluate the gain-bandwidth product.
ln
H
or3
r
6 . 4 2 A direct-coupled amplifier has a dominant pole at 100 rad/s and three coincident poles at a much higher frequency. These nondominant poles cause the phase lag of the amplifier at high frequencies to exceed the 90° angle due to the dominant pole. It is required to limit the excess phase at a> = 10 rad/s to 30° (i.e., to limit the total phase angle to -120°). Find the corresponding frequency of the nondominant poles.
, !
FIGURE P6.46
m
L
gd
gs
6 . 5 0 Using the method of open-circuit time constants, a set of amplifiers are found to be characterized by the following time constants and/or frequencies. For each case, estimate the 3-dB cutoff frequency in rad/s and in Hz: (a) (b) (c) (d) (e) (f) (g)
20 ns, 5 ns, 1 ns. 50 MHz, 200 MHz, 1 GHz. 50 Mrad/s, 200 Mrad/s, 1 Grad/s. 1 LIS, 200 ns, 200 ns. 1 fis, 0.4 fjs. 1 jus, 200 ns, 150 ns. 1 GHz, 2 GHz, 5 GHz, 5 GHz.
672
t"„ï
CHAPTER 6 S I N G L E - S T A G E I N T E G R A T E D - C I R C U I T A M P L I F I E R S
6 . 5 1 Consider an ideal voltage amplifier with a gain of 0.95 V/V and a resistance R = 100 kfl connected in the feedback path—that is, between the output and input terminals. Use Miller's theorem to find the input resistance of this circuit. 6 . 5 2 An ideal voltage amplifier with a voltage gain of - 1 0 0 0 V/V has a 0.1-pF capacitance connected between its output and input terminals. What is the input capacitance of the amplifier? If the amplifier is fed from a voltage source V having a resistance R = 1 k f i , find the transfer function V /V as a function of the complex-frequency variable s and hence the 3-dB frequency ./^ and the unity-gain frequency/,. sig
PROBLEMS
the output with almost-linear operation. What is the amplitude of the output sinusoid resulting? (Note: In practice, the amplifier would have a feedback circuit that causes it to operate at a point near the middle of its linear region).
SECTION 6 . 5 : THE COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS W I T H ACTIVE LOADS D 6 . 5 5 Find the intrinsic gain of an NMOS transistor fabri cated in a process for which k' = 125 pAN and y ~ 10 V/pm. The transistor has a 1-pm channel length and is operated at V = 0.2 V. If a 2-mA/V transconductance is required, what m u s t / and Wbel 2
n
ov
Ag
6 . 5 6 An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 100 V/V when operated at l of 100 pA. Find the intrinsic gain for I = 25 ,uA and / = 400 pA. For each of these currents, find the ratio by which g changes from its value at I = 100 pA. D
6 . 5 3 The amplifiers listed below are characterized by the descriptor (A, C), where A is the voltage gain from input to output and C is an internal capacitor connected between input and output. For each, find the equivalent capacitances at the input and at the output as provided by the use of Miller's theorem: (a) (b) (c) (d) (e)
0
D
m
A
sig
sig
l
2
+ 1.5 V
c
slg
0
(c) FOT finite r (\V \ = 20 V ) , what is the voltage gain from G to D and the input resistance at G? (d) If G is driven (through a large coupling capacitor) from a source v having a resistance of 100 kil., find the voltage gain v /v . (e) For what range of output signals do Q and Q remain in the saturation region? d
5 60 The power supply of the CMOS amplifier analyzed in Example 6.8 is increased to 5 V. What will the extent of the linear region at the output become?
6 7 3
6.61 Figure P6.61 shows an IC MOS amplifier formed by cascading two common-source stages. Assuming that 02
V „ \V I and the biasing current-sources have output resistances equal to those of Q and Q , find an expression for the overall voltage gain in terms of g and r of Q and Q . A
AP
x
2
m
a
x
2
D
6 . 5 7 The NMOS transistor in the circuit of Fig. P6.57 has V, = 0.5 V, k'„W/L = 2 m A / V , and V = 20 V. 2
A
- 1 0 0 0 V/V, 1 pF. - 1 0 V/V, 10 pF. - 1 V/V, 10 pF. +1 V/V, 10 pF. +10 V/V, 10 pF.
-1.5 V i r a
FIGURE P 6 . 6 3
D 6 . 6 4 Consider the active-loaded CE amplifier circuit of Fig. 6.19(a) for the case I = 1 mA, 3 = 100 and V = 100 V. Find R- , A , and R . If it is required to raise R by a factor of 4 by changing the bias current /, what value of I is required assuming that ¿8 remains unchanged? What are the new values of A, and R l If the amplifier is fed with a signal source having R = 5 kQ. and is connected to a load of 100-kQ resistance, find the overall voltage gain v /v in both cases.
-ov
v,o-
0
A
Note that the input capacitances found in case (e) can be used to cancel the effect of other capacitance connected from input to ground. In (e), what capacitance can be cancelled?
t
v0
0
J0
6 . 5 4 Figure P6.54 shows an ideal voltage amplifier with a gain of +2 V/V (usually implemented with an op amp connected in the noninverting configuration) and a resistance R connected between output and input.
0
FIGURE P 6 . 6 1
* 6 . 6 2 Consider the circuit shown in Fig. 6.18(a), using a3.3-V supply and transistors for which |V,| = 0.8 V and L = 1 pm. For Qi, k' = 100 pAN , V = 100 V, and W = 20 pm. For Q and Q , k = 50 pA/V and | V \ = 50 V. For Q , W=40 pm. For Q , W= 10 pm. 2
(a) Neglecting the dc current in the feedback network and the effect of r , find V and V . Now, find the dc current in the feedback network, and verify that you were justified in neglecting it. (b) Find the small-signal voltage gain, What is the peak of the largest output sine-wave signal that is possible while the NMOS remains in saturation? What is the corresponding input signal? (c) Find the small-signal input resistance R . 0
GS
DS
in
(a) Using Miller's theorem, show that the input resistance
D 6 . 5 8 Consider the CMOS amplifier of Fig. 6.18(a) when fabricated with a process for which k' = 2.5k' = 250 pAN~, \V \ = 0.6 V, and |V | = 10 V. Find 1^ and (W/L\ to obtain a voltage gain of - 4 0 V/V and an output resistance of 100 k£X If Q and Q are to be operated at the same overdrive voltage as Q what must their W/L ratios be? n
t
(b) Use Norton's theorem to replace V , R , and R with a signal current source and an equivalent parallel resistance. Show that by selecting R = R the equivalent parallel resistance becomes infinite and the current I into the load impedance Z becomes V /R. The circuit then functions as an ideal voltage-controlled current source with an output current I . sig
Ag
in
Ag
p
A
2
3
lt
sig
L
(c) If Z is a capacitor C, find the transfer function V /V and show it is that of an ideal noninverting integrator. L
0
sia
n
6 . 5 9 Consider the CMOS amplifier analyzed in Example 6.8. If v consists of a dc bias component on which is superimposed a sinusoidal signal, find the value of the dc component that will result in the maximum possible signal swing at t
A
2
2
3
2
p
A
m
2
2
3
x
7
A
0
2
0
DD
0
DD
23 k O
* * 6 . 6 3 The MOSFETs in the circuit of Fig. P6.63 are matched, having k' (W/L) = k' (W/L) = 1 m A / V and \V,\ = 0.5 V. The resistance R = 1 MQ. 2
y
p
2
(a) For G and D open, what arc the drain currents l and 1 ? (b) For r = oo, what is the voltage gain of the amplifier from G to D? m
s
6 . 6 5 Transistor Gji in the circuit of Fig. P6.65 is operating as a CE amplifier with an active load provided by transistor Q , which is the output transistor in a current mirror formed by Q and Q . (Note that the biasing arrangement for O is not shown.)
3
(a) If 2 i is to be biased at 100 pA, find I . For simplicity, ignore the effect of V . (b) What are the extreme values of v for which g , and Q just remain in saturation? (c) What is the large-signal voltage gain? (d) Find the slope of the transfer characteristic at v = V /2. (e) For operation as a small-signal amplifier around a bias point at v = V /2, find the small-signal voltage gain and output resistance.
n
L
L
a
sig
FIGURE P6.57
FIGURE P6.54
t
D2
a
FIGURE P6.65
o v„
674
CHAPTER 6
S I N G L E - S T A G E I N T EG R A T E D - C I R C U IT A M P L I F I E R S
PROBLEMS
(a) Neglecting the finite base currents of Q and Q and assuming that their V = 0.7 V and that Q has five times the area of Q , find the value of /. (b) If g i and «22 are specified to have \ V \ = 50 V, find r and r and hence the total resistance at the collector of Q (c) Find r and g assuming that B = 50. (d) F i n d i ? , A„, mdR .
0.5 pF, C = 2 p F , g = 20mArY, B = W0, r = 200 Q R[ = 5 k D , and R = 1 k D . Find the midband gain A the frequency of the zero f , and the approximate values of the pole frequencies f and f . Hence, estimate the 3-dB fre quency/#. (Note that this is the same amplifier considered i Problem 6.70; if you have solved Problem 6.70, compare your results.)
SECTION 6 . 6 :
* 6 . 7 2 Refer to Fig. P6.72. Utilizing the BJT high-frequency hybrid-ft model with r = 0 and r = °°, derive an expression for Z,-(s) as a function of r and C . Find the frequency at which the impedance has a phase angle of 45° for the case in which the BJT has f = 400 MHz and the bias current is rel atively high. What does this frequency become if the bias current is reduced so that CK=Cf} (Assume a = 1).
2
BE
3
2
3
A
0l
o2
v
nl
ml
x
in
a
L
m
x
ilg
M
z
Pl
P2
n
* 5 7 5 It is required to analyze the high-frequency response of he CMOS amplifier shown in Fig. P6.75. The dc bias current |s 100 fiA. For (2„ LinC = 90 /.lA/V , V = 12.8 V, WIL = 2
0X
c
0
2
A
F
C
0 1 5
F
m
d
C
2
0
f
R
100 um/1.6 P™' v = P ' ^ = °P> <» = For fi , C = 0.015 pF, C = 36 f F , and \V \ = 19.2 V. Assume that the resistance of the input signal generator is ne°ligibly small. Also, for simplicity assume that the signal voltage at the gate of Q is zero. Find the low-frequency gain, the frequency of the pole, and the frequency of the zero. 2
gd
ib
A
!
6 7 5
(c) For L = 0.5 tan, W = 25 ^ m , f = 12 GHz, and /u C = 200 /AA/V", design the circuit to obtain a gain of 3 V/V per stage. Bias the MOSFETs at V = 0.3 V. Specify the required values of W and I. What is the 3-dB frequency achieved? 2
T
n
ox
ov
x
G o-
D -o
2
HIGH-FREQUENCY RESPONSE
OF THE CS AND CE AMPLIFIERS
x
6 . 6 6 A C S amplifier that can be represented by the equivalent circuit of Fig. 6.20 has C = 2 pF, C = 0.1 pF, C = 1 pF, g = 5 mA/V, and R = R' = 20 k D . Find the midband gain A , the input capacitance C using the Miller equiva lence, and hence an estimate of the 3-dB frequency f . gs
m
gd
sXg
L
L
M
in
0
n
e
T
02
03
(a)
H
6 . 6 7 A CS amplifier that can be represented by the equivalent circuit of Fig. 6.20 has C = 2 pF, C = 0.1 pF, C = 1 pF, g = 5 mA/V, and R = R' = 20 k D . Find the midband A gain, and estimate the 3-dB frequency f using the method of open-circuit time constants. Also, give the percentage contri bution to T by each of three capacitances. (Note that this is the same amplifier considered in Problem 6.66; if you have solved Problem 6.66, compare your results.) gs
m
sig
gd
IBIAS
L
L
M
H
H
6 . 6 8 A CS amplifier represented by the equivalent circuit of Fig. 6.20 has C , = 2 pF, C = 0.1 pF, C = 1 pF, g = 5 m A / V , and R = R[ = 20 k D . Find the exact values of f , f , a n d / > using Eq. (6.60), and hence estimate f . Compare the values o f / a n d / to the approximate values obtained using Eqs. (6.66) and (6.67). (Note that this is the same amplifier considered in Problems 6.66 and 6.67; if you have solved either or both of these problems, compare your results.) g
gd
L
z
2
H
P1
FIGURE P 6 . 7 2
m
sig
n
Zt(s)
P 2
* 6 . 7 3 For the current mirror in Fig. P6.73. derive an expression for the current transfer function I (s)/Ij(s) taking into account the BJT internal capacitances and neglecting r and r . Assume the BJTs to be identical. Observe that a signal ground appears at the collector of Q . If the mirror is biased at 1 mA and the BJTs at this operating point are characterized by f = 400 MHz, C^ = 2 pF, and B = °°, find the frequencies of the pole and zero of the transfer function.
gs
gd
L
0
2
0
m
sis
M
US)
P1
m
gd
gs
2
x
2
0
i-*(
Ys.
L
i + s(C +
for small C„
cy;
L
ß
r
If the transistor is biased at I = 200 LLA and V = 100 V, = 0.2 pF, and C = 1 pF, find the dc gain, the 3-dB frequency, and the frequency at which the gain reduces to unity. Sketch a Bode plot for the gain magnitude. C
A
L
V„
G
n
1+ffl /(G +l)
FIGURE P6.73
H
n
L
GS
M
6 . 7 1 A common-emitter amplifier that can be represented by the equivalent circuit of Fig. 6.25(a) has C = 10 pF, =
x
r
x
sig
6 . 7 7 Consider an active-loaded common-emitter amplifier. Let the amplifier be fed with an ideal voltage source V , and neglect the effect of r . Assume that the bias current source has a very high resistance and that there is a capacitance C present between the output node and ground. This capacitance repre sents the sum of the input capacitance of the subsequent stage and the inevitable parasitic capacitance between collector and ground. Show that the voltage gain is given by t
(a) Show that for the case C < C and the gain of the common-source amplifier is low so that the Miller effect is negligible, the MOSFET can be modeled by the approximate equivalent circuit shown in Fig. P6.76(a), where co is the unity-gain frequency of the MOSFET. (b) Figure P6.76(b) shows an amplifier stage suitable for the realization of low gain and wide bandwidth. Transistors Q and Q have the same channel length L but different widths W and W . They are biased at the same V and have the s a m e / . Use the MOSFET equivalent circuit of Fig. P6.76(a) to model this amplifier stage assuming that its output is con nected to the input of an identical stage. Show that the voltage gain V /Vj is given by
p
L
FIGURE P 6 . 7 6
x
z
6 . 7 0 A common-emitter amplifier that can be represented by the equivalent circuit of Fig. 6.25(a) has C„ = 10 pF, C = 0.5 pF, C = 2 pF, g = 20 mA/V, B = 100, r = 200 D , R[ = 5 k D , and i ? = 1 k D . Find the midband gain A , and an estimate of the 3-dB frequency f using the Miller equivalence.
D * * 6 . 7 6 This problem investigates the use of MOSFETs in the design of wideband amplifiers (Steininger, 1990). Such amplifiers can be realized by cascading low-gain stages.
T
H
P2
(b)
x
T
6 . 6 9 A CS amplifier represented by the equivalent circuit of Fig. 6.20 has C = 2 pF, C = 0.1 pF, C = 1 pF, g = 5 m A / V , and R = R[ = 20 k D . It is required to find A , f , and the gain-bandwidth product for each of the following values of R[: 5 kD, 10 kD, and 20 kD. Use the approximate expression f o r / in Eq. (6.66). However, in each case, also evaluate f a n d / to ensure that a dominant pole exists, and in each case, state whether the unity-gain frequency is equal to the gain-bandwidth product. Present your results in tabular form, and comment on the gain-bandwidth trade-off.
FIGURE P 6 . 7 5
0
r
0
where 6 . 7 4 A CS amplifier modeled with the equivalent circuit of Fig. 6.26(a) is specified to have C = 2 p F , C = 0.1 pF, g = 5 m A / V , C = 1 pF, and R[ = 20 k D . Find A , / and/,. gs
L
gd
m
M
3 d B
6 . 7 8 A common-source amplifier fed with a low-resistance signal source and-operating with g = 1 mA/V has a unitygain frequency of 2 GHz. What additional capacitance must be connected to the drain node to reduce/, to 1 GHz? m
G =
5ml
0
?m2
w
2
CHAPTER 6
676
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS PROBLEMS
SECTION 6 . 7 : THE COMMON-GATE AND
an estimate of f , this time taking into account the finite MOSFET r of 20 kQ. If you have solved Problem 6.86, compare your results. H
COMMON-BASE AMPLIFIERS W I T H
0
ACTIVE LOADS 2 n
1
S
a
0
m
mb
0
0
vp
out
6 . 8 9 Use Eq. (6.112) to explore the variation of the input resistance R with the load resistance R . Specifically, find R as a multiple of r for R /r = 0 , 1 , 10, 100, 1000, and <». Let j3 = 100. Present your results in tabular form.
0
sia
sig
s
0
in
sia
0
0
0
in
sig
L
e
L
0
6 . 9 0 Consider an active-loaded BJT connected in the common-base configuration with 1=1 mA. If the intrinsic gain of the BJT is 2000, what value of R causes the input resistance R to be double the value of r l
0
L
in
2
in
e
A
FIGURE P 6 . 8 4
is
osc
sig
m
6.92 Use Eq. (6.118) to explore the variation of the output resistance of the CB amplifier with the signal-generator resistance R . First, derive an expression for R /r as a function of S and m, where m = R /r . Then use this expression to generate a table for R /r versus R with entiles for R = r , 2r , Wr , (p/2)r , dr , and 1000r,. Let B = 100.
3.3 V
s
ls
e
e
m
0
ont
0Ut
6 . 8 2 What is the approximate input resistance R of a CG amplifier loaded by a resistance R = A r . L
L
L
(a) Show that for r = o° the circuit can be separated into two parts: an input part that produces a pole at
e
e
1
f J P I
2KC (R \\r ) n
e
e
and an output part that forms a pole at
2n(C +C )R p
e
Q
0
L
L
Note that these are the bipolar counterparts of the MOS expressions in Eqs. (6.105) and (6.106). (b) Evaluate f and f and hence obtain an estimate for f for the case C = 14 pF, C = 2 pF, C = 1 pF, I = 1 mA, 7v = 1 k Q , andR = 1 0 k Q . Also, f i n d / of the transistor. pi
6.91 Use Fig. 6.34 to derive the expression in Eq. (6.117a).
6 . 8 1 Derive an expression for the overall short-circuit current gain of a CG amplifier, G = i /i in terms of A , R , and r . Under what condition does G become close to unity? {Hint: Refer to the equivalent circuit in Fig. 6.30). 0
e
L
in
6 . 8 0 Consider an NMOS CG amplifier for which the currentsource load is implemented with a PMOS transistor having an output resistance r equal to that of the NMOS transistor. Design the circuit to obtain v /vi = 100 V/V and R = 2 k Q . Assume | V | = 20 V, £ = 0.2, and £„' = 100 pAN . Specify 7 and M L of the NMOS transistor. 0
and R and feeding a load resistance R in parallel with a capacitance C . 0
6 . 8 8 Use Fig. 6.33(b) together with Eq. (6.110) to derive the expression in Eq. (6.111).
6 . 7 9 Consider a CG amplifier for which k = 160 /IAN , ^ = 0.1 V " , W/L = 50 /jm/0.5 ftm, x = 0.2,1 = 0.5 mA, and R = R = r . Find g , g , r , R , A , R , R , v /v„ and v /v . If die amplifier is instead fed with a current source z' having a source resistance R equal to r , find v /i and i /i , where j is the current through R . L
6 7 7
P2
H
n
sig
p
L
c
L
r
6 . 9 5 Adapt the expressions in Eqs. (6.107), (6.108), and (6.109) for the case of the CB amplifier.
e
e
e
e
e
o
6 . 9 6 For the constant-current source circuit shown in Fig. P6.96, find the collector current / and the output resistance. The BJT is specified to have ¡5 = 100 and V = 100 V. If the collector voltage undergoes a change of 10 V while the BJT remains in the active mode, what is the corresponding change in collector current? A
D 6 . 8 3 The MOSFET current-source shown in Fig. P6.83 is required to deliver a dc current of 1 mA with V = 0.8 V. If the MOSFET has V, = 0.55 V, V = 20 V, and the body transconductance factor £ = 0 . 2 , find the value of R that results in a current-source output-resistance of 200 kQ. Also, determine the required dc voltage V .
6.93 As mentioned in the text, the CB amplifier functions as a current buffer. That is, when fed with a current signal, it passes it to the collector and supplies the output collector current at a high output resistance. Figure P6.93 shows a CB amplifier fed with a signal current ;' „ having a source resistance R = 10 k Q . The BJT is specified to have ¡3 = 100 and V = 50 V. (Note that the bias arrangement is not shown.) The output at the collector is represented by its Norton equivalent circuit. Find the value of the current gain k and the output resistance R .
GS
100 YUA
A
s
S1
sig
B I A S
A
I FIGURE P6.85
out
Transistor Q has £ = 0.2. The signal v signal with no dc component. x
sig
A
is a small sinusoidal
(a) Neglecting the effect of V , find the dc drain current of Q and the required value of V ias(b) Find the values of g and g and of r for all transistors. (c) Find the value of R . (d) Find the value of R .' (e) Calculate the voltage gains v / v and v /v . (f) How large can f be (peak-to-peak) while maintaining saturation-mode operation for Q and Q{! A
B
x
ml
mbl
0
in
mt
0
t
0
FIGURE P 6 . 9 6
sig
sig
FIGURE P 6 . 8 3
6 . 8 4 Figure P6.84 shows the CG amplifier with the output short-circuited. Use this circuit to obtain an expression for i in terms of w „, and verify that this result is the same as that • G v /R obtained using G and R (i.e., using i osc
si
v0
0M
vo
0
sX
0M
6 . 8 6 A CG amplifier is specified to have C = 2 pF, C = 0.1 pF, C = 2 pF, g = 5 mA/V, % = 0.2, R = 1 kQ.'and R' = 20 kQ. Neglecting the effects of r„, find the lowfrequency gain v /v „ the frequencies of the poles f and fp2, and hence an estimate of the 3-dB frequency f . gs
L
m
6 . 8 5 In the common-gate amplifier circuit of Fig. P6.85, Q and Q axe matched, k' {W/L) = k' (W/L) = 4 m A / V , and all transistors have | V , | = 0 . 8 V and V, 2 0 V. 2
3
n
n
p
p
:
6 . 9 7 For the cascode amplifier of Fig. 6.36(a), let Q and Q be identical with V, = 0.6 V, k' = 160 pA/V , X= 0.05 V " , x = 0.2, W/L = 100, and V = 0.2 V. x
gd
2
2
sig
n
1
ov
L
0
si
Pi
H
2
SECTION 6 . 8 : THE CASCODE AMPLIFIER
x
6 . 8 7 For the CG amplifier considered in Problem 6.86, we wish to determine the low-frequency voltage gain vj v and sig
FIGURE P 6 . 9 3
(a) What must the bias current / be? (b) Calculate the values of g , g , g , r , r , A , and A . (c) Find the open-circuit voltage gain A . (d) Calculate the value of the effective short-circuit transconductance, G , of the cascode and the value of R ,. ml
m2
mb2
ol
vo
* 6 . 9 4 Sketch the high-frequency equivalent circuit of a CB amplifier fed from a signal generator characterized by V si
m
o2
0
vo2
CHAPTER 6
6 7 8
(e) If the constant-current source I is implemented with a cascode circuit like that in Fig. 6.43 with an output resistance of 10 MQ, find the voltage gain A . (f) Ignoring the small signal swing at the input and at the drain of Q , find the lowest value that V should have in order to operate Q and Q in saturation. v
x
B I A S
x
2
6 . 9 8 The cascode transistor can be thought of as providing a "shield" for the input transistor from the voltage variations at the output. To quantify this "shielding" property of the cas code, consider the situation in Fig. P6.98. Here we have grounded the input terminal (i.e., reduced v to zero), applied a small change v to the output node, and denoted the voltage change that results at the drain of Q by v . By what factor is v smaller than v 7 t
x
x
y
PROBLEMS
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
y
x
(a) Show that for this circuit V is double that of the original circuit, g is half that of the original circuit, a n d A is double that of the original circuit. ov
m
0
(b) Compare these values to those of the cascode circuit in Fig. 6.99(c), which is operating at the same bias current and has the same minimum voltage requirement at the drain as in the circuit of Fig. P6.99(b). . 1 0 ® (a) Consider a CS amplifier having C = 0.2 pF sig = - RL = 20 k Q , g = 5 mA/V, C , = 2 pF, C (including C, • ) = 1 pF, C = 0.2 pF, and r = 20 k Q . Find the lowfrequency gain A , and estimate f using open-circuit time constants. Hence determine the gain-bandwidth product, (b) If a CG stage is cascaded with the CS transistor in (a) to create a cascode amplifier, determine the new values of A ,f , and gain-bandwidth product. Assume R remains unchanged and x = 0.2. gd
R
n
L
m
db
g
db
L
0
M
H
M
H
L
D 6 . 1 0 1 It is required to design a cascode amplifier to pro vide a dc gain of 66 dB when driven with a low-resistance generator and utilizing NMOS transistors for which V = 10 V, Li C = 200 tiA/V , W/L = 10, C = 0.1 pF, and C = 1 pF. Assuming that R = R , detennine the over drive voltage and the drain current at which the MOSFETs should be operated. Neglect the body effect. Find the unitygain frequency and the 3-dB frequency. If the cascode tran sistor is removed and R remains unchanged, what will the dc gain become? (Hint: The result is different than what can be inferred from Fig. 6.39. Be careful!) 2
A
n
ox
gd
L
L
is fed with a signal source having R = 4 k Q . The load resistance R = 2.4 k Q . Find the low-frequency gainA , and estimate the value of the 3-dB frequency f„. sXg
L
M
* 6 . 9 9 In this problem we investigate whether, as an alterna tive to cascoding, we can simply increase the channel length L of the CS MOSFET. Specifically, we wish to compare the two circuits shown in Fig. P6.99(b) and (c). The circuit in Fig. P6.99(b) is a CS amplifier in which the channel length has been quadrupled relative to that of the original CS amplifier in Fig. P6.99(a) while the drain bias current has been kept constant.
ViO
1
W/L
W/4L
Vi o -
0
(a) Refer to the circuit in Fig. 6.42, and note that the total resistance between the collector of Q and ground will be equal to r , which is usually very small. It follows that the pole introduced at this node will typically be at a very high frequency and thus will have negligible effect onf . It also follows that at the frequencies of interest the gain from the base to the collector of Q will be -g r = - 1 . Use this to find the capacitance at the input of Q and hence show that the pole introduced at the input node will have a frequency x
e2
H
x
(a)
(b)
L
ml
F
=
e2
J
(ii)
R=i
10 k Q .
0 6 . 1 0 5 Design the circuit of Fig. 6.43 to provide an output current of 100 LLA. Use V = 3.3 V, and assume the PMOS transistors to have p C = 60 p.AN , -0.8 V, and t • | V \ = 5 V. The current source is to have the widest possible signal swing at its output. Design for V = 0.2 V, and spec ify the values of the transistor W/L ratios and of V and V . What is the highest allowable voltage at the output? What is the value of R 7 DD
p
ox
P
A
OV
B][AS1
B I A S 2
0
6 . 1 0 6 Find the output resistance of a double-cascoded PMOS current source operating at I = 0.2 m A with each transistor having V = 0.25 V. The PMOS transistors are specified to have j V"^ = 5 V. D
OV
Jpl
-27zR' (C sig
+ 2C^)
Kl
Then show that the pole introduced at the output node will * 6 . 1 0 7 Figure P6.107 shows four possible realizations of the folded-cascode amplifier. Assume that for the BITs B = 200 and | V | = 100 V and for the MOSFETs k'W/L = 2 m A / V ,
have a frequency fp2 =
om
0
in
m
1 2^ (C +C L
i
c s 2
+C„ )
2
2
A
©
21
A
out
0
t
6 . 1 0 3 Consider a bipolar cascode amplifier biased at a cur rent of 1 mA. The transistors used have B = 100, r = 100 kQ., C„ = 14 pF, C„ = 2 pF, C = 0, and r = 50 Q . The amplifier
©<
0
cs
W/L
1
W/L
x
x
x
(b)
©
21
21
Vl
v
0
© FIGURE P 6 . 9 9
cs
6 . 1 0 2 Consider a.bipolar cascode amplifier in which the current-source load is implemented with a circuit having an output resistance of Br . Let B = 100, | V | = 100 V, a n d / = 0.1 mA. Find R , G , R , and v /v . Also, find the gain of the CE stage.
VAS° 1 ViO
P 2
H
neglected.
© ©
PX
of the bipolar cascode amplifier in the case that r can be
(a)
©
(b) Evaluate f a n d / , and use the sum-of-the-squares for mula to estimate f for the amplifier with 1=1 mA, C„ = 5 pF, C^ = 1 pF, C =C = 0, B = 100, and r = 0 in the following two cases:
» 6 . 1 0 4 In this problem we consider the frequency response
L
FIGURE P 6 . 9 8
6 7 9
©'
(c) (c)
(d)
FIGURE P 6 . 1 0 7
©SO
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
CHAPTER 6
| V | = 5 V , and | V , | = 0 . 6 V . Also, let / = 100 fiA and V = +1 V, and assume that the output resistance of currentsource I is equal to the output resistance of its connected circuit. Current-source 21 should be assumed to be ideal. For each circuit, find: A
BlAS
(a) the bias current in Q (b) the voltage at the node between Q and Q (assume )V \=0.7 V). (c) g and r for each device. (d) the maximum allowable value of v . (e) the input resistance. (f) the output resistance. (g) the voltage gain. v
x
2
BE
m
0
0
Does the current-source 21 have to be a sophisticated one? For this generator, what output resistance would reduce the overall gain by 1%?
PROBLEMS
R = 20 kD, C„ = 2 pF, = 0.1 pF, and C = 1 p . the formula for z given in the statement for Problem 6.111 If f = 2 MHz is required, find the value needed for R and the corresponding value of \A \. slg
5
L
p
U
s
e
H
H
s
M
D 6 . 1 1 3 (a) Use the approximate expression in Eq. (6.156) to determine the gain-bandwidth product of a CS amplifier with a source-degeneration resistance. Assume C = 0.1 p and R = 10 k D . (b) If a low-frequency gain of 20 V/V is required, what / corresponds? (c) For g = 5 mA/V, x = 0-2, A = 100 V/V, and R 20 kQ, find the required value of R . gd
p
sig
m
0
L
117 A source follower has g = 5 mA/V, g = 1 mA/V, ' 20 k D , -R = 20 k D , R = 20 k D , C = 2 pF, C ^ = o'l pF, and C = 1 pF. Find A , R ,f , a n d / , . Also, find the percentage contribution of each of the three capacitances to the time-constant %. 6
m
sig
+ 10 V
mb
L
L
6 8 1
gs
M
0
z
6 . 1 1 8 For the source follower, the term C {R \\R ) is usually very small and can be neglected in the determination of %• K ' addition, 7^ > R[, show that L
t h i s
i s
t
n
e
c a s e
a n d
L
0
i n
sig
=
s
6 . 1 1 4 A CE amplifier operating at a collector of 0.5 mA has an emitter-degeneration resistance 0 = 100, V = 100 V, and R = r„, determine R , A , and the overall voltage gain v /v when R A
L
la
v
0
sig
sig
bias current of 100 Q. If R , A , G,„ = 10 kQ. 0
vo
FIGURE P 6 . 1 2 1 r
F
o
r
i v e n
v a l u e s
0 1
C
C
where R' = R II o II S « * s^' and / J , / H can be increased by reducing the term involving C . This in turn can be done by increasing g R' - Note, however, that g R[ cannot exceed \ / % . Why? What is the corresponding maximum for / ? Calculate the value of the maximum f for the source follower specified in Problem 6.117. L
L
s
m
* 6 . 1 1 5 In this problem we investigate the effect of emitter degeneration on the frequency response of a common-emitter amplifier.
6 . 1 ©8 A common-source amplifier with g = 2 mA/V, r = 50 k D , x = °-2, and R = 50 k D has a 500-D resistance connected in the source lead. Find R , A , A , G , and the fraction of p,- that appears between gate and source.
(a) Convince yourself that the MOSFET formulas in Equations (6.148) through (6.152) can be adapted to the BJT case to obtain the following:
PAIRINGS
L
m
SECTION 6 . 9 : THE CS AND CE AMPLIFIERS WITH SOURCE (EMITTER) DEGENERATION
SECTION 6 . 1 1 : SOME USEFUL TRANSISTOR
S I G
H
H
D * 6 . 1 2 2 The transistors in the circuit of Fig. P6.122 have P = 100, V = 100 V, C„ = 0.2 pF, and C = 0.8 pF. At a bias current of 100 pA,f = 400 MHz. (Note that the bias details are not shown.) 0
A
]e
T
m
0
L
oat
v0
v
m
^
0 6 . 1 @® A common-source amplifier has g = 2 mA/V, r = 50 k D , x = 0-2, and R = 50 k D . Find the value of the resistance R that, when connected in the source, reduces the signal v by a factor of 3 (i.e., with R connected v /v = \)What is the corresponding value of voltage gain obtained?
= [(*
+ r ) II RJd
slg
c
slg
L
x
0
p
T
z
+ G R[) + Rl
x
6 . 1 1 9 For an emitter follower biased at I = 5 mA and having R = 10 k D , R = 1 k D , r = 20 k D , 8 = 100, C = 2 pF, r =°200 D , and f = 800 MHz, find the low-frequency gain,/ , R R„, a n d / . p
H
m
m
0
6 . 1 2 0 For an emitter follower biased at = l mA and having R = R = lkQ, and using a transistor specified to have / = 2 G H z , C = 0 . 1 p F , r ^ l O O D , 8 = 100, and V = 20 V, evaluate the low-frequency g a i n A and the 3-dB frequency f .
RL = RL II # o u t
L
sig
s
gs
s
gs
RC
= RLWR
L
= R£
M
V
-
r
r
||
L
r
t
^sig + x +
R
M
A
E
M
H
6 . 1 1 0 A CS amplifier is specified to have g = 5 mA/V, r = 4 0 k D , C „ = 2 p F , C , = 0.1pF, C l p F , R = 20 kD, a n d f l = 40 k Q . ?
i =
m
tH — C v-Rv •
L
H
M
H
mb
C
+
JR I C RC
I
I
L
• .(b) Find A and f of a common-emitter amplifier having C = 10 pF, C = 0.5 pF, C = 2 pF, g = 20 mA/V, 8 = 100, r = 200 Q , r = 100 kQ,, R = 5.3 kQ, and R = 1 kD for the following two cases: M
» 6 . 1 2 1 For the emitter follower shown in Fig. P6.121, find the low-frequency gain and the 3-dB frequency f for the following three cases: H
L
H
n
p
L
x
m
a
L
sig
(i) R = 0. (ii) R = 200 D .
(a) 7x = l k D . (b) R = \0kQ. (c) i ? = 1 0 0 k D . sig
s
sig
s
L
sig
Let 8 = 100. f
e
T
= 400 MHz, and C = 2 pF.
%
= 1 + ( M )
+
C
i+k' 2 + k.
A
For simplicity, assume /f
om
s i? . 0
SECTION 6 . 1 0 : FOLLOWERS
THE SOURCE AND EMITTER
6 . 1 1 6 Consider a source follower for which the NMOS transistor has k' = 160 pAN , X = 0.05 V ~ \ x = 0- > 100, and V = 0.5 V. 2
where k =
R
8mb) s
W
/
L
=
ov
§ * 6 . 1 1 2 It is required to generate a table of \A \, f , and/, versus k = (g + g )R for a CS amplifier with a sourcedegeneration resistance R . The table should have entries for k = 0, 1, 2, . . . , 15. The amplifier is specified to have g = 5 mA/V, g = 1 mA/V, r = 40 k D , R = 40 k D , M
m
mb
s
s
m
2
n
.+
m 4
0
r
H
BE
T
t
2
gs
gd
(a) What must the bias current / b e ? (b) Calculate the values of g , g , and r . (c) F i n d A „ a n d / ? . (d) What does the voltage gain become when a 1-kD load resistor is connected? m
0
(a) Consider die dc bias circuit. Neglect the base current of Q in determining the current in Q find the dc bias currents in Q i and Q , and show that they are approximately 100 uA and 1 mA, respectively. (b) Evaluate the small-signal parameters of O, and Q at their bias points. (c) Consider the circuit at midband frequencies. First, determine the small-signal voltage gain VJV . (Note that # can be 2
h
2
p
{
0
C R
D * * 6 . 1 2 3 Consider the BiCMOS amplifier shown in Fig. P6.123. The BJT has j V \ = 0.7 V, ¿3 = 200, C„ = 0.8 pF, and f = 600 MHz. The NMOS transistor has V = 1 V, k'„ W/L = 2 m A / V , and C = C =l pF.
2
sig
e
6 . 1 1 1 For the CS amplifier with a source-degeneration resistance R , show for R > R and R = r that
H
t
sig
(a) Find the low-frequency gain AM, and use open-circuit time constants to estimate the 3-dB frequency f . Hence determine the gain-bandwidth product. (b) If a 500-12 resistance is connected in the source lead, find the new values of \A \, f , and the gain-bandwidth product. Assume g = 1 mA/V.
in
i + gR
m
o
(a) Find R and the midband gain. (b) Find an estimate of the upper 3-dB frequency f . Which capacitor dominates? Which one is the second most significant? (c) What are the effects of increasing the bias currents by a factor of 10?
mb
0
0
FIGURE P 6 . 1 2 2
G
PROBLEMS CHAPTER 6
633
SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS
+5 V
R
G
3kO C,
= 10 M i l
1 yaF
100 kfl
> ! kfi
i — V W -
0.1 ^ F
6.8 kfl ^
FIGURE P 6 . 1 2 3
neglected in this process.) Then use Miller's theorem onR to determine the amplifier input resistance R . Finally, deter mine the overall voltage gain VJV . (d) Consider the circuit at low frequencies. Determine the frequency of the poles due to C and C , and hence estimate the lower 3-dB frequency,/i. (e) Consider the circuit at higher frequencies. Use Miller's theorem to replace R with a resistance at the input. (The one at the output will be too large to matter.) Use open-circuit time constants to estimate f . (f) To considerably reduce the effect of R on 7? and hence on amplifier performance, consider the effect of adding another 10-MQ resistor in series with the existing one and placing a large bypass capacitor between their joint node and ground. What will R , A , and f become? a
in
sig
x
2
G
H
G
in
M
in
H
100-kQ resistance and is loaded with 1 kQ, find the input resis tance and the output resistance (excluding the load). Also find the overall voltage gain, both open-circuited and with load. 6 . 1 2 5 For the amplifier in Fig. 6.56(a), let I = 1 mA, /3= 120, f = 700 MHz, and = 0.5 pF, and neglect r and r . Assume that a load resistance of 10 kQ is connected to the output ter minal. If the amplifier is fed with a signal V having a source resistance i ? = 20 k Q , find A a n d / . T
x
sig
sig
M
m
ff
6 . 1 2 6 Consider the C D - C G amplifier of Fig. 6.56(c) for the case g = 5 mA/V, C - 2 pF, C = 0.1 pF, C (at the out put node) = 1 pF, and R = R = 20 kQ. Neglecting r and the body effect, find A and/^. m
gs
gi
Ag
L
L
0
M
* * * 6 . 1 2 7 In each of the six circuits in Fig. P6.127, let 8 = 100, C = 2 pF, and f = 400 MHz, and neglect r and r . Cal c u l a t e the midband gain A and the 3-dB frequency f . M
6 . 1 2 4 The BJTs in the Darlington follower of Fig. P6.124 have B = 100- If follower is fed with a source having a
0
T
x
0
M
H
e
0
SECTION 6 . 1 2 :
Vac
CURRENT-MIRROR CIRCUITS
W I T H IMPROVED PERFORMANCE 6 . 1 2 8 For the cascode current mirror of Fig. 6.58 with V,= 0.5 V, k' WIL = 4 mA/V , V = 8 V, I = 80 fiA, and V = +5 V, what value of I results? Specify the output resistance and the minimum allowable voltage at the output. 2
n
A
mF
0
0
6 . 1 2 9 In a particular cascoded current mirror, such as that shown in Fig. 6.58, all transistors have V, = 0.6 V, p C = 200 pAPV , L = 1 pm, and V = 20 V. Width W = W = 2 fim, and W = W = 40 fxm. The reference current I is 25 jiA. What output current results? What are the voltages at the gates of Q and 2 ? What is the lowest voltage at the out put for which current-source operation is possible? What are the values of g and r of Q and g ? What is the output resistance of the mirror?" n
0X
2
A
2
10 mA
3
2
4
mF
3
m
FIGURE P 6 . 1 2 4
X
2
3
(f) FIGURE P 6 . 1 2 7
,
683
CHAPTER 6
6 8 4
SINGLE-STAGE INTEGRATED-CIRCUIT
AMPLIFIERS
PROBLEMS
6 . 1 3 0 Find the output resistance of the double-cascode current mirror of Fig. P6.130.
5
V = 20 V. / R E P = 100. jizA. What value of I results? If the circuit is modified to that in Fig. 6.61(c), what value of I results? 0
0
CD
0 * 5 , 1 4 1 (a) Utilizing a reference current of 100 pA, design a Widlar current source to provide an output current of 10 pA. Let the BJTs have v = 0.7 V at 1-mA current, and assume 6 to be high.
ßA
BE
if p = 200 and V = 100 V, find the value of the output resistance, and find the change in output current corresponding to a 5-V change in output voltage. A
ß<" I i
0—H£
D6.142 Design three Widlar current sources, each having a 100-^iA reference current: one with a current transfer ratio of 0.9, one with a ratio of 0.10, and one with a ratio of 0.01, all assuming high ¡3. For each, find the output resistance, and contrast it with r of the basic unity-ratio source for which R = 0. U s e / 3 = ~ a n d F = 100 V.
0
a
E
A
FIGURE P 6 . 1 4 4
D * 6 . 1 4 5 If the pnp transistor in the circuit of Fig. P6.145 is characterized by its exponential relationship with a scale current I , show that the dc current I is determined by IR = V ln(/// ). Assume Q and Q to be matched and Q , Q , and Q to be matched. Find the value of R that yields a current / = 10 pA. For the BJT, V = 0.7 V at I = 1 mA. s
6.143 The BJT in the circuit of Fig. P6.143 has V B = 100, and V = 100 V. Find R .
BE
FIGURE P 6 . 1 3 4
A
= 0.7 V,
T
s
x
EB
FIGURE P 6 . 1 3 0
6 . 1 3 1 For the base-current-compensated mirror of Fig. 6.59, let the three transistors be matched and specified to have a collector current of 1 mA at V = 0.7 V. For / ^ p of 100 pA and assuming B = 200, what will the voltage at node x be? If 7 is increased to 1 mA, what is the change in V 7 What is the value of I obtained with V = V in both cases? Give the percentage difference between the actual and ideal value of I . What is the lowest voltage at the output for which proper current-source operation is maintained?
D 6 . 1 3 5 Use the pnp version of the Wilson current mirror to design a 0.1-mA current source. The current source is required to operate with the voltage at its output terminal as low as - 5 V. If the power supplies available are ±5 V, what is the highest voltage possible at the output terminal?
BE
R E F
x
0
0
x
0
* 6 . 1 3 6 For the Wilson current mirror of Fig. 6.60, show that the incremental input resistance seen by 7 is approximately 2 V /I : (Neglect the Early effect in this derivation.) Evaluate R for / ^ P = 100 pA.
R
n
X
R E F
T
mF
'lOkfl
in
6 . 1 3 7 Consider the Wilson current-mirror circuit of Fig. 6.60 when supplied with a reference current I of 1 mA. What is the change in I corresponding to a change of+10 V in the voltage at the collector of Q{! Give both the absolute value and the percentage change. Let ¡3 = 100, V = 100 V. and recall that the output resistance of the Wilson circuit is Br„/2.
T
mp
D 6 . 1 3 2 Extend the current-mirror circuit of Fig. 6.59 to, n outputs. What is the resulting current transfer ratio from the input to each output, 7 / / R E F ? If the deviation from unity is to be kept at 0.1% or less, what is the maximum possible number of outputs for BJTs with ¿8 = 100? 0
0
-5 V FIGURE P 6 . 1 4 3
A
D 6 . 1 4 4 (a) For the circuit in Fig. P6.144, assume BJTs with high ß and v = 0.7 V at 1 mA. Find the value of R that will result in I = 10 jiA. BE
* 6 . 1 33 For the base-current-compensated mirror of Fig. 6.59, show that the incremental input resistance (seen by the reference current source) is approximately 2 V /I . Evaluate R for / J E P = 100 pA. T
mF
in
6 . 1 3 8 For the Wilson current mirror of Fig. 6.61(a), all transistors have V, = 0.6 V, p C = 200 pAN , L = 1 pm, and V = 20 V. Width W = 2 pm, and W = W = 40 pm. The reference current is 25 pA. What output current results? What are the voltages at the gates of Q and Q 7 What is the lowest value of V for which current-source operation is possible? What are the values of g and r of Q and Q 7 What is the output resistance of the mirror? 0X
X
2
2
D * 6 . 1 3 4 (a) The circuit in Fig. P6.134 is a modified version of the Wilson current mirror. Here the output transistor is "split" into two matched transistors, Q and Q . Find I and I in terms of /j^p. Assume all transistors to be matched with current gain B. (b) Use this idea to design a circuit that generates currents of 1 mA, 2 mA, and 4 mA using a reference current source of 7 mA. What are the actual values of the currents generated for/3=50? 3
4
01
0
2
n
A
3
3
0
m
0
2
3
02
6 . 1 3 9 Show that the input resistance of the Wilson current mirror of Fig. 6.61(a) is approximately equal to 2/g under the assumption that Q and Q are identical devices. ml
2
3
* 6 . 1 4 0 A Wilson current mirror, such as that in Fig. 6.61(a), uses devices for which V, = 0.6 V, k' W/L = 2 m A / V , and 2
n
(b) For the design in (a), find R assuming ß = 100 and V = 100 V. 0
2
3
5
0
A
FIGURE P 6 . 1 4 5
E
4
Differential and Multistage Amplifiers Introduction
687
7.6
7.1
T h e M O S Differential Pair
7.2
Small-Signal O p e r a t i o n of the M O S Differential Pair
688
696
7.3
T h e B J T Differential Pair
704
7.4
Other Nonideal Characteristics of t h e Differential Amplifier
7.5
720
F r e q u e n c y R e s p o n s e of the Differential Amplifier
7.7
Multistage Amplifiers
7.8
S P I C E Simulation Example
740 749
767
Summary
773
Problems
775
T h e Differential Amplifier w i t h Active Load
727
INTRODUCTION T h e differential-pair or differential-amplifier configuration is t h e m o s t widely u s e d building b l o c k in a n a l o g integrated-circuit design. F o r instance, the input stage of e v e r y o p a m p is a differential amplifier. A l s o , the B J T differential amplifier is the basis of a very-high-speed logic circuit family, studied briefly in C h a p t e r 1 1 , called emitter-coupled logic ( E C L ) . Initially i n v e n t e d for u s e with v a c u u m tubes, the basic differential-amplifier configura tion w a s s u b s e q u e n t l y i m p l e m e n t e d with discrete bipolar transistors. H o w e v e r , it w a s the advent of integrated circuits that h a s m a d e the differential pair e x t r e m e l y p o p u l a r in both bipolar and M O S t e c h n o l o g i e s . T h e r e are t w o r e a s o n s w h y differential amplifiers are so well suited for I C fabrication: First, as w e shall shortly see, the p e r f o r m a n c e of t h e differential pair depends critically o n t h e matching between the t w o sides of the circuit. Integrated-circuit fabrication is c a p a b l e of p r o v i d i n g m a t c h e d devices w h o s e p a r a m e t e r s track o v e r w i d e r a n g e s of c h a n g e s in e n v i r o n m e n t a l c o n d i t i o n s . S e c o n d , b y their v e r y n a t u r e , differential amplifiers utilize m o r e c o m p o n e n t s ( a p p r o a c h i n g t w i c e as m a n y ) than s i n g l e - e n d e d cir cuits. H e r e again, t h e r e a d e r will recall from the d i s c u s s i o n in S e c t i o n 6.1 that a significant 6S7
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
a d v a n t a g e of integrated-circuit t e c h n o l o g y is t h e availability of large n u m b e r s of transistors at relatively l o w cost. W e a s s u m e that t h e r e a d e r is familiar w i t h t h e basic c o n c e p t of a differential amplifier as presented in Section 2 . 1 . N e v e r t h e l e s s it is w o r t h w h i l e to a n s w e r t h e question: W h y differ ential? Basically, there are t w o reasons for u s i n g differential in preference to single-ended amplifiers. First, differential circuits are m u c h less sensitive t o n o i s e and interference than single-ended circuits. T o appreciate this point, consider t w o wires carrying a small differential signal as t h e v o l t a g e difference b e t w e e n t h e t w o w i r e s . N o w , a s s u m e that there is an inter ference signal that is coupled t o t h e t w o wires, either capacitively or inductively. A s t h e t w o wires are physically close together, the interference voltages o n t h e t w o w i r e s (i.e., between each of the t w o wires a n d ground) will b e equal. Since, in a differential system, only t h e dif ference signal b e t w e e n t h e t w o wires is sensed, it will contain n o interference c o m p o n e n t ! T h e second reason for preferring differential amplifiers is that t h e differential configura tion enables u s to bias t h e amplifier a n d t o c o u p l e amplifier stages together w i t h o u t t h e need for b y p a s s a n d coupling capacitors such as t h o s e utilized i n t h e design of discrete-circuit amplifiers (Sections 4.7 and 5.7). This is another reason w h y differential circuits are ideally suited for I C fabrication w h e r e large capacitors are i m p o s s i b l e t o fabricate economically. T h e major topic of this chapter is t h e differential amplifier in both its M O S a n d bipolar implementations. A s will b e seen the design and analysis of differential amplifiers makes extensive u s e of the material on single-stage amplifiers presented in Chapter 6. W e will follow the study of differential amplifiers with examples of multistage amplifiers, again in both M O S and bipolar technologies. T h e chapter concludes with t w o S P I C E circuit simulation examples.
7.1
through a resistance R , in m o s t cases active (current-source) loads are e m p l o y e d , as will b e seen shortly. F o r t h e t i m e b e i n g , h o w e v e r , w e will explain t h e e s s e n c e of t h e differentialpair operation utilizing simple resistive loads. W h a t e v e r type of load is used, it is essential that t h e M O S F E T s not enter t h e triode region of operation. D
7 1 . 1 Operation with a Common-Mode Input Voltage To see h o w t h e differential pair w o r k s , consider first t h e case of t h e t w o gate terminals joined together a n d c o n n e c t e d to a voltage v , called t h e c o m m o n - m o d e v o l t a g e . T h a t is, as s h o w n in Fig. 7.2(a), v = v = v . Since Q a n d Q are m a t c h e d , it follows from s y m metry that t h e current / will divide equally b e t w e e n t h e t w o transistors. T h u s , i = i = 1/2, and t h e v o l t a g e at t h e sources, v , will b e CM
GX
G2
CM
x
DX
v =v -V s
where V
GS
CM
(7.1)
GS
a n d 7/2 are related b y
GS
I
1 ,/ W ,
- = 2
or in t e r m s of t h e overdrive voltage
T /
T /
..2
(7.2)
- k„-(v -v ) 2
GS
t
V, ov
V,ov
y,
Vr.
k
V
(7.3) (7.4)
Vov
2 'T
=
=
ov
x
D2
is t h e gate-to-source v o l t a g e c o r r e s p o n d i n g to a drain current of 1/2. N e g l e c t i n g
channel-length m o d u l a t i o n , V
T H E MOS DIFFERENTIAL PAIR
F i g u r e 7.1 s h o w s t h e basic M O S differential-pair configuration. It consists of t w o m a t c h e d transistors, Q a n d Q , w h o s e sources a r e joined- together a n d b i a s e d b y a constant-current s o u r c e I. T h e latter is u s u a l l y i m p l e m e n t e d b y a M O S F E T circuit of t h e type studied in Sections 6.3 a n d 6.12. F o r the time being, w e a s s u m e that the current source is ideal and that it has infinite output resistance. A l t h o u g h each drain is s h o w n connected to the positive supply
2
s
2 7.1
T H E M O S D I F F E R E N T I A L PAIR
Jl/k (W/L)
(7.5)
~
(7.6)
n
The v o l t a g e at e a c h drain will b e
2
V
Dl
V
- D2 —
T h u s , t h e difference in v o l t a g e b e t w e e n t h e t w o drains will b e zero.
A
À
J
1/2
|//2
V
-°
D2
.02
Ôi
j//2 S
©
=
V
-
R
2°
+
7/2| V
= 1DD
V
GS
CM —
Yes
Vos= V,+
V
ov
V,+ JI
-Vss FIGURE 7.1 The basic MOS differential-pair configuration.
FIGURE 7 . 2 The MOS differential pair with a common-mode input voltage v . CM
.
6 8 9
690
DIFFERENTIAL A N D MULTISTAGE
CHAPTER 7
e l l '
7.1
AMPLIFIERS
N o w , let u s vary t h e value of t h e c o m m o n - m o d e v o l t a g e v . O b v i o u s l y , as long as Q and Q r e m a i n in t h e saturation region, t h e current I will divide equally b e t w e e n Q and Q and t h e voltages at t h e drains will n o t c h a n g e . T h u s t h e differential pair does n o t respond to (i.e., it rejects) c o m m o n - m o d e input signals.
T H E M O S D I F F E R E N T I A L PAIR
CM
2
+ 1.5V
t
+ivo-4 i
CM
CM
x
2
-0.2 V o v
CMmax
-
(7.7)
V t + VDD
2.5 k Û
2.5kfi«
A n i m p o r t a n t specification of a differential amplifier is its i n p u t c o m m o n - m o d e r a n g e . This is t h e r a n g e of v over w h i c h the differential p a h operates properly. T h e highest value of v is limited b y the r e q u i r e m e n t that Q and Q r e m a i n in saturation, thus
i f-^
Y m
m
0.2 Y mA
0.2 I mAY
+lv
Y
I—R—O - 0 . 2 V + :
0.82 V
+
0.82 V
-1.02 V
T h e lowest value of v is determined by the n e e d to allow for a sufficient voltage across current source / for it to operate properly. If a voltage V is needed across t h e current source, then CM
cs
u
CMimii
= -V s S
+V
cs
+
V +V t
0.4 mA
(7.8
0
Y -1.5 V
EXERCISE
""(c) 7.1 For the M O S differential pair with a common-mode voltage v , applied, as shown in Fig. 7.2, let V V = 1.5 V, k' (W/L) = 4 m A / V . V, = 0.5 V. / = 0.4 m A . and R„ = 2.5 kQ, and neglect channel-length modulation. cs
DD
FIGURE 7.3
2
ss
(a) Find V
ov
(b) For w
(Continued)
l:
r j /
and V
us
Ans. (a) 0.316 V , 0.82 V ; (b) see Fig. 7.3(a); (c) see Fig. 7.3(b); (d) sec Fig. 7.3(c) (it is assumed that 0.48 V is sufficient for the current-source to operate properly.); (e) +1.5 V: (1) - 1 . 1 V . - 0 . 2 8 V
for each transistor.
= 0. find v , i , i , v , and v . s
m
n2
m
(c) Repeal (b) for v
c u
= +1 V.
(d) Repeat (b) for v
c u
= - 0 . 2 V. -
(e) What is the highest value of v
CM
Dl
7.1.2 Operation with a Differential Input Voltage for which O and Q remain in saturation? t
2
Next w e apply a difference or differential input v o l t a g e by g r o u n d i n g t h e gate of Q (i.e., setting v = 0) a n d applying a signal v t o t h e gate of Q as s h o w n i n F i g . 7.4. It is easy t o see that since v = v - v , if v is positive, v will b e greater than v and hence i 2
(f) If current source 7 requires a minimum voltage of 0.4 V t o operate properly, what is the lowest value allowed for v and hence for v 1 s
CM
G2
id
id
+ 1.5 V
GS2
id
GSl
GS2
m
+ 3.5 V
2.5 kÛ 0.2 mA
GS1
u
'
0.2 I mAY — o + l V
2.5 kft + 1 V o — I 0.2 T mA
0.2 i mAY
+ 1VO 0.82 V
0.2 f-njA
0.2 m
A
+ '
v
0.82 V
•==•
0.82 V
Q -1.5V
0
4 mA
.
-1.5V
(a)
- (b) The MOS differential pair with a differential input signal v applied. With v positive: v > % > i i > in* and v < v ; thus {v - v ) will be positive. With v negative: v < v , i < i , and % i > v ; thus (v - v ) will be negative.
F I G U R E 7.4
FIGURE 7.3 Circuits for Exercise 7.1. Effects of varying v
CM
on the operation of the differential pair.
S
id
D
m
D2
D2
D2
m
m
m
id
ld
csi
GS2
GSl
Di
w
7.1 2
*i
CHAPTER 7
DIFFERENTIAL AND
MULTISTAGE
THE
MOS
DIFFERENTIAL PAIR
AMPLIFIERS
will b e greater than i and the difference output voltage (v - v ) will b e positive. On the other h a n d , w h e n vid is negative, vGSX will b e l o w e r than vGS2, i will b e smaller than i , and c o r r e s p o n d i n g l y v will b e higher than v ; in other w o r d s , the difference or differential output v o l t a g e (v - v ) will b e negative. D2
m
m
m
m
D2
DI
'D2
m
D2
m
F r o m the a b o v e , w e see that the differential pair r e s p o n d s to d i f f e r e n c e - m o d e o r differ e n t i a l i n p u t s i g n a l s by providing a c o r r e s p o n d i n g differential output signal b e t w e e n the two drains. A t this point, it is useful to inquire about the value of v that causes the entire bias current / to flow in o n e of the t w o transistors. In the positive direction, this h a p p e n s when vGSX reaches the v a l u e that corresponds to i = I, and vGS2 is r e d u c e d to a value equal to the threshold voltage V , at w h i c h point v = -V . T h e value of v can b e found from jd
m
s
t
FIGURE 7.5 The MOSFET differential pair for the purpose of deriving the trans fer characteristics, i and i versus v, =
GS1
t
m
%1
D2
d
- %2-
as
v
GSl
J2I/K(W/L)
= V,+
to
= V + j2V t
(7.9)
0V
where V is the overdrive voltage c o r r e s p o n d i n g to a drain current of 1/2 (Eq. 7.5). Thus, the value of v at w h i c h the entire bias current I is steered into Q is ov
id
y
the differential i n p u t signal
T h e small-signal operation of the differential pair will b e
studied in detail in Section 7.2.
7.1.3 Large-Signal Operation W e shall n o w derive expressions for the drain currents i and i in terms of the input differ ential signal v = v - v . Since these expressions d o not d e p e n d o n the details of the circuit to w h i c h t h e drains are c o n n e c t e d w e do n o t s h o w these c o n n e c t i o n s in Fig. 7 . 5 ; w e simply assume that t h e circuit m a i n t a i n s Q and Q o u t of the triode region of operation at all times. T h e following derivation a s s u m e s that the differential pair is perfectly m a t c h e d a n d neglects channel-length m o d u l a t i o n (A = 0) and t h e b o d y effect. T o b e g i n with, w e express the drain currents of Q a n d Q as DX
"Mmax
=
V
+
GS\
V
S
= V +
id
j2V -V
t
0V
t
G1
x
= J2V
(7.10)
0V
if vld is increased b e y o n d J2V , i remains equal to I, vGSl remains equal to (V + J2V ), and v rises correspondingly, thus keeping Q off. In a similar m a n n e r w e can s h o w that in the negative direction, as v reaches -J2V , Q turns off and Q conducts the entire bias current I. T h u s the current / can b e steered from one transistor to the other by varying v in the range 0V
m
t
s
0V
2
id
0V
r
2
i
m
~j2V
2
x
id
ov
ov
i
D2
which defines the r a n g e of differential-mode operation. Finally, observe that w e h a v e assumed that <2i and Q remain in saturation even w h e n one of t h e m is conducting the entire current I. 2
D2
G2
2
=
h;^(v ,-vf
(7.11)
=
\K^(v -vf
(7.12)
GS
GS2
T a k i n g the square roots of b o t h sides of e a c h of Equations (7.11) a n d (7.12), w e obtain (7.13)
l
-K^(v -v ) GSl
l
Dl
IB.
F o r m e M O S differential pair specified in. Exercise 7:.l find(a) the .value of v, thai causes Q, to conduct the entire current /, and the corresponding values of v and v ; (b) the value of v that causes Q, to conduet the entire current/, and the corresponding values.of w and v,,,: (e) the corresponding range of the differential output voltage (v - v ).
r
D2
^Kr^(v ~V )
J^i =
d
m
t
GS2
(7.14)
t
id
flI
D2
Subtracting E q . (7.14) from E q . (7.13) and substituting
m
(7.15)
Ans. (a) +0.45 V, 0.5 V , 1.5 V ; (b) - 0 . 4 5 V, 1.5 V, 0.5 V; (c) +1 V to - 1 V
%S1
_
V
GS2
=
V
Cl
V
~~ G2
=
V
U
results in T o u s e the differential pair as a linear amplifier, w e k e e p the differential input signal v small. A s a result, the current in one of the transistors (Q w h e n v is positive) will increase b y an i n c r e m e n t A / p r o p o r t i o n a l to v , to {1/2 + AT). Simultaneously, the current in the other transistor will decrease b y the s a m e a m o u n t to b e c o m e (1/2 - A/). A voltage signal -AIR develops at one of the drains and an opposite-polarity signal, AIR , develops at the other drain. T h u s the output voltage taken b e t w e e n the t w o drains will b e 2AIR , w h i c h is proportional
1
id
,,W k
(7.16)
Vid
2 "T
id
x
id
D
D
D
T h e constant-current bias i m p o s e s the constraint (7.17)
6 9 3
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
7.1
E q u a t i o n s (7.16) a n d (7.17) a r e t w o equations in t h e t w o u n k n o w n s i s o l v e d as follows: S q u a r i n g both sides of (7.16) a n d substituting for i
DX
Z
l
-
l
»j Dl D2
1
n
m
and i
D2
+i
and can b e
= I gives
D2
T H E M O S D I F F E R E N T I A L PAIR
I
V i d
~2 ~[
Substituting for i from E q . (7.17) as i = 1- i a n d squaring b o t h sides of t h e resulting e q u a t i o n p r o v i d e s a quadratic e q u a t i o n in i that c a n b e solved to yield D2
D2
DX
D1
2
«
f
l
l
J ±
A
2-V
N
V2)\
'L
I
/
k
, W
N o w since t h e i n c r e m e n t in i a b o v e t h e bias v a l u e of (1/2) m u s t h a v e t h e s a m e polarity as v , only t h e r o o t with t h e " + " sign i n t h e second t e r m is p h y s i c a l l y meaningful; thus m
id
,2
T h e c o r r e s p o n d i n g v a l u e of i
is found f r o m i
D2
D2
= 1- i
DX
as ,2
FIGURE 7 . 6 Normalized plots of the currents in a MOSFET differential pair. Note that V drive voltage at which Q and Q operate when conducting drain currents equal to 7/2.
ov
x
is the over
2
A t t h e bias (quiescent) point, v = 0, l e a d i n g t o id
T h e transfer characteristics of E q s . (7.23) a n d (7.24) a n d F i g . 7.6 are obviously n o n :
di = i 2 = I
(7.20)
D
linear. This is d u e t o t h e t e r m involving v .
Since w e are interested in obtaining linear
id
amplification f r o m t h e differential pair, w e will strive to m a k e this t e r m as small as p o s s i b l e . F o r a g i v e n v a l u e of V ,
Correspondingly,
t h e only thing w e c a n d o is k e e p (v /2)
ov
m u c h smaller than
id
V
ov
w h i c h is t h e c o n d i t i o n for t h e small-signal a p p r o x i m a t i o n . It results in = % 5 2= V
(7.21)
GS
where
i=l^(Ves-Vf
=\ k ^ v l
(7.22)
v
/ 2
D2 = ; 2
This relationship enables us to replace k' (W/L) i and i in the alternative form
in E q s . (7.18) and (7.19) with l/V
n
DX
(
i \V
Y » Hd , o
y
(7.26)
)\l
to express
0V
which, as e x p e c t e d , i n d i c a t e that i
increases b y an i n c r e m e n t i a n d i
D1
d
decreases by the
D2
m
s a m e a m o u n t , i , w h e r e i is p r o p o r t i o n a l t o t h e differential i n p u t signal d
d
v, id
(7.27) V A2J 0V
l
D2 — 1(1 ~ ~
2
\(v \
L
Recalling f r o m o u r study of t h e M O S F E T in C h a p t e r 4 a n d Section 6.2 (refer t o T a b l e 6.3),
fv /2
vwdW-l-fcr' id
ld
< 7
-
2 4 )
that a M O S F E T b i a s e d at a current I
D
the factor (I/V )
in E q . (7.27) as g
N o w , w h y v /21
S i m p l y because v
ov
T h e s e t w o e q u a t i o n s d e s c r i b e t h e effect of a p p l y i n g a differential i n p u t signal v
id
o n the
m
id
currents i
a n d i . T h e y c a n b e u s e d to obtain t h e n o r m a l i z e d plots, i /I
DX
D2
Dl
a n d i /I D2
versus
v /2 id
v
id/V , ov
s h o w n in F i g . 7.6. N o t e that at v = 0, t h e t w o currents a r e e q u a l to 7 / 2 . M a k i n g v id
id
and v
gs2
id
= -v /2, id
has a transeonductance g
m
= 2I /V , D
we recognize
0V
of e a c h of Q a n d Q , w h i c h are b i a s e d at I x
2
D
-
1/2.
divides equally b e t w e e n the t w o devices with t ^
sl
=
w h i c h causes Q to h a v e a current increment i a n d Q t o h a v e a cur x
d
2
rent d e c r e m e n t i . W e shall return to the small-signal operation of t h e M O S differential pair d
positive c a u s e s i constant, i
m
to increase a n d i
m
+ i
D 2
t o d e c r e a s e b y e q u a l a m o u n t s so as t o k e e p the s u m
= I. T h e current is steered e n t i r e l y into Q w h e n v
D2
x
id
r e a c h e s t h e value
shortly. A t this t i m e , h o w e v e r , w e w i s h t o return to E q s . (7.23) and (7.24) and note that linearity c a n b e increased b y increasing t h e overdrive voltage V
ov
j2V y, 0
as w e found o u t earlier. F o r v
changing i
id
m
a n d i . In this case, v D2
id
n e g a t i v e , identical statements can b e m a d e b y inter
= -J2V
0V
steers t h e current entirely into Q . 2
at w h i c h each of Q and Q x
2
is operating. This c a n b e d o n e b y using smaller (W/L) ratios. T h e price paid for the increased linearity is a reduction in g„, and h e n c e a reduction in gain. In this regard, w e o b s e r v e that t h e
c".
6 9 5
7.2 696
£ 3
CHAPTER 7
S M A L L - S I G N A L O P E R A T I O N O F T H E M O S D I F F E R E N T I A L PAIR
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
72.1 Differential Gain Figure 7.8(a) s h o w s the M O S differential amplifier with input voltages V
(7.28)
V
\ id
+
% 1 = CM
and V
G2
Here, V
~ VcM -
(7.29)
V
\ id
d e n o t e s a c o m m o n - m o d e d c voltage w i t h i n the input c o m m o n - m o d e r a n g e of
CM
the differential amplifier. It is n e e d e d in o r d e r to set t h e d c voltage of t h e M O S F E T gates.
FIGURE 7 . 7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of V . ov
-o-
v
0
+o—II
n o r m a l i z e d plot of Fig. 7.6, though compact, m a s k s this design degree-of-freedom. Figure 7.7 s h o w s plots of the transfer characteristics i ^/I
versus v
m
id
for various v a l u e s of
+v
%t =
2
VcM iJ
=
2
V
CM~
V
J
2
(by u s i n g smaller W/L
ov
m
G % 2
ov
T h e linear r a n g e of oper-
ov
ation c a n b e e x t e n d e d b y operating t h e M O S F E T s at a h i g h e r V ratios) at the e x p e n s e of r e d u c i n g g
o2
02
V,
a s s u m i n g that t h e current I is k e p t constant. T h e s e g r a p h s clearly illustrate the l i n e a r i t y t r a n s c o n d u c t a n c e trade-off obtained b y c h a n g i n g t h e v a l u e of V :
ov
and h e n c e t h e gain. T h i s trade-off is b a s e d on the
a s s u m p t i o n that the bias current I is k e p t constant. T h e bias current can, of c o u r s e , be i n c r e a s e d to o b t a i n a h i g h e r g . T h e e x p e n s e for d o i n g this, h o w e v e r , is i n c r e a s e d p o w e r dism
T
sipation, a serious limitation in I C design. -V
ss
EXERCISE 7.3
(a)
2
A MOS differential pair is operated at a bias current / of 0.4 mA. if fj,,C„ = 0.2 mA/V , find these required values of W/L and the resulting g if the MOSFETs are operated at V = 0.2, 0.3, and 0.4 V . « r W « each value, give the maximum jw j for which the term involving iq in Eqs. (7.23) and (7.24), narnelyss "•'',./ o\> '- is limited to 0.1.' r
ln
()V
;
fd
v
d
-o -
7
R
Vol = -gm D(v /2)
>v =
+ o-
O-
id
o2
v„ + o—
+g R (v /2) m
D
id
V
V„ = gnP-D id
„(%/2)| |"Vov(V)
0.2
i W/L I 8
m
!
50 2
(mA/V)
| « M L > V )
126
0.3
0.4 J
22.2 1.33
12.5 1 1 }
190
253
j
Gi
ZQi^
-v /2 ld
"gsl
%/2
2
\gm(vJ )
^ 0 2
Biased at 1/2
JI Vgs2 •
o-vj2
G,o(c)
(b)
FIGURE 7 . 8 Small-signal analysis of the MOS differential amplifier: (a) The circuit with a common-mode voltage applied to set the dc bias voltage at the gates and with v applied in a complementary (or balanced) manner, (b) The circuit prepared for small-signal analysis, (c) An alternative way of looking at the small-signal operation of the circuit. id
In this section w e b u i l d o n t h e u n d e r s t a n d i n g g a i n e d of the b a s i c operation of the differential pair a n d c o n s i d e r in s o m e detail its operation as a linear amplifier.
02.
-Vid/2
0 V
" 7.2 SMALL-SIGNAL OPERATION OF I THE MOS DIFFERENTIAL PAIR
ßI
+
698
1 CHAPTER 7
7.2
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
Typically V is at the m i d d l e value of t h e p o w e r supply. T h u s , for our case, w h e r e two c o m p l e m e n t a r y supplies are utilized, V is typically 0 V. CM
S M A L L - S I G N A L O P E R A T I O N O F T H E M O S D I F F E R E N T I A L PAIR
\,„
699
If the output is t a k e n in a single-ended fashion, the resulting gain b e c o m e s
CM
T h e differential input signal v is applied in a c o m p l e m e n t a r y (or b a l a n c e d ) manner; that is, v is increased b y v /2 and v is d e c r e a s e d b y v /2. T h i s w o u l d b e t h e case, for instance, if t h e differential amplifier w e r e fed from the output of another differential ampli fier stage. S o m e t i m e s , h o w e v e r , the differential input is applied in a single-ended fashion, as w e saw earlier in F i g . 7.4. T h e difference in the p e r f o r m a n c e resulting is too subtle a point for o u r current n e e d s .
l
- -g
R
(
7
-
3
3
7
3
)
id
G1
id
G2
'id
id
or Vol
1
=
g
Rr,
20 m
,u
(
A s indicated in F i g . 7.8(a) the amplifier o u t p u t can b e t a k e n either b e t w e e n o n e of the drains and g r o u n d or b e t w e e n the t w o drains. In the first case, t h e resulting single-ended o u t p u t s v and v will b e riding o n top of t h e dc voltages at the drains ( V - ^ R ) . This is not the c a s e w h e n t h e output is t a k e n b e t w e e n the t w o drains; the resulting differential out p u t v (having a 0 V dc c o m p o n e n t ) will b e entirely a signal c o m p o n e n t . W e will see shortly that there are other significant a d v a n t a g e s to taking the output voltage differentially.
Alternatively, if t h e output is t a k e n differentially, t h e g a i n b e c o m e s
O u r objective n o w is to analyze the small-signal operation of the differential amplifier of F i g . 7.8(a) to d e t e r m i n e its voltage gain in r e s p o n s e to t h e differential input signal v . T o w a r d that e n d w e s h o w in Fig. 7.8(b) t h e circuit with the p o w e r supplies r e m o v e d and V eliminated. F o r the t i m e b e i n g w e will neglect t h e effect of the M O S F E T r , a n d as w e h a v e b e e n d o i n g since t h e b e g i n n i n g of this chapter, c o n t i n u e to neglect the b o d y effect (i.e., c o n t i n u e to a s s u m e that x = 0 ) . Finally n o t e that e a c h of Q and Q is b i a s e d at a dc current of 1/2 a n d is operating at an overdrive voltage V .
ended output is n e e d e d in s o m e applications. W e will h a v e m o r e to say about this later.
ol
o2
DD
0
id
CM
0
1
2
ov
F r o m t h e s y m m e t r y of the circuit as well as b e c a u s e of the b a l a n c e d m a n n e r in w h i c h v is applied, w e o b s e r v e that the signal voltage at the j o i n t source c o n n e c t i o n m u s t b e zero, acting as a sort of virtual ground. T h u s <2i h a s a g a t e - t o - s o u r c e v o l t a g e signal v = v /2 and Q has v = -v /2. A s s u m i n g v /2 < V , the condition for the small-signal approxi mation, the changes resulting in the drain currents of Q and Q will b e proportional to v and v , respectively. T h u s Q will h a v e a drain current i n c r e m e n t g (v /2) and 0 will h a v e a drain current d e c r e m e n t g (v /2), w h e r e g d e n o t e s the e q u a l t r a n s c o n d u c t a n c e s of t h e t w o devices, id
gsl
2
gs2
id
id
2
x
m
id
ov
x
gi2
gsl
m
id
id
A
d
s
=
D
4
)
u
g
(7.35)
R
v
id
Thus, another advantage of taking the output differentially is an increase in gain b y a factor of 2 (6 dB). It should b e noted, h o w e v e r , that although differential outputs are preferred, a singleA n alternative a n d useful w a y of v i e w i n g t h e operation of the differential pair in response to a differential input signal v is illustrated in F i g . 7.8(c). H e r e w e are m a k i n g u s e id
of the fact that t h e resistance b e t w e e n gate a n d s o u r c e of a M O S F E T , l o o k i n g into t h e source, is l/g . m
cuit, of 2/g . m
A s a result, b e t w e e n Gj and G w e h a v e a total resistance, in t h e s o u r c e cir 2
It follows that w e can obtain t h e current i simply by dividing v d
id
b y 2/g , m
as
indicated in t h e figure.
Effect of the MOSFET's r N e x t w e refine o u r analysis b y c o n s i d e r i n g t h e effect of t h e finite output resistance r of e a c h of Q and Q . A s well, w e m a k e t h e realistic a s s u m p t i o n that the bias current source I h a s a finite output resistance R . T h e resulting differential-pair circuit, p r e p a r e d for small-signal analysis, is s h o w n in Fig. 7.9(a). O b s e r v e that the circuit r e m a i n s perfectly s y m m e t r i c , a n d as a result t h e v o l t a g e signal at the c o m m o n source a
a
}
2
s s
2
m
2h 2Jim
gm=
=
V v
o v
= V o v
JL
( .30) 7
V o v
v
v
These results correspond to those obtained earlier using the large-signal transfer characteristics and i m p o s i n g t h e small-signal condition, E q s . (7.25) to (7.27). It is useful at this point to o b s e r v e again that a signal g r o u n d is established at the source terminals of t h e transistors without resorting t o t h e u s e of a l a r g e b y p a s s capacitor, clearly a major a d v a n t a g e of t h e differential-pair configuration. T h e essence of differential-pair operation is that it provides c o m p l e m e n t a r y current signals in t h e drains; w h a t w e d o with the resulting pair of c o m p l e m e n t a r y current signals is, in a sense, a separate issue. H e r e , of course, w e are simply p a s s i n g t h e t w o current signals through a pair of m a t c h e d resistors, R , and thus obtaining the drain voltage signals
VolO-
+ v /2o id
-%/2
1
D
' Biased at 7/2
V;
2
R
D
(7.31) (a)
and
n j R
D
(7-32) source amplifier, known as its differential "half-circuit.
(b)
7.2 7 0 0
1
CHAPTER 7
S M A L L - S I G N A L O P E R A T I O N O F T H E M O S D I F F E R E N T I A L PAIR
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
connection will b e zero. T h u s the signal current t h r o u g h R role in d e t e r m i n i n g t h e differential gain.
ss
will b e zero a n d R
ss
plays no
T h e virtual ground on the c o m m o n source connection enables u s to obtain t h e equivalent circuit shown in Fig. 7.9(b). It consists of two identical c o m m o n - s o u r c e amplifiers, one fed with + v /2 and t h e other fed w i t h - v / 2 . Obviously w e need only o n e of the t w o circuits to perform any analysis w e wish (including finding the frequency response, as w e shall d o shortly). Thus, either of the two common-source circuits is k n o w n as the differential half-circuit. id
i d
o—!
F r o m t h e equivalent circuit in Fig. 7.9(b) w e c a n write ? (R \\r )(v /2) m
D
0
o2
r )(v /2)
D
V + C—«I 0
O v
o2
Ql
Si
(7.36)
id
„(R W
u
-O -
0
-o -
v„, O -
id
o v
62TII— «
Qi
,2~ V i =
gm(RDÏÏr )v
0
-ov„-
v„ + c -
(7.37) o
(7.38)
id
L\ / r
© 2R
<•
SS
Biased at 1/2
SS
v
7.4
ss
A M O S differential pair is operated at a total bias current of 0.8 m A . using transistors with a W/L ratio of 100, n„C = 0.2 t n A / V , V = 20 V, and R = 5 k Q . Find V , g„„ r„, and A . 2
0X
A
D
ov
(b)
(a)
d
Ans. 0.2 V; 4 rnA/V; 50 k Q ; 18.2 V/V
FIGURE 7 . 1 0 (a) The MOS differential amplifier with a common-mode input signal v . (b) Equivalent circuit for determining the common-mode gain (with r ignored). Each half of the circuit is known as the "common-mode half-circuit." icm
0
7.2.2 Common-Mode Gain and Common-Mode Rejection Ratio (CMRR)
(b) T h e output is taken differentially:
W e next consider t h e operation of t h e M O S differential pair w h e n a c o m m o n - m o d e input signal v is applied, as s h o w n in Fig. 7.10(a). H e r e v represents a disturbance o r interfere n c e signal that is c o u p l e d s o m e h o w to b o t h input t e r m i n a l s . A l t h o u g h n o t s h o w n , t h e dc v o l t a g e of t h e input terminals m u s t still b e defined b y a v o l t a g e V as w e h a v e seen before. T h e s y m m e t r y of the circuit enables us t o b r e a k it into t w o identical halves, as s h o w n in Fig. 7.10(b). E a c h of the t w o halves, k n o w n as a C M half-circuit, is a M O S F E T biased at 1/2 and h a v i n g a source degeneration resistance 2R . N e g l e c t i n g t h e effect of r , w e c a n express the v o l t a g e gain of e a c h of the t w o identical half-circuits as icm
Vol-Vol
=
(7.44)
Q
icm
V
n7
- V„
SS
v
ol
ss
m
(7.39)
1
2,R<.£ gm enabling u s t o a p p r o x i m a t e E q . (7.39) as tcm
> l/g
D
It-
u
Usually, R
R
o2
11-
"tern
Vol
=
Vicm
(7.46)
C M R R = 00 Thus, even though R
ss
is finite, taking t h e output differentially results in an infinite C M R R .
H o w e v e r , this is true only w h e n t h e circuit is perfectly m a t c h e d .
__J_
}^O2^_RD_ v
Thus,
0
v
_
j
.
D
(7.40)
D
D
2R
c m
Effect o f R M i s m a t c h o n CMRR W h e n the two drain resistances exhibit a mismatch of AR . as they inevitably do, t h e c o m m o n - m o d e rejection ratio will b e finite even if the output is taken differentially. T o see h o w this comes about, consider the circuit in Fig. 7.10(b) for the case the load of Qi is R and that of Q is (R + AR ). T h e drain signal voltages arising from v will b e 2
D
n
wm
SS
N o w , consider t w o cases: (a) T h e output of t h e differential pair is taken single-endedly R
D
A
cm
(7.45)
R
nD
CM
= ^ 2R
(7.47) (7.41)
_
ss
R + AR _ D
D
(7.48)
2R?s: A\ d
= \g R 2 M
(7.42)
D
Thus, T h u s , t h e c o m m o n - m o d e rejection ratio is g i v e n b y CMRR
(7.49)
A
d
A ^•cm
g Rss m
(7-43)
7 0 1
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
In other w o r d s , the m i s m a t c h in R
AMPLIFIERS
c a u s e s the c o m m o n - m o d e i n p u t signal v-
D
S M A L L - S I G N A L OPERATION OF THE M O S
7.2
lcm
DIFFERENTIAL
to be con-
verted into a differential output signal; clearly an u n d e s i r a b l e situation! E q u a t i o n (7.49) indicates that t h e c o m m o n - m o d e gain will b e A
AR,
= -
2R
cm
(7.50)
- o — v0 + o -
ss
w h i c h c a n b e e x p r e s s e d in the alternative f o r m Rp
(AR
2R \
R
D
SS
S i n c e t h e m i s m a t c h in R
D
d
\ hi
hi I
(7.51)
= -8mR
u
gsl
V
gsl
(7.52)
D
and c o m b i n e Eqs. (7.51) and (7.52) to obtain the C M R R resulting from a mismatch (AR /R ) D
CMRR
hi y
D
will h a v e a negligible effect o n t h e differential gain, w e can write A
I hi
= ( 2 g
m
R
s
s
D
) / \ ^
as FIGURE 7 . 1 1 Analysis of the MOS differential amplifier to determine the common-mode gain resulting from a mismatch in the g values of <2i and Q .
(7.53)
m
2
Since Qi and Q are in effect operating as source followers w i t h a s o u r c e resistance R is typically m u c h larger than l/g , 2
ss
that
m
A VIOS differential pair operated at a bias current of 0.8 mA employs transistors with W/L = 100 and jU„C, * = 0.2 iriA/V , using R = 5 kQ, and R = 25 k Q .
(7.58)
2
;
n
ss
enabling u s to w r i t e E q . (7.57) as
(a) Find the differential gain, the common-mode gain, and the c o m m o n - m o d e rejection ratio (in dB) if the output is taken singlc-cndedly and the circuit is perfectly matched.
dl + d2
l
(b) Repeal (a) when ihe output is taken differentially.
l
(7.59)
:
R,
(c) Repeat (a) when the output is taken differentially but the drain resistances have a 1% mismatch. W e can n o w c o m b i n e E q s . (7.56) and (7.59) to obtain
Ans. (a) 10 V/V. 0.1 V/V. 4 0 d B : (b) 20 V/V. 0 V/V. » d B : fcl 20 V7V. 0.001 V/V. 86 dB
(7.60) Effect o f g
Mismatch on CMRR
m
(8mi
N e x t w e i n q u i r e into t h e effect of a m i s m a t c h between
t h e v a l u e s of t h e t r a n s c o n d u c t a n c e g
m
+
of t h e t w o M O S P E T s o n the C M R R of the differential
8 )Rss m2
8 ml ^icm
pair. S i n c e t h e circuit is n o l o n g e r m a t c h e d , w e c a n n o t e m p l o y the c o m m o n - m o d e half-
(8ml
+
(7.61)
8m2)RsS
circuit. Rather, w e refer to the circuit s h o w n in F i g . 7 . 1 1 , and w r i t e If g
ml
'¿1=^1^1 id2 = gmlVgsl
(7-54) '
and g
e x h i b i t a s m a l l m i s m a t c h Ag
m2
8ml F g 2 m
2g , m
(7-55)
(i.e., g
m
- g
ml
- Ag ),
m2
m
w e c a n a s s u m e that
=
where g
is t h e n o m i n a l v a l u e of g
m
and g ;
ml
thus
m2
(7.62) 1
Since v
gsl
- v
gs2
2
R
8m S
w e c a n c o m b i n e E q s . (7.54) a n d (7.55) to obtain and l
d\
_ 8ml
d2
8m2
l
(7.56) (7.63)
=
IM
2
T h e t w o drain currents s u m together in R
ss
8 Rss
to p r o v i d e
m
The differential o u t p u t v o l t a g e c a n n o w b e found as
v
s = (hi + hlWsS
V
V
R
o2 ~ o\ = -hl D
Thus idi + iai = ^ss K
(7-57)
K
l
+
l
D\ d\- d2)
R
hl D
~
~ 8m SS
2
R
V
^~ ic
T H E BJT D I F F E R E N T I A L PAIR
7.3 704
»wv'
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
from w h i c h the c o m m o n - m o d e gain can b e obtained as
2R A
g
SS
Since t h e g
m
al
al
al Y i
(7.64)
Y Rc
R
'Rc
R
c<
c
m i s m a t c h will h a v e a negligible effect on A , d
A-d =
(7.65)
R
~gm D
cc
cc
~2 c
c
IR
V
R
>V -J c
R
Vc "
- <* c '
and t h e C M R R resulting will be CMRR =
+1 Vo A,
(7.66)
&g Rss) m
+
D
i 2
Off
+0.3 V
0.7
V
CM '
'©
©
For the MOS amplifier specified in Exercise 7.5 with the output taken differentially compute CMRR that results from a 1 % mismatch in g .
oj
2 i
EXERCISE 7.6
r-\ rr
/ "v _
On {/
t>CM
The similarity of this expression to that resulting from the R mismatch (Eq. 7.53) should be noted.
1
Q ^ >
m
Ans.
-V,
dH
(b)
(a)
? J 7.3
THE BJT DIFFERENTIAL PAIR
1 Of
F i g u r e 7.12 s h o w s the basic B J T differential-pair configuration. It is very similar to the M O S F E T circuit and consists of t w o m a t c h e d transistors, <2i and Q , w h o s e emitters are j o i n e d t o g e t h e r and biased b y a constant-current s o u r c e /. T h e latter is usually i m p l e m e n t e d b y a transistor circuit of the type studied in Sections 6.3 and 6.12. A l t h o u g h each collector is s h o w n c o n n e c t e d to the positive supply v o l t a g e V through a resistance R , this connection is not essential to the operation of the differential p a i r — t h a t is, in s o m e applications the two collectors m a y b e c o n n e c t e d to other transistors rather t h a n to resistive loads. It is essential, t h o u g h , that the collector circuits b e such that <2i a n d Q n e v e r enter saturation.
'Rr
Rc
u
C
2
cc
v
[{V c
_ 2 l 2-, aMR ]
) c)
R K
R
kc
R
c'
c
V
CC
-
- i v o — ( \ hQi
2
7.3.1 Basic Operation
-?
(smk)H^
Q.
[(Vcc-^Rc) +
C
yr± Ï '\ ©
c
2aL\IR,
<*IR
aMR ] c
1
Y2
A/
-0.7 V
T o see h o w the B J T differential pair w o r k s , consider first the case of the t w o bases joined together and connected to a c o m m o n - m o d e voltage v . That is, as s h o w n in Fig. 7.13(a), CM
© "EE
Vcc
(d)
(C)
FIGURE 7 . 1 3 Different modes of operation of the BJT differential pair: (a) The differential pair with a common-mode input signal v . (b) The differential pair with a "'large" differential input signal, (c) The differential pah' with a large differential input signal of polarity opposite to that in (b). (d) The differential pair with a small differential input signal Note that we have assumed the bias current source / to be ideal (i.e., it has an infinite output resistance) and thus / remains constant with the change in v . CM
CM
B\ = VB2 = CM- Since Q and Q are matched, and assuming an ideal bias current source / with infinite output resistance, it follows that the current / will remain constant and from symmetry that I will divide equally between the two devices. T h u s i = i = 1/2, and the voltage at the emitters will b e v - V , w h e r e V is the b a s e - e m i t t e r voltage (assumed in Fig 7.13a to be V
V
x
2
m
FIGURE 7 . 1 2 The basic BJT differentialpair configuration.
CM
BE
BE
m
705
706
1.
i
DIFFERENTIAL A N D MULTISTAGE
CHAPTER 7
7.3
AMPLIFIERS
approximately 0.7 V ) corresponding to a n emitter current o f 1/2. T h e voltage at each collect TOR will b e V - \aIR , a n d the difference in voltage b e t w e e n t h e t w o collectors will b e zero. cc
c
N o w l e t u s vary t h e v a l u e of t h e c o m m o n - m o d e i n p u t signal v . O b v i o u s l y , as long as <2i a n d Q r e m a i n in the active r e g i o n t h e current I will still d i v i d e e q u a l l y b e t w e e n Q j Q , a n d t h e v o l t a g e s at t h e collectors will n o t c h a n g e . T h u s t h e differential pair does not r e s p o n d t o (i.e., it rejects) c o m m o n - m o d e i n p u t signals. CM
2
x
T H E BJT D I F F E R E N T I A L PAIR
7.3,2 Large-Signal Operation « r NOW o r e s e n t a g e n e r a l analysis of the B J T differential p a i r of F i g . 7.12. If w e d e n o t e t h e W E NOWat F t h e c o m m o n emitter . I _J.! I_: a p p lIi:e d] t o e„ a„ c„ h 1 , of / , Fthe TL,AH„N voltage b y vE, t ,h e e x p o n e n t,i a l relationship two
a i K
TRANSLATORS m a y b e w r i t t e n
2
v
Is
A s a n o t h e r e x p e r i m e n t , let t h e v o l t a g e v
B2
g r o u n d i n g B ) , a n d let v 2
= + 1 V (see F i g . 7.13b). W i t h a bit of r e a s o n i n g it c a n b e seen that
Bl
_
ip
<2i will b e o n a n d c o n d u c t i n g all of t h e current I a n d that Q will b e off. F o r Q to b e on 2
(with V 2
cx
= V
cc
- ccIR
c
and v
a
=
(7.67)
( B2- eV T
(7.68)
v
V
e a
= 0.7 V ) , the emitter h a s to b e a t a p p r o x i m a t e l y + 0 . 3 V , w h i c h k e e p s t h e E B J of
BE1
Q r e v e r s e - b i a s e d . T h e collector v o l t a g e s will b e v
t
v
Is
—
2 h 2
t
/ v
e
E\ = ~
b e set to a c o n s t a n t v a l u e , s a y , zero (by
v
( bi- e)
l
These t w o e q u a t i o n s c a n b e c o m b i n e d to obtain
Y. cc
Let u s n o w c h a n g e v t o - 1 V (Fig. 7 . 1 3 c ) . A g a i n with s o m e r e a s o n i n g it c a n b e seen that Qi will turn off, a n d Q will carry all the current / . T h e c o m m o n emitter will b e at - 0 . 7 V, w h i c h m e a n s that t h e E B J of Q will b e r e v e r s e - b i a s e d b y 0.3 V . T h e collector voltages will be v = V and v = V aIR . Bl
v
i\
v
/V
( B\- Bl) T
E
—
2
= e
l
E2
x
c l
cc
c2
cc
c
which c a n b e m a n i p u l a t e d t o y i e l d
F r o m t h e foregoing, w e see that t h e differential pair certainly responds to large difference£i lEl + hi
m o d e (or differential) signals. I n fact, with relatively small difference voltages w e are able to steer the entire bias current from o n e side of the pair to t h e other. This current-steering property of the differential pair allows it to b e used in logic circuits, as will b e demonstrated in Chapter 11.
T o u s e t h e B J T differential p a i r a s a linear amplifier w e a p p l y a v e r y s m a l l differential
r (7.70)
= (
» E L + »£2
throw switch that w e e m p l o y e d in the realization of the current-mode inverter of Fig. 1.33.
(7.69) ) / V
1
'£2
Indeed, the reader can easily see that the differential pair i m p l e m e n t s the single-pole double-
I 1+ > ( « - ° « e
=
1
+
«
E
^
The circuit i m p o s e s t h e additional constraint
signal (a f e w millivolts), w h i c h w i l l result i n o n e of t h e transistors c o n d u c t i n g a current of 1/2 + AI; t h e current in t h e other transistor will b e 1/2-
A / , with AI b e i n g proportional
to t h e difference input v o l t a g e (see F i g . 7.13d). T h e o u t p u t v o l t a g e taken b e t w e e n t h e two collectors will b e 2aAIR , c
+
¿£1
I
l
E2
(7.71)
U s i n g E q . (7.71) t o g e t h e r w i t h E q s . (7.69) a n d (7.70) a n d substituting v
- v
Bl
w h i c h is p r o p o r t i o n a l t o t h e differential input signal v . T h e
= v
B2
id
t
s m a l l - s i g n a l o p e r a t i o n of t h e differential p a i r will b e studied next, in Section 7 . 3 .
gives (7.72) 1 +< I
7.7
Find
l E 2
and v in the circuit of Fig. E7.7. Assume t h a t \ mately 0.7 V and that a = 1 C2
WßlK§EßlliEii/0EK8IS:
V b e
\ of a conducting transistor is approxi-
T h e collector currents i
c l
and i
c 2
"
-
»«/v
(
r
7
'
7
3
)
l+e c a n b e o b t a i n e d s i m p l y b y m u l t i p l y i n g t h e emitter currents
in E q s . (7.72) a n d ( 7 . 7 3 ) b y a, w h i c h is n o r m a l l y v e r y c l o s e t o u n i t y . T h e f u n d a m e n t a l o p e r a t i o n of t h e differential amplifier is illustrated b y E q s . (7.72) a n d
1 kft
(7.73). First, n o t e that t h e amplifier r e s p o n d s only to t h e difference voltage v . T h a t is, if id
B\ - B2 = %M> t h e current / d i v i d e s equally b e t w e e n t h e t w o transistors irrespective o f t h e
V u
T
V
E
V
value of t h e c o m m o n - m o d e v o l t a g e v . CM
T h i s is t h e e s s e n c e of differential-amplifier opera-
tion, w h i c h also gives rise to its n a m e .
+0.5 V o -
A n o t h e r i m p o r t a n t observation i s ' t h a t ' a relatively small difference voltage v
id
will c a u s e
the current I t o flow a l m o s t entirely in o n e of t h e t w o transistors. F i g u r e 7.14 shows a plot of the t w o collector currents (assuming a — 1) as a function* of the differential input signal. This
V1 C
is a n o r m a l i z e d p l o t that c a n b e used universally. N o t e that a difference voltage of about 4V
T
1 kO
1 kft
r
(—100 m V ) i s sufficient to switch the current almost entirely t o o n e side of the B J T pair. N o t e that this is m u c h smaller than the corresponding voltage for the M O S pair, J2V . 0V
T
Ans.-.H." \ : -5 V: - N . " \
T h e fact that
such a small signal can switch t h e current from one side of the B J T differential pair t o the other Î-a-.ÏURE E 7 . 7
means that the B J T differential pair can b e used as a fast current switch. A n o t h e r reason for the high speed of operation of the differential device as a switch is that neither of the transistors saturates. T h e reader will recall from Chapter 5 that a saturated transistor stores charge in its base that must b e r e m o v e d before the device c a n turn off, generally a slow process that results in
707
CHAPTER 7
7 0 8
7.3
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
T H E BJT D I F F E R E N T I A L PAIR
d3*
slow inverter. T h e absence of saturation in the n o r m a l operation of the B J T differential pahm a k e s the logic family based on it the fastest form of logic circuits available (see Chapter 11). T h e n o n l i n e a r transfer characteristics of the differential pair, s h o w n in Fig. 7.14, will not be utilized any further in this chapter. Rather, in the following w e shall be interested specif ically in t h e application of t h e differential pair as a small-signal amplifier. F o r this purpose the difference input signal is limited to less than about V /2 in order that w e m a y operate on a linear s e g m e n t of the characteristics a r o u n d the m i d p o i n t x (in Fig. 7.14). Before leaving t h e large-signal operation of the differential B J T pair, w e wish to point out an effective technique frequently e m p l o y e d to extend the linear r a n g e of operation. It consists of including t w o equal resistances R in series with the e m i t t e r s ' o f Q and Q , as s h o w n in F i g . 7.15(a). T h e resulting transfer characteristics for three different values of R are sketched in Fig. 7.15(b). O b s e r v e that expansion of the linear r a n g e is obtained at the expense of reduced g (which is the slope of the transfer curve at v = 0) and h e n c e reduced gain. This result should c o m e as n o surprise; R here is performing in exactly the same w a y as the emitter resistance R does in the C E amplifier with emitter degeneration (see Section 6.9.2). Finally, we also note that this linearization technique is in effect the bipolar counterpart of the technique e m p l o y e d for the M O S differential pair (Fig. 7.7). In the latter case, however, V w a s varied by changing the transistors' W/L ratio, a design tool with n o counterpart in the B J T . T
e
x
2
e
m
id
e
e
FIGURE 7 . 1 5 The transfer characteristics of the BJT differential pair (a) can be linearized fl>) (i.e., the linear range of operation can be extended) by including resistances in the emitters.
ov
7.3.3 Small-Signal Operation
7.8 For the B J T differential pair of Fig. 7.12. find the value of input differential signal which is sufficient to causeif! = 0.99/. Ans.
115
In this section w e shall study the application of t h e B J T differential pair in small-signal amplification. F i g u r e 7.16 s h o w s the B J T differential pair with a difference v o l t a g e signal v applied b e t w e e n the two bases. Implied is that the dc level at the input—that is, the c o m m o n m o d e input v o l t a g e — h a s b e e n s o m e h o w established. F o r instance, o n e of the t w o input terminals can b e g r o u n d e d a n d v applied to t h e other input terminal. Alternatively, t h e differential amplifier m a y b e fed from t h e output of another differential amplifier. In t h e latter case, t h e v o l t a g e at o n e of the input terminals will be V + v /2 w h i l e that at the other i n p u t terminal will b e V -v /2. W e will consider c o m m o n - m o d e operation subsequently. id
id
JIIV
CM
CM
1
Recall that saturation of a BJT means something completely different from saturation of a MOSFET!
id
id
710
.
;
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
T H E BJT D I F F E R E N T I A L PAIR
7.3
j/2. W h e n a "small-signal" v is applied differentially (i.e., b e t w e e n the t w o bases), the col lector current of Q increases by an increment i and that of Q decreases b y an equal amount. This ensures that the s u m of the total currents in <2i and Q r e m a i n s constant, as constrained by the current-source b i a s . T h e incremental (or signal) current c o m p o n e n t i is given b y id
x
c
2
2
c
al
v
2V
2
id
T
(7.79)
Equation (7.79) h a s an easy interpretation. First, n o t e from t h e s y m m e t r y of the circuit (Fig- 7-16) that t h e differential signal v should divide equally b e t w e e n t h e b a s e - e m i t t e r junctions of t h e t w o transistors. T h u s the total b a s e - e m i t t e r voltages will b e id
v
id
V
+
BE\QI
— VBE
BE\Q2
—
V
where V
BE
V
BE
x
m
FIGURE 7 . 1 6 The currents and voltages in the differential-amplifier when a small differential input signal v is applied.
id
2
is the dc B E voltage c o r r e s p o n d i n g to an emitter current of 7 / 2 . Therefore, the
collector current of Q will increase b y g v /2 by g v /2.
2
Here g
m
m
and t h e collector current of Q will decrease
id
2
denotes the t r a n s c o n d u c t a n c e of Q a n d of Q , w h i c h are e q u a l a n d X
2
given b y
id
h
=
The Collector Currents W h e n v
Is A p p l i e d
i d
F o r the circuit of Fig.
7.16.
we may
aI/2
=
(7.80)
use
Eqs. (7.72) a n d (7.73) to write
Thus Eq. (7.79) s i m p l y states that i =
g v !2.
c
m
id
An A l t e r n a t i v e V i e w p o i n t T h e r e is an e x t r e m e l y useful alternative interpretation of t h e results a b o v e . A s s u m e the current source / to b e ideal. Its i n c r e m e n t a l resistance then will b e infinite. T h u s t h e v o l t a g e v appeai-s across a total resistance of 2r , w h e r e id
e
1 + e M u l t i p l y i n g t h e n u m e r a t o r and the d e n o m i n a t o r of t h e r i g h t - h a n d side of E q . (7.74) by e gives ,d
lL h
= 121/2
(7.81)
T
Correspondingly there will b e a signal current i , as illustrated in Fig. 7.17, given b y e
Vid/2Vr
aIe •
Vid
e
~
e
,
+e
e
(7.82)
2r
e
A s s u m e that v < 2V . W e m a y thus e x p a n d the exponential only t h e first t w o t e r m s : id
(7.76)
T
( + v e
'"
/ 2 V T ) m
a
s e r
i
e S :
a p
d retain
Thus the collector of Q
l
will exhibit a current i n c r e m e n t i and the collector of Q c
2
will
exhibit a current d e c r e m e n t i : c
__a7(l + l c i
l + v /2V id
T
v /2V ) id
T
+
i
l~v /2V id
c
T
= ai
e
= p i 2r
=
g
e
Thus
C I
2
2V
T
{
2
'
m
^ 2
(7.83)
Note that in Fig. 7.17 w e h a v e s h o w n signal quantities only. It is implied, of c o u r s e , that each transistor is biased at an emitter current of 7 / 2 . This m e t h o d of analysis is particularly useful w h e n resistances are i n c l u d e d in the emit ters, as s h o w n in F i g . 7.18. F o r this circuit w e h a v e
S i m i l a r m a n i p u l a t i o n s can b e applied to E q . (7.75) to obtain i
= C 1
al _ 2
al
v
2V
2
T
id
(7.78)
E q u a t i o n s (7.77) and (7.78) tell us that w h e n v = 0, t h e bias current / divides equally b e t w e e n the t w o transistors of the pair. T h u s each transistor is biased at an emitter current of id
2i- + 2R„
•
(7-84)
I n p u t D i f f e r e n t i a l R e s i s t a n c e Unlike the M O S differential amplifier, which has an infinite input resistance, the b i p o l a r differential pair exhibits a finite input resistance, a result of t h e finite B of the B J T .
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
CHAPTER 7
7.3
T H E BJT D I F F E R E N T I A L PAIR
Thus the differential input resistance R is given b y id
T2r„
2r, I
R
l
d
^ = { B
+ l)2r =2r e
(7.86)
M
l
b
Rr
This result is just a restatement of the familiar resistance-reflection rule; namely, the resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by(B + l). We can employ this rule to find the input differential resistance for the circuit in Fig. 7.18 as
a
Vjd +
K
2r„ c
'id
08 + l)2r >-
e
R
•I
= (B + \){2r +2R )
id
e
(7.87)
e
D i f f e r e n t i a l V o l t a g e G a i n W e h a v e established that for small difference input voltages <4 2V ; i.e., v smaller t h a n about 20 m V ) the collector currents are given b y
7/2
T
id
k + gJj ici = Ic~ FIGURE 7 . 1 7 A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal v ; dc quantities are not shown. id
(7-88)
8 m ~
(7-89)
where /
= f
c
(7-90)
Thus the total voltages at the collectors will b e »ci = (V -IcRc)-g RcY cc
v2 C
(7.91)
m
= (V -I R ) cc
c
+g
c
m
R
c
^
(7.92)
The quantities i n parentheses are simply the d c voltages at each of the t w o collectors. As in the M O S case, the output voltage signal of a bipolar differential amplifier can be taken either differentially (i.e., b e t w e e n the two collectors) or single-endedly (i.e., between one col lector and g r o u n d ) . If the output is taken differentially, t h e n the differential gain (as o p p o s e d to the c o m m o n - m o d e gain) of the differential amplifier will b e Ad =
*
2(/3 + 1) (r, +
= ~g Rc
(7-93)
m
On the other h a n d , if w e take the output single-endedly (say, b e t w e e n the collector of g j a n d ground), t h e n the differential gain will b e given b y R) e
:
X-=— =-h Rc d
FIGURE 7 . 1 8 A differential amplifier with emitter resistances. Only signal quantities are shown (in color).
T h e input differential resistance is the resistance seen b e t w e e n the t w o bases; that is, it is the resistance seen by the differential input signal v . For the differential amplifier in Figs. 7.16 and 7.17 it can b e seen that the base current of Q s h o w s a n i n c r e m e n t i a n d the base current of Q s h o w s a n equal decrement,
(7-94)
IH
v
2
For the differential amplifier with resistances i n the emitter leads (Fig. 7.18) t h e differ ential gain w i t h the output is taken differentially is given b y
id
x
2
b
d
2r +2R e
e
r +R e
e
This equation is a familiar one: It states that the voltage gain is equal to the ratio of the total resistance in the collector circuit (2R ) to the total resistance in the emitter circuit (2r + 2R ). C
e
e
> 713
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
(a)
7.3
'
T H E BJT D I F F E R E N T I A L PAIR
(b)
FIGURE 7 . 1 9 Equivalence of the BJT differential amplifier in J[a) to the two common-emitter amplifiers in (b). This equivalence applies only for differential input signals. Either of the two common-emitter amplifiers in (b) can be used to find the differential gain, differential input resistance, frequency response, and so on, of the differential amplifier.
Equivalence of the Differential Amplifier to a Common-Emitter Amplifier
The
a n a l y s i s and results o n the p r e v i o u s p a g e are quite similar to t h o s e obtained in t h e case of a c o m m o n - e m i t t e r amplifier stage. T h a t t h e differential amplifier is in fact equivalent to a c o m m o n - e m i t t e r amplifier is illustrated in Fig. 7.19. Figure 7.19(a) shows a differential ampli fier fed b y a differential signal v
id
w h i c h is applied in a c o m p l e m e n t a r y ( p u s h - p u l l or
circuit m o d e l , t h e circuit in F i g . 7.21 results. In e v a l u a t i n g t h e m o d e l p a r a m e t e r s r , g„„ a n d n
b a l a n c e d ) m a n n e r . T h a t is, w h i l e t h e b a s e of Q is raised b y v /2, x
id
t h e b a s e of Q is l o w e r e d 2
r , w e m u s t recall that the half-circuit is biased at 7/2. T h e v o l t a g e gain of the differential 0
b y v /2.
W e h a v e also i n c l u d e d the output r e s i s t a n c e R
id
of t h e bias current source. F r o m
EE
symmetry, it follows that the signal voltage at the emitters will b e zero. T h u s the circuit is
amplifier (with t h e o u t p u t t a k e n differentially) is e q u a l to the v o l t a g e gain of the halfcircuit—that is, v /{v /2). cl
equivalent to the t w o c o m m o n - e m i t t e r amplifiers s h o w n in Fig. 7.19(b), w h e r e e a c h of the
id
H e r e , w e note that including r„ will modify the gain e x p r e s s i o n
in Eq. (7.93) to
t w o transistors is b i a s e d at an emitter c u r r e n t of 1/2. N o t e that t h e finite output resistance R
of t h e c u r r e n t s o u r c e will h a v e n o effect o n t h e o p e r a t i o n . T h e e q u i v a l e n t circuit in
EE
A
d
=-g (R Wr ) m
c
(7.96)
0
Fig. 7 . 1 9 ( b ) is valid for differential o p e r a t i o n only. In m a n y applications t h e differential amplifier is n o t fed in a c o m p l e m e n t a r y fashion; rather, t h e i n p u t signal m a y b e applied to o n e of the i n p u t terminals w h i l e the other terminal is g r o u n d e d , as s h o w n in F i g . 7.20. In this c a s e t h e signal v o l t a g e at t h e emitters will n o t b e zero, and t h u s t h e resistance R
EE
will h a v e an effect o n t h e operation. N e v e r t h e l e s s , if R
EE
2
large (R
> r ), as is u s u a l l y the c a s e , t h e n v
EE
e
id
amplifier in this c a s e will b e a l m o s t identical to that in the c a s e of s y m m e t r i c feed, a n d the = -v , cl
n
c o m m o n - e m i t t e r transistor w i t h a resistance R in t h e emitter lead. e
C o m m o n - M o d e Gain a n d CMRR
Figure 7.22(a) shows a differential amplifier fed b y a
c o m m o n - m o d e voltage signal r , , . 'flic resistance R v
is the incremental output resistance of the
EE
bias current source. F r o m symmetry it can be seen that the circuit is equivalent to that s h o w n in Fig. 7.22(b), w h e r e each of the t w o transistors g , arid Q is biased at an emitter current 1/2 and
c o m m o n - e m i t t e r e q u i v a l e n c e c a n still b e e m p l o y e d . c2
that is, 2r . Finally, w e note that the differential half-circuit of the amplifier of Fig. 7.18 is a
is
will still d i v i d e equally (approximately)
b e t w e e n t h e t w o j u n c t i o n s , as s h o w n in F i g . 7.20. T h u s t h e operation of the differential
S i n c e in F i g . 7.19 v
The input differential resistance of the differential amplifier is twice that of the half-circuit—
2
t h e t w o c o m m o n - e m i t t e r transistors in F i g . 7.19(b) yield
similar results a b o u t t h e p e r f o r m a n c e of t h e differential amplifier. T h u s only o n e is n e e d e d to a n a l y z e t h e differential small-signal o p e r a t i o n of t h e differential amplifier, and it is
has a resistance 2R
EE
in its emitter lead. T h u s the c o m m o n - m o d e output voltage v
cl
_
a
2R
FF
R
c
_
.,
+ r,
id
as the differential half-circuit and replace the transistor with its low-frequency equivalent
EB
appears in parallel with the much smaller r of Q . e
2
c
A t the other collector w e h a v e an e q u a l c o m m o n - m o d e signal aR,
Note that R
R
-v,
,
(7 97)
2R EE
k n o w n as t h e differential half-circuit. If w e t a k e t h e c o m m o n - e m i t t e r transistor fed with +v /2
a
will be
R
c
2 EE
v, c2
(7.98)
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
7.3
The analysis on t h e facing page assumes that t h e circuit is perfectly symmetrical. However, practical circuits are n o t perfectly symmetrical, with t h e result that t h e c o m m o n - m o d e gain will not b e zero even if t h e output is taken differentially. T o illustrate, consider t h e case of perfect s y m m e t r y except for a m i s m a t c h AR in t h e collector resistances. That is, let the collector of Q h a v e a load resistance R , and Q h a v e a load resistance R + AR . It follows that
Rr
C
x
v
c\ O -
-OV
-O
cl
Q ß ,
o
T H E BJT DIFFERENTIAL PAI
ß
2
V„
C-
c
2
c
C
aR
J
c
%i—°
o
°—K
1
• Biased at 1/2
2R
F
a(R
+ AR )
c
C
2R
+ r
EE
e
2R„ Thus the signal at t h e output d u e t o t h e c o m m o n - m o d e input signal will b e aAR
©
c
2R
+ r.
EE
and the c o m m o n - m o d e gain will b e _
- V ,EE
ft,-
aAR
AR
C
+r
EE
(a)
_
c
2R
2R
e
EE
(b)
This expression c a n b e rewritten as FIGURE 7 . 2 2 (a) The differential amplifier fed by a common-mode voltage signal i ^ . (b) Equivalent "half-circuits" for common-mode calculations. A
cm
- i
f"
2K
K
EE
N o w , if t h e output is taken differentially, then t h e output c o m m o n - m o d e voltage v = O c t - v ) will b e zero a n d t h e c o m m o n - m o d e g a i n also will b e zero. O n t h e other hand", if the output is taken single-endedly, t h e c o m m o n m o d e gain A will b e finite a n d given b y
C
(7-103)
c
a
cl
3
cm
aR
r
(7.99)
2R
g
Since i n this case t h e differential gain is
C o m p a r e t h e c o m m o n - m o d e gain in E q . (7.103) w i t h that for single-ended output in Eq. (7.99). W e see that the c o m m o n - m o d e gain is m u c h smaller in t h e case of differential output. Therefore t h e input differential stage of a n o p a m p , for e x a m p l e , is almost always a balanced one, w i t h t h e output taken differentially. T h i s ensures that t h e o p a m p will h a v e t h e lowest possible c o m m o n - m o d e gain or, equivalently, a h i g h C M R R . T h e input signals v a n d v t o a differential amplifier usually contain a c o m m o n - m o d e component, v , x
2
icm
R
~
\g C
(7.100)
m
v
the c o m m o n - m o d e rejection ratio ( C M R R ) will b e A„
CMRR
(7.101)
R
8m E
i
c
=
m
V
- ^
(7.104)
and a differential c o m p o n e n t v , id
v
v
v
td= \~ 2
N o r m a l l y t h e C M R R is expressed in decibels,
(7.105)
Thus t h e output signal will b e given in general b y CMRR = 20 log
(7.102) A
v
= A (y -
0
d
r
v) +
(7-106)
2
Each of t h e circuits in Fig. 7.22(b) is called t h e c o m m o n - m o d e half-circuit. The expressions in Eqs. (7.97) and (7.98) are obtained by neglecting r . A detailed derivation using the results of Section 6.4 shows that v /v and v /v are approximately 0
cl
km
c2
icm
I n p u t Common-Mode Resistance T h e definition of t h e c o m m o n - m o d e i n p u t r e s i s tance R is illustrated i n F i g . 7.23(a). F i g u r e 7.23(b) s h o w s t h e equivalent c o m m o n - m o d e half-circuit; its input resistance is 2R . T h e value of 2R can b e determined using t h e expression w e derived in Section 6.9 for t h e input resistance of a C E amplifier w i t h a resistance in t h e emitter. Specifically, w e can u s e E q . (6.157) a n d substitute R = 2R and R - R to o b t a i n for t h e c a s e R < r a n d 2R 9> r t h e a p p r o x i m a t e expression icm
lcm
~aR (^ 2R
2R
r
P
e
r
where it is assumed that R < Qr„ and 2R (7.98) when 2R <§; Br . c
EB
B
EE
icm
> r . This expression reduces to those in Eqs. (7.97) and
L
c
c
0
EE
e
n
4
2 ^ - 0 3 + 1 X 2 ^
\\r ) a
EE
7.3
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
T H E BJT DIFFERENTIAL
AMPLIFIERS
+ 15 V
R
R
= 10 k i l
r
5kO
B
-AAA/
VJ
2
C
lcm
B —6~ 2
V
R — 150 O
fid
Z R - 150 SI
F
k
-
VvV 5 Ml
(b) F I G U R E 7 . 2 3 (a) Definition of the input common-mode resistance R . mode half-circuit.
+
I -
S
W
n
L
+
6
2
v
01
t
°-
= 10 kfl
r
o-
(b) The equivalent common-
R
= 1 mA
= 200 k f l .
FF
Thus, FIGURE 7.24 lcm
EE
(b) E q u a t i o n (7.107) indicates that since R
is typically of the order of r , R
EE
Circuit for Example 7.1.
(7.107)
R ^(ß+l)[R \\^
a
icm
The voltage gain from the signal source to the bases of g i and Q is 2
will be very
R,
large.
R^
+ Ri,
40 = 0.8 V/V 5 + 5 + 40 The voltage gain from the bases to the output is The differential amplifier in Fig. 7.24 uses transistors with ¡5 = 100. Evaluate the following:
v
Total resistance in the collectors
0 =
~v~~, Total resistance in the emitters
(a) The input differential resistance R . id
(b) T h e overall differential voltage gain v„/v
sig
(neglect the effect of r ) .
5
2 x 10
2R
0
r
(c) The worst-case common-mode gain if the two collector resistances are accurate to within ±1 %.
2(r +R ) e
50 V/V
2 ( 5 0 + 150) x 10
E
(d) T h e C M R R , in dB. (e) T h e input c o m m o n - m o d e resistance (assuming that the Early voltage V = 100 V ) .
The overall differential voltage gain can now be found as
A
A
Solution (a) Each transistor is biased at an emitter current of 0.5 m A . Thus V
T
>"«2 =
T-
I
E
25 m V 0.5 m A
= Hz.
v
=
2 a'2± = 0 . 8 x 5 0 = 40 V/V
(c) Using Eq. (7.103), Rç
= 50 O c m
2R
EE
T h e input differential resistance can now b e found as id
=
2(ß+Y)(r +R ) e
C
R
c
where AR = 0 . 0 2 i ? in the worst case. Thus, r
R
&R
E
c
A
= c m
= 2 x 101 x ( 5 0 + 150) = 4 0 k Q
1
0
2 x 200
4
x 0.02 = 5 x lO^ V/V
PAIR
7 2 0
SLl*
CHAPTER 7
DIFFERENTIAL
A N D
MULTISTAGE
7.4
AMPLIFIERS
OTHER
NONIDEAL
CHARACTERISTICS
OF THE DIFFERENTIAL
AMPLIFIER
C M R R = 20 l o g — ^
(d)
j4
40 = 20 log= 98 dB 5 x 10" r
(e)
n
=
= 125
1/2
=
•Rn
Rm
200 k Q
-
0.5
+
Using Eq. (7.107), if—o-
Qi R
= {B+\)
icm
R^W-Z
hi"
101(200 k Q || 100 k Q ) = 6.7 M Q
'IP
EXERCISE T 7.9 For the circuit in Fig. 7.16, l e t / = 1 mA, V -= 15 V. R = 10 k Q , with a= I, and let the input voltages be: v = 5 + 0.005 sin 2 K X 1000?. volts, and v = 5 - 0.005 sin 2 K X 1000/, volts, (a) If the BJTs are specified to have v . of 0.7 V at a collector current of 1 mA. find the voltage al the emitters. (Hint: Observe the symmetry of the circuit.) (b) Find g for each of the two transistors, (c) Find i for each of the two transistors, (d) Find v for each of the two transistors, (c) Find the voltage between the two col lectors. (f)Find the gain experienced by the 1000-Hz signal. n
m
c
(a)
lG
FIGURE 7 . 2 5 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage V results, (b) Application of a voltage equal to the input offset voltage V to the input tenninals with opposite polarity reduces V to zero.
Bl :
m
c
0
c
os
Ans. (a) 4.317 V: (b) 20 rnA/V; (c) / = 0.5 + 0.1 sin 2 K X lOOOr, mA and i = 0.5 - 0.1 sin 2TT X 1 OOOr, mA; (d) v = 1 0 - 1 sin 2 K x lOOOf, V and v = 1 0 + 1 sin 2 K X 1000r. V; (e) v - v = 2 sin 2 K X 1000;, V; (f) 200 V/V n
0
C2
n
n
a
For the differential pair s h o w n in Fig. 7.25(a) consider first t h e c a s e w h e r e <2i a n d Q are 2
a
perfectly m a t c h e d b u t R
M
and R
D2
s h o w a m i s m a t c h AR ; that is, D
+ ^Y
R
=D
R2
{
D1
1
D
2
less, b e c a u s e o f t h e m i s m a t c h in l o a d r e s i s t a n c e s , t h e o u t p u t v o l t a g e s V
C o n s i d e r t h e basic M O S differential amplifier w i t h b o t h inputs grounded, as s h o w n in Fig. 7.25(a). If the t w o sides of the differential pair w e r e perfectly m a t c h e d (i.e., Q and Q identical and R = R = R ), then current I w o u l d split equally b e t w e e n Q and Q , and V w o u l d b e z e r o . Practical circuits exhibit m i s m a t c h e s that result in a dc output voltage V e v e n with b o t h inputs grounded. W e call V the o u t p u t d c offset v o l t a g e . M o r e c o m m o n l y , w e divide V b y t h e differential gain of the amplifier, A , to obtain a quantity k n o w n as the i n p u t offset v o l t a g e , V , D2
(7.H0)
B e c a u s e Q and Q a r e m a t c h e d , t h e c u r r e n t / will split e q u a l l y b e t w e e n t h e m . N e v e r t h e
7.4.1 Input Offset Voltage of the MOS Differential Pair
m
= R D - ^
D
7.4 OTHER NONIDEAL CHARACTERISTICS • OF THE DIFFERENTIAL AMPLIFIER
(7-109)
1
2
v., -
2
v
and V
D2
will b e
- ' { ^ )
m
0
0
0
0
d
T h u s t h e differential o u t p u t voltage V will be 0
os
J
V =V /A 0S
0
d
V =V
(7.108)
O b v i o u s l y , if w e apply a voltage -V b e t w e e n t h e input terminals of t h e differential amplifier, t h e n t h e output voltage will b e r e d u c e d to z e r o (see Fig. 7.25b). This observation gives rise t o the usual definition of the input offset voltage. It should b e noted, h o w e v e r , that since t h e offset v o l t a g e is a result of d e v i c e m i s m a t c h e s , its polarity is n o t k n o w n a priori.
0
-V
o
l
, (7.1H)
D
T h e c o r r e s p o n d i n g i n p u t offset v o l t a g e i s obtained b y d i v i d i n g V b y the gain g R 0
stituting for g
m
t
2
= (0Atf
os
T h r e e factors contribute t o the dc offset v o l t a g e of t h e M O S differential pair: m i s m a t c h in load resistances, m i s m a t c h in W/L, and m i s m a t c h in V . W e shall consider the three con tributing factors o n e at a time.
D
from E q . (7.30). T h e result is
m
D
and sub
722
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
T h u s t h e offset v o l t a g e is directly p r o p o r t i o n a l to V and, of c o u r s e , to AR /R . A s an e x a m p l e , c o n s i d e r a differential pair in w h i c h t h e t w o transistors are operating at an overdrive v o l t a g e of 0.2 V and each drain resistance is accurate to within ± 1 % . It follows that the w o r s t - c a s e resistor m i s m a t c h will b e ov
ARç
OTHER
7.4
D
D
NONIDEAL
CHARACTERISTICS OF THE DIFFERENTIAL
AMPLIFIER
Similarly, 2
L
"V.
V
- V
GS
t
It follows that k j-(V
0.02
2
n
-V )
GS
=
t
-
R
n
and the current i n c r e m e n t (decrement) in Q ( g i ) is
a n d the resulting input offset v o l t a g e will b e |y
0 5
2
| = 0.1x0.02 =
1
2mV
2 V
x
Dividing AI b y g
V
ov
= AV ,
os
(7.114)
\L
(7.120)
t
a very logical result! F o r m o d e r n M O S t e c h n o l o g y AV, can b e easily as h i g h as 2 m V . Finally, w e n o t e that since t h e three sources for offset v o l t a g e are n o t correlated, an estimate
S u c h a m i s m a t c h causes t h e current I to n o l o n g e r divide e q u a l l y b e t w e e n Q and Q . Rather, it can b e s h o w n that t h e currents I and I will b e x
x
V
input offset v o l t a g e (due to AV,). T h u s ,
(7.113)
W 2
gives half'the
m
+
L
2
t
2
= L^ 2 U^U
'W\
= W -V
GS
Next, c o n s i d e r t h e effect of a m i s m a t c h in t h e W/L ratios of Q a n d Q , expressed as 'W X
1
AVT
A/ =
2
of the total input offset v o l t a g e can b e found as
2
1=1 2
+
I(MW/Q} 2\2(W/L))
I = ï -
I(Mw/M
1
2
2
(7.115) (7.116)
2\2(W/L))
D i v i d i n g t h e current i n c r e m e n t 7.10 For the M O S differential pair specified in Hxcrci.se 7.4, find the three components of the input offset voltage. Let AR,JR„ = 2%, A( W/L)I(W/L) = 2%. and AV, = 2 mV. Use Eq. (7.123) to obtain an estimate of the total V .
I(A(W/L)\ 2\2(W/L))
os
b y 8m gives half the input offset v o l t a g e ( d u e to t h e m i s m a t c h in W/L values). T h u s
'-(-IS) . H e r e again w e n o t e that V , expected, A(W/L).
(7.117)
resulting from a (W/L) m i s m a t c h , is proportional to V
os
Ans. 4 mV: 4 mV; 2 m V ; 6 mV
ov
and, as
Finally, w e c o n s i d e r t h e effect of a m i s m a t c h AV b e t w e e n t h e t w o threshold voltages, t
(7.118)
7.4.2 Input Offset Voltage of the Bipolar Differential Pair The offset v o l t a g e of t h e bipolar differential pair s h o w n in F i g . 7.26(a) can b e d e t e r m i n e d in a manner a n a l o g o u s to that u s e d a b o v e for t h e M O S pair. N o t e , h o w e v e r , that in the bipolar case there is n o analog to t h e V, m i s m a t c h of the M O S F E T pair. H e r e the output offset results from m i s m a t c h e s in t h e load resistances R and R and from j u n c t i o n area, B, a n d other m i s m a t c h e s in Q and Q . C o n s i d e r first the effect of t h e load m i s m a t c h . L e t cl
v„
x
= V,
C2
2
(7.119)
2
R
L
=R
[
(
+
^£
(7.122)
T h e current Jj will b e g i v e n b y l,,W GS
R
•v, AV
t
1
2(V -V,)_ GS
w h i c h , for AV <& 2(V t
GS
- V ) [that is, AV
T
t
~
0V
,,,2(i
can b e a p p r o x i m a t e d as AV,
r
i
=
R
c
. ^ k
(7.123)
and a s s u m e that Qi and Q are perfectly m a t c h e d . It follows that current I will divide equally 2
between g , and Q , and thus 2
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
7.4
AMPLIFIERS
jives
OTHER NONIDEAL CHARACTERISTICS OF THE DIFFERENTIAL AMPLIFIER
rise to a proportional m i s m a t c h in the scale currents I
s
1
51
1
52
Refer to Fig. 7.26(a) and note that V
= I +^
(7.126)
= I
(7.127)
S
S
- ^
= V . T h u s , the current I will split b e t w e e n Q and
BE1
BE2
x
Q in proportion to their I values, resulting in 2
s
'.. = £+£J
C7.12S
© It follows that the output offset voltage will b e T (a)
(b)
F I G U R E 7 . 2 6 (a) The BJT differential parr with both inputs grounded. Device mismatches result in a finite dc output V . (b) Application of the input offset voltage V = V /A to the input terminals with opposite polarity reduces V to zero. 0
os
0
and the corresponding input offset voltage will be
d
0
\VOS\ ,\ v
T h u s the output voltage will be
n
= V,(^A "Ty j V is
(7.130)
As an e x a m p l e , a n area m i s m a t c h of 4 % g i v e s r i s e to AI /I = 0.04 a n d an i n p u t offset voltage of 1 m V . H e r e a g a i n w e n o t e that t h e offset v o l t a g e is p r o p o r t i o n a l t o V r a t h e r than to the m u c h l a r g e r V , w h i c h d e t e r m i n e s t h e offset of t h e M O S p a i r d u e to A(W/L) mismatch. S
V, Vo = V
- V
C2
cl
= a\
\\(AR )
T
C
ov
and the input offset voltage will be
Since the t w o contributions to the input offset voltage are n o t correlated, an estimate of
a(I/2)(AR ) c
V
os
Substituting A = g R d
m
c
S
(7.124)
A~,
the total input offset v o l t a g e can b e found as
and aI/2 V T
gives
- H * * J < * $ AR
C
W, os\
(7.125) ~Rr~
< 7 J 3 1 )
There are other p o s s i b l e sources for input offset voltage such as m i s m a t c h e s in the val ues of B and r . S o m e of t h e s e are investigated in the end-of-chapter p r o b l e m s . Finally, it should be noted that there is a p o p u l a r s c h e m e for c o m p e n s a t i n g for the offset voltage. It involves introducing a deliberate m i s m a t c h in the values of the t w o collector resistances such that the differential output voltage is r e d u c e d to zero w h e n b o t h input terminals are grounded. Such an o f f s e t - n u l l i n g s c h e m e is explored in P r o b l e m 7.57. 0
A n i m p o r t a n t p o i n t to note is that in c o m p a r i s o n to the c o r r e s p o n d i n g expression for the M O S pair (Eq. 7.113) h e r e the offset is proportional to V rather than V /2. V at 25 m V is 4 to 10 times l o w e r than V /2. H e n c e bipolar differential pairs exhibit lower offsets than then- M O S counterparts. A s an e x a m p l e , c o n s i d e r the situation w h e r e the collector resistors are accurate to within ± 1 %. T h e n the w o r s t case m i s m a t c h will b e ; T
ov
T
ov
7.4.3 Input Bias and Offset Currents of trie Bipolar Pair ^
= 0.02
In a perfectly s y m m e t r i c differential pair the t w o input terminals carry equal dc currents;
R
c
that is,
and the resulting input offset voltage will b e \V \ 0S
= 2 5 x 0 . 0 2 = 0.5 m V
=>*<--jh
N e x t consider the effect of m i s m a t c h e s in transistors Q a n d Q . In particular, let the transistors h a v e a m i s m a t c h in their e m i t t e r - b a s e j u n c t i o n areas. S u c h an area mismatch x
2
This is the input bias current of the differential amplifier.
( 7
'
1 3 2 )
7 2 6
.
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
7.5
AMPLIFIERS
M i s m a t c h e s in the amplifier circuit and m o s t importantly a m i s m a t c h in B m a k e the tw input dc currents u n e q u a l . T h e resulting difference is the input offset current, I , [ ° O S
=
IQS
G VSN
A S
_
|^fii -^B2|
THE DIFFERENTIAL AMPLIFIER WITH ACTIVE L O A D
$
differential stage in an o p - a m p circuit that primarily determines the o p - a m p dc offset volt age input bias and offset currents, a n d input c o m m o n - m o d e range.
(7.133)
Let 7 11 For a B J T differential amplifier utilizing transistors having B = 100. matched to 10% or belter, and areas that are matched to 10% or belter, along with collector resistors that are matched to 2% or better, find V , I , and I . The dc bias current / is 100 ^ A . , , Ans.2.55m\:ii.5.».\:50n.\ os
2
B
os
2
then /
B 1
r / B 2
7
1
~
~ 2 B+l+A/3/2 —
I
1
1
1
7
1
d
1
/
1
1
i
(,1
" 2 / 3 7 7 3 ^ 7 2 ~2/J7TL
0 S
^
1
( 7 J 3 4
TB)
~2jTlV
L
A D +
)
AB\ \
' 7.5
THE DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD
As w e learned in Chapter 6, replacing the drain resistance R with a constant-current source results in a m u c h higher voltage gain as well as savings in chip area. T h e same, of course, applies to the differential amplifier. In this section w e study an ingenious circuit for implementing an active-loaded differential amplifier and at the same time converting the output from differential to single-ended. W e shall study both the M O S and bipolar forms of this popular circuit. D
(7
2^J
-
135
)
(7.136)
2(f3+l){l3j
F o r m a l l y , the i n p u t bias current I is defined as follows: B
h
=
~ 2 ~
7
= 2Ô8+T)
^ -
1 3 7
)
Thus
/
o
s
=
(
7
-
1
3
8
)
A s an e x a m p l e , a 1 0 % /J m i s m a t c h results in an offset that is current one-tenth t h e value of the input bias current. Finally note that obviously a great a d v a n t a g e of the M O S differential pair is that it does n o t suffer from a finite input bias current or from m i s m a t c h e s thereof!
7.5.1 Differential-to-Single-Ended Conversion In the p r e v i o u s sections w e found that taking the output of the differential amplifier as the voltage b e t w e e n the t w o drains (or collectors) results in d o u b l e the value of the differential gain as well as a m u c h r e d u c e d c o m m o n - m o d e gain. In fact, the only reason a small fraction of an input c o m m o n - m o d e signal a p p e a r s b e t w e e n the differential output terminals is the mismatches inevitably present in the circuit. T h u s if a multistage amplifier (such as an op a m p ) is to achieve a h i g h C M R R , the output of its first stage m u s t b e taken differentially. B e y o n d the first stage, h o w e v e r , unless the system is fully differential, t h e signal is c o n v e r t e d from differential to single-ended. Figure 7.27 illustrates the simplest m o s t - b a s i c approach for differential-to-single-ended conversion. It consists of simply ignoring the drain current signal of Q and elirninating its drain {
7.4.4 Input Common-Mode Range A s m e n t i o n e d earlier, t h e i n p u t c o m m o n - m o d e r a n g e of a differential amplifier is the range of the input-voltage v over w h i c h the differential pair b e h a v e s as a linear amplifier for dif ferential i n p u t signals. T h e u p p e r limit of the c o m m o n - m o d e r a n g e is determined by Q and Q l e a v i n g the active m o d e a n d entering t h e saturation m o d e of operation in the B J T case or the triode m o d e of operation in the M O S case. T h u s , for the bipolar case the u p p e r limit is approximately equal to 0.4 V a b o v e the dc collector voltage of Qi and Q . F o r the M O S case, the u p p e r limit i s e q u a l t o V, volts a b o v e t h e v o l t a g e at the drains of Q a n d Q . T h e l o w e r limit is d e t e r m i n e d by the transistor that Supplies the biasing current I leaving its active r e g i o n of operation and thus n o l o n g e r functioning as a constant-current source. C u r r e n t - s o u r c e circuits w e r e studied i n Sections 6.3 a n d 6.12. CM
x
2
2
l
- o v„ -vjlo
11
I
Gi
~-<>-v /2 M
2
7.4.5 A Concluding Remark W e c o n c l u d e this section by noting that the definitions p r e s e n t e d h e r e are identical to those p r e s e n t e d in C h a p t e r 2 for o p a m p s . In fact, as will b e s e e n in C h a p t e r 9, it is the input
F I G U R E 7 . 2 7 A simple but inefficient approach for differential to single-ended
-v
ss
conversion.
7
CHAPTER 7
DIFFERENTIAL
A N D MULTISTAGE
AMPLIFIERS THE DIFFERENTIAL
7.5
resistor altogether, and taking t h e output between t h e drain of Q and ground. T h e obvious draw back of this scheme is that w e lose a factor of 2 (or 6 d B ) in gain as a result of "wasting" the drain signal current of Q A m u c h better approach w o u l d b e t o find a w a y of utilizing the draincurrent signal of Q j , and that is exactly w h a t t h e circuit w e are about to discuss accomplishes. 2
y
m
u
F i g u r e 7.28(a) s h o w s a M O S differential p a i r f o r m e d b y transistors Q a n d Q , loaded in a current m i r r o r formed b y transistors Q a n d Q . T o see h o w this circuit operates consider first t h e q u i e s c e n t state w i t h t h e t w o i n p u t t e r m i n a l s c o n n e c t e d t o a d c voltage equal to the c o m m o n - m o d e e q u i l i b r i u m v a l u e , in this c a s e 0 V , a s s h o w n in F i g . 7.28(b). A s s u m i n g per fect m a t c h i n g , t h e bias current I d i v i d e s equally b e t w e e n Q a n d Q . T h e drain current of Q 1/2, is fed t o the i n p u t transistor of t h e mirror, Q . T h u s , a r e p l i c a of this current is provided b y the output transistor of the mirror, Q . O b s e r v e t h a t at t h e output n o d e t h e t w o currents 1/2 balance e a c h o t h e r out, leaving a zero current t o flow o u t t o t h e n e x t stage or t o a load (not shown). If Q is perfectly m a t c h e d to Q , its drain v o l t a g e w i l l track t h e v o l t a g e at t h e drain }
3
2
4
x
2
3
4
4
3
h
ACTIVE
s
of Qi> e q u i l i b r i u m t h e v o l t a g e at t h e output will b e V - V . It should b e noted, however, that in practical i m p l e m e n t a t i o n s , there will a l w a y s b e m i s m a t c h e s , resulting in a net dc current at t h e output. In t h e absence of a load resistance, this current will flow into the output resistances of Q and Q and thus can cause a large deviation in t h e output voltage from the ideal value. Therefore, this circuit is a l w a y s designed so that the dc bias voltage at the output n o d e is defined by a feedback circuit rather than b y simply relying o n the m a t c h i n g of Q a n d Q - W e shall see h o w this is d o n e later. DD
2
7.5.2 The Active-Loaded MOS Differential Pair
AMPLIFIER WITH
4
SG3
4
3
Next, consider the circuit with a differential input signal v applied to the input, as shown in Fig. 7.28(c). Since w e are n o w investigating the small-signal operation of the circuit, we have r e m o v e d the d c supplies (including the current source 7). A l s o , for the time b e i n g let us ignore r o f all transistors. A s F i g . 7.28(c) s h o w s , a virtual g r o u n d will d e v e l o p at the c o m m o n - s o u r c e terminal of Q a n d Q . Transistor Q will c o n d u c t a drain signal current / = g v /2, a n d transistor Q will c o n d u c t an e q u a l b u t opposite current i. T h e drain signal cur rent i of Q\ is fed to the input of t h e Q - Q mirror, w h i c h r e s p o n d s b y p r o v i d i n g a replica in the drain of Q . N o w , at t h e output n o d e w e h a v e t w o currents, each e q u a l to i, which s u m together to p r o v i d e an output current 2i. It is this factor of 2, w h i c h is a result of the current mirror action, that m a k e s it possible to convert the signal to single-ended form (i.e., b e t w e e n the output n o d e a n d g r o u n d ) with n o loss of gain! If a load resistance is c o n n e c t e d to t h e out put node, the current 21 flows t h r o u g h it and thus determines die output voltage v . In the absence of a load resistance, t h e output voltage is d e t e r m i n e d b y the output current 2i a n d the output resistance of t h e circuit, as w e shall shortly see. id
0
x
mi
id
2
1
2
3
4
4
0
7.5.3 Differential Gain of the Active-Loaded MOS Pair As w e h a v e l e a r n e d in C h a p t e r 6, the output resistance r of t h e transistor plays a significant role in the operation of active-loaded amplifiers. Therefore, w e shall n o w take r into account and d e r i v e an expression for t h e differential gain v /v of t h e active-loaded M O S differential pair. Unfortunately, b e c a u s e the circuit is not s y m m e t r i c a l w e will not b e able to use the differential half-circuit technique. Rather, w e shall perform the derivation from first principles: W e will first find the short-circuit transconductance G and the output resistance R . Then, t h e g a i n will b e determined as G„,R . 0
vo
0
01
0
id
m
0
0
D e t e r m i n i n g the Transconductance G m F i g u r e 7.29(a) s h o w s t h e circuit p r e p a r e d for determining G . N o t e that w e h a v e short-circuited the output to g r o u n d in order to find G as i /v . A l t h o u g h t h e original circuit is n o t perfectly s y m m e t r i c a l , w h e n t h e output is shorted to ground, the circuit b e c o m e s almost symmetrical. T h i s is b e c a u s e t h e v o l t a g e b e t w e e n t h e drain of Q and g r o u n d is v e r y small. T h i s in turn is d u e to the l o w resistance b e t w e e n that n o d e a n d g r o u n d w h i c h is almost equal to l/g . T h u s , w e c a n i n v o k e s y m m e t r y a n d a s s u m e that a virtual ground will appear at the source of £>i and Q and in this w a y obtain the equivalent circuit s h o w n in Fig. 7.29(b). H e r e w e h a v e r e p l a c e d the d i o d e - c o n n e c t e d transistor Q b y its equivalent resistance {(l/g )\\r ].The v o l t a g e v that d e v e l o p s at t h e c o m m o n - g a t e line of the m i r r o r c a n b e found as m
0
m
id
x
m3
2
3
m3
o3
*
g3
g3
= -gJ^](^\\r V
w h i c h for t h e u s u a l c a s e of r
0V (c)
o l
and r
o3
2
o
3
\\r
o
l
)
7V^ 3
> (l/g )
(7.139) J
M
r e d u c e s to
m3
= -I
(7 140)
Sm3 Si
a C
e
1
d e d
M
S d i f f e r e n t i a l
P a k
( b )
T
h
e
S i n e IfL^ ^ r ; « ° ™ * equffibrium assuming perfect matchmg. (c) The circuit with a differential input signal applied, neglecting the r of all transistors. 0
-l7l(fl
-
This v o l t a g e controls t h e drain current* 3 of N o t e that the = Q resulting in a current of g v . ground at the output n o d e causes the currents in r and r to b e zero. T h u s the output current 4
o2
m4
o4
g3
LOAD
7.5
CHAPTER 7
DIFFERENTIAL
A N D MULTISTAGE
T H E DIFFERENTIAL AMPLIFIER WITH ACTIVE
AMPLIFIERS
^
l/gm3
< I-A R
QA
r 3< 0
A;
"«3
1 /2J . gml id/2y V
!
o - V /2
+ J2
id
(b)
Q:
r
o2.
01
1
O
V
P
R.
]^
FIGURE 7 . 3 0 Circuit for determining * . The circled numbers indicate the order of the analysis steps. 0
FIGURE 7 . 2 9 Determining the short-circuit transconductance G,„ = i /v differential pair. 0
of the active-loaded MOS
id
can n o w use E q . (6.101) to determine R R2
= '"
0
/„ will b e l
n
v
—
g4 3 m
+ Sm2[
g
b y substituting g
o2
(7.141)
2
which for g
ml
= g
= g
m2
m
and g r m2
o2
+ (l+g
o2
f f l 2
r
o 2
s
)(l/g
m l
ml
to obtain
)
> 1 yields R2
s 2r
0
Substituting for v
= 0 and R = l/g
mb
(7-144)
o 2
from (7.140) gives
g3
Returning to the circuit in F i g . 7.30, w e c a n w r i t e at t h e o u t p u t n o d e l
= 1+ 1+
x
N o w , since g
m3
= g
and g
m4
= g
ml
m2
= g , the current i b e c o m e s m
0
=
2
i
2\
+
' o4
Substituting for R
= 2 ^ + ^ R2 o4 r
0
from E q . (7.144) w e obtain
o2
from w h i c h G „ is found to b e G
m
(7.142)
—
T h u s the short-circuit t r a n s c o n d u c t a n c e of the circuit is e q u a l to g
m
of e a c h of t h e t w o tran
l%
m
w o u l d b e equal to
= -
0
R
0
F i g u r e 7.30 s h o w s the circuit for determining
a
2
exiting
h
at t h e drain to feed the Q - Q mirror. S i n c e for the d i o d e - c o n n e c t e d transistor Q , l/g o3
R
r \\r o2
(7.145) o4
M
R . O b s e r v e that t h e current i that enters Q m u s t exit at its source. It then enters Q m u c h smaller than r ,
=
o 4
Thus,
g /2.
Determining the Output Resistance 3
r
o2
sistors of the differential pair. H e r e w e s h o u l d n o t e that in t h e a b s e n c e of t h e c u r r e n t - m i r r o r action, G
r
4
3
m o s t of t h e current
m3
is
will flow into t h e drain of Q . T h e mirror
w h i c h is an intuitively a p p e a l i n g result. D e t e r m i n i n g t h e D i f f e r e n t i a l G a i n , E q u a t i o n s (7.142) a n d (7.145) c a n b e c o m b i n e d to obtain t h e differential gain A
d
as
3
r e s p o n d s b y p r o v i d i n g an equal current i in the drain of Q . It n o w r e m a i n s to d e t e r m i n e the
A s-2-
4
d
= GR m
='"g (r ]\r )
0
m
o2
(7.146)
o4
relationship b e t w e e n / a n d v . F r o m Fig. 7.30 w e see that x
i = where R
o2
is the output resistance of Q . N o w , 0 2
(7.143)
vJRo2 2
For the case r
o2
=r
o4
= r„, "-d
is a C G transistor and has in its source lead the
1 ^gm o J
input resistance of Q . T h e latter is connected in the C G configuration with a small resistance in x
the drain (approximately equal to l/g ), m3
thus its input resistance is approximately l/g \m
We
w h e r e A is t h e intrinsic gain of t h e M O S transistor. 0
AQ
^
(7.147)
LOAD
732
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
THE DIFFERENTIAL AMPLIFIER WITH ACTIVE L O A D
7.5
AMPLIFIERS
Transistor r
o4
»•
C-
senses this v o l t a g e a n d h e n c e p r o v i d e s a drain current i , 4
(7.151) Now, at t h e o u t p u t n o d e the c u r r e n t difference b e t w e e n i a n d i p a s s e s t h r o u g h r 4
2
o4
(since
R , P- r ) to provide v , 0
o4
0
V
0
Vicm O
I
1
I
Vlrn, °
ov
ic
r
=
(i -i ) o4 4
11
0 «
2
1 i [
11
~—II I o3
m4
_
|
I
2
?m3
Substituting for i
x
and i
2
f r o m E q . (7.148) a n d setting g
= g
m3
m4
w e obtain after s o m e
straightforward m a n i p u l a t i o n s A
1
=^2-
' oA l
2Rss
FIGURE 7 . 3 1
Usually, g r
W
(a)
m3
> 1 and r
o3
o3
(7.152)
+g,nir
o3
= r , yielding o4
Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain.
4
(7.153)
i
=
2g,„?Rt; ~ 6m3 SS lv
7.5.4 Common-Mode Gain and CMRR
Since R
A l t h o u g h its o u t p u t is single-ended, t h e a c t i v e - l o a d e d M O S differential amplifier h a s a low
ratio ( C M R R ) c a n n o w b e o b t a i n e d b y utilizing E q s . (7.146) a n d (7.153),
SS
is usually large, at least e q u a l to r , A 0
cm
will b e small. T h e c o m m o n - m o d e rejection
c o m m o n - m o d e gain and, c o r r e s p o n d i n g l y , a h i g h C M R R . F i g u r e 7.31(a) shows the circuit with v
resistance R
m
equally b e t w e e n Q and Q as
SS
X
2
o2
o4
M3
SS
A.,
of the bias-current source I. A l t h o u g h t h e circuit is not symmetrical and hence
SS
w e c a n n o t use the c o m m o n - m o d e half-circuit, w e can split R
(7.154)
ig (r \\r )][2g R ]
CMRR =
a p p l i e d a n d with the p o w e r supplies e l i m i n a t e d except, of course, for the output
icm
which for r
o2
=r
o4
= r and g 0
m3
=g
m
simplifies to
s h o w n in F i g . 7.3 l b . It c a n n o w b e seen that e a c h of Q a n d Q is a C S transistor with a large X
source d e g e n e r a t i o n resistance 2R .
2
d e t e r m i n e t h e currents i a n d i that result from the application of an i n p u t signal v . x
2
is u s u a l l y m u c h larger than \/g
SS
m
the signals at the s o u r c e terminals will b e a p p r o x i m a t e l y e q u a l to v . icm
and r
source / that features a h i g h o u t p u t resistance. S u c h circuits i n c l u d e t h e c a s c o d e current source and the W i l s o n current source studied in S e c t i o n 6.12.
2R ss
2
S
SS
and 7.12 An active-loaded M O S differential amplifier of the type shown in Fig. 7.28(a) is specified as follows:
Ri
= Ki
0
= r
o2
SS
W e observe that to obtain a l a r g e C M R R w e select an i m p l e m e n t a t i o n of the biasing current
2
oX
gmb •= 0 y i e l d s
oX
M
Also, the effect of r
x
T h e o u t p u t r e s i s t a n c e of e a c h of Q and Q is g i v e n b y E q . (6.101) w h i c h for R = 2R
where r
0
(7M48)
h = h =
X
m
of each of Q and Q ,
c a n b e s h o w n to b e negligible. T h u s , w e c a n write
o2
(7.155)
(g r )(g R )
Alter
icm
natively, w e o b s e r v e that since 2R
CMRR =
W e c a n u s e the f o r m u l a s derived in Section 6.9.1 to
SS
= r and g 0
=g
mX
m2
= r + 2R 0
rn
ol
3
o3
than r . T h u s , w e c a n easily n e g l e c t R
II (l/g )). m3
and R
oX
o2
of the drain n o d e s a n d ground. T h e current i is p a s s e d through ((l/g 3) x
ss
= g . N o t e that R
resistance i n t r o d u c e d b y Q , n a m e l y (r o4
+
m
(7.149)
2g r R,ss m
0
(W/L\
= 100, (W/L)
will b e m u c h greater than the parallel Similarly, R
o2
M
Calculate G . R „ . A , \Aj.. M
2
= 200, li„C
P
d
= 2 / < Q , = 0.2 m A A ' , V p
ALL
= \ V ! AP
= 20 V, 7 = 0.8 m A , R
and C M R R .
Ans. 4 m A / V ; 25 k Q ; 100 W V ; 0.005 VJV; 20,000 or 86 dB
will b e m u c h greater
in finding t h e total resistance b e t w e e n each
7.5.5 The Bipolar Differential Pair with Active Load || r ) o3
a n d as a result p r o d u c e s a voltage
v, g3
The bipolar version of the a c t i v e - l o a d e d differential p a i r is s h o w n in Fig. 7.32(a). T h e circuit structure and o p e r a t i o n are very similar to t h o s e of its M O S counterpart e x c e p t that h e r e w e have to c o n t e n d w i t h the effects of finite B a n d the resulting finite i n p u t r e s i s t a n c e at t h e
SS
= 25 k Q .
733
7 3 4
CHAPTER 7
DIFFERENTIAL A N DMULTISTAGE
T H EDIFFERENTIAL AMPLIFIER WITH
7.5
AMPLIFIERS
ACTIVE
that the voltage signal at the collector of Q will b e small as a result of t h e l o w resistance
Vcc
A
between that n o d e a n d ground (approximately equal to r ). T h e voltage v e3
r
"b3 =
b3
c a n b e found from
r
-8ml(^Yy ^\\ o3\\''„l\\r ) K4
v 2
t h e collector current ofmif-J^l Q will b e
Since v 4 = v , b
b3
(7-156)
4
v
V;.
= -g g r \
M
mA
nl
e3
(7.157)
2
The output current i„ c a n b e found from a n o d e e q u a t i o n at t h e o u t p u t as (V
-f)-g 4v 4 m
(7-158)
b
Using E q . (7.157) w e obtain i
0
= Sm2(y) + S«4Smirrf(y)
Since all devices are o p e r a t i n g at t h e s a m e bias current, g
ml
=g
(7-159) m2
=g
m4
= g , where m
7/2
(7.160)
V
T
and r
e3
= a /g 3
= a/g
m3
m
= l/g . m
T h u s , for G , E q . (7.159) yields m
G
= g
m
(7.161)
m
which is identical t o t h e result found for t h e M O S pair. N e x t w e d e t e r m i n e t h e o u t p u t resistance of t h e amplifier utilizing t h e equivalent circuit shown in F i g . 7 . 3 2 ( c ) . W e u r g e t h e r e a d e r t o carefully e x a m i n e this circuit a n d t o n o t e that the analysis is v e r y similar t o that for t h e M O S pair. T h e o u t p u t r e s i s t a n c e R
o2
of transistor
Q can b e f o u n d u s i n g E q . (6.160) b y n o t i n g that t h e r e s i s t a n c e R i n t h e emitter of Q is 2
e
2
approximately e q u a l t o r , thus ei
R2 0
R„ = base,
id
r^)]
el
+g r ) m2
el
= 2r
(7.162)
o2
FIGURE 7 . 3 2 (a) Active-loaded bipolar differential pair, (b) Small-signal equivalent circuit for deter 0
m2
o2
(c)
m
o2
= r (l
= i
mining the transconductance G = i /v .
= r [l+g {r \\
(c) Equivalent circuit for determining the output resistance
where w e m a d e u s e of t h e fact that c o r r e s p o n d i n g p a r a m e t e r s of all four transistors are equal. T h e current / c a n n o w b e found as
'IT-
i
= ^
= ^
L
(7-163)
F o r t h e tirne being, however, w e shall ignore t h e effect of finite B o n t h e dc bias of the
four transistors a n d assume that in equilibrium all transistors are operating at a dc current of 1/2.
and t h e current i c a n b e o b t a i n e d from a n o d e e q u a t i o n at t h e o u t p u t as x
i = 2 i +—
Differential Gain T o obtain an expression for the differential gain, w e apply an input differ ential signal v
id
as shown in the equivalent circuit in Fig. 7.32(b). N o t e that t h e output is con
nected t o ground in-order to determine t h e overall short-circuit transconductance G = m
= — + —
Thus,
i„/v . id
Also, as in the M O S case, w e h a v e a s s u m e d that the circuit is sufficiently balanced so that a vir
R — ~r — o2 II o 4 r
0
tual ground develops o n the c o m m o n emitter terminal. This assumption is predicated o n the fact
r
(7.164)
THE DIFFERENTIAL AMPLIFIER WITH ACTIVE
7.5
CHAPTER 7
737
LOAD
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
„„ b e shown that the output resistances of Q a n d Q , R
I t
x
This e x p r e s s i o n s i m p l y says that the o u t p u t r e s i s t a n c e of the amplifier is equal to the parallel
he neglected. T h e n , the voltage v
b3
e q u i v a l e n t of the output resistance of the differential p a i r a n d t h e o u t p u t resistance of the
Sad
2
and R ,
ol
are very large and h e n c e
o2
at the c o m m o n b a s e connection of Q and Q c a n be 3
4
by multiplying i b y the total resistance b e t w e e n the c o m m o n b a s e n o d e and ground as x
current mirror; a result identical to that o b t a i n e d for the M O S pair. E q u a t i o n s (7.161) a n d (7.164) c a n n o w b e c o m b i n e d to obtain t h e differential gain,
= -j/^-llr^lKsllr J
V b 3
169
V?m3
V- ^
A
d
=—
= GR m
0
= g (r \\r ) m
o2
a n d since r
o2
= r
[ n
= r , w e c a n simplify E q . (7.165) to
o4
= \g r
d
m
m
0
p o n s e to v
transistor Q p r o v i d e s a collector current g v .
b3
4
m4
(7.166)
0
A l t h o u g h this e x p r e s s i o n is identical to that found for t h e M O S circuit, the gain here is much larger b e c a u s e g r
r e s
A t the o u t p u t n o d e w e
b3
have
a
A
Z
0.165)
o4
Vjd
for the B J T is m o r e t h a n an o r d e r of m a g n i t u d e greater than g r m
0
v
= (-g
0
Substituting for v
b3
of a
v
m 4
7 17
-i )r
b 3
2
( - °)
o 4
from E q . (7.169) a n d for i a n d i f r o m E q . (7.168) gives x
A
=
' oA
— ^icm
M O S F E T . T h e d o w n s i d e , h o w e v e r , lies in t h e l o w i n p u t r e s i s t a n c e of B J T amplifiers.
2
^(T-IKS II o 3 II * 4 r
2R EE
r
m3
Indeed, t h e e q u i v a l e n t circuit of Fig. 7.32(b) indicates that, as expected, the differential input r e s i s t a n c e of t h e differential amplifier is e q u a l to 2r , %
<%3
R
= 2r
id
(7.167)
n
(7.171)
2R
t
r*4
' K3
in sharp contrast to the infinite input resistance of the M O S amplifier. T h u s , while the voltage gain realized in an active-loaded amplifier stage is large, w h e n a subsequent stage is connected
r o3
'r„A TtA
where w e h a v e a s s u m e d g
m3
= g . m4
N o w , for r
f
o3
= r
n4
and r
n3
> r ,
o3
K3
r , E q . (7.171) gives K4
to the output, its inevitably l o w input resistance will drastically r e d u c e the overall voltage gain. Common-Mode
Gain and
CMRR
The common-mode gain A
cm
a n d the c o m m o n - m o d e A
rejection ratio ( C M R R ) c a n b e found following a p r o c e d u r e identical to that utilized in the
^21 c m
~
2R EE
M O S case. F i g u r e 7.33 s h o w s the circuit p r e p a r e d for c o m m o n - m o d e signal analysis. T h e
8m3 +
—
collector currents of Q a n d Q are g i v e n b y x
2
(7.172) ii = i = - ^ 2 2 2R 2
2R
(7.168)
EE
B
BR
3
3
EE
1
EE
Using A from E q . (7.165) e n a b l e s u s to obtain t h e C M R R as d
\A \ C M R R = rr-^i \A d
,
= g (r m
o2
,, JP REE II r Y 3
' oA
r
For r."o2 ~ oA r
(7.173)
o4
'o'
CMRR =
\fi g Rt 3
(7.174)
m
from w h i c h w e observe that to obtain a large C M R R , the circuit i m p l e m e n t i n g the bias current source should h a v e a l a r g e o u t p u t r e s i s t a n c e R . EE
T h i s is p o s s i b l e w i t h , say, a W i l s o n current
mirror (Section 6.12.3).
7 13 For the active-loaded BJT differential amplifier let / = 0.8 mA, V, = 100 V, and B= 160 Find G
K„.
A,, and R, . If the bias current source is implemented with a simple npn current m u m , , i m d K , A „ „ . d
and CMKK. Ans. 16 mA/V: 125 k£2; 2000 V/V; 20 kil: 125 kQ; - 0 . 0 1 2 5 V/V; 160,000 or 104 dB FIGURE 7 . 3 3 Analysis of the bipolar active-loaded differential amplifier to determine the commonmode gain.
Eh
738
} CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
THE DIFFERENTIAL AMPLIFIER WITH
7.5
To r e d u c e this o u t p u t c u r r e n t t o z e r o , an i n p u t v o l t a g e V
os
ACTIVE
h a s to b e a p p l i e d w i t h
value of Ai G„, Substituting for Ai from Eq. (7.177) and for G„ — 8m
=
(ocI/2)/V , T
w e obtain for the
input offset v o l t a g e the expression
al/Pp
V,OS
2V
7
(7.178)
~aI/2V
T
As an e x a m p l e , for B = 5 0 , V — - 1 m V . T o r e d u c e V , an i m p r o v e d c u r r e n t m i r r o r such as t h e W i l s o n c i r c u i t s t u d i e d in S e c t i o n 6.12 s h o u l d b e u s e d . S u c h a c i r c u i t p r o v i d e s the a d d e d a d v a n t a g e of i n c r e a s e d o u t p u t r e s i s t a n c e a n d h e n c e v o l t a g e g a i n . H o w e v e r , to realize t h e full a d v a n t a g e of t h e h i g h e r o u t p u t r e s i s t a n c e of t h e a c t i v e load, t h e o u t p u t resistance of t h e differential p a i r should b e raised b y utilizing a c a s c o d e stage. F i g u r e 7.35 shows s u c h an a r r a n g e m e n t : A f o l d e d c a s c o d e s t a g e f o r m e d b y pnp t r a n s i s t o r s Q a n d Q is utilized to r a i s e t h e o u t p u t r e s i s t a n c e l o o k i n g i n t o t h e c o l l e c t o r of Q t o B r . A Wilson m i r r o r f o r m e d b y t r a n s i s t o r s Q , Q , a n d Q is u s e d t o i m p l e m e n t t h e a c t i v e load. F r o m S e c t i o n 6.12.3 w e k n o w t h a t t h e o u t p u t r e s i s t a n c e of t h e W i l s o n m i r r o r (i.e., looking into t h e c o l l e c t o r of Q ) is B (r /2). T h u s t h e o u t p u t r e s i s t a n c e of t h e amplifier P
FIGURE 7 . 3 4 The active-loaded BJT differential pair suffers from a systematic input offset voltage resulting from the error in the current-transfer ratio of the current mirror.
os
os
3
4
S y s t e m a t i c I n p u t O f f s e t V o l t a g e In addition to the r a n d o m offset voltages that result from the m i s m a t c h e s inevitably present in the differential amplifier, the active-loaded bipolar differential pair suffers from a systematic offset voltage. This is d u e to the error in the current transfer ratio of the current-mirror l o a d caused b y t h e finite f3 of t h e pnp transistors that m a k e up the mirror. T o see h o w this c o m e s about, refer to Fig. 7.34. H e r e t h e inputs are g r o u n d e d and the transistors are a s s u m e d to b e perfectly m a t c h e d . T h u s , t h e bias current I will divide equally b e t w e e n Q and Q w i t h the result that their t w o collectors c o n d u c t equal currents of aI/2. T h e collector current of Q is fed to t h e input of t h e current mirror. F r o m Section 6.3 w e k n o w that the current-transfer ratio of the mirror is l
4
5
5
5
6
4
o4
7
a5
2
x
1
(7.175)
w h e r e B is the value of B of the pnp transistors Q and Q . T h u s the collector current of Q will b e P
3
h =
4
ai/2
4
(7.176)
H
w h i c h does n o t exactly balance t h e collector current of Q . It follows that the current differ ence Ai will flow into t h e output terminal of the amplifier w i t h 2
^ . _ ai
=
3
0—4:%
al/2
ai
2/B
2
1+ 2
P
k
? -VEE
(7.177)
FIGURE 7 . 3 5 An active-loaded bipolar differential amplifier employing a folded cascode stage (Q and g ) and a Wilson current mirror load (Q , Q , and Q ). 3
5
6
7
4
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
FREQUENCY
7.6
RESPONSE OF T H E DIFFERENTIAL AMPLIFIER
_ >
is g i v e n b y
/V
o 4
The transconductance G remains equal to g gain b e c o m e s m
m
I I Ps^r
(7.179)
of Q a n d Q . T h u s t h e differential voltage x
2
V
o-f
0
/V
II
o 4
o
P ^r
J2i
If
(7.180)
5
-oy
0
I'
S
w h i c h c a n b e very large. F u r t h e r e x a m p l e s of i m p r o v e d - p e r f o r m a n c e differential amplifiers will b e studied in C h a p t e r 9.
^
ss
~~ [Rss II Q s ]
-°V /2 B
Qs
1
o
Z
^BIAS
Qi
Qs
2Rc.
2
V /2 id
7.14 Find G,„ and R , tli
/?„,, R , and A for the differential amplifier in Fig. 7.35 under the following condi n
(a)
d
(b)
(c)
tions: / = 1 in A. Bp = 50, By = 0 0 - and V = 100 V. 1
A
FIGURE 7 . 3 6 (a) A resistively loaded MOS differential pair with the transistor supplying the bias current explicitly shown. It is assumed that the total impedance between node 5 and ground, Z , consists of a resistance R in parallel with a capacitance C . (b) Differential half-circuit, (c) Common-mode half-circuit.
5
Ans. 20 mA/V; 10 M Q ; 10 M Q ; 5 M Q : 1 0 V/V or 100 dB
ss
ss
ss
7.6 FREQUENCY RESPONSE OF THE DIFFERENTIAL AMPLIFIER In this s e c t i o n w e s t u d y t h e f r e q u e n c y r e s p o n s e of t h e differential amplifier. W e will con sider t h e v a r i a t i o n w i t h f r e q u e n c y of b o t h t h e differential g a i n a n d t h e c o m m o n - m o d e gain and h e n c e of t h e C M R R . W e will rely heavily o n t h e study of frequency r e s p o n s e of singlee n d e d amplifiers p r e s e n t e d in C h a p t e r 6. A l s o , w e will only c o n s i d e r M O S circuits; t h e b i p o l a r c a s e is a straightforward e x t e n s i o n , as w e s a w o n a n u m b e r of o c c a s i o n s in C h a p t e r 6.
7.15 A M O S F E T differential amplifier such as that in Fig. 7.36(a) is biased with a current 1 = 0.8 mA. T h e transistors have W/L = 100, A', = 0.2 mA/V . V = 2 0 V, C = 5 0 IF, C,, = 10 fF, and C = 10 fF. T h e drain resistors are 5 k Q each. Also, there is a 100-fF capacitive load between each drain and ground. 2
A
(a) Find V
ov
? s
d
db
and g for each transistor. m
(b) Find the differential gain A . d
(c) If the input signal source has a small resistance A\ and thus die frequency response is determined primarily by tire output pole, estimate the 3-dB frequency f . (Hint: Refer to Section 6.6.5 and specifi cally to Eq. 6.79.) ia
7.6.1 Analysis of the Resistively Loaded MOS Amplifier W e b e g i n w i t h t h e basic, resistively l o a d e d M O S differential pair s h o w n i n F i g . 7.36(a). N o t e that w e h a v e explicitly s h o w n t h e transistor Q that supplies t h e bias current I. A l t h o u g h w e are s h o w i n g a dc bias voltage V at its gate, usually Q is part of a current mirror. T h i s detail, h o w e v e r , is of n o c o n s e q u e n c e to o u r p r e s e n t n e e d s . M o s t importantly, w e are interested in t h e total i m p e d a n c e b e t w e e n n o d e S a n d g r o u n d , Z . A s w e shall shortly see, this i m p e d a n c e plays a significant role in d e t e r m i n i n g t h e c o m m o n - m o d e gain a n d the C M R R of the differential amplifier. R e s i s t a n c e R is simply t h e output resistance of current source Q . C a p a c i t a n c e C is t h e total c a p a c i t a n c e b e t w e e n n o d e S a n d g r o u n d a n d includes C a n d C of Q , as well as C , a n d C . T h i s c a p a c i t a n c e c a n b e significant, especially if w i d e transistors are u s e d for Q , Q a n d Q . s
mAS
s
H
(d) If. in a different situation, the amplifier is fed symmetrically with a signal source of 20 kQ resistance (i.e.. 10 k Q in series with each gate terminal), use the open-circuit lime-constants method to estimate/,,. (Hint: Refer to Section 6.6.2 and specifically to Eqs. 6.57 and 6.58.) Ans. du 0.2 V, 4 mA/V: ' h i | X ? V/V: Id 2QI MH>: 01) 53.7 MHz
ss
ss
s
db
ss
gd
s
sbl
s
sb2
h
2
T h e differential half-circuit s h o w n in Fig. 7.36(b) c a n b e used to determine the frequency d e p e n d e n c e of the differential gain V /V . I n d e e d t h e gain function A (s) of the differential amplifier will b e identical t o t h e transfer function of this c o m m o n - s o u r c e amplifier. W e studied the frequency r e s p o n s e of the c o m m o n - s o u r c e amplifier at great length in Section 6.6 and will n o t r e p e a t this material here. 0
id
d
T h e c o m m o n - m o d e half-circuit is s h o w n in l i g . 7.36(c). A l t h o u g h this circuit h a s other capacitances, n a m e l y C , C , a n d C of t h e transistor i n addition t o other stray capaci tances, w e h a v e c h o s e n t o s h o w only C /2. T h i s is b e c a u s e ( C / 2 ) together with (2R ) forms a real-axis zero in t h e c o m m o n - m o d e gain function at a frequency m u c h l o w e r than those of t h e other poles a n d zeros of t h e circuit. This z e r o t h e n d o m i n a t e s t h e frequency dependence of A a n d C M R R . gs
gd
db
ss
s s
SS
cm
If the output of t h e differential amplifier is t a k e n single-endedly, t h e n the c o m m o n - m o d e gain of interest is V A^ . M o r e typically, t h e output is t a k e n differentially. Nevertheless, ocm
icm
7 4 1
7 4 2
f
':'
CHAPTER 7
DIFFERENTIAL A N DMULTISTAGE
as w e h a v e seen in Section 7.2, V /V ocm
7.6
AMPLIFIERS
FREQUENCY RESPONSE O FT H E DIFFERENTIAL
AMPLIFIER
still plays a major role in determining the common-
icm
m o d e gain. T o b e specific, consider w h a t h a p p e n s w h e n t h e output is taken differentially and there is a m i s m a t c h AR b e t w e e n t h e t w o drain resistances. T h e resulting c o m m o n - m o d e gain D
w a s f o u n d in S e c t i o n 7.2 t o b e (Eq. 7.51) ( R
\AR
D
A
-
w h i c h is simply t h e p r o d u c t of V /V ocm
D
(7 181
- )
i2^h7
=
a n d t h e p e r - u n i t m i s m a t c h (AR /R ).
icm
D
Similar
D
e x p r e s s i o n s c a n b e found for t h e effects of other circuit m i s m a t c h e s . T h e important point to note is that t h e factor R /(2R ) D
d e p e n d e n c e of A
cm
is always present in these expressions. Thus, the frequency
SS
c a n b e obtained b y simply r e p l a c i n g R
by Z
ss
ss
in this factor. Doing so
for t h e e x p r e s s i o n in E q . (7.181) gives A
(
)
1
2
^SS
\A \ (dB) d
'AR ^
- X =-N
A
D
R
-
D
J
-AR ~] D
R
*
D
J
fAR
D
yi+sc R ) SS
2 R
from w h i c h w e s e e that A
cm
(7.182)
SS
s s V DR
acquires a zero o n t h e n e g a t i v e real-axis of t h e s-plane with
frequency co?,
= 77-V ^ss ss
(0
Z
(7-183)
K
or in hertz,
f
z
= ®2 =
(7.184)
1 R
As mentioned above, usually f
z
2k 2kCss ss is m u c h l o w e r t h a n t h e frequencies of t h e other poles and
—6 d B / o c t a v e
zeros. A s a result, t h e c o m m o n - m o d e gain i n c r e a s e s at t h e rate of + 6 d B / o c t a v e (20 d B / d e c a d e ) starting at a relatively l o w frequency, as i n d i c a t e d in F i g . 7.37(a). O f course, A
cm
-12 dB/octave
drops off at h i g h frequencies b e c a u s e of t h e other p o l e s of t h e c o m m o n - m o d e half-circuit. It is, h o w e v e r , f that is significant, for it is t h e frequency at w h i c h t h e C M R R of the differential z
amplifier b e g i n s t o d e c r e a s e , as indicated in F i g . 7.37(c). N o t e that if b o t h A a n d A d
cm
are fz
e x p r e s s e d a n d plotted in d B , then C M R R in d B is s i m p l y t h e difference b e t w e e n A and A . d
cm
A l t h o u g h in t h e foregoing w e c o n s i d e r e d only t h e c o m i t i o n - m o d e gain resulting from an R
D
m
m o d i f y i n g E q . 7 . 6 4 b y replacing R
ss
mismatch,
b y Z , and so on. ss
/ ( l o g scale) (c)
m i s m a t c h , it s h o u l d b e o b v i o u s that t h e results apply t o t h e c o m m o n - m o d e gain resulting
from a n y other m i s m a t c h . F o r instance, it applies e q u a l l y w e l l t o t h e c a s e of a g
fa /
FIGURE 7 . 3 7 Variation of (a) common-mode gain, (b) differential gain, and (c) common-mode rejection ratio with frequency.
B e f o r e leaving this section, it is interesting t o p o i n t o u t a n i m p o r t a n t trade-off found in the d e s i g n of t h e current-source transistor Q : In o r d e r t o operate this current source with a
trade-off b e t w e e n t h e n e e d t o r e d u c e t h e d c v o l t a g e across Q a n d t h e n e e d t o k e e p t h e
small V
C M R R r e a s o n a b l y h i g h at h i g h e r frequencies.
s
DS
(to c o n s e r v e t h e already l o w V ), DD
w e desire to operate t h e transistor at a low
o v e r d r i v e v o l t a g e V . F o r a g i v e n v a l u e of t h e current I, h o w e v e r , this m e a n s using a large ov
W/L ratio (i.e., a w i d e transistor). This in torn increases C
ss
a n d h e n c e lowers f
z
with t h e result
that t h e C M R R deteriorates- (i.e., decreases) at a relatively l o w frequency. T h u s there is a
s
T o a p p r e c i a t e t h e n e e d for h i g h C M R R at h i g h e r frequencies, c o n s i d e r t h e situation illustrated in F i g . 7.38: W e s h o w t w o stages of a differential amplifier w h o s e p o w e r - s u p p l y voltage V
DD
is c o r r u p t e d w i t h high-frequency noise. S i n c e t h e quiescent voltage at e a c h of
7 4 4
.
CHAPTER 7
DIFFERENTIAL A N DMULTISTAGE
FREQUENCY RESPONSE O F T H EDIFFERENTIAL AMPLIFIER
7.6
AMPLIFIERS
+VJ2
t
?
FIGURE 7 . 3 8 The second stage in a differential amplifier is relied on to suppress high-frequency noise injected by the power supply of the first stage, and therefore must maintain a high CMRR at higher frequencies.
FIGURE 7 . 3 9 (a) Frequency-response analysis of the active-loaded MOS differential amplifier, (b) The overall transconductance G,„ as a function of frequency.
Capacitance C includes C , C , C , C as well as a n actual load c a p a c i t a n c e and/or the input c a p a c i t a n c e of a s u b s e q u e n t stage (C ), L
the drains of g i a n d Q is [V - (I/2)R ], w e see that v a n d v will h a v e the same highfrequency noise as V . T h i s high-frequency noise then constitutes a c o m m o n - m o d e input signal to t h e s e c o n d differential stage, f o r m e d b y Q a n d Q . If the s e c o n d differential stage is perfectly m a t c h e d , its differential output voltage V should b e free of high-frequency noise. H o w e v e r , in practice there is n o such thing as perfect m a t c h i n g a n d t h e second stage will h a v e a finite c o m m o n - m o d e gain. F u r t h e r m o r e , b e c a u s e of the zero formed b y R and C of the s e c o n d stage, t h e c o m m o n - m o d e gain will increase w i t h frequency, causing some of t h e noise t o m a k e its w a y to V . W i t h careful design, this u n d e s i r a b l e c o m p o n e n t of V can b e k e p t small. 2
DD
D
Dl
gd2
db4
gd4
x
m
DD
3
db2
CL
+
— Cgd2
C
+
DB2
I + C' rlUA +
C
g
C
(7.186)
v
4
0
ss
ss
0
0
These t w o c a p a c i t a n c e s primarily d e t e r m i n e the d e p e n d e n c e of the differential gain of this amplifier o n frequency. As indicated in Fig. 7.39(a) the input differential signal V is applied in a balanced fashion. Transistor Q will conduct a drain current signal of g V /2, which flows through the diodeconnected transistor Q a n d thus through the parallel combination of (l/g ) and C , where we have neglected the resistances r and r which are m u c h larger than (1 / g ) , thus id
x
m
id
3
m3
0]
o3
m
m 3
(7.187)
V. 5
EXERCISE
m3 + sC,„
In response t o V , transistor Q conducts a drain current I , o3
7.16 The differential amplifier specified in bxerctse 7.15 has R frequency of the C M R R .
= 2 5 k Q and C
ss
iS
4
d4
= 0.4 p h bind the 3-dB ^¿4
-
g,»3 ~F sC „ T
Ans. 15." \ Since g
m3
- g , this equation r e d u c e s t o m4
g yy2 m
(J.li
c 7.6.2 Analysis of the Active-Loaded MOS Amplifier
§m3 '
W e n e x t c o n s i d e r the frequency r e s p o n s e of t h e c u r r e n t - m i r r o r - l o a d e d M O S differential-pair circuit studied in Section 7 . 5 . T h e circuit is s h o w n in F i g . 7.39(a) w i t h t w o capacitances indicated: C , w h i c h is t h e total c a p a c i t a n c e at t h e input n o d e of t h e current mirror, a n d C , which is t h e total c a p a c i t a n c e at t h e output n o d e . C a p a c i t a n c e C is m a i n l y f o r m e d b y C and C b u t also includes C , C , a n d C , m
L
m
gs4
? d l
m
N o w , at the o u t p u t n o d e t h e total output current is l
o
L
— d4
Id2
g Vid/2 m
db3
+
C
db3
+C
gs3
+
(7.185)
C
gs4
, „ XV /2) id
1 Cm ~ Cgdl + Cdbl
+
gs3
+ 5 -
(7.189)
I
7 4 5
CHAPTER 7
DIFFERENTIAL
A N D MULTISTAGE
AMPLIFIERS
w h i c h flows t h r o u g h t h e parallel c o m b i n a t i o n of R
0
V
= r
a2
\\ r
a n d C , thus
o4
w
L
r
u
c
(7.190) + sC,
FREQUENCY
RESPONSE OF T H E DIFFERENTIAL
AMPLIFI
n
to gm' is double the value available without the current mirror). N o w , at high frequen cies C acts as a short circuit causing V to b e zero and h e n c e I will b e zero, reducing G t o g /2. Thus, if t h e output is short-circuited to ground a n d the short-circuit transconductance G is plotted versus frequency, the plot will have t h e shape s h o w n in Fig. 7.39(b). m
1
= !„•
0
7.6
g3
d4
m
m
Substituting for I from E q . (7.189) gives D
1 +1 -+s C„
R
§m o
1 1+
sC,R„
Consider an active-loaded M O S differential amplifier of the type shown in Fig. 7.28(a). Assume that for all transistors, W/L = 7.2 /jm/0.36 m n , C = 2 0 fF, C = 5 fF, and C = 5 fF. Also, let ^C = 387 ztA/V , ii C = 86 pAN , V' = 5 V/p:m, \ V \ = 6 V//im. The bias current I = 0.2 mA, and the bias current source has an output resistance R = 25 k f l and an output capacitance C = 0.2 pF. In addition to the capacitances introduced by the transistors at the output node, there is a capacitance C of 25 fF. It is required to determine the low-frequency values of A , A , and CMRR. It is also required to find the poles and zero of A and the dominant pole of CMRR. gs
2
ox
W h i c h c a n b e m a n i p u l a t e d to yield
gd
db
2
p
ox
An
Ap
ss
1 +2g.s
1 1
+sC,R,
l+s-
ss
"m3 r
(7.191)
x
d
cm
d
Solution W e recognize t h e first factor o n the right-hand side as t h e d c gain of the amplifier. T h e second factor indicates that C and R form a p o l e w i t h frequency f , L
0
Pl
Since 7 = 0.2 mA, each of the four transistors is operating at a bias current of 100 jiA, Thus, for 6Ji and Q , 2
1 fpi
(7.192)
2nC,R„
2
100 = - x 387 x — x V 2 0.36
o
T h i s , of c o u r s e , is a n entirely e x p e c t e d result, a n d in fact this o u t p u t p o l e is often dominant, especially w h e n a i a r g e load c a p a c i t a n c e is present. T h e third factor o n the right-hand side of E q . (7.191) indicates that t h e capacitance C at t h e i n p u t of t h e current mirror gives rise to a p o l e w i t h frequency f ,
v
which leads to
m
V
= 0.16 V
nv
P2
Thus, (7.193)
f, P2
2nC
n
8m = g,nl = gml = and a z e r o w i t h frequency
f, z
r o l
=
r o 2
=
2
8m3 2nC„
fz
(7.194)
5x036 0.1
= =
l
g
k
1
2
5
m
A
/
V
Q
For Q and Q w e have 3
T h a t is, t h e z e r o frequency is twice that o f the p o l e . S i n c e C„, is approximately C
gs3
4
+
Cgs4 — 2 C 3 ,
2
100 = - x 86 x — x V 2 0.36
g s
fp2
=
2n(2C )
(7.195)
'-fj/2
gs3
0
Thus,
and
0.34 V, (7.196)
fz = fi
and
w h e r e f is t h e frequency at w h i c h t h e m a g n i t u d e of t h e high-frequency current gain of the M O S F E T b e c o m e s unity (see Sections 4.8 a n d 6.2). T h u s , t h e m i r r o r p o l e a n d zero occur at very high frequencies. N e v e r t h e l e s s , their effect c a n b e significant.
2x0.1 = 0.6 m A / V 0.34
T
It is interesting and useful to observe that the p a t h of the signal current produced b y (2i has a transfer function different from that of the signal current produced b y Q . It is the first signal that encounters C and experiences t h e mirror pole. This observation leads to an interesting view of the effect of C on the overall transconductance G of the differential amplifier: A s w e learned in Section 7.5, at low frequencies I is replicated b y the mirror Q - Q in the collector of Q as I , w h i c h adds to I&Xo provide a factor-of-2 increase in G (thus m a k i n g G,„ equal
5m3
' o3 -
om4
6 x 0.36 0.1
'o4
21.6 k Q
2
m
m
dl
4
d4
The low-frequency value of the differential gain can b e determined from
m
3
m
A
d
=
g (r \\r ) m
o2
o4
4
= 1.25(18||21.6) = 12.3 V/V
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
7.7
AMPLIFIERS
The low-frequency value of the c o m m o n - m o d e gain can b e determined from Eq. (7.153) as
MULTISTAGE AMPLIFIERS
î'jfjî
EXERCISE
1 K
m
2g R M3
S
1
7.17 A bipolar current-mirror-loaded differential amplifier is biased with a current source / = 1 niA. The transistors are specified to have |V'J = 100 V. The total capacitance at the output node is 2 pp. Find the dc value and the frequency of the dominant high-frequency pole of the differential voltage gain.
= -0.033 V/V
2 x 0.6 x 25
Ans. 20,11. V V: n.S M i l /
The low-frequency value of the C M R R can now be determined as C M R R = -l^L \A \
= i ^ - = 369 0.033
cm
7.7
or,
MULTISTAGE AMPLIFIERS
20 log 369 = 51.3 dB Practical transistor amplifiers usually consist of a n u m b e r of stages connected in c a s c a d e . I n T o determine the poles and zero of A we first compute the values of the two pertinent capac d
itances C and C . Using Eq. (7.185), m
L
Cm
=
addition to p r o v i d i n g gain, t h e first (or input) stage is usually r e q u i r e d to p r o v i d e a high input resistance in o r d e r to avoid loss of signal level w h e n t h e amplifier is fed from a high-
Cgdl + C
+C
dbl
+C
db3
resistance source. In a differential amplifier the input stage m u s t also provide large c o m m o n -
+ C
gs3
gs4
mode rejection. T h e function of the m i d d l e stages of a n amplifier c a s c a d e is to p r o v i d e t h e = 5 + 5 + 5 + 20 + 20 = 55 fF
bulk of t h e v o l t a g e gain. I n addition, t h e m i d d l e stages p r o v i d e s u c h other functions as the conversion of the signal from differential m o d e to single-ended m o d e (unless, of course,
Capacitance C is found using Eq. (7.186) as L
the amplifier output also is differential) and t h e shifting of t h e d c level of the signal in o r d e r =
C-L
Cgd2 + C
+C
db2
+C
gd4
db4
+C
to allow the output signal to swing both positive and negative. T h e s e t w o functions and others
x
will b e illustrated later in this section and in greater detail in Chapter 9.
= 5 + 5 + 5 + 5 + 2 5 = 45 fF
Finally, t h e m a i n function of the last (or output) stage of an amplifier is to p r o v i d e a low Now, the poles and zero of A can b e found from Eqs. (7.192) to (7.194) as
output resistance in order to avoid loss of gain w h e n a l o w - v a l u e d load resistance is c o n
d
nected to the amplifier. A l s o , the output stage should b e able to supply the current required by
1 f
p
l
2KC R
the load in a n efficient m a n n e r — t h a t is, w i t h o u t dissipating a n u n d u l y large a m o u n t of p o w e r
1 2nxC (r \\r )
for i m p l e m e n t i n g output stages, n a m e l y , t h e source follower and t h e emitter follower. It will
=
L
L
0
o2
in the output transistors. W e h a v e already studied o n e type of amplifier configuration suitable
oA
be s h o w n in C h a p t e r 14 that t h e source and emitter followers are not o p t i m u m from the p o i n t 1
of view of p o w e r efficiency and that other, m o r e appropriate circuit configurations exist for
15
2 ? r x 4 5 x 10" (18 [|21.6)10 : 360 M H z
output stages that a r e required t o supply large a m o u n t s of output p o w e r . In fact, w e will
3
encounter s o m e such output stages in t h e o p - a m p circuit e x a m p l e s studied in Chapter 9.
\.,
T o illustrate t h e circuit structure and the m e t h o d o f analysis of m u l t i s t a g e amplifiers, w e "-3
0.6x10F 2
2nC
2KX55X
m
fz
=
2f
P2
L
10
?
4
G
H
will present t w o e x a m p l e s : a t w o - s t a g e C M O S o p a m p a n d a four-stage bipolar o p a m p .
z
1 5
7.7.1 A Two-Stage CMOS Op Amp
= 3.5 GHz
Thus the dominant pole is that produced b y C at the output node. As expected, the pole and zero L
of the mirror are at m u c h higher frequencies.
SS
tion. T h e circuit utilizes t w o p o w e r supplies, w h i c h can range from +2.5 V for the 0.5-pm
tech
nology d o w n to +0.9 V for the 0.18-^tm technology. A reference bias current 1^ is generated
The dominant pole of the C M R R is at the location of the common-mode-gain zero introduced by C
Figure 7.40 s h o w s a popular structure for C M O S o p amps k n o w n as the t w o - s t a g e c o n f i g u r a
and R , that is,
either externally or using on-chip circuits. O n e such circuit will b e discussed shortly. T h e cur rent m i r r o r f o r m e d b y Q a n d Q supplies t h e differential pair Q - Q with bias current. T h e
SS
s
5
{
2
W/L ratio of Q is selected to yield the desired value for the input-stage bias current I (or 1/2 for 5
each of Q and Q ). T h e input differential pair is actively loaded with the current mirror formed
2KC R SS
x
SS
3
1 2KX0.2X
1Q-
2
by Q and (J.. T h u s the input stage is identical to that studied in Section 7.5 (except that here the differential pair is implemented with P M O S transistors and the current mirror with N M O S ) . 1 2
x 2 5 x 10
3
T h e second stage consists of Q , w h i c h is a c o m m o n - s o u r c e amplifier actively loaded with 6
= 31.8 M H z
:
the current-source transistor Q . A capacitor C is included in the negative-feedback path of the 7
Thus, the C M R R begins to decrease at 31.8 M H z , which is much lower t h a n / .
c
second stage. Its function is to enhance t h e Miller effect already present in Q (through t h e 6
F 1
action of its C„ ) and thus provide the o p a m p with a dominant pole. B y the careful placement of d
7 4 9
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
7.7
MULTISTAGE
AMPLIFIERS
+ VDD i
Consider the circuit in Fig. 7.40 with the following device geometries (in /mi).
G
&3
Transistor
W/L
Qi
Q2
20/0.8
20/0.8
Q
Q
3
Q
4
5/0.8
5/0.8
Q
40/0.8
10/0.8
2
°—i
3'
Q
•0
7
Qs
40/0.8
40/0.8
5
2
Let /REF = 90 pA, V = 0.7 V, V = - 0 . 8 V, p„C = 160 pAN , p C = 4 0 fiAN , \V \ (for all devices) = 10 V, V = V = 2.5 V. For all devices evaluate I , | V |, | V |, g , and r . Also find A A , the dc open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of V on bias current. tn
tp
DD
Cr
1(
D,
0X
p
ss
0X
D
A
ov
GS
m
0
2
A
Solution H
a
Refer to Fig. 7.40. Since g and GJ are matched, 1 = I . Thus Q a current equal to 1/2 = 45 pA. Since Q is matched to Q and < 2 s > 90 pA. Finally, Q conducts an equal current of 90 pA. With I of each device known, w e use
.FIA
8
5
m p
7
Q , Q , and Q each conducts current in Q is equal to =
h
2
me
5
3
4
7
6
D
2
ID =
FIGURE 7 . 4 0 Two-stage CMOS op-amp configuration.
\{liC )(W/L)V ox
to determine W \ for each transistor. Then we find \ V \ from \ V are given in Table 7 . 1 . The transconductance of each device is determined from ov
this p o l e , t h e o p a m p can b e m a d e to h a v e a gain that d e c r e a s e s w i t h frequency at the rate of - 6 dB/octave. or, equivalently, - 2 0 dB/decade d o w n to unity gain or 0 d B . O p a m p s with such a gain function are guaranteed to operate in a stable fashion, as opposed to oscillating, with nearly all possible feedback connections. Such op a m p s are said to b e frequency compensated. We shall study the subject of frequency c o m p e n s a t i o n in Chapters 8 and 9. Here, w e will simply take C into account in the analysis of the frequency response of the circuit in Fig. 7.40. A striking feature of t h e circuit in F i g . 7.40 is that it d o e s n o t h a v e a low-outputresistance stage. I n fact, the output resistance of t h e circuit is e q u a l to (r \\ r ) and is thus rather h i g h . T h i s circuit, therefore, is n o t suitable for driving l o w - i m p e d a n c e l o a d s . Never theless, t h e circuit is v e r y popular, and is u s e d frequently for i m p l e m e n t i n g o p a m p s in V L S I circuits w h e r e t h e o p a m p n e e d s to drive only a s m a l l capacitive load, for e x a m p l e , in s w i t c h e d - c a p a c i t o r circuits (Chapter 12). T h e simplicity of t h e circuit results in an o p a m p of r e a s o n a b l y g o o d quality realized in a v e r y small c h i p area.
ov
GS
=
27 /jV D
O T
GS
\ = \V \ + \ V \. t
0Y
The results
|
4
The value of r„ is determined from
c
o6
ol
\v \/i A
D
The resulting values of g and r are given in Table 7 . 1 . The voltage gain of the first stage is determined from m
0
A,
=
r
I L ( o 2 II
r
od
= - 0 . 3 ( 2 2 2 II 222) = - 3 3 . 3 V/V The voltage gain of the second stage is determined from
Voltage Gain
T h e voltage gain of t h e first stage w a s found in Section 7.5 to b e given b y A , = -g i(r \\r ) m
o2
A
2
(7-197)
o4
=
r
-8m6( o6
II
r) ol
= - 0 . 6 ( 1 1 1 II 111) = - 3 3 . 3 V/V
w h e r e g is the transconductance of each of the transistors of the first stage, that is, Q and Q . T h e s e c o n d stage is an actively l o a d e d c o m m o n - s o u r c e amplifier w h o s e low-frequency v o l t a g e gain is g i v e n b y ml
x
A
2
= -g (r Jr ) m6
0
Qi
(7.198)
ol
T h e dc o p e n - l o o p gain of t h e o p a m p is t h e p r o d u c t of A
x
4
2
and A .
Q2
Q3
QA
Q
5
Qe
Q7
Q
8
(M)
45
45
45
45
90
90
90
90
\Vov\ (V) \V \ (V) g (mA/V)
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
1.1
1.1
1
1
1.1
1
1.1
0.3
0.3
0.3
0.3
0.6
0.6
0.6
1.1 0.6
r„ (ki2)
222
222
222
222
111
111
111
111
ID
2
' Readers who have studied Chapter 2 will recall that commercially available op amps With this uniform gain rolloff of - 2 0 dB/decade are said to be internally compensated. Here "internal" means that the frequency compensation network is internal to the package (i.e., on chip) and need not be supplied externally by the user. The PKLAX op amp is an example of an internally compensated op amp.
GS
m
CHAPTER 7
DIFFERENTIAL A N DMULTISTAGE
1.1
AMPLIFIERS
0
.
J
7 5 3
If this condition is not met, a systematic offset will result. F r o m the specification of the device geometries in E x a m p l e 7.3, w e can verify that condition (7.201) is satisfied, and, therefore, t h e op amp analyzed in that e x a m p l e should not exhibit a systematic input offset voltage.
Thus the overall dc open-loop gain is A
MULTISTAGE AMPLIFIERS
= A_A = ( - 3 3 . 3 ) x ( - 3 3 . 3 ) = 1109 V / V 2
or 20 log 1109 = 61 dB
EXERCISE
The lower limit of the input common-mode range is the value of input voltage at which Q and Q leave the saturation region. This occurs when the input voltage falls below the voltage at the drain of Q b y j V \ volts. Since the drain of Q_ is at - 2 . 5 + 1 = - 1 . 5 V, then the lower limit of the input common-mode range is - 2 . 3 V. The upper limit of the input common-mode range is the value of input voltage at which Q leaves the saturation region. Since for Q to operate in saturation the voltage across it (i.e., V ) should at least be equal to the overdrive voltage at which it is operating (i.e., 0.3 V), the highest volt age permitted at the drain of Q should be +2.2 V. It follows that the highest value of v should be
7 17 Consider the C M O S o p a m p of Fig. 7.40 when fabricated in a 0.8-jUm C M O S technology for which u . , C = 3u„C = 90 u A / V , IV,\ = 0.8 V, and V = V = 2.5 V. For a particular design. / = 100 ,uA, (W/L), = '(W/U) = (W/L), = 200, and (W/L) = (W/L) = 1.00.
2
x
2
tp
ot
2
ss
4
(a) Find the (W/L) ratios of O,. and Q. so that / , = 100 //A. r-:._
•&
sm
s
PD
2
s
5
m
(b) Find the overdrive voltage, IV ,l, a t w h i c h each of Q_. Q , and Q is operating.,... m
2
b
(c) Find g,„ for g „ ö , and ß . 2
f i
ICM
(d) If W \ = 10 V , find r„ , r„ , r„ , and r . A
"/CMNAX = 2 . 2 - 1 . 1 = 1.1 V
2
4
(l
o7
(e) Find the voltage gains A, and A , and the overall gain A. 2
The highest allowable output voltage is the value at which Q leaves the saturation region, which is DD ~ | ov7 j = 2.5 - 0.3 = 2.2 V. The lowest allowable output voltage is the value at which Q leaves saturation, which is ~V + V = - 2 . 5 + 0.3 = - 2 . 2 V. Thus, the output voltage range is - 2 . 2 V to +2.2 V.
Ans. (a) ( \ r / . ) = (W/L). = 200; (b) 0.129 V, 0.129 V, 0.105 V; (c) 0.775 mA/V, 0.775 mA/V, 1.90 mA/V; (d) 200 k Q , 200 k Q , 100 kfl, 100 L<>: ( e . 77.5 V/V. - 9 5 V/V. 7363 V / V
7
V
!:
v
6
SS
ov6
Frequency Response I n p u t O f f s e t V o l t a g e T h e d e v i c e m i s m a t c h e s i n e v i t a b l y p r e s e n t in t h e i n p u t stage give rise t o a n i n p u t offset v o l t a g e . T h e c o m p o n e n t s of this input offset v o l t a g e c a n b e calcu lated u s i n g the m e t h o d s d e v e l o p e d in Section 7 . 4 . 1 . B e c a u s e d e v i c e m i s m a t c h e s are random, the resulting offset v o l t a g e is referred t o as r a n d o m offset. T h i s is to distinguish it from a n o t h e r t y p e of i n p u t offset v o l t a g e that c a n b e p r e s e n t e v e n if all a p p r o p r i a t e devices are perfectly m a t c h e d . T h i s p r e d i c t a b l e o r s y s t e m a t i c offset c a n b e m i n i m i z e d b y careful design. Although it occurs also in B J T o p a m p s , a n d w e h a v e encountered it in Section 7.5.5, it is usually m u c h m o r e p r o n o u n c e d i n C M O S o p a m p s b e c a u s e their g a i n - p e r - s t a g e is rather low. _____ • T o see h o w systematic offset can occur in t h e circuit of Fig. 7.40, let t h e t w o input termi nals b e g r o u n d e d . If the input stage is perfectly b a l a n c e d , then the^-voltage a p p e a r i n g at the drain of Q will b e equal to that at t h e drain of Q , w h i c h is (-V& + V ). N o w this is also the voltage that i s fed to t h e gate o f Q . I n other w o r d s , a v o l t a g e equal t o V appears b e t w e e n gate a n d source of Q . T h u s t h e drain current of Q ,1 , will b e related to t h e drain current of Q , w h i c h is equal to 7/2, b y t h e relationship 4
3
GS4
6
GS4
6
6
6
4
h
=
T o d e t e r m i n e t h e frequency r e s p o n s e of t h e t w o - s t a g e C M O S
op a m p of Fig. 7.40, consider its simplified small-signal equivalent circuit s h o w n in Fig. 7 . 4 1 . Here G
is t h e t r a n s c o n d u c t a n c e of the input stage ( G
ml
tance of the first stage (R, = r
o 4
Ci = c
gd4
G
m2
+C
db4
+C
gd2
+C
db2
is t h e t r a n s c o n d u c t a n c e of t h e s e c o n d stage (G
m2
the second stage (R = r 2
o6
=
o 7
y
c
2
= c
d
b
6
+C
d b 7
+C
4
( 7
(W/L)
5
.201)
2
+ C
L
L
L
with t h e result that C is m u c h larger than C Finally, n o t e that in t h e equivalent circuit of 2
v
Fig. 7 . 4 1 w e should h a v e included C
gd6
which is the r e a s o n w e h a v e neglected
in parallel with C . Usually, h o w e v e r , C > c
C . gd6
(7.200)
{
2 YYBl
n6
where C is t h e load capacitance. U s u a l l y C is m u c h larger than t h e transistor capacitances,
7
=
= g ), R is t h e o u t p u t r e s i s t a n c e of
g d 7
5
(W/L)
gs6
op a m p
N o w , t h e condition for m a k i n g I = I can b e found from E q s . (7.199) a n d (7.200) as 6
+ C
2
(7.199)
(W/L)
m2
II r ) , a n d C is t h e total c a p a c i t a n c e at t h e output n o d e of t h e
7
7
= g ), R-i is t h e output resis
the first a n d s e c o n d stages
5
I
ml
x
In order for n o offset voltage to appear at t h e output, this current m u s t b e e x a c t l y equal to the current supplied b y Q . T h e latter current is related t o t h e current I of the parallel transis tor Q b y
c
=g
m l
II r ) , a n d C is the total capacitance at the interface b e t w e e n
o2
FIGURE 7 . 4 1
Equivalent circuit of the op amp in Fig. 7.40.
c
C
gd6
754
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS MULTISTAGE
7.7
T o d e t e r m i n e V„, analysis o f t h e circuit i n F i g . 7 . 4 1 p r o c e e d s a s follows. W r i t i n g a node e q u a t i o n at n o d e D y i e l d s 2
AMPLIFIERS
We recognize the first t e r m in t h e denominator as arising at t h e interface b e t w e e n the first a n d second stages. Here, R
the output resistance of the first stage, is interacting with the total capac-
h
itance at the interface. T h e latter is the s u m of C¡ and the Miller capacitance C ( l +
G R ),
c
G
SCLVI2
Vii+Y^
ml
+ SCC(V 2
V
'
= 0
'^
(7.202)
m2
m2
2
0
c
Q
i2
0
^ A V C
0
id
0
Vo_ v
id
2
(7.203)
T o e l i m i n a t e V a n d thus d e t e r m i n e V in t e r m s of V , w e u s e E q . (7.203) t o e x p r e s s V„ in terms of V a n d substitute t h e result into E q . ( 7 . 2 0 2 ) . After s o m e straightforward manipulations w e o b t a i n t h e amplifier transfer function i2
X
Pl
+ ^ + sC V + sC (V - V ) =
i2
• N o w , since R and R are usually of comparable value, w e see that the first term in t h e
denorninator will b e m u c h larger than the second a n d w é c a n approximate co as
6
G V
mX
1+ s t d * ! + CR 2
2
+ C (G c
m2
c
t
capacitance a n d G R m2
>l, thus
2
,-
i ? ! i v + R, + R )] + [C,C + 2
( 7
^ Y T T - W
2 2
m 2
+ Cc-a+G,^)]
A further a p p r o x i m a t i o n is possible b e c a u s e C is usually m u c h s m a l l e r than t h e M i l l e r
G {G -sC )R,R
=
2
c
is G Ri Writing a node equation at node D yields
m2
which results from connecting C in the negative-feedback path of the second stage whose gain
2
S
C (C,+
2
C )]R,R
C
2
2
'
2 0 9 )
T h e frequency o f t h e s e c o n d , n o n d o m i n a n t p o l e c a n b e f o u n d b y e q u a t i n g t h e coefficients o f 2
the s terms in t h e d e n o m i n a t o r of E q . (7.204) a n d in E q . (7.207) a n d substituting for co
Pl
(7.204)
from E q . (7.209). T h e result is
First w e n o t e that for s = 0 (i.e., dc), E q . (7.204) gives V„/Vid = ( G # i ) ( G i ? ) , which is w h a t w e should h a v e e x p e c t e d . S e c o n d , t h e transfer function i n E q . (7.204) indicates that the amplifier h a s a t r a n s m i s s i o n z e r o a t s = s , w h i c h is d e t e r m i n e d f r o m m l
m 2
2
to
G
= P 2
C
m2 C
C ^ + CdCt
+ C,)
z
Since Cj < C a n d C < C , co can b e approximated as 2
G
m2-S C z
A
c
P2
= 0
c
Thus,
(ú
=^ 2 C2
P2
s
z
=
(7.205)
(7.210)
In order t o p r o v i d e t h e o p a m p with a u n i f o r m gain rolloff of - 2 0 d B / d e c a d e d o w n t o 0 d B ,
C
the v a l u e of t h e c o m p e n s a t i o n c a p a c i t o r
c
is selected s o that t h e resulting value of
(Eq. 7.209) w h e n multiplied b y t h e d c gain (G^R^G^RJ
In o t h e r w o r d s , the z e r o is o n t h e p o s i t i v e real axis w i t h a frequency co of z
co
Pl
results in a unity-gain frequency
a>, lower t h a n a> a n d co^ Specifically z
%
= ~
(7.206)
fl* =
c
A l s o , t h e amplifier h a s t w o p o l e s that a r e t h e roots o f t h e d e n o m i n a t o r p o l y n o m i a l of E q . (7.204). If the frequencies of t h e t w o poles are denoted a> a n d co then t h e denominator p o l y n o m i a l c a n b e e x p r e s s e d as PX
00,=
P2
(G R G R )œ,'PI ml
(7.211) G
a n d co =
z
C0 J
^VCOPJ
P2
co
N o w if o n e o f the p o l e s , say that with frequency can b e a p p r o x i m a t e d b y
D(s)=l
+— oo
+
Pl
P2
F
5
2
co co Pl
P2
P2
and
sD7.1fsC;©nsider the frequency response of the op a m p analyzed in Example 7.3, Let C = 0.1 p F and C Find the value of C that results i n / = 1 0 M H z and verify that f is lower t h a n j | a n d / P . l
c
T h e frequency of t h e d o m i n a n t p o l e , a) , c a n n o w b e d e t e r m i n e d b y e q u a t i n g t h e coefficients of t h e s t e r m s in t h e d e n o m i n a t o r in E q . ( 7 . 2 0 4 ) a n d i n E q . ( 7 . 2 0 7 ) , P1
l R l
— + CR 2
2
— + C (G R R, c
m2
2
2
D(s)
(7.207)
'
W e will h a v e m o r e to say a b o u t this
P2
c
point in S e c t i o n 9 . 1 .
XO (0
P2
i s d o m i n a n t , t h e n
Pl
Pl
(0 J
2
^ C
G
(OpyJV
m2
c
w h i c h m u s t b e l o w e r than co = V
l
f
t
Ans. G = 4.8 p F ; / = 2 0 M H z ; / , , , = 48 M H z c
z
+R R ) 1+
2
A Bias C i r c u i t T h a t S t a b i l i z e s g
m
W e c o n c l u d e this section b y presenting a bias circuit
for t h e two-stage C M O S o p a m p . T h e circuit presented h a s t h e interesting a n d useful property of providing a bias current w h o s e value is independent of both the supply voltage a n d t h e
2
2
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
7.7
MULTISTAGE AMPLIFIERS
' .
7
This equation c a n b e r e a r r a n g e d to yield
(
2
A
3
H
(W/L)
2
1
(7.215)
2
/.l C (W/L) R ^(W/L) n
0X
12
B
from which w e observe that I is determined by the dimensions of Q B
n
the ratio of the dimensions of Q
l2
and the value of R
B
and by
and Q . Furthermore, Eq. (7.215) can b e rearranged to the form l3
j2ß„C (W/L) I ^(W/L) 0X
12 B
l3
in w h i c h w e r e c o g n i z e t h e factor j2fi C (W/L) I n
ßi3^ H
0X
as g ;
l2 B
iLTß
2(
ml2
|(W/L)
1 2
_
thus,
1 )
(
7
2
1
6
)
RM(W/L\ This is a very interesting result: g
is deteraiined solely by the value of R and the ratio of the
mU
K
F I G U R E 7 . 4 2 Bias circuit for the CMOS op amp.
ss
dimensions of Q
B
and Q . Furthermore, since g
l2
13
of a M O S F E T is proportional to
m
Jl (W/L), D
each transistor biased b y the circuit of Fig. 7.42; that is, each transistor w h o s e bias current is M O S F E T threshold voltage. Furthermore, the transconductances of the transistors biased by
derived from I will h a v e a g
this circuit h a v e values that are determined only b y a single resistor a n d the device dimensions.
M O S F E T will h a v e
B
m
value that is a multiple of g . ml2
Specifically, the ith
ra-channel
T h e bias circuit is s h o w n in F i g . 7.42. It consists of t w o deliberately m i s m a t c h e d transistors, Q
i2
and Q ,
with Q
13
usually about four t i m e s w i d e r than Q
12
and M a r t i n , 1997). A resistor R
is c o n n e c t e d in series with t h e source of Q .
B
be shown, R
B
and the transconductance g ,
B
ml2
should b e a c c u r a t e a n d stable; in m o s t applications, R
order to m i n i m i z e the c h a n n e l - l e n g t h m o d u l a t i o n effect o n Q ,
a c a s c o d e transistor Q
u
a m a t c h e d d i o d e - c o n n e c t e d transistor Q
l0
to p r o v i d e a bias v o l t a g e for Q ,
n
' I {W/L)
w
B
l2
its value
w o u l d b e an off-chip resistor. In
B
D
iml2 l
S i n c e , as will
i2
d e t e r m i n e s both the b i a s current I
I i(W/L)i
(Steininger, 1990; l o h n s
l3
and t h e ith /»-Channel d e v i c e will h a v e
and
is included.
im\2
p I (W/L) n B
l2
Finally, a ^ - c h a n n e l current m i r r o r f o r m e d b y a p a i r of m a t c h e d d e v i c e s , Q% a n d Q , repli9
cates the current I b a c k to Q B
n
and Q , 13
C M O S o p - a m p circuit of Fig. 7 . 4 0 .
as w e l l as p r o v i d i n g a b i a s line for Q a n d Q of the 5
7
T h e circuit o p e r a t e s as follows: T h e current m i r r o r (<2 , Q ) c a u s e s Q 8
9
l3
to c o n d u c t a cur-
by m a k i n g Q
l2
wider than g , as h a s already b e e n pointed out. Nevertheless, s o m e form of 1 3
instability m a y still occur; in fact, the circuit can operate in a stable state in w h i c h all currents
rent equal to that in Q , that is, I . T h u s , 1 2
Finally, it should b e noted that the bias circuit of Fig. 7.42 employs positive feedback, and thus care should b e exercised in its design to avoid unstable performance. Instability is avoided
5
B
are zero. T o get it out of this state, current needs to b e injected into one of its nodes, to "kick (7.212)
GS 12
Vi),,
start" its operation. F e e d b a c k and stability will b e studied in Chapter 8.
and, h
(7.213)
2
=
\ß C (j^jJV -V ) n
0X
GS13
t
7.20 Consider the bias circuit of Fig. 7.42 for the case: {W/l.\ = (W/L)
v
F r o m the circuit, w e see that the g a t e - s o u r c e v o l t a g e s of Q
l2
and Q
13
are related b y
i2
^0513
=
+
V~GS12 h
R
= (W/L)
m
= ( W / / . ) = (W/L) H
= 20 and
l3
( W / L ) = 80. Find the value ofJ? -that results in a bias current I = 10 juA. Also in a process technology fi
2
• having u,,C
B
B
rn
= 9 0 [ i M V . find t h e t r a n s c o n d u c t a n c e g , 2 . Bl
Ans. 5.27 k O ; 0.379 m A / V S u b t r a c t i n g V, from b o t h sides of this e q u a t i o n a n d u s i n g E q s . (7.212) a n d (7.213) to replace (V su G
~ V) and ( V t
G S 1 3
D7.21 Design the bias circuit of Fig. 7.42 to operate with the C M O S op amp of Example 7.3. Use Q and Q as 8
- V ) results in t
identical devices with Q having the dimensions g i v e n i n E x a m p l e 7.3. Transistors Q , Q , %
2/„ ß C (W/L) n
0X
2I„
(7.214)
^ß C (W/L)
i3
n
0X
v
M
B
R
$
9
required value of R . What is the voltage drop across H
l7
B
u
9
and Q
i3
are
to be identical, with the same £ a s Q and Q . T r a n s i s t o r , ^ is to be four times a s w i d e as Q . Find the gates of Q .
' We denote the bias current of this circuit by I . If this circuit is utilized to bias the CMOS op amp of Fig. 7.40, then I becomes the reference current 7
H)
0 , and Q . U )
A
Ans. 1.67 k Q : 150 m V ; - 1 . 5 V; - 0 . 5 V : +1.4 V
x3
Also give the values of the dc voltages at the
CHAPTER 7
7.7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
7.7.2 A Bipolar Op Amp O u r s e c o n d e x a m p l e of m u l t i s t a g e amplifiers is t h e f o u r - s t a g e b i p o l a r o p a m p s h o w n in F i g . 7 . 4 3 . T h e circuit consists of four stages. T h e input stage is differential-in, differentialo u t a n d c o n s i s t s of t r a n s i s t o r s Q_ and Q , w h i c h are b i a s e d b y current s o u r c e Q . The s e c o n d s t a g e is also a differential-input amplifier, b u t its o u t p u t is t a k e n s i n g l e - e n d e d l y at t h e c o l l e c t o r of Q . T h i s s t a g e is f o r m e d b y Q a n d Q , w h i c h are b i a s e d b y t h e current s o u r c e Q . N o t e that t h e c o n v e r s i o n from differential to s i n g l e - e n d e d as p e r f o r m e d b y the s e c o n d s t a g e results in a loss of g a i n b y a factor of 2. A m o r e e l a b o r a t e m e t h o d for a c c o m p l i s h i n g this c o n v e r s i o n w a s studied in S e c t i o n 7 . 5 ; it i n v o l v e s u s i n g a c u r r e n t m i r r o r as an a c t i v e l o a d . 2
5
3
4
5
MULTISTAGE AMPLIFIERS
provides a simple solution to t h e level-shifting p r o b l e m , other f o r m s of level shifter exist, one of which will b e d i s c u s s e d in C h a p t e r 9. F u r t h e r m o r e , n o t e that level-shifting is a c c o m plished in the C M O S o p a m p w e h a v e b e e n studying b y using c o m p l e m e n t a r y devices for the two stages; that i s , p - c h a n n e l for the first stage a n d ^ - c h a n n e l for t h e s e c o n d stage. T h e output stage of t h e o p a m p consists of emitter follower Q . A s w e k n o w from our study of o p a m p s in C h a p t e r 2 , t h e output o p e r a t e s ideally a r o u n d z e r o volts. T h i s a n d other features of the B J T o p a m p will b e illustrated in E x a m p l e 7.4. %
6
In addition to p r o v i d i n g s o m e voltage gain, the t h i r d stage, consisting of t h e pnp transistor Q , p r o v i d e s t h e essential function of shifting the dc level of t h e signal. T h u s w h i l e the signal at the collector of Q is not allowed to swing below the voltage at the base of Q (+10 V), the signal at the collector of Q-, c a n s w i n g negatively (and positively, of course). F r o m our study of o p a m p s in C h a p t e r 2 w e k n o w that the output terminal of the o p a m p should be capable of b o t h positive and negative voltage swings. Therefore every o p - a m p circuit includes a level-shifting arrangement. A l t h o u g h t h e u s e of the c o m p l e m e n t a r y pnp transistor 1
5
5
In this example, w e analyze the dc bias of the bipolar op-amp circuit of Fig. 7.43. Toward that end, Fig. 7.44 shows the circuit with the two input terminals connected to ground. (a) Perform an approximate dc analysis (assuming B > 1, \ V \ BE
— 0.7 V, and neglecting the
Early effect) to calculate the dc currents and voltages everywhere in the circuit. Note that Q has 6
four times the area of each of Q and Q . 9
3
(b) Calculate the quiescent power dissipation in this circuit. (c) If transistors Q and Q have ¡8 = 100, calculate the input bias current of the op amp. x
+15 V
2
(d) What is the input common-mode range of this op amp?
R, = 2.3 kft
+15 V
28.6 kfl
o v
0
R
6
= 3 kfl
-15 V
-15 V FIGURE 7 . 4 3
A four-stage bipolar op amp.
FIGURE 7 . 4 4
Circuit for Example 7.4.
760
CHAPTER 7
MULTISTAGE AMPLIFIERS
7.7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
Solution (a) The values of all dc currents and voltages are indicated on the circuit diagram. These values were calculated by ignoring the base current of every transistor—that is, by assuming B to be very high. The analysis starts by determining the current through the diode-connected transistor Q to be 9
0.5 mA. Then we see that transistor Q conducts 0.5 m A and transistor Q conducts 2 mA. The 3
6
Q ) with 0.5 mA. Thus each of G, and Q
current-source transistor Q feeds the differential pair (Q 3
T
«A
h
2
2
will be biased at 0.25 mA. The collectors of Q_ and Q, will be at [+15 - 0.25 x 20] = +10 V. Proceeding to the second differential stage formed by Q and Q , we find the voltage at their 4
5
emitters to be [+10 - 0.7] = 9.3 V. This differential pair is biased by the current-source transistor Q , which supplies a current of 2 mA; thus Q and Q will each be biased at 1 mA. W e can 6
4
5
n o w calculate the voltage at the collector of Q as [+15 - 1 x 3 ] = +12 V. This will cause the s
J
FIGURE 7 . 4 5 Equivalent circuit for calculating the gain, of the input stage of the amplifier in Fig. 7.43.
voltage at the emitter of the pnp transistor G to be +12.7 V, and the emitter current of Q will be 7
7
(+15 - 12.7)/2.3 = 1 m A . The collector current of G , 1 m A , causes the voltage at the collector to be [-15 + 1 x 15.7] =
[.¿1
7
+
•M
Since Gi and Q2 are
7
0 - V- The emitter of Q will be 0.7 V below the base; thus output terminal 3 will be at 0 V.
e
a
c
n
operating at an emitter current of 0.25 m A , it follows that
t
I ; J £m
25
Finally, the emitter current of G can be calculated to be [0 - (—15)]/3 = 5 mA.
'el
8
(b) To calculate the power dissipated in the circuit in the quiescent state (i.e., with zero input sigAssume B= 100; then
nal) we simply evaluate the dc current that the circuit draws from each of the two power supplies.
"^1 I
+
From the +15-V supply the dc current is I
= 0.25 + 0.25 + 1 + 1 + 1 + 5 = 8.5 m A . Thus the +
power supplied by the positive power supply is P
?*7r1
+
negative supply is P~ - 15 x 9 = 135 m W . Adding P +
D
101 x 100 = 10.1 k Q
^77
Thus R
and P~ provides the total power dissipated in
= 20.2 k Q
id
+ P~ = 262.5 m W .
D
—
= 15 x 8.5 = 127.5 m W . The - 1 5 - V supply
provides a current I~ given by F - 0.5 + 0.5 + 2 + 1 + 5 = 9 mA. Thus the power provided by the the circuit P : P = P
100 Q
0.25
To evaluate the gain of the first stage we first find the input resistance of the second stage, R
i2
(c) The input bias current of the op amp is the average of the dc currents that flow in the two input terminals (i.e., in the bases of Q and Q ). These two currents are equal (because w e have x
Ril - n4 r
2
assumed matched devices); thus the bias current is given by
+
r
n5
Q and Gj are each operating at an emitter current of 1 m A ; thus 4
(d) The upper limit on the input common-mode voltage is determined by the voltage at which
5
Thus R
i2
Qi and Q leave the active mode and enter saturation. This will happen if the input voltage exceeds 2
r
e4
= r
r
nA
= r
e5
x5
= 25 Q = 101 x 2 5 = 2.525 k Q
= 5.05 k Q . This resistance appears between the collectors of Q and Q , as shown in x
2
Fig. 7.45. Thus the gain of the first stage will be
the collector voltage, which is +10 V, by about 0.4 V. Thus the upper limit of the common-mode
_ v
Total resistance in collector circuit
ol
range is +10.4 V .
1 =
Tj~~
Total resistance in emitter circuit
d
The lower limit of the input c o m m o n - m o d e range is determined by the voltage at which Q
3
leaves the active m o d e and thus ceases to act as a constant-current source. This will happen if the
=
[R 11 (Ri + R )l l2
2
collector voltage of Q goes below the voltage at its base, which is - 1 4 . 3 V, by more than 0.4 V.
ri + r
3
e
e2
It follows that the input common-mode voltage should not go lower than - 1 4 . 7 + 0.7 = - 1 4 V. Thus the c o m m o n - m o d e range is - 1 4 V to +10.4 V.
=
(5.05 k Q II 4 0 k Q )
=
2
2
4
y
/
v
-, 200 Q Figure 7.46 shows an equivalent circuit for calculating the gain of the second stage. As indicated, the input voltage to the second stage is the output voltage of the first stage, v .
Also
ol
shown is the resistance R , which is the input resistance of the third stage formed by G . The 7
i3
value of R
U s e the dc bias quantities evaluated in Example 7.4 to analyze the circuit in Fig. 7.43, to deter-
i3
can be found by multiplying the total resistance in the emitter of G by (B + 1): 7
mine the input resistance.ihe voltage gain, and the outout resistance.
R
i3
= (B+l)(R
4
+
r) el
Since Q-i is operating at an emitter current of 1 m A ,
Solution The input differential resistance R
id
is given by "
Rid
=
I %\ + K2
r
R
r
.
e
l
=f
= 25 Q
R.„ = 101 x 2.325 = 234.8 k Q
7
6
2
'-sJ
C
H
A
P
T
E
R
7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
7.7
Vo3
MULTISTAGE AMPLIFIERS
<
Rr FIGURE 7 . 4 8 Equivalent circuit of the output stage of the amplifier circuit of Fig. 7.43.
The gain of the third stage is given by FIGURE 7 . 4 6 Equivalent circuit for calculating the gain of the second stage of the amplifier in Fig. 7.43. 3
v
r
o2
We can now find the gain A of the second stage as the ratio of the total resistance in the collector circuit to the total resistance in the emitter circuit:
+ R
el
4
2
A,=
§§1
(15.7 k O H 303.5 k Q ) 2.325 k Q
=
_
6
4
?
y
/
y
. ( M y r
Finally, to obtain the gain A of the output stage we refer to the equivalent circuit in Fig. 7.48
r
e4 + e5
4
and write y
50 Q
V
'
/
V
A =— v
i4
R
-
4
To obtain the gain of the third stage w e refer to the equivalent 'circuit shown in Fig. 7 47 where R is the input resistance of the output stage formed by g . U s i h g i h e resistance-reflection rule, we calculate the value of R as
< R + r
o3
6
e
8
3000 = 0.998 = 1 3000 + 5
l4
* , - 4 = (P+l)(r
ei
+ R) 6
The overall voltage gain of the amplifier can then be obtained as follows:
where
= AAAA X
R
i4
= 101(5 + 3000) = 303.5 k Q
2
3
= 8513 VAV
4
or 78.6 dB. To obtain the output resistance R we "grab hold" of the output terminal in Fig. 7.43 and look 0
back into the circuit. B y inspection w e find R
0
= RJ[r
ei
+
R /(P+l)] s
which gives A' = 152 Q
EXERCISE
R S
I
7.22 Use the results of Example 7.5 to calculate the overall voltage gain of the amplifier in Fig. 7.43 when it R
i4
is connected lo a source having a resistance of 10 k Q and a load of 1 k Q .
: FIGURE 7 . 4 7 Equivalent circuit for evaluating the gain of the third stage in the amplifier circuit of Fig. 7.43.
Ans. 4943 V/V
7 6 3
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
7.7
1—±— I
^ = Pi hi R
2 hs
k
t
hi ~
MULTISTAGE AMPLIFIERS
hi _
>_
R
3
hi
hi
hs 4J
i
c2
_
(R
y
+ R) 2
(R. +
RJ+Rn
T h e s e ratios c a n b e easily evaluated and their v a l u e s u s e d to d e t e r m i n e the v o l t a g e gain. W i t h a little practice, it is possible to carry out such an analysis v e r y quickly, forgoing FIGURE 7 . 4 9 The circuit of the multistage amplifier of Fig. 7.43 prepared for small-signal analysis. Indicated are the signal currents throughout the amplifier and the input resistances of the four stages.
explicitly labeling the signal currents on the circuit d i a g r a m . O n e s i m p l y " w a l k s t h r o u g h " the circuit, f r o m i n p u t to output, or vice versa, d e t e r m i n i n g the current-transmission factors one at a t i m e , in a c h a i n l i k e fashion.
Analysis Using Current Gains
T h e r e is an alternative m e t h o d for the analysis of bipolar
m u l t i s t a g e amplifiers that can b e s o m e w h a t easier to p e r f o r m in s o m e cases. T h e m e t h o d m a k e s use of current gains or m o r e appropriately current t r a n s m i s s i o n factors. In effect, o n e traces t h e transmission of the signal current t h r o u g h o u t the amplifier c a s c a d e , evaluating all
EXERCISE
the current t r a n s m i s s i o n factors in turn. W e shall illustrate the m e t h o d by using it to analyze 1
the amplifier circuit of the p r e c e d i n g e x a m p l e .
^
7.23 U s e the values of input resistance found in Example 7.5 to evaluate the seven current-transmission fac
\
tors and hence the overall current gain and voltage gain.
F i g u r e 7.49 s h o w s the amplifier circuit p r e p a r e d for small-signal a n a l y s i s . W e h a v e indi cated o n t h e circuit d i a g r a m the signal currents t h r o u g h all the circuit b r a n c h e s . A l s o indi cated are t h e i n p u t resistances of all four stages of the amplifier. T h e s e should b e evaluated before c o m m e n c i n g the following analysis.
Ans. The. current-transmission factors in the order of their listing are 101, 0.0492, 100, 0.0126, 100, 0.8879, 100 A/A; the overall current gain is 55993 A/A; the voltage gain is 8256 V/V. This value differs slightly from that found in Example 7.5 because of the various approximations made in the example (e.g.. a s 1).
T h e p u r p o s e of t h e analysis is to d e t e r m i n e t h e overall v o l t a g e gain (v lv ). T o w a r d that end, w e e x p r e s s v in t e r m s of t h e signal current in t h e emitter of Q , i , and v in terms of the i n p u t signal current i as follows: 0
B
s
id
eS
id
J
h
V
o
=
R hi
Frequency Response
b
Vid =
T h e bipolar o p - a m p circuit of F i g . 7.43 is rather c o m p l e x . N e v e r
theless, it is p o s s i b l e to o b t a i n an a p p r o x i m a t e e s t i m a t e of its h i g h - f r e q u e n c y r e s p o n s e .
Rilh
T h u s , the v o l t a g e gain can be e x p r e s s e d in t e r m s of the current g a i n {i /i,) e8
as
F i g u r e 7.50(a) s h o w s an a p p r o x i m a t e e q u i v a l e n t circuit for this p u r p o s e . N o t e that w e h a v e utilized t h e e q u i v a l e n t differential half-circuit concept, with Q representing the input stage 2
and Q r e p r e s e n t i n g t h e s e c o n d stage. W e o b s e r v e , of course, that t h e second stage is n o t 5
s y m m e t r i c a l , a n d strictly s p e a k i n g the e q u i v a l e n t half-circuit does not apply. N e v e r t h e l e s s , N e x t , w e e x p a n d the current gain (; //,-) in t e r m s of the signal currents t h r o u g h o u t t h e circuit as follows: e8
l
i
l
bi
'c7
^ _ hi
x
hi h5
x
hs hs h5 h x
2
x
h2 h
E a c h of the current-transmission factors o n t h e r i g h t - h a n d side is either t h e current gain of a transistor or the ratio of a current divider. T h u s , reference to F i g . 7.49 enables us to find these factors b y inspection,
w e use it as an a p p r o x i m a t i o n so as to obtain a q u i c k p e n c i l - a n d - p a p e r estimate of t h e d o m i nant h i g h - f r e q u e n c y p o l e of t h e amplifier. M o r e precise results c a n of c o u r s e b e o b t a i n e d using c o m p u t e r simulation with S F I C E (Section 7.8). E x a m i n a t i o n of the equivalent circuit in Fig. 7.50(a) reveals that if t h e resistance of t h e source of signal V, is small, the high-frequency limitation will not o c c u r at t h e i n p u t b u t rather at t h e interface b e t w e e n the first and the second stages. T h i s is b e c a u s e t h e total c a p a c i t a n c e at n o d e A will b e h i g h as a result of the M i l l e r multiplication of C^.
Also, the
third stage, f o r m e d b y transistor g , s h o u l d exhibit g o o d high-frequency r e s p o n s e , since 7
Qn has a large e m i t t e r - d e g e n e r a t i o n resistance, R . T h e s a m e is also true for the emitter3
follower stage, O . s
_ cl
T o d e t e r m i n e the frequency of the d o m i n a n t p o l e that is f o r m e d at the interface b e t w e e n
R
5
R5 + R/4
Q
2
and Q
5
w e - s h o w in Fig. 7.50(b) the pertinent equivalent circuit. T h e total resistance
7 6 5
766
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
7.8
~\ 7.8
SPICE S I M U L A T I O N E X A M P L E
SPICE SIMULATION EXAMPLE
\
W e c o n c l u d e this c h a p t e r b y p r e s e n t i n g a S P I C E simulation of t h e m u l t i s t a g e differential amplifier w h o s e d c bias w a s a n a l y z e d in E x a m p l e 7.4 and w h o s e small-signal p e r f o r m a n c e was the subject of E x a m p l e 7 . 5 .
SPICE SIMULATION OF A MULTISTAGE DIFFERENTIAL AMPLIFIER
The Capture schematic of the multistage op-amp circuit analyzed in Examples 7.4 and 7.5 is 6
shown in Fig. 7 . 5 1 . Observe the manner in which the differential signal input V and the commond
mode input voltage V
CM
are applied. Such an input bias configuration for an op-amp circuit was
presented and used in Example 2.9. In the following simulations, we will use parts Q2N3904 and (a) A
r2
->2 •
< ^ ^ /
0
vec
• ZR
= = Q
2
5
,==C
vec
vec
vec
vec vec
•
/
lVac (~) OVdc^.
(b)
{VCM} - —
______
FIGURE 7 . 5 0 (a) Approximate equivalent circuit for determining the high-frequency response of the op amp of Fig. 7.43. (b) Equivalent circuit of the interface between the output o f , g and the input of g . 2
5
OUT "—0
b e t w e e n n o d e A and g r o u n d c a n n o w b e found as
tf
eq
= R II r 2
o2
0"=:
|| r
n5
and the total c a p a c i t a n c e is
where R
L5
=
R l\r \\R 3
T h e frequency of t h e p o l e can b e calculated from i ?
o5
eq
i3
and C
e q
as
PARAMETERS: Rl = 20K R2 = 20K R3 = 3K R4 = 2.3K + R5 = 15.7K {VCC}-=. R6 = 3K RB = 28.6K VCC = 15 VCM = 0 VEE = - 1 5 FIGURE 7 . 5 1
7.24 Determine R_ C , andJ for the amplifier in Fig. 7.43 utilizing the facts that is biased at 0 25 m A and Q, at 1 m A. Assume Q = 100. V = 100 V, f = 400 M H z , and C„ = 2 pF. Assume K„ = R, Ans. 2.21 k i i : 2 - s J.snkll/ r
eq
}3 \
Q6A)
QÔBJ
Q6CJ
Q6DJ :(R6}
-=-{VEE} Q9
0
IrO
VEE
'
VEE
VEE
VEE
VEE
VEE VEE
Capture schematic of the op-amp circuit in Example 7.6.
P
A
T
6
This circuit cannot be simulated using the student evaluation version of PSpice (OrCAD 9.2 Lite Edition) that is included on the CD accompanying uiis book. This is because, in this free version of PSpice, circuit simulation is restricted to circuits with no more than 10 transistors.
VEE
"
!
7 6 7
CHAPTER 7
7.8
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
TABLE 7,2
SPICE S I M U L A T I O N E X A M P L E
20V
SPICE Model Parameters of the Q2N3904 and Q2N3906 Discrete BJTs
Q2N3904 Discrete BJT
IS=6.734f IKF=66.78m CJC=3.638p TR=239.5n
XTI=3 XTB=1.5 MJC=.3085 TF=301.2p
EG=l.ll BR=.7371 VJC=.75 ITF=.4
VAF=74.03 BF=416.4 NC=2 ISC=0 FC=.5 CJE=4.493p VTF=4 XTF=2
NE=1.259 IKR=0 MJE=.2593 RB=10
EG=1.11 BR=4.977 VJC=.75 ITF=.4
VAF=18 NC=2 FC=.5 VTF=4
BF=180.7 ISC=0 CJE=8.063p XTF=6
NE=1.5 -IKR=0 MJE=.3677 RB=10
ISE=6.734f RC=1 VJE=.75
Q2N3906 Discrete BJT
IS=1.41f IKF=80m CJC=9.728p TR=33.42n
XTI=3 XTB=1.5 MJC=.5776 TF=179.3p
ISE=0 RC=2.5 VJE=.75
Dc Collector Currents of t h e O p - A m p Circuit in Fig. 7.51 as C o m p u t e d by Hand Analysis (Example 7.4) and by PSps.re
TABLE 7.3
Collector Currents (mA) Hand Analysis (Example 7.4)
Transistor
0.25 0.25 0.5 1.0 1.0 2.0 1.0 5.0 0.5
Qi 02 03 04 05 06 07 08 09
PSpice
..
Error (%)
-20V -15
-10
° V(OUT) 0.281 0.281 0.567 1.27 1.21 2.50 1.27 6.17 0.48
-11.0 -11.0 -11.8 -21.3 -17.4 -20.0 -21.3 -18.9 +4.2
20V
10V Q2N3906 (from Fairchild Semiconductor) for the npn and pnp BJTs, respectively. The model parameters of these discrete BJTs are listed in Table 7.2 and are available in PSpice. In PSpice, the common-mode input voltage V of the op-amp circuit is set to 0 V (i.e., to the average of the dc power-supply voltages V and V ) to maximize the available input signal swing. A bias-point simulation is performed to determine the dc operating point. Table 7.3 sum marizes the values of the dc collector currents as computed by PSpice and as calculated by the hand analysis in Example 7.4. Recall that our hand analysis assumed B and the Early voltage V of the BJTs to be both infinite. However, our SPICE simulations in Example 5.21 (where we inves tigated the dependence of B on the collector current I ) indicate that the Q2N3904 has 8 ~ 125 at 7 = 0.25 mA. Furthermore, its forward Early voltage (SPICE parameter V A F ) is 74 V, as given in Table 7.2. Nevertheless, we observe from Table 7.3 that the largest error in the calculation of the dc bias currents is on the order of 2 0 % . Accordingly, we can conclude that a quick hand anal ysis using gross approximations can still yield reasonable results for a preliminary estimate and, of course, hand analysis yields much insight into the circuit operation. In addition to the dc bias currents listed in Table 7.3, the bias-point simulation in PSpice shows that the output dc offset (i.e., V T when V = 0) is 3.62 V and that the input bias current I is 2.88 jiA. CM
cc
EE
A
-10V--
c
C
0 U
d
d
CC
-4.0
° V(OUT)
V_Vd (mV) (b)
Bl
T o compute the large-signal differential transfer characteristic of the op-amp circuit, we perform a dc-analysis simulation in PSpice with the differential voltage input V swept over the r a n g e - V to +V , and w e plot the corresponding output voltage V UT- Figure 7.52(a) shows the E E
-20 V -5.0
0
FIGURE 7 . 5 2 (a) The large-signal differential transfer characteristic of the op-amp circuit in Fig. 7.51. The common-mode input voltage V M to 0 V. (b) An expanded view of the transfer characteristic in the high-gain region. i s
C
s e t
vlji
7 6 9
770
1
"
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
7.8
AMPLIFIERS
resulting dc transfer characteristic. The slope of this characteristic (i.e., DV /DV ) corre sponds to the differential gain of the amplifier. Note that, as expected, the high-gain region is in the vicinity of V = 0 V . However, the resolution of the input-voltage axis is too gross to yield much information about the details of the high-gain region. Therefore, to examine this region more closely, the dc analysis is repeated with V swept over the range —5 m V to + 5 mV at increments of 10 /uV. The resulting differential dc transfer characteristic is plotted in Fig. 7.52(b). Accordingly, the linear region of the large-signal differential characteristic is b o u n d e d ap proximately by V = - 1 . 5 m V and V = +0.5 m V . Over this region, the output level changes from V = - 1 5 V to about V = + 1 0 V in a linear fashion. Thus, the output voltage swing for this amplifier is between - 1 5 V and + 1 0 V, a rather asymmetrical range. A rough estimate for the differential gain of this amplifier can be obtained from the boundaries of the linear region as A = [l0- ( - 1 5 ) ] V / [ 0 . 5 - ( - 1 . 5 ) ] m V = 12.5 x 1 0 V/V. W e also observe from Fig. 7.52(b) that V = - 2 6 0 /iV when F = 0. Therefore, the amplifier has an input offset voltage V of + 2 6 0 LiV (by convention, the negative value of the jc-axis intercept of the large-signal dif ferential transfer characteristics). This corresponds to an output offset voltage of A V = (12.5 x 10 )(260 fjY) = 3.25 V, which is close to the value found through the bias-point simulation. It should be emphasized that this offset voltage is inherent in the design and is not the result of component or device mismatches. Thus, it is usually referred to as a systematic offset. 0X]T
d
SPICE S I M U L A T I O N
EXAMPLE
100-
82.8dB f
H
d
= 256.9kHz
d
d
d
0 U T
60
0 U T
3
d
d
0 U T
40-
os
d
os
3
Next, to c o m p u t e the f r e q u e n c y r e s p o n s e of the o p - a m p circuit and to measure its differ ential gain A and its 3-dB frequency f in PSpice, w e set the differential input voltage V to be a 1-V ac signal (with 0-V dc level), perform an ac-analysis simulation, and plot the output voltage m a g n i t u d e | V | versus frequency. Figure 7.53(a) shows the resulting frequency response. Accordingly, A = 13.96 x 1 0 V / V or 82.8 d B , and f = 256.9 k H z . Thus, this value of A is close to the value estimated using the large-signal differential transfer characteristic. d
H
1.0K
100 1.0 10 • dB(V(OUT))
10K
1.0M
100K
10M
100M
LOG
Frequency (Hz)
d
(a)
0 U T
3
d
H
d
An approximate value o f / Specifically,
H
can also be obtained using the expressions derived in Section 7.6.2.
f
= ~— 27r7? C
H
eq
(7.217) eq
where C
= C„ + C
e q
2
K5
+ C „ [ l + g (R 5
m5
II r
3
II (r
o5
Kl
+ (B+
l)R ))] 4
and R
eq
= * II r
II r
o2
2
K5
T h e values of the small-signal parameters as computed by PSpice can be found in the output file of a bias-point (or an ac-analysis) simulation. Using these values results in C = 338 pF, R = 2.91 k Q , and f = 161.7 kHz. However, this approximate value off is much smaller than the value computed by PSpice. The reason for this disagreement is that the foregoing expression f o r / was derived (in Section 7.6.2) using the equivalent differential half-circuit concept. How ever, the concept is accurate only when it is applied to a symmetrical circuit. The op-amp circuit in Fig. 7.51 is not symmetrical because the second gain stage formed by the differential pair Q4-Q5 has a load resistor R in the collector of Q only. T o verify that the expression f o r / # in Eq. (7.217) gives a close approximation fovf in the case of a symmetric circuit, w e insert a resistor R (whose size is equal to R ) in the collector of Q . Note that this will have only a minor effect on the dc operating point. The op-amp circuit with g having a collector resistor R is then simu lated in PSpice. Figure 7 3 3 ( b ) shows the resulting frequency response of this symmetric op amp e q
eq
H
H
H
3
5
H
3
3
4
4
3
FIGURE 7 . 5 3 Frequency response of (a) the op-amp circuit in Fig. 7.51 and (b) the op-amp circuit in Fig. 7.51 but with a resistor R' = R inserted in the collector of Q to make the op-amp circuit symmetrical. 3
3
4
772
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
S U M M A R Y
AMPLIFIERS
!.
7 7 3
where f = 155.7 kHz. Accordingly, in the ease of a perfectly symmetric op-amp circuit, the value of fn in Eq. (7.217) closely approximates the value computed by PSpice. Comparing the frequency responses of the nonsymmetric (Fig. 7.53a) and the symmetric (Fig. 7.53b) op-amp circuits, we note that the 3-dB frequency of the op amp drops from 256.9 kHz to 155.7 kHz when resistor R is inserted in the collector of Q to make the op-amp circuit symmetrical. This is because, with a resistor R , the collector of Q is no longer at signal ground and, hence, C^ experiences the Miller effect. Consequently, the high-frequency response of the op-amp circuit is degraded. Observe that in the preceding ac-analysis simulation, owing to the systematic offset inher ent in the design, the o p - a m p circuit is operating at an output dc voltage of 3.62 V. However, in an actual circuit implementation (with V = 0 ) , negative feedback is employed (see Chapters 2 and 8) and the output dc voltage is stabilized at zero. T h u s , the small-signal per formance of the o p - a m p circuit can be more accurately simulated b y biasing the circuit so as to force operation at this level of output voltage. This can be easily done by applying a differ ential dc input of -V . Superimposed on this dc input, w e can apply an ac signal to perform an ac-analysis simulation for the purpose of, for example, computing the differential gain and the 3-dB frequency. Finally, to compute the input c o m m o n - m o d e range of the op-amp circuit in Fig. 7.51, w e perform a dc-analysis simulation in PSpice with the input c o m m o n - m o d e voltage swept over the range -V to V , while maintaining V constant at —V in order to cancel the output offset voltage (as discussed earlier) and, thus, prevent premature saturation of the BJTs. T h e corre sponding output voltage V is plotted in Fig. 7.54(a). F r o m this c o m m o n - m o d e dc transfer characteristic w e find that the amplifier behaves linearly over the V range - 1 4 . 1 V to +8.9 V, which is therefore the i n p u t c o m m o n - m o d e r a n g e . In Example 7.4, w e noted that the upper limit of this range is determined by Q and Q saturating, whereas the lower limit is determined by Q saturating. T o verify this assertion, we requested PSpice to plot the values of the collectorbase voltages of these BJTs versus the input c o m m o n - m o d e voltage V . T h e results are shown in Fig. 7.54(b), from which w e note that our assertion is indeed correct (recall that an npn B I T enters its saturation region when its base-collector junction becomes forward biased, i.e., V >0). H
5V
3
4
3
4
4
CM
os
EE
cc
d
os
0 U T
CM
1
2
3
CM
BC
SUMMARY • V(C23:B)-V(C23:C) o V ( g l : B ) - V (gl:C) VJVCM (V)
•
(b) FIGURE 7 . 5 4 (a) The large-signal common-mode transfer characteristic of the op-amp circuit in Fig. 7.51. The differential input voltage V is set to -V = -260 LCV to prevent premature saturation, (b) The effect of the common-mode input voltage VCM on the linearity of the input stage of the op-amp circuit in Fig. 7.51. The basecollector voltage of Q and Q is shown as a function of VCM. The input stage of the op-amp circuit leaves the active region when the base-collector junction of either Q or Q becomes forward biased (i.e., when VBC SO). D
T
The differential-pair or differential-amplifier configura tion is the most widely used building block in analog IC design. The input stage of every op amp is a differential amplifier.
OS
3
X
3
•
There are two reasons for preferring differential to singleended amplifiers: Differential amplifiers are insensitive to
interference, and they do not need bypass and coupling capacitors. •
For a MOS (bipolar) pair biased by a current source I, each device operates at a drain (collector, assuming a = 1) current of 7 / 2 and a corresponding overdrive voltage V (no analog ,in bipolar). Each device has g = I/V (aI/2V , for bipolar) and r„ = \V \/(I/2). ov
m
T
A
ov
CHAPTER 7
774
S
DIFFERENTIAL A N D MULTISTAGE
With the two input terminals connected to a suitable dc voltage V , the bias current 7 of a perfectly symmetrical differential pair divides equally between the two transistors of the pair, resulting in a zero voltage difference between the two drains (collectors). To steer the current completely to one side of the pair, a difference input voltage v of at least J2V (4V for bipolar) is needed. cu
id
0V
AMPLIFIERS
PROBLEMS
Mismatches between the two sides of a differential pair result in a differential dc output voltage V even when the two input terminals are tied together and connected to a dc voltage V . This signifies the presence of an input offset voltage V = V /A . In a MOS pair there are three main sources for V : CM
os
0
d
os
Vgv _____D
id
I2
cu
ln
2
M
m
D
0
D
g(D
s
lcm
ss
\A \ cm
=
c
EE
EE
2R
RD/ SS
R
( C/2R
For the bipolar pair there are two main sources: AR
cm
cm
D
cm
cm
D
SS
D
D
ss
D
m
While the input differential resistance R of the MOS pair is infinite, that for the bipolar pair is only 2r but can be increased to 2(f5 + l)(r + R ) by including resistances R in the two emitters. The latter action, however, lowers A j . M
n
e
e
x
2
CM
ARr => Vn. = V
C
m
D2
s
m
D2
D2
=
m
7 . 4 For the differential amplifier specified in Problem 7.2, let v = 0 and v = v . Find the range of v needed to steer the bias current from one side of the pair to the other. At each end of this range, give the value of the voltage at the common-source terminal and the drain voltages. G2
Gl
id
id
D2
s
7.5 Consider the differential amplifier specified in Problem 7.1 with G grounded and v = v . Let v be adjusted to the value that causes i = 0 . 1 1 mA and i = 0.09 mA. Find the corresponding values of v , v , v , and hence v . What is the difference output voltage v - v l What is the voltage gain (v - v )/v l What value of v results in i = 0.09 mA and i = 0.11 mA? 2
G1
id
id
m
D2
GS2
s
id
GSl
D2
D2
m
Dl
m
id
id
D2
T
7.2 For the PMOS differential amplifier shown in Fig. P7.2 let V = - 0 . 8 V and k' W/L = 3.5 mAA^ . Neglect channellength modulation.
Rc
2
tp
AI
S
A/,
A popular circuit in both MOS and bipolar analog ICs is the current-mirror-loaded differential pair. It realizes a high differential gain t , ) and a \R 8m( o low common-mode gain, | A | =\i for the MOS circuit ( r / B R for the bipolar circuit), as well as performing the differential-to-single-ended conversion with no loss of gain.
(a) Q. (b) 0.5 2
p
For v = V = 0 V, find V and V for each of <2i and Also find v , v , and v . If the current source requires a minimum voltage of V, find the input common-mode range. Gl
G2
s
ov
m
GS
D2
N
r
+2.5 V
cm
o 4
3
ov
jd
m a x
ov
m
7.7 Use Eq. (7.23) to show that if the term involving v\ is to be kept to a maximum value of k then the maximum possible fractional change in the transistor current is given by
E E
fa!,,
0
The common-mode gain of the differential amplifier exhibits a transmission zero caused by the finite output resistance and capacitance of the bias current source; fz = T„ ss ss (t^EEREE for bipolar). Thus the CMRR has a pole at this relatively low frequency. C
7.6 The table providing the answers to Exercise 7.3 shows that as the maximum input signal to be applied to the differential pair is increased, linearity is maintained at the same level by operating at a higher V . If | v | is to be 150 mV, use the data in the table to determine the required V and the corresponding values of W/L and g . d
R
\ 1/2
0.7 mA
=
2jk(l-k)
and the corresponding maximum value of v is given by id
^Wmax
=
2jkV
ov
R
for the bipolar case) results.
EE
Taking the output differentially results in the perfectly matched case in zero A (infinite CMRR). Mismatches between the two sides of the pair make A finite even when the output is taken differentially: A mismatch AR causes | A | = (R /2R )(AR /R ); a mismatch Ag„, causes \A \ = (R /2R )(Ag /gJ. Corresponding expressions apply for the bipolar pah'.
Dl
CM
icm
ss
D2
c u
0
D
Dl
c u
0
An input common-mode signal v gives rise to drain (collector) voltage signals that are ideally equal and given by -v (R /2R ) [-v (R /2R ) for the bipolar pair], where R (R ) is die output resistance of the current source that supplies the bias current /. When the output is taken single-endedly a common-mode gain of magnitude
as
CM
c
The analysis of a differential amplifier to determine differential gain, differential input resistance, frequency response of differential gain, and so on is facilitated by employing the differential half-circuit, which is a common-source (common-emitter) transistor biased at 1/2.
icm
•
os
VÇY_ A(W/L) = -SZ2 W/L
II r ).
m
•
(a) Find V and V for each transistor. (b) For v = 0, find v , i , i , v , and v . (c) Repeat (b) for v = +1 V. (d) Repeat (b) for v = - 1 V. (e) What is the highest value of v for which Q and Q remain in saturation? (f) If current source I requires a minimum voltage of 0.3 V to operate properly, what is the lowest value allowed for v and hence for v 7
id
id
D
R
A(W/L) => V
D
n
x
id
ss
R
ov
CM
id
jd
S
2
id
n
DD
2
tn
and i = 0.15 mA; (e) i = 0 mA (Q_ just cuts off) and i 0.2 mA. For each case, find v , v , v , and (v - v ). D2
7.1 For an NMOS differential pair with a common-mode voltage v applied, as shown in Fig. 7.2, let V = V = 2.5 V, k' W/L = 3 mAA^ , V = 0.7 V, 7 = 0.2 mA, R = 5 k£2. and neglect channel-length modulation. n
r
CM
SECTION 7 . 1 : THE MOS DIFFERENTIAL PAIR
CM
T
Superimposing a differential input signal v on the dc common-mode input voltage V such that v = V + v /2 and v = V -v /2 causes a virtual signal ground to appear on the common source (emitter) connection. In response to v , the current in Q increases by g v /2 and the current in Q decreases by g v /2. Thus, voltage signals of ±g (R II r )v /2 develop at the two drains (collectors, with R replaced by R ). If the output voltage is taken single-endedly, that is, between one of the drains (collectors) and ground, a differential gain of \g (R [I r ) is realized. Taking the output differentially, that is, between the two drains (collectors) the differential gain realized is twice as large:
P R O B L E M S
0
AR . 9
775
Evaluate both expressions for k = 0.01, 0.1, and 0.2. 1
%i°
A multistage amplifier usually consists of three stages: an input stage having a high input resistance, a reasonably high gain, and, if differential, a high CMRR; an intermediate stage that realizes the bulk of the gain; and an output stage having a low output resistance. Many CMOS amplifiers serve to drive only small on-chip capacitive loads and hence do not need an output stage. In designing and analyzing a multistage amplifier; the loading effect of each stage on the one that precedes it must be taken into account.
Qi
7 . 8 An NMOS differential amplifier utilizes a bias current of 200 LiA. The devices have V, = 0.8 V,W= 100 Ltm, and L = 1.6 jtan, in a technology for which /U C = 90 tiA/V . Find V s, gm^ and the value of v for full-current switching. To what value should the bias current be changed in order to double the value of v for full-current switching?
-0%2
2
v o-
n
m
G
2kO.
"2kn
0X
u
id
D 7 . 9 Design the MOS differential amplifier of Fig. 7.5 to operate at V = 0.2 V and to provide a transconductance g of 1 mA/V. Specify the W/L ratios and the bias current. The technology available provides V, = 0.8 V and fi C = 90 jiAIN . ov
-2.5 V
m
FIGURE P 7 . 2
n
0X
2
e
7 . 3 For the differential amplifier specified in Problem 7.1 let v = 0 and v = v . Find the value of v that corresponds to each of the following situations: G2
G1
id
ld
7 . 1 0 Consider the NMOS differential pair illustrated in Fig. 7.5 under the conditions that 7 = 100 jiA, using FETs for which k' (W/L) = 400 ^ A ' V , and V, = 1 V. What is the voltage on the common-source connection for v = v = 0? 2 V? What is the relation between the drain currents in each 2
n
(a) i = i = 0.1 mA; (b) i = 0.15 mA and i = 0.05 mA; (c) im = 0.2 mA and i = 0 (Q just cuts off); (d) i = 0.05 mA m
D2
m
D2
D2
2
Dl
Gl
G2
776
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
of these situations? Now for v = 0 V, at what voltages must v be placed to reduce i by 10%? to increase i by 10%? What is the differential voltage, v = v - v , for which the ratio of drain currents i A is 1.0? 0.5? 0.9? 0.99? For the current ratio i /i 20.0, what differential input is required? G2
al
D2
D2
u
D2
Dl
SECTION 7 . 2 :
G2
cl
m
D
SMALL-SIGNAL OPERATION
OF THE M 0 S DIFFERENTIAL PAIR 7 . 1 1 An NMOS differential amplifier is operated at a bias current I of 0.5 mA and has a W/L ratio of 50, i C = 250 HAN , V 10 V, and R = 4 kQ. Find V , g , r and A . E n
A
D
ov
0X
m
0
rf
AMPLIFIERS
PROBLEMS
bias circuit that establishes an appropriate dc voltage at the drains of CJi and Q is not shown. Note that the equivalent differential half-circuit is an active-loaded common-source transistor of the type studied in Section 6.5. It is required to design the circuit to meet the following specifications: 2
(a) (b) (c) (d)
Differential gain A = 80 V/V. 7 ^ = 7 = 100 fiA. The dc voltage at the gates of Q and Q is +1.5 V. The dc voltage at the gates of Q , Q , and Q is - 1 . 5 V. d
6
7
m
ov
4
5
The technology available is specified as follows: )i C = 3 N C = 90 M / V ; V = \V \= 0.7 V, V = |V | = 20 V. Specify the required value of R and the W/L ratios for all transistors. Also specify I and | V \at which each transistor is operating. For dc bias calculations you may neglect channellength modulation. n
ox
2
p
0X
tn
tp
D
D 7 . 1 2 It is required to design an NMOS differential amplifier to operate with a differential input voltage that can be as high as 0.2 V while keeping the nonlinear term under the square root in Eq. (7.23) to a maximum of 0.1. A transconductance g of 3 mA/V is needed. Find the required values of V , I, and W/L. Assume that the technology available has p,,C = 100 pAIV . What differential gain A results when R = 5 k Q ? Assume X = 0. What is the resulting output signal corresponding to v at its maximum value?
3
An
d
D
id
GS
7 . 1 4 A design error has resulted in a gross mismatch in the circuit of Fig. P7.14. Specifically, Q has twice the W/L ratio of Q . If v is a small sine-wave signal, find: 2
y
ld
(a) I and I . (b) V for each of GJi and Q . (c) The differential gain A in terms of R , I, and m
D2
ov
2
d
D
V. ov
and
d
2
ov
p
m
d
D
ml
m
m
m2
m
cm
7.1 S For the differential amplifier shown in Fig. P7.2, let ft and Q have k' (WIL) = 3.5 m A / V , and assume that the bias current source has an output resistance of 30 kQ. Find V , g , \A \, \A \, and the CMRR (in dB) obtained with the output taken differentially. The drain resistances are known to have a mismatch of 2%. 2
777
Rm = RD- (AR /2). Also let g = g + (Ag /2) and g = 8m ~ (Ag /2). Follow an analysis process similar to that used to derive Eq. (7.64) to show that
cm
12*7 J 7 The differential amplifier in Fig. P7.17 utilizes a resistor R to establish a 1-mA dc bias current. Note that this amplifier uses a single 5-V supply and thus needs a dc common-mode voltage V . Transistors Q and Q have k'„W/L = 2.5 m A / V , V = 0.7 V, and 1 = 0 .
2R
y ss/y 8 m
R ) D
Note that this equation indicates that R can be deliberately varied to compensate for the initial variability in g and R , that is, to minimize A . (b) In a MOS differential amplifier for which R = 5 kQ and R = 25 kQ, the common-mode gain is measured and found to be 0.002 V/V. Find the percentage change required in one of the two drain resistors so as to reduce A to zero (or close to zero). D
m
D
cm
D
ss
an
ss
CM
x
7 . 1 ® Recalling that g of a MOSFET is given by m
2
8
(a) Find the required value of V . (b) Find the value of R that results in a differential gain A of 8 V/V. (c) Determine the dc voltage at the drains. (d) Determine the common-mode gain AV /AV . (Hint: You need to take l/g into account.) (e) Use the common-mode gain found in (d) to determine the change in V that results in Cj\ and Q entering the triode region. CM
D
d
D1
CM
5
V
DD
k' {^(V -V,) n
GS
we observe that there are two potential sources for a mis match between the g values in a differential pair: a mismatch A(W/L) in the (W/L) values and a mismatch AV, in the threshold voltage values. Hence show that m
CM
2
2
=
m
t
Ag
m
2
A
cm
2
0 * 7 . 1 3 Figure P7.13 shows a circuit for a differential amplifier with an active load. Here Q and Q form the differ ential pair while the current source transistors Q and Q form the active loads for <2i and Q , respectively. The dc x
d
Ap
1
BX
(a) If the output is taken single-endedly, find \A \, \A \,
CMRR. (b) If the output is taken differentially and there is a 1% mis match between the drain resistances, find \A \, \A \, and CMRR.
, -
m
8
m
=
A(W/L)
|
W/L
AV, Vv 0
Evaluate the worst-case fractional mismatch in g for a differ ential pair in which the (W/L) values have a tolerance o f + 1 % and the largest mismatch in V is specified to be 5 mV. Assume that the pair is operating at V = 0.25 V. If R = 5 kQ and R = 25 kQ, find the worst-case value of A . If the bias current 1=1 mA, find the corresponding worst-case CMRR. m
t
= 5V
A
ov
A
D
ss
+2.5 V
cm
A
SECTION 7 . 3 :
Ö
THE BJT DIFFERENTIAL PAIR
7 . 2 ® For the differential amplifier of Fig. 7.13(a) let I = 1 mA, V = 5 V, vat = - 2 V, R = 3 kQ, and Q = 100. Assume that the BJTs have v = 0.7 V at i = 1 mA. Find the voltage at the emitters and at the outputs.
3
cc
c
BE
c
7 . 2 1 For the circuit of Fig. 7.13(b) with an input of+1 V as indicated, and with 7 = 1 mA, V = 5V,R = 3 kQ, and B = 100, find the voltage at the emitters and the collector voltages. Assume that the BJTs have v = 0.7 V at i = 1 mA. cc
v j 2
o
1
Qi
Qi
2
-FJ
BE
C
c
7 . 2 2 Repeat Exercise 7.7 (page.X) for an input of - 0 . 3 V. 7 . 2 3 For the BJT differential amplifier of Fig. 7.12 find the value of the input differential signal, v = v - v , that causes i = 0.807. u
05
FIGURE
P7.17
Bl
B2
El
FIGURE P 7 . 1 4
-2.5 V
7 . 1 5 An NMOS differential pair is biased by a current source / = 0.2 mA having an output resistance R = 100 kQ. The amplifier has drain resistances R = 10 k Q , using tran sistors with k' W/L = 3 m A / V , and r that is large.
m
D
ss
D
FIGURE P 7 . 1 3
* 7 . 1 8 The objective of this problem is to determine the common-mode gain and hence the CMRR of the differen tial pair arising from a simultaneous mismatch in g and in R .
2
n
0
(a) Refer to the circuit in Fig. 7.11 and let the two drain resis tors be denoted R and R where R = R + (AR /2) and m
D2
Dl
D
D
B 7 . 2 4 Consider the differential amplifier of Fig. 7.12 and let the B JT P be very large: (a) What is the largest input common-mode signal that can be applied while the BJTs remain comfortably in the active region with v = 0? CB
CHAPTER 7
778
DIFFERENTIAL A N D
MULTISTAGE
(b) If an input difference signal is applied that is large enough to steer the current entirely to one side of the pair, what is the change in voltage at each collector (from the condition for which v = 0)? (c) If the available power supply V is 5 V, what value of IR should you choose in order to allow a common-mode input signal o f + 3 V? (d) For the value of IR found in (c), select values for I and R . Use the largest possible value for I subject to the constraint that the base current of each transistor (when I divides equally) should not exceed 2 /iA. Let ¡5= 100. id
cc
C
C
c
7 . 2 9 In a differential amplifier using a 6-mA emitter bias current source the two BJTs are not matched. Rather, one has one-and-a-half times the emitter junction area of the other. For a differential input signal of zero volts, what do the collector currents become? What difference input is needed to equalize the collector currents? Assume a=\.
El
El
El
u
El
id
ld
between the two collectors) of 200 V/V. The transistor B is specified to be at least 100. The available power supply is 10 V.
7 . 3 8 Find the voltage gain and input resistance of the amplifier in Fig. P7.38 assuming that 0 = 100.
7 . 3 3 For a differential amplifier to which a total difference signal of 10 mV is applied, what is the equivalent signal to its corresponding CE half-circuit? If the emitter current source is 100 t(A, what is r of the half-circuit? For a load resistance of 10 kQ in each collector, what is the half-circuit gain? What magnitude of signal output voltage would you expect at each collector?
+ 15 V i
c
* 7 . 3 0 Figure P7.30 shows a logic inverter based on the differential pair. Here, Q and Q form the differential pair, whereas 6J is an emitter follower that performs two functions: It shifts the level of the output voltage to make V and V centered on the reference voltage V , thus enabling one gate to drive another (this point will be explained in detail in Chapter 11), and it provides the inverter with a low output resistance. All transistors have V = 0.7 V at I = 1 mA and have 0 = 100. x
2
3
0H
0L
7 . 2 5 To provide insight into the possibility of nonlinear distortion resulting from large differential input signals applied to the differential amplifier of Fig. 7.12, evaluate the normalized change in the current i , Ai /I = (i - (1/2))//, for differential input signals v of 5, 10, 20, 30, and 40 mV. Provide a tabulation of the ratio ((Ai /I)/v ), which represents the proportional transconductance gain of the differential pair, versus v . Comment on the linearity of the differential pair as an amplifier.
779
PROBLEMS
AMPLIFIERS
R
BE
x
0
0H
x
0
cc
c
(a) For v sufficiently low that Q is cut off, find the value of the output voltage v . This is V . _ (b) For v, sufficiently high that Q is carrying all the current /, find the output voltage v . This is V . (c) Determine the value of v, that results in Q conducting 1% of /. This can be taken as V . (d) Determine the value of v, that results in Q conducting 99% of I. This can be taken as V . (e) Sketch and clearly label the breakpoints of the inverter voltage transfer characteristic. Calculate the values of the noise margins NM and NM . Note the judicious choice of the value of the reference voltage V . l
7"„34 A BJT differential amplifier is biased from a 2-mA constant-current source and includes a 100-Q resistor in each emitter. The collectors are connected to V via 5-kQ resistors. A differential input signal of 0.1 V is applied between the two bases.
0L
(a) Find the signal current in the emitters (i ) and the signal voltage v for each BJT. (b) What is the total emitter current in each BJT? (c) What is the signal voltage at each collector? Assume a = 1. (d) What is the voltage gain realized when the output is taken between the two collectors? e
be
FIGURE P 7 . 3 8
7 . 3 9 Derive an expression for the small-signal voltage gain v /vi of the circuit shown in Fig. P7.39 in two different ways: 0
x
0 7 . 2 6 Design the circuit of Fig. 7.12 to provide a differential output voltage (i.e., one taken between the two collectors) of 1 V when the-differential input signal is 10 mV. A current source of 2 mA and a positive supply of +10 V are available. What is the largest possible input common-mode voltage for which operation is as required? Assume a — 1.
1L
x
IH
H
L
R
D * 7 . 2 7 One of the trade-offs available in the design of the basic differential amplifier circuit of Fig. 7.12 is between the value of the voltage gain and the range of commonmode input voltage. The purpose of this problem is to demonstrate this trade-off.
(For the definitions of the parameters that are used to characterize the inverter VTC, refer to Section 1.7.) V
= 5V
rr
(a) Use Eqs. (7.72) and (7.73) to obtain i and i corresponding to a differential input signal of 5 mV (i.e., v -v = 5 mV). Assume 0 to be very high. Find the resulting voltage difference between the two collectors (v^ - v ), and divide this value by 5 mV to obtain the voltage gain in terms of (IR )(b) Find the maximum permitted value for v (Fig. 7.13a) while the transistors remain comfortably in the active mode with v = 0. Express this maximum in terms of V and the gain, and hence show that for a given value of V , the higher the gain achieved, the lower the common-mode range. Use this expression to find % corresponding to a gain magnitude of 100, 200, 300, and 400 WV. For each value, also give the required value of IR and the value of R for I = 1 mA. ci
a
m
B2
lkfU
:l
S 7 . 3 5 Design a BJT differential amplifier to amplify a differential input signal of 0.2 V and provide a differential output signal of 4 V. To ensure adequate linearity, it is required to limit the signal amplitude across each base-emitter junction to a maximum of 5 mV. Another design requirement is that the differential input resistance be at least 80 kQ. The BJTs available are specified to have 0 > 200. Give the circuit configuration and specify the values of all its components.
(a) as a differential amplifier (b) as a cascade of a common-collector stage Q common-base stage Q
t
and a
2
Assume that the BJTs are matched and have a current gain a. Verify that both approaches lead to the same result. Vcc
7 . 3 6 A particular differential amplifier operates from an emitter current source whose output resistance is 1 MQ. What resistance is associated with each common-mode half-circuit? For collector resistors of 20 kQ, what is the resulting common-mode gain for output taken (a) differentially, (b) single-endedly? 7 . 3 7 Find the voltage gain and the input resistance of the amplifier shown in Fig. P7.37 assuming P = 100.
m
cl
C
c u
CB
V O-
v,o
0
[öi
Q\ 2
<3V = 3.64V Ä
cc
cc
0
110 mA \ j l =
1 mA
M m a x
C
FIGURE P 7 . 3 9
7 . 4 0 The differential amplifier circuit of Fig. P7.40 utilizes a resistor connected to the negative power supply to establish the bias current I.
c
* 7 . 2 8 For the circuit in Fig. 7.12, assuming a = 1 and IR = 5 V, use Eqs. (7.67) and (7.68) to find i and i , and hence determine v„ = v - v for input differential signals v = v - v of 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, 30 mV, 35 mV, and 40 mV. Plot v„ versus v , and hence comment on the amplifier linearity. As another way of visualizing linearity, determine the gain (v /v ) versus v . Comment on the resulting graph.
FIGURE P 7 . 3 0
C
cl
C2
m
c2
cl
id
B2
7 . 3 1 A BJT differential amplifier uses a 300-tiA bias current. What is the value of g of each device? If 0 is 150, what is the differential input resistance?
(a) For v = v /2 and v = -v /2, where v is a small signal with zero average, find the magnitude of the differential gain, \v /v \.
D 7 . 3 2 Design the basic BJT differential amplifier circuit of Fig. 7.16 to provide a differential input resistance of at least 10 k Q and a differential voltage gain (with the output taken
(b) For v
Bl
m
id
0
id
id
id
0
t
m
B2
ld
id
=v
= v , find the magnitude of the common-
m
icm
mode gain, \v /v \. (c) Calculate the CMRR. 0
FIGURE P7.37
id
icm
780
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE AMPLIFIERS
PROBLEMS
<7™V
+5 V
(c) the differential input resistance (d) the common-mode gain to a single-ended output (e) the common-mode gain to a differential output
SECTION 7 . 4 : OTHER N0NIDEAL CHARACTERISTICS OF THE DIFFERENTIAL AMPLIFIER
7 . 4 3 In a differential-amplifier circuit resembling that shown in Fig. 7.23(a), the current generator represented by / and R consists of a simple common-emitter transistor operating at 100 jUA. For tills transistor, and those used in the differential pair, V = 200 V and B = 50. What common-mode input resistance would apply?
D 7 . 4 8 An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 kQ ± 1%. For the pair, k' w/L = 4 mA/V . A decision is to be made concerning the bias current / to be used, whether 200 /xA or 400 pA. For differential output, contrast the differential gain and input offset voltage for the two possibilities.
0 7 . 4 4 It is required to design a differential amplifier to provide the largest possible signal to a pair of 10-kQ load resistances. The input differential signal is a sinusoid of 5-mV peak amplitude which is applied to one input terminal while the other input terminal is grounded. The power supply available is 10 V. To determine the bias current required, 7, derive an expression for the total voltage at each of the collectors in terms of V and I in the presence of the input signal. Then impose the condition that both transistors should remain well out of saturation with a minimum v of approximately 0 V. Thus determine the required value of 7. For this design, what differential gain is achieved? What is the amplitude of the signal voltage obtained between the two collectors? Assume a = l.
D7.49 An NMOS amplifier, whose designed operating point is at V = 0.3 V, is suspected to have a variability of V, of ±5 mV, and of W/L and R (independently) of ± 2 % . What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero and thereby compensate for the uncertainties (including that of the other R ), what percentage change from nominal would you require? If by selection you reduced the contribution of the worst cause of offset by a factor of 10, what change in R would be needed?
EE
A
FIGURE P7.40
cc
(d) If v = 0.1 sin 2K x 60f + 0.005 sin 2K X lOOOi volts, v = 0.1 sin 2K x 60f - 0.005 sin 2K X lOOOf, volts, find v . B1
m
0
7 . 4 1 For the differential amplifier shown in Fig. P7.41, identify and sketch the differential half-Circuit and the Commonmode half-circuit. Find the differential gain, the differential input resistance, the common-mode gain, and the common-mode input resistance. For these transistors, B + 15 V
CB
P * 7 . 4 5 Design a BJT differential amplifier that provides two single-ended outputs (at the collectors). The amplifier is to have a differential gain (to each of the two outputs) of at least 100 V/V, a differential input resistance >10 k Q , and a common-mode gain (to each of the two outputs) no greater than 0.1 V/V. Use a 2-mA current source for biasing. Give the complete circuit with component values and suitable power supplies that allow for +2 V swing at each collector. Specify the minimum value that the output resistance of the bias current source must have. The BJTs available have ¡5 > 100. What is the value of the input common-mode resistance when the bias source has the lowest acceptable resistance? /
I
7 8 1
the resulting input offset voltage. Assume that the two transistors are intended to be biased at a V of about 10 V. CE
2
* 7.5 6 A differential amplifier is fed in a balanced or p u s h pull manner with the source resistance in series with each base being R . Show that a mismatch AR between the values of the two source resistances gives rise to an input offset voltage of approximately (I/2fi)AR . s
S
s
7 . 5 7 One approach to "offset correction" involves the adjustment of the values of R and R so as to reduce the differential output voltage to zero when both input terminals are grounded. This offset-nulling process can be accomplished by utilizing a potentiometer in the collector circuit, as shown in Fig. VI.51. W e wish to find the potentiometer setting, represented by the fraction x of its value connected in series with R , that is required for nulling the output offset voltage that results from: cl
-5 V
£.
ov
D
C2
cl
D
D
(a) R being 5% higher than nominal a n d i ? 5% lower than nominal (b) <2i having an area 10% larger than that of Q cl
C2
2
7.5© An NMOS differential pair operating at a bias current I of 100 /uA uses transistors for which k'„ = 100 jiAlY and W/L = 20, with V, = 0.8 V. Find the three components of input offset voltage under the conditions that AR /R = 5%, A(W/L)/(W/L) = 5%, and A V, = 5 mV. In the worst case, what might the total offset be? For the usual case of the three effects being independent, what is the offset likely to be? (Hint: For the latter situation, use a root-sum-of-squares computation.) 2
D
D
7 . 5 1 A differential amplifier using a 600-^iA emitter bias source uses two well-matched transistors but collector load resistors that are mismatched by 10%. What input offset voltage is required to reduce the differential output voltage to zero? 7.52 A differential amplifier using a 600-/M. emitter bias source uses two transistors whose scale currents I differ by 10%. If the two collector resistors are well matched, find the resulting input offset voltage. s
7 . 4 6 When the output of a BIT differential amplifier is taken differentially, its CMRR is found to be 40 dB higher than when the output is taken single-endedly. If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch be (in percent)? FIGURE P7.41
7 . 4 2 Consider the basic differential circuit in which the transistors have B = 200 and V = 200 V, with I = 0.5 mA, R = 1 M Q , and R = 20 kQ. Find: A
EE
c
* 7 o 4 7 In a particular BJT differential amplifier, a production error results in one of the transistors having an emitter-base junction area that is twice that of the other. With the inputs grounded, how will the emitter bias current split between the two transistors? If the output resistance of the current source is 1 M Q and the resistance in each collector (R ) is 12 kfi, find the common-mode gain obtained when the output is taken differentially. Assume a — I.
7.53 Modify Eq. (7.125) for the case of a differential amplifier having a resistance R connected in; the emitter of each transistor. Let the bias current source be 7. E
7.54 A differential amplifier uses two transistors whose B values are B and B . If everything else is matched, show that the input offset voltage is approximately V [ (1 / B ) - (1 /B )] • Evaluate V for B_ = 100 and B = 200. Assume the differential source resistance to be zero. x
2
T
os
x
2
7 . 5 8 A differential amplifier for which the total emitter bias current is 600 LIA uses transistors for which ß is specified to lie between 80 and 200. What is the largest possible input bias current? The smallest possible input bias current? The largest possible input offset current?
2
c
(a) the differential gain to a single-ended output (b) the differential gain to a differential output '
FIGURE P 7 . 5 7
* 7.5 5 A differential amplifier uses two transistors having V values of 100 V and 300 V. If everything else is matched, find A
* 7 . 5 9 A BJT differential amplifier, operating at a bias current of 500 fiA, employs collector resistors of 27 kQ (each) connected to a +15-V supply. The emitter current source employs a BJT whose emitter voltage is - 5 V. What are the
782
'
.'J
CHAPTER 7
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
PROBLEMS
positive and negative limits of the input common-mode range of the amplifier for differential signals of <20-mV peak amplitude, applied in a balanced or push-pull fashion? * * 7 . 6 0 In a particular BJT differential amplifier, a production error results in one of the transistors having an emitterbase junction area twice that of the other. With both inputs grounded, find the current in each of the two transistors and hence the dc offset voltage at the output, assuming that the collector resistances are equal. Use small-signal analysis to find the input voltage that would restore current balance to the differential pair. Repeat using large-signal analysis and compare results. Also find the input bias and offset currents assuming I = 0.1 mA and P\ = P = 100.
equivalent transconductance be 5 mA/V. Use ±5-V power supplies and BJTs that have P = 150 and V = 100 V. Give the complete circuit with component values and specify the differential input resistance R , the output resistance R , the open-circuit voltage gain A , the input bias current, the input common-mode range, and the common-mode input resistance. id
I
08
T
A
u
7 . 6 3 In a version of the active-loaded MOS differential amplifier shown in Fig. 7.28(a), all transistors have k'W/L = 0.2 mA/V and | V | = 20 V. For V = 5 V, with the inputs near ground, and (a) I = 100 pA or (b) I=400 p A , calculate the linear range of v„, the g of Q and Q , the output resistances of Q and Q , the total output resistance, and the voltage gain. A
DD
m
x
2
4
7 . 6 4 Consider the active-loaded MOS differential amplifier of Fig. 7.28(a) in two cases:
0
d
id
EE
FIGURE P 7 . 6 4
and for case (b)
x
CMRR =
JÎ
where V is the overdrive voltage that corresponds to a drain current of 7 / 2 . For k'W/L = 10 m A / V , / = 1 mA, and 10 V, find CMRR for both cases. ov
D * 7 . 6 5 Consider an active-loaded differential amplifier such as that shown in Fig. 7.28(a) with the bias current source implemented with the modified Wilson mirror of Fig. P7.64 with 7 = 100 p A . The transistors have |V,| = 0 . 7 V and k'iW/L) = 800 pAN . What is the lowest value of the total power supply (V + V ) that allows each transistor to operate with V \V \? 2
DD
n
ss
GS
* 7 . 6 6 (a) Sketch the circuit of an active-loaded MOS differential amplifier in which the input transistors are cascoded, and a cascode current mirror is used for the load, (b) Show that if all transistors are operated at an overdrive voltage V and have equal Early voltages | V |, the gain is given by ov
A
* 7 . 7 2 Consider the differential amplifier circuit of Fig. 7.32(a) with the two input terminals tied together and an input common-mode signal v applied. Let the output resistance of the bias current source be denoted by R , and let the P of the pnp transistors be denoted B . Assuming that P of the npn transistors is high, use the current transfer ratio of the mirror to show that there will be an output current of v /PpR . Thus, show that the common-mode transconductance is 1 /ppR . Use this result together with the differential transconductance G (derived in the text) to find an alternative measure of the common-mode rejection, unserve that this result differs from the CMRR expression in Eq. (7.174) by a factor of 2, which is simply the ratio of the output resistance for common-mode inputs (r ) and the output resistance for differential inputs (r // r ).
r
Recalling that for the simple mirror R = o \ and for the Wilson mirror R = g r r , and assuming that all transistors have the same | V | and k'W/L, show that for case (a) ss
o7
Ü2
r
d 5
(3>
wm
EE
icm
EE
2(V
A
/V
0
V
)
2
o5
A
CMRR = 2[ —
A
X 2
Q
Evaluate the gain for
V
o
v
=
0.25 V and
V
A
=
20 V.
7 . 6 7 The differential amplifier in Fig. 7.32(a) is operated with 7 = 100 p A , with devices for which V = 160 V and d = 100. What differential input resistance, output resistance, equivalent transconductance, and open-circuit voltage gain would you expect? What will the voltage gain be if the input resistance of the subsequent stage is 100 kQ? A
0 * 7 . 6 8 Design the circuit of Fig. 7.32(a) using a basic current mirror to implement the current source I. It is required that the
EE
-5V
FIGURE P 7 . 7 4
m
o4
o2
o4
D 7 . 7 5 Consider the bias design of the Wilson-loaded cascode differential amplifier shown in Fig. P7.74. (a) What is the largest signal voltage possible at the output without Q saturating? Assume that the CB junction conducts when the voltage across it exceeds 0.4 V. (b) What should the dc bias voltage established at the output (by an arrangement not shown) be in order to allow for positive output signal swing of 1.5 V? (c) What should the value of V be in order to allow for a negative output signal swing of 1.5 V? 7
* 7 . 7 3 Repeat Problem 7.72 for the case in which the current mirror is replaced with a Wilson mirror. Show that in this case the output current will be v /P R . Find the common-mode transconductance and theratio G /G . 2
=
~V =
EB
p
EE
mcm
(a) Current-source I is implemented with a simple current mirror. -(b) Current-source I is implemented with the modified Wilson current MINOR shown in Fig. P7.64.
m7
cm
2
ICM
A
d
ss
0
A
m
2
2
-o v
p
z
7
d
7 . 7 1 An active-loaded bipolar differential amplifier such as that shown in Fig. 7.32(a) has I = 0.5 mA, V = 120 V, and P = 150. Find G , R , A , and R . If the bias-current source is implemented with a simple npn current mirror, find R , A , and CMRR. If the amplifier is fed differentially with a source having a total of 10 k Q resistance (i.e., 5 k Q in series with the base lead of each of O and Q ), find the overall differential voltage gain.
W I T H ACTIVE LOAD
a
V
D 7 . 7 0 Modify the design of the amplifier in Problem 7.68 by connecting emitter-degeneration resistances of values that result in R = 100 k Q . What does A become?
2
D 7 . 6 2 In an active-loaded differential amplifier of the form shown in Fig. 7.28(a), all transistors are characterized by k'W/L = 3.2 m A / V , and | V 20 V. Find the bias current I for which the gain v /v = 80 V/V.
= +5
0
D * 7 . 6 9 Repeat the design of the amplifier specified in Problem 7.68 utilizing a Widlar current source [Fig. 6.62] to supply the bias current. Assume that the largest resistance available is 2 kQ.
07
cc
THE DIFFERENTIAL AMPLIFIER
783
d
id
SECTION 7 . 5 :
1
A
2
D 7 . 6 1 A large fraction of mass-produced differentialamplifier modules employing 20-kQ collector resistors is found to have an input offset voltage ranging from +3 mV to - 3 mV. If the gain of the input differential stage is 90 V/V, by what amount must one collector resistor be adjusted to reduce the input offset to zero? If an adjustment mechanism is devised that raises one collector resistor while correspondingly lowering the other, what resistance change is needed? Suggest a suitable circuit using the existing collector resistors and a potentiometer whose moving element is connected to V . What value of potentiometer resistance (specified to 1 significant digit) is appropriate?
Vrr
.
m
B I A S
7 . 7 4 Figure P7.74 shows a differential cascode amplifier with an active load formed by a Wilson current mirror. Utilizing the expressions derived in Chapter 6 for the output resistance of a bipolar cascode and the output resistance of the Wilson mirror, and assuming all transistors to be identical, show that the differential voltage gain A is given by d
(d) What is the upper limit on the input common-mode voltage
v p. ct
* 7 . 7 6 Figure P7.76 shows a modified cascode differential amplifier. Here ¿ 3 and Q are the cascode transistors. However, the manner in which Q is connected with its base current feeding the current mirror Q-,-Q results in very interesting input properties. Note that for simplicity the circuit is shown with the base of Q grounded. 4
3
A
d
Evaluate A
d
—
s
r
ßgm o
3
for the case I = 0.4 mA, P = 100, and V = 120 V. A
2
CHAPTER 7
784
DIFFERENTIAL A N D MULTISTAGE
PROBLEMS
AMPLIFIERS
SECTION 7 . 6 : FREQUENCY RESPONSE OF THE DIFFERENTIAL AMPLIFIER 7,8® A MOSFET differential amplifier such as that shown in Fig. 7.36(a) is biased with a current source I = 200 p A . The transistors have W/L = 25, k'„ = 128 pA/V , V = 20 V, C = 30 fF, C = 5 fF, and C = 5 fF. The drain resistors are 20 kQ each. Also, there is a 90-fF capacitive load between each drain and ground. 2
A
gd
gs
ib
(a) Find V and g for each transistor. (b) Find the differential gain A . (c) If the input signal source has a small resistance R and thus the frequency response is determined primarily by the output pole, estimate the 3-dB frequency f . (d) If, in a different situation, the amplifier is fed symmetri cally with a signal source of 40 kQ resistance (i.e., 20 kQ in series with each gate terminal), use the open-circuit timeconstants method to estimate f . ov
m
d
sig
H
IN
V[ o-
7 . 8 1 The amplifier specified in Problem 7.80 has R = 100 kQ and C = 0.2 pF. Find the 3-dB frequency of the CMRR. s s
7 . 8 2 A BJT differential amplifier operating with a 1-mA current source uses transistors for which B = 100, f = 600 MHz, C = 0.5 pF, and r = 100 Q. Each of the collector resistances is 10 kQ, and r is very large. The amplifier is fed in a sym metrical fashion with a source resistance of 10 kQ in series with each of the two input terminals.
0
T
u
x
a
FIGURE P 7 . 7 6
I
7
B
for p-channel MOSFETs is 10 V, | V \ for npn transistors is 120 V. Find G ,R , and A . A
m
0
d
a
m
(a) Sketch the differential half-circuit and its high-frequency equivalent circuit. (b) Determine the low-frequency value of the overall differ ential gain. (c) Use Miller's theorem to determine the input capacitance and hence estimate the 3-dB frequency f and the gainbandwidth product. H
b
i d
4
'0
2
7 . 7 7 Utilizing the expression for the current transfer ratio of the Wilson mirror derived in Section 6.12.3 (Eq. 6.193) derive an expression for the systematic offset voltage of a B JT differential amplifier that utilizes apnp Wilson current mirror load. Evaluate V for B = 50. os
e
K
m
7 . 8 5 A current-mirror-loaded MOS differential amplifier is biased with a current source 7 = 0.6 mA. The two NMOS tran sistors of the differential pair are operating at V = 0.3 V, and the PMOS devices of the mirror are operating at V = 0.5 V. The Early voltage V = \V \ = 9 V. The total capacitance at the input node of the mirror is 0.1 pF and that at the output node of the amplifier is 0.2 pF. Find the dc value and the fre quencies of the poles and zero of the differential voltage gain. ov
ov
An
a,
H
x
7 . 8 8 Consider the circuit of Fig. P7.88 for the case: 7 = 200
pA
and
V
o v
l(Ru
g
+
gd
H
r )\\RinKl+G R )+R x
m
c
c
where %
=
(B+l)(R
+
e
r) e
v
o S
0
The resistance R seen by C„ is given by T
d
n
7.79 let V
DD
For the BiCMOS differential amplifier in Fig. P7.79 = V = 3V,I= 0.4 mA, k'W/L = 6.4 m A / V ; IV J
- V 'ss ,
2
SS
FIGURE P 7 . 7 9
R
R
s i
„ + r
= r \\ —
1 +
x
+
R
e
- - K
gm e
Also determine the gain-bandwidth product.
= 0.25
V, R
sig
= 200
kQ,
R
D
= 50 kQ,
C
gs
=
C = 1 pF. Find the dc gain, the high-frequency poles, and an estimate oif .
u
=
is biased by a current source 1 MQ and an output capaci gain exhibits a dominant pole of the CMRR?
7 . 8 7 For the differential amplifier specified in Problem 7.82, find the dc gain a n d / when the circuit is modified by elimi nating the collector resistor of the left-hand-side transistor and the input signal is fed to the base of the left-hand-side transistor while the base of the other transistor in the pair is grounded. Let the source resistance be 20 kQ and neglect r . (Hint: Refer to Fig. 6.57.)
4
m
Ap
7 . 8 6 A differential amplifier having an output resistance of tance of 10 pF. The differential at 500 kHz. What are the poles
7 . 8 3 The differential amplifier circuit specified in Prob lem 7.82 is modified by including 100-Q resistor in each of the emitters. Determine the low-frequency value of the over all differential voltage gain; Also, use the method of opencircuit time-constants to obtain an estimate f o r / . Toward that end, note that the resistance 7? seen by C„ is given by
BIAS
A
e
e
H
7 . 7 8 For the folded-cascode differential amplifier of Fig. 7.35, find the value of V" that results in the largest possible positive output swing, while keeping Q , Q , and the pnp tran sistors, that realize the current sources out of saturation. Assume cc = VEE = 5 V. If the dc level at the output is 0 V, find the maximum allowable output signal swing. For I = 0.4 mA, B = 50, i% = 150, and V = 120 V find G , R ^ , R , R , and A . P
785
D 7 . 8 4 It is required to increase the 3-dB frequency of the differential amplifier specified in Problem 7.82 to 1 MHz by adding an emitter resistance R . Use the open-circuit timeconstants method to perform this design. Specifically, use the formulas for and R given in the statement for Problem 7.83 to determine the required value of the factor (1 + g R ) and hence find R . Make appropriate approximations to simplify the calculations. What does the dc gain become? Also deter mine the resulting gain-bandwidth product.
P
3
1
H
ss
(a) With v =OV dc, find the input bias current I assuming all transistors have equal value of B. Compare the case with out the Q -Q connection. (b) With »j = 0 V (dc) + v , find the input signal current i and hence the input differential resistance R . Compare with the case without the Qj-Qn connection. (Observe that Q arranges that the emitter currents of Q_ and Q are very nearly the same!)
y j
F I G U R E P7.88
786
CHAPTER 7
fcl?
DIFFERENTIAL A N D MULTISTAGE
AMPLIFIERS
PROBLEMS
7 8 7
+5 V
~V /2
V /2
sig
sig
FIGURE P7.95 FIGURE P 7 . 8 9
that a current g AV, appears at the output of the first stage. What is the corresponding input offset voltage? Evaluate this offset voltage for the circuit specified in Example 7.3 for AV, = 2 m V . (Use the results of Example 7.3.) m3
7 . 8 9 For the circuit in Fig. P7.89, let the bias be such that each transistor is operating at \QQ-(iA collector current. Let the BJTs have B = 200, f = 600 MHz, and C = 0.2 pF, and neglect r and r . Also, R = R = 50 kI2. Find the low-frequency gain, the input differential resistance, the high-frequency poles, and an estimate off . T
a
x
sig
p
c
H
SECTION 7 . 7 : MULTISTAGE AMPLIFIERS 7 . 9 0 Consider the circuit in Fig. 7.40 with the device geom etries (in (an) shown at the bottom of this page: Let 7REF = 225 (lA, \V,\ = 0.75 V for all devices, (i C = 9 V for all devices, 180 fiA/V-, (i C = 60 (lA/V V = 1.5 V. Determine the width of Q , W, that will ensure that the op amp will not have a systematic offset volt age. Then, for all devices.evaluateI , )V \, \V \, g , and r„. Provide your results in a table similar to Table 7.1. Also find Aj, A , the dc open-loop voltage gain, the input commonmode range, and the output voltage range. Neglect the effect of V on the bias current. n
p
0X
0X
ss
6
D
0V
GS
m
2
A
0 * 7 . 9 1 In a particular design of the CMOS op amp of Fig. 7.40 the designer wishes to investigate the effects of
increasing the W/L ratio of both Q and Q by a factor of 4. Assuming that all other parameters are kept unchanged, refer to Example 7.3 to help you answer the following questions: x
2
I W/L
Q.
30/0.5
Q
2
30/0.5
Q
3
10/0.5
Q
4
10/0.5
m
(a) Find the resulting change in | V | and in g of <2i and Q . (b) What change results in the voltage gain of the input stage? In the overall voltage gain? (c) What is the effect on the input offset voltages? (You might wish to refer to Section 7.4). (d) Iff, is to be kept unchanged, how must C be changed? ov
m
2
c
7 . 9 2 Consider the amplifier of Fig. 7.40, whose parameters are specified in Example 7.3. If a manufacturing error results in the W/L ratio of Q being 50/0.8, find the current that Q will now conduct. Thus find the systematic offset voltage that will appear at the output. (Use the results of Example 7.3.) Assuming that the open-loop gain will remain approximately unchanged from the value found in Example 7.3, find the cor responding value of input offset voltage, V . 7
7
os
7 . 9 3 Consider the input stage of the CMOS op amp in Fig. 7.40 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q and Q have a mismatch AV . Show 3
A
t
7 . 9 4 A CMOS op amp with the topology in Fig. 7.40 has Sm\ = gmi = 1 mA/V, g = 3 mA/V, the total capacitance between node D and ground = 0.2 pF, and the total capacitance between the output node and ground = 3 pF. Find the value of C that results iaf, = 50 MHz and verify that/, is lower t h a n / a n d / .
Q
s
60/0.5
Q
6
W/0.5
Q
7
60/0.5
Q
8
60/0.5 j
9
i2
n
2
p
DD
ss
B
B
l0
n
t2
l2
i3
w
8
m6
2
c
z
K
* 7 . 9 5 Figure P7.95 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig. 7.40. Here, the input differential pair Q_-Q is loaded in a current mirror formed by Q and 6j . The second stage is formed by the current-sourceloaded common-emitter transistor Q . Unlike the CMOS circuit, here there is an output stage formed by the emitter follower Q . Capacitor C is placed in the negative-feedback path of Q and thus is Miller-multiplied by the gain of Q . The resulting large capacitance forms a dominant low-frequency pole with r , thus providing the required uniform -20-dB/decade gain rolloff. All transistors have B = 100, | V \ = 0.7 V, and r- ="°°.
7 . 9 7 A BJT differential amplifier, biased to have r = 50 Q and utilizing two 100-Q emitter resistors and 5-kii loads, drives a second differential stage biased to have r = 20 Q. All BJTs have /3= 120. What is the voltage gain of the first stage? Also find the input resistance of the first stage, and the current gain from the input of the first stage to the collectors of the second stage. e
e
2
3
4
5
6
c
5
5
n5
BE
0
(a) For inputs grounded and output held at 0 V (by negative feedback, not shown) find the emitter currents of all transistors. (b) Calculate the dc gain of the amplifier with 7^ = 1 0 kQ. (c) With R as in (b), find the value of C to obtain a 3-dB frequency of 100 Hz. What is the value off, that results? L
Transistor
are to be identical and must have the same g as Q_ and Q . Transistor Q is to be four times as wide as Qi3- Let k' = 3k = 180 (lA/V , and V = V = 1.5 V. Find the required value of R . What is the voltage drop across R 7 Also specify the W/L ratios of Q , Q , Q , and Q and give the expected dc voltages at the gates of Q , Q , and g .
7 . 9 8 In the multistage amplifier of Fig. 7.43, emitter resistors are to be introduced—100 Q in the emitter lead of each of the first-stage transistors and 25 Q. for each of the secondstage transistors. What is the effect on input resistance, the voltage gain of the first stage, and the overall voltage gain? Use the bias values found in Example 7.4. D 7 . 9 9 Consider the circuit of Fig. 7.43 and its output resis tance. Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor of 2? What will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to approximately its prior value?
c
0 7 . 9 6 It is required to design the circuit of Fig. 7.42 to pro vide a bias current I of 225 (lA with Q_ and Q as matched devices having W/L = 60/0.5. Transistors Q , Q , and Q B
9
w
n
n
0 * 7 . 1 0 0 (a) If, in the multistage amplifier of Fig. 7.43, the resistor R is replaced by a constant-current source = 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become? 5
CHAPTER 7
788
PROBLEMS DIFFERENTIAL
A N D MULTISTAGE
AMPLIFIERS
+5 V
+ 10V
ov
lOkfl
0
-10V FIGURE P 7 . 1 0 1
Assume that the output resistance of the current source is very high. Use the results of Example 7.5, (b) With the modification suggested in (a), what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 Q to ground? The origi nal amplifier (before modification) has an output resistance of 152 Q. and a voltage gain of 8513 V/V. What is its gain when loaded by 100 O? Comment. Use j3= 100. * 7 . 1 0 1 Figure P7.101 shows a three-stage amplifier in which the stages are directly coupled. The amplifier, how ever, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest.
about 0 V. Find R so that the reference current I is 100 /JA. What are the voltages at all the labeled nodes? (b) Provide in tabular form the bias currents in all transistors together with g and r for the signal transistors (Q , Q , Q , QA, and Q ) and r for Q , Q , and Q . (c) Now, using P = 100, find the voltage gain v /(v+ - v_), and in the process, verify the polarity of the input terminals. (d) Find the input and output resistances. (e) Find the input common-mode range for linear operation. (f) For no load, what is the range of available output voltages, assuming | V | = 0 . 3 V? (g) Now consider the situation with a load resistance connected from the output to ground. At the positive and negative limits of the output signal swing, find the smallest load resistance that can be driven if one or the other of Q or Q is allowed to cut off. MP
m
a
0
S
X
C
D
BE
0
3
FIGURE P 7 . 1 0 2
0
+5 V
C £ s a t
X
(a) Find the dc bias current in each of the three transistors. Also find the dc voltage at the output. Assume j V \ = 0.7 V, P = 100, and neglect the Early effect. (b) Find the input resistance and the output resistance. (c) Use the current-gain method to evaluate the voltage gain v /v . (d) Find the frequency of the high-frequency pole formed at the interface between the first and the second stages. Assume that C ^ = 2 pF and C = 10 pF.
2
G
2
0 * * * 7 . 1 03 In the CMOS op amp shown in Fig. P7.103, all MOS devices have | V,| = 1 V, ji C = 2 o C = 40 pAN , \V \ = 50 V, and L = 5 /an. Device widths are indicated on the diagram as multiples of W, where W = 5 /mi. 2
n
ox
(
p
OT
A
t
%2
D * * * 7 . 1 0 2 For the circuit shown in Fig. P7.102, which uses a folded cascode involving transistor Q , all transistors h a v e \ V \ = 0.7 Vfor the currents involved, V = 200 V, and P= 100. The circuit is relatively conventional except for Q , which operates in a Class B mode (we will study this in Chapter 14) to provide an increased negative output swing for low-resistance loads. 3
B E
A
5
(a) Perform a bias calculation assuming | V g | = 0.7 V, high A VA = °°, v+ = v_ = 0 V, and v is stabilized by feedback to £
0
(a) Design R to provide a 10-/iA reference current. (b) Assuming v = 0 V, as established by external feedback, perform a bias analysis, finding all the labeled node voltages, V and I for all transistors. (c) Provide in table form 7 , V , g,„, and r for all devices. (d) Calculate the voltage gain v /(v v_), the input resistance, and the output resistance. (e) What is the input common-mode range? (f) What is the output signal range for no load? (g) For what load resistance connected to ground is the output negative voltage limited to - 1 V before Q-, begins to conduct? (h) For a load resistance one-tenth of that found in (g), what is the output signal swing? 0
GS
D
0
GS
0
0
+
-5 V FIGURE P 7 . 1 0 3
..I
789
WÊÊÊÊSmmm
«4L. 'ÙÊL. .-iJlL . JBL:
Feedback Introduction 8.1
8.8
S o m e P r o p e r t i e s of N e g a t i v e
8.9
8.4
8.5
The Series-Series Feedback Amplifier
8.6
802
811
The Shunt-Shunt and Shunt-Series Feedback Amplifiers
T h e Stability P r o b l e m
834
Effect of F e e d b a c k o n t h e 836
8 . 1 0 Stability S t u d y U s i n g B o d e Plots
798
The Series-Shunt Feedback Amplifier
831
Amplifier Poles
795
The Four Basic Feedback Topologies
Determining the L o o p Gain
792
Feedback 8.3
8.7
The General Feedback Structure
8.2
791
8.11
845
Frequency Compensation
849
8.12 S P I C E Simulation Example
855
Summary
859
Problems
860
818
INTRODUCTION M o s t p h y s i c a l s y s t e m s incorporate s o m e form of feedback. It is interesting to note, t h o u g h , that the t h e o r y o f n e g a t i v e f e e d b a c k h a s b e e n d e v e l o p e d b y e l e c t r o n i c s e n g i n e e r s . In h i s search for m e t h o d s for t h e d e s i g n of amplifiers w i t h stable g a i n for u s e in t e l e p h o n e r e p e a t e r s , H a r o l d B l a c k , an e l e c t r o n i c s e n g i n e e r w i t h the W e s t e r n E l e c t r i c C o m p a n y , i n v e n t e d t h e f e e d b a c k amplifier in 1 9 2 8 . S i n c e t h e n t h e t e c h n i q u e h a s b e e n so w i d e l y u s e d that it is a l m o s t i m p o s s i b l e to t h i n k of e l e c t r o n i c circuits w i t h o u t s o m e form of f e e d b a c k , either i m p l i c i t or explicit. F u r t h e r m o r e , t h e c o n c e p t of f e e d b a c k a n d its a s s o c i a t e d t h e o r y are c u r r e n t l y u s e d in areas o t h e r than e n g i n e e r i n g , s u c h as in the m o d e l i n g of b i o l o g i c a l systems.
7 9 2
CHAPTER
8
8.1
FEEDBACK
F e e d b a c k can b e either n e g a t i v e ( d e g e n e r a t i v e ) or positive (regenerative). In amplifier design, negative feedback is applied to effect o n e or m o r e of the following properties: 1. Desensitize
THE GENERAL
--
source
the gain: that is, m a k e the v a l u e of the gain less sensitive to variations in
Load
•i
-J
FEEDBACK STRUCTURE
—,
the value of circuit c o m p o n e n t s , such as m i g h t b e c a u s e d b y c h a n g e s in temperature x
f
2. Reduce nonlinear distortion: that is, m a k e the output proportional to the input (in other w o r d s , m a k e the gain constant, i n d e p e n d e n t of signal level). 3. Reduce the effect of noise: that is, m i n i m i z e the contribution to the output of unwanted electric signals generated, either by the circuit components themselves, or by extraneous interference. 4. Control the input and output impedances: that is, raise or l o w e r the input and output i m p e d a n c e s b y the selection of an appropriate feedback topology. 5. Extend
the bandwidth
-<— ft
FIGURE 8.1 General structure of the feedback amplifier. This is a signal-flow diagram, and the quantities x represent either voltage or current signals. The output x is fed to t h e load as well as to a f e e d b a c k n e t w o r k , w h i c h p r o d u c e s a s a m p l e of 0
of the amplifier.
the output. T h i s s a m p l e ^ is related to x b y the f e e d b a c k factor B, 0
All of the desirable properties above are obtained at the expense of a reduction in gain. It will b e s h o w n that the gain-reduction factor, called t h e a m o u n t of f e e d b a c k , is the factor by w h i c h t h e circuit is desensitized, b y w h i c h the input i m p e d a n c e of a voltage amplifier is increased, b y w h i c h the b a n d w i d t h is extended, and so on. In short, the basic idea of nega tive feedback is to trade off gain for other desirable properties. This c h a p t e r is devoted to the study of negative-feedback amplifiers: their analysis, design, and characteristics. U n d e r certain conditions, the negative feedback in an amplifier can b e c o m e positive and of such a magnitude as to cause oscillation. In fact, in Chapter 13 w e will study the use of posi tive feedback in the design of oscillators and bistable circuits. Here, in this chapter, however, w e are interested in the design of stable amplifiers. W e shall therefore study the stability p r o b l e m of negative-feedback amplifiers and their potential for oscillation. It should n o t b e implied, h o w e v e r , that positive f e e d b a c k a l w a y s leads to instability. In fact, positive feedback is quite useful in a n u m b e r of n o n r e g e n e r a t i v e applications, such as the design of active filters, w h i c h are studied in C h a p t e r 12. Before w e b e g i n our study of n e g a t i v e feedback, w e w i s h t o r e m i n d the r e a d e r that we h a v e already e n c o u n t e r e d n e g a t i v e feedback in a n u m b e r of applications. A l m o s t all o p - a m p circuits e m p l o y n e g a t i v e feedback. A n o t h e r p o p u l a r application of n e g a t i v e feedback is the u s e of the emitter resistance R to stabilize t h e bias p o i n t of bipolar transistors and to increase the input resistance, b a n d w i d t h , and linearity of a B J T amplifier. In addition, the source follower and the emitter follower both employ a large amount of negative feedback. The question then arises about the n e e d for a formal study of negative feedback. A s will b e appre ciated b y t h e e n d of this chapter, t h e formal study of f e e d b a c k p r o v i d e s an invaluable tool for the analysis a n d design of electronic circuits. A l s o , the insight gained b y thinking in t e r m s of feedback c a n b e e x t r e m e l y profitable.
Xf = px
(8.2)
0
The feedback signal x is subtracted from t h e source signal x , w h i c h is t h e input to the c o m plete feedback amplifier, to p r o d u c e the signal x w h i c h is t h e input to the basic amplifier, f
s
1
h
x. = x -x s
(8.3)
f
Here w e n o t e that it is this subtraction that m a k e s t h e feedback negative. In essence, n e g a tive feedback r e d u c e s t h e signal that appears at t h e input of the basic amplifier. Implicit in the description a b o v e is that the source, the load, a n d the feedback n e t w o r k do not load t h e b a s i c amplifier. T h a t is, t h e gain A d o e s n o t d e p e n d o n any of these three net works. In practice this will n o t b e the case, and w e shall h a v e to find a m e t h o d for casting a real circuit into the ideal structure depicted in Fig. 8.1. F i g u r e 8.1 also implies that the for ward transmission occurs entirely t h r o u g h the basic amplifier and t h e r e v e r s e transmission occurs entirely t h r o u g h the feedback n e t w o r k . T h e gain of the feedback amplifier can b e obtained b y c o m b i n i n g E q s . (8.1) through (8.3): A
f
3
=. - ° = x
(8.4) l+A/3
s
E
f
8.1 THE GENERAL FEEDBACK STRUCTURE
F i g u r e 8.1 s h o w s t h e basic structure of a f e e d b a c k amplifier. R a t h e r than s h o w i n g voltages a n d currents, F i g . 8.1 is a signal-flow d i a g r a m , w h e r e e a c h of t h e quantities x can represent either a v o l t a g e or a current signal. T h e open-loop amplifier h a s a gain A; thus its o u t p u t ^ is related to t h e input x b y t
(8.1)
The quantity Aft is called the l o o p g a i n , a n a m e that follows from Fig. 8.1. F o r t h e f e e d b a c k to be negative, t h e l o o p gain AB should b e positive; that is, the f e e d b a c k signal x should have t h e s a m e sign as x , thus resulting in a smaller difference signal x . E q u a t i o n (8.4) indi cates that for positive A B t h e gain-wifh-feedback A will b e smaller than the open-loop gain A by the quantity 1 + A/3, w h i c h is called the a m o u n t of f e e d b a c k . If, as is the c a s e in m a n y circuits, the loop gain AB is large, AB > 1, then from E q . (8.4) it follows that Af ===== 1 / j S . w h i c h is a very interesting result: The gain of the feedback ampli fier is almost entirely determined by the feedback network. Since t h e feedback n e t w o r k u s u ally consists of p a s s i v e c o m p o n e n t s , w h i c h usually can b e c h o s e n to b e as accurate as o n e wishes, t h e a d v a n t a g e of n e g a t i v e feedback in obtaining accurate, predictable, and stable f
s
t
f
In earlier chapters, we used the subscript "sig" for quantities associated with the signal source (e.g., v and R ). We did that to avoid confusion with the subscript "s," which is usually used with FETs to denote quantities associated with the source terminal of the transistor. At this point, however, it is expected that readers have become sufficiently familiar with the subject that the possibility of confu sion is minimal. Therefore, we will revert to using the simpler subscript s for signal-source quantifies. sig
sig
_'}\
793
8.2
794
CHAPTER 8
S O M E PROPERTIES
OF NEGATIVE
FEEDBACK
FEEDBACK
gain should b e apparent. In other w o r d s , t h e overall gain will h a v e very little dependence on the gain of t h e basic amplifier, A, a desirable property b e c a u s e the gain A is usually a function of m a n y manufacturing and application p a r a m e t e r s , s o m e of w h i c h m i g h t h a v e wide tolerances. W e h a v e seen a dramatic illustration of all of these effects in o p - a m p circuits w h e r e the c l o s e d - l o o p gain (which is another n a m e for the gain-with-feedback) is almost entirely determined b y the feedback e l e m e n t s .
§ | | 8.2
E q u a t i o n s (8.1) t h r o u g h (8.3) can b e c o m b i n e d to obtain the following expression for the feedback signal xf.
8.2.1 Gain Desensitivity
AP
/
T h u s for A¡3 > 1 w e see that x — x , w h i c h i m p l i e s that the signal x at the input of the basic amplifier is reduced to almost zero. T h u s if a large a m o u n t of negative feedback is employed, the feedback signal x b e c o m e s an a l m o s t identical replica of the input signal x . A n outcome of this p r o p e r t y is the tracking of the t w o input terminals of an op a m p . T h e difference b e t w e e n x a n d x , w h i c h is x is s o m e t i m e s referred to as t h e "error signal." Accordingly, the input differencing circuit is often also called a c o m p a r i s o n circuit. (It is also k n o w n as a m i x e r . ) A n expression for x, can b e easily deteirnined as f
s
t
f
s
f
SOME PROPERTIES OF NEGATIVE FEEDBACK
The properties of negative feedback w e r e m e n t i o n e d in t h e Introduction. In t h e following, we shall consider s o m e of these properties in m o r e detail.
The effect of negative feedback o n desensitizing t h e closed-loop gain w a s d e m o n s t r a t e d in Exercise 8.1, w h e r e w e s a w that a 2 0 % reduction in t h e gain of t h e b a s i c amplifier g a v e rise to only a 0 . 0 2 % reduction in the gain of t h e c l o s e d - l o o p amplifier. T h i s sensitivity-reduction property can b e analytically established as follows: A s s u m e that f3 is constant. T a k i n g differentials of b o t h sides of E q . (8.4) results in
dA =
b
^ £
1
=
-
l+A/3
(8.6)
s
dA
(l+A/3)
f
1
(8.7)
Dividing Eq. (8.7) by Eq. (8.4) yields
A -' ;
— ^ —
f
s
f g
g )
A
which says that the p e r c e n t a g e c h a n g e in A (due to variations in s o m e circuit parameter) is f
from w h i c h w e can verify that for A[3 > 1, x b e c o m e s very small. O b s e r v e that negative feedback r e d u c e s t h e signal that appeal's at the input terminals of the basic amplifier by the a m o u n t of feedback, (1 + AB). t
smaller than the p e r c e n t a g e c h a n g e in A b y the a m o u n t of feedback. F o r this r e a s o n the amount of feedback, 1 + A/3, is also k n o w n as the desensitivity factor.
8.2.2 Bandwidth Extension Consider an amplifier w h o s e high-frequency r e s p o n s e is characterized b y a single pole. Its gain at m i d and high frequencies can be expressed as A(s) 8.1
The noninverting op-amp configuration shown in Fig. E8.1 provides a direct implementation of the feedback loop of Fig. 8.1. (a) A s s u m e that the op a m p has infinite input resistance and zero output resistance. Find an expression for the feedback factor B. (b) If the open-loop voltage gain A = 10 , find R /Ri to obtain a closedtloop voltage gain A of 10. (c) W h a t is the amount of feedback in decibels? (d) If V = 1 V, find V , V , and V). (e) TEA decreases b y 2 0 % , what is the corresponding decrease in Afl 4
A
=
m
(8.9)
l+s/co
H
where A
M
d e n o t e s the m i d b a n d gain and co is the u p p e r 3-dB frequency. A p p l i c a t i o n of H
negative feedback, w i t h a f r e q u e n c y - i n d e p e n d e n t factor B, a r o u n d this amplifier results in a
2
f
s
0
f
closed-loop gain A (s) f
given b y A (s) A
f
(
S
)
l pA(s)
~
+
Substituting for A(s) from E q . (8.9) results, after a little m a n i p u l a t i o n , in
A As) = fK
A / ( 1 + A p) l + s/co (\ + A p) M
M
H
M
Thus the feedback amplifier will h a v e a m i d b a n d gain of A /( M
1 + A [3) M
and an u p p e r 3-dB
frequency a>Hf g i v e n b y
co = co (l+A p) Hf
H
(8.11)
M
It follows that t h e u p p e r 3-dB frequency i s increased b y a factor equal to the a m o u n t of ~
Ans. (a) ß = R /(R l
l
FIGURE E8.1
+ R ); (b) 9.01; (c) 60 dB; (d) 10 V, 0.999 V, 0.001 V; (e) 0.02% 2
feedback. Similarly, it c a n b e s h o w n that if t h e o p e n - l o o p g a i n is characterized b y a d o m i n a n t lowfrequency p o l e g i v i n g rise to a l o w e r 3-dB frequency co , then t h e feedback amplifier will L
7 9 6
CHAPTER 8
FEEDBACK
8.2
h a v e a l o w e r 3-dB frequency
co , Lf
s
S/N
N o t e that the amplifier b a n d w i d t h is i n c r e a s e d b y the s a m e factor by w h i c h its midband gain is decreased, maintaining the gain-bandwidth product at a constant value.
•
i g n a l - t o - n o i s e r a t i o for this amplifier is
03, (8.12)
S O M E PROPERTIES O F N E G A T I V E F E E D B A C K
= V /V s
(8.13)
n
Consider next t h e circuit in F i g . 8.2(b). H e r e w e a s s u m e that it is p o s s i b l e to b u i l d another a m
\
t n
p l i f i e r stage w i t h gain A
2
that does not suffer from the n o i s e p r o b l e m . If this is t h e case,
e n w e m a y p r e c e d e our original amplifier A j b y t h e clean amplifier A
2
and apply n e g a t i v e
feedback a r o u n d t h e overall c a s c a d e of such an a m o u n t as to k e e p the overall gain constant. ¿1
The output v o l t a g e of the circuit in F i g . 8.2(b) c a n b e found b y superposition:
-FFNF
A A
0
\
\
;
JDO.i
A
A l
+V
S
^ — l+A_A fi
n
0
Consider the noninverting op-amp circuit of Exercise 8.1. Let the open-loop gain A have a Jow-frequenef • value of JO and a uniform -6-dB/octave rolloff at high frequencies with a 3-dB frequency of 100 Hz Find the low-frequency gain and the upper 3-dB frequency of a closed-loop amplifier with.K, = 1 kil and R, ~ 9 kil. ' Ans. 9.9'J
A l
V = V 'l+A_A p
(8.14) '
n
2
2
Thus the signal-to-noise ratio at t h e output b e c o m e s
i
kHz
s v - = -^A N V t i m e s h i g h e r t h a n in the original case.
(8.15)
2
n
which is A
2
W e e m p h a s i z e o n c e m o r e that the i m p r o v e m e n t in signal-to-noise ratio b y the application of f e e d b a c k is p o s s i b l e only if o n e c a n p r e c e d e the n o i s y stage b y a (relatively) n o i s e -
8.2.3 Noise Reduction
free stage. This situation, h o w e v e r , is not u n c o m m o n in practice. T h e best e x a m p l e is found
N e g a t i v e feedback c a n be e m p l o y e d to r e d u c e t h e n o i s e or interference in a n amplifier or, m o r e precisely, to increase the ratio of signal to n o i s e . H o w e v e r , as w e shall n o w explain] this noise-reduction p r o c e s s is p o s s i b l e only u n d e r certain conditions. C o n s i d e r the situation illustrated in F i g . 8.2. F i g u r e 8.2(a) s h o w s an amplifier with gain A j , an i n p u t signal V„ and n o i s e , or interference, V . It is a s s u m e d that for s o m e r e a s o n this amplifier suffers n
from
n o i s e and that t h e n o i s e c a n b e a s s u m e d to b e i n t r o d u c e d at t h e i n p u t of the amplifier. The
in the output p o w e r - a m p l i f i e r stage of an a u d i o amplifier. S u c h a stage usually suffers from a p r o b l e m k n o w n as p o w e r - s u p p l y h u m . T h e p r o b l e m arises b e c a u s e of t h e large currents that this stage d r a w s from t h e p o w e r supply a n d t h e difficulty in p r o v i d i n g a d e q u a t e p o w e r supply filtering i n e x p e n s i v e l y . T h e p o w e r - o u t p u t stage is required to p r o v i d e large p o w e r gain b u t little or n o voltage gain. W e m a y therefore p r e c e d e the p o w e r - o u t p u t stage b y a small-signal amplifier that p r o v i d e s large voltage gain, and apply a large a m o u n t of negative feedback, t h u s restoring t h e v o l t a g e gain to its original value. S i n c e the small-signal a m p l i fier can b e fed f r o m another, less hefty (and h e n c e better regulated) p o w e r supply, it will n o t suffer from t h e h u m p r o b l e m . T h e h u m at t h e output will t h e n b e r e d u c e d b y t h e a m o u n t of the voltage g a i n of this a d d e d p r e a m p l i f i e r .
EXERCISE 8.3
Consider a power-output stage with voltage gain A, = 1. an i n p u t signal 1 V, and a hum V„ of 1 V. Assume that this power stage is preceded by a small-signal stage with gain A = 100 V/V and that overall feedback with B= 1 is applied. If V_ and V„ remain unchanged, find the signal and noise voltages al Ihc oulput and hence Ihc improvemenl in .S7.V. 2
Ans. = 1 V; =-0.01 V; 100 (40 dB)
8.2.4 Reduction in Nonlinear Distortion Curve (a) in F i g . 8.3 s h o w s t h e transfer characteristic of an amplifier. A s indicated, t h e characteristic is p i e c e w i s e linear, w i t h t h e v o l t a g e gain c h a n g i n g from 1000 to 100 and then to 0. This n o n l i n e a r transfer characteristic will result in this amplifier g e n e r a t i n g a large a m o u n t of nonlinear distortion. 3
(b)
T h e amplifier transfer characteristic can b e considerably l i n e a r i z e d (i.e., m a d e less nonlinear) t h r o u g h t h e application of n e g a t i v e feedback. T h a t this is p o s s i b l e s h o u l d not b e t o o
FIGURE 8 . 2 amplifiers.
Illustrating the application of negative feedback to improve the signal-to-noise ratio in
surprising, s i n c e w e h a v e already seen that n e g a t i v e f e e d b a c k r e d u c e s t h e d e p e n d e n c e of t h e overall c l o s e d - l o o p amplifier gain on the o p e n - l o o p gain of t h e basic amplifier. T h u s large
797
7 9 8
CHAPTER 8
FEEDBACK
8.3
THE FOUR BASIC FEEDBACK TOPOLOGIES
8,3.1 Voltage Amplifiers Voltage amplifiers are i n t e n d e d to amplify an input voltage signal and p r o v i d e an output voltage signal. T h e voltage amplifier is essentially a voltage-controlled v o l t a g e source. T h e input i m p e d a n c e is required to b e high, and the output i m p e d a n c e is required to b e low. Since the signal source is essentially a v o l t a g e source, i t is convenient to represent it in terms of a T h e v e n i n equivalent circuit. In a v o l t a g e amplifier the output quantity of interest is the output voltage. It follows that t h e f e e d b a c k n e t w o r k should sample t h e output voltage. Also, because of t h e T h e v e n i n representation of the source, the f e e d b a c k signal x should b e a voltage that can b e mixed w i t h the source v o l t a g e in series. A suitable feedback t o p o l o g y for the v o l t a g e amplifier is the v o l t a g e - m i x i n g voltagesampling one s h o w n in Fig. 8.4(a). B e c a u s e of the series c o n n e c t i o n at t h e input and the parallel or shunt c o n n e c t i o n at the output, this f e e d b a c k t o p o l o g y is also k n o w n as s e r i e s shunt feedback. A s will b e s h o w n , this t o p o l o g y not only stabilizes the voltage gain b u t also results in a h i g h e r input resistance (intuitively, a result of t h e series c o n n e c t i o n at t h e input) and a l o w e r o u t p u t r e s i s t a n c e (intuitively, a result of the parallel c o n n e c t i o n at t h e output), w h i c h are desirable properties for a v o l t a g e amplifier. T h e noninverting o p - a m p configuration of F i g . E 8 . 1 is an e x a m p l e of s e r i e s - s h u n t feedback. f
FIGURE 8.3 Illustrating the application of negative feedback to reduce the nonlinear distortion in amplifiers. Curve (a) shows the amplifier transfer characteristic without feedback. Curve (b) shows the characteristic with negative feedback (¡3 = 0.01) applied.
c h a n g e s in open-loop gain (1000 to 100 in this case) give rise to m u c h smaller corresponding c h a n g e s in the closed-loop gain. T o illustrate, let us apply n e g a t i v e f e e d b a c k w i t h /J = 0.01 to the amplifier w h o s e openloop voltage transfer characteristic is depicted in Fig. 8.3. T h e resulting transfer characteristic of the c l o s e d - l o o p amplifier is s h o w n in F i g . 8.3 as c u r v e (b). H e r e t h e slope of t h e steepest s e g m e n t is g i v e n b y
A
=
f l
lOQO
f l
=
9
o.9
1 + 1000x0.01
and the slope of t h e n e x t s e g m e n t is g i v e n b y
=
A
f2 / 2
IPO
=
5 Q
1 + 100x0.01
T h u s the order-of-magnitude change in slope has b e e n considerably reduced. T h e price paid, of course, is a reduction in voltage gain. T h u s if the overall gain has to b e restored, then a preamplifier should b e added. This preamplifier should not present a severe nonlinear-distortion p r o b l e m , since it will b e dealing with smaller signals. Finally, it should be noted that negative feedback can d o nothing at all about amplifier saturation, since in saturation the gain is very small (almost zero) and h e n c e the amount of feedback is also v e r y small (almost zero).
8.3.2 Current Amplifiers The input signal in a current amplifier is essentially a current, and thus the signal source is most conveniently r e p r e s e n t e d b y its N o r t o n equivalent. T h e output quantity of interest is current; h e n c e t h e f e e d b a c k n e t w o r k should sample the output current. T h e feedback signal should be in current form so that it m a y b e mixed in shunt with the source current. T h u s the feedback t o p o l o g y suitable for a current amplifier is the c u r r e n t - m i x i n g c u r r e n t - s a m p l i n g topology, illustrated in F i g . 8.4(b). B e c a u s e of t h e parallel (or shunt) c o n n e c t i o n at t h e input, and the series c o n n e c t i o n at the output, this f e e d b a c k topology is also k n o w n as s h u n t series feedback. A s will b e s h o w n , this t o p o l o g y n o t only stabilizes the current gain b u t also results in a l o w e r input resistance, and a h i g h e r output resistance, both desirable properties for a current amplifier. A n e x a m p l e of the s h u n t - s e r i e s feedback t o p o l o g y is given in Fig. 8.5. N o t e that t h e bias details are n o t s h o w n . A l s o n o t e that t h e current b e i n g s a m p l e d is n o t t h e output current, b u t the equal current flowing from t h e source of Q . T h i s u s e of a surrogate is d o n e for circuitdesign c o n v e n i e n c e and is quite usual in circuits involving current sampling. T h e r e f e r e n c e d i r e c t i o n i n d i c a t e d in F i g . 8.5 for t h e f e e d b a c k c u r r e n t If is s u c h t h a t it subtracts from I . T h i s r e f e r e n c e n o t a t i o n w i l l b e f o l l o w e d in all circuits in this c h a p t e r , since it is c o n s i s t e n t w i t h t h e n o t a t i o n u s e d in t h e g e n e r a l f e e d b a c k structure of F i g . 8 . 1 . In all circuits, t h e r e f o r e , for t h e f e e d b a c k to b e n e g a t i v e , t h e l o o p g a i n AB s h o u l d b e positive. T h e r e a d e r is u r g e d to verify, t h r o u g h q u a l i t a t i v e a n a l y s i s , that in t h e circuit of Fig. 8.5, A is n e g a t i v e a n d [3 is n e g a t i v e . It is of u t m o s t i m p o r t a n c e to b e able t o a s c e r t a i n qualitatively (and q u i c k l y ) t h e feedback polarity ( p o s i t i v e or n e g a t i v e ) . T h i s c a n b e d o n e b y " f o l l o w i n g t h e signal a r o u n d t h e l o o p . " F o r i n s t a n c e , let t h e c u r r e n t I in F i g . 8.5 i n c r e a s e . W e see that t h e gate v o l t a g e of Qi will i n c r e a s e , a n d t h u s its drain c u r r e n t w i l l also i n c r e a s e . T h i s will c a u s e t h e drain voltage of Qi ( a n d t h e gate v o l t a g e of Q ) to d e c r e a s e , a n d thus t h e drain c u r r e n t of Q ,1 , will d e c r e a s e . T h u s t h e s o u r c e current of Q ,1 , d e c r e a s e s . F r o m t h e f e e d b a c k n e t w o r k w e see that if I d e c r e a s e s , t h e n (in t h e direction s h o w n ) w i l l i n c r e a s e . T h e i n c r e a s e in I will subtract from I , c a u s i n g a s m a l l e r i n c r e m e n t to b e seen b y t h e amplifier. H e n c e t h e feedb a c k is n e g a t i v e . 2
s
s
8.3 THE FOUR BASIC FEEDBACK TOPOLOGIES
2
B a s e d o n the quantity to b e amplified (voltage or current) and o n the desired form of output (voltage or current), amplifiers can b e classified into four categories. T h e s e categories were discussed in C h a p t e r 1. In t h e following, w e shall r e v i e w this amplifier classification and p o i n t out t h e f e e d b a c k topology appropriate in e a c h case.
2
2
0
0
f
s
0
799
8.3
THE FOUR BASIC FEEDBACK TOPOLOGIES
R, -VVV-
" I c > 3 60
s
•2
i op 3 o I f 00
"AT
FIGURE 8.5 A transistor amplifier with shunt-series feedback. (Biasing not shown.)
8.3.3 Transconductance Amplifiers In transconductance amplifiers the input signal is a voltage and the output signal is a current. It follows that the appropriate feedback topology is the v o l t a g e - m i x i n g c u r r e n t - s a m p l i n g topology, illustrated in F i g . 8.4(c). T h e p r e s e n c e of t h e series c o n n e c t i o n at b o t h t h e input and the output gives this feedback topology the alternative n a m e s e r i e s - s e r i e s f e e d b a c k . A n e x a m p l e of this f e e d b a c k t o p o l o g y is g i v e n in F i g . 8.6. H e r e , n o t e that as in t h e cir cuit of Fig. 8.5 t h e current s a m p l e d is n o t the o u t p u t current b u t t h e a l m o s t - e q u a l emitter current of Q . In addition, the m i x i n g loop is not a c o n v e n t i o n a l o n e ; it is n o t a simple series connection, since t h e feedback signal d e v e l o p e d across R is in t h e emitter circuit of Q , while the source is in the b a s e circuit of Q . T h e s e t w o a p p r o x i m a t i o n s are d o n e for c o n v e nience of circuit design. 3
m
<1>
x
4^
«w
o
c •• c 'BO J| -§
-
§
S u I„ oo u
5
2
UJ
oo o
u
« T 3
c
FIGURE 8 . 6 An example of the series-series feedback topology. (Biasing not shown.) 8 0 0
x
....
801
8 0 2
_
CHAPTER 8
FEEDBACK
8.4
If
T H E SERIES-SHUNT
FEEDBACK
AMPLIFIER
R,
+
(a)
(h)
1 FIGURE 8 . 7 (a) The inverting op-amp configuration redrawn as (b) an example of shunt-shunt feedback.
8.3.4 Transresistance Amplifiers
O
; I
+
" j
».
In transresistance amplifiers t h e input signal is current a n d t h e output signal is voltage. It follows that t h e appropriate feedback topology is of the c u r r e n t - m i x i n g v o l t a g e - s a m p l i n g type, s h o w n in Fig. 8.4(d). T h e presence of the parallel (or shunt) connection at both the input and the output m a k e s this feedback topology also k n o w n as s h u n t - s h u n t feedback. A n e x a m p l e of this feedback t o p o l o g y is found i n the inverting o p - a m p configuration of Fig. 8.7(a). T h e circuit is r e d r a w n in Fig. 8.7(b) w i t h the source c o n v e r t e d t o N o r t o n ' s form.
—
1
"^^^^
8.4 THE SERIES-SHUNT FEEDBACK AMPLIFIER
S
K
«
ß circuit
O
8.4.1 The Ideal Situation T h e ideal structure of the s e r i e s - s h u n t feedback amplifier is s h o w n in Fig. 8.8(a). It consists of a unilateral o p e n - l o o p amplifier (the A circuit) a n d an ideal v o l t a g e - m i x i n g voltages a m p l i n g feedback n e t w o r k (the ¡3 circuit). T h e A circuit h a s an input resistance R , a voltage gain A, a n d an output resistance R . It is a s s u m e d that t h e source a n d load resistances have b e e n included inside the A circuit ( m o r e o n this point later). F u r t h e r m o r e , note that the ¡3 circuit does not load the A circuit; that is, connecting the ¡3 circuit does not c h a n g e the value of A (defined as A = V /V^. T h e circuit of Fig. 8.8(a) exactly follows t h e ideal feedback m o d e l of Fig. 8.1. Therefore the closed-loop voltage gain A i s given b y T
S'
0
0
O' (b)
FIGURE 8 . 8 The series-shunt feedback amplifier: (a) ideal structure and (b) equivalent circuit.
/
Thus,
A f
V.
(8.16)
IF
N o t e that A and ¡3 h a v e reciprocal units. This i n fact is a l w a y s t h e case, resulting in a dimensionless l o o p g a i n A/3. T h e equivalent circuit m o d e l of the series-shunt feedback amplifier is shown in Fig. 8.8(b). H e r e R a n d R f d e n o t e the input and output resistances with feedback. T h e relationship b e t w e e n R and R, c a n b e established b y considering t h e circuit in Fig. 8.8(a): IF
R
l+A/3
Q
IF
V.
s
V
f
'
T
t
s
s
= RYI = R < + ß
'v
s
:
V-./R,
(8.17)
t
Note, however, that this result is not surprising and is physically intuitive: Since the feedback voltage V subtracts from V , t h e voltage that appears across R —that is, V —becomes quite small [V, - V /(l + A¡3)]. T h u s the input current b e c o m e s correspondingly small and the resistance seen b y V b e c o m e s large. Finally, it should b e pointed out that Eq. (8.17) can b e generalized t o t h e form f
V
= R (l+Ap)
That is, i n this case the negative feedback increases the input resistance by a factor equal to the amount of feedback. Since t h e derivation a b o v e d o e s n o t d e p e n d o n t h e m e t h o d of s a m pling (shunt o r series), it follows that the relationship b e t w e e n 7?,^ and R, is a function only of the m e t h o d of m i x i n g . W e shall discuss this point further in later sections.
v
A
V
' Z (s) if
;
=
Z (s)[l+A(s)ß(s)] l
(8.18)
.
I
803
CHAPTER 8
FEEDBACK
8.4
Has'.c amplifier
Vs(±
AMPLIFII
Rr
Rn,
Rit 1-ml back
®
FIGURE 8 . 9 Measuring the output resistance of the feedback amplifier of Fig. 8.8(a): R = y / j
THE SERIES-SHUNT FEEDBACK
(D
IIL-LUULK
o f
(a) T o find t h e output resistance, R , of t h e f e e d b a c k amplifier in F i g . 8.8(a) w e reduce V to z e r o and apply a test voltage V at the output, as s h o w n in Fig. 8.9, of
t
V
R
-<
F r o m F i g . 8.9 w e c a n write V.-AV.
a n d since V = 0 it follows from F i g . 8.8(a) that s
v =-v t
f
= -Bv
=
V +
ApV
0
~Bv
t
Thus t
I =
t
R„
(b)
l e a d i n g to R„ R„f = T h a t is, the negative feedback the amount
of feedback.
( 8
l+A/3
in this case reduces
the output
resistance
by a factor
-
1 9 )
A circuit
-
equal to
W i t h a little t h o u g h t o n e c a n see that the derivation of Eq. (8.19)
does n o t d e p e n d o n the m e t h o d of m i x i n g . T h u s the relationship b e t w e e n R f and R a
0
depends
only o n t h e m e t h o d of s a m p l i n g . A g a i n , this result is not surprising and is physically intui tive: Since t h e f e e d b a c k samples t h e output v o l t a g e V , it acts to stabilize the value of V : 0
0
f I—F=—m
that is, to r e d u c e changes in the value of V , including changes that might b e brought about 0
ILIILLILL
by changing the current d r a w n from the amplifier output terminals. This, in effect, means that voltage-sampling feedback reduces the output resistance. Finally, w e note that Eq. (8.19) can be g e n e r a l i z e d to
ILL
LLLIBLÉLILL :
r Z (s) of
=
Z (s)
(8.20)
0
-o-
1+A(s)ß(s)
>h,A. <
8.4.2 The Practical Situation
- 0--
In a practical series-shunt feedback amplifier, the feedback network will not be an ideal voltagecontrolled voltage source. Rather, the f e e d b a c k n e t w o r k is usually resistive and hence will load t h e b a s i c amplifier and thus affect the v a l u e s of A, R
b
and R . In addition, the source
and load resistances will affect these three parameters. Thus the p r o b l e m w e have is as follows: Given a series-shunt feedback amplifier represented b y the block diagram of Fig. 8.10(a), find the A circuit a n d the B circuit.
3 circuit
(c)
0
URE 8 . 1 0 Derivation of the A circuit and B circuit for the series-shunt feedback amplifier, (a) Block lagram of a practical series-shunt feedback amplifier, (b) The circuit in (a) with the feedback network represented by its h parameters, (c) The circuit in (b) with h neglected. 21
8 0 5
R 8
FEEDBACK T H E SERIES-SHUNT FEEDBACK AMPLIFIER
8.4
O u r p r o b l e m essentially involves representing t h e amplifier of F i g . 8.10(a) b y t h e ideal structure of Fig. 8.8(a). A s a first step t o w a r d that e n d w e o b s e r v e that t h e source and load resistances should b e l u m p e d with t h e basic amplifier. This, together with representing the two-port feedback n e t w o r k in terms of its h p a r a m e t e r s (see A p p e n d i x B ) , is illustrated in Fig. 8.10(b). T h e choice of h p a r a m e t e r s is b a s e d o n t h e fact that this is t h e only parameter set that represents the feedback n e t w o r k b y a series n e t w o r k at port 1 a n d a parallel network at p o r t 2 . Such a representation is obviously c o n v e n i e n t in v i e w of the series connection at the input a n d t h e parallel connection at t h e output. E x a m i n a t i o n of t h e circuit in Fig. 8.10(b) reveals that t h e current source h I represents the forward fransrnission o f the feedback network. S i n c e t h e f e e d b a c k n e t w o r k is usually passive, its forward transmission c a n b e neglected in c o m p a r i s o n t o t h e m u c h larger forward transmission of t h e b a s i c amplifier. W e will therefore a s s u m e that |/i |feedback < \h \basic and thus o m i t the controlled source / z / j altogether. ° amplifier 2l
21
r
21
C o m p a r e t h e circuit of F i g . 8.10(b) (after eliminating t h e current source h d ) with the ideal circuit o f Fig. 8.8(a). W e see that b y i n c l u d i n g h a n d h w i t h t h e b a s i c amplifier w e obtain the circuit s h o w n in F i g . 8.10(c), w h i c h is v e r y similar t o the ideal circuit. N o w , if the basic amplifier is unilateral (or almost unilateral), a situation that prevails w h e n 2
n
l^lbasic
^
amplifier
8.4.3 Summary A summary of the rules for finding the A circuit a n d ¡3 for a given series-shunt feedback amplifier of the form in Fig. 8.10(a) is given i n Fig. 8 . 1 1 . A s for using t h e feedback formulas in Eqs. (8.17) a n d (8.19) t o determine the input a n d output resistances, it is important to note that:
1
21
n e
connection at t h e input suggests that (as in the case of finding t h e loading effects of the feedback network) ¡3 should b e found w i t h port 1 open-circuited.
x
22
l^ulfeedback
1. R a n d R are t h e i n p u t a n d output resistances, respectively, of t h e A circuit in Fig. 8.11(a). t
0
2. Rif a n d R f are the input a n d output resistances, respectively, of the feedback amplifier, including R a n d R (see F i g . 8.10a). a
s
L
3. T h e actual input and output resistances of the feedback amplifier usually exclude R a n d R . T h e s e are d e n o t e d i ? a n d R i n F i g . 8.10(a) a n d can b e easily d e t e r m i n e d as
s
L
m
out
R
R
^in = if~ s
(8.23) (8.24)
(8.21)
network
then the circuit of Fig. 8.10(c) is equivalent (or approximately equivalent) t o t h e ideal circuit. It follows t h e n that t h e A circuit is obtained b y a u g m e n t i n g t h e basic amplifier at the input w i t h t h e source i m p e d a n c e R a n d t h e i m p e d a n c e h of the feedback network, and at the output w i t h the load i m p e d a n c e R a n d the a d m i t t a n c e h o f the feedback n e t w o r k . W e c o n c l u d e that t h e loading effect of t h e feedback n e t w o r k o n t h e b a s i c amplifier is represented b y t h e c o m p o n e n t s h a n d h . F r o m t h e definitions o f t h e h parameters in A p p e n d i x B w e see that h is t h e i m p e d a n c e looking into port 1 o f the feedback network with port 2 short-circuited. Since port 2 of t h e feedback n e t w o r k is connected in shunt with the output port of the amplifier, short-circuiting port 2 destroys t h e feedback. Similarly, h is t h e a d m i t t a n c e looking into port 2 of t h e feedback n e t w o r k with port 1 open-circuited. S i n c e p o r t 1 o f t h e feedback n e t w o r k is c o n n e c t e d i n series with the amplifier input, opencircuiting port 1 destroys the feedback. T h e s e observations suggest a simple rule for finding t h e loading effects of the feedback n e t w o r k o n the b a s i c amplifier: T h e l o a d i n g effect is found b y looking into t h e appropriate port o f the feedback n e t w o r k while the other port is open-circuited o r short-circuited so as to destroy t h e feedback. If t h e connection is a shunt o n e , w e short-circuit t h e port; if it is a series o n e , w e open-circuit it. In Sections 8.5 a n d 8.6 it will b e seen that this simple rule applies also to t h e other three feedback t o p o l o g i e s . W e next consider the determination of ¡3. F r o m F i g . 8.10(c), w e see that /3 is e q u a l to h of the feedback n e t w o r k , s
(a)
The A circuit is
n
L
u
22
22
Rs VW-
-o
v,
(~D^ ™ o—
Ikl-...
-o
-AMr
n
R» Ri
22
where R
is obtained from
n
°
1
and R
Feedback network
® o-
is obtained from
2 2
L Feedback network
®
An
Rr
and the gain A is defined
2
A= —
n
(b)
ß is obtained from
if T
(8.22)
• " 1 2 —
i,=o T h u s to m e a s u r e ¡3, o n e applies a voltage t o port 2 of the feedback n e t w o r k a n d m e a s u r e s the voltage that appears at port 1 w h i l e the latter port is open-circuited. T h i s result is intuitively appealing because the object of the feedback n e t w o r k is to sample the output voltage (V = V ) and p r o v i d e a voltage signal (V, = V ) that is m i x e d in series with t h e input source. T h e series 2
®
Feedback network
ß
0
F
2
A simple rule to remember is: If the connection is shunt,
short it; if series, sever it.
8
1
CÂÏOT FMG S H),A) '" " ° R
UNI
AR
V
F
^
FIDDING
^
A
C K C U Í T
ß
i
m
T
O
L
L
A
S
&
-
I
D
I
X
I
N
S VOLTAGE-SAMPLING
;
\-
807
CHAPTER
8
FEEDBACK
Figure 8.12(a) shows an op amp connected in the noninverting configuration. The op amp has an open-loop gain [i, a differential input resistance R , and an output resistance r . Recall that in our analysis of op-amp circuits in Chapter 2, we neglected the effects of R (assumed it to be infinite) and of r (assumed it to be zero). Here we wish to use the feedback method to analyze the circuit taking both R and r into account. Find expressions for A, B, the closed-loop gain V /V , the input resistance R (see Fig. 8.12a), and the output resistance R . Also find numerical values, given n = 1 0 , R = 100 k Q , r = \Ml,R = 2 Ml, R_ = IM1,R =1 M Q , and R = 10 k Q . id
0
id
a
id
a
0
in
s
oM
4
id
0
L
2
s
Solution W e observe that the feedback network consists of R and R . This network samples the output voltage V* and provides a voltage signal (across R_) that is mixed in series with the input source V . The A circuit can be easily obtained following the rules of Fig. 8.11, and is shown in Fig. 8.12(b). For this circuit w e can write by inspection 2
x
0
s
A
Y o
s
V
lRj(Ri+m
=
M t
[R II(R_
+ R )1 + r R
L
2
a
+ R+
id
S
(R
IIR )
x
2
For the values given, we find that A — 6000 V7V. The circuit for obtaining B is shown in Fig. 8.12(c), from which w e obtain
V
R +R
0
x
2
The voltage gain with feedback is now obtained as A, ^ f
A l+AB
=
V
s
=
6000 7
=
The input resistance R determined by the feedback equations is the resistance seen by the exter if
nal source (see Fig. 8.12a), and is given by R
=
v
R (l+AB) i
where 7?,- is the input resistance of the A circuit in Fig. 8.12(b): R
s
For the values given,
=
R.+Ru+iRjlRJ
= 111 kQ, resulting in R
if
= 111 x 7 = 777 k Q
This, however, is not the resistance asked for. What is required is R , indicated in Fig. 8.12(a). in
T o obtain R
iri
w e subtract R from R : s
if
R
in
For the values given, R
in
R
=
R
if~ s
= 739 k Q . The resistance R
of
given by the feedback equations is the
output resistance of the feedback amplifier, including the load resistance R , as indicated in L
Fig. 8.12(a). R
of
is given by R
-
R
°
810
!
8.5
CHAPTER 8
T H E SERIES-SERIE5 F E E D B A C K A M P L I F I E R
FEEDBACK
where /?„ is the output resistance of the A circuit. fl„ can be obtained by inspection of Fig. 8.12(b) as R
= r HR ll(R
0
0
L
8.5
THE SERIES-SERIES FEEDBACK AMPLIFIER
+ R)
2
1
8.5.1 The Ideal Case 1
' •:.-t.
For the values given, R„ — 667 Q, and
As m e n t i o n e d in Section 8.3, the series-Series feedback t o p o l o g y stabilizes I /V 0
f
.'à,, The resistance asked for, R , out
s
and is
therefore b e s t suited for t r a n s c o n d u c t a n c e amplifiers. F i g u r e 8.13(a) s h o w s the ideal struc-
= 667 = 95.3 Q 7
ture for the s e r i e s - s e r i e s feedback amplifier. It consists of a unilateral o p e n - l o o p amplifier
is the output resistance of the feedback amplifier excluding R,.
(the A circuit) and an ideal f e e d b a c k n e t w o r k . N o t e that in this c a s e A is a t r a n s c o n d u c t a n c e ,
From Fig. 8.12(a) w e see that Rf = 0
R
A = — V
R
ouJI L
(8.25)
t
while B is a transresistance. T h u s the loop gain AB r e m a i n s a d i m e n s i o n l e s s quantity, as it
•:::;C Thus
should a l w a y s b e . «out =
100
Q
In the ideal structure of Fig. 8.13(a), t h e l o a d and source resistances h a v e b e e n a b s o r b e d inside the A circuit, and t h e ji circuit does n o t l o a d the A circuit. T h u s t h e circuit follows the ideal feedback m o d e l of F i g . 8 . 1 , and w e c a n w r i t e
A
f f
If the op a m p of Example 8.1 has a uniform -6-dB/octave highsfrequency rolloff with f
m
= ^ V
= s
- 1 kHz,
(8.26) l+AB
find (he 3-dB frequency of the closed-loop gain V'/V... Ans. 7 kHz The circuit shown in Fig. E8.5 consists of a differential stage followed b y an emitter follower, with series-shunt feedback supplied by the resistors R and R . Assuming that the dc component of V, is zero, and that ¡5 of the BJTs is very high, find the dc operating current of each of the three transistors and show that the dc voltage at the output is approximately zero. Then find the values of A, / i A , = V./V,, R , and R . A s s u m e thai the transistors have Q = 100. x
m
2
om
•10.7 V
10 l d l -A/VSr
- o \'„
5 mA
R,
• : kü
FIGURE E8.5
(b) Ans. 85.7 \ . A : (i.l \ A : N . 9 6 V / \ : M
ki>:
l'J.li2 FIGURE 8 . 1 3 The series-series feedback amplifier: (a) ideal structure and (b) equivalent circuit.
811
CHAPTER 8
FEEDBACK T H E SERIES-SERIES FEEDBACK AMPLIFIER
8.5
o
R, Haric amplifier
V,( +
O' FIGURE 8 . 1 4 Measuring the output resistance R of the series-series feedback amplifier.
KVDBACK NETWORK
af
J
®
T h i s transconductance-with-feedback is included in the equivalent circuit m o d e l of the feedb a c k amplifier, s h o w n in Fig. 8.13(b). In this m o d e l , is the input resistance with feedback. U s i n g an analysis similar to that in Section 8.4, w e can s h o w that R =R.(l+AB)
(a)
(8.27)
if
This relationship is identical to that obtained in the case of s e r i e s - s h u n t feedback. This confirms our earlier observation that the relationship b e t w e e n R and R is a function only of the m e t h o d of mixing. Voltage (or series) m i x i n g therefore always increases the input resistance. T o find the output resistance R of the series-series feedback amplifier of Fig. 8.13(a) we reduce V to zero and b r e a k the output circuit to apply a test current I„ as s h o w n in Fig. 8.14: if
t
of
s
Kf
= 7
(8-28)
It In this case, V- = -V t
f
= -Bl
0
= -¡31',. T h u s for the circuit in Fig. 8.14 w e obtain
V = (I -AV )Ro t
=
t
(b)
{I +ABI,)R t
0
Hence
A circuit R =(l+AB)R of
(8.29)
0
That is, in this case the negative feedback increases the output resistance. This should have b e e n expected, since the negative feedback tries to m a k e l constant in spite of changes in the output voltage, w h i c h means increased output resistance. This result also confirms our earlier observation: The relationship b e t w e e n R and R is a function only of the m e t h o d of sampling. W h i l e voltage (shunt) sampling reduces the output resistance, current (series) sampling increases it.
I I
0
of
0
R
-
C
-
v
f
+
R¡
W V
KASIC (IINNLITID
IL I
J-VA—
W V
AAA/I
8.5.2 The Practical Case F i g u r e 8.15(a) s h o w s a block d i a g r a m for a practical series-series feedback amplifier. T o be able to apply the feedback equations to this amplifier, w e h a v e to represent it by the ideal structure of Fig. 8.13(a). O u r objective therefore is to devise a simple m e t h o d for finding A and 8. O b s e r v e the definition of the amplifier input resistance R and output resistance R f It is i m p o r t a n t to note that t h e s e are different from R and R , w h i c h are d e t e r m i n e d by the feedback equations, as will b e c o m e clear shortly. T h e series-series amplifier of Fig. 8.15(a) is r e d r a w n in Fig. 8.15(b) w i t h R and R s h o w n closer to the basic amplifier, a n d the t w o - p o r t feedback n e t w o r k represented by its z p a r a m e t e r s ( A p p e n d i x B ) . T h i s p a r a m e t e r set has been chosen b e c a u s e it is the only one that provides a representation of the feedback n e t w o r k with a series circuit at the input and a in
if
r. -/
0VL
I
of
s
(c)
L
FIGURE 8 . 1 5 Derivation of the A <
1 c i r c u i t
t
h
e
B circuit
serie* , ^ P circuit for series-series feedback amplifiers, (a) A seriesfc) A rfvi P - (»>) " i t of (a) w i t h the feedback network represented by its z parameters w A íedrawmg of the circuit in (b) with z_\ neglected. fe>
a m
I l f i e r
T
h
e
c i r c
8 1 3
814
v
!
CHAPTER 8
FEEDBACK
T H E SERIES-SERIES FEEDBACK
8.5
series circuit at the output. This is obviously convenient in v i e w of the series connections at input a n d output. T h e input a n d output resistances w i t h feedback, R and R , are indicated o n t h e diagram. A s w e h a v e done in the c a s e of the s e r i e s - s h u n t amplifier, w e shall a s s u m e that the for w a r d transmission through the feedback n e t w o r k is negligible i n c o m p a r i s o n to that through the basic amplifier; that is, the condition if
(a)
The A circuit is
of
R
s
-o
V W
-o
Rn
Z
R2 2
Y
z
n
where R
n
is obtained from
and R
m
o
kdfeedback network
n
s
L
2 2
n
©
Feedback network
®
CD
o-
and the gain A is defined
(8.31)
then t h e circuit i n Fig. 8.15(c) is equivalent (or almost equivalent) t o t h e ideal circuit of Fig. 8.13(a). It follows that the A circuit is c o m p o s e d of t h e basic amplifier a u g m e n t e d a t t h e input with R and z and augmented at the output with R and z . Since z and z are the i m p e d a n c e s looking into ports 1 a n d 2 , respectively, of the feedback n e t w o r k with the other port open-circuited, w e s e e that finding t h e l o a d i n g effects of the f e e d b a c k n e t w o r k o n the basic amplifier follows the rule formulated in Section 8.4. T h a t is, w e look into o n e port of t h e f e e d b a c k n e t w o r k while t h e other port i s open-circuited o r short-circuited so as to destroy the feedback (open if series a n d short if shunt). F r o m F i g . 8.15(c) w e see that 8 is equal t o z of the f e e d b a c k network,
Feedback network
®
2 2
knlbasic ^ amplifier
is obtained from
22
2
n
L
R
(8.30)
is satisfied. W e c a n then dispense w i t h t h e v o l t a g e source z f\ Fig- 8.15(b). D o i n g this, and r e d r a w i n g the circuit to include z and z with the basic amplifier, results in t h e circuit in F i g . 8.15(c). N o w if the basic amplifier is unilateral (or almost unilateral), a situation that is o b t a i n e d w h e n
R
A Y'
Ri l 2l|basic amplifier
z
\ 2l\feedback ^ network
AMPLIFIER
(b)
A = 77-
ß is obtained from I_=0 + o-
2 2
Feedback network
®
Vf
1 2
FIGURE
zz
l
8.16
Finding the A circuit and B for the voltage-mixing current-sampling (series-series) case.
(8.32)-
y
=- - i 2
11
T h i s result is intuitively appealing. Recall that in this case the feedback n e t w o r k s a m p l e s the o u t p u t c u r r e n t [I = f] a n d p r o v i d e s a v o l t a g e [V} - V{\ that i s m i x e d in series w i t h t h e 2
i n p u t source. Again, t h e series c o n n e c t i o n a t t h e input suggests that 8 is m e a s u r e d with port 1 open.
Because negative feedback extends the amplifier bandwidth, it is commonly used in the design of broadband amplifiers. O n e such amplifier is the M C 1 5 5 3 . Part of the circuit of the M C 1 5 5 3 is shown in Fig. 8.17(a). T h e circuit shown (called a feedback triple) is composed of three gain stages with series-series feedback provided b y the network composed of R , R , and R . Assume that the bias circuit, which is not shown, causes I = 0.6 m A , I = 1 m A , and 7 = 4 mA. Using these values and assuming that h = 100 and r = °°, find the open-loop gain A, the feedback factor B, the closed-loop gain A = I / V , the voltage gain V /V , the input resistance ^in = Rif, and the output resistance R (between nodes Y and Y', as indicated). Now, if r of Q_ is 25 kT2, estimate an approximate value of the output resistance R . El
8.5.3 Summary
a
F o r future r e f e r e n c e w e p r e s e n t in F i g . 8.16 a s u m m a r y of t h e r u l e s for finding A a n d 8 for a g i v e n s e r i e s - s e r i e s f e e d b a c k amplifier of t h e t y p e s h o w n i n F i g . 8.15(a). N o t e that R is t h e i n p u t r e s i s t a n c e of t h e A circuit, a n d its o u t p u t r e s i s t a n c e i s R , w h i c h c a n b e deter m i n e d b y b r e a k i n g t h e o u t p u t l o o p a n d l o o k i n g b e t w e e n T a n d Y'. R a n d R c a n b e used in E q s . (8.27) a n d (8.29) t o d e t e r m i n e R a n d R (see F i g . 8.15b). T h e i n p u t a n d output r e s i s t a n c e s of t h e f e e d b a c k amplifier c a n t h e n b e f o u n d b y s u b t r a c t i n g R from R and 7?^ from R , t
0
t
if
a
fe
f
if
of
a
0
s
0
of
0
Solution Employing the loading rules given in Fig. 8.16, w e obtain the A circuit shown in Fig. 8.17(b). T o find A = I /V_ we first determine the gain of the first stage. This can be written by inspection as
i
f
-R
= R '
o
f
( 8 3 3 )
s
JII R
w
t
s
mt
g
=R
in
E2
C 3
of
s
R
F
C2
- R
L
'
(8-34)
Vi
-«I(*CI#r„2)
=
r
el
+ [R //(R El
F
+ R )] E2
8.5 CHAPTER 8
T H E SERIES-SERIES F E E D B A C K A M P L I F I E R
FEEDBACK
Since Qi is biased at 0.6 m A , r = 41.7 £2. Transistor 6J is biased as 1 m A ; thus r = h /g = 1 0 0 / 4 0 = 2.5 k£2. Substituting these values together with a, = 0.99, R = 9 k Q , R = 100 £2, R = 640 £2, and R = 100 O results in el
2
n2
CL
F
fe
m2
E1
E2
- ^ 1 = - 1 4 . 9 2 V/V V, Next, we determine the gain of the second stage, which can be written by inspection as (note that V =V ) b2
cl
Vç2
•g {R //(h +l)[r m2
C2
fe
+ (R //(R
e3
E2
+
F
R ))]} E1
Vex Substituting g 640 Í2, and R
E1
m 2
= 40 m A / V , R
= 5 k Q , h = 100, r
C2
fe
e3
= 2 5 / 4 = 6.25 £2, R^ = 100 Í2, R = F
= 100 £2, results in = - 1 3 1 . 2 VA^
Finally, for the third stage w e can write by inspection h
1 + (R //(R
_
V
V
c2
r
b3
e3
=
E2
P
+
R )) E1
= 10.6 m A / V
1—••
6.25 + (100//740) Combining the gains of the three stages results in A = — = - 1 4 . 9 2 x - 1 3 1 . 2 x 10.6 x 10"
3
= 20.7 A / V The circuit for determining the feedback factor B is shown in Fig. 8.17(c), from which w e find R e 2
ß=Yl= l
R
o
E2
+
R
F
x R +
E l
R
E1
100 x 100 = 11.9 £2 100 + 640 + 100 The closed-loop gain A can now be found from f
Af = — V
—— l+Aß
f
s
20.7 = 83.7 m A / V 1+20.7x11.9 The voltage gain is found from V
o
I
_
R
~ c C3
R
-h C3
-A R/ " C 3 f
= - 8 3 . 7 x 10
3
x 600 = - 5 0 . 2 V/V
The input resistance of the feedback amplifier is given by R
V
=
R,(l+AB)
817
8 1 8
'
CHAPTER 8
8.6
FEEDBACK
T H E SHUNT-SHUNT A N D SHUNT-SERIES FEEDBACK
AMPLIFIERS
'A circuit
where i?, is the input resistance of the A circuit. The value of R can b e found from the circuit in Fig. 8.17(b) as follows: {
= (h +l)[r fe
+ (R ll(R
el
E1
+
F
rr
«"1
R ))}
V W
E2
+
+
1/
= 13.65 k Q
v„
Thus, R
= 13.65(1 + 2 0 . 5 x 11.9) = 3.34 M Q
if
R, of
To find the output resistance R of the A circuit in Fig. 8.11(b), we break the circuit between Y and Y'. The resistance looking between these two nodes can be found to be a
R
= {R 2"(RF
0
+ REI)] + r ,
E
+
e
r"
T^TT
h +l which, for the values given, yields R = 143.9 Q. The output resistance R^of the feedback amplifier can now be found as fe
a
• ß circuit R
= R {\+Ap)
of
= 143.9(1 + 2 0 . 7 x 11.9) = 35.6 k Q
0
Note that the feedback stabilizes the emitter current of Q , and thus the output resistance that is determined b y the feedback formula is the resistance of the emitter loop (i.e., between Y and 1"), which we have just found, and not the resistance looking into the collector of Q . This is because the output resistance r of Q is in effect outside the feedback loop. W e can, however, use the value of R f to obtain an approximate value for R . T o do this, w e assume that the effect of the feedback is to place a resistance R (35.6 k Q ) in the emitter of Q , and find the output resistance from the equivalent circuit shown in Fig. 8.17(d). Using Eq. (6.117), J? can be found as
FIGURE 8 . 1 8 Ideal structure for the shunt-shunt feedback amplifier.
3
3
0
8.6.1 The Shunt-Shunt Configuration
3
0
Figure 8.18 s h o w s t h e ideal structure for a s h u n t - s h u n t feedback amplifier. H e r e the A circuit
ovt
of
has an input resistance R a transresistance A, a n d a n output resistance R . T h e /3 circuit is a h
a
3
out
voltage-controlled current source, a n d B is a transconductance. T h e closed-loop gain A is f
defined Rout
= r
0
+ (l +
g
m 3
r )(R 0
o f
llr
K 3
)
(8.35)
Af = — I
= 25 + (1 + 160 x 25)(35.6//0.625) = 2.5 M Q
f
Thus, the output resistance at the collector increases, but not b y (1 + A/3).
and is given b y
l+A/3 The input resistance w i t h f e e d b a c k is given b y 8.6 Reconsider the circuit in Fig. 8.17(a), this time with the output voltage taken at the emitter of Q , I n this case, the feedback can be considered to be of the voltage-mixing voltage-sampling type. Note, however, that the loop gain remains unchanged. Find the value of A = V /Vj (from Fig. 8.17(b)), Af = V /V , and the output resistance.
(8.36)
3
e3
e3
R i f
"l+A/3
s
Ans. 1827 V/V; 7.4 V/V; 0.14 Q
where w e n o t e that t h e shunt connection at t h e input results in a r e d u c e d input resistance. Also note that t h e resistance R is t h e resistance seen b y t h e source I , a n d it includes a n y if
s
source resistance. T h e output resistance with feedback is g i v e n b y
'
8.6 THE S H U N T - S H U N T AND S H U N T - S E R I E S FEEDBACK AMPLIFIERS
(8.37) R
°
f
l+A/3
where w e n o t e that t h e shunt c o n n e c t i o n at t h e output results i n a r e d u c e d output resistance. In this section w e shall e x t e n d — w i t h o u t p r o o f — t h e m e t h o d of Sections 8.4 a n d 8.5 t o the t w o r e m a i n i n g f e e d b a c k topologies.
3
This important point was first brought to the authors' attention by Gordon Roberts (see Roberts and Sedra, 1992).
This resistance i n c l u d e s any load resistance. Given a practical s h u n t - s h u n t feedback amplifier h a v i n g t h e b l o c k d i a g r a m o f F i g . 8.19, we use the m e t h o d given in Fig. 8.20 t o obtain the A circuit and the circuit for determining ¡3. As in Sections 8.4 a n d 8.5, t h e m e t h o d of F i g . 8.20 a s s u m e s that the basic amplifier is almost unilateral and that the forward transmission through the feedback network is negligibly small.
CHAPTER 8
FEEDBACK
T H E SHUNT-SHUNT A N D SHUNT-SERIES FEEDBACK
8.6
AMPLIFIERS
The second a s s u m p t i o n is justified w h e n t h e forward y p a r a m e t e r s satisfy the condition tîïl> ic ampliiicr
'R.
Rr. network
Finally, w e note that o n c e R a n d R if
of
(8.39)
l ^ l l basic
^211 feedback ^
amplifier
h a v e b e e n d e t e r m i n e d using t h e feedback formulas
(Eqs. 8.36 a n d 8.37), t h e input and output resistances of the amplifier proper (see definitions in Fig. 8.19) can b e o b t a i n e d as
Feedback,
®
network
=I
** /GHJ
<•**»
FIGURE 8 . 1 9 Block diagram for a practical shunt-shunt feedback amplifier.
(a)
The A circuit is
->-
R,
Basic amplifier
Ru
R,,
RL
We want to analyze the circuit of Fig. 8.21(a) to determine the small-signal voltage gain in
V /V , a
s
= R . The transistor has B = 100.
the input resistance R , and the output resistance R
out
of
RI
where R
n
is obtained from
and R
??
Solution
is obtained from
First w e determine the transistor dc operating point. The dc analysis is illustrated in Fig. 8.21(b),
©
Feedback network
©
©
Feedback network
from which we can write 2 V = 0.7 + (I„+ 0.07)47 = 3.99 + 4 7 7 c
=(P+ l ) 7 + 0.07
and
B
fi
These two equations can be solved to obtain I — 0.015 mA, I — 1.5 mA, and V = 4.7 V . To carry out small-signal analysis w e first recognize that the feedback is provided b y R , which samples the output voltage V and feeds back a current that is mixed with the source current. Thus it is convenient to use the Norton source representation, as shown in Fig. 8.21(c). The A circuit can be easily obtained using the rules of Fig. 8.20, and it is shown in Fig. 8.21(d). For the A circuit w e can write by inspection B
and the gain A is defined
£
A= —-
c
c
f
0
(b)
ß is obtained from
Vi = 0
Feedback network
®
3>
V
K
=
I^RJIRfllrJ
V =
-g V {R //R )
0
m
n
f
c
Thus A = Y FIGURE 8 . 2 0 Finding the A circuit and ¡3 for the current-mixing voltage-sampling (shunt-shunt) feedback amplifier in Fig. 8.19. 4
T h e first a s s u m p t i o n is justified w h e n t h e r e v e r s e y p a r a m e t e r s of the basic amplifier and of t h e feedback n e t w o r k satisfy the condition
=
-g (R //R )(RJIR Hr ) m
amplifier
^
Wnlfeedback
(8.38)
network
c
f
n
= -358.7 k Q The input and output resistances of the A circuit can be obtained from Fig. 8.21(d) as Ri = RJIR llr f
b'nlbasic
f
R
0
= R IIR c
f
n
= 1.4 k Q = 4.27 k Q
The circuit for determining B is shown in Fig. 8.21(e), from which we obtain Here, the y parameters (Appendix B) are used because this is the only two-port parameter set that provides a representation of the feedback network with a parallel circuit at the input and a parallel circuit at the output.
822
I
CHAPTER 8
THE SHUNT-SHUNT
8.6
FEEDBACK
To find the voltage gain V /V
+12 V
0
s
03 + 1 ) / + 0.07
kfl
r
B
I + 0.07 B
0
P I
FEEDBACK
AMPLIFIERS
v, = ' A Thus
!4.7 kfl
K V
V IR
Wv—
_41.6 . 10
0
s
ov
SHUNT-SERIES
we note that
t.
R =4J
A N D
S
S
-4.16 V/V
The input resistance with feedback (see Fig. 8.21c) is given by
47 kfl
R
0 kfl
R i
-
Thus
0.07 m A
R;
f , f
= — = 162.2 O 8.63
This is the resistance seen by the current source I in Fig. 8.21(c). To obtain the input resistance of the feedback amplifier excluding R (i.e., the required resistance R^) w e subtract 1/R from l/R^ and invert the result; thus R = 165 Q. Finally, the amplifier output resistance 7? is evaluated using s
(b)
(a)
s
S
m
AAAr
o/
R
=
of
-oV
- * o _
l+A/3
=
W
=
4 Q 5
Q
8.63
n
Rr
R¿f
8.6.2 An Important Note The m e t h o d w e h a v e b e e n e m p l o y i n g for the analysis of feedback amplifiers is predicated on t w o p r e m i s e s : M o s t of the forward transmission occurs in the basic amplifier, a n d m o s t of the reverse transmission (feedback) occurs in the feedback network. F o r each of the three topologies c o n s i d e r e d ' thus far, these t w o a s s u m p t i o n s w e r e mathematically e x p r e s s e d as conditions on the relative m a g n i t u d e s of the forward and reverse two-port p a r a m e t e r s of the basic amplifier a n d the feedback network. Since the circuit considered in E x a m p l e 8.3 is simple, w e h a v e a g o o d opportunity to c h e c k the validity of these a s s u m p t i o n s .
R, of
R
h
(c)
Reference to Fig. 8.21(d) indicates clearly that the basic amplifier is unilateral; thus all the reverse t r a n s m i s s i o n takes place in the feedback n e t w o r k . T h e case w i t h forward transmission, h o w e v e r , is not as clear, and w e m u s t evaluate the forward y p a r a m e t e r s . F o r the A circuit in F i g . 8.21(d), y i = g - For the f e e d b a c k n e t w o r k it c a n b e easily s h o w n that y i = -l/Rf. T h u s for our analysis m e t h o d to b e valid w e m u s t h a v e g >1/R . F o r the numerical values in E x a m p l e 8.3, g - 60 mATV and l/R = 0.02 m A / V , indicating that this assumption is m o r e t h a n justified. N e v e r t h e l e s s , in designing feedback amplifiers, care should b e taken in c h o o s i n g c o m p o n e n t values to e n s u r e that the t w o basic assumptions are valid.
+
2
m
2
m
m
(e)
(d) FIGURE 8 . 2 1
f
f
Circuits for Example 8.3.
Note that as usual the reference direction for 7^ has been selected so that I subtracts from I . The resulting negative sign of B should cause no concern, since A is also negative, keeping the loop gain A/3 positive, as it should be for the feedback to be negative. W e can now obtain A (for the circuit in Fig. 8.21c) as f
s
8.6.3 The Shunt-Series Configuration Figure 8.22 s h o w s the ideal structure of the s h u n t - s e r i e s feedback amplifier. It is a current amplifier w h o s e gain w i t h feedback is defined as
f
V
A l+Aß
A = h_ i 2 = A - ^ I, l+A/3 /
(8.42)
r
The input resistance with feedback is the resistance seen by the current source I and is given by s
R
*
=
Ti\ß
( 8
-
4 3 )
I
8 2 3
8 2 4
1
CHAPTER 8
THE S H U N T - S H U N T A N D SHUNT-SERIES FEEDBACK AMPLIFIERS
8.6
FEEDBACK
A circuit
(a)
The A circuit is
nr O
+
R, <
V,
Ru
ZJ
R
22
-WV—0 -
J
I_.
in
•~1
r"
O'
A
y'
Ri
R. of
where R
n
and R
is obtained from
22
is obtained from
o Feedback network
©
©
Feedback network
I
ß circuit
and the gain A is defined as
A = j-
FIGURE 8 . 2 2 Ideal structure for the shunt-series feedback amplifier. (b)
ß is obtained from
V,
Feedback network
= 0 ®
li;.vc ¡¡¡¡¡ÍIIM
v¡ =
©
Feedback network
0
FIGURE 8 . 2 4 Finding the A circuit and B for the current-mixing current-sampling (shunt-series) feedback amplifier of Fig. 8.23. and that m o s t of the r e v e r s e transmission takes place in the feedback network,
FIGURE 8 . 2 3 Block diagram for a practical shunt-series feedback amplifier.
^12! basic A g a i n w e note that the shunt connection at the input r e d u c e s the input resistance. T h e output resistance w i t h feedback is the resistance seen by breaking the output circuit, such as between O and O ' , and looking b e t w e e n the t w o terminals thus generated (i.e., b e t w e e n O a n d O')T h i s resistance, R , is given b y
(8.46)
Ic?12| feedback
^
amplifier
network
Finally, w e note that o n c e R and R h a v e b e e n d e t e r m i n e d using the feedback equations (Eqs. 8.43 a n d 8.44), the input and output resistances of the amplifier proper, R and R (Fig. 8.23), can b e found as if
of
m
out
of
R
of
= R (l+AB)
1
(8.44)
a
R
if
w h e r e w e n o t e that the increase in output resistance is G i v e n a practical s h u n t - s e r i e s feedback amplifier, d i a g r a m of Fig. 8.23, w e follow the m e t h o d given in H e r e again the analysis m e t h o d is predicated on the t r a n s m i s s i o n occurs in the basic amplifier,
d u e to the current (series) sampling. such as that represented b y the block Fig. 8.24 in order to obtain A and B. assumption that m o s t of the forward
^out
=
1 R
(8.47) s
(8.48)
Rof~RL
5
IS21I feedback
^
\82l\
basic
Figure 8.25 shows a feedback circuit of the shunt-series type. Find I /I__, the transistors to have B = 100 and V = 75 V. out
(8.45)
R , and R _ . Assume m
0
t
A
network
amplifier
Solution 5
For this amplifier topology, the most convenient set of two-port parameters to use is the set of g parameters; it is the only set that provides a representation that is composed of a parallel circuit at the input and a series circuit at the output (see Appendix B).
I
We begin by determining the dc operating points. In this regard we note that the feedback signal is capacitively coupled; thus the feedback has no effect on dc bias. Neglecting the effect
CHAPTER 8
THE S H U N T - S H U N T A N D SHUNT-SERIES FEEDBACK AMPLIFIERS
8.6
FEEDBACK
The required input resistance R
of finite transistor ¿8 and V , the dc analysis proceeds as follows:
is given by (see Fig. 8.25b).
in
A
y
12——
= B l
= 1.57 V
= 7~~ \IR -\IR
R
in
100+15
if
V
= 1 . 5 7 - 0 . 7 = 0.87 V
I
= 0.87/0.87 = 1 mA
E1
El
Since R
m
- R
it follows from Fig. 8.25(b) that 4 = I . The current gain A is given by
if>
s
=
W;
y
3
i 4 r -
-
f
8
7
A
/
A
= 12-10x1 = 2 V
c l
V
Note that because Ap > 1 the closed-loop gain is approximately equal to 1 / / ? . Now, the required current gain is given by
= 2 - 0 . 7 = 1.3 V
E2
7
= 29.5 Q s
= 1 . 3 / 3 . 4 ~ 0.4 m A
£ 2
V
{out
7
= 1 2 - 0 . 4 x 8 = 8.8 V
c2
Rg
{out _
I
jn
[c
R +R I
s
L
C2
Rg
I_o
R +
R I
=
S
L
C2
S
Thus, The amplifier equivalent circuit is shown in Fig. 8.25(b), from which w e note that the feedback network is composed of R 2
c
0 U t
/ / , will be slightly different than the closed-loop current gain A i n
f
=
The output resistance R
of
is given by
I /I . 0
s
R
of
T h e A circuit is shown in Fig. 8.25(c), where w e have obtained the loading effects of the feedback network using the rules of Fig. 8,24. For the A circuit we can write V
xl
= flRJ/iR^
V
b2
= -g iV, {r ///? //[r m
+ 1
c l
J [ 2
r
e2
+
140.1 k Q
can be obtained using the technique employed
out
in Example 8.2, namely, by considering that the effect of feedback is to place a resistance
R h\ of
2
+ (j8 + l ) ( / ? / / / ? ) ] } £2
Substituting, r results in
f
o2i^+g i{rJIR )] m
= 7 5 / 0 . 4 = 187.5 k Q , g
m2
R
where we have neglected the effect of r . These equations can be combined to obtain the open-
oat
u2
loop current gain A,
r
*out =
/
(R IIR ) E2
-
0
the emitter of Q (see Fig. 8.25e). Thus, using Eq. (6.78), w e can write
RfV/RJ/r^]
o l
= R (l+AB)
An estimate of the required output resistance i ?
o2
0
= "3-44 A / A
f
Q , I„, which is approximately equal to the collector current I . Also note that the required current gain, 7
W i n
and R . The feedback network samples the emitter current of
E2
of
= 16 m A / V , r
= 6.25 k Q , and R
n2
of
= 140.1 k Q ,
= 18.1 M O
Thus, while negative feedback considerably increases R , mt
the increase is not by the factor (1 + A/3),
simply because the feedback network samples the emitter current and not the collector current.
A= — — - 2 0 1 . 4 5 A/A h
Thus, in effect, the feedback network "does not k n o w " about the existence of r . o2
T h e input resistance R is given by t
Ri = RJI(R
+ R )IIR llr
E2
f
B
= 1.535 k Q
nl
The output resistance R is that found by looking into the output loop of the A circuit between 0
nodes Y and Y' (see Fig. 8.25c) with the input excitation l effect of r
o2
t
set to zero. Neglecting the small
it can be shown that
1.7 Use the feedback method to find the voltage gain V /V , the input resistance R- . and the output resistance R of the inverting o p - a m p configuration of Fig. E 8 . 7 . Let the o p a m p have o p e n - l o o p gain H = 1 0 V/V, R = 100 k Q , and r„ = 1 k Q . (Hint: T h e feedback is of the shunt-shunt type.) 0
s
m
om
4
u
R
0
= (R f/ ) E2
Rf
+r
e2
+
R
jj^
= 2.69 k Q
R, =
R j l I
=
P
0
R
E2
^ ? _ = - M = _ + Rf 13.4
0.254
1 kil
- W v
T h e circuit for determining ¿8 is shown in Fig. 8.25(d), from which w e find
- v.
O
: A'
:
ki»
Thus, 1 + A / 3 = 52.1 F I G U R E ES.7
The input resistance R is given by if
Ans. -
\
\ ; | s i i I)
:
o2 11
8 2 9
ï ^
00
<=>*-< 00 ^ CO 00 00
CS CS CS 00* 00* oô CO
^
^
8.6.4 Summary of Results
CS 00 CO* CO CO
CO 00 00 CO
DETERMINING THE LOOP
8.7
Table 8.1 p r o v i d e s a s u m m a r y of the rales and relationships e m p l o y e d in t h e analysis of t h e four types of f e e d b a c k amplifier.
oa.
=a.
+
+
=3.
+
N
N +
' 8.7
W e h a v e already seen that the loop gain AB is a very i m p o r t a n t quantity that characterizes a
«a. «a.
feedback loop. F u r t h e r m o r e , in the following sections it will b e s h o w n that AB d e t e r m i n e s
+
N
N
+
whether the f e e d b a c k amplifier is stable (as o p p o s e d to oscillatory). In this section, w e shall
NT
N
J3 a
1>
describe an alternative approach to t h e determination of loop gain.
8.7.1 An Alternative Approach for Finding Afi
.'S
u
c
Ö
0)"
D S C o o 7"! Ö o< O > O,
g S
L I S
u
•s.a2 u S 9 a M « i 53
M ,
a C3
T3 O
Consider first the general f e e d b a c k amplifier s h o w n in Fig. 8 . 1 . Let the external source x b e s
set to zero. O p e n t h e f e e d b a c k loop by b r e a k i n g the c o n n e c t i o n of x to t h e f e e d b a c k net-
a. o o o >
fcl
s
5
DETERMINING THE LOOP GAIN
a
w o r k and apply a test signal x . W e see that the signal at the output of the f e e d b a c k n e t w o r k t
TA
is Xf= fix/, that at t h e input of the basic amplifier is x — -fix,; and the signal at the output of t
.9 o a
£Hi
ff .a g u m
03 C
O S O' a CM J ? o
J» . aJ o 8 S
60 S a •s u a O .3 c-'_ a >>" CQ
a <~ es ^
H O O ~
u p .
O o . .55 a O o
pa
H S Üs
g u pa
the amplifier, w h e r e the l o o p w a s broken, will b e x = -ABx . a
.5
O Q •
1 *
is given b y t h e n e g a t i v e of the ratio of the returned
-Is
-s S '
is, AB = —x /x .
PoùQ .3 g TU 2s
broken.
It should also b e o b v i o u s that this applies regardless of w h e r e the l o o p is
o
the conditions that existed prior to breaking the loop do not c h a n g e . This is achieved b y termi-
o g u
nating the loop w h e r e it is o p e n e d with an i m p e d a n c e e q u a l to that seen before the loop w a s
cs^ vi .,
t
It follows that the l o o p gain AB
However, in breaking the feedback loop of a practical amplifier circuit, w e must ensure that
so
^ g
a
t
signal to the applied test signal; that
broken. T o b e specific, consider the conceptual f e e d b a c k loop s h o w n in F i g . 8.26(a). If w e
PQ
break the loop at X X ' , and apply a test voltage V, to the terminals thus created to the left of X X ' , t h e terminals at t h e right of X X ' should b e l o a d e d w i t h an i m p e d a n c e Z as s h o w n in t
c
Fig. 8.26(b). T h e i m p e d a n c e Z, is equal to that previously seen looking to the left of X X ' .
> ML)
o
H
The loop gain Af5 is t h e n d e t e r m i n e d from
o Z,
J3
H
^l*>
Aß
(8.49)
=
1*^ Finally, it should b e n o t e d that in s o m e cases it m a y be c o n v e n i e n t to d e t e r m i n e AB b y applying a test current / , and finding the returned current signal I . In this case, AB =
-l /l .
r
r
t
A n alternative e q u i v a l e n t m e t h o d for d e t e r m i n i n g Aj5 (see R o s e n s t a r k , 1986) that is usually c o n v e n i e n t to e m p l o y especially in S P I C E simulations is as follows: A s before, the loop is broken at a c o n v e n i e n t point. T h e n the open-circuit transfer function T
oc
indicated in Fig. 8.26(c), and the short-circuit transfer function T
sc
is d e t e r m i n e d as
is d e t e r m i n e d as s h o w n in
Fig. 8.26(d). T h e s e t w o transfer functions are then c o m b i n e d to obtain the loop gain AB,
Aß, CA O 3
(8.50)
O
Ö
This m e t h o d is particularly useful w h e n it is not easy to d e t e r m i n e the t e r m i n a t i o n i m p e d -
•2 a h
ance Z,. I S 'S, » «
3 •
."¿¿3
3 CA
ï
a
C C3
I CS
T o illustrate t h e p r o c e s s of d e t e r m i n i n g loop gain, w e consider the f e e d b a c k l o o p s h o w n in Fig. 8.27(a). This feedback loop represents both the inverting and the noninverting o p - a m p
GAIN
CHAPTER 8
FEEDBACK
8.7
DETERMINING THE LOOP
(c) FIGURE 8 . 2 7 The loop gain of the feedback loop in (a) is determined in (b) and (c).
(c)
8.7.2 Equivalence of Circuits from a Feedback-Loop Point of View
(d)
FIGURE 8 . 2 6 A conceptual feedback loop is broken at X X ' and a test voltage V, is applied. The imped ance Z, is equal to that previously seen looking to the left of X X ' . The loop gain A/5 = -V /V , where V is the returned voltage. As an alternative, Ad can be determined by finding the open-circuit transfer function T , as in (c), and the short-circuit transfer function T , as in (d), and combining them as indicated. r
oc
t
r
sc
configurations. U s i n g a simple equivalent circuit m o d e l for the o p a m p w e obtain t h e circuit of Fig. 8.27(b). E x a m i n a t i o n of this circuit reveals that a convenient place to break t h e loop is at the input terminals of the op a m p . T h e loop, b r o k e n in this manner, is s h o w n in Fig. 8.27(c) w i t h a test signal V, applied to the r i g h t - h a n d - s i d e terminals a n d a resistance R terminating the left-hand-side terminals. T h e returned v o l t a g e V is found b y inspection as id
r
{ K / / [ * + / V / ( A , + R)]} L
r
M
1
{R //[R L
2
[RJ/jRu
2
+ R //(R l
id
+ R)l}
+
r W(R 0
id
+ R)]
R
id
+ R)l+R2R,d
( g
5
1
)
+R
This e q u a t i o n c a n b e u s e d directly to find t h e l o o p gain L = AB = -V /V =-V /V Since t h e loop gain L is generally a function of frequency, it is usual to call it l o o p r
t r a n s m i s s i o n a n d denote it b y L(s) or L(ja>).
t
r
v
F r o m the study of circuit theory w e k n o w that the poles of a circuit are i n d e p e n d e n t of t h e external excitation. In fact the poles, or the natural m o d e s (which is a m o r e appropriate n a m e ) , are d e t e r m i n e d b y setting the external excitation to zero. It follows that the poles of a feedback amplifier depend only on the feedback loop. This will b e confirmed in a later section, where w e s h o w that the characteristic equation ( w h o s e roots are the poles) is c o m p l e t e l y determined b y the l o o p gain. T h u s , a given feedback l o o p m a y b e used to generate a n u m b e r of circuits h a v i n g t h e s a m e poles b u t different transmission zeros. T h e closed-loop gain a n d the transmission zeros d e p e n d on h o w and w h e r e the input signal is injected into the l o o p . A s an e x a m p l e consider t h e feedback l o o p of F i g . 8.27(a). This loop can b e u s e d to gen erate the noninverting o p - a m p circuit b y feeding the input voltage signal to t h e terminal of R that is c o n n e c t e d to ground; that is, w e lift this terminal off g r o u n d a n d connect it to V . T h e same feedback loop c a n b e u s e d to generate the inverting o p - a m p circuit b y feeding t h e input v o l t a g e signal to the terminal of i?, that is c o n n e c t e d to ground. s
R e c o g n i t i o n of the fact that t w o or m o r e circuits are equivalent from a feedback-loop point of v i e w is very useful b e c a u s e (as will b e s h o w n i n Section 8.8) stability is a function of the loop. T h u s o n e n e e d s to perform the stability analysis only o n c e for a given loop. In C h a p t e r 12 w e shall e m p l o y the concept of loop e q u i v a l e n c e in t h e synthesis of active filters.
GAIN
CHAPTER 8
8 3 4
FEEDBACK
8.8
It is the m a n n e r in w h i c h the loop gain varies w i t h frequency that d e t e r m i n e s the stability or
EXERCISES
instability of t h e f e e d b a c k amplifier. T o a p p r e c i a t e this fact, c o n s i d e r the frequency at w h i c h the p h a s e a n g l e
8.8
Consider the feedback amplifier whose equivalent circuit is shown in Fig. 8.25(b). Break the feedback loop at the input to transistor Q-,: that is, apply a test voltage V, to the base of Q,, and find the returned voltage that appears across r . Thus show that the loop gain is given (neglecting r „ , t o simplify the analysis) by: Ap
= g,„ \rJ/R //\r ]
n
R II(R E2
X
R ll{R E2
+ (h
7!2
{
f
+
fc
itive. If at co = co
m
+ (R //RJ/r )) u
H
+r
KX
e2
(R //R //r ) f
B
f
will b e greater than t h e o p e n - l o o p gain A
(jco),
since the
will b e stable.
ra
O n the other h a n d , if at the frequency co
the m a g n i t u d e of the l o o p gain is e q u a l to
m
unity, it follows from E q . (8.53) that
+R
ri
A (jco)
d e n o m i n a t o r of E q . (8.53) will b e s m a l l e r than unity. N e v e r t h e l e s s , t h e f e e d b a c k amplifier
RjIRgllr^
K]
+ {R JIRJIr )) r
f
t h e m a g n i t u d e of the l o o p gain is less than unity, t h e n from E q . (8.53) w e
see that t h e c l o s e d - l o o p gain
l)(R ll(K +{K /IRJ/r )))]} E2
t h e l o o p g a i n A(jco)[3(jeo) will
b e a real n u m b e r w i t h a n e g a t i v e sign. T h u s at this frequency t h e f e e d b a c k will b e c o m e p o s
Ki
r
A (jco) f
will b e infinite. This m e a n s that the amplifier
will h a v e an o u t p u t for z e r o input; this is b y definition an oscillator. T o visualize h o w this
Using'the COMPONENT MILLIE* in l.vmiplo S . l . liiul THE VALUE of \/)'AND CMIIPAIV II u i t h the value found
feedback l o o p m a y oscillate, consider the g e n e r a l l o o p of Fig. 8.1 with t h e external i n p u t x
in Example 8.4.
set to z e r o . A n y d i s t u r b a n c e in the circuit, such as the c l o s u r e of t h e p o w e r - s u p p l y switch,
s
will g e n e r a t e a signal x,(t) at the input to the amplifier. S u c h a n o i s e signal u s u a l l y c o n t a i n s a
Ans. 49.3 versus 52.1 8.9
THE STABILITY PROBLEM
w i d e r a n g e of frequencies, a n d w e shall n o w c o n c e n t r a t e o n t h e c o m p o n e n t with frequency
Find the numerical value of A/? for the amplifier in Exercise 8.7.
co = co , m
Ans. ( S 5 8 0 W \
that is, t h e signal X
sin(t»
t
180
r ) . T h i s i n p u t signal will result in a feedback signal
given b y
X = AUco^PUco^X; f
' 8.8
Since X is f
THE STABILITY PROBLEM
= -X;
further m u l t i p l i e d b y - 1 in the s u m m e r b l o c k at the input, w e see that the feed
back causes t h e signal X,- at the amplifier i n p u t to b e sustained.
T h a t is, from this p o i n t on,
there will b e sinusoidal signals at the amplifier i n p u t a n d o u t p u t of frequency co . m
8.8.1 Transfer Function of the Feedback Amplifier
amplifier is said to oscillate at the frequency
In a f e e d b a c k amplifier such as that r e p r e s e n t e d b y t h e general structure of F i g . 8.1, the o p e n - l o o p gain A is generally a function of frequency, a n d it s h o u l d therefore b e m o r e accu
T h u s the
co . m
T h e q u e s t i o n n o w is: W h a t h a p p e n s if at a>
m
t h e m a g n i t u d e of the l o o p gain is greater
than u n i t y ? W e shall a n s w e r this question, n o t in g e n e r a l , but for the restricted yet v e r y
A l s o , w e h a v e b e e n a s s u m i n g for the
important class of circuits in w h i c h w e are interested h e r e . T h e a n s w e r , w h i c h is not o b v i o u s
m o s t p a r t that t h e feedback n e t w o r k is resistive a n d h e n c e that the f e e d b a c k factor P is con
from E q . (8.53), is that the circuit will oscillate, a n d the oscillations will g r o w in a m p l i t u d e
rately called the o p e n - l o o p t r a n s f e r f u n c t i o n , A(s).
stant, b u t this n e e d not b e a l w a y s t h e c a s e . W e shall therefore a s s u m e that in t h e general case
until s o m e n o n l i n e a r i t y ( w h i c h is a l w a y s p r e s e n t in s o m e form) r e d u c e s the m a g n i t u d e of the
t h e f e e d b a c k transfer f u n c t i o n is P(s). It follows that t h e c l o s e d - l o o p t r a n s f e r function
loop gain to e x a c t l y unity, at w h i c h p o i n t sustained oscillations will b e obtained. This m e c h
A (s) f
is g i v e n b y
anism for starting oscillations b y u s i n g p o s i t i v e f e e d b a c k with a l o o p gain greater than unity,
?
and then u s i n g a n o n l i n e a r i t y to r e d u c e t h e l o o p gain to unity at t h e desired a m p l i t u d e , will A As) = }
•A
^
(8-52)
be exploited in the d e s i g n of sinusoidal oscillators in C h a p t e r 13. O u r objective h e r e is j u s t the opposite: N o w that w e k n o w h o w oscillations c o u l d o c c u r in a n e g a t i v e - f e e d b a c k a m p l i
l+A(s)P(s)
fier, w e w i s h to find m e t h o d s to p r e v e n t their o c c u r r e n c e .
T o focus attention on the p o i n t s central to o u r discussion in this section, w e shall assume that t h e amplifier is direct-coupled w i t h c o n s t a n t d c gain A a n d with p o l e s a n d z e r o s occur 0
ring in the h i g h - f r e q u e n c y b a n d . A l s o , for t h e t i m e b e i n g let u s a s s u m e that at l o w frequen cies p(s)
r e d u c e s to a constant value. T h u s at l o w frequencies t h e l o o p g a i n
A(s)P(s)
b e c o m e s a constant, w h i c h should b e a p o s i t i v e n u m b e r ; o t h e r w i s e the f e e d b a c k w o u l d not b e n e g a t i v e . T h e question then is: W h a t h a p p e n s at h i g h e r frequencies?
(
i
w
)
=
T h e N y q u i s t p l o t is a formalized a p p r o a c h for testing for stability b a s e d o n the discussion above. It is s i m p l y a p o l a r p l o t of l o o p gain w i t h frequency u s e d as a p a r a m e t e r . F i g u r e 8.28 shows s u c h a plot. N o t e that the radial d i s t a n c e is \AP\ a n d the angle is the p h a s e a n g l e 0.
F o r p h y s i c a l frequencies s = jco, E q . (8.52) b e c o m e s A
8.8.2 The Nyquist Plot
The solid-line p l o t is for positive
A(jCQ)
(
8
53)
frequencies.
S i n c e the l o o p g a i n — a n d for that m a t t e r a n y
g a m function of a p h y s i c a l n e t w o r k — h a s a m a g n i t u d e that is an e v e n function of frequency and a p h a s e that is an o d d function of frequency, the A/3 plot for n e g a t i v e frequencies
T h u s t h e l o o p gain A(jco)P(jco)
is a c o m p l e x n u m b e r that c a n b e r e p r e s e n t e d b y its magni
(shown in F i g . 8.28 as a b r o k e n line) can b e d r a w n as a m i r r o r i m a g e t h r o u g h the R e axis. T h e N y q u i s t p l o t i n t e r s e c t s t h e n e g a t i v e r e a l axis at t h e
tude and phase,
frequency
co . m
T h u s , if this
intersection o c c u r s to t h e left of the p o i n t ( - 1 , 0 ) , w e k n o w that t h e m a g n i t u d e of l o o p L(jco)
SE
A(jco)P(jco)
5 4 )
gain at this f r e q u e n c y is g r e a t e r t h a n u n i t y a n d t h e a m p l i f i e r will b e u n s t a b l e . O n t h e o t h e r hand, if the i n t e r s e c t i o n o c c u r s to the right of t h e p o i n t ( - 1 , 0) t h e a m p l i f i e r will b e stable.
=
mco)
\A(jco)p(jco)\e
It follows that if t h e N y q u i s t p l o t encircles
t h e p o i n t ( - 1 , 0) t h e n t h e a m p l i f i e r w i l l b e
835
8 3 6
•.
CHAPTER 8
8.9
FEEDBACK
EFFECT O F F E E D B A C K O N T H E A M P L I F I E R POLES
8.9.1 Stability and Pole Location
Iml
W e shall b e g i n by considering t h e relationship b e t w e e n stability and p o l e location. F o r an amplifier or any other s y s t e m to b e stable, its p o l e s should lie in t h e left half of t h e s plane. A pair of c o m p l e x - c o n j u g a t e poles o n the jco axis gives rise to sustained sinusoidal oscilla tions. P o l e s in the right half of t h e s plane g i v e rise to g r o w i n g oscillations.
w negative ai increasing, in
T o verify the statement above, consider an amplifier with a p o l e pair at s = a0 ± ja>„. If this amplifier is subjected to a d i s t u r b a n c e , such as that c a u s e d b y c l o s u r e of t h e p o w e r supply switch, its transient r e s p o n s e will contain terms of the form v(t) = e
[e
+e
0
] = 2e
cos(ay)
(8.55)
This is a sinusoidal signal with an e n v e l o p e e"'. N o w if the poles are in t h e left half of t h e s plane, then r j will b e n e g a t i v e and t h e oscillations will d e c a y exponentially t o w a r d zero, as s h o w n in Fig. 8.29(a), indicating that the system is stable. If, on the other hand, the poles are in the right half-plane, then O" will b e positive, and the oscillations will grow exponentially 0
0
FIGURE 8 . 2 8 The Nyquist plot of an unstable amplifier.
u n s t a b l e . It s h o u l d b e m e n t i o n e d , h o w e v e r , that this s t a t e m e n t is a simplified v e r s i o n of t h e N y q u i s t c r i t e r i o n ; n e v e r t h e l e s s , it a p p l i e s to all t h e circuits in w h i c h w e are inter ested. F o r t h e full t h e o r y b e h i n d t h e N y q u i s t m e t h o d a n d for details of its application, consult Haykin (1970).
8.10 Consider a feedback amplifier for which the open-loop transfer function A (s) is given by 10 -l+s/10 Let the feedback factor B be a constant independent of frequency. Find the frequency
fi^at
which the
phase shift is 180°. Then, show that the feedback amplifier will be stable if the feedback factor B is less than a critical value B and unstable if B > B , and find the value of /!,.. a
Ans.
a
= 7 3 x 1 0 rad/s; B = 0.008 4
m
a
.1.9 EFFECT OF FEEDBACK ON THE AMPLIFIER POLES T h e amplifier frequency r e s p o n s e and stability are d e t e r m i n e d directly by_ its p o l e s . W e shall therefore investigate the effect of f e e d b a c k o n t h e poles of t h e amplifier.
6
For a brief review of poles and zeros and related concepts, refer to Appendix E.
FIGURE 8 . 2 9 Relationship between pole location and transient response.
8 3 8
:".„\
CHAPTER 8
FEEDBACK
(until s o m e nonlinearity limits their g r o w t h ) , as s h o w n in F i g . 8.29(b). Finally, if the poles are o n the ja
EFFECT OF FEEDBACK O N THE AMPLIFIER POLES
8.9
.
dBA
axis, then o will b e zero and t h e oscillations will b e sustained, as s h o w n in 0
20 log (1 +
Fig. 8.29(c).
oh
i
A l t h o u g h the discussion a b o v e is in terms of c o m p l e x - c o n j u g a t e p o l e s , it c a n b e s h o w n j plane
that the e x i s t e n c e of a n y right-half-plane poles results in instability.
A 3)
0
8.9.2 Poles of the Feedback Amplifier F r o m t h e c l o s e d - l o o p transfer function in E q . (8.52), w e see that t h e p o l e s of t h e feedback amplifier are the zeros of 1 + A(s)B(s).
T h a t is, t h e feedback-amplifier p o l e s are obtained by w
solving t h e e q u a t i o n
Pf
l+A(s)B(s)
= 0
(8.56)
w h i c h is called t h e c h a r a c t e r i s t i c e q u a t i o n of t h e f e e d b a c k l o o p . It s h o u l d therefore be
- co (l +
A B)
P
co (log scale)
0
(a)
(b)
FIGURE 8 . 3 0 Effect of feedback on (a) the pole location and (b) the frequency response of an amplifier having a single-pole open-loop response.
apparent that applying feedback to an amplifier c h a n g e s its p o l e s . In t h e following, w e shall c o n s i d e r h o w f e e d b a c k affects the amplifier p o l e s . F o r this p u r p o s e w e shall a s s u m e that the o p e n - l o o p amplifier has real p o l e s and n o finite zeros (i.e., all t h e zeros are at s = °°). This will simplify the analysis a n d e n a b l e us to focus our attention
result, h o w e v e r , is hardly surprising, since the p h a s e lag associated with a single-pole r e s p o n s e can n e v e r b e greater than 90°. T h u s the loop gain n e v e r achieves the 180° p h a s e shift required for the f e e d b a c k to b e c o m e positive.
o n the f u n d a m e n t a l c o n c e p t s i n v o l v e d . W e shall also a s s u m e that t h e f e e d b a c k factor ¡5 is i n d e p e n d e n t of frequency.
8.9.3 Amplifier with a Single-Pole Response
8.11 An op a m p having a single-pole rolloff at 100 Hz and a low-frequency gain of 10 is operated in a feedback loop with B = 0 . 0 1 . What is the factor by which feedback shifts the pole? To what frequency? If B is changed to a value that results in a closed-loop gain of + 1 , to what frequency does the pole shift? Ans. K i d ] 100.1 kHz; 1 0 M H z 5
C o n s i d e r first the c a s e of an amplifier w h o s e o p e n - l o o p transfer function is characterized by a single p o l e :
:
A(s)
A
= .
\
1
(8.57)
+s/CQ
P
T h e c l o s e d - l o o p transfer function is given b y A
A As) = / V
;
°
8.9.4 Amplifier with Two-Pole Response /
(
1
+
A
^ s/co (l+A B) P
Q
T h u s t h e f e e d b a c k m o v e s the p o l e along t h e n e g a t i v e real axis to a frequency a=
(8.58)
Q
l +
(0 , Pf
® (1+A B)
Pf
P
Consider next am amplifier w h o s e o p e n - l o o p transfer function is characterized b y t w o realaxis poles:
( 8
(l+s/o) )(l+s/co )
(8.59)
0
Pl
P2
-
6 1 )
In this case, t h e c l o s e d - l o o p p o l e s are obtained from 1 + A(s)/3 = 0, w h i c h leads to T h i s p r o c e s s is illustrated in F i g . 8.30(a). F i g u r e 8.30(b) s h o w s B o d e plots for \A\ a n d
\A \.
N o t e that w h i l e at l o w frequencies the difference b e t w e e n t h e t w o plots is 2 0 l o g ( l +
A B),
f
0
t h e t w o c u r v e s c o i n c i d e at h i g h frequencies. O n e c a n s h o w that this i n d e e d is the case by a p p r o x i m a t i n g E q . (8.58) for frequencies co > co (\ P
A (s) f
1
-
^
-
+A B):
Pl
+ co ) + ( 1 + A B)o3 (o P2
0i
Pi
= 0
P2
(8.62)
Thus the c l o s e d - l o o p p o l e s are given b y
0
A(s)
2
s + s{co
(8.60)
s
Physically speaking, at such high frequencies the loop gain is m u c h smaller than unity and the
s = -\{cDp_ + (o ) P2
± Y((Op_
+ o) F-4(1+A B)co oo P2
F i g u r e 8.30(b) clearly illustrates t h e fact that a p p l y i n g n e g a t i v e f e e d b a c k to an amplifier results in e x t e n d i n g its b a n d w i d t h at the e x p e n s e of a r e d u c t i o n in gain. S i n c e t h e p o l e of the c l o s e d - l o o p amplifier n e v e r enters the right half of t h e s p l a n e , the single-pole amplifier is stable for a n y v a l u e of B. T h u s this amplifier is said to be u n c o n d i t i o n a l l y stable. This
P1
P2
(8.63)
From E q . (8.63) w e see that as the loop gain A /3 is increased from z e r o , the p o l e s are brought closer together. T h e n a v a l u e of l o o p gain is r e a c h e d at w h i c h the p o l e s b e c o m e coincident. If the l o o p g a i n is further increased, the p o l e s b e c o m e c o m p l e x conjugate and move along a vertical line. F i g u r e 8.31 s h o w s the locus of the p o l e s for increasing l o o p gain. This plot is called a r o o t - l o c u s d i a g r a m , w h e r e " r o o t " refers to the fact that t h e p o l e s are the roots of the characteristic e q u a t i o n . 0
f e e d b a c k is ineffective.
0
8 3 9
CHAPTER 8 F E E D B A C K 8.9
EFFECT OF F E E D B A C K O N T H E A M P L I F I E R P O L E S
.
t s plane -0)pi
~Q>P2
F I G U R E 8 . 3 1 Root-locus diagram for a feedback amplifier whose open-loop transfer function has two real poles. TO (log scale) F r o m the root-locus d i a g r a m of Fig. 8.31 w e see that this feedback amplifier also is unconditionally stable. A g a i n , this result s h o u l d c o m e as n o surprise; the m a x i m u m phase shift of AC?) in this case is 180° (90° p e r p o l e ) , but this value is r e a c h e d at co= °°. T h u s there is n o finite frequency at w h i c h the p h a s e shift r e a c h e s 180°. A n o t h e r observation to m a k e on the root-locus d i a g r a m of Fig. 8.31 is that the open-loop amplifier m i g h t h a v e a d o m i n a n t pole, but this is not necessarily the case for the closed-loop amplifier. T h e r e s p o n s e of the closed-loop amplifier can, of course, always b e plotted once the poles h a v e b e e n found from E q . (8.63). A s is t h e case with second-order responses generally, the c l o s e d - l o o p r e s p o n s e c a n s h o w a p e a k (see C h a p t e r 12). T o b e m o r e specific, the characteristic equation of a second-order n e t w o r k can be written in the standard form CO
2
s + s—
2^
+ co
0
FIGURE 8 . 3 3 Normalized gain of a two-pole feedback amplifier for various values of Q. Note that Q is determined by the loop gain according to Eq. (8.65).
F r o m t h e study of s e c o n d - o r d e r n e t w o r k r e s p o n s e s in C h a p t e r 12, it will b e seen that the response of the feedback amplifier u n d e r consideration s h o w s n o p e a k i n g for Q < 0.707. The b o u n d a r y case c o r r e s p o n d i n g to Q = 0.707 (poles at 4 5 ° angles) results in t h e m a x i m a l l y flat r e s p o n s e . F i g u r e 8.33 s h o w s a n u m b e r of possible responses obtained for various values of Q (or, correspondingly, various values of A0/3).
(8.64)
0
Q
w h e r e cab is called the pole f r e q u e n c y and Q is called p o l e Q factor. T h e poles are c o m p l e x if Q is greater than 0.5. A geometric interpretation for (OQ and Q of a pair of complex-conjugate poles is given in Fig. 8.32, from w h i c h w e n o t e that co is the radial distance of the poles from the origin and that Q indicates the distance of the poles from the jco axis. Poles on the jco axis h a v e Q - ° o .
£12 A n amplifier with a low-frequency gain o f IQOand poles at 1 0 rad/s and 10'rad/s is incorporated in a « negative- feedback toop with feedback factor [i. For what value of 0 do the poles of the closed-loop, ampltficreoineide? W b a t i s the corresponding Q of the resulting second-order s w o r n ? For what value o f / i is a maKtmally flat response achieved? What is the !ov> frequency closeifloop gain m the maximally flat case? 4
0
B y c o m p a r i n g E q s . (8.62) and (8.64) w e obtain the Q factor for the poles of the feedback
Ans. 0.245: 0.5: 0.5: 1.96 \ 7 V
amplifier as
J(l+A ß)co co co + co 0
Q
=
P1
P1
P
(8.65)
P2
JO>k
i \i
As an illustration of some of the ideas just discussed, we consider the positive-feedback circuit shown in Fig. 8.34(a). Find the loop transmission L(s) and the characteristic equation. Sketch a few root-locus diagram for varying K, and find the value of K that results in a maximally flat response, Wj. and the value of K that makes the circuit oscillate. Assume that the amplifier has infinite input t impedance and zero output impedance.
s plane
— H ft>
Solution
0
*
2 Q
F I G U R E 8 . 3 2 Definition of 0% and Q of a pair of complexconjugate poles.
^
To obtain the loop transmission, w e short-circuit the signal source and break the loop at the amplifier input. W e then apply a test voltage V, and find the returned voltage V„ as indicated in
841
842
CHAPTER
8.9 8
EFFECT OF FEEDBACK O N THE AMPLIFIER
FEEDBACK
Thus, j, x L(s) =
-s(K/CR) -•—!> 1 s +s(3/CR) + {l/CR)
(8.68) 2
The characteristic equation is 1+L(s)
= 0
(8.69)
that is,
CR
S+S
\CRJ
CR
+
=
-CR {CR)
O
( 8
-
? O )
By comparing this equation to the standard form of the second-order characteristic equation (Eq. 8.64) we see that the pole frequency COQ is given by
ö
°
=
CT?
( 8
-
? 1 )
and the Q factor is Q = ^
(8.72)
Thus, for K = 0 the poles have Q = | and are therefore located on the negative real axis. As K is increased the poles are brought closer together and eventually coincide (Q = 0,5, K= 1). Further increasing K results in the poles becoming complex and conjugate. The root locus is then a circle because the radial distance co remains constant (Eq. 8.71) independent of the value of K. 0
The maximally flat response is obtained when Q = 0.707, which results when K = 1.586. In this case the poles are at 45° angles, as indicated in Fig. 8.34(c). The poles cross the jco axis into the right half of the s plane at the value of K that results in Q = °°, that is, K=3. Thus for K > 3 this circuit becomes unstable. This might appear to contradict our earlier conclusion that the feedback amplifier with a second-order response is unconditionally stable. Note, however, that the circuit in this example is quite different from the negative-feedback amplifier that we have been studying. Here we have an amplifier with a positive gain K and a feedback network whose transfer function T(s) is frequency dependent. This feedback is in fact positive, and the circuit will oscillate at the frequency for which the phase of T(jco) is zero.
E x a m p l e 8.5 illustrates the u s e of f e e d b a c k (positive f e e d b a c k in this case) to m o v e the poles of an R C n e t w o r k from their n e g a t i v e real-axis locations to c o m p l e x - c o n j u g a t e loca tions. O n e can a c c o m p l i s h t h e s a m e task u s i n g n e g a t i v e feedback, as the root-locus d i a g r a m of Fig. 8.31 d e m o n s t r a t e s . T h e process of p o l e control is t h e e s s e n c e of active-filter design, as will b e discussed in C h a p t e r 12. Fig. 8.34(b). The loop transmission L(s) =A(s)ß(s) Us)
=
is given by =
8.9.5 Amplifiers with Three or More Poles
(8.66)
-KT(s)
'38
where T(s) is the transfer function of the two-port R C network shown inside the broken-line box in Fig. 8.34(b):
Figure 8.35 s h o w s t h e root-locus d i a g r a m for a feedback amplifier w h o s e o p e n - l o o p response is characterized b y three p o l e s . A s indicated, increasing the loop gain from zero moves the highest-frequency p o l e o u t w a r d w h i l e t h e t w o other poles are b r o u g h t closer together. A s A j5 is increased further, the t w o poles b e c o m e coincident and then b e c o m e complex a n d conjugate. A v a l u e of A B exists at w h i c h this pair of c o m p l e x - c o n j u g a t e poles enters the right half of the s plane, thus c a u s i n g the amplifier to b e c o m e unstable. Q
sjl/CR) v
i
2
s + s(3/CR)
(8.67) +
(l/CRT
Q
POLES
844
flJ:
1
CHAPTER 8
FEEDBACK
8.10
STABILITY STUDY USING BODE
PLOTS
Let the feedback factor ß be frequency independent. Find the closed-loop poles as functions of ß, and show that the root locus is that of Fig. E8.13. Also find the value of ß at which the amplifier becomes unstable. (Note: This is the same amplifier that was considered in Exercise 8.10.)
s plane (normalized to 10 rad/s)
a
4
FIGURE 8 . 3 5 Root-locus diagram for an amplifier with three poles. The arrows indicate the pole movement as A„/3 is increased.
This result is n o t entirely u n e x p e c t e d , since an amplifier with three poles has a phase shift that reaches - 2 7 0 ° as co a p p r o a c h e s °°. T h u s there exists a finite frequency
0
0
0
0
FIGURE ES.13
Ans. Sec Fig. E8.13: yS , , , = 0 . 0 0 8 C] Li a
0
Before leaving this section w e p o i n t out that construction of t h e root-locus d i a g r a m for amplifiers h a v i n g three or m o r e poles as well as finite zeros is an i n v o l v e d process for w h i c h a systematic p r o c e d u r e exists. H o w e v e r , such a p r o c e d u r e will n o t b e presented here, and the interested r e a d e r should consult H a y k i n (1970). A l t h o u g h t h e root-locus d i a g r a m provides t h e amplifier designer w i t h considerable insight, other, simpler techniques b a s e d o n B o d e plots can b e effectively e m p l o y e d , as will b e e x p l a i n e d in Section 8.10.
8.13 Consider a feedback amplifier for which the open-loop transfer function A(s) is given by
8.10 STABILITY STUDY USING BODE PLOTS 8.10.1 Gain and Phase Margins F r o m Sections 8.8 a n d 8.9 w e k n o w that o n e can d e t e r m i n e w h e t h e r a f e e d b a c k amplifier is or is n o t stable b y e x a m i n i n g its l o o p gain AB as a function of f r e q u e n c y . O n e of t h e s i m plest and m o s t effective m e a n s for doing this is through the use of a B o d e plot for A/3, such as the one s h o w n in Fig. 8.36. (Note that because the p h a s e approaches - 3 6 0 ° , the network e x a m ined is a fourth-order one.) T h e feedback amplifier w h o s e loop gain is plotted in Fig. 8.36 will be stable, since at the frequency of 180° phase shift, co , the m a g n i t u d e of the loop gain is less than unity (negative d B ) . T h e difference b e t w e e n the value of \Ap\ at 0) a n d unity, called the g a i n m a r g i n , is usually e x p r e s s e d in decibels. T h e gain m a r g i n represents t h e a m o u n t b y which t h e loop gain can b e increased w h i l e stability is maintained. F e e d b a c k amplifiers are usually d e s i g n e d to h a v e sufficient gain m a r g i n to allow for the inevitable c h a n g e s in l o o p gain with t e m p e r a t u r e , time, and so on. m
m
A n o t h e r w a y to investigate t h e stability and to express its degree is to e x a m i n e the B o d e plot at t h e frequency for w h i c h \AB\ = 1, w h i c h is t h e point at w h i c h the m a g n i t u d e plot crosses the 0-dB line. If at this frequency the p h a s e angle is less (in m a g n i t u d e ) than 180°, then the amplifier is stable. T h i s is the situation illustrated in Fig. 8.36. T h e difference between t h e p h a s e angle at this frequency and 180° is t e r m e d the p h a s e m a r g i n . O n the
846
! CHAPTER 8
FEEDBACK
\Aß\
8.10
dB A
STABILITY STUDY USING BODE
PLOTS
At (Oi t h e c l o s e d - l o o p gain is A J int. } = = AfUtOi)
1
^
(8.74)
1+A(;û),)0 Substituting from Eq. (8.73a) gives
V
M
)
.
i l l Ê ï Ç
(
8
.
7
5
)
l+e Thus t h e m a g n i t u d e of the gain at co is 1
\l + e~ For a p h a s e m a r g i n of 4 5 ° , 9= 135°; a n d w e obtain \A Uah)\ f
.1 = 1.3i
'p~
(8.77)
That is, t h e gain p e a k s b y a factor of 1.3 a b o v e t h e low-frequency value of IIp. This p e a k i n g increases as t h e p h a s e m a r g i n is reduced, eventually reaching °° w h e n the p h a s e m a r g i n is zero. Z e r o p h a s e m a r g i n , of course, implies that t h e amplifier c a n sustain oscillations [poles on the jco axis; N y q u i s t plot p a s s i n g t h r o u g h ( - 1 , 0 ) ] . FIGURE 8 . 3 6 Bode plot for the loop gain Af3 illustrating the definitions of the gain and phase margins.
other hand, if at the frequency of unity loop-gain magnitude, the p h a s e lag is in excess of 180°, the amplifier will b e unstable. 8.15 Find the closed-loop gain at &>, relative to the low-frequency gain when the phase margin is 30°. 60°, and 90°. Ans. 1.93; 1: 0.707
8.14 Consider an op a m p having a single-pole open-loop response with A = 1 0 a n d / = 10 H z . L e t the op amp b e ideal otherwise (infinite input impedance, zero output impedance, etc.). If this amplifier is connected in the noninverting configuration with a nominal low-frequency closed-loop gain, of 100, find the frequency at which Aß] - 1. Also, find the phase margin. Ans. 10 Hz; 90° 5
0
P
4
8.10.3 An Alternative Approach for Investigating Stability mvestigating stability b y constructing B o d e plots for the loop gain A/3 c a n b e a tedious a n d t i m e - c o n s u m i n g process, especially if w e h a v e t o investigate the stability of a given amplifier for a variety of f e e d b a c k n e t w o r k s . A n alternative approach, w h i c h is m u c h simpler, is t o construct a B o d e plot for the o p e n - l o o p gain A(ja>) only. A s s u m i n g for the t i m e b e i n g that p is i n d e p e n d e n t of frequency, w e can plot 2 0 log(l//3) as a horizontal straight line o n t h e s a m e plane u s e d for 2 0 log \A\. T h e difference b e t w e e n t h e t w o curves will b e
8.10.2 Effect of Phase Margin on Closed-Loop Response F e e d b a c k amplifiers a r e normally d e s i g n e d w i t h a p h a s e m a r g i n of at least 4 5 ° . T h e a m o u n t of p h a s e m a r g i n h a s a profound effect o n t h e s h a p e of t h e closed-loop gain r e s p o n s e . T o see this r e l a t i o n s h i p , c o n s i d e r a f e e d b a c k amplifier w i t h a l a r g e l o w - f r e q u e n c y l o o p gain, A [3 > 1. It follows that t h e closed-loop gain at l o w frequencies is a p p r o x i m a t e l y 1/0. D e n o t i n g t h e frequency at w h i c h t h e m a g n i t u d e of l o o p gain is unity b y co w e h a v e (refer to Fig. 8.36) 0
1
A(ja> )P=lxe~
ie
1
(8.73a)
where 0 = 1 8 0 ° - p h a s e margin
(8.73b)
201og|A(;ffl)|-201og±
= 201og|A/3|
(8.78)
w h i c h is t h e l o o p gain (in d B ) . W e m a y therefore study stability b y e x a m i n i n g t h e difference between t h e t w o plots. If w e wish to evaluate stability for a different feedback factor w e simply d r a w a n o t h e r horizontal straight line at t h e level 2 0 log(l//3). T o illustrate, consider a n amplifier w h o s e o p e n - l o o p transfer function i s characterized by three poles. F o r simplicity let the three poles b e widely separated—say, at 0.1 M H z , 1 M H z , a n d 10 M H z , as s h o w n in Fig. 8.37. N o t e that because the poles are widely separated, the p h a s e is a p p r o x i m a t e l y - 4 5 ° at t h e first p o l e f r e q u e n c y , - 1 3 5 ° at t h e s e c o n d , a n d - 2 2 5 ° at the third. T h e frequency at w h i c h the p h a s e of A(jco) is - 1 8 0 ° lies o n the - 4 0 - d B / d e c a d e segment, as i n d i c a t e d i n F i g . 8.37.
8 4 7
CHAPTER 8
FEEDBACK
8.11
FREQUENCY COMPENSATION
§&S
frequency, Eq. (8.79) gives a gain m a g n i t u d e of 58.2 d B , w h i c h is r e a s o n a b l y close to the approximate v a l u e of 6 0 d B given b y Fig. 8.37. Consider next t h e straight line labeled (a) in F i g . 8.37. This line represents a feedback factor for w h i c h 2 0 log(l/j8) = 85 d B , w h i c h c o r r e s p o n d s to B- 5.623 x 1 0 " and a closedloop gain of 83.6 d B . Since the l o o p gain is the difference b e t w e e n the \A\ c u r v e and t h e IIB line, the point of intersection X_ corresponds to the frequency at w h i c h |Aj3| = 1. U s i n g the graphs of Fig. 8.37, this frequency can b e found to b e approximately 5.6 x 1 0 H z . A m o r e exact value of 4.936 x 1 0 can b e obtained using t h e transfer-function equations. At this frequency the p h a s e angle is approximately - 1 0 8 ° . T h u s the c l o s e d - l o o p amplifier, for which 2 0 log(l/j8) = 85 d B , will b e stable with a p h a s e m a r g i n of 7 2 ° . T h e gain m a r g i n can be easily obtained from F i g . 8.37; it is 25 d B .
dB A
5
5
5
Next, suppose that w e wish to use this amplifier to obtain a closed-loop gain of 5 0 - d B nominal value. S i n c e A - 100 d B , w e see that A B > 1 and 2 0 log(A B) — 5 0 d B , resulting in 201og(l/j8) — 5 0 d B . T o see whether this closed-loop amplifier is or is not stable, w e draw line (b) in F i g . 8.37 with a height of 5 0 d B . This line intersects the open-loop gain curve at point X , w h e r e the c o r r e s p o n d i n g p h a s e is greater than 180°. T h u s the c l o s e d - l o o p amplifier with 5 0 - d B gain will b e unstable. 0
0
0
2
In fact, it can easily b e seen from Fig. 8.37 that t h e minimum value of 2 0 log(l/j8) that can be used, with the resulting amplifier b e i n g stable, is 6 0 d B . In other w o r d s , t h e m i n i m u m value of stable closed-loop gain obtained with this amplifier is approximately 6 0 d B . A t this value of gain, h o w e v e r , t h e amplifier m a y still oscillate, since n o m a r g i n is left to allow for possible c h a n g e s in gain. Since the 180°-phase point always occurs o n the - 4 0 - d B / d e c a d e s e g m e n t of the B o d e plot for |A|, a rule of t h u m b to guarantee stability is as follows: The closed-loop amplifier will be stable if the 2 0 l o g ( l / / j ) line intersects the 201og[A| curve at a point on the - 2 0 - d B / decade segment. F o l l o w i n g this rule ensures that a p h a s e m a r g i n of at least 45° is obtained. For the e x a m p l e of Fig. 8.37, t h e rule implies that t h e m a x i m u m v a l u e of B is 1 0 , w h i c h corresponds to a closed-loop gain of approximately 8 0 d B . - 4
FIGURE 8.37
T h e rule of t h u m b a b o v e can b e generalized for the case in w h i c h B is a function of frequency. T h e general rule states that at the intersection of 2 0 l o g [ l / | j 8 ( j o ) | ] and 20 log|A(y'fi))| the difference of slopes (called t h e r a t e of c l o s u r e ) should not exceed 20 dB/decade.
Stability analysis using Bode plot of IAI.
T h e o p e n - l o o p gain of this amplifier can b e e x p r e s s e d as A =
^
(i +
-
(8.79)
1
jf/ i o ) ( i + jf/ i o ) ( i + jf 5
no )
6
from w h i c h \A\ can be easily d e t e r m i n e d for any f r e q u e n c y / ( i n H z ) , and the p h a s e can be obtained as 1
3
1
6
1
7
(8.80)
T h e m a g n i t u d e and p h a s e graphs s h o w n in Fig. 8.37 are obtained using t h e m e t h o d for constructing B o d e plots ( A p p e n d i x E ) . T h e s e g r a p h s p r o v i d e a p p r o x i m a t e values for impor tant amplifier p a r a m e t e r s , w i t h m o r e exact values obtainable from E q s . (8.79) and (8.80). F o r e x a m p l e , the f r e q u e n c y / at w h i c h the p h a s e angle is 180° c a n b e found from F i g . 8.37 to b e a p p r o x i m a t e l y 3.2 X 1 0 H z . U s i n g this v a l u e as a starting point, a m o r e exact value can b e found b y trial and error using Eq. (8.80). T h e result i s / = 3.34 x 1 0 H z . A t this 1 8 0
6
6
1 8 0
8.16 Consider an op amp whose open-loop gain is identical to that of Fig. 8.37. Assume that the op amp is 'ideal otherwise. Let the op amp be connected as a differentiator. Use the rale of thumb above to show that for stable performance die differentiator time constant should be greater than 159 ms. [Hint: Recall that for a differentiator, the Bode plot for l/}B(jco)\ has a slope of +20 dB/decade and intersects the 0-dB line at 1/r, where -Tis uie differentiator timeconstant.] ^
8.11
FREQUENCY COMPENSATION
In this section, w e shall discuss m e t h o d s for modifying t h e open-loop transfer function A(s) of an amplifier h a v i n g three or m o r e poles so that t h e closed-loop amplifier is stable for any desired value of closed-loop gain.
8 4
CHAPTER 8
FEEDBACK
8.11
dB À
FREQUENCY
COMPENSATION
Careful examination of Fig. 8.38 shows that the gain A'(s) is l o w because of the pole a t / . If we can s o m e h o w eliminate this pole, then—rather than locating point Y, drawing YY', and so w e can start from point Z (at the frequency of the second pole) and draw the line Z Z ' . This P 1
o
n
would result in the open-loop curve A " ( s ) , which shows considerably higher gain than A'(s). A l t h o u g h it is not possible to eliminate the p o l e at f , it is usually possible to shift that pole f r o m / = / p i to / - f' . T h i s m a k e s t h e p o l e d o m i n a n t and eliminates the n e e d for introducing an additional lower-frequency pole, as will b e explained next. P1
D
8.11.2 Implementation W e shall n o w address t h e question of i m p l e m e n t i n g the f r e q u e n c y - c o m p e n s a t i o n s c h e m e discussed a b o v e . T h e amplifier circuit n o r m a l l y consists of a n u m b e r of c a s c a d e d gain stages, with e a c h stage r e s p o n s i b l e for o n e or m o r e of the transfer-function p o l e s . T h r o u g h manual and/or c o m p u t e r analysis of the circuit, o n e identifies w h i c h stage introduces each of the important poles f ,f , and so on. F o r t h e p u r p o s e of our discussion, a s s u m e that t h e first pole//>i is i n t r o d u c e d at the interface b e t w e e n t h e t w o c a s c a d e d differential stages s h o w n in Fig. 8.39(a). In Fig. 8.39(b) w e s h o w a simple small-signal m o d e l of t h e circuit at this interface. Current source l represents the output signal current of the Q - Q stage. Resistance R and c a p a c i t a n c e C represent the total resistance and capacitance b e t w e e n the t w o n o d e s B and B ' . I t follows that t h e p o l e / ] . ! is g i v e n b y PX
P1
x
x
x
2
x
fiPI
(8.81) 2nC R r
r
2
FIGURE 8 . 3 8 Frequency compensation for /3 = 10 . The response labeled A' is obtained by introducing an additional pole at f . The A" response is obtained by moving the original low-frequency pole to f' . D
B'
D
8.11.1 Theory
I
T h e simplest m e t h o d of frequency c o m p e n s a t i o n consists of introducing a n e w p o l e in the function A(s) at a sufficiently l o w frequency, f , such that the modified open-loop gain, A'(s), intersects the 2 0 l o g ( l / | / J | ) c u r v e with a slope difference of 2 0 d B / d e c a d e . A s an e x a m p l e , let it b e required to c o m p e n s a t e the amplifier w h o s e A(s) is s h o w n in Fig. 8.38 such that closed-loop amplifiers with ¡3 as high as 1 0 " (i.e., closed-loop gains as l o w as approximately 4 0 d B ) will b e stable. First, w e d r a w a i i o r i z o n t a l straight line at the 4 0 - d B level to represent 2 0 log(l//3), as s h o w n in Fig. 8.38. W e then locate point Y on this line at the freq u e n c y of the first p o l e , / . F r o m F w e d r a w a line with - 2 0 - d B / d e c a d e slope and determine the point at w h i c h this line intersects the dc gain line, point Y'. This latter point gives the freq u e n c y f of the n e w p o l e that has to be introduced in the open-loop transfer function.
L i
1
D
2
(a)
P 1
D
T h e c o m p e n s a t e d o p e n - l o o p r e s p o n s e A'(s) is indicated in F i g . 8.38. It h a s four p o l e s : at /d»/pi./p2» a n d / . T h u s \ A ' \ begins to roll off with a slope of - 2 0 d B / d e c a d e a t / . Aif the slope c h a n g e s to - 4 0 d B / d e c a d e , at f it c h a n g e s to - 6 0 d B / d e c a d e , a n d so on. S i n c e the 2 0 l o g ( l / / J ) line intersects the 2 0 l o g | A ' | c u r v e at point Y on the - 2 0 - d B / d e c a d e s e g m e n t , the closed-loop amplifier with this ¡3 value (or l o w e r values) will b e stable. P 3
D
B'
B'
B
B
Pl
P2
A serious disadvantage of this c o m p e n s a t i o n m e t h o d is that at m o s t frequencies the openl o o p gain has b e e n drastically reduced. This m e a n s that at m o s t frequencies the a m o u n t of feedback available will b e small. Since all the a d v a n t a g e s of negative feedback are directly proportional to the a m o u n t of feedback, the p e r f o r m a n c e of the c o m p e n s a t e d amplifier has been impaired.
(b)
(c)
FIGURE 8 . 3 9 (a) Two cascaded gain stages of a multistage amplifier, fb) Equivalent circuit for the interface between the two stages in (a), (c) Same circuit as in (b) but with a compensating capacitor C added. Note that the analysis here applies equally well to MOS amplifiers. c
8 5 2
_
> CHAPTER 8
FEEDBACK
FREQUENCY C O M P E N S A T I O N
8.11
L e t u s n o w c o n n e c t t h e c o m p e n s a t i n g c a p a c i t o r C b e t w e e n n o d e s B a n d B ' . This will r e s u l t in t h e m o d i f i e d e q u i v a l e n t circuit s h o w n in F i g . 8.39(c) f r o m w h i c h w e see that the p o l e i n t r o d u c e d will n o l o n g e r b e atf ; rather, t h e p o l e c a n b e at a n y desired lower frequency :
In t h e a b s e n c e of t h e c o m p e n s a t i n g capacitor C , w e c a n see f r o m F i g . 8.40(b) that there
C
P1
f
are t w o p o l e s — o n e at t h e i n p u t a n d o n e at t h e output. L e t u s a s s u m e that t h e s e t w o p o l e s a r e /
r t
a n d / o f F i g . 8.38; thus, K
FP, = f f
D
1
= 2K{C
X
+
f? =
C
( 8 X
-
8 2
)
J
2nC R x
C )R
(8.83)
P
J p l
n
2%C R
x
2
2
With C present, analysis of the circuit yields t h e transfer function f
W e thus c o n c l u d e that o n e c a n select a n a p p r o p r i a t e v a l u e for C t o shift t h e p o l e frequency from/pi to the value d e t e r m i n e d b y p o i n t Z' in Fig. 8.38. c
A t this j u n c t u r e it should b e p o i n t e d out that a d d i n g t h e capacitor C will usually result in c h a n g e s in t h e location of the other p o l e s (those atf a n d / > ) . O n e m i g h t therefore need to calculate t h e n e w location of f a n d perform a few iterations t o arrive at t h e required v a l u e for C .
R R
_ _ T
(sCf-Sm) i 2
~ 1 + s[C R x
+ CR+
x
2
C (g R R
2
f
m
x
(§ ) 84
2
+ R + R )] + s [C C
2
x
2
x
+ C (C
2
f
x
+
C )]R R 2
X
2
C
P2
3
P2
The zero is usually at a m u c h h i g h e r frequency than t h e d o m i n a n t pole, a n d w e shall neglect its effect. T h e d e n o m i n a t o r p o l y n o m i a l D(s) c a n b e written in t h e f o r m
C
A d i s a d v a n t a g e of this i m p l e m e n t a t i o n m e t h o d is that t h e required v a l u e of C is usually
D
C
{
s w
= ( i + _ £ _ Y1 + ^ = I co A (ù' )
)
PX
quite large. T h u s if t h e amplifier t o b e c o m p e n s a t e d is a n I C o p a m p , it will b e difficult, and p r o b a b l y i m p o s s i b l e , to include this c o m p e n s a t i n g capacitor o n t h e I C chip. ( A s p o i n t e d out
w h e r e a'
in C h a p t e r 6 a n d in A p p e n d i x A , t h e m a x i m u m practical size of a m o n o l i t h i c capacitor is
be d o m i n a n t ; w'
P1
1
+
/ - J L \to_\_
P2
+ — l ^ CO CO
+
CO J P2
P1
(8.85)
P2
a n d CÛ' are t h e n e w frequencies of t h e t w o p o l e s . N o r m a l l y o n e of the p o l e s will P2
PX
< co .
Thus,
P2
about 100 p F . ) A n elegant solution t o this p r o b l e m is t o c o n n e c t t h e c o m p e n s a t i n g capacitor D(s)
in t h e f e e d b a c k p a t h of a n amplifier stage. B e c a u s e of t h e Miller effect, t h e c o m p e n s a t i n g
-
1+ - 4 -+
c a p a c i t a n c e will b e multiplied b y t h e stage gain, resulting in a m u c h larger effective capaci-
CO
\
(8-86)
(0 (O
Pl
tance. F u r t h e r m o r e , as explained later, a n o t h e r u n e x p e c t e d benefit accrues.
s
,
PX
P2
E q u a t i n g t h e coefficients of s in t h e d e n o m i n a t o r of E q . (8.84) a n d in E q . (8.86) results i n
, _
8.11.3 Miller Compensation and Pole Splitting
1
œ p i
" CR which c a n b e a p p r o x i m a t e d b y X
F i g u r e 8.40(a) s h o w s o n e gain stage in a m u l t i s t a g e amplifier. F o r simplicity, t h e stage is
X
+ CR 2
+ C (g R R
2
f
m
x
+R + R)
2
X
2
s h o w n as a c o m m o n - e m i t t e r amplifier, b u t in p r a c t i c e it can b e a m o r e e l a b o r a t e circuit. In
<
t h e f e e d b a c k p a t h of this c o m m o n - e m i t t e r stage w e h a v e p l a c e d a c o m p e n s a t i n g capacitor C . F
(8 87)
- —TFT R
-
R
8m 2Cf l
F i g u r e 8.40(b) s h o w s a simplified equivalent circuit of the gain stage of Fig. 8.40(a). Here
2
R
X
a n d C represent the total resistance a n d total capacitance b e t w e e n n o d e B a n d ground.
T o obtain cȣ, w e e q u a t e t h e coefficients of s in t h e d e n o m i n a t o r of E q . (8.84) a n d i n
X
Similarly, R
2
a n d C represent t h e total resistance a n d total capacitance b e t w e e n n o d e C 2
Eq. (8.86) a n d u s e E q . (8.87):
and g r o u n d . F u r t h e r m o r e , it is a s s u m e d that C includes t h e Miller c o m p o n e n t d u e t o capaciX
m
t a n c e Cu, a n d C includes t h e input capacitance of t h e succeeding amplifier stage. Finally, I 2
m T
represents t h e output signal current of the p r e c e d i n g stage.
'
= n
CC x
2
h£l C (C
+
f
(8.88) x
+
C) 2
F r o m E q s . (8.87) a n d (8.88), w e see that as C is increased, co' f
PX
is r e d u c e d a n d w
P2
increased. T h i s action is referred to as p o l e s p l i t t i n g . N o t e that t h e increase in co
P2
is
is highly
beneficial; it a l l o w s u s t o m o v e p o i n t Z (see F i g . 8.38) further to t h e right, thus resulting in h i g h e r c o m p e n s a t e d o p e n - l o o p gain. Finally, n o t e from E q . (8.87) that C is multiplied b y f
the Miller-effect factor g R , m
2
thus resulting in a m u c h larger c a p a c i t a n c e , g R C . m
2
f
In other
w o r d s , t h e r e q u i r e d v a l u e of C^will b e m u c h smaller t h a n that of C in F i g . 8.39. c
Consider an op amp whose open-loop transfer function is identical to that shown in Fig. 8.37. W e wish to compensate this o p amp so that the closed-loop amplifier with resistive feedback is stable for any gain (i.e., for B up to unity). Assume that the op-amp circuit includes a stage such as that (a)
(b)
of Fig. 8.40 with C = 100 pF, C = 5 p F , and g = 4 0 m A / V , that the pole a t / x
FIGURE 8 . 4 0 (a) A gain stage in a multistage amplifier with a compensating capacitor connected in the feedback path and (b) an equivalent circuit. Note that although a BJT is shown, the analysis applies equally well to the MOSFET case.
2
m
input circuit of that stage, and that the pole at f
n
P 1
is caused by the
is introduced by the output circuit. Find the
value of the compensating capacitor for two cases: either if it is connected between the input node B and ground or in the feedback path of the transistor.
8 5 3
8 5 4
i
CHAPTER 8
FEEDBACK
8.12
SPICE S I M U L A T I O N
EXAMPLE
Solution
First we détermine R and R from f x
8.17 A multipole amplifier having a first pole at 1 M H z and an open-loop gain of 100 dB is to be compen sated for closed-loop gains as low as 20 dB by the introduction of a new dominant pole. At what frequency must the new pole be placed?
1
= 0.1 M H z -
P1
2
2KC R X
X
Ans. K m 11/ R
Thus,
x
f
= — Q. In
1
1
= 1 MHz =
P2
8.18 For the amplifier described in Exercise 8.17. rather than introducing a new dominant pole, we can use additional capacitance at the circuit node at which the first pole is formed to reduce the frequency of the first pole. If the frequency of the second pole is 10 MHz and if it remains unchanged while additional capacitance is introduced as mentioned, find the frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop gains as low as 20 dB. By what factor must the capacitance at the controlling node be increased?
Thus, 71
Ans. 1000 Hz; 1000
If a compensating capacitor C is connected across the input terminals of the transistor stage, then the frequency of the first pole changes fxoxnf to f' : c
P1
r
D
1
-. 2n(C
+
x
C )R C
X
The second pole remains unchanged. The required value for f' is determined by drawing a -20-dB/ decade line from the 1-MHz frequency point on the 20 log(l//f) = 20 log 1 = 0 dB line. This line will intersect the 100-dB dc gain line at 10 Hz. Thus, D
f'
2n(C
+
l
C )R c
l
which results in C — 1 /JF, which is quite large and certainly cannot be included on the IC chip. Next, if a compensating capacitor Cf is connected in the feedback path of the transistor, then both poles change location to the values given by Eqs. (8.87) and (8.88): c
f
1 2ng R C R
=
J p l
m
2
f
f
analysis of f e e d b a c k circuits.
1
= 10 Hz =
D
W e conclude this chapter b y presenting an e x a m p l e that illustrates the u s e of S P I C E in t h e
8m^f + C {C
=
J P 1
2n[C C
l
l
2
f
/g gQ\ l
DETERMINING
THE
LOOP
GAIN
USING
SPICE
This example illustrates the use of SPICE to compute the loop gain A[3. T o be able to compare results, we shall use the same shunt-series feedback amplifier considered in Example 8.4 and redrawn in Fig. 8.41. This, however, does not limit the generality of the methods described.
+ C )] 2
T o determine where we should locate the first pole, we need to know the value of f' . approximation, let us assume that Cf > C , which enables us to obtain P2
As an
2
/' J
=
n
im 2K{C
= 60.6 M H z
+
1
C) 2
Thus it appears that this pole will move to a frequency higher than f
n
(which is 10 M H z ) . Let us
therefore assume that the second pole will be aXf . This requires that the first pole be located at P3
=
In A
=
l O l l ^
o
=
100
Hz
10
Thus, f
= 100 Hz :
Pl
1 2jzg R C R m
2
f
x
which results in C = 78.5 pF. Although this value is indeed much greater than C , we can determine the location of the pole f' from Eq. (8.89), which yields f = 57.2 M H z , confirming that this pole has indeed been moved p a s t / > . W e conclude that using Miller compensation not only results in a much smaller compensat ing capacitor but, owing to pole splitting, also enables us to place the dominant pole a decade higher in frequency. This results in a wider bandwidth for the compensated op amp. f
2
P2
P2
3
I
V A
lOkfl FIGURE 8 . 4 1
Circuit of the shunt-series feedback amplifier in Example 8.4.
85©
CHAPTER 8
8.12
FEEDBACK
To compute the loop gain, w e set the input signal
SPICE S I M U L A T I O N E X A M P L E
to zero, and we choose to break the feed
; k loop between the collector of Q and the base of Q . However, in breaking the feedback 1
2
>p, we must ensure that the following two conditions that existed prior to breaking the feed: k loop do not change: (1) the dc bias situation and (2) the ac signal termination. T o break the feedback loop without disturbing the dc bias conditions of the circuit, we insert arge inductor Lt,
reak
, as shown in Fig. 8.42(a). Using a value of, say, Lbreak
=
1 GH will ensure
it the loop is opened for ac signals while keeping dc bias conditions unchanged. T o break the feedback loop without disturbing the signal termination conditions, we must load ! loop output at the collector of g
with a termination impedance Z, whose value is equal to the
t
pedance seen looking into the loop input at the base of Q . Furthermore, to avoid disturbing the 2
bias conditions, Z, must be connected to the collector of Q via a large coupling capacitor. Howx
;r, it is not always easy to determine the value of the termination impedance Z . So, we will t
scribe two simulation methods to compute the loop gain without explicitly determining Z . t
iViethod 1
Using the open-circuit
and short-circuit
transfer
functions
described in Section 8.7, the loop gain can be expressed as
V
>ere T
OC
±
Sl
is the open-circuit voltage transfer function and T
oc
sc
is the short-circuit current transfer
tction. T h e circuit for determining T
oc
is shown in Fig. 8.42(a). Here, an ac test signal voltage V is t
ipplied to the loop input at the base of Q via a large coupling capacitor (having a value of, say, 2
F ) to avoid disturbing the dc bias conditions. Then, V rf
ere V
OC
is the ac open-circuit output voltage at the collector of Q .
oc
t
In the circuit for determining T
sc
(Fig. 8.42b), an ac test signal current 7, is applied to the
>p input at the base of Q . N o t e that a coupling capacitor is not needed in this case because 2
iht: ac current source appears as an open circuit at dc, and, hence, does not disturb the dc bias omditions. T h e loop output at the collector of Q is ac short-circuited to ground via a large capacitor x
(
. Then, sc
T - ^ i sc ~ f if v here I
sc
is the ac short-circuit output current at the collector of Q .
Method 2
x
Using a replica
circuit
shown in Fig. 8.43, a replica of the feedback amplifier circuit can be simply used as a mination impedance. Here, the feedback loops of both the amplifier circuit and the replica cirt are broken using a large inductor L
b l e a k
to avoid disturbing the dc bias conditions. T h e loop
i'input at the collector of Q in the amplifier circuit is then connected to the loop input at the base l
Q in the replica circuit via a large coupling capacitor C 2
to
(again, to avoid disturbing the dc
s conditions). Thus, for ac signals, the loop output at the collector of Q in the amplifier circuit
R
f
x
s an impedance equal to that seen before the feedback loop is broken. Accordingly, we have
I
vVSf
n ;ured that the conditions that existed in the amplifier circuit prior to breaking the loop have not J i mged.
•
—
(b) FIGURE 8 . 4 2 Circuits for simulating (a) the open-circuit voltage transfer function T and (b) the shortcircuit current transfer function T of the feedback amplifier in Fig. 8.41 for the purpose of computing its loop gain. x
sc
CHAPTER 8
FEEDBACK SUMMARY
•
859
o P (-V (returned) /V (test)) Frequency (Hz) FIGURE 8.44
(a) Magnitude and (b) phase of the loop gain Ap of the feedback-amplifier circuit in Fig. 8.41.
SUMMARY S
drcukmefhod
3
^
^
l 0
P
° ^
f
° ^
^
i
n
8
M
8
The advantages above are obtained at the expense of a re duction in gain and at the risk of the amplifier becoming unstable (that is, oscillating). The latter problem is solved by careful design.
•
For each of the four basic types of amplifier, there is an appropriate feedback topology. The four topologies, to gether with their analysis procedure and their effects on input and output impedances, are summarized in Table 8.1 on page 830.
™ » § the replica-
Next, to determine the loop gain A/3, we apply an ac test-signal voltage V, via a large coupling capacitor C to the loop input at the base of 0 in the amplifier circuit. Then, as described in Section 8.7, a
2
V r
Ap = — -
-"< The key feedback parameters are the loop gain (AP), which for negative feedback must be a positive dimensionless number, and the amount of feedback (1 + A/3). The latter directly determines gain reduction, gain desensitivity, bandwidth extension, and changes in Z,- and Z .
•
For the feedback amplifier to be stable, its poles must all be in the left half of the s plane.
•
Stability is guaranteed if at the frequency for which the phase angle of A/3 is 180° (i.e., &> ), \ AP\ is less than uni ty; the amount by which it is less than unity, expressed in decibels, is the gain margin. Alternatively, the amplifier is stable if, at the frequency at which |A/3| = 1, the phase angle is less than 180°; the difference is the phase margin. 180
H
The stability of a feedback amplifier can be analyzed by constructing a Bode plot for \A\ and superimposing on it a plot for 1 / 1 p |. Stability is guaranteed if the two plots inter sect with a difference in slope no greater than 6 dB/octave.
•
To make a given amplifier stable for a given feedback fac tor P, the open-loop frequency response is suitably modi fied by a process known as frequency compensation.
•
A popular method for frequency compensation involves connecting a feedback capacitor across an inverting stage in the amplifier. This causes the pole formed at the input of the amplifier stage to shift to a lower frequency and thus become dominant, while the pole formed at the output of the ampli fier stage is moved to a very high frequency and thus be comes unimportant. This process is known as pole splitting.
:
V, where V is the ac returned signal at the loop output, at the collector of Q in the amplifier circuit. T o compute the loop gain AP of the feedback amplifier circuit in Fig. 8.41 using PSpice, we choose to simulate the circuit in Fig. 8.43. In the PSpice simulations, we used part Q2N3904 (whose SPICE model is given in Table 5.9) for the BJTs, and we set L to be 1 G H and the coupling and bypass capacitors to be 1 kF. The magnitude and phase of AP are plotted in Fig. 8.44, from which w e see that the feedback amplifier has a gain margin of 53.7 dB and a phase margin of 88.7°. r
Negative feedback is employed to make the amplifier gain less sensitive to component variations; to control input and output impedances; to extend bandwidth; to reduce nonlinear distortion; and to enhance signal-to-noise (and signal-to-interference) ratio.
x
0
break
B
Since A and P are in general frequency dependent, the poles of the feedback amplifier are obtained by solving the characteristic equation 1 + A(s)P(s) = 0.
PROBLEMS 860
CHAPTER 8
-2
8 6 1
distortion (see Section 14.3). Consider this follower driven by the output of a differential amplifier of gain 100 whose positive-input terminal is connected to the input signal source v and whose negative-input terminal is connected to the emitters of the follower. Sketch the transfer characteristic v versus v of the resulting feedback amplifier. What are the limits of the dead band and what are the gains outside the dead band?
is employed around a gain stage, its x-dB frequency is increased by the factor (1 + AB).] SECTION 8 . 1 : THE GENERAL FEEDBACK STRUCTURE
SECTION 8 . 2 : SOME PROPERTIES OF NEGATIVE FEEDBACK
8 . 1 A negative-feedback amplifier has a closed-loop gain A = 100 and an open-loop gain A = 10 . What is the feedback factor Bl If a manufacturing error results in a reduction of A to 10 , what closed-loop gain results? What is the percentage change in A corresponding to this factor of 100 reduction inA?
8 „ 9 For the negative-feedback loop of Fig. 8.1, find the loop gain A/3 for which the sensitivity of closed-loop gain to openloop gain [i.e., (dA /A )/(dA/A)] is - 2 0 dB. For what value of A/3 does the sensitivity become 1/2?
5
f
3
f
8 . 2 Repeat Exercise 8.1, parts (b) through (e), for A = 100. 3
8 . 3 Repeat Exercise 8.1, parts (b) through (e), for A = 10 . For part (d) use V = 0.01 V. f
s
8 . 4 The noninverting buffer op-amp configuration shown in Fig. P8.4 provides a direct implementation of the feedback loop of Fig. 8.1. Assuming that the op amp has infinite input resistance and zero output resistance, what is /3? If A = 100, what is the closed-loop voltage gain? What is the amount of feedback (in dB)? For V = 1 V, find V and V If A decreases by 10%, what is the corresponding decrease in Af! s
V
FEEDBACK
0
t
f
f
0 8 . 1 0 It is required to design an amplifier with a gain of 100 that is accurate to within + 1 % . You have available amplifier stages with a gain of 1000 that is accurate to within ±30%. Provide a design that uses a number of these gain stages in cascade, with each stage employing negative feedback of an appropriate amount. Obviously, your design should use the lowest possible number of stages while meeting specification. 4
f
f
u
L
8 . 6 Find the open-loop gain, the loop gain, and the amount of feedback of a voltage amplifier for which A and 1/73 differ by (a) 1%, (b) 5%, (c) 10%, (d) 50%.
D * 8 . 1 3 It is required to design an amplifier to have a nominal closed-loop gain of 10 V/V using a battery-operated amplifier whose gain reduces to half its normal full-battery value over the life of the battery. If only 2% drop in closedloop gain is desired, what nominal open-loop amplifier gain must be used in the design? (Note that since the change in A is large, it is inaccurate to use differentials.) What value of B should be chosen? If component-value variation in the B network may produce as much as a ± 1 % variation in ¡3, to what value must A be raised to ensure the required minimum gain?
8 . 7 In a particular amplifier design, the B network consists of a linear potentiometer for which B is 0.00 at one end, 1.00 at the other end, and 0.50 in the middle. As the potentiometer is adjusted, find the three values of closed-loop gain that result when the amplifier open-loop gain is (a) 1 V/V, (b) 10 V/V, (c) 100 V/V, (d) 10,000 V/V.
8 . 1 4 A capacitively coupled amplifier has a midband gain of 100, a single high-frequency pole at 10 kHz, and a single low-frequency pole at 100 Hz. Negative feedback is employed so that the midband gain is reduced to 10. What are the upper and lower 3-dB frequencies of the closed-loop gain?
8 . 8 A newly constructed feedback amplifier undergoes a performance test with the following results: With the feedback connection removed, a source signal of 2 mV is required to provide a 10-V output to the load; with the feedback connected, a 10-V output requires a 200-mV source signal. For this amplifier, identify values of A, B, AB, the closed-loop gain, and the amount of feedback (in dB).
D * * 8 . 1 5 It is required to design a dc amplifier with a lowfrequency gain of 1000 and a 3-dB frequency of 0.5 MHz. You have available gain stages with a gain of 1000 but with a dominant high-frequency pole at 10 kHz. Provide a design that employs a number of such stages in cascade, each with negative feedback of an appropriate amount. Use identical stages. [Hint: When negative feedback of an amount (1 + AB)
FIGURE P8.4
8 . 5 In a particular circuit represented by the block diagram of Fig. 8.1, a signal of 1 V from the source results in a difference signal of 10 mV being provided to the amplifying element A, and 10 V applied to the load. For this arrangement, identify the values of A and B that apply.
f
s
0
s
D 8 . 2 0 A particular amplifier has a nonlinear transfer characteristic that can be approximated as follows:
D8.17 Design a feedback amplifier that has a closed-loop gain of 100 V/V and is relatively insensitive to change in basic-amplifier gain. In particular, it should provide a reduction in Ay to 99 V/V for a reduction inA to one-tenth its nominal value. What is the required loop gain? What nominal value of A is required? What value of B should be used? What would the closed-loop gain become if A were increased tenfold? If A were made infinite?
3
(a) For small input signals, \v_\ < 10 mV, v /v, = 10 (b) For intermediate input signals, 10 m V < | v_\ < 50 mV, 0
v /VJ
= 10
0
(c) For large input signals, |w | > 50 mV, the output saturates If the amplifier is connected in a negative-feedback loop, find the feedback factor B that reduces the factor-of-10 change in gain (occurring at \v,\ = 10 mV) to only a 10% change. What is the transfer characteristic of the amplifier with feedback? 7
3
8 . 1 1 In a feedback amplifier for which A = 10 and A = 10 , what is the gain-desensitivity factor? Find A exactly, and approximately using Eq. (8.8), in the two cases: (a) A drops by 10% and (b) A drops by 30%. 8 . 1 2 Consider an amplifier having a midband gain A and a low-frequency response characterized by a pole at s = -co and a zero at s = 0. Let die amplifier be connected in a negativefeedback loop with a feedback factor /3. Find an expression for the midband gain and the lower 3-dB frequency of the closed-loop amplifier. By what factor have both changed?
K0
P 8 . 1 6 Design a supply-ripple-reduced power amplifier, for which an output stage having a gain of 0.9 V/V and +1 -V output supply ripple is used. A closed-loop gain of 10 V/V is desired. What is the gain of a low-ripple preamplifier needed to reduce the output ripple to ±100 mV? To ±10 mV? To +1 mV? For each case, specify the value required for the feedback factor B.
D 8 . 1 8 A feedback amplifier is to be designed using a feedback loop connected around a two-stage amplifier. The first stage is a direct-coupled small-signal amplifier with a high upper 3-dB frequency. The second stage is a power-output stage with a midband gain of 10 V/V and upper- and lower 3-dB frequencies of 8 kHz and 80 Hz, respectively. The feedback amplifier should have a midband gain of 100 V/V and an upper 3-dB frequency of 40 kHz. What is the required gain of the small-signal amplifier? What value of B should be used? What does the lower 3-dB frequency of the overall amplifier become?
SECTION 8 . 3 : THE FOUR BASIC FEEDBACK TOPOLOGIES 8 . 2 1 A series-shunt feedback amplifier representable by Fig. 8.4(a) and using an ideal basic voltage amplifier operates with V = 100 mV, V = 95 mV, and V = 10 V. What are the corresponding values of A and Bl Include the correct units for each. s
f
a
8 . 2 2 A shunt-series feedback amplifier representable by Fig. 8.4(b) and using an ideal basic current amplifier operates with I = 100 fiA, I = 95 fiA, and I = 10 mA. What are the corresponding values of A and Bl Include the correct units for each:
» 8 . 1 9 The complementary BIT follower shown in Fig. P8.19(a) has the approximate transfer characteristic shown in Fig. P8.19(b). Observe that for - 0 . 7 V < v, < +0.7 V, the output is zero. This "dead band" leads to crossover
s
f
0
+V
<
<
V
0
h
vo 0
T -V (a) FIGURE P 8 . 1 9
(b)
+0.7
vi
CHAPTER 8
8 6 2
FEEDBACK
PROBLEMS
* 8 . 2 3 Consider the shunt-series feedback amplifier of Fig. 8.5: (a) For R , r , and r assumed very large, use direct circuit analysis (as opposed to feedback analysis) to show that the overall current gain is given by s
ol
approximately as the current divider ratio of the (R network. Find 0 and show that the approximate expressi for A found above is simply 1/0.
SECTION 8 . 4 : 0 n
f
o2
A
[o
s
=
Ri + g R {R ml
Ll
s
+ R)
l
2
and the input resistance is R
in
= R +R 1
+
2
AR f
1
f
L1
in
f
AMPLIFIER g 27 A series-shunt feedback amplifier employs a basic mDlifier with input and output resistances each of 1 kD and „;n 4 = 2000 V/V. The feedback factor 0=0.1 V/V. Find the gain Ap the input resistance R , and the output resistance R of the closed-loop amplifier.
L1
m2
x
2
* 8 . 2 6 For each of the op-amp circuits shown in Fig. P8.26 identify the feedback topology and indicate the output vari able being sampled and the feedback signal. In each case assuming the op amp to be ideal, find an expression for 0, and hence find A . f
(c) For the case R = 1 kD and R = 1 kD, sketch and label an equivalent circuit following the model in Fig. 8.10(c). s
L
Ri W v
®
if
f
3 28 For a particular amplifier connected in a feedback loop in which the output voltage is sampled, measurement of the output resistance before and after the loop is connected shows a change by a factor of 80. Is the resistance with feed back higher or lower? What is the value of the loop gain A/3? IfRcfis 100 D, what is R without feedback? 0
m2
f
ml
f
8 . 2 5 A shunt-shunt feedback circuit representable by Fig. 8.4(d) and using an ideal transresistance amplifier oper ates with I = 100 fiA, I = 95 fiA, and V„ = 10 V. What are the corresponding values of A and 07 Include the correct units for each. s
Hence, find approximate expressions for A and R for the case in which g R >1 and (l/g ) « A\. (b) Evaluate A and R^, exactly and approximately, for the case in which g R = 1 0 0 , R = 1 0 k D , R = 90 kD, and g = 5 mA/V. (c) Since the negative feedback forces the input terminal of the amplifier toward ground, the value of 0 can be determined ml
8 . 2 4 A series-series feedback circuit representable h Fig. 8.4(c) and using an ideal transconductance amplifi/ operates with V = 100 mV, V = 95 mV, and /„ = io ^ What are the corresponding values of A and 07 Include the correct units for each.
THE SERIES-SHUNT FEEDBACK
8 6 3
»*g,29 A series-shunt feedback circuit employs a basic voltage amplifier that has a dc gain of 10 W V and an STC frequency response with a unity-gain frequency of 1 MHz. The input resistance of the basic amplifier is 10 kD, and its output resistance is 1 kD. If the feedback factor 0 = 0.1 WV, find the input impedance Z and the output impedance Z of the feedback amplifier. Give equivalent circuit representa tions of these impedances. Also find the value of each imped ance at 10 Hz and at 10 Hz. 4
if
3
of
5
FIGURE P 8 . 3 0
8 . 3 1 A feedback amplifier utilizing voltage sampling and employing a basic voltage amplifier with a gain of 100 V/V and an output resistance of 1000 D has a closed-loop output resistance of 100 D. What is the closed-loop gain? If the basic amplifier is used to implement a unity-gain voltage buffer, what output resistance do you expect? * 8 . 3 2 In the series-shunt amplifier shown in Fig. P8.32, the transistors operate at V = 0.7 V with h of 100 and an Early voltage that is very large. BE
FE
(a) Derive expressions for A, 0, R and R . (b) F o r 7 = 0.1 mA, I = 1 mA, R = 1 kD, R = 10 kD, R = 100 D, and R = 1 kD, find the dc bias voltages at the input and at the output, and find A = v /v , R^, and R . b
gl
B2
0
x
2
s
L
8 . 3 0 A series-shunt feedback amplifier utilizes the feed back circuit shown in Fig. P8.30. (a) Find expressions for the h parameters of the feedback circuit (see Fig. 8.10b). (b) If R = 1 kD and 0 = 0.01, what are the values of all four h parameters? Give the units of each parameter. t
(c) FIGURE P 8 . 2 6
(d) FIGURE
P8.32
f
0
s
mt
D * 8 . 3 3 Figure P8.33 shows a series-shunt amplifier with a feedback factor 0=1. The amplifier is designed so that v = 0 for v = 0, with small deviations in v from 0 V dc being mini mized by the negative-feedback action. The technology utilized has k' = 2k' = 120 pA/V ,\V \ = 0.7 V, and\V' \ = 24V/pon. o
s
0
2
n
t
A
CHAPTER 8
864
PROBLEMS
FEEDBACK
(d) Find the gain-with-feedback, A , and the output resis-
(a) With the feedback loop opened and the gate terminals of Q and Q grounded find the dc current and the overdrive voltage at which each of Q to Q is operating. Ignore the mismatch in I between g i and Q arising from their different drain voltages. Also find the dc voltage at the output. (b) Find g and r of each of the five transistors. (c) Find the values of A and R . Assume that the bias current sources are ideal. x
f
tance
2
x
2
m
a
* * 8 . 3 4 For the circuit in Fig. P8.34, \V,\ = 1 V, k'W/L = 1 mA/V , h = 100, and the Early voltage magnitude for all
A
devices (including those that implement the current sources) is 100 V. The signal source V has a zero dc component. Find the dc voltage at the output and at the base of Q . Find the values of A, B, A , R , and R . s
OUT
(e) How would you modify the circuit to realize a closedloop voltage gain of 5 V/V? What is the value of output resistance obtained?
s
D
R .
2
fe
3
f
IN
MT
0 * 8 . 3 5 Figure P8.35 shows a series-shunt, feedback amplifier without details of the bias circuit. (a) Sketch the A circuit and the circuit for determining B. (b) Show that if AB is large then the closed-loop voltage gain is given approximately by
+2.5 V
R
=Yo
A
f
„. F
R
s
(c) If RE is selected equal to 50 Q, find R that will result in a closed-loop gain of approximately 25 V/V. (d) If Qi is biased at 1 mA, Q at 2 mA, and Q at 5 mA, and assuming that the transistors have h = 100, find approximate values for R and R to obtain gains from the stages of the A circuit as follows: a voltage gain of Q of about - 1 0 and a voltage gain of Q of about - 5 0 . (e) For your design, what is the closed-loop voltage gain realized? (f) Calculate the input and output resistances of the closedloop amplifier designed.
(120/1)
2
(20/1)
0 .2i (20/1)
"<3
3
fe
CL
300 fiA
C2
x
2
02 (20/1)
8 . 3 7 A series-series feedback amplifier employs a transconductance amplifier having G = 100 mA/V, input resistance of 10 k£2, and output resistance of 100 Ml. The feedback network has B = 0.1 V/mA, an input resistance (with port 1 open-circuited) of 100 D, and an input resistance (with port 2 open-circuited) of 10 kQ. The amplifier operates with a signal source having a resistance of 10 kQ and with a load resistance of 10 kO. Find A , R , and R . m
f
1 mA
©
IN
M
D * 8 . 3 8 Figure P8.38 shows a circuit for a voltage-controlled current source employing series-series feedback through the resistor R . (The bias circuit for the transistor is not shown.) Show that if the loop gain AB is large, l± = _ L Vs RE Then find the value of R to obtain a circuit transconductance of 1 mA/V. If the voltage amplifier has a differential input resistance of 100 Ml, a voltage gain of 100, and an output resistance of 1 Ml, and if the transistor is biased at a current of 1 mA, and has h of 100 and r of 100 Ml, find the actual value of transconductance (I /V ) realized. Use R = 10 Ml. Also find the input resistance R _ and the output resistance R . For calculating R , recall that the output resistance of a BIT with an emitter resistance that is much larger than r is approximately h r . E
fe
a
0
s
S
H
OUT
OUT
K
fe
200 yuA
865
E
F
03 (40/1)
'
E
+ RE
V
: _
0
cc
<
-2.5 V FIGURE P 8 . 3 3
V, o -
© R
S
- o V„
0.5 mA
© ~ C
= 100 kfi
\AA
©
o
1
Qi
RF
A
0
900 k f i > ß
I
2
T — V A
100 k i i £ 1 mA
.__
5 mA
"
©
'
—°
yo
* 8 . 3 9 Figure P8.39 shows a circuit for a voltage-to-current converter employing series-series feedback via resistor R . The MOSFETs have the dimensions shown and \x C = 20 iiA/V , \V \ = 1 V, and \ V \ = 100 V. What is the value of I /V obtained for large loop gain? Use feedback analysis to find a more exact value for I /V . Also, if the output voltage is taken at the source of Q , what closed-loop voltage gain is realized? F
FIGURE P 8 . 3 5
M
RL
ox
2
2 kíl
t
SECTION 8 . 5 : THE SERIES-SERIES FEEDBACK AMPLIFIER 8 . 3 6 For the circuit in Fig. 8.17(a), find an approximate value for I /V assuming that the loop gain is large. Use it to determine the voltage gainV /V . Compare your results with the values found in Example 8.2. 0
a
A
s
0
s
5
s
0
FIGURE P 8 . 3 4
FIGURE P 8 . 3 8
3
s
8 . 4 ® For the series-series feedback amplifier in Fig. P8.40, the op amp is characterized by an open-loop voltage gain ¡1,
CHAPTER 8
8 6 6
PROBLEMS
FEEDBACK
10 kO and an input resistance (with port 2 short-circuited) of 10 kO and provides a feedback factor ¡5 = 0.1 mA/V. The amplifier is fed with a current source having R = 10 kO, and a load resistance R = 1 k O is connected at the output. Find the transresistance A of the feedback amplifier, its input resistance R , and its output resistance R . s
L
f
ia
out
8 . 4 4 For the shunt-series feedback amplifier of Fig. P8.44, derive expressions for A, B, A , R , and R (the latter between the terminals labeled XX). Neglect r and the body effect. Evaluate all parameters for g =g = 5 mA/V, R = 10 kO, R = 10 kO, and R = 90 kO. Noting that R can be considered as a source-degeneration resistance for Q , find R for the case r = 20 kO and neglecting the body effect. (Hint: A source-degeneration resistance R increases R by approximately g R.) f
m
of
' .
867
(b) Using three cascaded stages of the type shown in Fig. P8.46(b) to implement the amplifier jj., design a feedback amplifier with a voltage gain of approximately - 1 0 0 V/V. The amplifier is to operate between a source resistance R = 10 k O and a load resistance R = 1 kO. Calculate the actual value of V /V realized, the input resistance (excluding R ), and the output resistance (excluding R ). Assume that the BJTs have h of 100. (Note: In practice, the three amplifier stages are not made identical, for stability reasons.) s
L
0
s
s
L
fe
0
R = 10 k i l s
W v
ml
c>
s
m2
D
F
of
2
0.8 mA
out
o2
om
m
FIGURE P8.39
(a)
an input differential resistance R = 10 k O , and an output resistance r„ = 100 ¿ 1 The amplifier supplies a cuiTent z' to a load resistance = 1 kO. The feedback network is composed of resistors r = 100 Q, R = 10 kQ, and R It is required to find the gain-with-feedback A = i /v , the input resistance R- , and the output resistance R for the following cases: id
0
2
v
f
0
s
m
mt
+15 V
Calculate this gain for the component values given on the circuit diagram, and compare the result with that found in Example 8.3. Find a new value for R to obtain a voltage gain of approximately - 7 . 5 V/V.
4
A
f
8 . 4 2 The shunt-shunt feedback amplifier in Fig. P8.42 has / = 1 mA and V = 0.8 V. The MOSFET has V, = 0.6 V and V = 30 V. For R = 10 kO, R = 1 M O , and R = 4.7 M O , find the voltage gain v /v , the input resistance R and the output resistance ^ . cs
5
(a) t z = 1 0 V/V and ^ = 100 0 (b) t x = 1 0 V/V and # ! = »<=
A
4
s
t
0
s
2
im
o u t
FIGURE P 8 . 4 4
8.45 Reconsider the circuit in Fig. P8.44. Now let the drain of Q be connected to V and let the output be taken as the voltage at the source of Q . Now R should be considered as part of the A circuit, since the voltage V develops across it. Convince yourself that now the amplifier can be viewed as a shunt-shunt topology with the feedback network composed of R . Find expressions for A, j3, A , R , and R , where R is the resistance looking back into the output terminal. Neglect r„ and the body effect. Find the values of all parameters for the case in which g = g = 5 mA/V, R = 10 kO, R = 10 kfl, andfl =90kQ. 2
DD
2
0
F
FIGURE P 8 . 4 0
f
ml
SECTION 8 . 6 : THE S H U N T - S H U N T AND THE S H U N T - S E R I E S FEEDBACK AMPLIFIERS D * 8 . 4 1 For the amplifier topology shown in Fig. 8.21(a), show that for large loop gain, R
f
V,
FIGURE P8.42
8 . 4 3 A transresistance amplifier having an open-circuit "gain" of 100 V/mA, an input resistance of 1 kO, and an output resistance of 1 k O is connected in a negative-feedback loop employing a shunt-shunt topology. The feedback network has an input resistance (with port 1 short-circuited) of
(b)
s
in
m2
ml
D
ml
s
F
D * * 8 . 4 6 (a) Show that for the circuit in Fig. P8.46(a) if the loop gain is large, the voltage gain V„/V is given approximately by s
FIGURE P 8 . 4 6
D 8 . 4 7 Negative feedback is to be used to modify the characteristics of a particular amplifier for various purposes. Identify the feedback topology to be used if: (a) Input resistance is to be lowered and output resistance raised. (b) Both input and output resistances are to be raised. (c) Both input and output resistances are to be lowered. * 8 . 4 8 For the circuit of Fig. P8.48, use the feedback method to find the voltage gain V /V , the input resistance R , and the output resistance R . The op amp has open-loop gain fi = 10 V/V, R = 100 kO, and r = 1 k O . 0
in
s
oat
4
v
s
R
id
s
0
!
8 6 8
1
CHAPTER 8
FEEDBACK
PROBLEMS
signal source V has zero dc component. Determine the output resistance R t] s
ou
-o V„ >R, = 2 k f i
100 k f i
2
x
2
R
1 kfi
°
x
u t
3
h
? 2 C2J fe3
+
m
R
C2
4
r
8 . 6 3 An op amp having a low-frequency gain of 10 and a single-pole rolloff at 1 0 rad/s is connected in a negativefeedback loop via a feedback network having a transmission k and a two-pole rolloff at 10 rad/s. Find the value of k above which the closed-loop amplifier becomes unstable. 3
4
4
s
R
AB =
+ (h +l)
l
)
[r +R +
m
e3
8 . 6 4 Consider a feedback amplifier for which the openloop gain A(s) is given by
(R llr )}
F
E
eX
1000
A(s)
a,R
4
-(*cA*2
* 8 . 4 9 Consider the amphfier of Fig. 8.25(a) to have its output at the emitter of the rightmost transistor Q . Use the technique for a shunt-shunt feedback amplifier to calculate ( V / 7 ) and R . Using this result, calculate I /I- . Compare this with the results obtained in Example 8.4. 2
out
in
in
wx
m
8 . 5 0 A current amplifier with a short-circuit current gain of 100 A/A, an input resistance of 1 k Q , and an output resistance of 10 kfi is connected in a negative-feedback loop employing the shunt-series topology. The feedback network provides a feedback factor ¡5 = 0.1 A/A. Lacking complete data about the situation, estimate the current gain, input resistance, and output resistance of the feedback amplifier.
8 . 5 2 The feedback amplifier of Fig. P8.52 consists of a common-gate amplifier formed by Q and R , and a feedback circuit formed by the capacitive divider (C_, C ) and the common-source transistor Q . Note that the bias circuit for Qf is not shown. It is required to derive expressions for A = V /I , R , and R . Assume that C and C are sufficiently small that their loading effect on the basic amplifier can be neglected. Also neglect r and the body effect. Find the values of A , R , and R for the case in which g = 5 mA/V, R =10 kfi, Q = 0.9 pF, C = 0.1 pF, and g = 1 mA/V. x
D
2
f
0
s
m
out
x
in
mt
D
mX
2
mf
o4
F
o5
{R llr )+\/g F
o5
m5
where g
mX2
m
x
2
8.56 Derive an expression for the loop gain of each of the four feedback circuits shown in Fig. P8.26. Assume that the op amp is modeled by an input resistance R , an open-circuit voltage gain fi, and an output resistance r . * 8 . 5 7 Find the loop gain of the feedback amplifier shown in Fig. P8.33 by breaking the loop at the gate of Q (and, of course, setting v = 0). Use the values given in the statement of Problem 8.33. Determine the value of R . 2
M
8.58 For the feedback amplifier in Fig. P8.42, derive an expression for the loop gain by breaking the loop at the gate terminal of the MOSFET (and, of course, setting v = 0). Find the value of the loop gain for the component values given in Problem 8.42. s
r°
Qi
1
= 500 O
8.59 For the feedback amplifier in Fig. P8.44, set I = 0 and derive an expression for the loop gain by breaking the loop at the gate terminal of transistor Q . s
fiA
.©
= 10 kfi
R
F
=
10 kfi
Qf
s
5 140 fi FIGURE P8.51
8 . 5 3 Determine the loop gain of the amplifier in Fig. P8.34 by breaking the loop at the gate of Q and finding the returned voltage across the 100-kfi resistor (while setting V to zero). The devices have \V,\ = 1 V, k' W/L = 1 mA/V , and h = 100. The Early voltage magnitude for all devices (including those that implement the current sources) is 100 V. The 2
RE
8.61 An op amp designed to have a low-frequency gain of 10 and a high-frequency response dominated by a single pole at 100 rad/s, acquires, through a manufacturing error, a pair of additional poles at 10,000 rad/s. At what frequency does the total phase shift reach 180°? At this frequency, for what value of ¡5, assumed to be frequency independent, does the loop gain reach a value of unity? What is the corresponding value of closed-loop gain at low frequencies?
8 . 6 8 Reconsider Example 8.5 with the circuit in Fig. 8.34 modified to incorporate a so-called tapered network, in which the components immediately adjacent to the amplifier input are raised in impedance to C/10 and 10 R. Find expressions for the resulting pole frequency a> and Q factor. For what value of K do the poles coincide? For what value of K does the response become maximally flat? For what value of K does the circuit oscillate?
s
0
2
n
fe
(a) For what value of P do the closed-loop poles become coincident? At what frequency? (b) What is the low-frequency gain corresponding to the situation in (a)? What is the value of the closed-loop gain at the frequency of the coincident poles? (c) What is the value of Q corresponding to the situation in (a)? (d) If P is increased by a factor of 10, what are the new pole locations? What is the corresponding pole QI
SECTION 8 . 8 : THE STABILITY PROBLEM
8.60 For the feedback amplifier in Fig. P8.52, set I — 0 and derive an expression for the loop gain by breaking the loop at the gate terminal of transistor Qf.
:c
SECTION 8 . 7 : DETERMINING THE LOOP GAIN
4
s
D 8 . 6 7 A dc amplifier has an open-loop gain of 1000 and two poles, a dominant one at 1 kHz and a high-frequency one whose location can be controlled. It is required to connect this amplifier in a negative-feedback loop that provides a dc closed-loop gain of 100 and a maximally flat response. Find the required value of P and the frequency at which the second pole should be placed.
x
FIGURE P8.52 R,
4
s
i n
R,
* 8 . 6 6 An amplifier having a low-frequency gain of lO" and poles at 1 0 Hz and 1 0 Hz is operated in a closed negativefeedback loop with a frequency-independent p. 5
DD
k
-oV„
200
8 . 6 5 A dc amplifier having a single-pole response with pole frequency 1 0 Hz and unity-gain frequency of 10 MHz is operated in a loop whose frequency-independent feedback factor is 0.1. Find the low-frequency gain, the 3-dB frequency, and the unity-gain frequency of the closed-loop amplifier. By what factor does the pole shift? 4
is the g of each of Q and 0 .
id
2
s
o2
If the feedback factor P is independent of frequency, find the frequency at which the phase shift is 180°, and find the critical value of P at which oscillation will commence.
0
s
0
m
2
0
f
g ia(r //r )
+s/10 )
SECTION 8 . 9 : EFFECT OF FEEDBACK ON THE AMPLIFIER POLES
R llr
f
* 8 . 5 1 For the amplifier circuit in Fig. P8.51, assuming that V has a zero dc component, find the dc voltages at all nodes and the dc emitter currents of Q and Q . Let the BJTs have P = 100. Use feedback analysis to find V /V and ^ . x
8 . 5 5 Show that the loop gain of the amphfier circuit in Fig. P8.39 is AB =
5 2
(1 + i / 1 0 ) ( l
F
FIGURE P8.48
3 6 9
* * 8 . 6 2 For the situation described in Problem 8.61, sketch Nyquist plots for B = 1.0 and 10" . (Plot for co = 0 rad/s, 100 rad/s, 10 rad/s, 10 rad/s, and «, ad/s.) 3
g 5 4 It is required to determine the loop gain of the amplifier circuit shown in Fig. P8.35. The most convenient place to break the loop is at the base of Q . Thus, connect a resistance equal to between the collector of Q and ground, apply a test voltage V, to the base of Q , and deterrnine the returned voltage at the collector of Q (with V set to zero, of course). Show that
i
0
870
CHAPTER 8
FEEDBACK
8.69 Three identical logic inverters, each of which can be characterized in its switching region as a linear amplifier having a gain -K and a pole at 10 Hz, are connected in a ring. Regarding this as a negative-feedback loop with ¡5 = 1, find the minimum value of K for which the inverter ring must oscillate. What would the frequency of oscillation be for very small signal operation? [Note that in practice such a ring oscillator operates with relatively larger signal (logic levels) at a somewhat lower frequency.] 7
frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop gains as low as unity. By what factor is the capacitance at the controlling node increased? 8.78 Contemplate the effects of pole splitting by considering Eqs. (8.87) and (8.88) under the conditions thati? = U = .R, C = d / 1 0 = C,C > C, and g = 100/«, by calculating co , co , and a> , co . t
2
f
P2
P1
Pl
P2
08.79
SECTION 8 . 1 0 :
STABILITY STUDY USING
4
An op amp with open-loop voltage gain of 10 Hz and poles at 10 Hz, 10 Hz, and 10 Hz is to be compensated by the addition of a fourth dominant pole to operate stably with unity feedback (/3 = 1). What is the frequency of the required dominant pole? The compensation network is to consist of an RC low-pass network placed in the negativefeedback path of the op amp. The dc bias conditions are such that a 1-Mfl resistor can be tolerated in series with each of the negative and positive input terminals. What capacitor is required between the negative input and ground to implement the required fourth pole? 5
BODE PLOTS 8 . 7 0 Reconsider Exercise 8.14 for the case of the op amp wired as a unity-gain buffer. At what frequency is |A/3| = 1? What is the corresponding phase margin? 8 . 7 1 Reconsider Exercise 8.14 for the case of a manufacturing error introducing a second pole at 10 Hz. What is now the frequency for which |AjS| = 1? What is the corresponding phase margin? For what values of ¡5 is the phase margin 45° or more? 4
8.72 For what phase margin does the gain peaking have a value of 5%? Of 10%? Of 0.1 dB? Of 1 dB? (Hint: Use the result in Eq. 8.76.)
6
8 . 7 3 An amplifier has a dc gain of 10 and poles at 10 Hz, 3.16 x 10 Hz, and 10 Hz. Find the value of /3, and the corresponding closed-loop gain, for which a phase margin of 45° is obtained. s
5
6
8 . 7 4 A two-pole amplifier for which A = 10 and having poles at 1 MHz and 10 MHz is to be connected as a differentiator. On the basis of the rate-of-closure rule, what is the smallest differentiator time constant for which operation is stable? What are the corresponding gain and phase margins? 3
0
» 8 . 7 5 For the amplifier described by Fig. 8.37 and with frequency-independent feedback, what is the minimum closed-loop voltage gain that can be obtained for phase margins of 90° and 45°?
A multipole amplifier having a first pole at 2 MHz and a dc open-loop gain of 80 dB is to be compensated for closed-loop gains as low as unity by the introduction of a new dominant pole. At what frequency must the new pole be placed? D 8 . 7 7 For the amplifier described in Problem 8.76, rather than introducing a new dominant pole we can use additional capacitance at the circuit node at which the pole is formed to reduce the frequency of the first pole. If the frequency of the second pole is 10 MHz and if it remains unchanged while additional capacitance is introduced as mentioned, find the
Operational-Amplifier and Data-Converter Circuits
9.2
The Folded-Cascode CMOS Op Amp 883
9.3
The 741 Op-Amp Circuit
**8.81
9.4
DC Analysis of the 741
9.5
Small-Signal Analysis of the 741 905
5
6
Introduction
6
m
P1
9.1
P 2
The op amp in the circuit of Fig. P8.81 has an open-" loop gain of 10 and a single-pole rolloff with o = 10 rad/s. 5
3 d B
(a) Sketch a Bode plot for the loop gain. (b) Find the frequency at which \A3\ = 1, and find the corresponding phase margin. (c) Find the closed-loop transfer function, including its zero and poles. Sketch a pole-zero plot. Sketch the magnitude of the transfer function versus frequency, and label the important parameters on your sketch.
9.6
871
The Two-Stage CMOS Op Amp 872
893 899
9.7
Data Converters—An Introduction 922
9.8
D/A Converter Circuits 925
9.9
A/D Converter Circuits
929
9.10 SPICE Simulation Example 934 Summary
940
Problems
941
Gain, Frequency Response, and Slew Rate of the 741 917
INTRODUCTION
SECTION 8 . 1 1 : FREQUENCY COMPENSATION
D8.76
7
D * 8 . 8 0 An op amp with an open-loop voltage gain of 80 dB and poles at 10 Hz, 10 Hz, and 2 x 10 Hz is to be compensated to be stable for unity ¡5. Assume that the op amp incorporates an amplifier equivalent to that in Fig. 8.40, with Q = 150 pF, C = 5 pF, and g = 40 mA/V, and t h a t / is caused by the input circuit a n d / by the output circuit of this amplifier. Find the required value of the compensating Miller capacitance and the new frequency of the output pole. 2
5
2
m
R, = 100 kfl
FIGURE P8.81
Analog ICs i n c l u d e operational amplifiers, a n a l o g multipliers, analog-to-digital (A/D) and drgital-to-analog ( D / A ) converters, p h a s e - l o c k e d loops, and a variety of other, m o r e specialized functional b l o c k s . All these analog s u b s y s t e m s are constructed internally using t h e basic building b l o c k s w e h a v e studied in earlier chapters, including single-stage amplifiers, differential pairs, current mirrors, and M O S switches. In this chapter, w e shall study the internal circuitry of the most important analog ICs, namely, operational amplifiers and data converters. T h e terminal characteristics and circuit applications of o p amps h a v e already been covered in Chapter 2. Here, our objective is to expose the reader to some of the ingenious techniques that have evolved over the years for combining elementary analog circuit building blocks to realize a complete op amp. W e shall study both CMOS and bipolar o p amps. T h e C M O S o p - a m p circuits considered find application in the
8 7 1
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS
9.1
design of analog and mixed-signal V L S I circuits. Because these o p amps are usually designed with a specific application in mind, they can b e optimized to meet a subset of the list of desired specifications, such as high dc gain, wide bandwidth, or large output-signal swing. In contrast the bipolar op-amp circuit w e shall study is of the general-purpose variety a n d therefore is designed to fit a wide range of specifications. A s a result, its circuit represents a compromise between m a n y performance parameters. This 741-type of o p a m p has been in existence for over 35 years. Nevertheless its internal circuit remains as relevant and interesting today as it ever was
T H ET W O - S T A G E C M O S O P A M P
as well as performing conversion from differential t o single-ended form w h i l e p r o v i d i n g a reasonable c o m m o n - m o d e rejection ratio ( C M R R ) . T h e differential pair is b i a s e d b y current source Q , w h i c h is o n e of the t w o output tran sistors of the current mirror formed b y Q , Q , a n d Q . T h e current mirror is fed b y a reference current which can b e generated b y simply connecting a precision resistor (external to t h e chip) to the negative supply voltage -V or to a m o r e precise negative voltage reference if one is available in t h e same integrated circuit. Alternatively, for applications with m o r e strin gent requirements, can b e generated using a circuit such as that studied in Section 7.7.1. T h e s e c o n d gain stage consists of t h e c o m m o n - s o u r c e transistor Q a n d its currentsource load Q . T h e s e c o n d stage typically p r o v i d e s a gain of 5 0 V / V to 8 0 V / V . In addition, it takes part i n t h e p r o c e s s of frequency c o m p e n s a t i n g t h e o p a m p . F r o m Section 8.11 t h e reader will recall that t o g u a r a n t e e that t h e o p a m p will operate in a stable fashion (as opposed to oscillating) w h e n n e g a t i v e feedback of various a m o u n t s is applied, t h e o p e n - l o o p gain is m a d e t o roll off w i t h frequency at t h e u n i f o r m rate of - 2 0 d B / d e c a d e . This in turn is achieved b y introducing a p o l e at a relatively l o w frequency a n d arranging for it t o d o m i n a t e the frequency-response determination. I n t h e circuit w e are studying, this i s i m p l e m e n t e d using a compensation capacitance C connected in t h e negative-feedback path of the secondstage amplifying transistor Q . A s will b e seen, C (together with t h e m u c h smaller capaci tance C across it) is Miller-multiplied b y t h e gain of t h e s e c o n d stage, a n d t h e resulting capacitance at t h e input of t h e second stage interacts with the total resistance there to p r o vide the required d o m i n a n t p o l e ( m o r e o n this later). Unless properly designed, the C M O S o p - a m p circuit of Fig. 9.1 can exhibit a s y s t e m a t i c o u t p u t d c offset voltage. This point w a s discussed in Section 7.7.1, w h e r e it w a s found that the dc offset can b e eliminated b y sizing the transistors so as to satisfy thé following constraint: 5
&
5
7
SS
T h e material o n data-converter circuits presented in this c h a p t e r should serve as a bridge b e t w e e n a n a l o g circuits, o n w h i c h w e h a v e b e e n concentrating in Chapters 6 t o 8, a n d digital circuits w h o s e study is u n d e r t a k e n in C h a p t e r s 10 a n d 11.
6
7
In addition to e x p o s i n g t h e r e a d e r t o s o m e of t h e ideas that m a k e analog I C design such an exciting topic, this chapter should serve t o tie together m a n y of t h e concepts a n d methods studied thus far.
9.1
THE TWO-STAGE CMOS OP AMP
c
T h e first o p - a m p circuit w e shall study is t h e t w o - s t a g e C M O S topology s h o w n in F i g . 9 . 1 . This s i m p l e b u t elegant circuit h a s b e c o m e a classic a n d is u s e d i n a variety of forms in the design of V L S I s y s t e m s . W e h a v e already studied this circuit in Section 7.7.1 as a n example of a m u l t i s t a g e C M O S amplifier. W e u r g e t h e r e a d e r to r e v i e w Section 7.7.1 before proceed ing further. H e r e , o u r discussion will e m p h a s i z e t h e performance characteristics of t h e circuit a n d t h e trade-offs i n v o l v e d in its design.
6
c
gd6
9.1.1 The Circuit
(W/L)
6
T h e circuit consists of t w o gain stages: T h e first stage is formed b y t h e differential pair Qi-Q together with its current mirror l o a d Q -Q . This differential-amplifier circuit, studied in detail in Section 7.5, provides a voltage gain that is typically in the r a n g e of 2 0 V / V to 6 0 V/V, 3
_
(W/L)
7
(W/L)
2
(W/L)
4
5
4
9.1.2 Input Common-Mode Range and Output Swing Refer to F i g . 9.1 a n d consider w h a t h a p p e n s w h e n t h e t w o input terminals are tied together and connected t o a v o l t a g e V . T h e lowest v a l u e of V h a s to b e sufficiently large t o k e e p Qi a n d Q in saturation. T h u s , t h e lowest value of V should n o t b e l o w e r than t h e v o l t a g e at the drain of Q (-V + V = -V + V,„ + V ) b y m o r e than | V \, thus ICM
/ C M
2
3'
ICM
x
H
fi
ss
GS3
5
SS
OV3
V,cM^-V
+ V
ss
M
ICM
•0
pi
O V 3
~\V
T P
\
(9.2)
5
SD5
0V5
5
Qi
DD
+ \\—o
0V5
ICM
—
VICM — VDD ~ I V~OV5 I
^SGl
or equivalently VICM ^ V
Q:
+ V
T h e highest v a l u e o f V should ensure that Q r e m a i n s in saturation; that is, t h e v o l t a g e across Q , V , should n o t decrease b e l o w | V |. Equivalently, t h e voltage at the drain of 2 should n o t g o h i g h e r than V - | V \. T h u s t h e u p p e r limit of V is 5
0—1
T
24
D
- \
V
0 V 5
\ - \ V
T
P
V I
\ - \
(9.3)
0V!
T h e expressions in E q s . (9.2) a n d (9.3) can b e c o m b i n e d t o express t h e input c p m m o n - m o d e range as - Vss + V
0V3
FIGURE 9.1 The basic two-stage CMOS op-amp configuration.
D
+V -\ tn
V I
[CM
DD
-\V \tp
IV
ovl
I- I V
ovs
(
(9.4)
A s expected, t h e overdrive voltages, w h i c h are i m p o r t a n t design p a r a m e t e r s , subtract from the dc supply voltages, thereby r e d u c i n g t h e input c o m m o n - m o d e r a n g e . It follows that from VICM r a n g e point-of-view it is desirable t o select t h e values of V as l o w as possible. A
O
V
CHAPTER 9
9.1
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS
T h e extent of the signal swing allowed at the output of the o p a m p is limited at the lower end b y the need to k e e p Q saturated and at the upper end b y the need to k e e p Q saturated, thus 6
Since Qx and Qi are operated at e q u a l bias currents {1/2) V i =
7
0V
-
+ V v6 0
-
v
o - VDD - I V
0 V 1
2(7/2)
G
J _
=
select v a l u e s for j V
ov
\ of Q and Q as l o w as p o s s i b l e . T h i s r e q u i r e m e n t , h o w e v e r , is coun 6
(9.7)
v
^ovi H e r e again w e o b s e r v e that to a c h i e v e a w i d e r a n g e for t h e output v o l t a g e s w i n g w e need to
and equal o v e r d r i v e v o l t a g e s ,
Von,
(9.5)
1
THE TWO-STAGE CMOS OP
ovi
Resistance R_ r e p r e s e n t s the output resistance of the first stage, thus
7
teracted b y t h e n e e d to h a v e a h i g h transition frequency f
Ri=r \\r
for Q . F r o m T a b l e 6.3 and the
T
o2
(9.8)
oA
6
c o r r e s p o n d i n g discussion in Section 6.2.3, w e k n o w t h a t / is p r o p o r t i o n a l to V ; . t h u s the r
ov
high-frequency p e r f o r m a n c e of a M O S F E T i m p r o v e s with the increase of the overdrive
where
\YàÀ
r , =
v o l t a g e at w h i c h it is operated.
0 2
to b e c o n n e c t e d b a c k to its n e g a t i v e i n p u t t e r m i n a l so that a u n i t y - g a i n amplifier is obtained.
and
F o r such a c o n n e c t i o n to b e possible, there m u s t b e a substantial o v e r l a p b e t w e e n the allow
-Yâ± 7/2
r
able range of v and the allowable range of V . 0
KM
(9.9)
1/2
A n i m p o r t a n t r e q u i r e m e n t of an o p - a m p circuit is that it b e possible for its output terminal
This is usually the case in the C M O S amplifier
o
'
4
(9.10)
_
circuit u n d e r study. The dc gain of the first stage is thus A i = - G
m
l
R
(9-lD
l
? (r Wr ) ml
For a particular design of the two-stage C M O S op amp of Fig. 9.1. ±1.65-V supplies are utilized and all transistors except for Q and Q are operated with overdrive voltages of 0.3-V magnitude; Q and Q u s e overdrive voltages of 0.5-V magnitude. The fabrication process employed provides V = \ V j = 0.5 V. Find the input c o m m o n - m o d e range and the range allowed for v . b
7
6
m
o2
1 2
(9- )
o4
1 +
\V \
ovi
(9.13)
1 :
7
V
A2
A4
tp
Observe that the m a g n i t u d e of Ai is i n c r e a s e d by operating t h e differential-pair transistors,
0
Q and Q , at a l o w o v e r d r i v e voltage, and b y c h o o s i n g a l o n g e r c h a n n e l l e n g t h to obtain 2
Ans.-1,35 V to 0.55 V ; - 1 . 1 5 V t o + 1 . 1 5 V
larger Early v o l t a g e s , |V \. B o t h actions, however, d e g r a d e the frequency r e s p o n s e of the A
amplifier (see Table 6.3 and t h e c o r r e s p o n d i n g discussion in Section 6.2.3). R e t u r n i n g to t h e e q u i v a l e n t circuit in F i g . 9.2 and leaving the d i s c u s s i o n of t h e v a r i o u s
9.1.3 Voltage Gain
model c a p a c i t a n c e s until the n e x t section, w e n o t e that t h e s e c o n d - s t a g e t r a n s c o n d u c t a n c e
T o d e t e r m i n e t h e v o l t a g e gain and t h e frequency r e s p o n s e , consider a simplified equivalent
G
m2
is given b y
circuit m o d e l for the small-signal operation of t h e C M O S amplifier (Fig. 9.2), w h e r e each of
r
the t w o stages is m o d e l e d as a t r a n s c o n d u c t a n c e amplifier. A s e x p e c t e d , the i n p u t resistance
a
=
J
^ m2
is practically infinite,
=
(9.14)
yOV6
5m6
Resistance R r e p r e s e n t s t h e output resistance of t h e s e c o n d stage, thus 2
R
=
2
T h e first-stage t r a n s c o n d u c t a n c e G
r
o6
II
(9.15)
r o l
is e q u a l to the t r a n s c o n d u c t a n c e of e a c h of Q and Q
m l
x
2
where
(see Section 7.5), G
ml
=
8ml
=
8m2
(9.16)
(9-6)
'06
—
t
In
and =
ri
=
0
[YAA
=
IZdll
(9.17)
T h e v o l t a g e g a i n of t h e s e c o n d s t a g e c a n n o w b e f o u n d as A
2
= -G R m2
=
FIGURE 9 . 2 Small-signal equivalent circuit for the op amp in Fig. 9.1.
'
2
-g (r Ur ) m6
o6
o7
(9-18) (9-19)
A M P
:
876
CHAPTER
9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS
THE TWO-STAGE CMOS
9.1
O P A M P
H e r e a g a i n w e o b s e r v e that t o i n c r e a s e t h e m a g n i t u d e of A , Qe h a s t o b e o p e r a t e d at a low 2
o v e r d r i v e v o l t a g e , a n d t h e c h a n n e l l e n g t h s of Q a n d Q s h o u l d b e m a d e longer. B o t h these 6
7
a c t i o n s , h o w e v e r , w o u l d r e d u c e t h e a m p l i f i e r b a n d w i d t h , w h i c h p r e s e n t s t h e d e s i g n e r with a n i m p o r t a n t trade-off. T h e overall d c v o l t a g e gain c a n b e f o u n d as the p r o d u c t A A
—
v
A,
X
2
AA X
=
2
G RG R ml
l
r
= 8 \( o2ÏÏ
m2
r )g (r
m
o4
V„
(9.21)
2
m6
II r )
o6
_
(9.22)
ol
FIGURE 9 . 3 An approximate highfrequency equivalent circuit of the twostage op amp. This circuit applies for frequencies f> f . P1
N o t e that A „ i s of t h e order of (g r ) m
. T h u s t h e m a x i m u m v a l u e of A will b e in the range of
0
v
500 V/V to 5000 V/V.
Here, f
is t h e d o m i n a n t p o l e formed b y t h e interaction of M i l l e r - m u l t i p l i e d C
Pi
Finally, w e n o t e that the o u t p u t r e s i s t a n c e of t h e o p a m p is e q u a l t o t h e output resistance
m2
of the s e c o n d stage,
[i.e.,
c
(1 + G R )C 2
= G RC]
c
m2
2
a n d R . T o a c h i e v e t h e goal of a u n i f o r m - 2 0 d B / d e c a d e gain
c
x
rolloff d o w n t o 0 d B , t h e unity-gain f r e q u e n c y / , R
0
= r
o6
II r
(9.23)
o l
ft
=
H e n c e R c a n b e large (i.e., in the tens-of-kilohms r a n g e ) . N e v e r t h e l e s s , since on-chip C M O S 0
_
o p a m p s a r e rarely required t o drive h e a v y l o a d s , t h e l a r g e o p e n - l o o p o u t p u t resistance is
(9.29)
fpi G
ml
(9.30)
2nC
u s u a l l y n o t a n i m p o r t a n t issue.
r
must b e l o w e r t h a n / p a n d / , thus t h e design m u s t satisfy t h e following t w o conditions 2
z
EXERCISE
(9.31) C
C
r
9.2
The C M O S op amp of Fig. 9.1 is fabricated in a process for which V' = j V' \ = 20 V/,i/m. Find A,, A,, and A. if all devices arc I um long. V , , = 0.2 V, and V , = 0.5 V. Also, find the op-amp output resistance obtained when the second stage is biased at 0.5 m A .
and
Ans. - 1 0 0 V/V: - 4 0 V/V: 4000 V/V: 20 k Q
Simplified
M
m
Ap
OV(
2
(9.32)
G „ I < G„
Equivalent Circuit
quencies/^ f
Pl
T h e uniform - 2 0 - d B / d e c a d e gain rolloff obtained at fre-
suggests that at these frequencies, the o p a m p can b e represented b y the simpli-
fied equivalent circuit shown in Fig. 9.3. Observe that this attractive simplification is based o n the assumption that the gain of the second stage, | A \,
9.1.4 Frequency Response
is large, and hence a virtual ground appears
2
Refer t o t h e e q u i v a l e n t circuit in Fig. 9.2. C a p a c i t a n c e C is t h e total c a p a c i t a n c e b e t w e e n
at the input terminal of the second stage. T h e second stage then effectively acts as an integrator
x
that is fed with t h e output current signal of the first stage; G V . ml
the o u t p u t n o d e of t h e first stage a n d g r o u n d , thus
Although derived for the
id
C M O S amplifier, this simplified equivalent circuit is general and applies to a variety of two-stage G\
=
Cgd2
+
Cdbl + Cgd4
+
G
4 + C'gs6
db
-
(9.24)
op amps, including the first t w o stages of the 741-type bipolar op a m p studied later in this chapter.
C a p a c i t a n c e C represents t h e total c a p a c i t a n c e b e t w e e n t h e output n o d e of t h e o p a m p and 2
g r o u n d a n d includes w h a t e v e r load capacitance C that the amplifier is required to drive, thus
Phase M a r g i n
T h e frequency c o m p e n s a t i o n s c h e m e utilized in t h e t w o - s t a g e C M O S
L
amplifier is of the pole-splitting t y p e , studied i n Section 8.11.3: It p r o v i d e s a d o m i n a n t l o w C =C 2
db6
+ C
dbl
+ C
gd7
+C
(9.25)
L
frequency p o l e w i t h frequency f
Pl
a n d shifts t h e s e c o n d p o l e b e y o n d f . F i g u r e 9.4 s h o w s a t
U s u a l l y , C is larger than t h e transistor c a p a c i t a n c e s , w i t h t h e result that C b e c o m e s m u c h
representative B o d e plot for t h e gain m a g n i t u d e a n d phase. N o t e that at t h e unity-gain fre-
larger t h a n C . Finally, note that C
quency f , t h e p h a s e lag exceeds t h e 90° caused b y t h e d o m i n a n t pole atf .
L
2
x
gd6
s h o u l d b e s h o w n i n parallel with C
c
b u t h a s been
i g n o r e d b e c a u s e C is usually m u c h larger. c
t
Pl
This so-called
excess phase shift is d u e t o t h e s e c o n d p o l e ,
T h e equivalent circuit of Fig. 9.2 w a s analyzed in detail in Section 7.7.1, w h e r e it w a s found that it has t w o poles and a positive real-axis zero with the following approximate frequencies:
0 and the
right-half-plane
P2
=-
tan_1
(y-J
9
( -
3 3
zero, (9.34)
1
z = - t a n " ^ fz Thus t h e p h a s e l a g a t / = / will b e
_ 1
1
(///p )+tan- (/// ) 2
z
(9.35)
)
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
9.1
CIRCUITS
THE TWO-STAGE CMOS O P A M P
transmission zero, set V = 0. T h e n , the current t h r o u g h C will b e V /(R node equation at t h e output yields
20 log |A| (dB)
0
A
c
20 log | A j
v
»
-
r
i2
+ l/sC ), c
8 7 9
and a
v
sC
c
Thus the zero is n o w at
1
fp2
fpi
f \
fz
• -•Mi-*)
fc
0
/ ( l o g scale)
W e observe that b y selecting R = l/G , w e c a n p l a c e the z e r o at infinite frequency. A n even better c h o i c e w o u l d b e to select R greater than 1 / G , thus p l a c i n g the zero at a n e g a tive real-axis location w h e r e the p h a s e it i n t r o d u c e s adds to t h e p h a s e m a r g i n .
1
1
m2
m 2
_ J
^
1
/ ( l o g scale) 9.3
|_L_
A particular implementation of the C M O S amplifier of Figs. 9.1 and 9.2 provides G , = I mA/V, G 2 mA/V, r„ = r„ = 100 k Q , r = r„ = 4 0 k Q . and C = 1 p F . H
2
Phase margin |
i
4
o 6
7
c
(b) Find the value of the resistance R that when placed/in series with Q- causes the transmission zero to be located at infinite frequency. (c) Find the frequency of the second pole and hence find the excess phase lag a t / = / „ introduced by the second pole, and the resulting phase margin assuming that the situation in (b) pertains.
F I G U R E 9 . 4 Typical frequency response of the two-stage op amp.
Ans. 1.6 pF; 50 kHz; 500 Q ; 318 M H z ; 17.4°; 72.fi and thus t h e p h a s e m a r g i n will b e 18O°-0
t o t a l
1
= 9 0 ° - tan" ( / / f
P 2
)
1
- tan" ( / / / ) z
(9.36)
F r o m o u r study of t h e stability of f e e d b a c k amplifiers i n Section 8.10.2, w e k n o w that the m a g n i t u d e of t h e p h a s e m a r g i n significantly affects t h e c l o s e d - l o o p gain. Therefore obtain ing a desired m i n i m u m value of p h a s e m a r g i n is usually a design r e q u i r e m e n t . . T h e p r o b l e m of the additional p h a s e lag p r o v i d e d b y the zero h a s a rather simple a n d ele gant solution: B y including a resistance R in series w i t h C , as s h o w n in F i g . 9.5, t h e trans m i s s i o n z e r o c a n b e m o v e d to other less-harmful locations. T o find t h e n e w location of the c
9.1.5 Slew Rate The slew-rate limitation of op a m p s is discussed in Chapter 2. Here, w e shall illustrate the ori gin of the slewing p h e n o m e n o n in the context of the two-stage C M O S amplifier u n d e r study. C o n s i d e r t h e unity-gain follower of F i g . 9.6 with a step of say, 1 V applied at the input. Because of the amplifier d y n a m i c s , its output will n o t c h a n g e in z e r o t i m e . T h u s , i m m e d i ately after the input is applied, t h e entire value of the step will appear as a differential signal between t h e t w o input terminals. In all likelihood, such a large signal will e x c e e d the voltage required to turn off o n e side of the pair (J2V ; see F i g . 7.6) and switch the entire bias 0V
-o IV
v,( + o
F I G U R E 9 . 5 Small-signal equivalent circuit of the op amp in Fig. 9.1 with a resistance R included in series with C . c
=
(a) Find the value of C that results in / — 100 MHz. W h a t i s the 3-dB frequency of the open-loop gain?
\
>
Phase margin =
m2
2
+
;
F I G U R E 9 . 6 A unity- gain follower with a large step input. Since the output voltage cannot change imme diately, a large differential voltage appears between the op-amp input terminals.
CHAPTER 9
8 8 0
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
9.1
CIRCUITS
THE TWO-STAGE CMOS
OP A M P
'
\ We conclude our study of the two-stage C M O S op a m p with a design example. Let it be required
•
j to design the circuit to obtain a dc gain of 4000 V/V. A s s u m e that the available fabrication technology is of the 0.5-jUm type for which V An
- j V'
j = 20 V/fjm, and V
kp
DD
=V
2
= |V \
tn
V'
= 0.5 V, k' = 200 pAN ,
lp
n
k
p
ss
£ = 1 faa for all devices. Also, for simplicity, operate all devices at the same | V \, ov
of 0.2 V to 0.4 V. Use 7 = 200 -uA, and to obtain a higher G ,
2
pATV ,
in the range
and hence a higher f ,
m2
F I G U R E 9 . 7 Model of the two-stage CMOS op amp of Fig. 9.1 when a large differential voltage is applied.
= 80
- 1.65 V. To achieve a reasonable dc gain per stage, use
P2
use I
=
D6
0.5 mA. Specify the W/L ratios for all transistors. Also give the values realized for the input common-mode range, the m a x i m u m possible output swing, R
and R . If C_ = 0.2 p F and C =
in
0
2
0.8 pF, find the required values of C and the series resistance R to place the transmission zero at c
s = °° and to obtain the highest possible / consistent with a phase margin of 75°. Evaluate the
current 7 to t h e other side. R e f e r e n c e to Fig. 9.1 s h o w s that for our e x a m p l e , Q will turn off, 2
values obtained for / and SR.
a n d <2i will c o n d u c t t h e entire current 7. T h u s Q will sink a current 7 that will b e pulled from 4
C , as s h o w n in F i g . 9.7. H e r e , as w e did in F i g . 9 . 3 , w e are m o d e l i n g t h e s e c o n d stage as an c
Solution
ideal integrator. W e see that the output v o l t a g e will b e a r a m p w i t h a slope of 7 / C : c
Using the voltage-gain expression in Eq. (9.22), (9.38) r
&v =
r
r
r
8m\( o2\\ o<Ù8mf>( o(>\\ ol)
T h u s the slew rate, SR, is g i v e n b y V
2
ov
SR =
—
ml
=g
ml
To obtain A
A s i m p l e relationship exists b e t w e e n t h e unity-gain = I/V ,
v
= 4000, given V = 20 V, A
400
4000
2
to obtain
ovl
SR =
Vov (9.40)
2nf V t
2
ov
ov
b a n d w i d t h / , a n d t h e slew rate SR. T h i s r e l a t i o n s h i p c a n b e found b y c o m b i n i n g E q s . (9.30) a n d (9.39) a n d n o t i n g that G
V
V
It should b e pointed out, h o w e v e r , that this is a rather simplified m o d e l of the slewing process.
Relationship Between SR and f,
(7/2)
(9.39)
0
mm
Vv 0
= 0.316 V
or equivalently, To obtain the required (W/L) ratios of Q and Q , x
SR = V o),
2
(9.41)
ov
T
T h u s , for a g i v e n co , t h e s l e w r a t e is d e t e r m i n e d b y t h e o v e r d r i v e v o l t a g e at w h i c h the
T/
_
2
t
f i r s t - s t a g e t r a n s i s t o r s are o p e r a t e d . A h i g h e r s l e w r a t e is o b t a i n e d b y o p e r a t i n g Q a n d Q x
at a l a r g e r V . ov
N o w , for a g i v e n b i a s c u r r e n t 7, a l a r g e r V
ov
is o b t a i n e d if Q
l
/7-channel d e v i c e s . T h i s is an i m p o r t a n t r e a s o n for u s i n g p - c h a n n e l rather t h a n
2
I
a n d Q axe, re-channel
will b e h i g h , resulting in a higher
V
xO-316
=
LJ_
t
ml
x
W\
s e c o n d - p o l e frequency and a c o r r e s p o n d i n g l y h i g h e r (O . H o w e v e r , the p r i c e paid for these i m p r o v e m e n t s is a l o w e r G
O
2
Thus,
stage to e m p l o y a n re-channel d e v i c e . N o w , since re-channel devices h a v e greater transconm2
~ 2 AL)X
100 = I
d e v i c e s in the first stage of the C M O S o p a m p . A n o t h e r r e a s o n is that it allows the second d u c t a n c e s than c o r r e s p o n d i n g p - c h a n n e l d e v i c e s , G
m
2
25 ^ m 1 /j.m
a n d h e n c e a l o w e r d c gain. and
EXERCISE
W\
=
L)
2
9.4
Find SR for the C M O S op a m p of Fig. 9.1 for the c a s e / , = 100 MFIz and V what must the bias current / be?
im
Ans. I 2 ( . \
us;200,uA
= 0.2 V. If Q - = 1.6 p i
25 ^ m 1 jim
For Q and Q we write 3
j^.
4
100 = -x20o(-]
xO.316
2
I
D6
8 8 1
882
! CHART ER
9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS
To move the transmission zero to s =
to obtain
LJ
4
we select the value of R as
R = — = m2
I 1 (im
\L)
3
THE FOLDED-CASCODE CMOS OP
9.2
- 3.2x10
G
= 316 O
For a phase margin of 75°, the phase shift due to the second pole at / = / , must b e 15°, that is,
For Q , 5
x80
200
= ^ (f)
1
xO.316
tan" ^
2
= 15°
J P 2
Thus,
Thus,
f = 637 x tan 15° = 171 M H z t
LJ
{ I
5
The value of C can be found using Eq. (9.30),
/mi.
c
Since <2 is required to conduct 500 jiA, its (W/L) ratio should b e 2.5 times that of Q 7
5
Cr = C
2nf
t
.lJ
' lzj
7
where
I 1 (im
5
„
2 x 100 LiA 0,316
=
n
^,63 m A ./
V °'
= *3 m » l. =
For Of, we write
Vn 7
Thus, 500 = i x 2 0 0 x f — ) x O . 3 1 6 2 VL
2
=
C
0.63 x 1 0 "
3
= 0.6 p F
2 ^ x 171 x 10
Thus, Vf\
The value of SR can now be found using Eq. (9.40) as
50 jxm
=
LJ
1 /jm
6
SR = 2KX171
= 340 V/,us
Finally, let's select / ^ p = 20 fiA, thus
-
]
Zj
6
x 1 0 x 0.316
0.lR = ^
=
vL./
8
9.2
1 pm
5
THE FOLDED-CASCODE CMOS OP AMP
The input c o m m o n - m o d e range can b e found using the expression in Eq. (9.4) as In this section w e study a n o t h e r t y p e of C M O S o p - a m p circuit: the folded c a s c o d e . T h e cir -1.33 V < V
ICM
< 0.52 V
cuit is b a s e d o n t h e f o l d e d - c a s c o d e amplifier studied in Section 6.8.6. T h e r e , it w a s m e n tioned that a l t h o u g h it is c o m p o s e d of a C S transistor a n d a C G transistor of o p p o s i t e
The m a x i m u m signal swing allowable at the output is found using the expression in Eq. (9.5) as -1.33 V < v
0
polarity, t h e f o l d e d - c a s c o d e configuration is g e n e r a l l y c o n s i d e r e d to b e a single-stage a m p l i fier. Similarly, t h e o p - a m p circuit that is b a s e d o n t h e c a s c o d e configuration is c o n s i d e r e d to
< 1.33 V
b e a single-stage o p a m p . N e v e r t h e l e s s , it c a n b e d e s i g n e d to p r o v i d e p e r f o r m a n c e p a r a m e
The input resistance is practically infinite, and the output resistance is
ters that e q u a l a n d in s o m e respects e x c e e d t h o s e of t h e t w o - s t a g e t o p o l o g y studied in the preceding section. Indeed, the folded-cascode o p - a m p topology is currently as popular as the
K
= r \\r o(l
= ± x | |
ol
= 20 k Q
two-stage structure. F u r t h e r m o r e , the folded-cascode configuration can b e used in conjunction with the two-stage structure to provide performance levels higher than those available from
T o determine f
P2
we use Eq. (9.27) and substitute for
G ,
either circuit a l o n e .
m2
21 2 x 0.5 = 7 7 ^ = rTTÎT = " V 0.316 D6
G
ml
3
= g
m6
ov
Thus,
2
mA/V
9.2.1 The Circuit Figure 9.8 s h o w s t h e structure of the C M O S f o l d e d - c a s c o d e o p a m p . H e r e , Qi a n d Q
2
form
the input differential pair, a n d Q and Q are the c a s c o d e transistors. R e c a l l that for differen 3
4
tial input signals, e a c h of Q a n d Q acts as a c o m m o n - s o u r c e amplifier. A l s o n o t e that t h e x
gate terminals of Q
3
and Q
4
2
are c o n n e c t e d to a constant d c v o l t a g e (VBIASI) afld h e n c e are
A M P
CHAPTER 9
THE FOLDED-CASCODE CMOS OP
9.2
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS
Cascode transistors
II ^ ov
0
/ Input differential pair
II,»
I' • 'I •
1
• Cascode current mirror
I
-Vss
FIGURE 9 . 8 Structure of the folded-cascode CMOS op amp.
FIGURE 9 . 9 A more complete circuit for the folded-cascode CMOS amplifier of Fig. 9.!
at signal ground. T h u s , for differential input signals, each of the transistor pairs Q\~Q and Q2-Q4 acts as a folded-cascode amplifier, such as the o n e in Fig. 6.45. N o t e that the input differential pair is biased b y a constant-current source / . T h u s each of Q and Q is operating at a bias current 1/2. A n o d e equation at each of their drains s h o w s that the bias current of e a c h of Q and Q is (I - 1 / 2 ) . Selecting I = I forces all transistors to operate at the same bias current of 1/2. F o r reasons that will b e explained shortly, h o w e v e r , the value of I is usually m a d e s o m e w h a t greater t h a n I. 3
y
3
4
B
2
B
B
A s w e learned in C h a p t e r 6, if the full a d v a n t a g e of the high output-resistance achieved t h r o u g h c a s c o d i n g is to b e realized, the output resistance of the current-source load m u s t b e equally high. T h i s is the reason for using the c a s c o d e current mirror Q to <2 , in the circuit of Fig. 9.8. (This current-mirror circuit w a s studied in Section 6.12.1.) Finally, note that capacitance C denotes the total capacitance at the output n o d e . It includes the internal tran sistor capacitances, an actual load capacitance (if any), and possibly an additional capacitance deliberately introduced for the p u r p o s e of frequency c o m p e n s a t i o n . In m a n y cases, however, the load capacitance will b e sufficiently large, obviating the need t o p r o v i d e additional capacitance t o achieve the desired frequency c o m p e n s a t i o n . This topic will b e discussed shortly. F o r the t i m e being, w e note that unlike the t w o - s t a g e circuit, that requires the introduction of a separate c o m p e n s a t i o n capacitor C , h e r e the load capacitance contributes to frequency c o m p e n s a t i o n . 5
c
A m o r e c o m p l e t e circuit for the C M O S folded-cascode op a m p is s h o w n in Fig. 9.9. H e r e w e s h o w the t w o transistors Q a n d Q , w h i c h p r o v i d e the constant bias currents I , and transistor Q , w h i c h provides the c o n s t a n t current / utilized for biasing the differential pair. O b s e r v e that the details for generating the bias voltages V , V , and V are h o t s h o w n . N e v e r t h e l e s s , w e are interested in h o w the values of these voltages are to b e selected. T o w a r d that end, w e evaluate the input c o m m o n - m o d e range and the allowable output swing. ]0
B
n
B [ A S 1
T o find the input c o m m o n - m o d e range, let the t w o input terminals b e tied together and con nected to a voltage V . T h e m a x i m u m value of V is h m i t e d by the requirement that Q and Q operate in saturation at all times. Thus V should b e at most V volts above the voltage at the drains of Q and Q . T h e latter voltage is determined by V and m u s t allow for a volt age drop across Q and Q at least equal to their overdrive voltage, | V 1 V 1. A s s u m ing that Q and Q are indeed operated at the e d g e of saturation, V will b e lCM
ICM
2
x
/ C M n a x
1
2
9
9
tn
B I A S 1
w
ov9
10
OV10
ICMmax
V
W,OV9
n
(9.42)
+ V
tm
8
L
9
9.2.2 Input Common-Mode Range and the Output Voltage Swing
BIAS2
which can b e larger than V , a significant i m p r o v e m e n t over the case of the two-stage cir cuit. T h e v a l u e of V IAS2 should b e selected to yield the required value of I while operating Q and Q at a small v a l u e of | V | (e.g., 0.2 V or so). T h e m i n i m u m value of V is the same as in the case of the two-stage circuit, n a m e l y DD
B
9
B
w
ov
ICMmin
1CM
(9.43)
-v.
The p r e s e n c e of the threshold voltage V, in this expression indicates that V / is not suf ficiently low. Later in this section w e shall describe an ingenious t e c h n i q u e for solving this problem. F o r the t i m e b e i n g , note that the v a l u e of V should b e selected to p r o v i d e the required v a l u e of I w h i l e operating Q at a low overdrive voltage. C o m b i n i n g E q s . (9.42) and (9.43) p r o v i d e s n
C M m i n
BlAS3
n
-V
ss
+V
o v n
+
V +V
tn
lCM
D
(9.44)
Vn
B I A S 3
T h e upper end of the allowable range of v is determined by the need to maintain Q and Q in saturation. N o t e that Q will operate in saturation as long as an overdrive voltage, | V \, appears across it. It follows that to maximize the allowable positive swing of v (and V ), 0
w
w
4
o v w
0
/ C M m a x
A M P
8 8 5
I
CHAPTER
9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
w e should select the value of V
9.2
CIRCUITS
+ -o
so that Q operates at the edge of saturation, that is,
BlASl
L0
V
=
VBIASI
d d
-\V
| - V
o v l 0
(9.45)
SG4
C— +
-o V
T h e u p p e r limit of v will then b e 0
<$> G V m
V
V
V
^Omax = DD ~\ OVW
I " I OV4
9
I
( -46)
irl
FIGURE 9 . 1 0 Small-signal equivalent cir cuit of the folded-cascode CMOS amplifier. Note that this circuit is in effect an operational transconductance amplifier (OTA).
o— w h i c h is t w o overdrive voltages b e l o w V . T h e situation i s n o t as good, however, at the DD
other e n d : S i n c e t h e voltage at t h e gate of Q is - V ^ + V 6
V
+V
0V1
ov5
GS1
+ V
GS5
o r equivalently -V
ss
THE FOLDED-CASCODE CMOS OP A M P
+
+ 2V , t h e lowest p o s s i b l e v is obtained w h e n Q r e a c h e s t h e e d g e of satura tn
0
6
tion, n a m e l y , w h e n v d e c r e a s e s b e l o w t h e voltage at t h e gate of Q b y V , that is, 0
6
v
* W
= ~ ss + Vovi + V
+ V
0V5
T h e dc o p e n - l o o p gain c a n n o w b e found u s i n g G and R , as
m
M
(9.47)
tn
N o t e that this v a l u e is t w o o v e r d r i v e v o l t a g e s plus a threshold voltage a b o v e -V . T h i s is a ss
A.
G
M
R
0
(9.54)
A
Thus,
d r a w b a c k of utilizing t h e c a s c o d e mirror. T h e p r o b l e m can b e alleviated b y u s i n g a modified A
m i r r o r circuit, as w e shall shortly see.
r
r
R
— gml{[gm4 o4( o2
v
H OTO)] II
r
(9.55)
r
(gm6 o6 o&)}
Figure 9 . 1 0 s h o w s t h e e q u i v a l e n t circuit m o d e l i n c l u d i n g t h e l o a d c a p a c i t a n c e C , w h i c h w e L
shall t a k e into a c c o u n t shortly. B e c a u s e t h e f o l d e d - c a s c o d e o p a m p i s a t r a n s c o n d u c t a n c e amplifier, it h a s b e e n given the n a m e o p e r a t i o n a l t r a n s c o n d u c t a n c e amplifier ( O T A ) . Its very h i g h output resistance, l'or a particular d e i g n of the folded cascode op amp o f Fig. '>.'). i l . o 5 - V supplies are inili/cd and all transistors are operated at»?oserdrive voltages of 0.3-V magnitude. T h e fabrication process employed provides V,„ = \V | = 0 . 5 V. Find the input,common-mode range and t h e range allowed for v .
2
which is of t h e order of g r m
0
(see E q . 9.53) is w h a t m a k e s it p o s s i b l e to realize a relatively
high v o l t a g e gain in a single amplifier stage. H o w e v e r , such a h i g h output resistance m a y b e
t
a cause of c o n c e r n t o t h e reader; after all, i n C h a p t e r 2, w e stated that a n ideal o p a m p h a s a
0
zero output r e s i s t a n c e ! T o alleviate this c o n c e r n s o m e w h a t , let u s find t h e c l o s e d - l o o p out
Ans.-0.55 V t o + 1 . 8 5 V ; - 0 . 5 5 V t o + 1 : 0 5 V.
put resistance of a unity-gain follower formed b y connecting t h e output terminal of t h e cir cuit of F i g . 9.9 b a c k to t h e n e g a t i v e input t e r m i n a l . S i n c e this f e e d b a c k is of t h e v o l t a g e sampling type, it r e d u c e s t h e output resistance b y t h e factor ( 1 + AB) w h e r e A = A a n d v
9.2.3 Voltage Gain
B = 1, that is,
T h e folded-cascode o p a m p is simply a transconductance amplifier with an infinite input resis tance, a transconductance G and an output resistance R . G is equal to g M
0
M
m
R
of each of the t w o
Rq of
1+A,
transistors of the differential pair,
„Rq
(9.56)
A„
Substituting for A f r o m E q . (9.54) gives v
G
=g
M
= g
mi
(9-48)
m2
Thus,
R
G
=
M
= V
(9.49) OVl
M
T h e output resistance R is t h e parallel e q u i v a l e n t of t h e output resistance of t h e c a s c o d e 0
= R JR
06
(9-50)
R e f e r e n c e t o F i g . 9.9 s h o w s that t h e r e s i s t a n c e R
is t h e output resistance of t h e C G transis
0
0
O4
tor Q . T h e latter h a s a resistance (r 4
II r
o2
o l 0
The resistance R
O6
m l
, thus
Since g
ml
(9.58)
is of t h e o r d e r o f 1 m A / V , R will b e of the o r d e r of 1 k Q . A l t h o u g h this is n o t OF
very small, it is r e a s o n a b l e i n v i e w of t h e simplicity of t h e o p - a m p circuit as w e l l as t h e fact that this t y p e of o p a m p is n o t u s u a l l y i n t e n d e d t o drive l o w - v a l u e d resistive loads.
) i n its s o u r c e lead, thus
R 4 = (Sm^ Kr 0
=g R of
amplifier and t h e output resistance of t h e c a s c o d e mirror, thus R
(9.57)
which is a g e n e r a l result that applies t o a n y O T A t o w h i c h 1 0 0 % v o l t a g e f e e d b a c k is applied. F o r o u r particular circuit, G
V
OVl
o f = \
o4
II r )
o2
(9.51)
olQ
EXERCISE
is the output resistance of the cascode mirror and is thus given by 9.6
E q . (6.141), thus
C o m b i n i n g E q s . (9.50) t o (9.52) gives
Ans.
Ro = lgmAr (r o4
I he C M O S op amp ol I igv ' ) > and >)M i- fabricated in a process u-r which I .' - I '. • 2D V m u . If all d e v i c e s h a v e l - ^ m i c h a n n e l length and are operated at equal overdrive voltages of 0.2-V magnitude, Inul the wiliri'v ":iin nht.'iiiii'd If all devices are biased at I0D //.V uh.il \alue nl A', is ohlained'.'
o2
|| r
o l 0
) ] II (g r r _) m6
o6
0
(9.53)
V ' V A ' : 15.1 Mi.2.
J 8 7
CHAPTER 9
OPERATIONAL-AMPLIFIER
A N D
DATA-CONVERTER
9.2
CIRCUITS
THE FOLDED-CASCODE
C M O S OP
the following relationship b e t w e e n SR a n d /
9.2.4 Frequency Response F r o m our study of t h e c a s c o d e configuration in Section 6.8 w e k n o w that o n e of its advan tages is its excellent high-frequency r e s p o n s e . It has poles at t h e input, at the connection b e t w e e n the C S a n d C G transistors (i.e., at t h e source terminals of Q and Q ), and at the output terminal. N o r m a l l y , t h e first t w o poles are at very h i g h frequencies, especially w h e n t h e resistance of t h e signal generator that feeds t h e differential pair is small. S i n c e t h e pri m a r y p u r p o s e of C M O S o p a m p s is to feed capacitive loads, C is usually large, and the pole at the output b e c o m e s d o m i n a n t . E v e n if C is n o t large, w e can increase it deliberately to give t h e o p a m p a d o m i n a n t p o l e . F r o m F i g . 9.10 w e c a n write 3
A
SR =
2Kf,V
(9.63)
0Vl
which is identical to the c o r r e s p o n d i n g relationship in the case of the t w o - s t a g e design. Note, h o w e v e r , that this relationship applies only w h e n I > I. B
L
L
V
o
m
V
0
(9.59)
l+sC R
id
B
0V
GR
_
Consider a design of the folded-cascode op amp of Fig. 9.9 for which / = 200 p.A, I = 250 /xA, and \V \ for all transistors is 0.25 V. Assume that the fabrication process provides k' = 100 fiA/V ,kp = 40 jUA/V , | V' | = 20 V/zxm. V = V = 2.5 V, and | V \ = 0.75 V. Let all transistors have L = 1 pm and assume that C = 5 pF. Find I , g , r„, and W/L for all transistors. Find the allowable range of V and of the output voltage swing. Determine the values of A . , , / , f , and SR. W h a t is the power dissipation of the op amp?
L
0
n
2
2
A
DD
ss
L
T h u s , t h e d o m i n a n t p o l e has a frequency
f,
t
D
m
ICM
P
P
(9.60) 2nC R L
0
Solution From the given values of / and I we can determine the drain current I for each transistor. The B
and the unity-gain f r e q u e n c y / , will b e
D
transconductance of each device is found using
f, = G RJ m
P
=
Q ^
21c
(9.61)
21c
=
V
0.25
ov
F r o m a design point-of-view, the v a l u e of C should b e such that at / = / t h e excess phase resulting from t h e n o n d o m i n a n t poles is small e n o u g h to p e r m i t the required p h a s e margin to b e achieved. If C is n o t large e n o u g h to a c h i e v e this p u r p o s e , it can b e a u g m e n t e d . It is i m p o r t a n t to n o t e the different effects of increasing the l o a d capacitance o n the oper ation of t h e t w o o p - a m p circuits w e h a v e studied. In the t w o - s t a g e circuit, if C is increased, the frequency of the second p o l e d e c r e a s e s , t h e excess p h a s e shift a t / = / increases, and the p h a s e m a r g i n is reduced. H e r e , on t h e other h a n d , w h e n C is increased, / decreases, but the p h a s e m a r g i n increases. In other w o r d s , a h e a v i e r capacitive load decreases the bandwidth of the folded-cascode amplifier b u t does n o t i m p a i r its r e s p o n s e (which h a p p e n s w h e n the p h a s e m a r g i n decreases). Of c o u r s e , if an increase in C is anticipated in the two-stage o p - a m p case, the designer can increase C , thus d e c r e a s i n g / , and restoring the p h a s e margin to its required value. L
and the output resistance r from 0
20
L
The W/L ratio for each transistor is determined from
L
L
L
1 &,(mA/V) ! r (kO) ! W/L 0
A s discussed in Section 9.1.5, s l e w i n g occurs w h e n a large differential input signal is applied. Refer to F i g . 9.8 and consider t h e c a s e w h e n a large signal V is applied so that Q cuts off a n d Qi c o n d u c t s the entire bias current I. W e see that Q will n o w carry a current ( 7 - 7 ) , and Q will c o n d u c t a current I . T h e current mirror will see an input current of (I -1) t h r o u g h <2 a n d <2 a n d t h u s its o u t p u t c u r r e n t in t h e drain of Q will be (I -I). It follows that at the output n o d e t h e current that will flow into C will b e 7 - 7 = I - (I -I) = I. Thus the output v will be a r a m p with a slope of I/C which is the slew rate, id
2
Oi
Q
100 0.8
100 0.8 200 32
200 32
2
Q
4
B
7
L
B
k'Vov
4
150 1.2 133 120
Qs
Q
150 1.2
150
6
1.2 133 48
133 48
Q
Q
150 1.2
150 1.2
133 48
133 48
250 2.0 80 200
8
9
i
Note that for all transistors, gr m
V
0
GS
= 160 V / V = 1.0 V
6
B
B
Q
1.2 133 120
B
5
3
150
z
B
r
h
The results are as follows:
c
9.2.5 Slew Rate
2I
W
(
L
0
4
6
Using the expression in Eq. (9.44), the input common-mode range is found to be
L
- 1 . 2 5 V
SR = J-
(9.62)
The output voltage swing is found using Eqs. (9.46) and (9.47) to be - 1 . 2 5 V < v <2 Q
N o t e that t h e r e a s o n for selecting I > I is to avoid turning off the current m i r r o r com pletely; if the current rnirror turns off, the output distortion increases. Typically, I is set 1 0 % to 2 0 % larger than I. Finally, E q s . (9.61), (9.62), and (9.49), can b e c o m b i n e d to obtain B
V
To obtain the voltage gain, we first determine R
o4
V
using Eq. (9.51) as
B
R
o4
= 160(200 II 80) = 9.14 M Q
Qio 250 2.0 80 200
200 1.6 100 64
A M P
CHAPTER 9
OPERATIONAL-AMPLIFIER
and R
o6
A N D DATA-CONVERTER
CIRCUITS
9.2
THE FOLDED-CASCODE
CMOS
OP A M P
891
using Eq. (9.52) as R
= 21.28 M Q
o6
The output resistance R can then be found as u
R
= R \\R
0
o4
= 6.4 M Q
o6
and the voltage gain A
3
= GR
v
m
= 0.8 x 1 0 " x 6.4 x 1 0
0
6
= 5120 V / V The unity-gain bandwidth is found using Eq. (9.61), 8
f, =
x
l
° ° — 27rx5xl0
= 25.5 M H z
Thus, the dominant-pole frequency must be k
f
J p
= 25^MHz 5120
A
v
=
fflz
The slew rate can be determined using Eq. (9.62), S
R
±
=
200 X 1 0 -
=
5 x 10~
C
L
6 =
4
Q
V
/
M
s
12
FIGURE 9 . 1 1 A folded-cascode op amp that employs two parallel complementary input stages to achieve rail-to-rail input common-mode operation. Note that the two "+" terminals are connected together and the two "-" terminals are connected together.
Finally, to determine the power dissipation w e note that the total current is 500 fiA = 0.5 mA, and the total supply voltage is 5 V, thus P
D
= 5 x 0.5 = 2.5 m W Thus, the v o l t a g e gain will b e A
9.2.6 Increasing the Input Common-Mode Range: Rail-to-Rail Input Operation
v
DD
7
ss
3
turn occurs only o v e r a limited r a n g e of V . O v e r the r e m a i n d e r of the input c o m m o n ICM
half of the value in E q . (9.65). This rail-to-rail folded-cascode structure is utilized in a c o m mercially available o p a m p .
magnitude and have j V,\ = 0.7 V and that V
nD
M
m2
0
(d) Find the input common- mode range /(Note^iatto:operate properly, each of the currentasources requires a minimum voltage of j V ,\ its terminals). m
m4
Ans.—1.2 V to +2.9 V; - 2 . 9 V to +1.2 V, - 1 . 2 V to +1.2 \ : 2.0 V to +2.9 V
id
-
= 2.5 v!"
.-(b). Find the range over which the P M O S input stage operates.
0
V
ss
• (c) Find the range over which both operate (the overlap range),
id
m
= V
„(a) Find the range.over which the N M O S input stage operates.
4
F i g u r e 9.11 indicates b y a r r o w s the direction of the current i n c r e m e n t s that result from the application of a positive differential input signal V . E a c h of the current i n c r e m e n t s indi cated is equal to G (V /2) w h e r e G„, = g = g = g,„_ = g - T h u s t h e total current feeding each of the t w o output n o d e s will b e G V . N o w , if the output resistance b e t w e e n each of the t w o n o d e s and g r o u n d is d e n o t e d R , t h e output voltage will b e jd
1
9.7 For the circuit in Fig. 9.11, assume that ail transistors arc operating at equal overdrive voltages of 0.3-V
0
m
(9.65)
0
m o d e r a n g e , only o n e of the t w o differential pairs will be operational, and the gain drops to
6
i
m
This, h o w e v e r , a s s u m e s that b o t h differential pairs will b e operating simultaneously. This in
In Section 9.2.2 w e found that w h i l e t h e u p p e r limit o n the input c o m m o n - m o d e range e x c e e d s t h e supply voltage V , the l o w e r limit is significantly l o w e r than V . T h e opposite situation occurs if the input differential amplifier is m a d e u p of P M O S transistors. It follows that an N M O S and a P M O S differential pair p l a c e d in parallel w o u l d p r o v i d e an input stage with a c o m m o n - m o d e r a n g e that e x c e e d s t h e p o w e r supply voltage in b o t h directions. This is k n o w n as rail-to-rail input operation. F i g u r e 9.11 s h o w s such an arrangement. T o k e e p the d i a g r a m simple, w e h a v e not s h o w n the parallel c o n n e c t i o n of t h e t w o differential pairs: T h e t w o positive input terminals are to b e c o n n e c t e d together and t h e two n e g a t i v e input termi nals are to b e tied together. Transistors Q a n d Q are t h e c a s c o d e transistors for the Q\-Q% pair, and transistors Q and Q are t h e c a s c o d e devices for the Q -Q pair. T h e output volt age V is s h o w n taken differentially b e t w e e n the drains of t h e c a s c o d e devices. T o obtain a single-ended output, a differential-to-single-ended c o n v e r s i o n circuit should b e connected in cascade. 5
= 2G R
2G R V m
0
id
(9.64)
1
The Texas Instruments OPA357.
across
8 9 2
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS
9.3
Q)
THE 741 O P - A M P CIRCUIT
9.8 Show that if transistor & in the circuit of Fig. E9.8 has a W/L ratio equaEto one-quarter (hat o f m e teal* sistors in the wide-swing current mirror of Fig. 9.12(b). and provided (he same value of / is utilized in both circuits, then the voltage generated. K, is V, + 2V , which is the value of V needed for t h e gales of Q and (J . P t p
ov
1V,+ 3
4
2V, + 2V
0
r
VBIAS =
V
>
j2 2 y
+
3
©
o
V, + V
0
02
/ref
llSlik. vtff3l»i^^^iiii^i|iilWiB^^^ silfSlsf§1 li^^li^^., JiliSil^S '.¿11111Stiffs
v,+ v
V +V t
4
ov
til
0
Q
3
V
B 1 N S
0
0
(b)
(a)
FIGURE E9.8
FIGURE 9 . 1 2 (a) Cascode current mirror with the voltages at all nodes indicated. Note that the minimum voltage allowed at the output is V, + V . (b) A modification of the cascode mirror that results in the reduction of the minimum output voltage to V . This is the wide-swing current mirror. ov
ov
9.3 9.2.7 Increasing the Output Voltage Range: The Wide-Swing Current Mirror In Section 9.2.2 it w a s found that w h i l e t h e output v o l t a g e of t h e circuit of F i g . 9.9 can s w i n g t o within 2 | V | of V , t h e c a s c o d e current m i r r o r limits t h e n e g a t i v e s w i n g to [ 2 | V \ + V,] a b o v e -V . In other w o r d s , the c a s c o d e rmrror r e d u c e s t h e v o l t a g e swing by V, volts. T h i s point is further illustrated i n F i g . 9.12(a), w h i c h s h o w s a c a s c o d e m i r r o r (with V = 0, for simplicity) and indicates t h e voltages that result at t h e various n o d e s . Observe that b e c a u s e t h e voltage at t h e gate of Q is 2V, + 2V ,_ t h e m i n i m u m voltage permitted at the o u t p u t ( w h i l e Q r e m a i n s saturated) is V, + 2V , h e n c e t h e extra V A l s o , o b s e r v e that C2i is operating with a drain-to-source v o l t a g e V, + V , w h i c h is V, volts greater than it n e e d s to o p e r a t e in saturation. W
ov
DD
ss
ss
3
3
0V
ov
r
ov
T h e observations a b o v e lead u s to t h e c o n c l u s i o n that t o p e r m i t t h e output voltage at the drain of Q to s w i n g as l o w as 2V , w e m u s t l o w e r the voltage at the gate of Q from 2V, + 2V t o V + 2V . This is e x a c t l y w h a t is d o n e in t h e modified m i r r o r circuit in F i g . 9.12(b): T h e gate of Q is n o w c o n n e c t e d t o a bias v o l t a g e V IAS V, + 2V . T h u s t h e output voltage can g o d o w n t o 2V with Q still in saturation. A l s o , t h e v o l t a g e at t h e drain of Q is now V a n d thus g , is operating at t h e e d g e of saturation. T h e s a m e is true of Q a n d thus the current tracking b e t w e e n Q a n d Q will b e assured. N o t e , h o w e v e r , that w e c a n n o longer c o n n e c t t h e gate of Q to its drain. R a t h e r , it is c o n n e c t e d t o t h e drain of Q . T h i s establishes a v o l t a g e of V, + V at the drain of Q w h i c h is sufficient t o operate Q in saturation (as long as V, is greater than V , w h i c h is usually the case). T h i s circuit is k n o w n as t h e w i d e - s w i n g c u r r e n t m i r r o r . Finally, note that F i g . 9.12(b) does n o t s h o w t h e circuit for generating V . T h e r e are a n u m b e r of possible circuits t o a c c o m p l i s h this task, o n e of which is explored in Exercise 9.8. " 3
0V
0V
t
3
Our study of B I T o p a m p s is focused on the 741 o p - a m p circuit, which is shown in Fig. 9 . 1 3 . Note that in k e e p i n g w i t h t h e I C d e s i g n p h i l o s o p h y t h e c i r c u i t u s e s a l a r g e n u m b e r of transistors, b u t relatively few resistors, a n d only o n e capacitor. This p h i l o s o p h y is dictated by the e c o n o m i c s (silicon area, ease of fabrication, quality of realizable c o m p o n e n t s ) of t h e fabrication of active and p a s s i v e c o m p o n e n t s in I C form ( s e e Section 6.1 a n d A p p e n d i x A ) . A s is t h e c a s e with m o s t general-purpose I C o p a m p s , t h e 7 4 1 requires t w o p o w e r supplies, +V and -V . Normally, V = V = 15 V , b u t t h e circuit also operates satisfactorily with the p o w e r supplies reduced to m u c h l o w e r values (such as ± 5 V ) . It is important t o observe that n o circuit node is connected to ground, the c o m m o n terminal of the t w o supplies. CC
EE
cc
EE
W i t h a relatively large circuit such as that s h o w n in Fig. 9 . 1 3 , t h e first step in t h e analysis is the identification of its r e c o g n i z a b l e parts a n d their functions. This can b e d o n e as follows.
9.3.1 Bias Circuit
0V
=
3
B
0V
0V
3
x
ov
2
x
2
2
4
ov
4
ov
B I A S
THE 741 OP-AMP CIRCUIT
4
The reference bias current of t h e 7 4 1 circuit, I^p, is g e n e r a t e d in t h e b r a n c h at t h e e x t r e m e left of Fig. 9 . 1 3 , consisting of t h e t w o d i o d e - c o n n e c t e d transistors Q a n d Q a n d t h e resistance R . U s i n g a W i d l a r current source f o r m e d b y Q , Q , a n d i ? , bias current for t h e first stage is g e n e r a t e d i n t h e collector of g . A n o t h e r current mirror f o r m e d b y Q a n d Q t a k e s part in biasing t h e first stage. n
5
n
] 0
l0
12
4
8
9
T h e reference bias current is used to provide t w o proportional currents in t h e collectors of Q . T h i s d o u b l e - c o l l e c t o r lateral pnp transistor c a n b e t h o u g h t of as t w o 2
13
See Appendix A for a description of lateral pnp transistors. Also, their characteristics were discussed in Section 6.2.
IMi^iMB^X^^
8 9 3
9.3
THE 741 O P - A M P CIRCUIT
transistors w h o s e b a s e - e m i t t e r j u n c t i o n s a r e c o n n e c t e d in parallel. T h u s Q a n d Q f o r m a t w o - o u t p u t c u r r e n t mirror: O n e output, t h e c o l l e c t o r of Q , p r o v i d e s b i a s current feig n , a n d t h e o t h e r o u t p u t , t h e collector of Q , p r o v i d e s b i a s current for t h e o u t p u t stage of the o p a m p . l2
13
l3B
13A
T w o m o r e transistors, Q and <2i9 is to establish t w o V
-a op
and Q , take part in t h e dc bias p r o c e s s . T h e p u r p o s e of Q drops b e t w e e n the b a s e s of the output transistors Q and Q .
Xi
O
l9
BE
Io
K
14
2(3
o
.2
*
¿3
8-a
g
9.3.2 Short-Circuit Protection Circuitry T h e 7 4 1 circuit includes a n u m b e r of transistors that are n o r m a l l y off a n d c o n d u c t only in the event that o n e attempts to d r a w a large current from the o p - a m p output terminal. This h a p p e n s , for e x a m p l e , if t h e output terminal is short-circuited to one of the t w o supplies. T h e short-circuit protection n e t w o r k consists of R , R , Q , Q , Q , R , and Q . In the following w e shall a s s u m e that these transistors are off. Operation of the short-circuit protection network will b e explained in Section 9.5.3.
00
6
S 3
M
g '3
-a ™ bo
l5
2l
24
u
22
9.3.3 The Input Stage T h e 7 4 1 circuit consists of three stages: an input differential stage, an intermediate singleended high-gain stage, and an output-buffering stage. T h e input stage consists of transistors g [ through Q , w i t h biasing performed b y <2 , Q , and f2io- Transistors Q and Q act as emitter followers, c a u s i n g the input resistance to b e h i g h and delivering the differential input signal to the differential c o m m o n - b a s e amplifier f o r m e d b y Q and Q . T h u s t h e input stage is the differential version of the c o m m o n - c o l l e c t o r c o m m o n - b a s e configuration discussed in Section 6.11.3.
1
Oi
o)
7
s
Sffl
7
ID
8
9
x
3
C -S
to cS s
4
Transistors Q , Q , and Q and resistors R R , and R form the load circuit of the input stage. This is an elaborate current-mirror load circuit, w h i c h w e will a n a l y z e in detail in S e c tion 9.5.1. It will b e s h o w n that this load circuit not only p r o v i d e s a high-resistance load but also converts the signal from differential to single-ended form with n o loss in gain or c o m m o n - m o d e rejection. T h e output of t h e input stage is t a k e n single-endedly at t h e collector of Q . A s m e n t i o n e d in Section 7.7.2, every o p - a m p circuit includes a level shifter w h o s e function is to shift t h e dc level of the signal so that t h e signal at the o p - a m p output can swing positive and n e g a t i v e . In the 7 4 1 , level shifting is d o n e in the first stage u s i n g t h e lateral pnp transistors Q and Q . A l t h o u g h lateral pnp transistors h a v e p o o r high-frequency performance, their u s e in the c o m m o n - b a s e configuration ( w h i c h is k n o w n to h a v e g o o d highfrequency r e s p o n s e ) does not seriously i m p a i r the o p - a m p frequency r e s p o n s e . s
13
2
6
7
u
2
3
6
Ml
-S £
T3 r- » § O) 2
3
Ol a ' .a
° a
o o g
4
T h e u s e of t h e lateral pnp transistors Q and Q in the first stage results in an a d d e d advantage: protection of t h e input-stage transistors Q and Q against e m i t t e r - b a s e j u n c t i o n breakdown. S i n c e t h e e m i t t e r - b a s e j u n c t i o n of an npn transistor b r e a k s d o w n at about 7 V of reverse bias (see Section 5.2.5), regular npn differential stages suffer such a b r e a k d o w n if, say, the supply v o l t a g e is accidentally c o n n e c t e d b e t w e e n t h e input terminals. Lateral pnp transistors, h o w e v e r , h a v e h i g h e m i t t e r - b a s e b r e a k d o w n voltages (about 5 0 V ) ; and b e c a u s e they are connected in series with Q and Q , they provide protection of the 741 input transistors, fii and Q . 3
4
x
H ° ? °
s a
x
2
2
2
; oi
9.3.4 The Second Stage The second or intermediate stage is c o m p o s e d of Q , Q , Q , and the t w o resistors R% and A \ . Transistor Q acts as an emitter follower, thus giving the second stage a high input 16
16
8 9 4
l7
nB
895
896
!"
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS
9.3
resistance. T h i s m i n i m i z e s the l o a d i n g on t h e input stage and avoids loss of gain. Transistor <2n acts as a c o m m o n - e m i t t e r amplifier w i t h a lOO-Q resistor in the emitter. Its load is com p o s e d of t h e h i g h output resistance of t h e pnp current source Q in parallel with the input resistance of t h e output stage (seen l o o k i n g into the b a s e of Q ). U s i n g a transistor current source as a load resistance (active load) enables o n e to obtain h i g h gain w i t h o u t resorting to the u s e of large load resistances, w h i c h w o u l d o c c u p y a large chip area and require large p o w e r - s u p p l y voltages.
THE 741 O P - A M P CIRCUIT
"cc A
l3B
23
V; o -
-Ov
T h e output of the s e c o n d stage is t a k e n at t h e collector of Q . Capacitor C is connected in the f e e d b a c k path of the s e c o n d stage to p r o v i d e frequency c o m p e n s a t i o n u s i n g the Miller c o m p e n s a t i o n t e c h n i q u e studied in Section 8 . 1 1 . It will b e s h o w n in Section 9.5 that the rel atively small capacitor C gives the 7 4 1 a d o m i n a n t p o l e at about 4 H z . F u r t h e r m o r e , pole splitting causes other poles to b e shifted to m u c h higher frequencies, giving the o p a m p a uniform - 2 0 - d B / d e c a d e gain rolloff w i t h a unity-gain b a n d w i d t h of about 1 M H z . It should b e p o i n t e d out that although C is small in value, t h e chip area that it o c c u p i e s is about 13 t i m e s that of a standard npn transistor! X1
n
c
c
c
(a)
(b)
9.3.5 The Output Stage T h e p u r p o s e of t h e output stage is to p r o v i d e t h e amplifier with a l o w output resistance. In addition, t h e output stage should b e able to supply relatively large load currents without dissipating an u n d u l y large a m o u n t of p o w e r in the I C . T h e 741 u s e s an efficient output circuit k n o w n as a class A B o u t p u t stage. O u t p u t stages are studied in detail in C h a p t e r 14, and t h e output stage of the 7 4 1 will be discussed in s o m e detail in Section 9.4. F o r t h e t i m e b e i n g w e w i s h to point out t h e differ e n c e b e t w e e n t h e class A B output stage a n d t h e output stage w e are familiar with, namely the emitter (or source) follower. F i g u r e 9.14(a) s h o w s an emitter follower b i a s e d with a constant-current source /. T o k e e p the emitter-follower transistor c o n d u c t i n g at all times and thus ensure t h e l o w output resistance it p r o v i d e s , the bias current I m u s t b e greater t h a n the largest m a g n i t u d e of load current i . T h i s is k n o w n as class A o p e r a t i o n and t h e emitter(source) follower is a class A o u t p u t stage. T h e d r a w b a c k of class A operation is the large p o w e r dissipated in the transistor. T h e p o w e r dissipated in the o u t p u t - s t a g e can b e r e d u c e d b y a r r a n g i n g for t h e transistor to turn o n o n l y w h e n an i n p u t signal is a p p l i e d . F o r this to w o r k , h o w e v e r , o n e n e e d s two t r a n s i s t o r s , an npn to s o u r c e o u t p u t c u r r e n t a n d a pnp to sink o u t p u t current. S u c h an a r r a n g e m e n t is s h o w n in F i g . 9 . 1 4 ( b ) . O b s e r v e t h a t b o t h t r a n s i s t o r s w i l l b e c u t off w h e n Vj = 0. In o t h e r w o r d s , t h e t r a n s i s t o r s a r e b i a s e d at a z e r o dc c u r r e n t . W h e n v g o e s posi tive, Q c o n d u c t s w h i l e Q r e m a i n off. W h e n v, g o e s n e g a t i v e t h e t r a n s i s t o r s r e v e r s e r o l e s . T h i s a r r a n g e m e n t is k n o w n as c l a s s B o p e r a t i o n a n d t h e c i r c u i t as a class B output stage. A l t h o u g h efficient in terms of p o w e r dissipation, t h e class B circuit causes output-signal distortion, as illustrated in Fig. 9.14(c). T h i s is a result of the fact that for \ v,\ less than about 0.5 V , neither of the transistors c o n d u c t s and v = 0. This t y p e of distortion is k n o w n as c r o s s o v e r distortion. C r o s s o v e r distortion can b e r e d u c e d b y b i a s i n g t h e output-stage transistors at a l o w cur rent. T h i s ensures that t h e output transistors Q and Q will r e m a i n c o n d u c t i n g w h e n v is small. A s vj increases, o n e of the t w o transistors c o n d u c t s m o r e , w h i l e the other shuts off, in a m a n n e r similar to that in the class B stage. T h e r e are a n u m b e r of w a y s for biasing the transistors of the class A B stage. Figure 9.14(d) s h o w s o n e such a p p r o a c h utilizing t w o d i o d e - c o n n e c t e d transistors Q and Q with junction L
1
N
A, A , V\7
• Time
P
(c)
(d)
FIGURE 9 . 1 4 (a) The emitter follower is a class A output stage, (b) Class B output stage, (c) The output of a class B output stage fed with an input sinusoid. Observe the crossover distortion, (d) Class AB output stage.
Q
N
P
r
x
2
areas m u c h smaller t h a n those of Q and Q . A s o m e w h a t m o r e elaborate biasing n e t w o r k is utilized in t h e 7 4 1 output stage. N
P
T h e output stage of t h e 7 4 1 consists of the c o m p l e m e n t a r y pair Q and Q , w h e r e Q is a substrate pnp (see A p p e n d i x A ) . Transistors Q and Q are fed b y current source Q and bias the output transistors Q and Q . Transistor Q (which is a n o t h e r substrate pnp) acts as an emitter follower, thus m i n i m i z i n g the loading effect of the output stage o n the second stage. 14
1S
14
20
K
23
2 0
20
i3A
8 9 7
CHAPTER 9
OPERATIONAL-AMPLIFIER AND DATA-CONVERTER
CIRCUITS
9.4
9.3.6 Device Parameters
.
D C ANALYSIS O F THE 7 4 1
9.4 DC ANALYSIS OF THE 741
In t h e following sections w e shall carry o u t a detailed analysis of the 7 4 1 circuit. F o r the standard npn and pnp transistors, t h e following p a r a m e t e r s will b e used: npn; pnp:
I 4
I
s
= 10" A, B = 200,V
A
1 4
I
s
= 10" A, B = 50, V
A
In t h e 7 4 1 circuit t h e n o n s t a n d a r d devices a r e Q , Q , l3
a s s u m e d to b e equivalent t o t w o transistors, Q
13A
u
= 125 V = 50 V a n d Q . Transistor Q 20
n
will b e
and Q , with parallel b a s e - e m i t t e r j u n c 13B
tions and h a v i n g t h e following saturation currents: I
SA
Transistors Q
l4
and Q
2Q
1 4
In this section, w e shall carry out a d c analysis of t h e 7 4 1 circuit t o d e t e r m i n e the bias point of each device. F o r the d c analysis of a n o p - a m p circuit t h e input t e n r u n a l s a r e g r o u n d e d . Theoretically speaking, this should result in zero d c voltage at the output. H o w e v e r , b e c a u s e the o p a m p has very large gain, any slight a p p r o x i m a t i o n in the analysis will show that t h e output v o l t a g e is far from being zero and is close t o either +V o r -V . I n actual practice, an o p a m p left o p e n - l o o p will h a v e an o u t p u t voltage saturated close t o o n e of the t w o supplies. T o o v e r c o m e this p r o b l e m in t h e d c analysis, it will b e a s s u m e d that the o p a m p is connected in a negative-feedback loop that stabilizes the output dc voltage to zero volts. CC
EE
1 4
= 0.25 x 1 0 " A
I'SB = 0.75 x 1 0 " A XB
will b e a s s u m e d t o e a c h h a v e a n area three times that of a standard
device. O u t p u t transistors usually h a v e relatively large areas, to b e able to supply large load currents and dissipate relatively large a m o u n t s of p o w e r w i t h only a m o d e r a t e increase in
9.4.1 Reference Bias Current The reference bias current 1^ is generated in t h e b r a n c h c o m p o s e d of t h e t w o d i o d e connected transistors Q and Q and resistor R . W i t h reference t o Fig. 9 . 1 3 , w e can write n
n
5
device t e m p e r a t u r e .
EXERCISES
For V
9.9 For the standard npn transistor whose parameters are given in Section 9.3.6« find approximate vajues> for the following parameters a t / = 1 mA: V , r . r . and r„. c
BC
c
x
C C
= V
= 15 V a n d V
EE
B E U
= V
0.7 V , w e h a v e /
E B 1 2
R
E
F
= 0.73 m A .
9.4.2 Input-Stage Bias Transistor Q is biased b y I^p, a n d t h e v o l t a g e d e v e l o p e d across it is u s e d to bias Q , which has a series emitter resistance R . T h i s part of the circuit is r e d r a w n in Fig. 9.15 a n d can b e r e c o g n i z e d as the W i d l a r current source studied in Section 6.12.5. F r o m the circuit, and a s s u m i n g B t o b e large, w e h a v e n
Ans. 633 i n V : 4tl m A / V : 25 LI: 5 k U . 125 kl'2
l0
4
9.10 For the circuit in F i g . € 9 . 1 0 , neglect base currents and use the exponential ^ ^ r e l a t i o n s h i p to show that
w
VBEU
.52
~ VBEIO —
Thus -15 V À
k
VVln^SF
è
=
j
c
i
o
R
4
(
9
M
)
•*C10
where it has been assumed that I = I . Substituting the k n o w n values for 4 ^ and R , this equation can be solved by trial and error to determine I . For our case, the result is 7 = 19 pA. S10
s n
4
C10
-t. 15 \
FIGURE E9.io
FIGURE 9 . 1 5 The Widlar current source.
C I 0
C^J
899
CHAPTER 9
9.4
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS
For the 7 4 1 , I
c
w
= 19 piA; thus I — 9.5 piA. W e h a v e thus d e t e r m i n e d that
!ci = Ic2 1 Design i h c W i d l a r current source of Fig. 9.15 to generate a c u r r e n t / If at a collector current of 1 mA, V
HE
Ans. A'.-- 1 1.5 ki»:
= 0.7 V, find V
, and
HFA
V
a o
= 10 p.A given that /
R E r
- 1 mA.
7
= c s = ICA = 9.5 piA
At this point, w e should n o t e that transistors Q t h r o u g h g , g , and Q f o r m a n e g a t i v e f e e d b a c k l o o p , w h i c h w o r k s to stabilize the v a l u e of I at a p p r o x i m a t e l y 7 / 2 . T o appreciate this fact, a s s u m e that for s o m e reason t h e current I in Q and Q increases. This will cause the current p u l l e d from <2 to increase, and t h e output current of t h e Q -Q mirror will correspondingly increase. H o w e v e r , since I r e m a i n s constant, n o d e X forces t h e c o m bined b a s e currents of Q and Q to decrease. This in turn will c a u s e the emitter currents of Q and Q , and h e n c e the collector currents of Q and Q , to decrease. T h i s is opposite in direction to the c h a n g e originally a s s u m e d . H e n c e the feedback is negative, and it stabilizes the value of I. x
.
4
8
9
c l 0
uklQ
-<>." \ : V .. .. -H.5S5 \
x
:
2
8
s
c
3
H a v i n g d e t e r m i n e d I , w e p r o c e e d to d e t e r m i n e t h e dc current in each of t h e input-stage transistors. Part of t h e input stage is r e d r a w n in F i g . 9.16. F r o m s y m m e t r y , w e see that c w
=
Id
Id
3
4
4
Gifr
1
2
t h e n
— -TE4 ~ I
a n d t h e b a s e currents of Q and Q are equal, w i t h a v a l u e of 3
9
w
Figure 9.17 s h o w s the r e m a i n d e r of the 7 4 1 input stage. If w e neglect the b a s e current of
D e n o t e this current b y I. W e see that if t h e npn ¡3 is high, t h e n IE3
DC ANALYSIS O F THE 741
4
+ 1) - / / B , w h e r e B P
P
Similarly, n e g l e c t i n g the b a s e current of Q w e obtain
d e n o t e s B of t h e pnp devices.
7
T h e current m i r r o r formed b y g and Q is fed b y an input current of 27. U s i n g t h e result 8
9
in Eq. (6.21), w e c a n express the output current of t h e mirror as The bias current of Q can b e d e t e r m i n e d from 7
J ci
l
~ T -— 1EI
2
1
+ +
V
B
E
6
+
I
R
¡0.(9.67) m\
L
^
W e c a n n o w write a n o d e equation for n o d e X in Fig. 9.16 a n d thus d e t e r m i n e t h e v a l u e of 7. where fi denotes ¡5 of the npn transistors. T o d e t e r m i n e V tial relationship a n d write
If B > 1, t h e n this n o d e equation gives
N
P
BE6
w e u s e t h e transistor e x p o n e n -
2 / - lew V
BE6
= V In y T
1 4
Substituting I - 1 0 " A and I = 9.5 jiA results i n V (, — 5 1 7 m V . T h e n substituting in Eq. (9.67) yields I = 10.5 piA. N o t e that t h e b a s e current o f Q is i n d e e d negligible i n comparison to t h e value of I, as has b e e n a s s u m e d . s
BE
C1
I i I » I
lew
1 I I
FIGURE 9 . 1 6 The dc analysis of the 741 input stage.
7
) 901
9 0 2
i'i
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS 9.4
9.4.3 Input Bias and Offset Currents
D C ANALYSIS O FT H E 7 4 1
b a s e - e m i t t e r voltage of Q is l7
T h e i n p u t b i a s c u r r e n t of an o p a m p is defined (Chapters 2 a n d 7) as T
Ibi
_
+
V n
= V ln-^
BE
^B2
= 618 m V
T
T h e collector current of Q c a n b e d e t e r m i n e d from l6
F o r t h e 7 4 1 w e obtain J_
T
~
ci6
— 'ei6
J
U s i n g B = 2 0 0 , yields I = 47.5 n A . N o t e that this v a l u e is r e a s o n a b l y small a n d is typical of g e n e r a l - p u r p o s e o p a m p s that u s e B J T s in t h e input stage. M u c h l o w e r input b i a s currents (in the p i c o a m p o r f e m t o a m p r a n g e ) c a n b e o b t a i n e d using a F E T input stage. A l s o , there exist t e c h n i q u e s for r e d u c i n g t h e input bias current of bipolar-input o p a m p s . B e c a u s e of possible m i s m a t c h e s in t h e B v a l u e s o f Q_ and Q , the input b a s e currents will n o t b e equal. G i v e n t h e value o f t h e ¡3 m i s m a t c h , o n e c a n u s e E q . (7.137) to calculate the i n p u t offset current, defined as N
B
T
-
T
-
' j n
_i_ -^£17-^8 + -
1
^BEVl
r; Rg
This calculation yields 7 = 16.2 pA. N o t e that t h e b a s e current of Q will indeed b e negligible c o m p a r e d t o t h e input-stage bias 7, as w e h a v e a s s u m e d . 16
C ] 6
9.4.7 Output-Stage Bias
2
F i g u r e 9 . 1 8 s h o w s t h e o u t p u t s t a g e o f t h e 7 4 1 w i t h t h e s h o r t - c i r c u i t - p r o t e c t i o n circuitry omitted. Current source Q delivers a current of 0 . 2 5 7 ^ (because 7 of Q is 0 . 2 5 t i m e s t h e I o f Q ) t o t h e n e t w o r k c o m p o s e d o f Q , Q , a n d 7? . If w e n e g l e c t t h e b a s e currents o f < 2 i a n d Q2Q, t h e n t h e e m i t t e r c u r r e n t o f Q23 will also b e e q u a l t o 0 . 2 5 7 . Thus l3A
5
i2
S
1S
19
R E F
4
9.4.4 Input Offset Voltage F r o m C h a p t e r 7 w e k n o w that t h e input offset v o l t a g e i s d e t e r m i n e d primarily b y mism a t c h e s b e t w e e n t h e t w o sides of the input stage. I n t h e 7 4 1 o p a m p , t h e input offset voltage is d u e t o m i s m a t c h e s b e t w e e n Q a n d Q , b e t w e e n Q a n d Q , b e t w e e n Q a n d Q , and b e t w e e n R a n d R . Evaluation of t h e c o m p o n e n t s of V c o r r e s p o n d i n g t o t h e various mism a t c h e s follows t h e m e t h o d outlined i n S e c t i o n 7.4. Basically, w e find t h e current that results at the output of the first stage d u e to t h e particular m i s m a t c h being considered. Then w e find t h e differential input v o l t a g e that m u s t b e applied t o r e d u c e t h e output current to zero. 1
t
2
3
2
4
5
6
leu
-
I 2i = 0 - 2 5 7 ^ E
= 180 M
Thus w e see that t h e b a s e current of Q is only 1 8 0 / 5 0 = 3.6 pA, w h i c h is negligible c o m pared t o 7 , as w e h a v e a s s u m e d . 23
C 1 7
os
cc
in
9.4.5 Input Common-Mode Range
A
|0.25/
T h e i n p u t c o m m o n - m o d e r a n g e is t h e r a n g e of input c o m m o n - m o d e v o l t a g e s over which the input stage r e m a i n s in t h e linear active m o d e . Refer t o F i g . 9 . 1 3 . W e see that in the 741 circuit t h e input c o m m o n - m o d e r a n g e is d e t e r m i n e d at t h e u p p e r e n d b y saturation of Q and Q , a n d at t h e l o w e r e n d b y saturation of Q a n d Q .
R E F
x
2
3
4
—(Q9 —o
9.12 Neglect the voltage drops across /?, and R and assume that V = V = 15 V. Show that the input commonmode range of the 741 is approximately - ( 2 . 9 to +14.7 V . (Assume that V = 0.6 V and that to avoid saturation V > - 0 . 3 V for an npn transistor, and V > - 0 . 3 V iorapnp transistor.) 2
cc
0V
n:
BE
CB
= 0 . 257
BC
R
v
9.4.6 Second-Stage Bias If w e n e g l e c t t h e b a s e current of Q t h e n w e see from F i g . 9.13 that t h e collector current ot < 2 i is a p p r o x i m a t e l y equal to the current supplied b y current source Q13B. B e c a u s e Qi3B has a scale current 0.75 t i m e s that of Q , its collector current will b e 7 = 0 . 7 5 7 ^ , where we h a v e a s s u m e d that / j $> 1. T h u s I = 5 5 0 pA a n d 7 = 5 5 0 pA. A t this current level the 23
7
n
p
C 1 3 B
C 1 3 B
C 1 7
l3A
10
FIGURE 9 . 1 8 The 741 output stage without the short-circuit protection devices.
9 0 3
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
If w e a s s u m e that V
B £ 1 8
CIRCUITS
9.5
is a p p r o x i m a t e l y 0.6 V , w e c a n d e t e r m i n e t h e c u r r e n t i n R
as
w
SMALL-SIGNAL ANALYSIS O F THE 7 4 1
EXERCISE
15 jUA. T h e emitter current of Q is therefore 1&
/
9.13 If in the circuit of Fig. 9.18 the Q\$-Q network is replaced by two diode-connected transistors, find • the current in OY, and (Hint: Use the result of Exercise 9.10.V
= 1 8 0 - 15 = 165 LiA
E 1 8
i9
:
Ans. 540 LIA
Also, Iciz
~ hy% = 165 piA
A t this value of current w e find that V
B E n
= 5 8 8 m V , w h i c h is quite c l o s e to the value
a s s u m e d . T h e b a s e current of Q is 165/200 = 0.8 LiA, w h i c h c a n b e a d d e d to t h e current in x8
R
! 9.5 SMALL-SIGNAL ANALYSIS OF THE 741
to d e t e r m i n e t h e Q current as
l0
X9
9.5.1 The Input Stage
hi9 = 15.8 LiA
'ci9 =
T h e voltage d r o p across t h e b a s e - e m i t t e r j u n c t i o n of Q c a n n o w b e d e t e r m i n e d a s l9
Figure 9.19 s h o w s part of the 7 4 1 input stage for the p u r p o s e of p e r f o r m i n g small-signal analysis. N o t e that since the collectors of Q a n d Q me connected to a constant dc voltage, they are s h o w n g r o u n d e d . A l s o , t h e constant-current biasing of t h e bases o f Q a n d Q i s equivalent to h a v i n g the c o m m o n b a s e terminal open-circuited. T h e differential signal v, applied b e t w e e n t h e input terminals effectively appears across four equal emitter resistances connected in s e r i e s — t h o s e of Q Q , Q , a n d Q . A s a result, emitter signal currents flow as indicated in Fig. 9.19 w i t h t
2
3
V
= V In ^ Is
BEl9
T
530 m V
=
A s m e n t i o n e d in Section 9.3.5, t h e p u r p o s e of the Qi$-Qi
n e t w o r k is to establish t w o V
9
BE
drops b e t w e e n t h e bases of t h e output transistors Q a n d Q . T h i s voltage d r o p , V , can b e u
20
lt
I I
V
BB
BB
=V
+V
BEW
BE19
3
4
BB
n o w calculated a s
Since V
2
A
(9.68)
4r„
= 5 8 8 + 5 3 0 = 1.118 V
appears across the series c o m b i n a t i o n of t h e b a s e - e m i t t e r j u n c t i o n s of Q and
where r denotes t h e emitter resistance of e a c h of Q t h r o u g h Q . T h u s e
l
4
u
25 m V 9.5 ^ A
Q , w e c a n write 2Q
I
2.63
m
7
V =
V r l n ^ + V V l n - ^
BB
ASM
Thus the four transistors Q through Q supply t h e load circuit with a pair of c o m p l e m e n t a r y current signals ai , as indicated in Fig. 9.19. The input differential resistance of the o p a m p c a n b e obtained from Fig. 9.19 as x
*S20
4
e
U s i n g t h e calculated v a l u e of V
BB
a n d substituting I
S14
=I
S20
= 3 x 10~
1 4
A , w e determine the~
collector currents as
R
id
LEU = Icio = 154 M
= 4(p +l)r N
e
(9.69)
For P = 2 0 0 , w e obtain R = 2.1 M O . N
id
T h i s is t h e small current at w h i c h t h e class A B output stage is biased.
9.4.8 Summary F o r future reference, T a b l e 9.1 p r o v i d e s a listing of t h e v a l u e s of t h e collector bias currents of the 7 4 1 transistors.
9/]
Dc Collector Currents of t h e 741 Circuit (t/A) 19
QlîB
550
&
19
Gio on
G l4 Gl5
154
19 730
Ql2
730
0,
9.5
Q%
0-, \£2 0% 3Z>5
9.5
Ok
9.5
c\
9.5
06
9.5
9.5
e 10.5 7
Ô13A
180
Û19 1
0
16.2
Ô20
4r„
1 j4 A
G21
U A
<2l7
550
Q22 Q23
G8l
165
Q24
Ô16
15.i,8 C/l
U 1
en A
U
FIGURE 9 . 1 9 Small-signal analysis of the 741 input stage.
£*\
CHAPTER 9
OPERATIONAL-AMPLIFIER
A N D
DATA-CONVERTER
CIRCUITS
9.5
SMALL-SIGNAL
ANALYSIS OF THE
FIGURE 9 . 2 1 Simplified circuits for finding the two components of the output resistance R of the first stage. ol
(a)'
(b)
T o c o m p l e t e our m o d e l i n g of the 741 input stage w e m u s t find its output resistance R . This is t h e r e s i s t a n c e seen " l o o k i n g b a c k " into t h e collector t e r m i n a l of Q in F i g . 9.20. T h u s R is the parallel equivalent of t h e output resistance of the current source supplying the sig nal current ai and the output resistance of Q . T h e first c o m p o n e n t is t h e resistance looking into the collector of Q in F i g . 9.19. F i n d i n g this resistance is considerably simplified if w e assume that the c o m m o n b a s e s of Q and Q are at a virtual ground. This of course h a p p e n s only w h e n the input signal v, is applied in a c o m p l e m e n t a r y fashion. N e v e r t h e l e s s , this assumption d o e s n o t result in a large error. oi
F I G U R E 9 . 2 0 The load circuit of the input stage fed by the two complementary current signals generated by Qi through Q in Fig. 9.19. Circled numbers indicate the order of the analysis steps. 4
6
gl
e
6
4
P r o c e e d i n g w i t h t h e input-stage analysis, w e s h o w in Fig. 9.20 the load circuit fed with the c o m p l e m e n t a r y pair of current signals f o u n d earlier. N e g l e c t i n g t h e signal current in the b a s e of Q , w e see that t h e collector signal current of Q is a p p r o x i m a t e l y equal to the input current ai . N o w , since Q and Q are identical a n d their b a s e s a r e tied together, a n d since e q u a l resistances are c o n n e c t e d in their e m i t t e r s , it follows that then collector signal currents m u s t b e equal. T h u s the signal current in t h e collector of Q is forced to b e e q u a l to ai . In other w o r d s , the load circuit functions as a current mirror. N o w consider the output n o d e of t h e input stage. T h e output current i is given b y 7
5
e
5
6
-
6
e
3
4
A s s u m i n g that the b a s e of Q is at virtual g r o u n d , t h e resistance w e a r e after is R , indi cated in F i g . 9.21(a). This is t h e output resistance of a c o m m o n - b a s e transistor that has a resistance (r of Q ) in its e m i t t e r . T o find R w e m a y use the following expression (Eq. 6.118): 4
e
o4
2
o4
0
i
= 2ai
a
R=
(9.70)"
e
T h e factor of 2 in this equation indicates that c o n v e r s i o n from differential to single-ended is p e r f o r m e d w i t h o u t losing half the signal. T h e trick, of c o u r s e , is the u s e of t h e current mirror to invert o n e of t h e current signals and then add the result to t h e other current signal (see S e c t i o n 7.5).
m
E
(9.72)
x
Substituting R - r = 2.63 k Q a n d r = V /I, w h e r e V = 5 0 V and 1= 9.5 fiA (thus r = 5.26 M Q ) , a n d neglecting r since it is (B + 1) t i m e s larger t h a n R , results in R - 10.5 M Q . E
e
0
n
A
A
0
E
o4
T h e second c o m p o n e n t of the output resistance is that seen l o o k i n g into t h e collector of Q in Fig. 9.20. A l t h o u g h the b a s e of Q is not at signal ground, w e shall a s s u m e that the signal voltage at t h e b a s e is small e n o u g h to m a k e this a p p r o x i m a t i o n valid. T h e circuit then takes the form s h o w n in F i g . 9.21(b), and R can b e d e t e r m i n e d using Eq. (9.72) with R = R . Thus R = 18.2 M Q . 6
E q u a t i o n s (9.68) a n d (9.70) can b e c o m b i n e d to obtain the t r a n s c o n d u c t a n c e of the input
r„[l+g (R //r )]
0
6
o6
stage, G,„_:
Finally, w e c o m b i n e R and R stage, R , as R = 6.7 M Q . o4
G
m
l
^
= f-
(9.71)
ol
o6
2
in parallel t o obtain t h e output resistance of the input
0l
Figure 9.22 s h o w s the equivalent circuit that w e h a v e derived for the input stage. Substituting r = 2 . 6 3 kQ and a
1 y i e l d s G,„, = 1/5.26 m A / V .
e
9 1 4 For the circuit in F i g . 9.20, find in terms of i : (a) the signal voltage at the base of fi ; (b) the signal current in the emitter of Qi (c) the signal current in the base of Qi (d) the signal voltage at the base ot Qi (e) the input resistance seen by the left-hand-side signal current source m . (Note: For simplicity, assume that I ~ I s ~ e
6
e
a
C
Ans. (a) 3.63 k Q x i ; (b) 0.08*,; (c) 0.0004;,; (d) 3.84 kQ x i ; (e) 3.84 k Q e
E
o6
e
FIGURE 9 . 2 2 Small-signal equivalent circuit for the input stage of the 741 op amp.
741
907
9 0 8
CHAPTER
9
OPERATIONAL-AMPLIFIER
A N D
DATA-CONVERTER
CIRCUITS
9.5
W e wish to find the input offset voltage resulting from a 2 % mismatch between the resistances R,
SMALL-SIGNAL
ANALYSIS OF THE
909
741
The purpose of this series of exercises is to determine the finite c o m m o n - m o d e gain that results from a mismatch in the load circuit of the input stage of the 741 op amp. Figure E9.15 shows the input stage with an input c o m m o n - m o d e signal v applied and with a mismatch AR between the t w o resistances R and R . Note that to simplify matters, w e have opened the c o m m o n - m o d e feedback loop and included a resis tance R„, which is t h e resistance seen looking to the left of node Y in the circuit of Fig. 9.13. T h u s R is the parallel equivalent of R, (the output resistance of Q ) and R (the output resistance of Q ). 9.15 Shovv that the current / (Fig. E9.15) is given approximately by
and R in Fig. 9.13. 2
inH
Solution
t
2
Consider first the situation when both input terminals are grounded, and assume that R =R and R = R + AR, where AR/R = 0.02. F r o m Fig. 9.23 we see that while Q still conducts a current equal to I, the current in Q will be smaller by AI. The value of AI can be found from }
2
5
A
6
V +IR
= V +{I-AI)(R
BE5
r +r e]
V -V BE5
=IAR-AI(R
BE6
+ AR)
The quantity on the left-hand side is in effect the change in V
BE
due to a change in I of A7. We
A7 I
Air.
(9.74)
0
P
9.17 Using the results of Exercises 9.15 and 9.16, and assuming that AR < (R + r ) and Ra/(PP ( ' e i + r ), show that the common-mode iransconductance G,,„.„, is given approximately by e
Ai?
=
(9.75)
R + AR + r„
2A'
e
x
2
J
to an output current AI = 5.5 x 10~ 7. To reduce this output current to zero we have to apply an
1
given by V
0S
Substituting 1= 9.5 LiA and G
m l
=
A7
5.5 x 10
/
(9.76)
= 1/5.26 m A / V results in the offset voltage V
os
= 0.3 mV.
It should be pointed out that the offset voltage calculated is only one component of the input offset voltage of the 7 4 1 . Other components arise because of mismatches in transistor character istics. The 741 offset voltage is specified to be typically 2 m V .
so
[2R /(p +l)]
e3
Substituting R = 1 k O and r = 2.63 k Q shows that a 2 % mismatch between R and R gives rise
1
+
\R
E
Equations (9.73) and (9.74) can be combined to obtain
©
eJ
i„ = -i V,BE6
os
1Q
9.16 Show that
(9.73)
may therefore write
input voltage V
lA0
+ AR)
BE6
Thus
4
•H
"~1
©
AI I-
AI
3 R = R +
R, = R
t
v
2
AR
t
FIGURE 9 . 2 3 Input stage with both inputs grounded and a mismatch AR between R and R . x
2
-9
FIGURE E9.15
R-r
t
+ 1)
S>
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
9 18 Refer to Fi« 9 11 and assume that the bases of 0 (signal ground). Find
R
oi0
T r a n s c o n d u c t a n c e F r o m t h e equivalent circuit of Fig. 9 . 2 5 , w e see that t h e t r a n s c o n ductance G is t h e ratio of t h e short-circuit output current t o t h e input voltage. Shortcircuiting t h e output terminal of t h e s e c o n d stage (Fig. 9.24) t o g r o u n d m a k e s t h e signal current t h r o u g h the output resistance of Q zero, a n d t h e output short-circuit current b e c o m e s e q u a l t o t h e collector signal current of Q ( / ) . This latter current c a n b e easily related t o v as follows:
and Gin are at approximately constant voltages
9
and hence R„. Use V = 125 V for npn and 50 V loxpnp A
SMALL-SIGNAL ANALYSIS OF T H E741
9.5
CIRCUITS
M2
transistors.
n
Ans. A' .. - 2 A ' M12: A' ... -- 31.1 M12: A' - 2.-15 M i l
B
l7
9.19 For ft, = 50 and AR/R = 0.02, evaluate G"„,.„, obtained in Exercise 9.17. t
cl7
i2
Ans. 0.057 u . V V 9.20 U s e the value of G
MCM
obtained in Exercise 9.19 and t h e value of G
obtained from Eq. (9.71) to find
ML
(9.78)
'cl7
the C M R R , that is the ratio of G,„, to G , expressed in decibels. Ans. 70.5 dB 9 21 N'odno that with the c o m m o n - m o d e negative-feedback loop in place the c o m m o n - m o d e gain will MAA
v
bn
- i27UlTU~TZ (R IIRm) + r v
9
(9.79) e l 6
decrease by the amount of feedback, and noting that t h e loop gain is approximately equal to ft (see R
Problem 9.26), find t h e C M R R with the feedback loop in place. (ft, = 50.) Ans. 104.6 dB
= (P +l)(r
m
17
+R)
el7
(9.80)
8
These e q u a t i o n s c a n b e c o m b i n e d to obtain G
= ^ v
M2
9.5.2 The Second Stage F i g u r e 9.24 s h o w s t h e 7 4 1 second stage p r e p a r e d for small-signal analysis. In this section w e shall a n a l y z e t h e second stage to d e t e r m i n e t h e values of t h e p a r a m e t e r s of t h e equivalent
T h e input resistance R
i2
R
.
a
which, for t h e 7 4 1 p a r a m e t e r v a l u e s , is found t o b e G
M2
= 6.5 m A / V .
O u t p u t R e s i s t a n c e T o determine the output resistance R of the second stage in Fig. 9.24, we g r o u n d t h e input t e r m i n a l a n d find t h e resistance l o o k i n g b a c k into t h e o u t p u t terminal. It follows that R is given b y o2
circuit s h o w n in F i g . 9 . 2 5 . Input Resistance
(9.81) j2
= (B
l6
+ l)[r
el6
+
can b e found b y inspection t o b e
R //(P„ + 9
Substituting t h e appropriate p a r a m e t e r v a l u e s yields R
i2
l)(r
e l 7
+ Kg)]
o2
(9-77)
R2 0
^ 4 MQ.
(9-82)
= (ROIIBIIROII)
where R \_ is t h e resistance l o o k i n g into t h e collector of Q connected t o ground. It c a n b e easily seen that 0
B
13B
ROUB
For the 741 c o m p o n e n t values w e obtain R \
0 3B
= r
w h i l e its b a s e a n d emitter are
(9.83)
o i 3 B
= 9 0 . 9 kQ.
T h e second c o m p o n e n t in Eq. (9.82), R , is t h e resistance seen looking into t h e collector of <2n, as indicated i n F i g . 9.26. S i n c e the resistance b e t w e e n t h e b a s e of Q a n d g r o u n d is relatively small, o n e can considerably simplify m a t t e r s b y a s s u m i n g that t h e b a s e is grounded. D o i n g this, w e c a n u s e E q . (9.72) t o d e t e r m i n e R . F o r o u r c a s e t h e result is R = 787 k Q . Combining R and R i n parallel yields R = 81 k Q . oi7
l7
ol7
ol7
ol3B
ol7
o2
T h e v e n i n E q u i v a l e n t C i r c u i t T h e s e c o n d - s t a g e equivalent circuit c a n b e c o n v e r t e d t o the T h e v e n i n form, as s h o w n in F i g . 9 . 2 7 . N o t e that t h e stage o p e n - c i r c u i t v o l t a g e g a i n is ~G R . M2
Ra
O2
FIGURE 9 . 2 4 The 741 second stage prepared for small-signal analysis.
-0C
Bi60—
17
j~
•BE
*WV-
R •
•R,
FIGURE 9 . 2 5 Small-signal equivalent circuit model of the second stage.
FIGURE 9 . 2 6 Definition of R„, . 7
9 1
1
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS
SMALL-SIGNAL ANALYSIS OF THE 741
9.5
H -
-oC,
-AfW
'16 0-
o
(l. K
FIGURE 9 . 2 7 Thevenin form of the small-signal model of the second stage.
9.22 Use Eq. (9.77) to show that R = 4 M O . i2
9.23 U s e E q s . (9.78) to (9.81) to verify that G is 6.5 m A / V . m2
9.24 Verify that R
oZ
=* 81 k O .
9.25 F i n d the. open-circuit voltage gain of the second stage of t h e 7 4 1 . Ans. - 5 2 6 . 5 V/V
9.5.3 The Output Stage T h e 7 4 1 output stage is s h o w n in F i g . 9.28 w i t h o u t t h e short-circuit-protection circuitry. The stage is s h o w n driven b y t h e second-stage transistor Q a n d l o a d e d with a 2 - k O resistance. T h e circuit is of t h e A B class (Section 9.3.5), w i t h t h e n e t w o r k c o m p o s e d of Q , Q , and R p r o v i d i n g t h e bias of t h e output transistors Q a n d Q . T h e u s e of this n e t w o r k rather than t w o d i o d e - c o n n e c t e d transistors in series enables biasing t h e output transistors at a low current (0.15 m A ) i n spite of t h e fact that t h e output devices are three t i m e s as large as the standard devices. This is obtained b y arranging that t h e current in Q is very small a n d thus its V is also small. W e analyzed t h e d c bias in Section 9.4.7. u
ls
10
u
X9
2a
Ro2
°23
Out —o—
-o—
19
•II
BE
+
v
i3
A n o t h e r feature of t h e 741 output stage w o r t h noting is that t h e stage is driven by an emitter f o l l o w e r Q . A s will b e s h o w n , this e m i t t e r f o l l o w e r p r o v i d e s a d d e d buffering, which m a k e s the o p - a m p gain almost independent of t h e parameters of t h e output transistors. 23
O u t p u t V o l t a g e Limits
T h e m a x i m u m positive output voltage is limited b y t h e satura-
tion of current-source transistor Q . T h u s
FIGURE 9 . 2 9 Model for the 741 output stage. This model is based on the amplifier equivalent circuit presented in Table 5.5 as "Equivalent Circuit C."
nA
v
0 m
„ = Vcc - Vcs,* - V
(9-84)
BEU
the open-circuit output v o l t a g e of t h e second stage. F r o m F i g . 9.27, v is g i v e n b y o2
w h i c h is about 1 V b e l o w V . T h e m i n i m u m output v o l t a g e (i.e., m a x i m u m n e g a t i v e ampli-
v
oi
cc
tude) is limited b y t h e saturation of Q . N e g l e c t i n g t h e v o l t a g e d r o p across R , w e obtain l7
s
where G
m2
VOmm = - EE + ^CEsat + V V
EB23
+ V
(9.85)
EB20
tance R
in3
and R
o2
= -G R v m2
o2
(9.86)
i2
w e r e p r e v i o u s l y d e t e r m i n e d as G
m2
= 6.5 m A / V and R
o2
= 8l k O . R e s i s -
i s t h e input resistance of t h e output stage d e t e r m i n e d w i t h t h e amplifier l o a d e d
with A\. A l t h o u g h the effect of loading an amplifier stage o n its input resistance is negligible w h i c h is about 1.5 V a b o v e -V .
m the input a n d s e c o n d stages, this is n o t t h e c a s e i n general in an output stage. Defining 7 ?
Small-Signal M o d e l W e shall n o w carry o u t a small-signal analysis of t h e output stage for t h e p u r p o s e of determining t h e values of t h e p a r a m e t e r s of t h e equivalent circuit model s h o w n in F i g . 9 . 2 9 . N o t e that this m o d e l is b a s e d o n the general amplifier equivalent circuit p r e s e n t e d in T a b l e 5.5 as " E q u i v a l e n t Circuit C . " T h e m o d e l is s h o w n fed b y v , which is
in this m a n n e r ( s e e T a b l e 5.5) enables correct evaluation of t h e voltage gain of t h e s e c o n d
EE
o2
M
stage, A , as 2
V
3
A = ' V
i2
—
r
P
^¡"3
Km3
(9.87)
+K
0
"_
•
913
914
'
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
9.5
CIRCUITS
T o determine R , assume that o n e of t h e t w o output transistors—say, Q —is conducting a current of, say, 5 m A . It follows that t h e input resistance l o o k i n g into t h e b a s e of Q is a p p r o x i m a t e l y P R - A s s u m i n g j5 = 5 0 , for R - 2 k Q t h e input resistance of Q is 100 k Q . T h i s resistance appears i n parallel w i t h t h e series c o m b i n a t i o n of t h e output resistance of Q (r =* 2 8 0 k Q ) and the resistance of the Q Q network. T h e latter resistance is very small (about 160 Q ; s e e later: E x e r c i s e 9.26). T h u s t h e total resistance in the emitter of Q is a p p r o x i m a t e l y ( 1 0 0 k Q / / 2 8 0 k Q ) or 7 4 kQ a n d t h e input resistance R is given b y in3
20
20
20
L
13A
20
L
20
ol3A
lfr
19
23
o2
Q
i4
2Q
out
A s indicated i n Fig. 9.30, t h e resistance seen l o o k i n g into t h e emitter of Q
23
R o2
R
n
& 3 + I kQ
Substituting = 81 k Q , B resistance appears in parallel Q1S-Q19 n e t w o r k . S i n c e r tance b e t w e e n t h e b a s e of Q the output resistance R as
23
w h i c h for / 3 = 5 0 is i v = 3.7 M Q . S i n c e R = 8 1 kQ, w e s e e that R > R , a n d the v a l u e of R will h a v e little effect on t h e p e r f o r m a n c e of t h e o p a m p . W e c a n u s e t h e value obtained for R t o determine the gain of t h e second stage using E q . (9.87) as A = - 5 1 5 V / V . T h e value of A will b e n e e d e d in Section 9.6 in c o n n e c t i o n with t h e frequency-response analysis. 2 3
iD3
o2
m3
o2
in3
in3
2
2
o l 3 A
20
vo3
+ re23
(9.89)
e23
o23
o l 3 A
o23
o23
mt
-^out —
(9.90)
20
is t h e o p e n - c i r c u i t o v e r a l l v o l t a g e g a i n of t h e output stage,
For p = 5 0 , t h e first c o m p o n e n t of R is 3 4 Q . T h e s e c o n d c o m p o n e n t d e p e n d s critically on the value of output current. F o r an output current of 5 m A , r is 5 Q a n d R is 3 9 Q . T o this value w e m u s t a d d t h e resistance A> (27 Q ) (see F i g . 9.13), w h i c h is i n c l u d e d for shortcircuit protection. T h e output resistance of t h e 7 4 1 is specified t o b e typically 7 5 Q . 20
(9.:
is
= 50, and r = 25/0.18 = 139 Q yields R = 1.73 k Q . This with t h e series c o m b i n a t i o n of r a n d the resistance of t h e alone (0.28 M Q ) is m u c h larger than R , t h e effective resisa n d g r o u n d is a p p r o x i m a t e l y equal to R . N o w w e c a n find
C o n t i n u i n g w i t h t h e determination of t h e equivalent circuit-model-parameters, w e note from F i g . 9.29 that G
I 91 5
resistance of t h e s e c o n d stage, R ) is included. W e h a v e a s s u m e d that t h e output voltage v is negative, a n d thus Q20 is c o n d u c t i n g m o s t of t h e current; transistor Q h a s therefore b e e n eliminated. T h e exact value of the output resistance will of course d e p e n d on which transistor (Qu or Q ) is c o n d u c t i n g a n d on the v a l u e of load current. Nevertheless, w e wish t o find an estimate of R .
in3
# i n 3 =* P23 x 7 4
SMALL-SIGNAL ANALYSIS OF THE 741
mt
e2B
mt
7
W i t h R = co, t h e gain of t h e e m i t t e r - f o l l o w e r o u t p u t t r a n s i s t o r (Q or Q ) will b e nearly unity. A l s o , w i t h R = °° t h e r e s i s t a n c e in t h e e m i t t e r of Q will b e v e r y large. T h i s m e a n s that t h e g a i n of Q will b e n e a r l y u n i t y a n d t h e i n p u t r e s i s t a n c e of Q will b e v e r y large. W e thus conclude that G — 1. L
u
L
20
23
23
23
vo3
N e x t , w e shall find t h e value of t h e o u t p u t resistance of t h e o p a m p , R . F o r this p u r p o s e refer to t h e circuit s h o w n in F i g . 9.30. I n a c c o r d a n c e with the definition of R , the input source feeding t h e output stage is g r o u n d e d , b u t its resistance (which is t h e output ovt
0M
9.26 Using a simple ( r . g„.) model for each of the t w o transistors Ç>, and Q in Fig. E9.26, find the small-signal resistance between A and A'. (Nate: From Table 9 . 1 , / = 165 ,uA and l — 16 uA. T
s
o
ïiifcilIIB^ A
Rio = 40 k ü
FIGURE E9.26
FIGURE 9 . 3 0 Circuit for finding the output resistance R<
lv
s
n 9
\j
CHAPTER 9
OPERATIONAL-AMPLIFIER
A N D
DATA-CONVERTER
CIRCUITS
^ ....
Figure E 9 27 shows the circuit for determining the o p - a m p output resistance w h e n v is positive a n 0
Q° is conducting m o s t of the current. U s i n g the resistance of the Q -Q u
ls
Exercise 9.26 and neglecting the large output resistance of Q , 13A
l9
find R
oat
GAIN, FREQUENCY RESPONSE, A N D SLEW RATE OF THE
9.6
network calculated i when Q
u
9.6 GAIN, FREQUENCY RESPONSE, AND SLEW RATE OF THE 741
In this section w e shall evaluate the overall small-signal v o l t a g e gain of the 7 4 1 o p a m p . W e shall t h e n consider t h e o p a m p ' s frequency r e s p o n s e and its slew-rate limitation.
is sourcmg a
output current of 5 m A . Ans. 14.4 Q
9.6.1 Small-Signal Gain T h e overall small-signal gain can b e easily found from the c a s c a d e of the equivalent circuits d e r i v e d in t h e p r e c e d i n g sections for t h e t h r e e o p - a m p stages. T h i s c a s c a d e is s h o w n in F i g . 9 . 3 1 , l o a d e d w i t h R = 2 k Q , w h i c h is t h e typical value u s e d in m e a s u r i n g and specify ing the 7 4 1 data. T h e overall gain can be e x p r e s s e d as L
Vf
V; V
?.91)
V„
n
0
= -G (R //R )(-G R )G ml
ol
i2
n2
o2
\
vo3 K
L
(9.92) K
+
om
U s i n g t h e v a l u e s found earlier yields for t h e overall open-circuit v o l t a g e gain, A = ^ = - 4 7 6 . 1 x ( - 5 2 6 . 5 ) x 0.97 = 2 4 3 , 1 4 7 V / V v,
(9.93)
0
s 107.7 d B
9.6.2 Frequency Response T h e 7 4 1 is an internally c o m p e n s a t e d o p a m p . It e m p l o y s the Miller c o m p e n s a t i o n tech nique, studied in Section 8 J 1.3, to introduce a d o m i n a n t low-frequency p o l e . Specifically, a 30-pF capacitor ( C ) is c o n n e c t e d in the negative-feedback p a t h of t h e s e c o n d stage. A n approximate estimate of the frequency of t h e d o m i n a n t p o l e can b e obtained as follows. c
U s i n g M i l l e r ' s t h e o r e m (Section 6.4.4) the effective c a p a c i t a n c e d u e to C base of Q and g r o u n d is (see Fig. 9.13)
c
b e t w e e n the
16
Cm = C ( 1 + | A | ) C
where A is the second-stage gain. U s e of the value calculated for A in Section 9.5.3, A = - 5 1 5 , results in C- = 15,480 p F . Since this capacitance is quite large, w e shall neglect all other capacitances b e t w e e n t h e b a s e of Q and signal ground. T h e total resistance b e t w e e n this node and g r o u n d is 2
O u t p u t Short-Circuit Protection
If t h e o p - a m p output terminal is short-circuited to
(9.94)
2
2
2
m
one of t h e p o w e r supplies, o n e of t h e t w o output transistors could c o n d u c t a large a m o u n t of current. S u c h a large current can result in sufficient heating to c a u s e b u r n o u t of the IC
l6
( C h a p t e r 14). T o g u a r d against this possibility, t h e 7 4 1 o p a m p is e q u i p p e d w i t h a special circuit for short-circuit protection. T h e function of this circuit is to limit t h e current in the output transistors in the event of a short circuit. R e f e r to F i g . 9 . 1 3 . R e s i s t a n c e R
6
w o u l d flow o u t of Q
u
e m i t t e r of Q
14
R, =
{R IIR ) ol
i2
= ( 6 . 7 M Q / / 4 M Q ) = 2.5 M Q
t o g e t h e r w i t h transistor Q
15
(9.95)
limits t h e current that
in t h e e v e n t of a short circuit. Specifically, if t h e c u r r e n t in the
e x c e e d s a b o u t 2 0 m A , t h e v o l t a g e d r o p across R e x c e e d s 5 4 0 m V , which 6
t u r n s 2 i 5 on. A s Q
l5
turns on, its c o l l e c t o r r o b s s o m e of t h e c u r r e n t s u p p l i e d b y Q , 13A
r e d u c i n g t h e b a s e current of Q . u
thus
T h i s m e c h a n i s m t h u s limits t h e m a x i m u m current that
t h e o p a m p c a n s o u r c e (i.e., s u p p l y f r o m t h e o u t p u t t e r m i n a l in t h e o u t w a r d direction) to about 20 mA. L i m i t i n g of the m a x i m u m current that t h e o p a m p c a n sink, and h e n c e t h e current t h r o u g h Q , is d o n e b y a m e c h a n i s m similar to t h e o n e discussed a b o v e . T h e relevant circuit 20
is c o m p o s e d of R , Q , 7
21
Q, 24
and Q . 22
F o r t h e c o m p o n e n t s s h o w n , the current in the inward
direction is limited also to about 2 0 m A .
FIGURE 9 . 3 1 Cascading the small-signal equivalent circuits of the individual stages for the evaluation of the overall voltage gain.
741
CHAPTER 9
OPERATIONAL-AMPLIFIER
\A\
A
0
A N D
DATA-CONVERTER
CIRCUITS
9.6
GAIN, FREQUENCY
RESPONSE, A N D SLEW RATE OF THE 741
(dB)|
= 107.7 dB
+
+ 20 d B / d e c a d e
FIGURE 9 . 3 3
0 FIGURE 9 . 3 2
/
3 d B
= 4.1Hz
f
i
=
A o
f
3 i B
=
gain of the s e c o n d stage is a s s u m e d sufficiently large that a virtual g r o u n d appears at its input. F o r this r e a s o n t h e output resistance of t h e input stage and t h e input resistance of the second stage h a v e b e e n omitted. F u r t h e r m o r e , the output stage is a s s u m e d to b e an ideal unity-gain follower. E x c e p t for the p r e s e n c e of the output stage, this m o d e l is identical to that w h i c h w e u s e d for the t w o - s t a g e C M O S amplifier in Section 9.1.4 (Fig. 9.3). Analysis of the m o d e l in F i g . 9.33 gives
1 MHz
Bode plot for the 741 gain, neglecting nondominant poles.
T h u s the d o m i n a n t p o l e has a frequency f
P
A simple model for the 741 based on modeling the second stage as an integrator.
given by ml
1 fp
(9.96)
= 4.1 H z
2nC R,
(9.99)
sC
r
Thus,
in
It s h o u l d b e n o t e d t h a t this a p p r o a c h is e q u i v a l e n t t o u s i n g t h e a p p r o x i m a t e f o r m u l a in A(jco)
Eq. (8.87).
= ~ J®C
?.100) C
A s discussed in Section 8.11.3, Miller c o m p e n s a t i o n p r o v i d e s an additional advanta g e o u s effect, n a m e l y p o l e splitting. A s a result, the other poles of t h e circuit are m o v e d to
and t h e m a g n i t u d e of gain b e c o m e s unity at 00 - co , w h e r e t
very h i g h frequencies. This h a s b e e n c o n f i r m e d b y c o m p u t e r - a i d e d analysis [see G r a y et al (9.101)
(2000)]. A s s u m i n g that all n o n d o m i n a n t poles are at v e r y h i g h frequencies, the calculated values give rise to the B o d e plot shown in Fig. 9.32 w h e r e /
3 d B
=f . P
T h e unity-gain bandwidth / , can
Substituting G
ml
= 1/5.26 m A / V and C = 3 0 p F yields c
b e calcitlated from
/, = ^
(9.97) Thus, f = 243,147x4.1 = 1 MHz t
(9.98)
A l t h o u g h this B o d e plot implies that the p h a s e shift a t / , is - 9 0 ° and thus that t h e phase m a r g i n is 9 0 ° , in practice a p h a s e m a r g i n of about 80° is obtained. T h e excess p h a s e shift (about 10°) is d u e to the n o n d o m i n a n t p o l e s . T h i s p h a s e m a r g i n is sufficient to p r o v i d e stable operation of closed-loop amplifiers w i t h any value of f e e d b a c k factor ft. This c o n v e n i e n c e of u s e of t h e internally c o m p e n s a t e d 7 4 1 is a c h i e v e d at the e x p e n s e of a great reduction in o p e n - l o o p gain and h e n c e in t h e a m o u n t of n e g a t i v e feedback. In other w o r d s , if o n e requires a closed-loop amplifier with a gain of 1000, t h e n the 7 4 1 is overcompensated for such an application, and o n e w o u l d b e m u c h better off designing o n e ' s o w n compensation (assuming, of course, the availability of an o p a m p that is not already internally c o m p e n s a t e d ) .
9.6.3 A Simplified Model c
(9.102)
which is e q u a l to the value calculated before. It should be p o i n t e d out, h o w e v e r , that this model is valid only at f r e q u e n c i e s / >f . A t s u c h frequencies the gain falls off with a slope of - 2 0 d B / d e c a d e , j u s t like that of an integrator. 3dB
9.6.4 Slew Rate The slew-rate limitation of o p a m p s is discussed in C h a p t e r 2. H e r e w e shall illustrate t h e origin of the s l e w i n g p h e n o m e n o n in the c o n t e x t of the 7 4 1 circuit. Consider t h e unity-gain follower of F i g . 9.34 with a step of, say, 10 V applied at t h e input. B e c a u s e of amplifier d y n a m i c s , its output will not c h a n g e in zero t i m e . T h u s i m m e d i ately after the input is applied, almost t h e entire value of t h e step will appear as a differential signal b e t w e e n t h e t w o input terminals. This large input voltage causes t h e input stage to b e o v e r d r i v e n , and its small-signal m o d e l n o l o n g e r applies. Rather, half the stage cuts off and the other half c o n d u c t s all the current. Specifically, reference to F i g . 9.13 shows that a large positive differential input v o l t a g e causes Q and Q to c o n d u c t all the available bias current (21) while 0 2 a n d g will b e cut off. T h e current mirror Q , Q , and Q will still function, and Q will p r o d u c e a collector current of 21. x
F i g u r e 9.33 s h o w s a simplified m o d e l of the 7 4 1 o p a m p in w h i c h the h i g h - g a i n second stage, w i t h its feedback capacitance C , is m o d e l e d b y an ideal integrator. In this m o d e l , the
= 1 MHz
2K
4
6
3
5
6
n
$
.C
919
92t
CHAPTER 9
9.6
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS
GAIN, FREQUENCY RESPONSE, A N D SLEW RATE OF T H E 741
w h e r e r is the emitter resistance of e a c h of Q t h r o u g h Q . T h u s e
V
0
4
~"°'N
i
+ 10
x
V
and
Vo
C
t
FIGURE 9 . 3 4 A unity-gain follower with a large step input. Since the output voltage cannot change instanta neously, a large differential voltage appears between the op-amp input terminals.
1
-
(9.105)
Substituting in E q . (9.101) results in co,
-
' Substituting for 7 / C
c
(9.106)
— - —
2C VV C
from E q . (9.104) gives SR CO, = -jjf
I '.107)
4V
T
0
la
which can b e e x p r e s s e d in the alternative f o r m V
4V co,
SR =
:
.108)
T
As a check, for t h e 7 4 1 w e h a v e 3
SR = 4 x 2 5 x 1 0 " x 2n x 1 0
FIGURE 9 . 3 5 Model for the 741 op amp when a large positive differential signal is applied.
6
= 0.63 V / t i s
which is the result obtained previously. Observe that Eq. (9.108) is of the same form as U s i n g t h e observations a b o v e , and m o d e l i n g t h e s e c o n d stage as an ideal integrator,
Eq. (9.41), w h i c h applies to the two-stage C M O S o p a m p . Here, 4V replaces V . T
ov
Since, typi
results in t h e m o d e l of Fig. 9.35. F r o m this circuit w e see that the output v o l t a g e will be a
cally, V
r a m p w i t h a slope of
equal to that of the 7 4 1 exhibits a slew rate that is t w o to three times as large as that of the 7 4 1 .
2I/C : C
ov
will b e t w o to three times the value of 4V , a two-stage C M O S o p a m p with an f T
t
A general f o r m for the relationship b e t w e e n SR and co, for an o p a m p with a structure v {t) 0
= prf
(9.103)
similar to that of the 7 4 1 (including the t w o - s t a g e C M O S circuit) is SR -
T h u s t h e slew rate SR is given b y
co/a
where a is t h e constant of proportionality relating the t r a n s c o n d u c t a n c e of the first s t a g e (9.104)
G , to the total bias current of t h e input differential stage. T h a t is, for the 7 4 1 circuit G m l
a(2I), w h i l e for t h e C M O S circuit of Fig. 9 . 1 , G
ml
F o r t h e 7 4 1 , 1 = 9.5 ttA and C = 3 0 p F , resulting in SR = 0.63 V / i t s . c
It should b e pointed out that this is a rather simplified m o d e l of t h e s l e w i n g process. M o r e detail c a n b e found in G r a y et al ( 2 0 0 0 ) .
= al?
m l
=
F o r a g i v e n co„ a h i g h e r v a l u e of SR
is obtained b y m a k i n g a smaller; that is, the total bias current is k e p t constant and G
m l
Is
reduced. This is a viable technique for increasing slew rate. It is referred to as the G - r e d u c t i o n m
method (see E x e r c i s e 9.30).
EXERCISES 9.28 Use the value of the slew rate calculated above to find the full-power b a n d w i d t h / ; , of the 741 op amp.
9.29 Consider the integrator model o § t h e op amp in Fig. 9.33. Find the value of the resistor that, when con nected across C . provides the correct value of the dc gain.
Assume that the m a x i m u m output is ±10 V.
c
Ans. 1 M < )
Ans. in k l l /
09,30 If a resistance R is included in each of the emitter leads of g? and Q, show that 57? = 4 ( V + Ä p ' 2 ) s ß p Hence find the value of R that would double the 741 slew rate while keeping co, and /unehanged?;What are the new values of C,-, the dc gain, and the 3-dB frequency? E
r
F
9.6.5 Relationship Between f and S R t
Ans. 5.26 kil: 15 pF; .1.01.7 dB (a 6-dB decrease); 8.2 Hz
A s i m p l e relationship exists b e t w e e n t h e u n i t y - g a i n b a n d w i d t h f, and t h e slew rate SR. relationship is obtained from E q s . (9.101) and (9.104) together w i t h The difference is just a matter of notation; we used I to denote the total bias current of the input differential stage of the CMOS circuit, and we used 21 for the 741 case!
9 2 1
922
'
"
CHAPTER 9
O P E R A T I O N A L - A M P L I F I E R A N D D A T A - C O N V E R T E R CIRCUITS
9.7
9.7
DATA CONVERTERS—AN INTRODUCTION
DATA CONVERTERS-AN INTRODUCTION
In this section w e b e g i n the study of another g r o u p of analog I C circuits of great importance; n a m e l y , d a t a converters.
9.7.1 Digital Processing of Signals M o s t physical signals, such as t h o s e obtained at transducer outputs, exist in analog form. S o m e of the p r o c e s s i n g required on these signals is m o s t conveniently p e r f o r m e d in an a n a l o g fashion. F o r instance, in instrumentation systems it is quite c o m m o n to u s e a highi n p u t - i m p e d a n c e , high-gain, h i g h - C M R R differential amplifier right at the output of the transducer. T h i s is usually followed b y a filter w h o s e p u r p o s e is to eliminate interference. H o w e v e r , further signal p r o c e s s i n g is usually required, w h i c h c a n r a n g e from simply obtain ing a m e a s u r e m e n t of signal strength to p e r f o r m i n g s o m e algebraic m a n i p u l a t i o n s on this and related signals to obtain the v a l u e of a particular s y s t e m p a r a m e t e r of interest, as is usu ally t h e c a s e in systems intended to p r o v i d e a c o m p l e x control function. A n o t h e r e x a m p l e of signal p r o c e s s i n g can be found in the c o m m o n need for transmission of signals to a remote receiver.
,
M a n y such forms of signal processing c a n b e performed b y analog m e a n s . In earlier chapters w e e n c o u n t e r e d circuits for i m p l e m e n t i n g a n u m b e r of such tasks. H o w e v e r , an attractive alternative exists: It is to convert, following s o m e initial analog processing, the signal from analog to digital form a n d t h e n u s e e c o n o m i c a l , accurate, and c o n v e n i e n t digital ICs to p e r f o r m d i g i t a l s i g n a l p r o c e s s i n g . S u c h p r o c e s s i n g can in its simplest f o r m provide us w i t h a m e a s u r e of the signal strength as an easy-to-read n u m b e r (consider, e.g., t h e digital voltmeter). In m o r e i n v o l v e d cases the digital signal processor can perform a variety of arithmetic and logic operations that i m p l e m e n t a f i l t e r i n g a l g o r i t h m . T h e resulting d i g i t a l f i l t e r d o e s m a n y of the s a m e tasks that an a n a l o g filter p e r f o r m s — n a m e l y , eliminate inter ference and noise. Y e t another e x a m p l e of digital signal p r o c e s s i n g is found in digital com m u n i c a t i o n s s y s t e m s , w h e r e signals are transmitted as a s e q u e n c e of binary p u l s e s , with the o b v i o u s a d v a n t a g e that corruption of the a m p l i t u d e s of these pulses by noise is, to a large extent, of n o c o n s e q u e n c e . O n c e digital signal p r o c e s s i n g h a s b e e n performed, w e m i g h t b e content to display the result in digital form, such as a printed list of n u m b e r s . Alternatively, w e m i g h t require an analog output. S u c h is t h e c a s e in a t e l e c o m m u n i c a t i o n s system, w h e r e t h e u s u a l output may b e audible speech. If such an analog o u t p u t is desired, t h e n o b v i o u s l y w e n e e d to convert the digital signal b a c k to an analog form.
FIGURE 9 . 3 6 The process of periodically sampling an analog signal, (a) Sample-and-hold (S/H) circuit. The switch closes for a small part (T seconds) of every clock period (T). (b) Input signal waveform, (c) Sam pling signal (control signal for the switch), (d) Output signal (to be fed to A/D converter).
It is not our p u r p o s e h e r e to study the t e c h n i q u e s of digital signal p r o c e s s i n g . Rather, we shall e x a m i n e the interface circuits b e t w e e n t h e a n a l o g and digital d o m a i n s . Specifically, we shall study t h e basic techniques a n d circuits e m p l o y e d to convert an analog signal to digital f o r m ( a n a l o g - t o - d i g i t a l o r s i m p l y A / D c o n v e r s i o n ) a n d t h o s e u s e d to c o n v e r t a digital s i g n a l t o a n a l o g form. ( d i g i t a J - t o - a n a l o g or s i m p l y D / A c o n v e r s i o n ) . D i g i t a l c i r c u i t s are studied in C h a p t e r s 10 and 1 1 .
stored (held) o n t h e capacitor. T h e circuit of F i g . 9.36 is k n o w n as a s a m p l e - a n d - h o l d (S/H) c i r c u i t . A s indicated, the S/H circuit consists of an analog switch that can b e i m p l e m e n t e d by a M O S F E T t r a n s m i s s i o n gate (Section 10.5), a storage capacitor, and (not s h o w n ) a buffer amplifier.
9.7.2 Sampling of Analog Signals T h e principle u n d e r l y i n g digital signal p r o c e s s i n g is that of s a m p l i n g t h e analog signal. F i g u r e 9.36 illustrates in a c o n c e p t u a l form t h e p r o c e s s of obtaining s a m p l e s of an analog signal. T h e switch s h o w n closes periodically u n d e r the control of a periodic p u l s e signal (clock). T h e closure t i m e of the switch, T, is relatively short, and t h e s a m p l e s obtained are
B e t w e e n the s a m p l i n g intervals—that is, during the hold i n t e r v a l s — t h e voltage level on the capacitor represents the signal s a m p l e s w e are after. E a c h of these voltage levels is t h e n fed to the input of an A / D converter, w h i c h p r o v i d e s an TV-bit binary n u m b e r proportional to the value of signal s a m p l e . T h e fact that w e can d o our p r o c e s s i n g o n a limited n u m b e r of samples of an a n a l o g signal w h i l e i g n o r i n g the analog-signal details b e t w e e n s a m p l e s is b a s e d on the S h a n n o n ' s sampling t h e o r e m [see Lathi ( 1 9 6 5 ) ] .
-
923
CHAPTER 9
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D/A CONVERTER CIRCUITS
9.8
$¿1}
low-pass filter, giving rise t o t h e s m o o t h c u r v e s h o w n i n color in F i g . 9 . 3 8 . In this WE
9.7.3 Signal Quantization C o n s i d e r an analog signal w h o s e v a l u e s r a n g e f r o m 0 t o + 1 0 V . L e t u s a s s u m e that w e w i s h 4
to c o n v e r t this signal t o digital f o r m and that t h e r e q u i r e d output is a 4-bit digital s i g n a l . W e
analog output signal is reconstructed. Finally, n o t e that t h e q u a n t i z a t i o n error of an A / D verier is e q u i v a l e n t t o ± 1 least significant bit (b ). N
k n o w that a 4-bit b i n a r y n u m b e r c a n r e p r e s e n t 16 different v a l u e s , 0 t o 15; it follows that the resolution
of o u r c o n v e r s i o n will b e 10 V / 1 5 = | V . T h u s an a n a l o g signal of 0 V will b e
r e p r e s e n t e d b y 0 0 0 0 , \ V will b e r e p r e s e n t e d by 0 0 0 1 , 6 V will b e r e p r e s e n t e d b y 1 0 0 1 , and 10 V will b e r e p r e s e n t e d b y 1 1 1 1 .
9.31 An analog signal in the range 0 to + 1 0 V is to be converted to an 8-bit digital signal. What is the resolution of the conversion in volts? What is the digital representation of an input of 6 V? What is the representation of an input of 6.2 V ? W h a t i s the error made in:the quantization of 6.2 V in absolute terms and a> WA.. a percentage ofithe input? As a percentage of lull scale? W h a t is the largest possible quantization erroi as a percentage of full scale?
A l l t h e s e s a m p l e n u m b e r s a r e m u l t i p l e s of t h e b a s i c i n c r e m e n t ( | V ) . A q u e s t i o n n o w arises r e g a r d i n g t h e c o n v e r s i o n of n u m b e r s that fall b e t w e e n t h e s e successive i n c r e m e n t a l levels. F o r instance, consider the case of a 6 . 2 - V a n a l o g level. T h i s falls b e t w e e n 1 8 / 3 and 2 0 / 3 . H o w e v e r , since it is closer to 1 8 / 3 w e treat it as if it w e r e 6 V a n d code it as 1 0 0 1 . This p r o c e s s is called q u a n t i z a t i o n . O b v i o u s l y errors are inherent in this p r o c e s s ; such errors are
Ans. 0.0392 V; 10011001; 1 0 0 1 1 1 1 0 ; - 0 . 0 0 6 4 V : - 0 , 1 % ; - 0 . 0 6 4 % : 0.196 /r c
called q u a n t i z a t i o n errors. U s i n g m o r e bits t o r e p r e s e n t ( e n c o d e or, simply, c o d e ) a n analog signal r e d u c e s quantization errors b u t requires m o r e c o m p l e x circuitry.
9.7.4 The A / D and D/A Converters as Functional Blocks
-
9.8 D/A CONVERTER CIRCUITS
F i g u r e 9.37 depicts the functional b l o c k representations of A / D and D / A converters. A s indicated, t h e A / D c o n v e r t e r (also called an A D C ) accepts an analog s a m p l e v a n d p r o d u c e s an A
TV-bit digital w o r d . C o n v e r s e l y , t h e D / A c o n v e r t e r (also called a D A C ) a c c e p t s an n-bit digital w o r d a n d p r o d u c e s an a n a l o g s a m p l e . T h e output s a m p l e s of t h e D / A converter are often fed to a s a m p l e - a n d - h o l d circuit. A t t h e output of t h e S/H circuit a staircase waveform,
9.8.1 Basic Circuit Using Binary-Weighted Resistors Figure 9.39 s h o w s a s i m p l e circuit for an TV-bit D / A converter. T h e circuit consists of a reference voltage VREF, TV b i n a r y - w e i g h t e d resistors R, 2R, 4R, 8R, . . . , 2 ~ R, N single-pole d o u b l e - t h r o w s w i t c h e s S S , • • . , S , a n d an o p a m p t o g e t h e r w i t h its f e e d b a c k resistance R = R/2. N
lt
such as that i n F i g . 9 . 3 8 , is obtained. T h e staircase w a v e f o r m c a n then b e s m o o t h e d by a
2
l
N
f
TV-bit digital word
T h e s w i t c h e s a r e controlled b y an TV-bit digital i n p u t w o r d D,
D
\
o-
1)
iiiinenei
-o 1 -o 2 -o 3
=
hh +
2 0
&
3
O
where b
u
+
...
2-
+
hi
.
(9 109) N
2
b , a n d so o n are bit coefficients that a r e either 1 o r 0. N o t e that t h e bit b 2
N
least significant bit ( L S B ) a n d b
Y
Fig. 9.39, b controls switch S {
FIGURE 9 . 3 7 The A/D and D/A converters as circuit blocks.
1
u
is t h e
is t h e m o s t significant b i t ( M S B ) . In t h e circuit in
b controls S , a n d so o n . W h e n b is 0, switch S is in p o s i 2
2
t
t
tion 1, and w h e n b is 1 switch 5,- is in position 2. (
Since position 1 of all switches is g r o u n d a n d position 2 is virtual g r o u n d , t h e current through e a c h resistor r e m a i n s constant. E a c h switch simply controls w h e r e its c o r r e s p o n d i n g current g o e s : t o g r o u n d ( w h e n t h e c o r r e s p o n d i n g bit is 0) or t o virtual g r o u n d ( w h e n t h e corr e s p o n d i n g bit is 1). T h e currents flowing i n t o t h e virtual g r o u n d a d d u p , a n d the s u m flows
FIGURE 9 . 3 8 The analog samples at the output of a D/A converter are usually fed to a sample-and-hold circuit to obtain the staircase waveform shown. This waveform can then be filtered to obtain the smooth waveform, shown in color. The time delay usually introduced by the filter is not shown.
4
Bit stands for Mnary dig;'?.
FIGURE 9 . 3 9 An TV-bit D/A converter using a binary-weighted resistive ladder network.
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CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
9.8
CIRCUITS
CIRCUITS
resistance to t h e right of e a c h l a d d e r n o d e , s u c h as that labeled X , is equal to 27?. T h u s the
t h r o u g h t h e f e e d b a c k resistance R . T h e total current i is therefore given b y F
D/A CONVERTER
0
current flowing to t h e right, a w a y from e a c h m o d e , is e q u a l to the current flowing d o w n w a r d to ground, a n d t w i c e that current flows into the n o d e from the left side. It follows that 1
R
N L
27?
2'R
7 2VREFpi
b
W
2
R
2
1
27 = 4 7 = -
=
2
•
3
bji
+
Z
(9.112)
*N
+
2
T h u s , as in the b i n a r y - w e i g h t e d resistive n e t w o r k , the currents controlled b y the switches
N
2
are binary w e i g h t e d . T h e o u t p u t current i will therefore b e given b y 0
Thus, D
REF
(9.110)
7? and the output voltage v
0
is g i v e n b y v
0
D
(9.113)
7?
9.8.3 A Practical Circuit Implementation = -i R 0
f
= -V D
(9.111)
}m
w h i c h is directly p r o p o r t i o n a l to t h e digital w o r d D, as desired.
A practical circuit implementation of the D A C utilizing an 7?-27? ladder is s h o w n in Fig. 9 . 4 1 . T h e circuit utilizes B J T s to g e n e r a t e b i n a r y - w e i g h t e d constant currents / , , 7 , . . . , I , w h i c h 2
It should b e noted that the accuracy of the D A C d e p e n d s critically on (1) the accuracy of V r e f , (2) the precision of the b i n a r y - w e i g h t e d resistors, and (3) the perfection of t h e switches.
W e shall first s h o w that t h e currents I to I
R e g a r d i n g the third point, w e should e m p h a s i z e that these switches h a n d l e analog signals;
ing to the M S B a n d 7^ c o r r e s p o n d i n g to t h e L S B of the D A C .
thus their perfection is of considerable interest. W h i l e the offset v o l t a g e and the finite on
N
are switched b e t w e e n g r o u n d and virtual g r o u n d of an o u t p u t s u m m i n g o p a m p (not s h o w n ) . x
N
are i n d e e d b i n a r y - w e i g h t e d , w i t h I
x
Starting at t h e t w o r i g h t m o s t transistors, Q
correspond
a n d Q), w e see that if they are m a t c h e d , their
N
resistance are n o t of critical significance in a digital switch, these p a r a m e t e r s are of i m m e n s e
emitter currents will b e e q u a l a n d are d e n o t e d (I /d).
i m p o r t a n c e in analog
proper t e r m i n a t i o n of t h e 7?-27? n e t w o r k . T h e v o l t a g e b e t w e e n the b a s e line of the B I T s a n d
switches.
T h e u s e of M O S F E T s to i m p l e m e n t analog switches will b e
discussed in C h a p t e r 10. Also, w e shall shortly see that in practical circuit i m p l e m e n t a t i o n s of
Transistor Q, is i n c l u d e d to p r o v i d e
N
node N will b e
the D A C , the b i n a r y - w e i g h t e d currents are g e n e r a t e d b y current sources. I n this case the analog switch can b e realized u s i n g t h e differential-pair circuit, as will b e s h o w n shortly.
V
N
=
VBE +{^\(2R) n
A d i s a d v a n t a g e of t h e b i n a r y - w e i g h t e d resistor n e t w o r k is that for a large n u m b e r of bits (TV > 4 ) t h e spread b e t w e e n the smallest a n d largest resistances b e c o m e s q u i t e large. This
To virtual ground of output op amp
i m p l i e s difficulties in m a i n t a i n i n g a c c u r a c y in resistor v a l u e s . A m o r e c o n v e n i e n t scheme exists utilizing a resistive n e t w o r k called t h e 7?-27? ladder.
cv
9.8.2 R-2R Ladders F i g u r e 9.40 s h o w s the basic a r r a n g e m e n t of a D A C u s i n g an R-2R
c\
9 5i
VW 9
ladder. B e c a u s e of the
o
o
c\
9S
o \ s
2
3
small spread in resistance values, this n e t w o r k is u s u a l l y preferred to the b i n a r y - w e i g h t e d s c h e m e d i s c u s s e d earlier, especially for N>4.
O p e r a t i o n of t h e #-27? l a d d e r is straightfor
w a r d . First, it c a n b e s h o w n , b y starting from t h e right a n d w o r k i n g t o w a r d the left, that the so
A sO V
fQl
l^gREF
fQl
B
j^g
3
j^g.V
1 fQs
fQ
t
S
^ A,
h
^REF w
h
«
y
2R
'iI
a
|
2Re 2R.
2R", R
a
a
R AAA
R ^ V W
a
2R •
R N
-s-
a
• wv 1 - =2IN — N a
To op amp virtual ground
to FIGURE 9 . 4 0 The basic circuit configuration of a DAC utilizing an R-2R ladder network.
FIGURE 9 . 4 1
A practical circuit implementation of a DAC utilizing an R-2R ladder network.
asm,
9 2 7
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS
9.9
where V is the b a s e - e m i t t e r v o l t a g e of Q . S i n c e t h e current flowing t h r o u g h the resistor R c o n n e c t e d to n o d e TV is (2I /a), t h e v o l t a g e b e t w e e n n o d e B and n o d e (TV - 1) will be BE
N
N
^*
+
mr
BEN
I
ms
B I A S
N
N
V
N
N
X
N
BE
I =2I L
2
= 4I
N
= ---
3
= 2 -%
(9.114)
u n d e r t h e a s s u m p t i o n that the E B J areas of Q to Q are scaled in a b i n a r y - w e i g h t e d fashion. N e x t consider o p a m p A w h i c h , together with the reference transistor <2REF, forms a negative-feedback loop. ( C o n v i n c e yourself that the feedback is indeed negative.) A virtual g r o u n d appears at t h e collector of QREF forcing it to c o n d u c t a collector current I = VRJEF/RREF i n d e p e n d e n t of w h a t e v e r imperfections <2REF m i g h t h a v e . N o w , if Q and Q are m a t c h e d , their collector currents will b e equal, l
m
mr
The current switch of Fig. 9.42 is s i m p l e a n d features h i g h - s p e e d operation. It suffers, however, from the fact that part of t h e current 7 flows t h r o u g h t h e b a s e of Q and thus does not appear on t h e o u t p u t s u m m i n g line. M o r e e l a b o r a t e circuits for current switches c a n be found in G r e b e n e (1984). A l s o , in a B i C M O S t e c h n o l o g y t h e differential-pair transistors Q and Q can b e r e p l a c e d with M O S F E T s , t h u s e l i m i n a t i n g t h e b a s e current p r o b l e m . m
ms
ms
mr
EXERCISES 9.32 What.is the m a x i m u m resistor ratio required by a 12-bit D/A converter utilizing a binary-weighted resistor network? Ans. 2048
m v
R E F
=
ms
ms
N
h
h
ms
m
BEN
N
B
m
m
A s s u m i n g , for the m o m e n t , that V = V , w e see that a v o l t a g e of (4I /a)R appears across t h e resistance 2R in the emitter of Q _ T h u s Q _ will h a v e an emitter current of (2I /a) and a collector current of (2I ), t w i c e t h e current in Q . T h e t w o transistors will have equal V drops if their j u n c t i o n areas are scaled in t h e s a m e proportion as their currents, w h i c h is usually d o n e in practice. P r o c e e d i n g in t h e m a n n e r a b o v e w e c a n s h o w that
l
9.33 If the input bias current of an op amp, used as the output summer in a 10-bit DAC. is to be no more than that equivalent to 1 E S B . what is the m a x i m u m current required to flow in R, for an op amp whose bias current is as great as 0.5 ziA?
IREP
Ans. 2.046 m A
T h u s , t h e b i n a r y - w e i g h t e d currents are directly related to t h e reference current, independent of the exact values of V
BE
and a. A l s o o b s e r v e that o p a m p A , supplies the b a s e currents of
all the B J T s .
; 9.9
9.8.4 Current Switches E a c h of t h e single-pole d o u b l e - t h r o w switches in t h e D A C circuit of F i g . 9.41 can b e imple m e n t e d b y a circuit such as that s h o w n in F i g . 9.42 for switch S . Here I denotes the current flowing in the collector of t h e mth-bit transistor. T h e circuit is a differential pair with the m
m
A / D CONVERTER CIRCUITS
There exist a n u m b e r of A / D c o n v e r s i o n t e c h n i q u e s v a r y i n g in c o m p l e x i t y and speed. W e shall discuss four different a p p r o a c h e s : t w o s i m p l e , b u t slow, s c h e m e s , o n e c o m p l e x (in terms of the a m o u n t of circuitry required) b u t e x t r e m e l y fast m e t h o d , and, finally, a m e t h o d particularly suited for M O S i m p l e m e n t a t i o n .
io
9.9.1 The Feedback-Type Converter Figure 9.43 s h o w s a s i m p l e AID converter that e m p l o y s a c o m p a r a t o r , an u p / d o w n counter, and a D / A converter. T h e c o m p a r a t o r circuit p r o v i d e s an o u t p u t that a s s u m e s one of t w o
Analog input o -
FIGURE 9 . 4 2 Circuit implementation of switch S in the DAC of Fig. 9.41. In a BiCMOS technology, Qm and Q can be implemented using MOSFETs, thus avoiding the inaccuracy caused by the base current of BJTs.
Differential comparator
Up/down control
Up/down counter
m
mr
!
base of the reference transistor Q c o n n e c t e d t o a suitable d c v o l t a g e V IAS> and the digital signal representing the mth bit b applied to t h e b a s e of t h e o t h e r transistor Q . If the volt age representing b is h i g h e r than V b y a few h u n d r e d millivolts, Q will turn on and q will turn off. T h e bit current I will flow t h r o u g h Q a n d o n t o the output s u m m i n g line. On the other h a n d , w h e n b is l o w , Q will b e off a n d I will flow t h r o u g h Q to ground. m
" » - . - " » -
A / D CONVERTER CIRCUITS
FIGURE 9 . 4 3
A simple feedback-type A/D converter.
Clock . 1 -o 2 TV-bit •o 3 •digital output
9 2 9
930
StVS
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS 9.9
A / D CONVERTER CIRCUITS
distinct v a l u e s : p o s i t i v e w h e n t h e difference input signal is positive, a n d n e g a t i v e when the difference input signal is n e g a t i v e . W e shall study c o m p a r a t o r circuits in C h a p t e r 13. A n u p / d o w n counter is simply a c o u n t e r that c a n c o u n t either u p o r d o w n d e p e n d i n g o n the b i n a r y level applied at its u p / d o w n control t e r m i n a l . B e c a u s e t h e A7D c o n v e r t e r of Fig. 9.43 e m p l o y s a D A C i n its f e e d b a c k loop it is usually called a f e e d b a c k - t y p e A / D converter. It operates as follows: W i t h a 0 c o u n t in t h e counter, t h e D / A c o n v e r t e r output, v , will b e zero 0
and t h e output of t h e c o m p a r a t o r will b e h i g h , instructing the c o u n t e r to c o u n t t h e clock
C
p u l s e s in t h e u p direction. A s t h e c o u n t i n c r e a s e s , t h e output of t h e D A C rises. T h e process continues until t h e D A C output r e a c h e s t h e value of t h e a n a l o g input signal, at w h i c h point
+ F
VAQ
S
o
v
R E F
F
e q u i v a l e n t of t h e i n p u t a n a l o g v o l t a g e . O p e r a t i o n of t h e converter of F i g . 9.43 is slow if it starts from zero. T h i s converter h o w -
>F Vl
V W
t h e c o m p a r a t o r switches a n d stops t h e counter. T h e counter output will t h e n b e t h e digital
ever, tracks i n c r e m e n t a l c h a n g e s in t h e i n p u t signal quite rapidly.
Comparator
9.9.2 The Dual-Slope A / D Converter
ob ~ x
A v e r y p o p u l a r h i g h - r e s o l u t i o n ( 1 2 - t o 14-bit) (but slow) A / D c o n v e r s i o n s c h e m e is illustrated in F i g . 9.44. T o s e e h o w it o p e r a t e s , refer t o F i g . 9.44 a n d a s s u m e that t h e analog i n p u t signal v is n e g a t i v e . P r i o r t o t h e start of t h e c o n v e r s i o n cycle, s w i t c h S is closed, A
ob
2
l miiiiil lode
2
> Output
Counter
t h u s d i s c h a r g i n g c a p a c i t o r C and setting v = 0. T h e c o n v e r s i o n c y c l e b e g i n s w i t h opening x
°
S a n d c o n n e c t i n g t h e integrator i n p u t t h r o u g h s w i t c h S t o t h e a n a l o g i n p u t signal. S i n c e v 2
x
A
Start/Stop o -
is n e g a t i v e , a current I = v /R will flow t h r o u g h R in t h e direction a w a y f r o m t h e integrator. A
T h u s v rises linearly w i t h a slope of I/C = v /RC, x
__NN_
as i n d i c a t e d in F i g . 9.44(b). Simulta-
A
Clock
n e o u s l y , t h e c o u n t e r is e n a b l e d a n d it c o u n t s t h e p u l s e s f r o m a fixed-frequency clock. This (a)
p h a s e of t h e c o n v e r s i o n p r o c e s s c o n t i n u e s for a fixed d u r a t i o n T . It e n d s w h e n t h e counter x
h a s a c c u m u l a t e d a fixed c o u n t d e n o t e d n ^ . U s u a l l y , for an TV-bit converter, n ^ p = 2 . N
Denoting the p e a k voltage at the output of the integrator as V
P E A
k»
w
e
c
a
n
w r
i t e with reference
to F i g . 9.44(b) V
PEAK _
A
T
(9.115)
RC
x
A t t h e e n d of this p h a s e , t h e counter is reset t o zero. P h a s e II of t h e c o n v e r s i o n b e g i n s att=T
Fixed 1 _ V r e f
b y c o n n e c t i n g t h e integrator input through
x
slope J
t o t h e positive reference v o l t a g e V ^ p . T h e current into t h e integrator reverses
switch
RC
T h u s v decreases linearly with a slope of ( V r e p / R C ) . Simul-
direction and is equal to V /R. WF
x
taneously t h e counter is e n a b l e d a n d it c o u n t s t h e pulses from t h e fixed-frequency clock. W h e n v r e a c h e s zero volts, t h e c o m p a r a t o r signals t h e control logic t o stop t h e counter. x
D e n o t i n g t h e duration of p h a s e II b y T , w e c a n write, by reference to F i g . 9.44(b), 2
^PEAK
_
m
^REF
T
116)
RC
2
E q u a t i o n s (9.115) a n d (9.116) c a n b e c o m b i n e d to yield 7/, = r.PM REF
S i n c e t h e c o u n t e r reading, n
m
F
(9.H7) y
Phase I Fixed interval (T )
, at t h e e n d of T is proportional t o T a n d t h e reading, n, at x
x
x
the e n d of T is proportional t o T , w e h a v e 2
I
Phase II Variable interval (T ) 2
2
(b)
ft ^ref/
FIGURE 9 . 4 4
The dual-slope A/D conversion method. Note that v is assumed to be negative. A
b
N
-
j ^ ï
931
932
t
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
CIRCUITS A / D CONVERTER
9.9
Analog input
-o—> o—> V
Bit 1 o
Comparator
v
R1
—o
o V
>
c
Bit 2 o
> Comparator
2-
Digital output
Losic
R2
= 0
0
Si
c
c
2
4
\
1
C
sV
sÀ
19
\o
c_.
C_,
16'
16'
s \
3
19
\
s \ \
19
F ~
1QV> ~o
Bit TV o
- o — > - Comparator o—>• V,
Control parator logic
s \ \
v
A
o
o y-p,
o
o v
o
o V
R
V
N
R(2 -
1)
(a)
FIGURE 9 . 4 5 Parallel, simultaneous, or flash A/D conversion. y
3
T h u s the c o n t e n t of the c o u n t e r , n, at the e n d of the c o n v e r s i o n p r o c e s s is the digital equiv-
0
alent of v .
c
A
T h e dual-slope converter features h i g h a c c u r a c y , since its p e r f o r m a n c e is i n d e p e n d e n t of
C 4
2
C
= - v, _C .
C_,
16'
16'
t h e e x a c t v a l u e s of R a n d C. T h e r e exist m a n y c o m m e r c i a l i m p l e m e n t a t i o n s of t h e dualslope m e t h o d , s o m e of w h i c h utilize C M O S t e c h n o l o g y .
9.9.3 The Parallel or Flash Converter T h e fastest A / D c o n v e r s i o n s c h e m e is the s i m u l t a n e o u s , parallel, or flash c o n v e r s i o n process illustrated in Fig. 9.45. C o n c e p t u a l l y , flash c o n v e r s i o n is very simple. It utilizes 2 N
c o m p a r a t o r s to c o m p a r e the i n p u t signal level with e a c h of the 2
A
- 1
- 1 p o s s i b l e quantization
levels. T h e outputs of the c o m p a r a t o r s are p r o c e s s e d b y a n e n c o d i n g - l o g i c b l o c k to provide
R
(b)
the TV bits of t h e output digital w o r d . N o t e that a c o m p l e t e c o n v e r s i o n c a n b e o b t a i n e d within o n e c l o c k cycle. >
A l t h o u g h flash c o n v e r s i o n is very fast, the p r i c e p a i d is a rather c o m p l e x circuit imple- -
.
m e n t a t i o n . V a r i a t i o n s on the b a s i c t e c h n i q u e h a v e b e e n successfully e m p l o y e d in t h e design C
of I C c o n v e r t e r s .
.
_L ~r
9.9.4 The Charge-Redistribution Converter
Sx/
Cj_
2~ ^T ~r 2
,\
T h e last A / D c o n v e r s i o n t e c h n i q u e t h a t w e shall d i s c u s s is p a r t i c u l a r l y suited for C M O S i m p l e m e n t a t i o n . A s s h o w n in F i g . 9.46, t h e c i r c u i t utilizes a b i n a r y - w e i g h t e d capacitor Q
array, a v o l t a g e c o m p a r a t o r , a n d a n a l o g s w i t c h e s ; c o n t r o l l o g i c (not s h o w n in F i g . 9.46) is a l s o r e q u i r e d . T h e circuit s h o w n is for a 5-bit c o n v e r t e r ; c a p a c i t o r C
T
^
•
Çj_
2
S
v
j
\o
4
C_\_
3
£_]_
C_J_
8 ~ r I6~T~ i 6 ~ r
~ r 4 s
0
o =
sJ
\
j^
V)
s
\
5
^o/
o
^
s
\o
T
*~
I
C r
/
S
^ /
A
o
o v
A
serves the purpose
of t e r m i n a t i n g the c a p a c i t o r array, m a k i n g the total c a p a c i t a n c e e q u a l to t h e d e s i r e d value of2C.
(C)
O p e r a t i o n of t h e converter c a n b e d i v i d e d into t h r e e distinct p h a s e s , as illustrated in Fig. 9.46. In the s a m p l e p h a s e (Fig. 9.46a) switch S is closed, thus c o n n e c t i n g t h e top plate B
of all capacitors to g r o u n d and setting v
to z e r o . M e a n w h i l e , switch S is c o n n e c t e d to the
0
A
A
A
FIGURE 9 . 4 6 Charge-redistribution A/D converter suitable for CMOS implementation: (a) sample phase (b) hold phase, and (c) charge-redistribution phase.
A
a n a l o g input v o l t a g e v . T h u s the v o l t a g e v resulting in a stored c h a r g e of 2Cv .
a p p e a r s across t h e total c a p a c i t a n c e of 2C,
T h u s , d u r i n g this p h a s e , a s a m p l e of v is t a k e n and a A
D u r i n g the h o l d p h a s e (Fig. 9.46b), switch S is o p e n e d a n d switches 5 to S , and S B
t
5
T
are
thrown to the g r o u n d side. T h u s the top plate of t h e c a p a c i t o r array is open-circuited w h i l e
p r o p o r t i o n a l a m o u n t of c h a r g e is stored o n the capacitor array.
their b o t t o m plates are c o n n e c t e d to g r o u n d . Since n o d i s c h a r g e p a t h h a s b e e n p r o v i d e d , the capacitor c h a r g e s m u s t r e m a i n constant, with the total e q u a l to 2Cv . A
5
Note that n is not a continuous function of v , as might be inferred from Eq. (9.118). Rather, n takes on discrete values corresponding to one of the 2 quantized levels of v . A
age at the top p l a t e m u s t b e c o m e -v . A
N
A
nected to
It follows that the volt-
Finally, n o t e that d u r i n g the h o l d p h a s e , S
Vrjp in p r e p a r a t i o n for the charge-redistribution
A
phase.
CIRCUITS
is c o n -
9 3 4
V,-3
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS 9.10
N e x t , w e consider t h e operation during t h e charge-redistribution p h a s e illustrated in Fig. 9.46(c). First, switch S is connected to (through S ). T h e circuit then consists of VREP, a series capacitor C, and a total capacitance to ground of value C. This capacitive divider causes a voltage increment of V /2 t o appear on t h e t o p plates. N o w , if v is greater than V R E P / 2 , the n e t voltage at the top plate will remain negative, which m e a n s that S will b e left in its n e w position as w e m o v e on t o switch S . If, o n the other hand, v w a s smaller than V R E F / 2 , then the net voltage at t h e top plate would b e c o m e positive. T h e comparator will detect this situation a n d signal the control logic to return S to its ground position a n d then to m o v e on to S . Next, switch S is c o n n e c t e d to V^-p, w h i c h causes a v o l t a g e i n c r e m e n t of V^/4 to appear on t h e t o p plate. If t h e resulting v o l t a g e is still negative, S is left in its n e w position; otherwise, S is returned t o its g r o u n d position. W e then m o v e o n t o switch S , a n d so on until all t h e bit switches S t o S h a v e b e e n tried. It c a n b e seen that during t h e charge-redistribution p h a s e t h e voltage on the t o p plate will b e r e d u c e d incrementally t o zero. T h e c o n n e c t i o n of t h e bit switches at t h e c o n c l u s i o n of this p h a s e gives t h e output digital w o r d ; a switch c o n n e c t e d t o g r o u n d indicates a 0 v a l u e for the c o r r e s p o n d i n g bit, w h e r e a s c o n n e c t i o n to V indicates a 1. T h e particular switch configuration depicted in F i g . 9.46(c) is for D = 0 1 1 0 1 . O b s e r v e that at t h e e n d of t h e conversion p r o c e s s , all t h e c h a r g e is stored in t h e capacitors c o r r e s p o n d i n g t o 1 bits; t h e capacitors of the 0 bits h a v e b e e n discharged. x
A
mF
A TWO-STAGE CMOS OP AMP
A
x
2
In this example, w e will use PSpice to aid in designing the frequency compensation of t h e twostage C M O S circuit whose Capture schematic is shown in Fig. 9.47. PSpice will then b e employed to determine the frequency response and the slew rate of t h e op amp. W e will assume a 0.5-(im n-well C M O S technology for the M O S F E T s and use the SPICE level-1 model parameters listed in Table 4.8. Observe that t o eliminate the body effect and improve the matching between M and M , the source terminals of the input P M O S transistors M , and M are connected to their n well.
A
x
2
2
x
2
2
3
x
SPICE SIMULATION EXAMPLE
-«?*
5
2
2
T h e op-amp circuit in Fig. 9.47 is designed using a reference current 7 ^ = 90 /¿A, a supply voltage V = 3.3 V, and a load capacitor C = 1 pF. Unit-size transistors with W/L = 1.25 t i m / 0 . 6 fim are used for both the N M O S and P M O S devices. The transistors are sized for an overdrive voltage V = 0.3 V. T h e corresponding multiplicative factors are given in Fig. 9.47. DD
L
ov
V
R E F
In PSpice, the common-mode input voltage V of the op-amp circuit is set to V /2 = 1.65 V. A bias-point simulation is performed to determine the dc operating point. Using the values found in the simulation output file for the small-signal parameters of the M O S F E T s , we obtain CM
DD
7
G
ML
= 0.333 m A / V
G
M2
= 0.650 m A / V
Huf
T h e accuracy of this A / D conversion m e t h o d is independent of the value of stray capacitances from t h e b o t t o m plate of the capacitors to ground. This is b e c a u s e t h e b o t t o m plates are connected either to ground o r to V ; thus the charge on the stray capacitances will not flow into t h e capacitor array. Also, because both t h e initial and t h e final voltages on t h e t o p plate are zero, the circuit is also insensitive t o the stray capacitances between t h e t o p plates and ground. T h e insensitivity to stray capacitances m a k e s the charge-redistribution technique a reasonably accurate m e t h o d capable of i m p l e m e n t i n g A / D converters with as m a n y as 10 bits.
C, = 26.5 f F
• f
mF
= .1.04 p F
C
2
6
Be
using Eqs. (9.7), (9.14), (9.24), and (9.25), respectively. Then, using Eq. (9.27), the frequency of the second, nondominant, pole can b e found as
fp2 = irrr = 97.2 M H z 2nC P 1
2
In order to place the transmission zero, given by Eq. (9.37), at infinite frequency, w e select 9.34 Consider the 5-bit charge-redistribution converter in Fig. 9.46 with V = 4 V. What is the voltage increment appearing on the top plate when S is switched? What is the full-scale voltage of this converter? If v = 2.5 V , which switches will b e connected t o at the end of conversion? R E F
5
R = -}-
= 1.53 k Q
A
Ans.
I V; |
V; S, and 5 ,
+t-
9.35 Express the m a x i m u m quantization error of an /V-bit A / D converter in terms of its least-significant bit (LSB) and in terms of its full-scale analog input V . Ans. ; I.SH: r , , • 2 . : ' ' - 1 i FS
;
Now, using E q . (9.36), t h e phase margin of the op a m p can b e expressed as -
%
PM = W - t a n ^ - ^ )
(9.119)
w h e r e / , is the unity-gain frequency, given in Eq. (9.30), (7 f /
' 9.10 SPICE SIMULATION EXAMPLE
(
_ "ml " 2K~C
(9-120)
C
Using Eqs. (9.119) and (9.120) we determine that compensation capacitors of C = 0 78 p F and <-c - 2 p F are required to achieve phase margins of P M = 55° and P M = 75°, respectively. C
W e c o n c l u d e this chapter with an e x a m p l e to illustrate t h e u s e of S P I C E in t h e simulation of
I
the two-stage C M O S op amp.
6
More precisely, the final voltage can deviate from zero by as much as the analog equivalent of the LSB. Thus, the insensitivity to top-plate capacitance is not complete.
Recall that G
ML
ZZ^TT°^
and G
are the transconductances of, respectively, the first and second stages of the
M2
1
W
i
C l
r e
r e s e n t
t h e t o t a l
P capacitance to ground at the output nodes of, respectively, the first and second stage of the op amp.
• 9 3 5
9.10
75
•H : '—i —
SPICE S I M U L A T I O N
EXAMPLE
d ——H 0
= 0
50 25 Of -25 o o dB (V (OUT)) -:
1 C
c
\ V
—H = 0 | i
\ -90d C
c
= 0.6 pF
•
135d ;
•-'
-180d 1.0
10
!
I—•—
|
100
1.0K
4
10K
•——I
100K
PM = 55°
—I— ——\—
' 100M
L
1.0M
10M
LOG
• o P(V(OUT)) Frequency (Hz) FIGURE 9 . 4 8 Magnitude and phase response of the op-amp circuit in Fig. 9.47: R = 1.53 kCl, C = 0 (no frequency compensation), and C = 0.6 pF (PM = 55°). c
c
Next, an ac-analysis simulation is performed in PSpice to compute the frequency response of the op amp and to verify the foregoing design values. It was found that, with R = 1.53 k Q , w e needed C = 0.6 p F and C = 1.8 p F to set P M = 55° and P M = 75°, respectively. W e note that c
c
these values are reasonably close to those predicted by hand analysis. T h e corresponding fre o 00
O
quency responses for the compensated op amp are plotted in Figs. 9.48 and 9.49. F o r compari son, we also show the frequency response of the uncompensated op amp (C = 0). Observe that, c
the unity gain frequency/, drops from 70.2 M H z to 26.4 M H z as C is increased to improve P M _1
INN
c
(as anticipated from Eq. 9.120). Rather than increasing the compensation capacitor C , the value of the series resistor R can c
II
be increased to improve the phase margin P M : For a given C , increasing R above 1/G
z +
c
S J3
IN o
op amp. To verify this point, w e simulate in PSpice the step response of the op amp for P M = 5 5 ° and PM = 75°. To do that, we connect the op amp in a unity-gain configuration, apply a small
OS
(10-mV) pulse signal at the input with very short (1-ps) rise and fall times to emulate a step input, a ) co M M ^ II
9 3 6
c
Increasing the P M is desirable because it reduces the overshoot in the step response of the
C/3
0«
we set C to 0.6 p F and simulate the op-amp circuit in PSpice for the cases of 7? = 1.53 k O and 7? = 3.2 k O . The corresponding frequency response is plotted in Fig. 9.50. Observe h o w / , is approximately independent of R. However, by increasing R, P M is improved from 55° to 75°.
o
<
places
adds to the phase margin. Thus, P M can be improved without affecting / . T o verify this point,
T31
>
m2
the transmission zero at a negative real-axis location (Eq. 9.37), where the phase it introduces
1 5! o
II
II
II
II
I/->
^ H
II
II
!>:
22
II
P<
>>
>> H
O
cc o
perform a transient-analysis simulation, and plot the output voltage as shown in Fig. 9.51. Observe that the overshoot in the step response drops from 1 5 % to 1.4% when the phase margin is increased from 55° to 75°.
938
I
CHAPTER
9.10 9
OPERATIONAL-AMPLIFIER
A N D
DATA-CONVERTER
SPICE S I M U L A T I O N
EXAMPLE
CIRCUITS
1.660V PM =
55°
1.656V— ;
PM = 75°
1.652V
1.648V
1.644V 150
250
200 V (OUT)
300
350
Time (ns)
FIGURE 9 . 5 1 Small-signal step response (for a 10-mV step input) of the op-amp circuit in Fig. 9.47 connected in a unity-gain configuration: PM = 55° ( C = 0.6 pF, R = 1.53 k£2) and PM = 75° ( C = 0.6 pF, R = 3.2 kd). c
c
W e conclude this example by computing 57?, the slew rate of the op amp. From Eq. (9.40), SR:
G„
2n f V =-^V l
ov
ov
= 166.5 W pis
when C = 0.6 pF. Next, to determine 57? using PSpice (see Example 2.9), we again connect the op amp in a unity-gain configuration and perform a transient-analysis simulation. However, we now apply a large pulse signal (3.3 V) at the input to cause slew-rate limiting at the output. The corresponding output-voltage waveform is plotted in Fig. 9.52. T h e slope of the slew-rate-limited output waveform corresponds to the slew rate of the op amp and is found to be 57? = 160 V/fis and 60 V/its for the negative- and positive-going output, respectively. These results, with the unequal c
FIGURE 9 . 5 0 Magnitude and phase response of the op-amp circuit in Fig. 9.47: C = 0.6 pF, R = 1.53 kD. (PM = 55°), and R = 3.2 kil (PM = 75°). c
FIGURE 9 . 5 2 Large-signal step response (for a 3.3-V step-input) of the op-amp circuit in Fig. 9.47 con nected in a unity-gain configuration. The slope of the rising and falling edges of the output waveform correspond to the slew rate of the op amp.
9 4 0
f j !
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER CIRCUITS
PROBLEMS
values of SR in the two directions, differ from those predicted by the simple model for the slewrate limiting of the two-stage op-amp circuit (Section 9.1.5). The difference can perhaps be said to be a result of transistor M entering the triode region and its output current (which is sourced through C ) being correspondingly reduced. Of course, the availability of PSpice should enable the reader to explore this point further.
'
941
PROBLEMS
4
SECTION 9 . 1 : THE TWO-STAGE CMOS OP AMP 9 . 1 A particular design of the two-stage CMOS operational amplifier of Fig. 9.1 utilizes +2.5-V power supplies. All tran sistors are operated at overdrive voltages of 0.3-V magnitude. The process technology provides devices with V = | V | = 0.7 V. Find the input common-mode range, and the range allowed for v . M
SUMMARY
LP
0
Most CMOS op amps are designed to operate as part of a VLSI circuit and thus are required to drive only small capacitive loads. Therefore, most do not have a low-outputresistance stage. There are basically two approaches to the design of CMOS op amps: a two-stage configuration, and a singlestage topology utilizing the folded-cascode circuit. In the two-stage CMOS op amp, approximately equal gains are realized in the two stages. The threshold mismatch AV, together with the low transconductance of the input stage result in a larger input offset voltage for CMOS op amps than for bipolar units. Miller compensation is employed in the two-stage CMOS op amp, but a series resistor is required to place the trans mission zero at either s - <*> or on the negative real axis. CMOS op amps have higher slew rates than their bipolar counterparts with comparable / , values.
output stage). It is the same structure used in the two-stage CMOS op amp of Section 9.1.
To obtain high input resistance and low input bias current, the input stage of the 741 is operated at a very low current level. In the 741, output short-circuit protection is accomplished by turning on a transistor that takes away most of the base current drive of the output transistor. The use of Miller frequency compensation in the 741 circuit enables locating the dominant pole at a very low frequency, while utilizing a relatively small compensating capacitance. Two-stage op amps can be modeled as a transconductance amplifier feeding an ideal integrator with C as the inte grating capacitor. c
Use of the cascode configuration increases the gain of a CMOS amplifier stage by about two orders of magnitude, thus making possible a single-stage op amp.
The slew rate of a two-stage op amp is determined by the first-stage bias current and the frequency-compensation capacitor.
The dominant pole of the folded-cascode op amp is deter mined by the total capacitance at the output node, C . Increasing C improves the phase margin at the expense of reducing the bandwidth.
A/D and D/A converters constitute an important group of analog ICs.
L
L
By using two complementary input differential pairs in parallel, the input common-mode range can be extended to equal the entire power-supply voltage, providing so-called rail-to-rail operation at the input. The output voltage swing of the folded-cascode op amp can be extended by utilizing a wide-swing current mirror in place of the cascode mirror. The internal circuit of the 741 op amp embodies many of the design techniques employed in bipolar analog inte grated circuits. The 741 circuit consists of an input differential stage, a high-gain single-ended second stage, and a class AB out put stage. This structure is typical of modern BIT op amps and is known as the two-stage topology (not counting the
9.2 The CMOS op amp of Fig. 9.1 is fabricated in a process for which V „ = 25 V/^m and \V' \ = 20 V/fim. Find A A , and A if all devices are 0.8-/mi long and are operated at equal overdrive voltages of 0.25-V magnitude. Also, deter mine the op-amp output resistance obtained when the second stage is biased at 0.4 mA. What do you expect the output resistance of a unity-gain voltage amplifier to be, using this op amp? A
To obtain low input offset voltage and current, and high CMRR, the 741 input stage is designed to be perfectly bal anced. The CMRR is increased by common-mode feed back, which also stabilizes the dc operating point.
A DAC consists of (a) a circuit that generates a reference cur rent, (b) a circuit that assigns binary weights to the value of the reference current, (c) switches that, under the control of the bits of the input digital word, direct the proper combina tion of binary-weighted currents to an output summing node, and (d) an op amp that converts the current sum to an output voltage. The circuit of (b) can be implemented by either a binary-weighted resistive network or an R-2R ladder. Two simple but slow implementations of the ADC are the feedback-type converter [Fig. 9.43] and the dual-slope converter [Fig. 9.44].
2
AP
(c) With R in place, as in (b), find the value of C that results in the highest possible value of f while providing a phase margin of 80°. What value off is realized? What is the corre sponding frequency of the dominant pole? (d) To what value should C be changed to double the value of//? At the new value of/, what is the phase shift introduced by the second pole? To reduce this excess phase shift to 10° and thus obtain an 80° phase margin, as before, what value should R be changed to? c
c
u
v
D9.3 The CMOS op amp of Fig. 9.1 is fabricated in a process for which | V | for all devices is 10 V//xm. If all transistors have L = 1 jjm and are operated at equal overdrive voltages, find the magnitude of the overdrive voltage required to obtain a dc open-loop gain of 2500 V/V. A
t
c
D 9 . 6 A two-stage CMOS op amp similar to that in Fig. 9.1 is found to have a capacitance between the output node and ground of 1 pF. If it is desired to have a unity-gain bandwidth / of 100 MHz with a phase margin of 75° what must g be set to? Assume that a resistance R is connected in series with the frequency-compensation capacitor C and adjusted to place the transmission zero at infinity. What value should R have? If the first stage is operated at | V | = 0.2 V, what is the value of slew rate obtained? If the first-stage bias current I = 200 [lA, what is the required value of C ? m6
c
0V
c
D 9 . 7 A CMOS op amp with the topology shown in Fig. 9.1 but with a resistance R included in series with C is designed to provide G = 1 mA/V and G = 2 mA/V. c
9 . 4 This problem is identical to Problem 7.90.
mI
Consider the circuit in Fig. 9.1 with the device geometries shown at the bottom of this page: Let 4 E = 225 pA, \V,\ for all devices = 0.75 V, fi C = 180 M / V , Vt>C = 60 fiAJ V , | V \ for all devices = 9 V, Vdd = ss = L5 V. Determine the width of Q , W, that will ensure that the op amp will not have a systematic offset volt age. Then, for all devices, evaluate I , | V \, | V \, g , and r . Provide your results in a table. Also find A A , the dc open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of V on the bias currents. F
n
2
A
v
6
D
OV
GS
0
u
(a) Find the value of C that results i n / = 100 MHz. (b) For R = 500 Q., what is the maximum allowed value of C for which a phase margin of at least 60° is obtained? c
2
m
2
OX
m2
9 . 8 A two-stage CMOS op amp resembling that in Fig. 9.1 is found to have a slew rate of 60 V//is and a unity-gain b a n d w i d t h / of 50 MHz.
m
2
A
(a) Estimate the value of the overdrive voltage at which the input-stage transistors are operating. (b) If the first-stage bias current I = 100 /J.A, what value of C must be used? (c) For a process for which fi C = 50 jiAN , what W/L ratio applies for Q and Qfl c
2
p
D9.5 A particular implementation of the CMOS ampli fier of Figs. 9.1 and 9.2 provides G = 0.3 mA/V, G = 0.6 mA/V, >•„, = r = 222 k Q , r = r = 111 k Q , and C =lpF. ml
o4
o6
m2
0l
2
x
D 9 . 9 Sketch the circuit of a two-stage CMOS amplifier having the structure of Fig. 9.1 but utilizing NMOS transis tors in the input stage (i.e., Q and Q ). x
(a) Find the frequency of the second p o l e , / . (b) Find the value of the resistance R which when placed in series with C causes the transmission zero to be located at P2
c
5 = oo.
0X
SECTION 9 . 2 :
2
THE FOLDED-CASCODE OP AMP
D 9 . 1 0 If the circuit of Fig. 9.8 utilizes ±1.65-V power sup plies and the power dissipation is to be limited to 1 mW, find
The fastest possible ADC implementation is the parallel or flash converter [Fig. 9.45]. The charge-redistribution method [Fig. 9.46] utilizes switched-capacitor techniques and is particularly suited for the implementation of ADCs in CMOS technology.
Transistor
j W/L (jtim/um)
Q,
30/0.5
Q
2
30/0.5
Q
3
10/0.5
Q
4
10/0.5
Q
5
60/0.5
Qe
W/0.5
Qs
60/0.5
60/0.5
942
CHAPTER 9
'
OPERATIONAL-AMPLIFIER
A N D
the values of I and /. To avoid turning off the current mirror during slewing, select I to be 2 0 % larger than I. B
B
D 9 . 1 1 For the folded-cascode op amp utilizing power supplies of + 1 . 6 5 V , find the values of V I A S I > ^BIAS2» d V to maximize the allowable range of V and v . Assume that all transistors are operated at equal overdrive voltages of 0 . 2 V . Assume \V\ for all devices is 0 . 5 V . Specify the maximum range of V, and of v . a n
BlAS3
B
ICM
CM
0
0
DATA-CONVERTER
9 . 1 6 A particular design of the wide-swing current mirror of Fig. 9.12(b) utilizes devices having W/L = 25 and V = 0.5 V For / R E P = 1 0 0 pA give the voltages that you expect to appear at all nodes and specify the minimum voltage allowable at the output terminal. If V is specified to be 10 V, what is the output resistance of the mirror? t
A
D 9 . 1 7 It is required to design the folded-cascode circuit of Fig. 9.9 to provide voltage gain of 80 dB and a unity-gain frequency of 10 MHz when C = 10 pF. Design for I = / and operate all devices at the same | V \. Utilize transistors with l-pm channel length for which |V | is specified to be 20 V. Find the required overdrive voltages and bias currents. What slew rate is achieved? Also, for k' = 2.5ifc' = L
D 9 . 1 2 For the folded-cascode op-amp circuit of Figs. 9 . 8 and 9 . 9 with bias currents I = 1 2 5 pA and I = 1 5 0 pA, and with all transistors operated at overdrive voltages of 0 . 2 V , find the W/L ratios for all devices. Assume that the technology available is characterized by k' = 2 5 0 pA/V and k' = 90 pA/V . B
B
ov
A
9 . 2 3 In the circuit of Fig. 9.13, C?i and Q exhibit emitterbase breakdown at 7 V, while for Q and Q such a breakdown occurs at about 50 V. What differential input voltage would result in the breakdown of the input-stage transistors? 2
3
A
p * 9 . 2 4 Figure P9.24 shows the CMOS version of the circuit in Fig. E9.10. Find the relationship between I and I in terms of k k , k , and k of the four transistors, assuming the threshold voltages of all devices to be equal in magnitude. Note that k denotes ^pC W/L. In the event that k = k and k = k = 16k find the required value of I to yield a bias current in Q and Q of 1.6 mA. 3
u
2
3
x
ox
2
3
A
x
u
3
p
2
X
A
r
L
200 /xA/V , specify the required width of each of the 11 transistors used. D 9 . 1 3 Sketch the circuit that is complementary to that in Fig. 9.9, that is, one that uses an input p-channel differential pair.
B
ov
m
0
>
A
S9
SS
a o
to
CL
C2
2
6
3
9 . 3 2 Consider the input circuit of the 7 4 1 op amp of Fig. 9 . 1 3 when the emitter current of Q is about 1 9 pA. If B of Q is 1 5 0 and that of Q is 2 0 0 , find the input bias current I and the input offset current 7 of the op amp. S
P
SECTION 9 . 3 :
X
2
B
0 S
9 . 3 3 For a particular application, consideration is being given to selecting 7 4 1 ICs for bias and offset currents limited to 4 0 nA and 4 nA, respectively. Assuming other aspects of the selected units to be normal, what minimum 0 and what B variation are implied?
THE 7 4 1 OP-AMP CIRCUIT
N
9 . 2 0 In the 741 op-amp circuit of Fig. 9.13, Q Q , Q , and Q are biased at collector currents of 9.5 pA; Q is biased at a collector current of 16.2 pA; and Q is biased at a collector current of 550 pA. All these devices are of the "standard npri" type, having I = 1 0 " A, B = 200, and V = 125 V. For each of these transistors, find V , g , r , r , and r . Provide your results in table form. (Note that these parameter values are utilized in the text in the analysis of the 741 circuit.) u
2
5
FIGURE P 9 . 2 4
N
16
A
BE
m
e
K
0
D 9 . 2 1 For the (mirror) bias circuit shown in Fig. E9.10 and the result verified in the associated Exercise, find I for the case in which 7 = 3 x 1 0 " A, I = 6 x 1 0 " A, and I = I = 1 0 " A and for which a bias current 7 = 154 pA is required. X
14
14
53
S4
SL
14
S2
ss
D 9 . 2 9 Consider the dc analysis of the 7 4 1 input stage shown in Fig. 9 . 1 6 for the situation in which I = 2I . F o r 7 = 1 9 pA and assuming BP be high, what does / become? Redesign the Widlar source to reestablish I = I = 9.5 pA.
P
14
DD
2
Av=200.
3
S
9 . 1 5 For the circuit in Fig. 9.11, assume that all transistors are operating at equal overdrive voltages of 0.2-V magnitude and have | V,| = 0.5 V and that V = V = 1.65 V. Find (a) the range over which the NMOS input stage operates, (b) the range over which the PMOS input stage operates, (c) the range over which both operate (the overlap range), and (d) the input common-mode range.
x
s
D 9 . 1 9 For the folded-cascode circuit of Fig. 9.8, let the total capacitance to ground at each of the source nodes of Q and Q be denoted C . Show that the pole that arises at the interface between the first and second stages has a frequency fp ~ Sm^^Cp. Now, if this is the only nondominant pole, what is the largest value that C can be (expressed as a fraction of C ) while a phase margin of 75° is achieved? Assume that all transistors are operated at the same bias current and overdrive voltage.
17
FIGURE P 9 . 1 4
P
c l 0
3
v
-oV„
9 . 2 8 Consider the dc analysis of the 7 4 1 input stage shown in Fig. 9 . 1 6 . For what value of fi do the currents in Q and Q differ from the ideal value of 7 / 2 by 1 0 % ?
C3
6
9C
BE10
D 9 . 3 1 It is required to redesign the circuit of Fig. 9 . 1 7 by selecting a new value for R so that when the base currents are not neglected, the collector currents of Q , Q , and Q-, all become equal, assuming that the input current I = 9 . 4 pA. Find the new value of R and the three currents. Recall that
A
C
BEU
6
L
9 . 1 4 Consider a design of the cascode op amp of Fig. 9.9 for which 7 = 1 2 5 pA and I = 1 5 0 pA. Assume that all transistors are operated at | V \ = 0 . 2 V and that for all devices, | V | = 1 0 V . Find G , R , and A . Also, if the op amp is connected in the feedback configuration shown in Fig. P 9 . 1 4 , find the voltage gain and output resistance of the closed-loop amplifier.
C 1 0
S
9 . 3 0 For the mirror circuit shown in Fig. 9 . 1 7 with the bias and component values given in the text for the 7 4 1 circuit, what does the current in Q become if R is shorted?
P
2
D9.13 Consider the folded-cascode op amp when loaded with a 1 0 - p F capacitance. What should the bias current I be to obtain a slew rate of at least 1 0 V / i t s ? If the inputstage transistors are operated at overdrive voltages of 0 . 2 V , what is the unity-gain bandwidth realized? If the two nondominant poles have the same frequency of 2 5 MHz, what is the phase margin obtained? If it is required to have a phase margin of 7 5 ° , what m u s t / be reduced to? By what amount should C be increased? What is the new value of SRI
D 9 . 2 7 Design the Widlar current source of Fig. 9.15 to generate a current 7 = 20 pA given that I-^EF ~ mA. Ifßfor the transistors, 7 = 10 A, find V and V 0.5 . Assume to be high.
A
2
n
9 4 3
PROBLEMS
CIRCUITS
3
SECTION 9 . 4 :
DC ANALYSIS OF THE 7 4 1
D 9 . 2 5 For the 741 circuit, estimate the input reference current 7 in the event that ±5-V supplies are used. Find a more precise value assuming that for the two BITs involved, I = 1 0 " A. What value of R would be necessary to reestablish the same bias current for +5-V supplies as exists for ±15 V in the original design? R E F
L3
- 1 4
SA
14
SB
A
EB
m
c
0
X
A
14
s
5
* 9 . 2 6 In the 741 circuit, consider the c o m m o n - m o d e feedback loop comprising transistors Q Q , Q , Q , 2 , <2 , and Q . W e wish to find the loop gain. This can be conveniently done by breaking the loop between the common collector connection of Q and Q , and the diode-connected transistor Q . Apply a test current signal I, to Q and find the returned current signal l in the combined collector connection of GJi and Q . Thus determine the loop gain. Assume that Q and Q act as ideal current sources. If Q and Q have B = 50, find the amount of common-mode feedback in decibels. h
9
2
3
A
8
w
y
9 . 2 2 Transistor Q in the circuit of Fig. 9.13 consists, in effect, of two transistors whose emitter-base junctions are connected in parallel and for which I = 0.25 x 1 0 A, I = 0.75 x 1 0 ~ A, B = 50, and V = 50 V. For operation at a total emitter current of 0.73 mA, find values for the parameters V , g , r , r„, and r for the A and B devices.
9 . 3 4 A manufacturing problem in a 7 4 1 op amp causes the current transfer ratio of the mirror circuit that loads the input stage to become 0 . 9 A/A. For input devices (Q -Q ) appropriately matched and with high /3, and normally biased at 9 . 5 pA, what input offset voltage results?
%
S
2
w
9
C 1 6
0 9 . 3 6 Reconsider the 7 4 1 output stage as shown in Fig. 9 . 1 8 , in which R is adjusted to make I = 7 - What is the new value of 7? ? What values of 7 and 7 result? 10
CL9
10
C 1 4
a 8
C 2 0
2
r
9
D 9 . 3 5 Consider the design of the second stage of the 7 4 1 . What value of R would be needed to reduce 7 to 9 . 5 pA7
3
A
D * 9 . 3 7 An alternative approach to providing the voltage drop needed to bias the output transistors is the Vg -multiplier circuit shown in Fig. P 9 . 3 7 . Design the circuit to provide a terminal voltage of 1 . 1 1 8 V (the same as in the 7 4 1 circuit). Base your design on half the current flowing through R and assume that I = 1 0 " A and /3= 2 0 0 . What is the incremental £
lt
1 4
S
944
CHAPTER 9
OPERATIONAL-AMPLIFIER A N D DATA-CONVERTER
resistance between the two terminals of the V -multiplier S£
CIRCUITS
PROBLEMS
AR/R between R and R , x
circuit?
2
AR
l +
"OS
2V
R
1
T
r./R
Vn,/2V "OS ' ^
T
N
y
T
where r is the emitter resistance of each of Q to Q , and R is the nominal value of R and R . (Hint: Use Eq. 9.75) (b) Find AR/R to trim a 5-mV offset to zero. (c) What is the maximum offset voltage that can be trimmed this way (corresponding to R completely shorted)? e
I = 180 pA
x
x
bias current of 9.5 pA. Find the input resistance of the commonmode half-circuit using B = 200, B = 50, and V - 125 V for npn and 50 V for pnp transistors. To find the common-mode input resistance of the 741 note that it has commonmode feedback that increases the input common-mode resistance. The loop gain is approximately equal to B . Find the value of R .
6
2
P
A
P
lcm
I Ri
Q:
Rl
9 . 3 8 For the circuit of Fig. 9.13, what is the total current required from the power supplies when the op amp is operated in the linear mode, but with no load? Hence, estimate the quiescent power dissipation in the circuit. (Hint: Use the data given in Table 9.1.)
the current in Q equal to the maximum current available from the input stage (i.e., the current in g ) ? What simple change would you make to reduce this current limit to 10 mA? 22
8
SECTION 9 . 6 : G A I N , FREQUENCY RESPONSE, AND SLEW RATE OF THE 7 4 1
9 . 5 5 A 741 op amp has a phase margin of 80°. If the excess phase shift is due to a second single pole, what is the frequency of this pole?
W W v V F I G U R E P9.37
9 4 5
9 . 5 4 Using the data provided in Eq. (9.93) (alone) for the overall gain of the 741 with a 2-kQ. load, and realizing the significance of thé factor 0.97 in relation to the load, calculate the open-circuit voltage gain, the output resistance, and the gain with a load of 200 Q. What is the maximum output voltage available for such a load?
2
180 pA
I
9 . 5 6 A 741 op amp has a phase margin of 80°. If the op amp has nearly coincident second and third poles, what is their frequency?
Y -V
EE
FIGURE P 9 . 4 7
FIGURE P 9 . 4 2
D * 9 . 5 7 For a modified 741 whose second pole is at 5 MHz, what dominant-pole frequency is required for 85° phase margin with a closed-loop gain of 100? Assuming C continues to control the dominant pole, what value of C would be required? c
9 . 4 3 Through a processing imperfection, the B of fi in Fig. 9.13 is reduced to 25, while the B of Q remains at its regular value of 50. Find the input offset voltage that this mismatch introduces. (Hint: Follow the general procedure outlined in Example 9.3.) 4
SECTION 9 . 5 :
SMALL-SIGNAL ANALYSIS
3
OF THE 7 4 1 9 . 3 9 Consider the 741 input stage as modeled in Fig. 9.19, with two additional npn diode-connected transistors, Q and Q , connected between the present npn and pnp devices, one per side. Convince yourself that each of the additional devices will be biased at the same current as Q to Q —that is, 9.5 pA. What does R become? What does G become? What is the value of R now? What is the output resistance of the first stage, R 7 What is the new open-circuit voltage gain, G R ? Compare these values with the original ones. la
2a
x
id
4
mX
o4
9 . 4 4 Consider the circuit of Fig. 9.13 modified to include resistors R in series with the emitters of each of Q and Q . What does the resistance looking into the collector of Q , R , become? For what value of R does it equal R l For this case, what does R looking to the left of node Y become? %
9
9
o9
oW
ol
3
2
3
4
P
P
4
0
mcm
2
9 . 4 2 In Example 9.3 we investigated the effect of a mismatch between R and R on the input offset voltage of the op amp. Conversely, 7?, and R can be deliberately mismatched (using the circuit shown in Fig. P9.42, for example) to compensate for the op amp input offset voltage. x
x
2
o2
oX3B
l2
X3A
X3B
l3B
0 3B
0ll
9 . 5 8 An internally compensated op amp having a n / , of 5 MHz and dc gain of 10 utilizes Miller compensation around an inverting amplifier stage with a gain of -1000. If space exists for at most a 50-pF capacitor, what resistance level must be reached at the input of the Miller amplifier for compensation to be possible? 6
o2
9 . 5 0 For a 741 employing ±5-V supplies, | V \ = 0.6 V and | V c . | = 0.2 V, find the output voltage limits that apply. £sat
D 9 . 5 1 Consider stage in which Q emitter are joined. the collector of Q . 23
an alternative to the present 741 output is not used, that is, in which its base and Reevaluate the reflection of R = 2 kQ to What does A become? L
2
9 . 5 2 Consider the positive current-limiting circuit involving Q , Q , and R . Find the current in R at which the collector current of Q equals the current available from Q (180 pA) minus the base current of g . (You need to perform a couple of iterations.) 13A
l5
6
6
X5
2
X3A
9 . 5 9 Consider the integrator op-amp model shown in Fig. 9.33. For G = 10 mA/V, C = 50 pF, and a resistance of 10 Q shunting C , sketch and label a Bode plot for the magnitude of the open-loop gain. If G is related to the first-stage bias current via Eq. (9.105), find the slew rate of this op amp. ml
c
8
c
ml
9 . 6 0 For an amplifier with a slew rate of 10 Y/ps, what is the full-power bandwidth for outputs of ±10 V? What unitygain bandwidth, w„ would you expect if the topology was similar to that of the 741? D * 9 . 6 1 Figure P9.61 shows a circuit suitable for op-amp applications. For all transistors 0 = 100, V = 0.7 V, and BE
] 4
* 9 . 4 7 Figure P9.47 shows the equivalent common-mode half-circuit of the input stage of the 741. Here R is the resistance seen looking to the left of node F i n Fig. 9.13; its value is approximately 2.4 MQ. Transistors Q and g operate at a a
os
9 . 4 9 In the analysis of the 741 second stage, note that R is affected most strongly by the low value of R . Consider the effect of placing appropriate resistors in the emitters of Q , Q , and Q on this value. What resistor in the emitter of Q would be required to make R i equal to R and thus R half as great? What resistors in each of the other emitters would be required?
xl
* 9 . 4 6 What is the effect on the differential gain of the 741 op amp of short-circuiting one, or the other, or both, of R and R in Fig. 9.13? (Refer to Fig. 9.20.) For simplicity, assume
2
(a) Show that an input offset voltage V can be compensated for (i.e., reduced to zero) by creating a relative mismatch
m2
P
ml
ml
9 . 4 1 Repeat Exercise 9.14 with 7?, = R replaced by 2-kQ resistors.
i2
BE
* 9 . 4 5 Refer to Fig. E9.15 and let R = R . If g and Q have a B mismatch such that for Q the current gain is B and for Q the current gain is k(5 , find i„ and G^. For R = 2.43 MQ, B = 20, 0.5 < k < 2, G (differential) = 1/5.26 kQ, find the worstcase CMRR: ; G /G (in dB) that results. Assume everything else is ideal. x
© 9 . 4 0 What relatively simple change can be made to the mirror load of stage 1 to increase its output resistance, say by a factor of 2?
8
a
ol
ml
9 . 4 8 Consider a variation on the design of the 741 second stage in which R = 50 Q. What R and G correspond?
c
x
3
(a) For inputs grounded and output held at 0 V (by negative feedback) find the emitter currents of all transistors. D 9 . 5 3 Consider the 741 sinking-current limit involving ^ 7 > Q21, Q , R\\, and Q . For what current through R-, is (b) Calculate the gain of the amplifier with a load of 10 kQ.. 24
22
946
I CHAPTER 9
OPERATIONAL-AMPLIFIER A N D
DATA-CONVERTER
PROBLEMS
CIRCUITS
+10 V
0 * 9 . 6 7 The circuit in Fig. 9.41 can be used to multiply an analog signal by a digital one by feeding the analog signal to the VREF terminal. In this case the D/A converter is called a multiplying D A C or MDAC. Given an input sine-wave signal of 0.1 sin cot volts, use the circuit of Fig. 9.41 together with an additional op amp to obtain v = WD sin cot, where D is the digital word given by Eq. (9.109) and N = 4. How many discrete sine-wave amplitudes are available at the output? What is the smallest? What is the largest? To what digital input does a 10-V peak-to-peak output correspond? 0
9 . 6 8 What is the input resistance seen by V , in the cir cuit of Fig. 9.41? KTJ
SECTION 9 . 9 :
A/D CONVERTER CIRCUITS
9.69 A 12-bit dual-slope ADC of the type illustrated in Fig. 9.44 utilizes a 1-MHz clock and has = 10 V. Its analog input voltage is in the range 0 to - 1 0 V. The fixed
FIGURE P9.61
(c) With load as in (b) calculate the value of the capacitor C required for a 3-dB frequency of 1 kHz. SECTION 9 . 7 : DATA CONVERTERS— AN INTRODUCTION 9 . 6 2 An analog signal in the range 0 to +10 V is to be digi tized with a quantization error of less than 1% of full scale. What is the number of bits required? What is the resolution of the conversion? If the range is to be extended to +10 V with the same requirement, what is the number of bits required? For an extension to a range of 0 to +15 V, how many bits are required to provide the same resolution? What is the corre sponding resolution and quantization error? * 9 . 6 3 Consider Fig. 9.38. On the staircase output of the S/H circuit sketch the output of a simple low-pass RC circuit with a time constant that is (a) one-third of the sampling interval and (b) equal to the sampling interval. SECTION 9 . 8 :
D/A CONVERTER CIRCUITS
* 9 . 6 4 Consider the DAC circuit of Fig. 9.39 for the cases N=2,4, and 8. What is the tolerance, expressed as ±x%, to which the resistors should be selected to limit the resulting output error to the equivalent of ±1 LSB? 9 . 6 S The BITs in the circuit of Fig. P9.65 have their b a s e emitter junction areas scaled in the ratios indicated. Find/j to I a in terms of I.
1
l x
1
2x
4x
8X
J
FIGURE P9.65
D 9 . 6 6 A problem encountered in the DAC circuit of Fig. 9.41 is the large spread in transistor EBI areas required when N is large. As an alternative arrangement, consider using the circuit in Fig. 9.41 for 4 bits only. Then, feed the current in the collector of the terminating transistor Q, to the circuit of Fig. P9.65 (in place of the current source / ) , thus producing currents for 4 more bits. In this way, an 8-bit DAC can be implemented with a maximum spread in areas of 8. What is the total area of emitters needed in terms of the smallest device? Contrast this with the usual 8-bit circuit. Give the complete circuit of the converter thus realized.
947
interval 7\ is the time taken for the counter to accumulate a count of 2 . What is the time required to convert an input voltage equal to the full-scale value? If the peak voltage reached at the output of the integrator is 10 V , what is the integrator time constant? If through aging, R increases by 2% and C decreases by 1%, what does V p K become? Does the conversion accuracy change? N
E A
D 9 . 7 0 The design of a 4-bit flash ADC such as that shown in Fig. 9.45 is being considered. How many comparators are required? For an input signal in the range of 0 to +10 V, what are the reference voltages needed? Show how they can be generated using a 10-V reference and several 1-kO resistors (how many?). If a comparison is possible in 50 ns and the associated logic requires 35 ns, what is the maximum possi ble conversion rate? Indicate the digital code you expect at the output of the comparators and at the output of the logic for an input of (a) 0 V, (b) +5.1 V , and (c) +10 V.
Digital CMOS Logic Circuits Introduction 10.1
Inverter CMOS
CMOS
955
10.6
963
Pseudo-NMOS Circuits
10.7
982
Dynamic Logic Circuits
991
S P I C E Simulation Example
Logic-Gate
Circuits 10.4
950
Pass-Transistor Logic Circuits
Design and Performance A n a l y s i s of t h e
10.3
10.5
Digital Circuit D e s i g n : An Overview
10.2
949
998
Summary
1002
Problems
1003
Logic
974
INTRODUCTION This c h a p t e r is c o n c e r n e d w i t h t h e study of C M O S digital logic circuits. C M O S is b y far t h e m o s t p o p u l a r t e c h n o l o g y for the i m p l e m e n t a t i o n of digital systems. T h e small size, e a s e of fabrication, and l o w p o w e r dissipation of M O S F E T s enable e x t r e m e l y h i g h levels of inte gration of b o t h logic and m e m o r y circuits. T h e latter will b e studied in C h a p t e r 1 1 . T h e c h a p t e r b e g i n s with an o v e r v i e w section w h o s e objective is to p l a c e in p r o p e r per spective the m a t e r i a l w e shall study in this c h a p t e r a n d the next. T h e n , building o n the study of the C M O S inverter in Section 4.10, w e take a comprehensive l o o k at its design and analysis. This material is then applied to the design of C M O S logic circuits and t w o other types of logic circuits ( n a m e l y , p s e u d o - N M O S and pass-transistor logic) that are frequently e m p l o y e d in special applications, as s u p p l e m e n t s to C M O S . T o r e d u c e the p o w e r dissipation even further, and simultaneously to increase perfor m a n c e (speed of operation), d y n a m i c logic t e c h n i q u e s are e m p l o y e d . This challenging topic is t h e subject of Section 10.6 and c o m p l e t e s o u r study of logic circuits. T h e c h a p t e r c o n cludes w i t h a S P I C E s i m u l a t i o n e x a m p l e . In s u m m a r y , this c h a p t e r p r o v i d e s a r e a s o n a b l y c o m p r e h e n s i v e and in-depth treatment of C M O S digital integrated-circuit design, p e r h a p s t h e m o s t significant area (at least in
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CIRCUITS
10.1
t e r m s of p r o d u c t i o n v o l u m e and societal impact) of electronic circuits. T o gain t h e m o s t out of studying this chapter, the r e a d e r m u s t b e t h o r o u g h l y familiar w i t h the M O S transistor. T h u s , a r e v i e w of C h a p t e r 4 is r e c o m m e n d e d , a n d a careful study of Section 4.10 is a must!
" '" 10.1 DIGITAL CIRCUIT DESIGN: AN OVERVIEW In this section, w e build on the introduction to digital circuits presented in Section 1.7 and provide an o v e r v i e w of the subject. W e discuss the various technologies and logic-circuit families currently in use, consider the p a r a m e t e r s e m p l o y e d to characterize the operation and performance of logic circuits, and finally m e n t i o n the various styles for digital-system design.
10.1.1 Digital IC Technologies and Logic-Circuit Families T h e chart in Figure 10.1 s h o w s the major I C technologies and logic-circuit families that are currently in use. T h e concept of a logic-circuit family p e r h a p s n e e d s a few w o r d s of expla nation. M e m b e r s of each family are m a d e w i t h t h e s a m e t e c h n o l o g y , h a v e a similar circuit structure, a n d exhibit the s a m e basic features. E a c h logic-circuit family offers a u n i q u e set of a d v a n t a g e s and disadvantages. In the c o n v e n t i o n a l style of designing systems, one selects an appropriate logic family (e.g., T T L , C M O S , or E C L ) and attempts to i m p l e m e n t as m u c h of the s y s t e m as possible using circuit m o d u l e s ( p a c k a g e s ) that b e l o n g to this family. In this w a y , interconnection of the various p a c k a g e s is relatively straightforward. If, o n t h e other h a n d , p a c k a g e s from m o r e than o n e family are used, o n e h a s to design suitable interface cir cuits. T h e selection of a logic family is b a s e d on such considerations as logic flexibility, speed of operation, availability of c o m p l e x functions, noise immunity, operating-temperature range, p o w e r dissipation, and cost. W e will discuss s o m e of these considerations in this chapter and the next. T o begin with, w e m a k e s o m e brief r e m a r k s on each of t h e four tech nologies listed in the chart of Fig. 1 0 . 1 . CMOS A l t h o u g h s h o w n as one of four p o s s i b l e technologies, this is not an indication of digital I C m a r k e t share: C M O S t e c h n o l o g y is, b y a large margin, the m o s t d o m i n a n t of all t h e I C t e c h n o l o g i e s available for digital-circuit design. A s m e n t i o n e d earlier, C M O S h a s r e p l a c e d N M O S , w h i c h w a s e m p l o y e d in t h e early d a y s of V L S I (in the 1970s). T h e r e are a n u m b e r of reasons for this d e v e l o p m e n t , t h e m o s t i m p o r t a n t of w h i c h is the m u c h l o w e r p o w e r dissipation of C M O S circuits. C M O S h a s also r e p l a c e d bipolar as the technology-ofchoice in digital-system design, and has m a d e possible levels of integration (or circuit-packing
Digital IC technologies and logic-circuit families
" Bipolar
CMOS
Complementary Pseudo-NMOS CMOS FIGURE 1 0 . 1
Pass-transistor logic
Dynamic logic
Digital IC technologies and logic-circuit families.
TTL
ECL
f t BiCMOS
GaAs
DIGITAL
CIRCUIT DESIGN: AN
OVERVIEW
densities), a n d a r a n g e of a p p l i c a t i o n s , n e i t h e r of w h i c h w o u l d h a v e b e e n p o s s i b l e w i t h b i polar technology. Furthermore, C M O S continues to advance, whereas there appear to be few innovations at t h e p r e s e n t t i m e in bipolar digital circuits. S o m e of t h e r e a s o n s for C M O S displacing bipolar t e c h n o l o g y in digital applications are as follows: 1. C M O S logic circuits dissipate m u c h less p o w e r than bipolar logic circuits and t h u s o n e can p a c k m o r e C M O S circuits o n a chip t h a n is possible w i t h bipolar circuits. W e will h a v e a lot m o r e to say about p o w e r dissipation in t h e following sections. 2. T h e h i g h input i m p e d a n c e of the M O S transistor allows the designer to u s e c h a r g e storage as a m e a n s for the temporary storage of information in b o t h logic and m e m o r y circuits. T h i s t e c h n i q u e cannot b e u s e d in bipolar circuits. 3. T h e feature size (i.e., m i n i m u m c h a n n e l length) of the M O S transistor h a s d e c r e a s e d dramatically o v e r the y e a r s , with s o m e recently reported d e s i g n s utilizing c h a n n e l lengths as short as 0.06 pun. This permits very tight circuit p a c k i n g and, c o r r e s p o n d ingly, v e r y h i g h levels of integration. Of the v a r i o u s forms of C M O S , c o m p l e m e n t a r y C M O S circuits b a s e d on t h e inverter stud ied in Section 4 . 1 0 are the m o s t w i d e l y used. T h e y are available b o t h as small-scale inte grated (SSI) circuit p a c k a g e s (containing 1-10 logic gates) and m e d i u m - s c a l e integrated (MSI) circuit p a c k a g e s ( 1 0 - 1 0 0 gates p e r chip) for a s s e m b l i n g digital s y s t e m s on printedcircuit b o a r d s . M o r e significantly, complementary C M O S is used in V L S I logic (with millions of gates per chip) and memory-circuit design. In s o m e applications, c o m p l e m e n t a r y C M O S is s u p p l e m e n t e d b y o n e (or both) of t w o other M O S logic circuit forms. T h e s e are p s e u d o N M O S , s o - n a m e d because of the similarity of its structure to N M O S logic, and pass-transistor logic, b o t h of w h i c h will b e studied in this chapter. A fourth t y p e of C M O S logic circuit utilizes d y n a m i c techniques to obtain faster circuit operation, w h i l e k e e p i n g t h e p o w e r dissipation very low. D y n a m i c C M O S logic represents an area of g r o w i n g i m p o r t a n c e . Lastly, C M O S t e c h n o l o g y is u s e d in t h e design of m e m o r y chips, as will b e detailed in C h a p t e r 1 1 .
Bipolar T w o logic-circuit families b a s e d o n t h e b i p o l a r j u n c t i o n transistor are in s o m e u s e at p r e s e n t : T T L and E C L . T r a n s i s t o r - t r a n s i s t o r logic ( T T L or T L ) w a s for m a n y y e a r s the m o s t w i d e l y u s e d logic-circuit family. Its d e c l i n e w a s precipitated b y the a d v e n t of t h e V L S I era. T T L m a n u f a c t u r e r s , h o w e v e r , fought b a c k w i t h t h e i n t r o d u c t i o n of l o w - p o w e r and h i g h - s p e e d v e r s i o n s . In t h e s e n e w e r v e r s i o n s , t h e h i g h e r s p e e d s of o p e r a t i o n are m a d e possible b y p r e v e n t i n g the B J T from saturating a n d thus a v o i d i n g t h e s l o w turnoff p r o c e s s of a saturated transistor. T h e s e n o n s a t u r a t i n g v e r s i o n s of T T L utilize t h e S c h o t t k y d i o d e discussed in Section 3.8 and are called S c h o t t k y T T L or variations of this n a m e . D e s p i t e all these efforts, T T L is n o l o n g e r a significant logic-circuit family a n d will n o t b e studied in this b o o k . 2
T h e other bipolar logic-circuit family in p r e s e n t u s e is emitter-coupled logic ( E C L ) . It is based o n the current-switch i m p l e m e n t a t i o n of t h e inverter, discussed in Section 1.7. T h e basic e l e m e n t of E C L is t h e differential B J T pair studied in C h a p t e r 7. B e c a u s e E C L is basi cally a current-steering logic, and, correspondingly, also called c u r r e n t - m o d e logic ( C M L ) , in w h i c h saturation is avoided, very h i g h speeds of operation are possible. Indeed, of all t h e c o m m e r c i a l l y available logic-circuit families, E C L is the fastest. E C L is also u s e d in V L S I circuit design w h e n very high operating speeds are required and t h e designer is willing to accept h i g h e r p o w e r dissipation and increased silicon area. A s such, E C L is considered an important specialty t e c h n o l o g y and will b e briefly discussed in C h a p t e r 1 1 .
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DIGITAL CIRCUIT DESIGN: AN
OVERVIEW
B i C M O S B i C M O S combines the high operating speeds possible with BJTs (because of their inherently higher transconductance) with the l o w power dissipation and other excellent charac teristics of C M O S . Like C M O S , B i C M O S allows for the implementation of both analog and digital circuits on the same chip. (See the discussion of analog B i C M O S circuits in Chapter 6.) A t present, B i C M O S is used to great advantage in special applications, including m e m o r y chips, where its high performance as a high-speed capacitive-current driver justifies the m o r e complex process technology it requires. A brief discussion of B i C M O S is provided in Chapter 11. G a l l i u m A r s e n i d e ( G a A s ) T h e h i g h carrier mobility in G a A s results in very h i g h speeds of operation. T h i s has b e e n d e m o n s t r a t e d in a n u m b e r of digital I C chips utilizing GaAs technology. It should b e pointed out, h o w e v e r , that G a A s remains an "emerging technology," o n e that appears to h a v e great potential b u t h a s n o t yet a c h i e v e d such potential c o m m e r cially. A s such, it will not b e studied in this b o o k . Nevertheless, considerable material on G a A s devices and circuits, including digital circuits, can b e found on the C D accompanying this b o o k and on the b o o k ' s website.
10.1.2 Logic-Circuit Characterization
~H
M
IH
IL
lh
IH
—
VOL
10%—|—VI I -H
h
H
L
- J -
!
I
\
->|
I
t
—
P
T h e r o b u s t n e s s of a logic-circuit family is d e t e r m i n e d b y its ability to reject n o i s e , and t h u s b y t h e noise m a r g i n s NH a n d NM , L
T L H
FIGURE 1 0 . 3 Definitions of propagation delays and switching times of the logic inverter. An ideal inverter is one for w h i c h NM
H
= NM
L
= V /2, DD
where V
is the power-supply
DD
voltage. Further, for an ideal inverter, t h e threshold voltage V
M
=
V /2. DD
P r o p a g a t i o n D e l a y T h e d y n a m i c p e r f o r m a n c e of a logic-circuit family is characterized by the p r o p a g a t i o n delay of its basic inverter. F i g u r e 10.3 illustrates the definition of t h e low-to-high p r o p a g a t i o n delay (t ) a n d t h e h i g h - t o - l o w p r o p a g a t i o n delay (t ). The inverter p r o p a g a t i o n delay (t ) is defined as the a v e r a g e of these t w o quantities: PLH
NM =V -V
IH
(10.1)
NM =V -V
0L
(10.2)
H
L
0H
IL
^
t
IL
0
H
1
90%-V
OH)
T h e following p a r a m e t e r s are usually u s e d to characterize the operation and p e r f o r m a n c e of a logic-circuit family.
0L
PHL
V
0
0H
L
1 OH
{(V L+
N o i s e M a r g i n s T h e static operation of a logic-circuit family is characterized b y the volt age transfer characteristic ( V T C ) of its basic inverter. F i g u r e 10.2 shows such a V T C and defines its four p a r a m e t e r s ; V , V , V , a n d V . N o t e that V and V are defined as the points at w h i c h t h e slope of t h e V T C is - 1 . A l s o indicated is the definition of t h e threshold v o l t a g e V , or V as w e shall frequently call it, as the point at w h i c h v = v R e c a l l that w e discussed t h e V T C in its generic f o r m in Section 1.7, and h a v e also seen actual V T C s : in Section 4.10 for the C M O S inverter, a n d in Section 5.10 for the B J T inverter.
1
A
PHL
P
tp —
PLH +
(10.3)
t„ L)
Obviously, t h e shorter the propagation delay, the h i g h e r t h e speed at w h i c h the logic-circuit family can b e operated.
Power D i s s i p a t i o n P o w e r dissipation is an i m p o r t a n t issue in digital-circuit design. T h e need to m i n i m i z e t h e gate p o w e r dissipation is m o t i v a t e d b y the desire to p a c k an everincreasing n u m b e r of gates o n a chip, w h i c h in turn is m o t i v a t e d b y space and e c o n o m i c considerations. In general, h o w e v e r , m o d e r n digital s y s t e m s utilize large n u m b e r s of gates and m e m o r y cells, and thus to keep the total p o w e r r e q u i r e m e n t within reasonable b o u n d s , the p o w e r dissipation p e r gate and p e r m e m o r y cell should b e k e p t as low as possible. T h i s is particularly t h e case for portable, battery-operated e q u i p m e n t such as cellular p h o n e s and personal digital assistants ( P D A s ) . T h e r e are t w o types of p o w e r dissipation in a logic gate: static and d y n a m i c . Static power refers to the p o w e r that the gate dissipates in the absence of switching action. It results from t h e p r e s e n c e of a path in the gate circuit b e t w e e n the p o w e r supply and g r o u n d in one or b o t h of its t w o states (i.e., with t h e o u t p u t either l o w or high). D y n a m i c p o w e r , o n the other hand, occurs only w h e n the gate is switched: A n inverter operated from a p o w e r supply V , and driving a load capacitance C, dissipates d y n a m i c p o w e r P , DD
FIGURE 1 0 . 2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.
D
(10.4)
fcv
L
954
;'„"
CHAPTER 10
DIGITAL CMOS
LOGIC
w h e r e / i s the frequency at w h i c h t h e inverter is being switched. T h e derivation of this for m u l a (Section 4.10) is b a s e d on the a s s u m p t i o n that the l o w and h i g h output voltage levels are 0 and V , respectively. DD
D e l a y - P o w e r P r o d u c t O n e is usually interested in h i g h - s p e e d p e r f o r m a n c e (low t ) c o m b i n e d w i t h low p o w e r dissipation. Unfortunately, these t w o r e q u i r e m e n t s are often in conflict; generally, w h e n designing a gate, if o n e attempts to r e d u c e p o w e r dissipation by decreasing t h e supply voltage, or t h e supply current, or both, the current-driving capability of the gate d e c r e a s e s . This in turn results in longer times to c h a r g e and d i s c h a r g e the load and parasitic capacitances, and thus t h e p r o p a g a t i o n delay increases. It follows that a figureof-merit for c o m p a r i n g logic-circuit t e c h n o l o g i e s (or families) is t h e d e l a y - p o w e r product, defined as P
DP = P t
(10.5)
D P
where P
D
DESIGN A N D PERFORMANCE ANALYSIS OF THE CMOS
10.2
CIRCUITS
is the p o w e r dissipation of t h e gate. N o t e that DP has t h e units of j o u l e s . T h e
l o w e r t h e DP figure for a logic family, t h e m o r e effective it is. S i l i c o n A r e a A n o b v i o u s objective in t h e design of digital V L S I circuits is t h e minimiza tion of silicon area p e r logic gate. S m a l l e r area r e q u i r e m e n t enables the fabrication of a larger n u m b e r of gates p e r chip, w h i c h h a s e c o n o m i c and s p a c e a d v a n t a g e s from a systemdesign standpoint. A r e a reduction occurs in three different w a y s : t h r o u g h a d v a n c e s in pro cessing t e c h n o l o g y that enable t h e r e d u c t i o n of t h e m i n i m u m device size, t h r o u g h advances in circuit-design t e c h n i q u e s , and t h r o u g h careful chip layout. In this b o o k , our interest lies in circuit design, and w e shall m a k e frequent c o m m e n t s o n the relationship b e t w e e n the circuit design and its silicon area. A s a general rule, t h e simpler t h e circuit, the smaller the area required. A s will b e seen shortly, the circuit designer has to decide o n device sizes. Choosing smaller devices has the obvious a d v a n t a g e of requiring smaller silicon area and at the same t i m e r e d u c i n g parasitic capacitances and thus increasing speed. S m a l l e r devices, however, h a v e l o w e r current-driving capability, w h i c h tends to increase delay. T h u s , as in all engi n e e r i n g design p r o b l e m s , there is a trade-off to b e quantified and exercised in a m a n n e r that o p t i m i z e s w h a t e v e r aspect of the design is t h o u g h t to b e critical for the application at hand. F a n - I n a n d F a n - O u t T h e fan-in of a gate is the n u m b e r of its inputs. T h u s , a four-input N O R gate has. a fan-in of 4. F a n - o u t is t h e m a x i m u m n u m b e r of similar gates that a gate can drive while remaining within guaranteed specifications. As an example, w e saw in Section 4.10 that increasing the fan-out of the B J T inverter reduces V and hence NM . In this case, to keep NM a b o v e a certain m i n i m u m , t h e fan-out h a s to b e limited to a calculable m a x i m u m value. 0H
H
INVERTER
according to a pattern specified by the user to implement the u s e r ' s particular functional need. A m o r e recently available t y p e of gate array, k n o w n as a field-programmable gate array ( F P G A ) , can, as its n a m e indicates, be p r o g r a m m e d directly b y the user. F P G A s p r o v i d e a very c o n v e n i e n t m e a n s for the digital-system designer to i m p l e m e n t c o m p l e x logic functions in V L S I form w i t h o u t h a v i n g to incur either the cost or the "turnaround t i m e " inherent in custom and, to a lesser extent, in semicustom I C design [see B r o w n and R o s e (1996)].
10.1.4 Design Abstraction and Computer Aids The design of very c o m p l e x digital systems, whether on a single I C chip or using off-the-shelf c o m p o n e n t s , is m a d e possible b y the use of different levels of design abstraction, and t h e use of a variety of c o m p u t e r aids. T o appreciate the c o n c e p t of design abstraction, consider the process of designing a digital s y s t e m using off-the-shelf p a c k a g e s of logic gates. T h e designer consults data sheets (and b o o k s ) to d e t e r m i n e the input and output characteristics of the gates, their fan-in a n d fan-out limitations, and so on. In connecting the gates, t h e designer n e e d s to adhere to a set of rales specified b y t h e manufacturer in the data sheets. T h e designer d o e s n o t n e e d to consider, in a direct w a y , the circuit inside the gate p a c k a g e . In effect, t h e circuit has b e e n abstracted in t h e form of a functional b l o c k that can b e u s e d as a component. T h i s greatly simplifies system design. T h e digital-IC designer follows a similar process. Circuit b l o c k s are designed, characterized, a n d stored in a library as standard cells. These cells can t h e n b e u s e d b y the I C designer to a s s e m b l e a larger s u b s y s t e m (e.g., an adder or a multiplier), w h i c h in turn is characterized and stored as a functional b l o c k to b e used in the design of an e v e n larger system (e.g., an entire processor). At every level of design abstraction, the n e e d arises for simulation and other c o m p u t e r programs that h e l p m a k e the design process as a u t o m a t e d as possible. W h e r e a s S P I C E is employed in circuit simulation, other software tools are utilized at other levels and in other phases of the design p r o c e s s . A l t h o u g h digital-system design and design automation are out side the s c o p e of this b o o k , it is important that t h e reader appreciate the role of design abstraction a n d c o m p u t e r aids in digital design. T h e y are w h a t m a k e it h u m a n l y possible to design a 100-million-transistor digital I C . Unfortunately, analog I C design does not lend itself to the s a m e level of abstraction and a u t o m a t i o n . E a c h analog I C to a large extent h a s to be "handcrafted." A s a result, the c o m p l e x i t y and density of analog I C s r e m a i n m u c h b e l o w what is possible in a digital I C . W h a t e v e r a p p r o a c h or style is adopted in digital design, s o m e familiarity with die various digital-circuit technologies and design techniques is essential. This chapter and the next a i m to provide such a b a c k g r o u n d .
H
10.1.3 Styles for Digital System Design T h e c o n v e n t i o n a l a p p r o a c h to d e s i g n i n g digital s y s t e m s consists of a s s e m b l i n g the system u s i n g standard I C p a c k a g e s of various levels of c o m p l e x i t y (and h e n c e integration). M a n y s y s t e m s h a v e been built this w a y using, for e x a m p l e , T T L S S I and M S I p a c k a g e s . T h e a d v e n t of V L S I , in addition to p r o v i d i n g t h e s y s t e m designer with m o r e powerful off-theshelf c o m p o n e n t s such as m i c r o p r o c e s s o r s and m e m o r y chips, h a s m a d e possible alternative design styles. O n e such alternative is to o p t for i m p l e m e n t i n g part or all of t h e s y s t e m using o n e or m o r e custom VLSI chips. H o w e v e r , c u s t o m I C design is usually e c o n o m i c a l l y justi fied only w h e n the production v o l u m e is large (greater than about 100,000 parts). A n intermediate approach, k n o w n as semicustom design, utilizes gate-array chips. These are integrated circuits containing 100,000 or m o r e u n c o n n e c t e d logic gates. Their intercon nection can be achieved b y a final metallization step (performed at the I C fabrication facility)
'
10.2 DESIGN AND PERFORMANCE ANALYSIS OF THE CMOS INVERTER
The C M O S logic inverter w a s introduced and studied in Section 4.10, w h i c h w e u r g e the reader to r e v i e w before p r o c e e d i n g any further. In this section, w e take a m o r e c o m p r e h e n sive look at t h e inverter, investigating its p e r f o r m a n c e and exploring the trade-offs available in its design. T h i s material will serve as the foundation for t h e study of C M O S logic circuits in the following section.
10.2.1 Circuit Structure The inverter circuit, s h o w n in Fig. 10.4(a), consists of a pair of c o m p l e m e n t a r y M O S F E T s switched by the input v o l t a g e v Although not s h o w n , the source of each device is connected P
9 5 6
CHAPTER 10
10.2
DIGITAL C M O S LOGIC CIRCUITS
DESIGN A N D PERFORMANCE ANALYSIS O FTHE C M O S
INVERTER
Slope = - 1 A
-o %
V[ o -
FIGURE 1 0 . 4 (a) The CMOS inverter and (b) its representation as a pair of switches oper ated in a complementary fashion.
(b)
(a)
to its b o d y , thus eliminating t h e b o d y effect. U s u a l l y , t h e threshold voltages V a n d V are tn
e q u a l i n m a g n i t u d e ; that is, V
tp
FIGURE 1 0 . 5 The voltage transfer charac teristic (VTC) of the CMOS inverter when Q and Q are matched.
= \V \ = V , w h i c h is i n t h e r a n g e of 0.2 V to 1 V , with val
tn
tp
t
u e s n e a r t h e l o w e r e n d of this r a n g e for m o d e r n p r o c e s s t e c h n o l o g i e s h a v i n g s m a l l feature
N
P
size (e.g., w i t h c h a n n e l length of 0.5 to 0.1 pm or less). T h e inverter circuit can b e represented b y a pair of switches operated in a complementary fashion, as s h o w n in Fig. 10.4(b). A s indicated, e a c h switch is m o d e l e d b y a finite on resistance, w h i c h is t h e source-drain resistance of the respective transistor, evaluated near j v \ = 0,
'DSN
'DSP
(10.6)
(v -v )
= 1/
DD
t
=V
0H
DD
t
(i.e., p /p
times)
p
Since p
n
is t w o
t w o to four t i m e s
(W/L) , n
?! - ?,(!). N o r m a l l y , t h e t w o d e v i c e s h a v e t h e s a m e c h a n n e l length, L, w h i c h is set at t h e m i n i m u m
DD
DD
DS
p
(10.7)
(V -V )
= 1/
= V , and t h e output n o d e is c o n n e c t e d to V through the resistance V = 0, and t h e output n o d e r p of t h e pull-up transistor Q . Similarly, with v, = V , v of t h e p u l l - d o w n transistor Q . T h u s , in is c o n n e c t e d to g r o u n d t h r o u g h t h e resistance r, o
to four t i m e s larger t h a n p , m a t c h i n g is a c h i e v e d b y m a k i n g (W/L) n
10.2.2 Static Operation W i t h vj = 0,v
T h u s a s y m m e t r i c a l transfer characteristic is o b t a i n e d w h e n the devices are d e s i g n e d t o h a v e equal t r a n s c o n d u c t a n c e p a r a m e t e r s , a condition w e refer t o as matching.
DS
P
DD
0 i
0
D S N
N
allowable for t h e given p r o c e s s t e c h n o l o g y . T h e m i n i m u m width of t h e N M O S transistor is usually o n e a n d a half t o t w o t i m e s L, a n d t h e w i d t h of t h e P M O S transistor t w o t o three times that. F o r e x a m p l e , for a 0 . 2 5 - ^ m process for w h i c h p /p n
0.375 J U M / 0 . 2 5 pm, a n d (W/L)
t h e steady state, n o direct-current path exists b e t w e e n V
a n d ground, a n d t h e static-current
DD
p
=3,L = 0.25 pm, (W/L)„ =
= 1.125 / i m / 0 . 2 5 pm. A s w e shall discuss shortly, if t h e
p
inverter is required to drive a relatively large capacitive load, t h e transistors a r e m a d e wider.
a n d t h e static-power dissipation are b o t h zero (leakage effects a r e usually negligibly small
H o w e v e r , to c o n s e r v e chip area, m o s t of t h e inverters w o u l d h a v e this " M I N I M U M s i z e . " F o r
particularly for large-feature-size d e v i c e s ) .
future p u r p o s e s , w e shall d e n o t e t h e (W/L) ratio of t h e N M O S transistor of this m i n i m u m -
T h e voltage transfer characteristic of t h e inverter is s h o w n i n F i g . 10.5, from w h i c h it is
size inverter b y n a n d t h e (W/L) ratio of t h e P M O S transistor b y p. Since t h e inverter area
c o n f i r m e d that t h e output voltage levels a r e 0 a n d V , a n d thus t h e output voltage s w i n g is
can b e r e p r e s e n t e d b y W L
the m a x i m u m p o s s i b l e . T h e fact that V
(n + p)L , a n d w e c a n u s e t h e factor (n + p) a s a p r o x y for area. F o r t h e e x a m p l e cited earlier,
DD
and V
0L
a r e i n d e p e n d e n t of d e v i c e d i m e n s i o n s
0H
m a k e s C M O S v e r y different from other forms of M O S logic.
n=\.5,p
T h e C M O S inverter c a n b e m a d e t o s w i t c h at t h e m i d p o i n t of t h e logic s w i n g , 0 t o V , DD
that i s , at V /2, DD
b y appropriately sizing
the transistors.
n
Specifically, it can b e s h o w n that
n
+ WL p
p
= (W„ + W )L, t h e area of t h e m i n i m u m - s i z e inverter is P
= 4 . 5 , a n d t h e area factor n +p = 6.
B e s i d e s p l a c i n g t h e gate threshold at t h e center of t h e logic swing, m a t c h i n g t h e t r a n s c o n d u c t a n c e p a r a m e t e r s of Q a n d Q p r o v i d e s t h e inverter w i t h e q u a l current-driving N
t h e s w i t c h i n g t h r e s h o l d V (or V ) is g i v e n b y th
\v, \
V,
P
capability i n b o t h directions (pull-up a n d p u l l - d o w n ) . F u r t h e r m o r e , a n d o b v i o u s l y related, it
M
P
1 +
+Jkyk v P
tn
(10.8)
makes r
DSN
delays, t
PLH
Jk /k
=r . DSP
and
T h u s a n inverter with m a t c h e d transistors will h a v e e q u a l p r o p a g a t i o n t . PHL
n
W h e n t h e inverter threshold is at V /2, DD
w h e r e k = k'„(W/L) n
n
V,n = \V \, V tp
th
and k = k' (W/L) ,
= V /2 DD
p
p
p
from w h i c h w e see that for t h e typical case w h e r e
t h e n o i s e m a r g i n s NM and NM are equalized, H
L
and their v a l u e s are m a x i m i z e d , such that (Section 4.10):
for k = *„, that is, n
k' (W/L)„ n
=
k' (W/L) p
p
(10.9)
NM =NM H
L
= \(V
DD
+ \V ) t
(10.11)
CHAPTER 10
DIGITAL C M O S LOGIC CIRCUITS
10.2
DESIGN A N D P E R F O R M A N C E ANALYSIS O F T H E C M O S INVERTER
S i n c e typically V = 0.1 t o 0.2 V , t h e noise m a r g i n s a r e a p p r o x i m a t e l y 0.4 V . T h i s value, b e i n g close t o half t h e p o w e r - s u p p l y voltage, m a k e s t h e C M O S inverter nearly ideal from a n o i s e - i m m u n i t y standpoint. Further, since t h e inverter d c input current is practically zero, t h e noise m a r g i n s are n o t d e p e n d e n t o n t h e gate fan-out. A l t h o u g h w e h a v e e m p h a s i z e d t h e a d v a n t a g e s of m a t c h i n g Q a n d Q , t h e r e a r e occa sions in w h i c h this scaling is n o t adopted. O n e m i g h t , for instance, forgo t h e a d v a n t a g e s of m a t c h i n g in return for r e d u c i n g c h i p area a n d s i m p l y m a k e (W/L) = (W/L) . T h e r e are also instances in w h i c h a deliberate m i s m a t c h is used t o place V at a specified v a l u e other than V /2. N o t e that b y m a k i n g k > k , V m o v e s closer t o zero, w h e r e a s k > k„ m o v e s V closer t o V .
Fig. 10.6 to t h e value of the equivalent load c a p a c i t a n c e C:
A s a final c o m m e n t o n t h e inverter V T C , w e note that t h e slope in t h e transition region,
dbl
t
DD
DD
N
1. T h e g a t e - d r a i n overlap capacitance of Q C , c a n b e replaced b y a n equivalent c a p a c i t a n c e b e t w e e n the output n o d e a n d g r o u n d of 2C . T h e factor 2 arises b e c a u s e of the M i l l e r effect (Section 6.4.4). Specifically, n o t e that as v, goes h i g h a n d v goes l o w b y t h e s a m e a m o u n t , the c h a n g e in voltage across C is twice that a m o u n t . T h u s t h e output n o d e sees in effect twice t h e value of C T h e s a m e applies for t h e g a t e drain overlap c a p a c i t a n c e of Q , C , w h i c h c a n b e replaced b y a c a p a c i t a n c e 2C b e t w e e n t h e output n o d e a n d ground. u
gdl
0
p
p
gdl
gdh
n
2
th
DD
n
p
th
p
+
mN
oN
gd2
2. E a c h of t h e d r a i n - b o d y capacitances C and C h a s a terminal at a constant volt age. T h u s for t h e p u r p o s e of o u r analysis h e r e , C and C can b e replaced with equal capacitances b e t w e e n t h e output n o d e a n d ground. N o t e , h o w e v e r , that the for m u l a s given in Section 4 . 8 for calculating C and C a r e small-signal relation ships, w h e r e a s t h e analysis h e r e is obviously a large-signal one. A t e c h n i q u e has b e e n d e v e l o p e d for finding equivalent large-signal values for C and C [see H o d g e s a n d J a c k s o n (1988) a n d R a b a e y ( 2 0 0 2 ) ] . dhl
g )(r //r ). mP
gd2
th
DD
t h o u g h large, is finite a n d is given b y -(g
gdl
oP
db2
db2
dbl
10.2.3 Dynamic Operation
dbl
T h e p r o p a g a t i o n delay, of t h e inverter is usually d e t e r m i n e d u n d e r t h e condition that it is driving a n identical inverter. This situation is d e p i c t e d in F i g . 10.6. W e wish t o a n a l y z e this circuit t o d e t e r m i n e t h e propagation delay of t h e inverter c o m p r i s i n g Q a n d Q , w h i c h is driven b y a l o w - i m p e d a n c e source v a n d is l o a d e d b y t h e inverter c o m p r i s i n g Q a n d Q . Indicated i n t h e figure are t h e v a r i o u s transistor internal capacitances that a r e c o n n e c t e d to t h e output n o d e of t h e (Q Q ) inverter. O b v i o u s l y , a n exact p e n c i l - a n d - p a p e r analysis of this circuit will b e t o o c o m p l i c a t e d t o y i e l d useful design insight, a n d a simplification of the circuit is in order. Specifically, w e w i s h t o r e p l a c e all t h e c a p a c i t a n c e s attached to t h e inverter output n o d e w i t h a single c a p a c i t a n c e C c o n n e c t e d b e t w e e n t h e output n o d e and ground. If w e a r e able to d o that, w e c a n utilize t h e results of t h e transient analysis per formed i n Section 4.10. T o w a r d that end, w e n o t e that during t or t , t h e o u t p u t of the first inverter changes from 0 to V /2 o r from V to V /2, respectively. It follows that the s e c o n d inverter r e m a i n s i n t h e s a m e state d u r i n g e a c h of o u r analysis intervals. T h i s obser vation will h a v e a n important b e a r i n g o n o u r estimation of the equivalent input capacitance of t h e s e c o n d inverter. L e t ' s n o w c o n s i d e r t h e contribution of e a c h of t h e capacitances in x
b
u
db2
3. Since t h e s e c o n d inverter does n o t switch states, w e will a s s u m e that t h e input c a p a c itances of Q a n d Q r e m a i n a p p r o x i m a t e l y constant a n d equal t o t h e total gate c a p a c itance (WLC +C + C ). T h a t is, t h e input capacitance of t h e load inverter will b e
2
3
db2
3
4
4
0X
gsov
gdov
2
PLH
DD
DD
PHL
^«3
+
=
(WL)iC
0X
+ (WL) C 4
+C
0X
+C
gsov3
+C
g d o v 3
g s o v 4
+C
g d o v 4
4. T h e last c o m p o n e n t of C is t h e wiring c a p a c i t a n c e C , w h i c h simply adds t o t h e v a l u e of C. w
Thus, t h e total value of C is given b y
DD
C
=
2C
gdl
+ 2C
gd2
+C
dbl
+C
+C
db2
g3
+C
g4
+C
(10.12)
w
Having d e t e r m i n e d a n a p p r o x i m a t e value for t h e equivalent capacitance b e t w e e n t h e inverter output n o d e a n d g r o u n d , w e c a n utilize t h e circuits in F i g . 10.7 to d e t e r m i n e t n and t , respectively. S i n c e t h e t w o circuits a r e similar, w e n e e d only consider o n e a n d apply t h e result directly to t h e other. C o n s i d e r the circuit in F i g . 10.7(a), w h i c h applies w h e n v goes h i g h a n d Q discharges C from its initial v o l t a g e of V t o t h e final value of 0. T h e analysis is s o m e w h a t c o m p l i c a t e d b y t h e fact that initially Q will b e in t h e saturation m o d e and then, w h e n v falls b e l o w V - V„ it will g o into t h e triode region of operation. W e h a v e in fact p e r f o r m e d this analysis in Section 4.10 a n d o b t a i n e d t h e following approxi mate expression for t : P
L
PLH
I
N
DD
N
0
DD
PHL
1.6C
(10.13)
< 7 > where w e h a v e a s s u m e d that V, = 0.2 V , w h i c h is typically t h e case. DD
T h e r e is a n alternative, a n a p p r o x i m a t e b u t simpler, m e t h o d for analyzing t h e circuit i n Fig. 10.7(a). It i s b a s e d o n c o m p u t i n g a n a v e r a g e v a l u e for t h e discharge current i during the interval t = 0 t o t = t . Specifically, at t = 0, Q will b e saturated, a n d i (0) is g i v e n by m
PHL
FIGURE 1 0 . 6 Circuit for analyzing the propagation delay of the inverter formed by <2i and Q , which i: driving an identical inverter formed by Q and Q . 2
3
4
N
W ( 0 ) = \K{j)
DN
(V -V f DD
t
(10.14)
,'
959
CHAPTER 10
DIGITAL C M O S LOGIC
10.2
CIRCUITS
DESIGN A N DP E R F O R M A N C E ANALYSIS O F T H E C M O S INVERTER
A n e x p r e s s i o n for t h e low-to-high inverter delay, t ,
c a n b e written b y analogy t o t h e
PLH
t
pHL
expression i n E q . (10.17), 1.7C
(10.19)
Finally, t h e p r o p a g a t i o n delay t c a n b e found a s t h e a v e r a g e of t P
PHL
h
=
\(?PHL
+
and
t , PLH
l
PLH)
E x a m i n a t i o n of t h e formulas i n E q s . (10.18) a n d (10.19) enables u s to m a k e a n u m b e r of useful o b s e r v a t i o n s : 1. A s e x p e c t e d , t h e t w o c o m p o n e n t s of t c a n b e equalized b y selecting t h e (W/L) ratios P
0-,
vi
to equalize k and k , that is, b y m a t c h i n g Q and Q . n
p
N
P
"DD'
2. Since t is p r o p o r t i o n a l t o C, t h e designer should strive to r e d u c e C. T h i s is a c h i e v e d P
by u s i n g t h e m i n i m u m possible c h a n n e l length and b y m i n i m i z i n g wiring a n d other parasitic c a p a c i t a n c e s . Careful layout of t h e chip c a n result in significant reduction in
c—
s u c h c a p a c i t a n c e s a n d i n t h e v a l u e of C . db
0
tpLH
3. U s i n g a p r o c e s s t e c h n o l o g y with larger t r a n s c o n d u c t a n c e p a r a m e t e r k' c a n result i n shorter p r o p a g a t i o n delays. K e e p i n m i n d , h o w e v e r , that for s u c h p r o c e s s e s C
ox
is
increased, a n d t h u s t h e v a l u e of C increases at t h e s a m e time.
(b)
4. U s i n g larger (W/L) ratios c a n result i n a r e d u c t i o n in t . Care, h o w e v e r , should b e P
F I G U R E 1 0 . 7 Equivalent circuits for determining the propagation delays (a) t
PHL
and (b)
t
PLH
of the
inverter.
exercised h e r e also, since increasing t h e size of t h e devices increases t h e v a l u e of C, and t h u s t h e e x p e c t e d r e d u c t i o n i n t m i g h t n o t m a t e r i a l i z e . R e d u c i n g t b y i n c r e a s P
P
i n g (W/L), h o w e v e r , is a n effective strategy w h e n C is d o m i n a t e d b y c o m p o n e n t s n o t At t = t , PHL
Q will b e i n t h e triode r e g i o n , a n d i (t ) N
DN
will b e
PHL
directly related t o t h e size of the driving d e v i c e (such as wiring or fan-out devices). 5. A l a r g e r s u p p l y v o l t a g e V
DD
,(W
(V
l( DD^ V
-V\^DD
results i n a l o w e r t . H o w e v e r , V P
DD
is d e t e r m i n e d b y t h e
2
(10.15)
p r o c e s s t e c h n o l o g y a n d thus is often n o t u n d e r t h e control of t h e designer. Further m o r e , m o d e r n p r o c e s s t e c h n o l o g i e s i n w h i c h d e v i c e sizes are r e d u c e d r e q u i r e l o w e r V
T h e a v e r a g e discharge current c a n then b e found a s
DD
(see Table 6.1). A motivating factor for lowering V
DD
is the need to k e e p t h e
d y n a m i c p o w e r dissipation at acceptable levels, especially in very-high-density chips. (10.16)
W e will h a v e m o r e to say o n this p o i n t shortly. T h e s e o b s e r v a t i o n s clearly illustrate t h e conflicting r e q u i r e m e n t s a n d t h e trade-offs avail
and t h e d i s c h a r g e interval t
PHL
c o m p u t e d from CAV
able in t h e d e s i g n of a C M O S digital integrated circuit ( a n d i n d e e d i n a n y engineering _
l
DN\
design p r o b l e m ) .
CV /2 DD
(10.17)
l
DN\
10.2.4 Dynamic Power Dissipation
Utilizing E q s . (10.14) t h r o u g h (10.17) a n d substituting V = 0.2 V t
t PHT.
DD
gives
T h e negligible static p o w e r dissipation of C M O S h a s b e e n a significant factor in its d o m i n a n c e as t h e t e c h n o l o g y of c h o i c e in i m p l e m e n t i n g high-density V L S I circuits. H o w e v e r , as
1.7C
(10.18)
='
the n u m b e r of gates p e r c h i p steadily increases, t h e d y n a m i c p o w e r dissipation h a s b e c o m e a serious issue. T h e d y n a m i c p o w e r dissipated i n t h e C M O S inverter is given b y E q . (10.4), which w e repeat here as
w h i c h yields a v a l u e very close t o that o b t a i n e d b y t h e m o r e p r e c i s e f o r m u l a of E q . (10.13).
P
D
W h i c h f o r m u l a t o u s e is n o t very relevant, for w e h a v e a l r e a d y m a d e m a n y a p p r o x i m a t i o n s . I n d e e d , o u r interest in t h e s e formulas is n o t in o b t a i n i n g a precise v a l u e of t
PHL
b u t in w h a t
= fCVlo
(10.20)
w h e r e / is t h e frequency at w h i c h t h e gate is switched. It follows that m i n i m i z i n g C is a n
they tell u s about the effect of t h e v a r i o u s e l e m e n t s o n d e t e r m i n i n g t h e inverter delay. It is
effective m e a n s for reducing d y n a m i c - p o w e r dissipation. A n even m o r e effective strategy is
s u c h insight that t h e circuit d e s i g n e r h o p e s to g l e a n from m a n u a l analysis. Precise values for
the use of a l o w e r power-supply voltage. A s w e have mentioned, n e w C M O S process technol
delay c a n b e d e t e r m i n e d using c o m p u t e r s i m u l a t i o n (Section 10.7).
ogies utilize V
DD
values as l o w as 1 V . T h e s e n e w e r chips, however, pack m u c h m o r e circuitry
961
962
CHAPTER 10
D I G I T A L C M O S LOGIC CIRCUITS
10.3
o n t h e chip (as m a n y a s 100 million transistors) a n d o p e r a t e at h i g h e r frequencies (micro-
C M O S LOGIC-GATE CIRCUITS
'
963
and
processor clock frequencies above 1 G H z a r e n o w available). T h e d y n a m i c p o w e r dissipation of s u c h high-density chips c a n b e o v e r 100 W .
5
C(VDD/2) - —\
l
PHL
=
;
'DAT |
6.25 x l Q - ' x 1.25 — — — ~ = 23.3 ps 6
3 4 9 x 10"
a v
Since W /W„ = 3 and pi„/pl = 3 . 8 3 , the inverter is not perfectly matched. Therefore, w e expect t to b e greater than t by a factor of 3 . 8 3 / 3 = 1.3, thus p
p
PLH
PHL
0
Consider a C M O S inverter fabricated in a 0.25-jUm process for which C
= 6 f F / t t n T , p„C
m
2
115 LiA/V ,
2
pC p
0X
= 30 pA/V ,
V = -V M
= 0.4 V, and V
tp
DD
t
-
0X
= 2.5 V. The W/L ratio of Q is N
P
L
H
1 . 3 x 2 3 . 3 = 30 p s
=
and thus t will b e P
0 . 3 7 5 ^ / 0 . 2 5 pm, and that for Q is 1.125 z i m / 0 . 2 5 pm. The gate-source and gate-drain overlap P
capacitances are specified t o b e 0.3 f¥/pm body capacitances are C
= 1 f F and C
dbn
tp
of gate width. Further, the effective value of d r a i n = 1 f F . The wiring capacitance C = 0.2 fF. Find
dbp
w
-
t
+
i( PHL
hm)
= 1(23.3 + 30) = 26.5 p s
t , PHL
t , and t . PLH
P
Solution First, w e determine the value of the equivalent capacitance C using Eq. (10.12), C = 2C
í á l
+ 2 Cgdl~ , +C £
d 2
d M
+C 10.1 Consider the inverter specified in Example 10.1 when loaded with an additional 0.1 -pF capacitance. What will'the propagation delay become?
where Cg
0.3 x W , = 0.3 x 0.375 = 0.1125 f F
c gd2
0.3 x W
Ans. 437 p s
C
p
= 0.3 x 1.125 = 0.3375 f F
10.2 In an attempt to decrease the area of the inverter in Example 10.1, (W/L) the percentage reduction in-area achieved? Find the new values of C:t does not change'significantly.
p
PHh
= 1 fF
dbl
C db2 ' C
g3
C
g4
1 fF
is made equal to (W/L) . What is r , and i . Assume that. C „ n
m /
P
Ans. 5 0 % ; 4.225 fF; 15.8 p s ; 20.5 ps; 18.1 p s
= 0.375 x 0.25 x 6 + 2 x 0.3 x 0.375 = 0.7875 fF = 1.125 x 0.25 x 6 + 2 x 0.3 x 1.125 = 2.3625 fF
10.3 For the inverter of Example 10.1, find the dynamic power dissipation when clocked at a 500-MHz rate. Ans. 19.5 fjW
C„. = 0.2 f F Thus, C = 2 x 0.1125 + 2 x 0.3375 + 1 + 1 + 0.7875 + 2.3625 + 0.2 = 6.25 f F
10.3
CMOS LOGIC-GATE CIRCUITS
Next, although w e can use the formula in Eq. (10.18) to determine t , w e shall take an alternaPHL
tive route. Specifically, w e shall consider the discharge of C through Q and determine the aver-
In this section, w e b u i l d o n o u r k n o w l e d g e of inverter design a n d consider t h e design of
age discharge current using Eqs. (10.14) through (10.16):
C M O S circuits that r e a l i z e c o m b i n a t i o n a l - l o g i c functions. I n c o m b i n a t i o n a l circuits, t h e
N
output at a n y t i m e is a function only of the v a l u e s of input signals at that time. T h u s , t h e s e
wo) = |*;(f)
circuits d o n o t h a v e m e m o r y a n d d o n o t e m p l o y feedback. C o m b i n a t i o n a l - l o g i c circuits a r e
(V -Vf DD
used in l a r g e quantities i n a m u l t i t u d e of a p p l i c a t i o n s ; indeed, every digital s y s t e m contains . 115f032f)(2.5-0.4) 0.25
2
X
DD
2
large n u m b e r s of c o m b i n a t i o n a l - l o g i c circuits.
10.3.1 Basic Structure
V
y.Vpp
(V
380 pA
=
1( DD 2{ 2
A C M O S logic circuit is i n effect a n extension, o r a generalization, of t h e C M O S inverter: The inverter consists of a n N M O S p u l l - d o w n transistor, a n d a P M O S p u l l - u p transistor,
=
115 x
0.375 (2.5-0.4)^-if^ 2 2\ 2 0.25
2
operated b y t h e i n p u t v o l t a g e i n a c o m p l e m e n t a r y fashion. T h e C M O S logic gate consists of
v
•- 318 pA
two n e t w o r k s : t h e p u l l - d o w n n e t w o r k ( P D N ) c o n s t r u c t e d of N M O S transistors, a n d t h e pullup n e t w o r k ( P U N ) c o n s t r u c t e d of P M O S transistors ( s e e F i g . 10.8). T h e t w o n e t w o r k s a r e operated b y t h e i n p u t v a r i a b l e s , i n a c o m p l e m e n t a r y fashion. T h u s , for t h e three-input g a t e
Thus
380 + 318
represented i n F i g . 10.8, t h e P D N will c o n d u c t for all i n p u t c o m b i n a t i o n s that r e q u i r e a l o w 349 pA
output (Y= 0 ) a n d will then pull t h e o u t p u t n o d e d o w n t o g r o u n d , c a u s i n g a zero v o l t a g e t o
db
CHAPTER 1 0 D I G I T A L C M O S L O G I C C I R C U I T S
v
10.3
DD
A c—j
Ao-
C M O S LOGIC-GATE CIRCUÍ
QA B O—I
B
QB
^-Í\_ZQB
PuJl-up network
B o-
C
(
>
H|ÍIOC
Co-o Y
o Y
o Y
-o Y
Y =A +B
AoB oCo-
Pull-doVW: l\H''"ik
(a)
(Pl)N)
FIGURE 1 0 . 1 0 FIGURE 1 0 . 8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.
y = AB "
(b)
Examples of pull-up networks.
will b e low w h e n A is high or B is high, which can b e expressed as Y =
a p p e a r at the output, v = 0. Simultaneously, t h e P U N will b e off, a n d n o direct d c path will exist b e t w e e n V a n d ground. O n t h e other hand, all input c o m b i n a t i o n s that call for a high output (Y= 1) will cause the P U N to conduct, a n d t h e P U N will t h e n pull t h e output n o d e up to V , estabhshing an output voltage v = V . Simultaneously, tire P D N will b e cut off, and again, n o d c current path b e t w e e n V a n d g r o u n d will exist in t h e circuit. N o w , since the P D N comprises N M O S transistors, and since an N M O S transistor conducts w h e n the signal at its gate is high, the P D N is activated (i.e., conducts) when the inputs are high. In a dual manner, the P U N comprises P M O S transistors, and a P M O S transistor conducts w h e n the input signal at its gate is low; thus the P U N is activated w h e n the inputs are low. T h e P D N and the P U N each utilizes devices in parallel to form an O R function, and devices in series to form an A N D function. Here, the O R a n d A N D notation refer to current flow or conduction. Figure 10.9 shows examples of P D N s . For the circuit in Fig. 10.9(a), we observe that Q will conduct w h e n A is high (v = V ) and will then pull the output node down to ground (v = 0 V , Y = 0). Similarly, Q conducts and pulls Y d o w n w h e n B is high. Thus Y Y
A+B
or equivalently
DD
DD
Y
DD
DD
A
A
Y
Y = A +B The P D N in F i g . 10.9(b) will conduct only w h e n A and B are both h i g h simultaneously. Thus F w i l l b e l o w w h e n A is h i g h and Bis high, Y = AB or equivalently Y = AB As a final e x a m p l e , t h e P D N in F i g . 10.9(c) will c o n d u c t a n d cause Y to b e 0 w h e n A is h i g h or w h e n B and C are both high, thus Y=A+BC
DD
B
or equivalently Y=A+BC Next c o n s i d e r the P U N e x a m p l e s s h o w n in Fig. 10.10. T h e P U N in Fig. 10.10(a) will conduct a n d pull Y u p to V (Y = 1) w h e n A is l o w or B is l o w , thus DD
-o Y
-oY -OY
A o—I
QA B
QA
BO—\
A oH
B o—I
QB
F = A + 5
Y = AB
(a)
(b)
FIGURE 1 0 . 9 Examples of pull-down networks.
The P U N in F i g . 10.10(b) will c o n d u c t a n d p r o d u c e a h i g h output (v = V , when A and B are b o t h l o w , thus Y
BO—\\ZQ
A o—I
Y = A +B
QA
Y= 1) only
Y = AB Cc—j^Tßc
Y =
DD
A+BC (c)
Finally, the P U N in F i g . 10.10(c) will c o n d u c t a n d cause Y to b e high (logic 1) if A is low or if B and C are both l o w , thus Y=A+BC Having developed an understanding and an appreciation of the structure a n d operation of PDNs and P U N s , w e n o w consider complete C M O S gates. Before doing so, however, w e wish to introduce alternative circuit symbols, that are almost universally used for M O S transistors b y
966
i
CHAPTER 10
DIGITAL CMOS
LOGIC
CIRCUITS
10.3
CMOS
LOGIC-GATE
CIRCUITS
VDD
A o
1
o
1
O
c|
A
0 - 0 |
50—0|
QPB -of
NMOS
PMOS
(a)
(b)
FIGURE 1 0 . 1 1
Usual and alternative circuit symbols for MOSFETs.
ao—I
digital-circuit designers. Figure 10.11 shows our usual symbols (left) and the corresponding "digital" s y m b o l s (right). O b s e r v e that the s y m b o l for the P M O S transistor with a circle at the gate terminal is intended to indicate that the signal at the gate has to b e low for the device to be activated (i.e., to conduct). T h u s , in t e r m s of logic-circuit terminology, the gate terminal of the P M O S transistor is an active low input. Besides indicating this property of P M O S devices, the digital symbols o m i t any indication of w h i c h of the device terminals is the source and w h i c h is the drain. This should, c a u s e n o difficulty at this stage of our study; simply r e m e m b e r that for an N M O S transistor, t h e drain is t h e terminal that is at the higher voltage (current flows from drain to source), and for a P M O S transistor the source is the terminal that is at the higher voltage (current flows from source to drain). T o b e consistent with the litera ture, w e shall henceforth use these modified symbols for M O S transistors in logic applica tions, except in locations w h e r e our usual s y m b o l s help in understanding circuit operation.
NA
Q
NB
FIGURE 1 0 . 1 2
Y = A + B
A two-input CMOS NOR gate.
VDD
A Ao—o|
A
Qp
flo-o|
A
QPB
-OY A o
10.3.2 The Two-Input NOR Gate
#o—|
Q
1
QNA
W e first consider t h e C M O S gate that realizes the two-input N O R function Bo Y = A + B
AB
(10.21)
W e see that Y is to b e l o w ( P D N c o n d u c t i n g ) w h e n A is h i g h or B is h i g h . T h u s the P D N consists of t w o parallel N M O S devices w i t h A a n d B as inputs (i.e., the circuit in F i g . 10.9a). F o r the P U N , w e n o t e from t h e s e c o n d e x p r e s s i o n in Eq. (10.21) that 7 is to b e h i g h w h e n A and B are b o t h low. T h u s t h e P U N consists of t w o series P M O S devices with A a n d B as the inputs (i.e., t h e circuit in Fig. 10.10b). Putting the P D N and the P U N together gives the C M O S N O R gate s h o w n in Fig. 10.12. N o t e that extension to a h i g h e r n u m b e r of inputs is straightforward: F o r each additional input, an N M O S transistor is added in parallel w i t h Q and Q , and a P M O S transistor is a d d e d in series with Q and Q . NA
NB
PA
PB
1
Q
NB
Y = AB
FIGURE 1 0 . 1 3 A two-input CMOS NAND gate.
second expression in E q . (10.22) as A low or B l o w . T h u s , t h e P U N consists of t w o parallel P M O S transistors w i t h A and B applied to their gates (such as t h e circuit in Fig. 10.10a). Putting the P D N a n d P U N together results in the C M O S N A N D gate i m p l e m e n t a t i o n s h o w n in Fig. 10.13. N o t e that extension to a h i g h e r n u m b e r of inputs is straightforward: F o r each additional input, w e add an N M O S transistor in series with Q and Q , a n d a P M O S tran sistor in parallel with Q and Q . NA
10.3.3 The Two-Snput NAND Gate
PA
NB
PB
T h e two-input N A N D function is described b y the B o o l e a n expression Y = AB =
A+B
(10.22)
10.3.4 A Complex Gate Consider n e x t t h e m o r e c o m p l e x logic function
T o synthesize the P D N , w e consider the input c o m b i n a t i o n s that require Y to b e l o w : T h e r e is only o n e such combination, n a m e l y , A and B b o t h high. T h u s , the P D N simply comprises t w o N M O S transistors in series (such as t h e circuit in Fig. 10.9b). T o synthesize the P U N , w e consider the input c o m b i n a t i o n s that result in Y being high. T h e s e are found from the
Y = A{B +
CD)
(10.23)
Since Y = A(B + CD), w e see that Y should b e l o w for A high and simultaneously either B high or C and D b o t h high, from w h i c h the P D N is directly obtained. T o obtain t h e P U N , w e
CHAPTER 1 0 D I G I T A L C M O S L O G I C C I R C U I T S
10.3
n e e d to e x p r e s s Y in t e r m s of t h e c o m p l e m e n t e d variables. W e d o this t h r o u g h repeated application of D e M o r g a n ' s law, as follows:
it should, h o w e v e r , b e m e n t i o n e d that at t i m e s it is not easy to obtain o n e of the t w o net works from t h e other u s i n g the duality property. F o r s u c h cases, o n e has to resort to a m o r e
Y =
rigorous p r o c e s s , w h i c h is b e y o n d the s c o p e of this b o o k [see K a n g and L e b l e b i c i ( 1 9 9 9 ) ] .
A(B+CD)
= A + B + CD =Ä
C M O S LOGIC-GATE CIRCUITS
+
10.3.6 The Exclusive-OR Function
BCD
An important function that often arises in logic design is t h e e x c l u s i v e - O R ( X O R ) function,
= Ä + B(V + D)
(10.24)
T h u s , Y is h i g h for A l o w or B l o w and either C or D l o w . T h e corresponding c o m p l e t e C M O S
Y = AB + AB
(10.25)
W e observe that since Y (rather than Y) is given, it is easier to synthesize the P U N . W e note, however, that unfortunately Y is n o t a function of the c o m p l e m e n t e d variables only (as w e
circuit will b e as s h o w n in Fig. 10.14.
would like it to b e ) . T h u s , w e will n e e d additional inverters. T h e P U N obtained directly from Eq. (10.25) is s h o w n in Fig. 10.15(a). N o t e that the Q
lt
Q b r a n c h realizes the first t e r m 2
10.3.5 Obtaining the PUN from the PDN and Vice Versa
(AB), w h e r e a s the Q , Q b r a n c h realizes t h e s e c o n d t e r m (AB). N o t e also t h e n e e d for t w o
F r o m t h e C M O S gate circuits c o n s i d e r e d thus far (e.g., that in F i g . 10.14), w e o b s e r v e that
additional inverters to g e n e r a t e A and B.
3
A
the P D N a n d t h e P U N are dual n e t w o r k s : W h e r e a series b r a n c h exists in o n e , a parallel
A s for synthesizing the P D N , w e c a n obtain it as t h e dual n e t w o r k of t h e P U N in
b r a n c h exists in t h e other. T h u s , w e c a n o b t a i n o n e from t h e other, a p r o c e s s that c a n b e sim
Fig. 10.15(a). Alternatively, w e c a n d e v e l o p an e x p r e s s i o n for Y and u s e it to synthesize the
pler t h a n h a v i n g to synthesize e a c h separately f r o m t h e B o o l e a n e x p r e s s i o n of t h e function.
PDN. L e a v i n g t h e first a p p r o a c h for the r e a d e r to d o as an exercise, w e shall utilize t h e
F o r instance, in t h e circuit of F i g . 10.14, w e found it relatively easy to obtain t h e P D N , sim
direct synthesis a p p r o a c h . D e M o r g a n ' s l a w can b e applied to t h e expression in E q . (10.25)
ply b e c a u s e w e already h a d Y in t e r m s of t h e u n c o m p l e m e n t e d inputs. O n t h e other hand, to
to obtain F as
obtain t h e P U N , w e h a d to m a n i p u l a t e t h e g i v e n B o o l e a n e x p r e s s i o n to express Y as a func
Y = AB + AB
tion of t h e c o m p l e m e n t e d variables; t h e f o r m c o n v e n i e n t for synthesizing P U N s . Alterna
(10.26)
tively, w e c o u l d h a v e u s e d this duality p r o p e r t y to obtain t h e P U N from the P D N . The
The c o r r e s p o n d i n g P D N will b e as in Fig. 10.15(b), w h i c h s h o w s the C M O S realization of
r e a d e r is u r g e d to refer to F i g . 10.14 to c o n v i n c e herself that this is i n d e e d p o s s i b l e .
the e x c l u s i v e - O R function e x c e p t for t h e t w o additional inverters. N o t e that the exclusiveOR requires 12 transistors for its realization, a rather c o m p l e x network. Later, in Section 10.5, we shall s h o w a simpler realization of the X O R e m p l o y i n g a different f o r m of C M O S logic. V
V
DD
A o—Cj
A o—o)
öi
B o—o|
02
DD
Ao-oj
03
A o—dl
A o—Oj
Bo—q
04
B o-<^
B o—c|
-OY
(a)
Y = A(B + CD)
FIGURE 1 0 . 1 4 plex gate.
CMOS realization of a com
-o Y
A o—I
A o—{
B o—I
B o—J
(b)
FIGURE 1 0 . 1 5 Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10.25). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (10.26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10.27).
\ •wr
969
10.3 9 7 0
CHAPTER 10
DIGITAL C M O S LOGIC
C M O S LOGIC-GATE
CIRCUITS
CIRCUITS
kv
DD
A n o t h e r interesting observation f o l l o w s from t h e circuit in F i g . 10.15(b). T h e P D N and t h e P U N h e r e are not d u a l n e t w o r k s . I n d e e d , duality of t h e P D N a n d t h e P U N is n o t a neces sary condition. T h u s , a l t h o u g h a dual of P D N (or P U N ) c a n a l w a y s b e u s e d for P U N (or
A o—
P D N ) , t h e t w o n e t w o r k s a r e n o t necessarily duals. B o—d[
10.3.7 Summary of the Synthesis Method
Ap
1. T h e P D N c a n b e m o s t directly s y n t h e s i z e d b y e x p r e s s i n g Y as a function of the uncomplemented
Co—Oj
variables. If c o m p l e m e n t e d variables a p p e a r in this expression,
additional inverters will b e r e q u i r e d to g e n e r a t e t h e m . 2. T h e P U N c a n b e m o s t directly s y n t h e s i z e d b y e x p r e s s i n g Y as a function of the com plemented
4p
variables a n d t h e n a p p l y i n g t h e u n c o m p l e m e n t e d variables to t h e gates of -o
the P M O S transistors. If u n c o m p l e m e n t e d variables a p p e a r in t h e expression, addi
Y= A + B + C + D
tional inverters will b e n e e d e d . 3. T h e P D N c a n b e obtained from t h e P U N (and v i c e v e r s a ) u s i n g t h e duality property. A
10.3.8 Transistor Sizing
1
o
o—I B
o—I
C
D
O n c e a C M O S gate circuit h a s b e e n generated, t h e only significant step r e m a i n i n g in the d e s i g n is t o d e c i d e on W/L ratios for all d e v i c e s . T h e s e ratios usually a r e selected t o provide t h e g a t e w i t h current-driving capability i n b o t h directions e q u a l t o that of t h e b a s i c inverter. T h e r e a d e r will recall from Section 10.2 that for t h e b a s i c inverter design, w e denoted
F I G U R E 1 0 . 1 6 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of Q and Q , respectively, of the basic inverter. N
(W/L)
n
= n a n d (W/L)
(pi /p )n. n
p
p
P
= p, w h e r e n is usually 1.5 t o 2 and, for a m a t c h e d design, p =
T h u s , w e w i s h t o select individual W/L ratios for all transistors in a logic gate so
that t h e P D N should b e able t o p r o v i d e a c a p a c i t o r discharge current at least e q u a l t o that of
resulting in t h e following expression for (W/L)
eq
for transistors c o n n e c t e d i n series:
an N M O S transistor w i t h W/L = n, a n d t h e P U N s h o u l d b e able t o p r o v i d e a charging current at least e q u a l to that of a P M O S transistor with W/L = p. This will guarantee a worst-case
g a t e delay e q u a l t o that of t h e b a s i c inverter.
(W/L)
= —
sq
1
In t h e preceding description, t h e idea of " w o r s t c a s e " should b e emphasized. It m e a n s that
(W/L)/
(10.27) +
(W/L)
2
" '
in deciding o n device sizing, w e should find t h e input combinations that result in the lowest output current and then c h o o s e sizes that will m a k e this current equal to that of t h e basic
Similarly, w e c a n show that t h e parallel connection of transistors with W/L ratios of
inverter. B e f o r e w e consider e x a m p l e s , w e n e e d t o address t h e issue of d e t e r m i n i n g the
(W/L) , 2
(W/L),,
• • •, results in a n equivalent W/L of
current-driving capability of a circuit consisting of a n u m b e r of M O S devices. In other words, w e n e e d t o find t h e equivalent
(W/L)
W/L ratio of a n e t w o r k of M O S transistors. T o w a r d that end,
e q
= . ( W / L ) ! + (W/L)
2
+ •••
(10.28)
w e consider t h e parallel and series connection of M O S F E T s a n d find the equivalent W/L ratios. T h e derivation of t h e e q u i v a l e n t W/L ratio is b a s e d o n t h e fact that t h e o n r e s i s t a n c e of a M O S F E T is inversely p r o p o r t i o n a l t o W/L. T h u s , if a n u m b e r of M O S F E T s h a v i n g ratios of (W/L) , x
(W/L) , 2
. . . are c o n n e c t e d in series, t h e e q u i v a l e n t series resistance obtained by
A s an e x a m p l e , t w o identical M O S transistors w i t h individual W/L ratios of 4 result i n an equivalent W/L of 2 w h e n c o n n e c t e d in series a n d of 8 w h e n c o n n e c t e d in parallel. A s an e x a m p l e of p r o p e r sizing, c o n s i d e r t h e four-input N O R in F i g . 10.16. H e r e , t h e worst case (the l o w e s t current) for t h e P D N is obtained w h e n only o n e of t h e N M O S transis
a d d i n g t h e on-resistances will b e
tors is c o n d u c t i n g . W e therefore select t h e W/L of e a c h N M O S transistor t o b e e q u a l t o that ^series
r
DSl
=
r
+ DS2
+ ' ' "
of the N M O S transistor of t h e basic inverter, n a m e l y , n. F o r t h e P U N , h o w e v e r , t h e Worst-
_ constant
constant
(W/L)
(W/L)
x
case situation (and i n d e e d t h e only case) is w h e n all inputs are l o w a n d t h e four series P M O S
+
transistors a r e c o n d u c t i n g . S i n c e t h e e q u i v a l e n t W/L will b e o n e - q u a r t e r of that of e a c h
2
v
= constant I (W/L), _
constant
~
(W/L)
(W/L)
2
v• • • J
P M O S d e v i c e , w e s h o u l d select the W/L ratio of e a c h P M O S transistor t o b e four t i m e s that of Q of t h e b a s i c inverter, that is, Ap. P
A s another e x a m p l e , w e s h o w in F i g . 10.17 t h e p r o p e r sizing for a four-input N A N D gate. C o m p a r i s o n of t h e N A N D a n d N O R g a t e s in Figs. 10.16 and 10.17 indicates that
eq
b e c a u s e p is u s u a l l y t w o t o three times n, t h e N O R gate will r e q u i r e m u c h greater area than the N A N D gate. F o r this reason, N A N D gates a r e generally preferred for i m p l e m e n t i n g 1
This statement assumes that the total effective capacitance C of the logic gate is the same as that of the inverter. In actual practice, the value of C will be larger for a gate, especially as the fan-in is increased.
c o m b i n a t i o n a l logic functions in C M O S .
972
CHAPTER 10
DIGITAL C M O S LOGIC
CIRCUITS
10.3
"DD
A
O—0|
P
P
O—Oj
V
DD
O—Oj
P
o—C\ D
c
B
C M O S LOGIC-GATE CIRCUITS
D o—0|
QPD (3.75/0.25)
(1.875/0.25) co—o|
Qpc (3.75/0.25)
QPB
B P—Oj
-oY = ABCD An
B o-—j
An
j
An
CO
A O—o|
UFA (3.75/0.25) -07
2^(0.75/0.25)
5
°H
Do
|
An
A
o—l
Q
NA
(0.375/0.25)
Co—I
QNC
FIGURE 1 0 . 1 7 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of Q and Q , respectively, of the basic inverter. N
Q
ND
(0.75/0.25)
(0.75/0.25)
P
FIGURE 1 0 . 1 8
Circuit for Example 10.2.
Finally, the W/L ratio for Q should be selected so that the equivalent W/L of the series connec tion of Q and Q should b e equal to p. It follows that for Q the ratio should be 1.5/?, PB
Provide transistor W/L ratios for the logic circuit shown in Fig. 10.18. Assume that for the basic inverter n = 1.5 and p = 5 and that the channel length is 0.25 pm.
PB
PA
PB
Q: PB
W/L = 1.5p = 7.5 = 1.875/0.25
Figure 10.18 shows the circuit with the transistor sizes indicated.
Solution Refer to Fig. 10.18, and consider the P D N first. W e note that the worst case occurs when Q is on and either Q or Q is on. That is, in the worst case, w e have two transistors in series. Therefore, w e select each of Q , Q , and Q to have twice the width of the n-channel device in the basic inverter, thus NB
NC
ND
NB
NC
10.3.9 Effects of Fan-In and Fan-Out on Propagation Delay
ND
QNB
W/L = In = 3 = 0 . 7 5 / 0 . 2 5
QNC
W/L
=2n = 3 = 0 . 7 5 / 0 . 2 5
W/L
= 2n = 3 = 0 . 7 5 / 0 . 2 5
E a c h additional input t o a C M O S gate requires t w o additional transistors, o n e N M O S a n d one P M O S . T h i s is in contrast t o other forms of M O S logic, w h e r e each additional input requires only o n e additional transistor. T h e additional transistor i n C M O S n o t only increases the chip area b u t also increases t h e total effective capacitance p e r gate a n d in turn increases the p r o p a g a t i o n delay. T h e size-scaling m e t h o d described earlier c o m p e n s a t e s for s o m e (but not all) of the increase i n t . Specifically, b y increasing device size, w e a r e able t o p r e s e r v e the current-driving capability. H o w e v e r , t h e capacitance C increases b e c a u s e of b o t h t h e increased n u m b e r of inputs and t h e increase in device size. T h u s t will still increase w i t h fan-in, a fact that i m p o s e s a practical limit on t h e fan-in of, say, t h e N A N D gate t o about 4 . If a h i g h e r n u m b e r of inputs is required, then "clever" logic design should b e a d o p t e d to realize t h e g i v e n B o o l e a n function w i t h gates of n o m o r e than four inputs. T h i s w o u l d usually m e a n a n increase in t h e n u m b e r of c a s c a d e d stages a n d thus an increase i n delay. H o w e v e r , such a n increase in delay c a n b e less than t h e increase d u e t o t h e large fan-in (see P r o b l e m 10.36). A n i n c r e a s e in a g a t e ' s fan-out adds directly t o its load capacitance and, thus, increases its p r o p a g a t i o n delay. P
For transistor Q , select W/L to be equal to that of the w-channel device in the basic inverter: NA
W/L
QA
1.5 = 0 . 3 7 5 / 0 . 2 5
Next, consider the PUN. Here, w e see that in the worst case, w e have three transistors in series: Q , Q , and Q . Therefore, w e select the W/L ratio of each of these to be three times that of Q in the basic inverter, that is, 3p, thus PA
PC
PD
P
Q:
W/L = 3p = 15 = 3 . 7 5 / 0 . 2 5
Q:
W/L =3p=15
Q:
W/L = 3p = 15 = 3 . 7 5 / 0 . 2 5
PA
PC
PD
= 3.75/0.25
P
Zijà
973
I
CHAPTER 10
10.4
DIGITAL C M O S LOGIC CIRCUITS
T h u s although C M O S has m a n y a d v a n t a g e s , it does suffer from i n c r e a s e d circuit c o m
DD
plexity w h e n the fan-in and fan-out are increased, and from the c o r r e s p o n d i n g effects of this
P S E U D O - N M O S LOGIC CIRCUITS
VDD
A
V
DD
A
c o m p l e x i t y o n b o t h chip area and p r o p a g a t i o n delay. In the following t w o sections, w e shall
A
study s o m e simplified forms of C M O S l o g i c that a t t e m p t to r e d u c e this complexity,
02
Qp
a l t h o u g h at the e x p e n s e of forgoing s o m e of the a d v a n t a g e s of b a s i c C M O S .
-O
Vn
O
V
0
1
fl/O For a process technology with L = 0.5 lira, n = 1.5. /; = 6, give the sizes of all transistors in (a) a fourinput NOR and (b) a four-input NAND. Also, give the relative areas of the two gates.
+
+
Vi
Vi
Ans..ni \ . \ I O S . d o k v - . : U /L^n.~5 n.5. P M O S d ^ k v - : 12 " . - : ihi W I O S d e » u v - : U L--
n.5. PMOS device-:
!
(c)
(b)
(a)
o.v
F I G U R E 1 0 . 1 9 (a) The pseudo-NMOS logic inverter, (b) The enhancement-load NMOS inverter, (c) The depletion-load NMOS inverter.
N( >K a r c a / N A N D area = 2.125 For the scaled N A N D gate in Exercise 10.4. find the ratio of the maximum to minimum current avail able to (a) charge a load capacitance and (b) discharge a load capacitance.
It w a s initially expected that the depletion N M O S with V
Ans. (a) 4: ib) I
GS
= 0 w o u l d operate as a constant2
current source and would thus provide an excellent load e l e m e n t . However, it w a s quickly real ized that the b o d y effect in the depletion transistor causes its i-v characteristic to deviate con siderably from that of a constant-current source. Nevertheless, depletion-load N M O S circuits
10.4
P S E U D O - N M O S LOGIC CIRCUITS
feature significant i m p r o v e m e n t s over their enhancement-load counterparts, e n o u g h to justify the extra processing step required to fabricate the depletion devices (namely, ion-implanting the
A s explained in Section 10.3, despite its m a n y great a d v a n t a g e s , C M O S suffers
from
channel). A l t h o u g h depletion-load N M O S has b e e n virtually replaced b y C M O S , one can still
i n c r e a s e d area, and c o r r e s p o n d i n g l y i n c r e a s e d c a p a c i t a n c e and delay, as t h e l o g i c gates
see s o m e depletion-load circuits in specialized applications. W e will not study depletion-load
b e c o m e m o r e c o m p l e x . F o r this r e a s o n , designers of digital integrated circuits h a v e b e e n
N M O S logic here (the interested reader can refer to the third edition of this b o o k ) .
searching for forms of C M O S logic circuits that can b e used to supplement the complementary-
T h e p s e u d o - N M O S inverter that w e are a b o u t to study is similar to depletion-load
t y p e circuits studied in Sections 10.2 and 1 0 . 3 . T h e s e forms are not i n t e n d e d to r e p l a c e c o m
N M O S but with rather i m p r o v e d characteristics. It also has the advantage of being directly
p l e m e n t a r y C M O S but rather to b e u s e d in special applications for special p u r p o s e s . W e
compatible with c o m p l e m e n t a r y C M O S circuits.
shall e x a m i n e t w o s u c h C M O S logic styles in this a n d t h e following section.
10.4.2 Static Characteristics 10.4.1 The Pseudo-NMOS Inverter
T h e static characteristics of the p s e u d o - N M O S inverter c a n b e derived in a m a n n e r similar
Figure 10.19(a) shows a modified form of the C M O S inverter. Here, only Q is driven by the
to that u s e d for c o m p l e m e n t a r y C M O S . T o w a r d that end, w e note that the drain currents of
input voltage while the gate of Q
Q
N
P
is grounded, and Q
P
acts as an active load for Q . Even N
N
and Q are g i v e n b y P
before w e e x a m i n e the operation of this circuit in detail, an advantage over complementary i
C M O S is obvious: E a c h input m u s t b e c o n n e c t e d to the gate of only o n e transistor or, alterna tively, only o n e additional transistor (an N M O S ) will b e n e e d e d for each additional gate input.
v
D N
gate will b e reduced. This is indeed the motivation for exploring this modified inverter circuit.
v >v,-
2
= * „ [ ( > / - V )v -\v ],
hp
= k (V -V,f,
ip
= k [(V -V,)(V -v )
t
2
p
V,
0
iM D
T h u s the area and delay penalties arising from increased fan-in in a c o m p l e m e n t a r y C M O S
for
= 5 * „ ( w / -
(saturation)
for v < v , - V,
0
(triode)
0
foxv
DD
0
(10.29) (10.30)
(saturation)
t
(10.31)
T h e inverter circuit of Fig. 10.19(a) r e s e m b l e s other forms of N M O S logic that consist of a driver transistor (Q ) N
and a l o a d transistor (in this case, Q ); h e n c e t h e n a m e p s e u d o P
D
p
DD
DD
- \{V -
0
DD
v
0
) \
for v >V, 0
(triode)
(10.32)
N M O S . F o r c o m p a r i s o n p u r p o s e s , w e shall briefly m e n t i o n t w o older forms of N M O S logic. T h e earliest form, p o p u l a r in the m i d - 1 9 7 0 s , utilized an e n h a n c e m e n t M O S F E T for the load element, in a topology w h o s e basic inverter is s h o w n in Fig. 10.19(b). E n h a n c e m e n t - l o a d
where w e have a s s u m e d that V = -V te
tp
= V , and h a v e used k = k'„(W/L)„ and k t
n
= k'
p
p
(W/L)
p
to simplify m a t t e r s .
N M O S logic circuits suffer from a relatively s m a l l logic s w i n g , small n o i s e m a r g i n s , and 2
h i g h static p o w e r dissipation. F o r t h e s e r e a s o n s , this logic-circuit t e c h n o l o g y is n o w virtu ally obsolete. It w a s r e p l a c e d in the late 1970s a n d early 1980s with d e p l e t i o n - l o a d N M O S circuits, in w h i c h a depletion N M O S transistor with its gate c o n n e c t e d to its source is used as the load element. T h e topology of the basic depletion-load inverter is shown in Fig. 10.19(c).
A constant-current load provides a capacitor-charging current that does not diminish as v rises toward V , as is the case with a resistive load. Thus the value of t obtained with a current-source load is significantly lower than that obtained with a resistive load (see Problem 10.38). Of course, a resistive load is simply out of the question because of the very large silicon area it would occupy (equivalent to that of thousands of transistors!). 0
DD
PLH
10.4 9 7 6
:
CHAPTER 10
P S E U D O - N M O S LOGIC CIRCUITS
DIGITAL C M O S LOGIC CIRCUITS
Region I — > A >~ 5»
VQH
o v
V
0L
V -V
t
DD
V
t
B
• Region II
>
-Slope = - 1
v
DD
0
-Slope = + 1 FIGURE 1 0 . 2 0
(v = Vj) 0
Graphical construction to determine the VTC of the inverter in Fig. 10.19.
T o obtain t h e V T C of t h e inverter, w e s u p e r i m p o s e t h e load c u r v e r e p r e s e n t e d b y Eqs. (10.31) a n d (10.32) o n the i -v characteristics of Q , w h i c h can b e relabeled as imr-^o and d r a w n for various values of v = v S u c h a graphical construction is s h o w n in Fig. 10.20 w h e r e , t o k e e p t h e d i a g r a m simple, w e s h o w t h e Q curves for only t h e t w o e x t r e m e values of vj, n a m e l y , 0 a n d V . T w o observations follow: D
DS
GS
N
P
N
DD
1. T h e l o a d c u r v e represents a m u c h l o w e r saturation current (Eq. 10.31) t h a n is repre sented b y the c o r r e s p o n d i n g c u r v e for Q , n a m e l y , that for v = V . T h i s is a result of the fact that the p s e u d o - N M O S inverter is usually d e s i g n e d so that k is greater than k b y a factor of 4 to 10. A s w e will s h o w shortly, this inverter is of t h e so-called ratioed t y p e , a n d t h e ratio r = k /k d e t e r m i n e s all the breakpoints of the V T C , that is, V , V , V , a n d so on, a n d t h u s d e t e r m i n e s the noise m a r g i n s . Selection of a rel atively h i g h value for r r e d u c e s V a n d w i d e n s the noise m a r g i n s . N
I
DD
n
p
3
n
0L
IL
p
IH
0L
2. A l t h o u g h o n e tends t o think of Q as acting as a constant-current s o u r c e , it actually operates in saturation for only a small r a n g e of v , n a m e l y , v < V . F o r t h e r e m a i n der of t h e v r a n g e , Q operates in the triode region. P
0
0
0
t
P
C o n s i d e r first t h e t w o e x t r e m e cases of v W h e n v = 0, Q ^ i s c u t off a n d Q is operating in the triode region, t h o u g h with zero current a n d zero d r a i n - s o u r c e voltage. T h u s t h e operating point is that labeled A in F i g . 10.20, w h e r e v = V - V , t h e static current is zero, a n d the static p o w e r dissipation is zero. W h e n v = V , the inverter will operate at the point labeled E in F i g . 10.20. O b s e r v e that unlike c o m p l e m e n t a r y C M O S , h e r e V i s n o t zero, a n obvious d i s a d v a n t a g e . A n o t h e r d i s a d v a n t a g e is that t h e gate c o n d u c t s current ( / ) in t h e low-output state, a n d thus there will b e static p o w e r dissipation (P = 7 x V ). P
t
0
I
P
0H
DD
DD
0L
FIGURE 1 0 . 2 1 and r = 9.
VTC for the pseudo-NMOS inverter. This curve is plotted for V
DD
= 5 V, V = -V - 1 V, m
tp
stat
D
s t a t
DD
of operation of g a n d Q . T h e four r e g i o n s , t h e c o r r e s p o n d i n g transistor m o d e s of opera tion, a n d t h e conditions that define t h e r e g i o n s are listed in T a b l e 1 0 . 1 . W e shall utilize t h e information i n this table together w i t h t h e d e v i c e e q u a t i o n s g i v e n in E q s . (10.29) t h r o u g h (10.32) t o derive expressions for the various s e g m e n t s of t h e V T C a n d in particular for t h e i m p o r t a n t p a r a m e t e r s that characterize t h e static operation of t h e inverter. w
10.4.3 Derivation of the VTC F i g u r e 10.21 s h o w s t h e V T C of the p s e u d o - N M O S inverter. A s indicated, it h a s four distinct regions, labeled I through I V , corresponding t o the different combinations of possible m o d e s 3
For the NMOS inverters, V depends on the ratio of the transconductance parameters of the devices, that is, on the ratio ( £ ' ( W / L ) ) / ( f c ' ( W / L ) ) . Such circuits are therefore known as ratioed logic circuits. Complementary CMOS logic circuits do not have such a dependency and can therefore be called ratioless. 0L
driver
•
P
Region I (segment AB):
load
V,OH
V DD
(10.33)
.
977
978
CHAPTER 10
10.4
DIGITAL C M O S LOGIC CIRCUITS
P S E U D O - N M O S LOGIC CIRCUITS
Finally, w e c a n u s e E q s . (10.35) a n d (10.39) t o d e t e r m i n e NM a n d E q s . (10.33) a n d (10.38) to d e t e r m i n e NM , L
1CI
Ti5i
Regions of Operation of the Pseudo-NMOS Inverter
cy
Segment of VTC
Region
H
Condition
QP
NM
=
L
v,
Triode Triode Triode Saturation
Cutoff Saturation Triode Triode
AB BC CD DE
I II HI IV
t
DD
DN
k
0
0
NM
=
H
t
(V -V,)[1
J3r<
from E q . (10.32) together w i t h substituting
10.4.4 Dynamic Operation
p
T h e v a l u e of V
2
dv /dv 0
l
= V + J(V -V ) -r(v -V f 1
DD
t
I
(10.34)
t
c a n b e obtained b y differentiating this equation a n d substituting
IL
t
0L
DP
0
(10.42)
DD
A s a final observation, w e note that since V and V are determined b y the process technology, the only design parameter for controlling the values of V and the noise margins is the ratio r.
from E q . (10.29) a n d i
v
_2_
t
t
= rk , and w i t h s o m e m a n i p u l a t i o n s , w e obtain
n
(10.41)
t
Region II (segment BC): Equating i
1
t
DD
•
1 _
V -(V -V ) 1 - 1 -
Analysis of t h e inverter transient r e s p o n s e to d e t e r m i n e t with t h e inverter l o a d e d b y a capacitance C is identical to that of t h e c o m p l e m e n t a r y C M O S inverter. T h e c a p a c i t a n c e will b e c h a r g e d b y t h e current i ; w e c a n d e t e r m i n e a n estimate for t b y using t h e aver age value of i over t h e r a n g e v - 0 t o v = V /2. T h e result is the following a p p r o x i m a t e expression ( w h e r e w e h a v e a s s u m e d V, = 0.2V ): PLH
DP
DP
- -I a n d Vj= V , IL
PLH
0
0
DD
DD
V
=V
IL
t
^ ^
+
(10.35) (
tPLH = K
1
0
-
4
3
)
p DD V
T h e threshold v o l t a g e V (or V ) is b y definition the value of v for w h i c h v = v„ M
th
I
0
T h e case for t h e capacitor discharge is s o m e w h a t different b e c a u s e t h e current IQ has t o b e subtracted from i t o d e t e r m i n e t h e d i s c h a r g e current. T h e r e s u l t is t h e a p p r o x i m a t e expression, P
V
=V
M
^
1 +
^
(10.36)
DN
JT+l Finally, t h e e n d of the r e g i o n I I s e g m e n t (point C ) c a n b e found b y substituting v
0
-
t
PHL
=
;
7
C
(10.44)
n
OF Y
v - V, in E q . (10.34), t h e condition for Q leaving saturation a n d entering t h e triode l
1
,
k J l - ^ \ V
N
D
D
region. •
Region III (segment CD) T h i s is a short s e g m e n t that is n o t of great interest. Point D i s characterized b y v = V . 0
tpHL=~^-
m Region I V (segment DE) E q u a t i n g z' from Eq. (10.30) t o i DAf
which, for a large v a l u e of r, r e d u c e s t o
t
(10.45) K
V
n DD
from Eq. (10.31) and substituting k = rk results in
DP
n
% = (»/- V )- ^Vj-V f-HV -V f t
t
DD
p
(10.37)
t
A l t h o u g h t h e s e a r e identical formulas t o those for t h e c o m p l e m e n t a r y C M O S inverter, t h e p s e u d o - N M O S inverter has a special p r o b l e m : Since k is r times smaller than k , t will b e r times larger t h a n t . T h u s t h e circuit exhibits a n a s y m m e t r i c a l delay p e r f o r m a n c e . Recall, h o w e v e r , that for gates with large fan-in, p s e u d o - N M O S requires fewer transistors and thus C c a n b e smaller t h a n in t h e c o r r e s p o n d i n g c o m p l e m e n t a r y C M O S gate. p
n
PLH
PHL
T h e value of V
m
dv /dvj 0
can b e determined b y differentiating this equation a n d setting
= -land v =
V ,
7
IH
V
= V + ^=(V -V )
IH
T h e v a l u e of V
0L
t
DD
t
can b e found b y substituting Vj = V
DD
(10.38)
10.4.5 Design
(10.39)
T h e d e s i g n i n v o l v e s selecting t h e ratio r a n d t h e (W/L) for o n e o f t h e transistors. T h e value of (W/L) for t h e o t h e r d e v i c e c a n t h e n b e o b t a i n e d u s i n g r. T h e d e s i g n p a r a m e t e r s of interest a r e V , NM , NM , 7 , P , t , a n d t . I m p o r t a n t d e s i g n c o n s i d e r a t i o n s a r e as follows:
into Eq. (10.37),
0L
VOL
~ V,) 1 -
= (V
DD
1
T h e static current conducted b y the inverter in the low-output state is found from Eq. (10.31) as
L
= \k {V -V f p
DD
t
(10.40)
stat
D
PLH
PHL
1. T h e ratio r d e t e r m i n e s all t h e breakpoints of t h e V T C ; t h e larger t h e value of r, t h e l o w e r V is (Eq. 10.39) and the w i d e r t h e n o i s e m a r g i n s a r e (Eqs. 10.41 a n d 10.42). H o w e v e r , a larger r increases t h e a s y m m e t r y in the d y n a m i c response and, for a given (W/L) , m a k e s t h e gate larger. T h u s selecting a value for r represents a c o m p r o m i s e OL
I^
H
p
CHAPTER 1 0
DIGITAL C M O S LOGIC CIRCUITS
10.4
P S E U D O - N M O S LOGIC CIRCUITS
b e t w e e n n o i s e m a r g i n s o n the o n e h a n d a n d silicon area a n d t o n t h e other. Usually, P
r is selected i n the r a n g e 4 t o 10. 2. O n c e r h a s b e e n d e t e r m i n e d , a v a l u e for (W/L)
p
or (W/L)„ c a n b e selected a n d t h e
o t h e r d e t e r m i n e d . H e r e , o n e w o u l d select a s m a l l (W/L)
n
t o k e e p t h e g a t e area small
Consider a pseudo-NMOS inverter fabricated in the C M O S technology specified in Example 10.1 for which p C = 115 pAIN , pC = 30 pA/V , V = - V„ = 0.4 V, and V = 2.5 V. Let the W/L ratio of Q be (0.375 / t m / 0 . 2 5 /mi) and r = 9. Find: 2
a n d thus obtain a s m a l l v a l u e for C. Similarly, a small (W/L)
keeps 7
p
stat
and P
low.
D
O n the other h a n d , o n e w o u l d w a n t t o select larger (W/L) ratios t o o b t a i n l o w t and
n
2
ox
p
ox
m
DD
N
P
thus fast r e s p o n s e . F o r u s u a l ( h i g h - s p e e d ) applications, (W/L)
p
is i n t h e r a n g e of 5 0 t o 100 pA, w h i c h for V
DD
is selected s o that Z
= 5 V results i n P
stat
i n t h e r a n g e of
D
(a) V , V , V , V , V , NM , and NM 0H
(b)
0L
[L
m
u
H
L
(W/L)
p
0.25 m W to 0.5 m W . (c) 7
s t a t
andP
D
(d) t , t , and t , assuming a total capacitance at the inverter output of 7 fF
10.4.6 Gate Circuits
PLH
E x c e p t for the load device, t h e p s e u d o - N M O S gate circuit is identical to the P D N of the com p l e m e n t a r y C M O S gate. F o u r - i n p u t p s e u d o - N M O S N O R a n d N A N D gates a r e s h o w n in Fig. 10.22. N o t e that e a c h requires five transistors c o m p a r e d t o t h e eight used i n comple m e n t a r y C M O S . I n p s e u d o - N M O S , N O R gates a r e preferred over N A N D gates since the
PHL
P
Solution
(a) V =V OH
V
DD
= 2.5V
is determined from Eq. (10.39) as
0L
former d o n o t utilize transistors in series, a n d thus c a n b e d e s i g n e d with m i n i m u m - s i z e V
N M O S devices.
0L
= (2.5 - 0 . 4 ) [ l - y r n ] = 0.12 V /
V is determined from Eq. (10.35) as lL
10.4.7 Concluding Remarks
V
7i
= 0.4 +
P s e u d o - N M O S is particularly suited for applications i n w h i c h the o u t p u t r e m a i n s h i g h most of t h e t i m e . I n such applications, t h e static p o w e r dissipation can b e r e a s o n a b l y l o w (since
V
m
2
5
4
' ~°= 0.62 V 7 9 ( 9 + 1)
is determined from Eq. (10.38) as
the g a t e dissipates static p o w e r only i n the l o w - o u t p u t state). Further, t h e o u t p u t transitions that m a t t e r w o u l d p r e s u m a b l y b e h i g h - t o - l o w o n e s w h e r e the p r o p a g a t i o n delay c a n b e m a d e
V
LH
= 0-4 +
d e c o d e r s for m e m o r y chips (Section 11.5) and i n r e a d - o n l y m e m o r i e s (Section 11.6).
x (2.5 - 0.4) = 1.21 V
73l<9
as short as necessary. A particular application of this t y p e can b e found in the design of address V is determined from Eq. (10.36) as M
VDD
y
= 0.4 + ^
M
^
= 1-06 V
79TT
A The noise margins can n o w b e determined as NM
-OY
A QNA
_w
= V
NM
= V
L
- V
0H
1L
= 2.5 - 1.21 = 1.29 V
[H
- V
0L
= 0 . 6 2 - 0 . 1 2 = 0.50 V
Observe that the noise margins are not equal and that 7VM is rather low. L
(b) The (W/L) ratio of Q can be found from
Qp
J7
H
P
'o—l -oY
_w
Q.NB
fi C (W/L) n
ox
n
= 9
ß C (W/L) p
Co Do QNA
QNC
QNB
1
—•
Do
1 1
— • QNC
—>
0X
p
. 0.375 115x: 0.25 30(W/L)
QND
=
9
p
QND
Thus Y=A+B+C+D (a) FIGURE 1 0 . 2 2
NOR and NAND gates of the pseudo-NMOS type.
(W/L\
Y = ABCD (b)
= 0.64
(c) The dc current in the low-output state can b e determined from Eq. (10.40), as 7
stat = \
x
30 x 0 . 6 4 ( 2 . 5 - 0 . 4 )
2
= 42.3
pA
982
!
CHAPTER 10
10.5
DIGITAL C M O S LOGIC CIRCUITS
B
The static power dissipation can n o w be found from PD
=
PASS-TRANSISTOR LOGIC CIRCUITS
ISVSSYDD
= 42.3 x 2.5 = 106 pW (d) The low-to-high propagation delay can b e found from Eq. (10.43), as tpjjj =
1 5
1.7x7xl0~ 30 x 10
, = 0.25 ns n
o
x 0.64x2.5
The high-to-low propagation delay can b e found from Eq. (10.45), as
hHL
1.7x7xl0"
=
FIGURE 1 0 . 2 3 Conceptual pass-transistor logic gates, (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A{B + C).
1 5 n
n
a
= 0.03 ns
115 x 1 0 " x 9^22 2.5 6
0.25
X
Now, the propagation delay can be determined, as t
P
= | ( 0 . 2 5 + 0.03) = 0.14 ns
Although the propagation delay is considerably greater than that of the complementary CMOS inverter of Example 10.1, this is not an entirely fair comparison: Recall that the advantage of p s e u d o - N M O S occurs in gates with large fan-in, not in a single inverter. C o
y
-o D1Ö.6 While keeping r unchanged, redesign the inverter circuit of Example 10.3 to lower its static power dis sipation to half the value found. Find the W/L ratios for the new design. Also find t , t , and t , assuming that C remains unchanged. Would the noise margins change? PLH
Ans. (W/L)
= 1.5: (W/L)
n
PHL
T h o u g h c o n c e p t u a l l y s i m p l e , pass-transistor logic circuits h a v e t o b e d e s i g n e d with care.
D10.7 Redesign the inverter of Example 10.3 using r = 4. Find V and the noise margins. If (W/L) 0.375 jUm/0.25 pm, find (W/L) , 7 , P , t , t , and t . Assume C = 7 fF. 0L
p
slat
D
P U 1
P H L
L
w / i
H
n
=
In the following, w e shall study the basic principles of P T L circuit d e s i g n a n d p r e s e n t e x a m ples of its application.
P
Ans. V = 0-28 V; NM = 0.59 V; NM = 0.89 V; (W/L) 0.11 n s ; i = 0.03 ns; t = 0.07 ns 0L
(a)
P
= 0.32; 0.5 ns; 0.03 ns; 0.27 ns; no
p
FIGURE 1 0 . 2 4 Two possible implemen tations of a voltage-controlled switch con necting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.
p
= 1.44; 7
stat
= 95.3 pA: P = 0.24 m W ; t D
P U i
=
10.5.1 An Essential Design Requirement
P
A n e s s e n t i a l r e q u i r e m e n t i n t h e d e s i g n of P T L circuits is e n s u r i n g that every has at all times a low-resistance
10.5
PASS-TRANSISTOR LOGIC CIRCUITS
path to V
DD
or ground.
circuit
node
T o a p p r e c i a t e this p o i n t , c o n s i d e r
the s i t u a t i o n d e p i c t e d i n F i g . 10.25(a): A s w i t c h S ( u s u a l l y p a r t of a l a r g e r P T L n e t w o r k , x
not s h o w n ) is u s e d t o f o r m t h e A N D function o f its c o n t r o l l i n g v a r i a b l e B a n d t h e v a r i a b l e A c o n c e p t u a l l y s i m p l e a p p r o a c h for i m p l e m e n t i n g logic functions utilizes series a n d parallel
A a v a i l a b l e at t h e o u t p u t of a C M O S inverter. T h e o u t p u t Y of t h e P T L circuit is s h o w n
c o m b i n a t i o n s of switches that a r e controlled b y i n p u t l o g i c variables t o c o n n e c t t h e input
c o n n e c t e d t o t h e i n p u t of a n o t h e r inverter. O b v i o u s l y , if B is h i g h , S c l o s e s a n d Y = A.
a n d o u t p u t n o d e s (see F i g . 10.23). E a c h of t h e s w i t c h e s c a n b e i m p l e m e n t e d either b y a
N o d e Y will t h e n b e c o n n e c t e d e i t h e r t o V
t
DD
(if A is h i g h ) t h r o u g h Q o r t o g r o u n d (if A is 2
single N M O S transistor (Fig. 10.24a) o r b y a p a i r of c o m p l e m e n t a r y M O S transistors con
low) through Q
n e c t e d i n w h a t is k n o w n as the C M O S t r a n s m i s s i o n - g a t e configuration (Fig. 10.24b). T h e
b e c o m e a h i g h - i m p e d a n c e n o d e . If initially, v w a s z e r o , it will r e m a i n s o . H o w e v e r , if
result is a s i m p l e f o r m of logic circuit that is particularly suited for s o m e special logic func
initially, v w a s h i g h at V , this v o l t a g e w i l l b e m a i n t a i n e d b y t h e c h a r g e o n t h e p a r a s i t i c
tions a n d is frequently used i n conjunction w i t h c o m p l e m e n t a r y C M O S logic t o i m p l e m e n t
c a p a c i t a n c e C, b u t for o n l y a t i m e : T h e i n e v i t a b l e l e a k a g e c u r r e n t s w i l l s l o w l y d i s c h a r g e
v
But, what happens w h e n B goes l o w a n d S opens? N o d e Y will n o w x
Y
Y
DD
C, and v will d i m i n i s h c o r r e s p o n d i n g l y . I n any c a s e , t h e circuit c a n n o l o n g e r b e c o n s i d e r e d
s u c h functions efficiently.
Y
B e c a u s e this form of logic utilizes M O S transistors i n the series p a t h f r o m i n p u t t o out
a static c o m b i n a t i o n a l l o g i c circuit.
(PTL). As
T h e p r o b l e m c a n b e easily solved b y establishing for n o d e Y a l o w - r e s i s t a n c e p a t h that is
m e n t i o n e d earlier, C M O S t r a n s m i s s i o n gates a r e frequently e m p l o y e d t o i m p l e m e n t t h e
activated w h e n B g o e s l o w , a s s h o w n i n F i g . 10.25(b). H e r e , a n o t h e r switch, S , controlled
switches, g i v i n g this logic-circuit f o r m t h e alternative n a m e , transmission-gate
b y B is c o n n e c t e d b e t w e e n Y a n d ground. W h e n B g o e s l o w , S closes a n d establishes a l o w -
put, t o pass
or b l o c k signal transmission, it is k n o w n as pass-transistor
logic
logic. T h e
t e r m s are u s e d i n t e r c h a n g e a b l y i n d e p e n d e n t of t h e actual i m p l e m e n t a t i o n of the switches.
2
2
resistance p a t h b e t w e e n Y a n d g r o u n d .
9 8 4
' _ !
:
CHAPTER 10
10.5
DIGITAL C M O S LOGIC CIRCUITS
PASS-TRANSISTOR LOGIC CIRCUITS
v = VDD c
V
DD
iL B r—ol
'
02 A
1
Y
/ Si B
Qi
FIGURE 1 0 . 2 7 Operation of the NMOS switch as the input goes low (v, = 0 V). Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source termi nals interchange roles in comparison to the circuit in Fig. 10.26.
S~ 2
(a)
(b) T h u s , initially (at t = 0 ) , V, = V a n d t h e c u r r e n t i is r e l a t i v e l y l a r g e . H o w e v e r , a s C charges u p a n d v r i s e s , V, i n c r e a s e s (Eq. 10.47) a n d i d e c r e a s e s . T h e latter effect is d u e to b o t h t h e i n c r e a s e i n v and in V . I t f o l l o w s t h a t t h e p r o c e s s of c h a r g i n g t h e c a p a c i t o r will b e r e l a t i v e l y s l o w . M o r e seriously, o b s e r v e from E q . ( 1 0 . 4 6 ) t h a t i r e d u c e s t o z e r o w h e n v r e a c h e s (V - V,). T h u s the h i g h o u t p u t v o l t a g e (V ) w i l l n o t b e e q u a l t o V ; rather, it will b e l o w e r b y V„ and t o m a k e m a t t e r s w o r s e , t h e v a l u e of V, can b e a s h i g h a s 1.5 to 2 t i m e s V l t0
FIGURE 1 0 . 2 5 A basic design requirement of PTL circuits is that every node have, at all times, a lowresistance path to either ground or V . Such a path does not exist in (a) when B is low and 5! is open. It is provided in (b) through switch S .
D
0
DD
D
0
2
t
D
0
10.5.2 Operation with NMOS Transistors as Switches I m p l e m e n t i n g the switches in a P T L circuit w i t h single N M O S transistors results in a simple circuit w i t h small area a n d small n o d e c a p a c i t a n c e s . T h e s e a d v a n t a g e s , h o w e v e r , are obtained at t h e e x p e n s e of serious s h o r t c o m i n g s in b o t h t h e static characteristics a n d the d y n a m i c p e r f o r m a n c e of the resulting circuits. T o illustrate, consider the circuit s h o w n in F i g . 10.26, w h e r e a n N M O S transistor Q is u s e d t o i m p l e m e n t a switch c o n n e c t i n g a n input n o d e with v o l t a g e v; and a n output n o d e . T h e total capacitance b e t w e e n t h e output n o d e and g r o u n d is r e p r e s e n t e d b y capacitor C. T h e switch is s h o w n in the closed state w i t h the con trol signal applied t o its gate b e i n g h i g h at V . W e w i s h t o analyze the operation of the cir cuit as t h e input voltage v, goes h i g h (to V ) at t i m e t = 0. W e a s s u m e that initially t h e output voltage v is zero and capacitor C is fully discharged.
0H
0H
W h e n v, goes high, the transistor operates in the saturation m o d e and delivers a current i to c h a r g e the capacitor, 2
0
- V)
n
DD
i
(10.46)
t
D
= \k (V -Vf n
(10.48)
DD
w h e r e w e n o t e that since the source is n o w at 0 V (note that the drain and source h a v e inter c h a n g e d roles), t h e r e will b e n o b o d y effect, and V, r e m a i n s constant at V . A s C discharges, v decreases and the transistor enters t h e triode region at v = V - V . Nevertheless, t h e capacitor d i s c h a r g e continues until C is fully discharged and v = 0. T h u s , the N M O S tran sistor p r o v i d e s V = 0, o r a " g o o d 0." A g a i n , t h e p r o p a g a t i o n delay t can b e d e t e r m i n e d using u s u a l t e c h n i q u e s , as illustrated b y the following e x a m p l e .
w h e r e k = k' (W/L), and V is determined b y the b o d y effect since the source is at a voltage v relative t o the b o d y , thus (see Eq. 4.33), n
DD
0
D
- V
P
PLH
0
DD
= \K(VDD
T
t0
0
0
v
, = V , + y O o + 20/ - J74 ) 0
(10.47)
f
DD
t0
0
D
0H
In addition t o r e d u c i n g t h e gate noise i m m u n i t y , t h e l o w value of V (commonly referred t o a s a " p o o r 1") h a s another detrimental effect: C o n s i d e r w h a t h a p p e n s w h e n t h e output n o d e is c o n n e c t e d to the input of a c o m p l e m e n t a r y C M O S inverter (as w a s t h e c a s e in Fig. 10.25). T h e l o w v a l u e of V can c a u s e Q of t h e l o a d inverter t o conduct. T h u s t h e inverter will h a v e a finite static current and static p o w e r dissipation. T h e p r o p a g a t i o n delay t of t h e P T L gate of F i g . 10.26 can b e d e t e r m i n e d a s the t i m e for v to r e a c h V /2. T h i s can b e calculated u s i n g techniques similar to those e m p l o y e d in the p r e c e d i n g sections, as will b e illustrated shortly in an e x a m p l e . Figure 10.27 s h o w s t h e N M O S switch circuit w h e n v, is b r o u g h t d o w n to 0 V . W e a s s u m e that initially v = V . T h u s at t = 0+, t h e transistor conducts a n d operates in t h e saturation region,
DD
i
DD
0
DD
t
0
0L
PHL
Consider the N M O S transistor switch in the circuits of Figs. 10.26 and 10.27 to be fabricated in a technology for which Li C = 50 i z A / V , pi C = 20 LiA/V , \ V, \ = 1 V , y = 0.5 V , 2
n
ox
2
p
0X
DD
FIGURE 1 0 . 2 6 Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for the case with the switch closed (v is high) and the input going high (v, = V ). c
DD
*M
(a) For the case with v, high (Fig. 10.26), find
1 / 2
0
V . 0H
f
? _ .! 9 8 5
HAPTER 10
DIGITAL C M O S LOGIC CIRCUITS
10.5
(b) If the output feeds a C M O S inverter whose (W/L)
= 2.5 (W/L)
p
= 10 /j.va/2 pm, find the
n
static current of the inverter and its power dissipation when its input is at the value found in (a).
and t
can be found as
PLH
C{V /2)
Also find the inverter output voltage. (c)
PASS-TRANSISTOR LOGIC CIRCUITS
DD
Fmdt . PLH
(d) For the case with v, going low (Fig. 10.27), find
50 x 10"
t . PHL
x 2.5
425 x 1 0 "
(e) Find t . P
= 0.29 ns
6
(d) Refer to the circuit in Fig. 10.27. Observe that, here, V remains constant at V = 1 V. T h e drain current at t = 0 is t
Solution (a) Refer to Fig. 10.26. V
is the value of v at which Q stops conducting,
0H
i (0)
0
v -v -v DD
0H
= 0
t
= \ x 50 x | ( 5 - l )
D
PHL
i (t HL) D
=
V
D
D
- V
Thus, the average discharge current is given by
Eq. (10.47), 7
OH
i \ = 1(800 + 690) = 7 4 0 pA lav 2
+ 2$ - J24 ) f
and t
f
can b e determined as
PHL
= v + rUv t0
Substituting V = l , y = 0.5, V tQ
DD
-v, + 2 -
DD
2
50x^[(5-l)x2.5-ix2.5 ]
= 690 pA 0H
t0
=
P
T
where V, is the value of the threshold voltage at a source-body reversed bias equal to V . Using
v, = v + Uv
= 800 pA
At t = t , Q will b e operating in the triode region, and thus
thus, VOH
2
t0
f
Ji4 )
50xl0"
f
hm.
= 5, and 2
1 5
x2.5 T~ 740 x 10
=
f
=
17
°-
n
s
solution yields (e) t
V, = 1.6 V
P
= \{t
+t )
PLH
PHL
= | ( 0 . 2 9 + 0.17) = 0.23 ns
Thus, V
0H
= 3.4 V
Note that this represents a significant loss in signal amplitude.
E x a m p l e 10.4 illustrates clearly t h e p r o b l e m of signal-level loss a n d its deleterious effect on t h e operation of t h e succeeding C M O S inverter. S o m e rather ingenious techniques h a v e been d e v e l o p e d t o restore t h e output level to V . W e shall briefly discuss t w o such tech niques. O n e is circuit-based a n d t h e other is b a s e d o n p r o c e s s technology. DD
(b) The load inverter will have an input signal of 3.4 V. Thus, its Q will conduct a current of P
T h e circuit-based a p p r o a c h is illustrated in Fig. 10.28. H e r e , Q is a pass-transistor con trolled b y input B. T h e output n o d e of the P T L n e t w o r k is c o n n e c t e d t o t h e input of a c o m p l e m e n t a r y inverter formed b y Q a n d Q . A P M O S transistor Q , w h o s e gate is controlled b y t h e o u t p u t v o l t a g e of t h e inverter, v , h a s b e e n a d d e d t o t h e circuit. O b s e r v e that in t h e event that t h e output of t h e P T L gate, v is l o w (at g r o u n d ) , v will b e high (at V ), a n d Q will b e off. O n t h e other h a n d , if v is h i g h b u t n o t quite equal to V , t h e output of t h e l
i
= | x 20 x ^ ( 5 - 3.4 - l )
DP
2
= 18
LIA
Thus, the static power dissipation of the inverter will be
N
P
R
02
P
D
= V i
DD DP
= 5 x 18 = 90 pW
o
The output voltage of the inverter can be found by noting that Q will be operating in the triode
R
u
02
DD
0l
DD
N
region. Equating its current to that of Q (i.e., 18 pA) enables us to determine the output voltage P
to be 0.08 V .
VDD
A
(c) T o determine t , w e need to find the current i at t = 0 (where v = 0, V = V = 1 V) and at PLH
t =t
PLH
D
0
t
l0
(where v = 2.5 V, V, to be determined), as follows: 0
(J, i (0) D
2
= I x 50 x \ x (5 - l ) = 800 pA
IA VDD
V,(at v = 2.5 V ) = 1+0.5(72.5 + 0.6-706) = 1 . 4 9 V 0
l\~Qp = \ x 5 0 x ^ ( 5 - 2.5 - 1 . 4 9 )
i (tpLH) D
2
= 50
pA
-0%2
Qi W e can now compute the average discharge current as . ,
800 + 50
= 425 pA
OA
FIGURE 1 0 . 2 8 The use of transistor Q , con nected in a feedback loop around the CMOS inverter, to restore the V level, produced by Q to V . R
OH
DD
u
10.5
CHAPTER 1 0 D I G I T A L C M O S L O G I C C I R C U I T S
m
V
C
R
m
lV
V = DD
inverter will b e l o w (as it should b e ) a n d Q will turn o n , supplying a current to charge C up to V . T h i s p r o c e s s will stop w h e n v = V , that is, w h e n t h e output voltage h a s been restored to its p r o p e r level. T h e "level-restoring" function performed b y Q is frequently e m p l o y e d in M O S digital-circuit design. It should b e noted that although t h e description of operation is relatively straightforward, t h e addition of Q closes a "positive-feedback" loop a r o u n d t h e C M O S inverter, a n d t h u s operation is m o r e i n v o l v e d than it appears, especially d u r i n g transients. Selection of a W/L ratio for Q is also a s o m e w h a t i n v o l v e d process, a l t h o u g h normally k is selected to b e m u c h l o w e r than k (say a third o r a fifth as large). Intuitively, this is appealing, for it implies that Q will not play a major role in circuit opera tion, apart from restoring the level of V to V , as explained [see R a b a e y (1996)]. Transistor Q is said t o b e a " w e a k P M O S transistor." T h e other t e c h n i q u e for correcting for t h e loss of the high-output signal level (V ) is a t e c h n o l o g y - b a s e d solution. Specifically, recall that t h e loss in t h e value of V is equal to V . It follows that w e c a n r e d u c e t h e loss b y u s i n g a l o w e r value of V for t h e N M O S switches, a n d w e c a n eliminate t h e loss altogether b y u s i n g devices for w h i c h V„, = 0. These zero-threshold devices c a n b e fabricated b y using i o n implantation to control t h e value of V and a r e k n o w n as n a t u r a l d e v i c e s . DD
PASS-TRANSISTOR LOGIC CIRCUITS
DD
R
R
R
r
n
R
0H
DD
R
0H
0H
m
tn
m
10.5.3 The Use of CMOS Transmission Gates as Switches G r e a t i m p r o v e m e n t s in static a n d d y n a m i c p e r f o r m a n c e are obtained w h e n t h e switches are i m p l e m e n t e d w i t h C M O S t r a n s m i s s i o n gates. T h e transmission gate utilizes a pair of com p l e m e n t a r y transistors connected i n parallel. It acts as a n excellent switch, providing bidi rectional current flow, a n d it exhibits a n on-resistance that r e m a i n s almost constant for wide r a n g e s of input voltage. T h e s e characteristics m a k e t h e transmission gate n o t only a n excel lent switch in digital applications b u t also a n excellent analog switch in such applications as data converters (Chapter 9) a n d switched-capacitor filters (Chapter 12). F i g u r e 10.29(a) s h o w s the transmission-gate switch in t h e " o n " position with the input, v rising to V at t = 0. A s s u m i n g , as before, that initially t h e output v o l t a g e is zero, w e see" that Q will b e operating in saturation a n d p r o v i d i n g a c h a r g i n g current of b
(b) FIGURE 1 0 . 2 9 Operation of the transmission gate as a switch in PTL circuits with (a) v high and (b) v, low. I
where \ V \ is g i v e n b y tp
= V +YlJV -v
K\
l0
DD
+ 2$ -j2j ]
o
f
(10.52)
f
DD
Transistor Q , h o w e v e r , continues t o c o n d u c t until C is fully discharged a n d v = V N
0
0L
= 0 V,
N
i
D N
=
a "good 0."
iK(V -v -V f DD
0
(10.49)
tn
W e c o n c l u d e that transmission gates p r o v i d e far superior performance, b o t h static a n d d y n a m i c , t h a n is p o s s i b l e with single N M O S switches. T h e price p a i d is increased circuit
w h e r e , as in t h e c a s e of the single N M O S switch, V is d e t e r m i n e d b y t h e b o d y effect, m
complexity, area, a n d capacitance.
v = v +/(V^W/ - M ) tn
t0
5
a°-°)
f
Transistor Q will conduct a d i m i n i s h i n g current that reduces to zero at v = V O b s e r v e , h o w e v e r , that Q operates w i t h V = V a n d is initially in saturation, N
0
P
SG
ip D
DD
V. m
DD
2
= {k (V -\V \) p
-
DD
(10.51)
lp
w h e r e , since t h e b o d y of Q is c o n n e c t e d to V , \ V, \ r e m a i n s constant at t h e value V , a s s u m e d t o b e t h e s a m e value as for t h e w-channel device. T h e total capacitor-charging cur rent is t h e s u m of i a n d i . N o w , Q will enter the triode region at v = | V, \, b u t will con tinue to c o n d u c t until C is fully c h a r g e d a n d v = V = V . T h u s , t h e ^ - c h a n n e l device will p r o v i d e t h e gate w i t h a " g o o d 1." T h e v a l u e of t can b e calculated using u s u a l techniques, w h e r e w e expect that a s a result of the additional current available from t h e P M O S device, for t h e s a m e value of C, t will b e l o w e r than in t h e case of the single N M O S switch. Note, h o w e v e r , that a d d i n g the P M O S transistor increases the value of C. W h e n v goes low, as s h o w n in F i g . 10.29(b), Q a n d Q i n t e r c h a n g e roles. A n a l y s i s of t h e circuit in F i g . 10.29(b) will indicate that Q will cease c o n d u c t i o n w h e n v falls t o \ V \, P
DN
DP
DD
p
m
P
0
0
0H
p
PLH
N
P
:
:
P
n
p
;
!iff!§ifi y|§|§^^ (a) F o r the situation in Fig. 10.29(a). find z' (0), i {0\ ttV
DP
i (t ), m
PLH
1
i ( rLn)DP
a
" d hi.n-
DD
PLH
s
10.8 T h e transmission gate of Fies. 10.29(a) and 10.29(b) is fabricated in a C M O S process technology for which A' - 5 0 / i \ - V . A,' - 2 0 ,
P
0
tp
(b) For ihe situation depicted in Fig. 10.29(b). find / ( 0 ) . i (0), value of v will Q turn off? (>v
0
nr
i {t ), m
Plll
i (t dDP
PH
and t , PW
At what
r
(c) F i n d / . P
Ans. (a) 800 /xA, 320 ,uA, 50 i(A, 275 fiA, 0.24 ns; (b) 800 fiA, 320 (c) 0.22 ns
yA, 688 u A , 20 u A , 0.19 ns, 1.6 V;
9 8 9
990
".. !
CHAPTER 10
10.6
DIGITAL C M O S LOGIC CIRCUITS
10.5.4 Pass-Transistor Logic Circuit Examples W e c o n c l u d e this section b y s h o w i n g e x a m p l e s of P T L logic circuits. Figure 10.30 shows a P T L realization of a t w o - t o - o n e multiplexer: D e p e n d i n g on t h e logic v a l u e of C, either A or B is c o n n e c t e d to the output Y. T h e circuit realizes the B o o l e a n function Y=CA
Our second example is an efficient reahzation of the exclusive-OR ( X O R ) function. T h e circuit s h o w n in Fig. 1 0 . 3 1 , utilizes four transistors in the transmission gates and another four for the t w o inverters n e e d e d to g e n e r a t e t h e c o m p l e m e n t s A and B, for a total of eight transis tors. N o t e that 12 transistors are n e e d e d in t h e realization with c o m p l e m e n t a r y C M O S . O u r final P T L e x a m p l e is the circuit s h o w n in F i g . 10.32. It uses N M O S switches with l o w o r z e r o threshold. O b s e r v e that b o t h the input variables and their c o m p l e m e n t s are
.
5o 1
™ -o Y = AB
2 B o-
+ CB
DYNAMIC LOGIC CIRCUITS
__4
Y = A + B = AB
B o~
FIGURE 1 0 . 3 2 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated.
e m p l o y e d and that the circuit generates b o t h the B o o l e a n function a n d its c o m p l e m e n t . T h u s this form of circuit is k n o w n as c o m p l e m e n t a r y p a s s - t r a n s i s t o r logic ( C P L ) . T h e circuit consists of t w o identical n e t w o r k s of pass transistors w i t h t h e c o r r e s p o n d i n g transistor gates controlled by t h e s a m e signal (B and By T h e inputs to the P T L , h o w e v e r , are c o m p l e mented: A and B for the first network, and À and B for the second. T h e circuit s h o w n realizes both the A N D a n d N A N D functions.
C Q
A o
- o Y = CA + CB
C<
J0;9 ^Consider the circuit in Fig. 10.32 with the input signals changed as follows. For each case, find F a n d Y: •*(a) T h e signals at,terminals.5 and 6 interchanged ( 5 applied to 5 and B applied to 6). All the rest are the same.
Bo-
(b) The signals at terminals 5 or 6 interchanged as in (a), and the signals at 2 and,4 changed to A and A, respectively. All the rest remain the same. FIGURE 1 0 . 3 0 Realization of a two-to-one mul tiplexer using pass-transistor logic.
B
Ans. (a) Y = A + B, F = AB = 1 + 7 ? (i.e., O R - N O R ) ; (b) Y = AB + AB, Y = AB + AB (i.e., XOR XN'OR)
10.5.5 A Final Remark
1
A l t h o u g h t h e u s e of zero-threshold devices solves t h e p r o b l e m of the loss of signal levels w h e n N M O S switches are used, the resulting circuits can b e m u c h m o r e sensitive to n o i s e and other effects, such as l e a k a g e currents resulting from subthreshold conduction.
TT_ Ao-
10.6
DYNAMIC LOGIC CIRCUITS
- 0 7 = AB + AB T h e logic circuits that w e h a v e studied t h u s far are of the static t y p e . In a static logic circuit, every n o d e h a s , at all t i m e s , a low-resistance p a t h to V or ground. B y the s a m e token, the voltage of e a c h n o d e is well defined at all times, a n d n o n o d e is left floating. Static circuits do not need clocks (i.e., periodic t i m i n g signals) for their operation, although.clocks m a y b e present for other p u r p o s e s . In contrast, the d y n a m i c logic circuits w e are about to discuss rely o n the storage of signal voltages o n parasitic capacitances at certain circuit n o d e s . S i n c e c h a r g e will leak a w a y w i t h t i m e , t h e circuits n e e d to b e periodically refreshed; thus the p r e s e n c e of a clock with a certain specified m i n i m u m frequency is essential. DD
FIGURE 1 0 . 3 1 Realization of the XOR function using pass-transistor logic.
991
CHAPTER 10 D I G I T A L C M O S L O G I C C I R C U I T S
992
10.6
T o place dynarnic-logic-circuit techniques into perspective, l e t ' s take stock of the various logic-circuit styles w e h a v e studied. C o m p l e m e n t a r y C M O S excels in nearly every perfor m a n c e category: I t is easy t o design, h a s t h e m a x i m u m possible logic s w i n g , is robust from a n o i s e - i m m u n i t y standpoint, dissipates n o static p o w e r , a n d c a n b e designed to p r o v i d e equal l o w - t o - h i g h and high-to-low p r o p a g a t i o n delays. Its m a i n d i s a d v a n t a g e is t h e requirement of t w o transistors for each additional gate input, w h i c h for h i g h fan-in gates c a n m a k e the chip area large a n d increase t h e total c a p a c i t a n c e a n d , c o r r e s p o n d i n g l y , t h e propagation delay and t h e d y n a m i c p o w e r dissipation. P s e u d o - N M O S r e d u c e s t h e n u m b e r of required transis tors at t h e e x p e n s e of static p o w e r dissipation. Pass-transistor logic c a n result in simple small-area circuits b u t is limited t o special applications a n d requires t h e u s e of c o m p l e m e n tary inverters t o restore signal levels, especially w h e n t h e switches a r e simple N M O S transistors. T h e d y n a m i c logic t e c h n i q u e s studied in this section m a i n t a i n t h e l o w device c o u n t of p s e u d o - N M O S w h i l e r e d u c i n g the static p o w e r dissipation t o zero. A s will b e seen, this is a c h i e v e d at t h e e x p e n s e of m o r e c o m p l e x , a n d less robust, design.
DYNAMIC LOGIC CIRCUITS
During t h e evaluation p h a s e , Q is off and Q is turned on. N o w , if the i n p u t c o m b i n a t i o n is o n e that c o r r e s p o n d s to a h i g h output, t h e P D N does not c o n d u c t (just as i n a c o m p l e m e n tary C M O S gate) a n d t h e o u t p u t r e m a i n s h i g h at V , t h u s V = V . O b s e r v e that n o low-to-high p r o p a g a t i o n delay is required, thus t = 0. O n the other h a n d , if the c o m b i n a tion of inputs is o n e that c o r r e s p o n d s to a l o w output, t h e appropriate N M O S transistors in the P D N will c o n d u c t a n d establish a path b e t w e e n t h e output n o d e a n d g r o u n d t h r o u g h t h e on-transistor Q . T h u s C will b e discharged through t h e P D N , a n d t h e v o l t a g e at t h e output node will r e d u c e t o V = 0 V . T h e h i g h - t o - l o w p r o p a g a t i o n delay t c a n b e calculated in exactly t h e s a m e w a y as for a c o m p l e m e n t a r y C M O S circuit except that h e r e w e h a v e a n additional transistor, Q , i n t h e series p a t h to ground. A l t h o u g h this will increase t h e delay slightly, t h e increase will b e m o r e t h a n offset b y t h e r e d u c e d capacitance at t h e output n o d e as a result of the a b s e n c e of t h e P U N . As an example, w e show in Fig. 10.33(c) the circuit that realizes the function Y = A + BC. Sizing of t h e P D N transistors often follows t h e s a m e p r o c e d u r e e m p l o y e d i n t h e design of static C M O S . F o r Q , w e select a W/L ratio large e n o u g h to ensure that C will b e fully charged d u r i n g t h e p r e c h a r g e interval. T h e size of Q , h o w e v e r , should b e small s o that t h e capacitance C will n o t b e increased significantly. T h i s is a ratioless f o r m of M O S logic, where t h e output levels d o n o t d e p e n d o n t h e transistors' W/L ratios. p
e
DD
0H
DD
PLH
e
L
0L
PHL
e
p
10.6.1 Basic Principle
I ^ T
L
p
F i g u r e 10.33(a) s h o w s t h e basic d y n a m i c - l o g i c gate. It consists of a p u l l - d o w n network ( P D N ) that realizes the logic function in exactly the s a m e w a y as the P D N of a complementary C M O S gate or a p s e u d o - N M O S gate. H e r e , h o w e v e r , w e h a v e t w o switches in series that are periodically operated b y the clock signal (j) w h o s e w a v e f o r m is s h o w n in Fig. 10.33(b). W h e n
L
p
p
e
L
p
L
DD
Consider a four-input N A N D grte realized in the dynamic logic form and fabricated in a C M O S process technology for which u , C „ , = 5 0 ,uA/v\ j.i C = 20 fiA/V , V,„ = jV ,! = I V, V = 5 V. T o keep C, small, minimum-size NMOS devices are used for which W/L = 4 / / m / 2 urn (this includes CJ,,).The P M O S precharge transistor Q„ has a W/L = 6 , u m / 2 ,um. The.total capacitance C. is found to be 30 IF. 2
;
p
ox
(/
0D
L
e
19.10 Consider the precharge operation with the gate of Q„ falling to 0 V, and assume that at / = 0, Q i s fully dis charged. W e wish to calculate the risesfime of the output voltage, defined as the time for v to rise fjom 10% to 9 0 % of the final value of 5 V?. Find the/current at v = 0.5 V and the current at v = 4.5 V, then compute an approximate value for t ,t f=:G (4.5 - 0 . 5 ) / 7 , where / is thesaverage yaluejof the two currents. v
Y
r
DD
A
r
L
a v
Y
a v
Ans. 4 8 0 / t A ; 112,t'A; 0.4 ns 10.11 Next, consider the computation of the high-to-low propagation delay t . Find the equivalent W/L ratio of the five N M O S transistors in series. Then, find the discharge current at v = 5 V and at v = 2.5 V . Finally, use the average of these two currents to compute:an approximate value f o r / . P m
'c—cj
Y
Q
P
Y:
/ w
Ans. (W/L ),,: - 0.4: 160 ,uA: 138 uA: 0.5 us L
A.
j
Ac—j
ßo—
PDN
10.6.2 Nonideal Effects
C L -
W e n o w briefly consider various sources of n o n i d e a l operation of d y n a m i c logic circuits. Noise M a r g i n s duct for V[= V ,
'C—\
Since, during t h e evaluation p h a s e , t h e N M O S transistors b e g i n t o con
tn
1.
V =V =V lL
(a)
(b)
(c)
FIGURE 1 0 . 3 3 (a) Basic structure of dynamic-MOS logic circuits, (b) Waveform of the clock needed to operate the dynamic logic circuit, (c) An example circuit.
!H
tn
and thus t h e n o i s e m a r g i n s will b e NM
L
NM
H
= V
= V
tn
DD
- V
m
»94
CHAPTER 10
DIGITAL C M O S LOGIC
10.6
CIRCUITS
T h u s t h e n o i s e m a r g i n s are far from equal, a n d NM
is rather l o w . A l t h o u g h NM
L
H
is high,
Thus i
will d i s c h a r g e C a n d c h a r g e Q . A l t h o u g h eventually i
m
L
DYNAMIC LOGIC CIRCUITS
will r e d u c e t o zero, C
m
L
other n o n i d e a l effects r e d u c e its v a l u e , as w e shall shortly s e e . A t this t i m e , h o w e v e r ,
will h a v e lost s o m e of its c h a r g e , w h i c h will h a v e b e e n transferred to C . T h i s p h e n o m e n o n
o b s e r v e that t h e o u t p u t n o d e is a h i g h - i m p e d a n c e n o d e a n d thus will b e susceptible t o noise
is k n o w n as c h a r g e sharing.
x
W e shall n o t p u r s u e t h e p r o b l e m of c h a r g e sharing a n y further here, e x c e p t to p o i n t o u t a
p i c k u p a n d o t h e r disturbances.
couple of t h e t e c h n i q u e s usually e m p l o y e d t o m i n i m i z e its effect. O n e a p p r o a c h i n v o l v e s O u t p u t V o l t a g e D e c a y D u e t o L e a k a g e Effects
I n t h e a b s e n c e of a p a t h t o g r o u n d
adding a ^ - c h a n n e l d e v i c e that c o n t i n u o u s l y c o n d u c t s a small current t o replenish t h e c h a r g e
T h i s , h o w e v e r , is
lost b y C , as s h o w n i n F i g . 10.34(b). This a r r a n g e m e n t should r e m i n d us of p s e u d o - N M O S .
b a s e d o n t h e a s s u m p t i o n that t h e c h a r g e o n C will r e m a i n intact. In p r a c t i c e , t h e r e will b e
Indeed, a d d i n g this transistor will cause t h e gate t o dissipate static p o w e r . O n t h e positive
t h r o u g h t h e P D N , t h e o u t p u t v o l t a g e will ideally r e m a i n h i g h at V . DD
L
L
to decay. T h e principal
side, h o w e v e r , t h e a d d e d transistor will l o w e r t h e i m p e d a n c e level of t h e output n o d e a n d
s o u r c e o f l e a k a g e is t h e r e v e r s e c u r r e n t of t h e r e v e r s e - b i a s e d j u n c t i o n b e t w e e n t h e drain
m a k e it less susceptible t o n o i s e as well as solving t h e l e a k a g e a n d c h a r g e - s h a r i n g p r o b l e m s .
l e a k a g e c u r r e n t that will c a u s e C
L
to slowly discharge and v
Y
diffusion of t r a n s i s t o r s c o n n e c t e d t o t h e o u t p u t n o d e a n d t h e s u b s t r a t e . S u c h c u r r e n t s c a n b e i n t h e r a n g e of l C f
12
15
A to 10~ A, and they increase rapidly with temperature (approx-
i m a t e l y d o u b l i n g for e v e r y 1 0 ° C rise i n t e m p e r a t u r e ) . T h u s t h e circuit c a n m a l f u n c t i o n if
A n o t h e r a p p r o a c h to solving t h e c h a r g e - s h a r i n g p r o b l e m is t o p r é c h a r g e t h e internal n o d e s , that is, t o p r é c h a r g e capacitor C . T h e p r i c e p a i d in this case is i n c r e a s e d circuit c o m p l e x i t y x
and n o d e c a p a c i t a n c e s .
t h e c l o c k is o p e r a t i n g at a v e r y l o w f r e q u e n c y a n d t h e o u t p u t n o d e is n o t " r e f r e s h e d " perio d i c a l l y . T h i s e x a c t s a m e p o i n t will b e e n c o u n t e r e d w h e n w e s t u d y d y n a m i c m e m o r y cells
Cascading D y n a m i c Logic Gates
in C h a p t e r 1 1 .
d y n a m i c l o g i c g a t e s . C o n s i d e r t h e situation d e p i c t e d in F i g . 1 0 . 3 5 , w h e r e t w o s i n g l e - i n p u t
A s e r i o u s p r o b l e m arises if o n e a t t e m p t s t o c a s c a d e
d y n a m i c g a t e s a r e c o n n e c t e d in c a s c a d e . D u r i n g t h e p r é c h a r g e p h a s e , C
and C
Ll
Charge Sharing
T h e r e is a n o t h e r a n d often m o r e serious w a y for C t o l o s e s o m e of its L
be charged through Q
pl
p2
c h a r g e a n d thus c a u s e v to fall significantly b e l o w V . T o see h o w this c a n h a p p e n , refer to
vn = DD a n d v
Fig. 10.34(a), w h i c h s h o w s only Q a n d Q , t h e t w o t o p transistors of the P D N , together with
of h i g h i n p u t A . O b v i o u s l y , t h e correct r e s u l t w i l l b e Y l o w (v
the p r é c h a r g e transistor Q . H e r e , C is t h e c a p a c i t a n c e b e t w e e n t h e c o m m o n n o d e of Q and
V ).
Y
DD
V
Y2
l
2
= V . DD
N o w c o n s i d e r w h a t h a p p e n s i n t h e e v a l u a t i o n p h a s e for t h e c a s e 1
p
x
x
DD
Q a n d g r o u n d . A t the b e g i n n i n g of t h e e v a l u a t i o n p h a s e , after Q h a s t u r n e d off a n d with C 2
p
L
DD
(Fig. 10.34a), w e a s s u m e that C is initially d i s c h a r g e d a n d that t h e inputs x
begins to discharge. Only when v
drops below V
Y1
than t h e e x p e c t e d v a l u e of V .
m
Y2
2
l o w . W e c a n easily see that Q will turn on, a n d its drain current, i , will flow as indicated. x
2
begins to discharge. However, simultaneously, Q turns on and C
ever, b y t h a t t i m e , C
2
= 0 V ) a n d Y h i g h {v
= Y
turns o n a n d C
are s u c h that at t h e gate of Q w e h a v e a h i g h signal, w h e r e a s at t h e gate of Q t h e signal is x
Y1
W h a t h a p p e n s , h o w e v e r , is s o m e w h a t different. A s t h e e v a l u a t i o n p h a s e b e g i n s , Q L1
charged to V
will
L2
a n d Q , r e s p e c t i v e l y . T h u s , at t h e e n d of t h e p r é c h a r g e i n t e r v a l ,
L2
m
L2
also
will Q turn off. U n f o r t u n a t e l y , h o w 2
will h a v e lost a significant a m o u n t of its c h a r g e , a n d v
Y2
will b e less
( H e r e , it is i m p o r t a n t t o n o t e that in d y n a m i c l o g i c , o n c e
DD
c h a r g e h a s b e e n lost, it c a n n o t b e r e c o v e r e d . ) T h i s p r o b l e m i s sufficiently s e r i o u s t o m a k e simple cascading an impractical proposition. A s usual, h o w e v e r , the ingenuity of circuit DD
designers h a s c o m e to t h e rescue, a n d a n u m b e r of s c h e m e s h a v e b e e n proposed to m a k e cas-
A
cading possible in dynamic-logic circuits. W e shall discuss o n e such s c h e m e after considering E x e r c i s e 10.12.
1
= VDD O — o j
jo -or V
f
V o—i
v
DD
Q
DD
A i o—OJ
A
o - o ) Q
QL
P
DD
DD
A
A
Q,•pi
-OF
Cr
T OVo
|l
¿p2
0:
I I I
(a)
i
J _
10
> O
\\_J2e
J
i
(b)
FIGURE 1 0 . 3 4 (a) Charge sharing, (b) Adding a permanendy turned-on transistor Q solves the chargesharing problem at the expense of static power dissipation. L
FIGURE 1 0 . 3 5 Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase C will partially discharge and the output at Y will fall lower than V , which can cause logic malfunction. L2
2
DD
'
995
996
I". V "Van**
CHAPTER 10
DIGITAL CMOS
LOGIC
CIRCUITS 10.6
-
DYNAMIC
LOGIC CIRCUITS
EXERCISE 10.12 T o gain further insight into the cascading problem described, let us determine the decrease in the output - voltage r.')- for the circuit in Fig. 10.35. Specifically, consider the circuit as the evaluation phase begins: At if = 0, r.' .| = v = V and v = v = V . Transistors Q and Q,, are cut off and can be removed from the equivalent circuit. Furthermore, for the purpose of this approximate analysis, we can replace the series combination of ¡2, and Q with a single device having an appropriate W/L, and similarly for the combination of Q and Q , . The result is the approximate equivalent circuit in Fig. E10.J2. W e are interested in the operation of this circuit id the interval At during which v , fails from V to V, at which time CJ turns off and C slops discharging. A s s u m e that the process technology has (he parameter values specified in E x a m p l e 10.4: that for all N M O S transistors in the circuil of Fig. 10.35. W/L = 4 pm/2 ,um, and that C,, = C = 40 IE. ;
}
Y2
DD
6
A
DD
p]
X
2
ei
2
t 2
Y
cq2
DD
Bo— Co—I
h2
pjj\
L2
FIGURE 1 0 . 3 6 The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, 7 either will remain low (at 0 V) or will make one 0-to-l transition (to V ).
CJe,2 1
l|. ^
.
=
DD
('•
FIGURE E 1 0 . 1 2 (a) Find ( W / X ) ,
and(W/L) .
e q
(b) Find the values of i
eq2
m
at%, = V
DD
(c) Use the average value of i
pl
and at v
n
= V,. Hence determine an average value for i . m
found in (b) to determine an estimate for the interval At.
(d) Find the average value of i during Af. To simplify matters, take the average to be the value of i obtained w h e n the gate voltage » is midway through its excursion (i.e., vy, = 3 ¥ ) . (Hint: Q will remain in saturation.) D2
D2
n
eq2
(e) Use the value of Âtfound m (e) together with t h e a v e r a g e value of% detcrminedin (d) tofind an estimate of the reduction in v d u r i n g A r . H e n e e rieterminethe final value of v . 2
Y2
Y2
Ans. (a) 1,1; (b) 400 i/A and 175 pA, for an average value of 288 p.A; (c) 0.56 ns; (d) 100 pA; (e) Av 1.4 \ ' . ihus ay. decreases to 3.6 V
n
=
10.6.3 Domino CMOS Logic D o m i n o C M O S logic is a form of d y n a m i c logic that results in cascadable gates. Figure 10.36 s h o w s t h e structure of the D o m i n o C M O S logic gate. W e o b s e r v e that it is s i m p l y the basic d y n a m i c - l o g i c gate of Fig. 10.33(a) with a static C M O S inverter c o n n e c t e d to its output. O p e r a t i o n of the gate is straightforward. D u r i n g p r e c h a r g e , X will b e raised to V , DD
t
and the
gate output Y will b e at 0 V. D u r i n g e v a l u a t i o n , d e p e n d i n g on the c o m b i n a t i o n of input variables, either X will r e m a i n high a n d thus the o u t p u t Y will r e m a i n l o w (t
PHL
b r o u g h t d o w n to 0 V a n d t h e o u t p u t F will rise to V
DD
(t
PLH
= 0) or X will be
finite). T h u s , d u r i n g evaluation,
(b) FIGURE 1 0 . 3 7 (a) Two single-input Domino CMOS logic gates connected in cascade, (b) Waveforms during the evaluation phase.
the o u t p u t either r e m a i n s l o w or m a k e s only o n e l o w - t o - h i g h transition. T o see w h y D o m i n o C M O S gates can b e cascaded, consider the situation in Fig. 10.37(a),
T h u s , as (j) g o e s u p , capacitor C will b e g i n d i s c h a r g i n g , p u l l i n g X d o w n . M e a n w h i l e , the low i n p u t at the g a t e of Q k e e p s Q off, a n d C r e m a i n s fully charged. W h e n v falls below t h e t h r e s h o l d v o l t a g e of inverter / , , Y will g o u p t u r n i n g Q on, w h i c h in turn b e g i n s to d i s c h a r g e C a n d pulls X low. E v e n t u a l l y , Y rises to V . L1
w h e r e w e s h o w t w o D o m i n o gates c o n n e c t e d in c a s c a d e . F o r simplicity, w e s h o w single-
2
i n p u t gates. A t the e n d of p r e c h a r g e , X
x
will b e at V , DD
Y, will b e at 0 V, X will b e at 2
V , DD
t
2
L2
xl
x
and Y will b e at 0 V . A s in the preceding case, a s s u m e A is high at the beginning of evaluation. 2
L2
2
2
2
DD
K
'_
'
9 9 7
9."
i
CHAPTER 10
DIGITAL CMOS
LOGIC
CIRCUITS
10.7
F r o m this description, w e s e e that b e c a u s e t h e output of the D o m i n o gate is l o w at the
PARAMETERS:
b e g i n n i n g of evaluation, n o p r e m a t u r e c a p a c i t o r d i s c h a r g e will o c c u r in the subsequent gate s e c o n d s after t h e rising e d g e of the clock. S u b s e q u e n t l y , output Y m a k e s a 0 - t o - l transition
MN = 1
after another t
MP = 1
2
interval. T h e p r o p a g a t i o n of t h e rising e d g e t h r o u g h a c a s c a d e of gates
resembles contiguously placed d o m i n o e s falling over, each toppling the next, w h i c h is the ori-
<;'_-.
J
VDD
C L = 0.5p
in t h e c a s c a d e . A s indicated in F i g . 10.37(b), output 7j will m a k e a 0 - t o - l transition t»,,
PLH
SPICE S I M U L A T I O N E X A M P L E
M = {MP} W = 1.25u L = 0.5u
V D D = 3.3
gin of the n a m e D o m i n o C M O S logic. D o m i n o C M O S logic finds application in the design of address decoders in m e m o r y chips, for e x a m p l e .
PMOS0P5
VDD IN
A
10.6.4 Concluding Remarks
OUT
D y n a m i c logic presents m a n y c h a l l e n g e s t o t h e circuit designer. A l t h o u g h it c a n provide c o n s i d e r a b l e r e d u c t i o n in t h e c h i p - a r e a r e q u i r e m e n t , as w e l l as h i g h - s p e e d operation, and zero (or little) static-power dissipation, t h e circuits are p r o n e to m a n y n o n i d e a l effects, some
Vsupply
VI V2 TD TR TF PW PER
of w h i c h h a v e b e e n discussed h e r e . It s h o u l d also b e r e m e m b e r e d that d y n a m i c - p o w e r dissiDC = {VDD}
pation is a n important issue in d y n a m i c logic. A n o t h e r factor that should b e considered is the " d e a d t i m e " during p r é c h a r g e w h e n t h e output of t h e circuit is n o t y e t available.
¡0.7
SPICE SIMULATION EXAMPLE
M = {MN} W = 1.25u L = 0.5u
= 0 = {VDD} = 2n = lp = lp = 6n = 12n
:{CL} NMOS0P5
W e c o n c l u d e this chapter with a n e x a m p l e illustrating t h e u s e of S P I C E i n t h e analysis of C M O S digital circuits. T o appreciate t h e n e e d for S P I C E , recall that t h r o u g h o u t this chapter
FIGURE 1 0 . 3 8
Capture schematic of the CMOS inverter in Example 10.5.
w e h a v e h a d t o m a k e m a n y simplifying a s s u m p t i o n s s o that m a n u a l analysis c a n b e m a d e p o s s i b l e and also s o that the results c a n b e sufficiently simple t o yield design insight. This is especially t h e case in t h e analysis of t h e d y n a m i c operation of logic circuits. Computer-aided analysis u s i n g S P I C E n o t only obviates t h e n e e d t o m a k e a p p r o x i m a t i o n s , thus providing accurate results, but it also allows the u s e of m o r e precise M O S F E T m o d e l s . S u c h models, of c o u r s e , are too c o m p l e x to u s e in m a n u a l analysis.
To c o m p u t e both t h e voltage transfer characteristic ( V T C ) of the inverter and its supply current at various values of the input voltage V" , w e apply a dc voltage source at the input and in
perform a dc analysis with V" swept over the range 0 to V . T h e resulting V T C is plotted in in
DD
Fig. 10.39. N o t e that t h e slope of t h e V T C in t h e switching region (where t h e N M O S and P M O S devices are both in saturation) is n o t infinite as predicted from the simple theory p r e sented earlier (Section 4.10, Fig. 4.55). Rather, the nonzero value of X causes the inverter gain to b e finite. Using t h e derivative feature of Probe, w e can find the two points on the V T C at which the inverter gain is unity (i.e., the V T C slope is - 1 V/V) and, h e n c e , determine V
IL
OPERATION OF THE CMOS INVERTER
and
V . Using the results given in Fig. 10.39, the corresponding noise margins are NM = NM = IH
L
H
In this example, w e will use PSpice to simulate the C M O S inverter whose Capture schematic is
1.34 V for t h e inverter with m/ni, = 4 , while NM = 0.975 V a n d NM
shown in Fig. 10.38. W e will assume a 0.5-/xm C M O S technology for the M O S F E T s and use
inverter with m /m
parts N M O S 0 P 5 and P M O S 0 P 5 whose level-1 model parameters are listed in Table 4.8. In addi-
obtained using t h e approximate formula in Eq. (10.8). Furthermore, note that, with »^/m„ =
L
p
n
H
= 1.74 V for t h e
= 1. Observe that these results correlate reasonably well with the values
tion to the channel length L and the channel width W, w e have used the multiplicative factor m to
ft/ft>
specify the dimensions of the M O S F E T s . T h e M O S F E T parameter m, whose default value is 1, is
are equal.
used in SPICE to specify the number of unit-size M O S F E T s connected in parallel (see Fig. 6.65).
The threshold voltage V of the C M O S inverter is defined as the input voltage in an identical output voltage w , that is,
In our simulations, we will use unit-size transistors with L = 0.5 / a n and W= 1.25 /im. W e will simulate the inverter for two cases: (a) setting m /m p
= 4 so that the P M O S transistor is four times
p
wider than the N M O S transistor (to compensate for the lower mobility in /7-channel devices as compared with re-channel ones). Here, m and m are the multiplicative factors of, respectively, n
the N M O S and P M O S transistors of the inverter.
th
that results
0 U T
= 1 so that the N M O S and P M O S transistors
n
have equal widths, and (b) setting rtip/m^ = p /p n
= 4, the N M O S and P M O S devices are closely matched and, hence, the two noise margins
p
(10.53)
9 9 9
CHAPTER 10
DIGITAL CMOS
LOGIC
CIRCUITS
10.7
3.3V
3.3V
—•
m
m
pl n
=
•
!
1
:
V - M
l \
•
=
1
:
:
•
:
!
1
SPICE S I M U L A T I O N
EXAMPLE
:
4
" T v ; = T . 6 4 v ^ ^ ^ 1.35 V s j
:- V =
2.475V — •
!H
1 n O
1.65 V
•
V (OUT)
5—ä
1 i
'
V A
3
1
1
V (IN) (a)
400uA
•
•
•
!
:
•
:I
•
1
•
\
j
1
^
0.825V 200uA
•
!
|
/
m /l«,= p
l V
>y
1
!
0V
0.825V
0V o
3.3V
2.475V
o V (OUT)
F I G U R E 1 0 . 3 9 Input-output voltage transfer characteristic (VTC) of the CMOS inverter in Example 10.5 with m /m = 1 and m /m = 4 . p
n
p
n
OA 0V 0.825 V o o — l (Vsupply)
1.650V
3.3V
2.475V
V(IN) (b)
F I G U R E 1 0 . 4 0 (a) Output voltage, and (b) supply current versus input voltage for the CMOS inverter in Example 10.5 with m /m = 1 and m /m = 4. n
p
n
Thus, as shown in Fig. 10.40, V is the intersection of the V T C with the straight line corresponding th
to v
=
0 U T
(this line can b e simply generated in Probe by plotting v
Fig. 10.40). Note that V ~ V /2 th
m /m p
decreases V
n
th
current versus
DD
for the inverter with m /m p
m
versus v
o m
, as shown in
= 4 . Furthermore, decreasing
n
(see earlier: Exercise 4.44). Figure 10.40 also shows the inverter supply
Observe that the location of the supply-current peak shifts with the threshold
voltage. T o investigate the dynamic operation of the inverter with P S p i c e , w e apply a pulse signal at t h e input (Fig. 10.38), perform a transient analysis, and plot t h e input a n d output wave forms as shown in Fig. 10.41. T h e rise and fall times of the pulse source are chosen t o b e very short. N o t e that increasing m /m p
n
from 1 t o 4 decreases t
PLH
(from 1.13 ns t o 0.29 ns) because
of t h e increased current available t o charge C , with only a minor increase in t L
PHL
0.33 ns t o 0.34 ns). T h e t w o propagation delays, t
PLH
m /m p
V(IN)
and t , PHL
(from
are not exactly equal when
= 4 because t h e N M O S a n d P M O S transistors a r e still n o t perfectly m a t c h e d (e.g.,
n
V,n*\V \). tp
lOn
12n
14n
Time (s) FIGURE 1 0 . 4 1 Transient response of the CMOS inverter in Example 10.5 with m /m p
n
= 1 and m /m„ = 4 . p
1 0 0 2
•
CHAPTER 10
DIGITAL CMOS
LOGIC
PROBLEMS
CIRCUITS
.
1 0 0 3
SUMMARY •
•
Although CMOS is one of four digital IC technologies currently in use (the others are bipolar, BiCMOS and GaAs), it is the most popular. This is due to its zero staticpower dissipation and excellent static and dynamic characteristics. Further, advances in CMOS process tech nology have made possible the fabrication of MOS tran sistors with channel lengths as small as 0.06 Lira. The high input impedance of MOS transistors allows the use of charge storage on capacitors as a means of realizing mem ory, a technique successfully exploited in both dynamic logic and dynamic memory. The CMOS inverter is usually designed using the mini mum channel length for both the NMOS and PMOS transistors. The width of the NMOS transistor is usually 1.5 to 2 times L, and the width of the PMOS device is (Li /ii ) times that. This latter (matching) condition ensures that the inverter will switch at V /2 and gives equal current-driving capabilities in both directions and hence symmetrical propagation delays. n
are made equal to those of the basic (matched) inverter. Transistor sizing is based on this principle and makes use of the equivalent (W/L) ratios of series and parallel devices (Eqs. 10.27 and 10.28). •
Complementary CMOS logic utilizes two transistors, an NMOS and a PMOS, for each input variable. Thus the circuit complexity, silicon area, and parasitic capaci tance all increase with fan-in.
•
To reduce the device count, two other forms of static CMOS, namely, pseudo-NMOS and pass-transistor logic (PTL), are employed in special applications as supplements to complementary CMOS.
•
p
A simple technique for determining the propaga tion delay of a logic gate is to determine the average current 7 available to charge (or discharge) a load capacitance C. Then, t (or t ) is determined as C(V /2)/7 .
0L
•
av
PLH
D D
M
•
pm
a v
A complementary CMOS logic gate consists of an NMOS pull-down network (PDN) and a PMOS pull-up network (PUN). The P D N conducts for every input combination that requires a low output. Since an NMOS transistor conducts when its input is high, the PDN is most directly synthesized from the expression for the low output ( ? ) as a function of the uncomplemented inputs. In a complementary fashion, the PUN conducts for every input combination that corresponds to a high output. Since a PMOS conducts when its input is low, the PUN is most directly synthesized from the expres sion for a high output (F) as a function of the comple mented inputs. CMOS logic circuits are usually designed to provide equal current-driving capability in both directions. Furthermore, the worst-case value of the pull-up and pull-down currents
Pseudo-NMOS utilizes the same PDN as in complemen tary CMOS logic but replaces the PUN with a single PMOS transistor whose gate is grounded. Unlike comple mentary CMOS, pseudo-NMOS is a ratioed form of logic in which V is determined by the ratio r of k to k . Nor mally, r is selected in the range 4 to 10 and its value determines the noise margins. n
p
Pseudo-NMOS has the disadvantage of dissipating static power when the output of the logic gate is low. Static power can be eliminated by turning the PMOS load on for only a brief interval, known as the pré charge interval, to charge the output node to V . Then the inputs are applied, and depending on the input com bination, the output node either remains high or is dis charged through the P D N . This is the essence of dynamic logic. DD
II
Pass-transistor logic utilizes either single NMOS transistors or CMOS transmission gates to implement a network of switches that are controlled by the input logic variables. Switches implemented by single NMOS transistors, though simple, result in the reduction of V from V to 0H
DD
v -v DB
•
r
A particular form of dynamic logic circuits, known as domino logic, allows the cascading of dynamic logic gates.
becomes 150 /xA. Estimate the equivalent capacitance at the output node of the inverter.
1 0 . 1 For a logic-circuit family employing a 3-V supply, suggest an ideal set of values for V, , V , V , V , V , NM , NM . Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply? h
DD
•
SECTION 1 0 . 1 : DIGITAL CIRCUIT DESIGN: AN OVERVIEW
L
IL
m
0L
0H
H
1 0 . 2 For a particular logic-circuit family, the basic techno logy used provides an inherent limit to the small-signal lowfrequency voltage gain of 50 V/V. If, with a 3.3-V supply, the values of V and V are ideal, but V = 0.4 V , what are the best possible values of V and V that can be expected? What are the best possible noise margins you could expect? If the actual noise margins are only 7 / 1 0 of these values, what V, and V result? What is the large-signal voltage gain [defined as (V - V )/(V - V )]. (Hint: Use straightline approximations for the VTC.) 0L
0H
th
IL
L
DD
lH
m
0H
0L
IL
IH
* 1 0.3 A logic-circuit family intended for use in a digitalsignal-processing application in a newly developed hearing aid can operate down to single-cell supply voltages of 1.2 V. If for its inverter, the output signals swing between 0 and V , the "gain-of-one" points are separated by less than 1/3 V , and the noise margins are within 30% of one another, what ranges of values of V , V , V V , NM , and NM can you expect for the lowest possible battery supply? DD
DD
IL
m
ou
0H
L
H
1 0 . 4 In a particular logic family, the standard inverter, when loaded by a similar circuit, has a propagation delay specified to be 1.2 ns: (a) If the current available to charge a load capacitance is half as large as that available to discharge the capacitance, what do you expect t and t to be? (b) If when an external capacitive load of 1 pF is added at the inverter output, its propagation delays increase by 70%, what do you estimate the normal combined capacitance of inverter output and input to be? (c) If without the additional 1-pF load connected, the load inverter is removed and the propagation delays were observed to decrease by 40%, estimate the two components of the capacitance found in (b) that is, the component due to the inverter output and other associated parasitics, and the com ponent due to the input of the load inverter? PLH
1 0 . 6 A collection of logic gates for which the static-power dissipation is zero, and the dynamic-power dissipation, as specified by Eq. (10.4), is 10 mW are operated at 50 MHz with a 5-V supply. By what fraction could the power dissipa tion be reduced if operation at 3.3 V were possible? If the frequency of operation is reduced by the same factor as the supply voltage (i.e., 3 . 3 / 5 ) , what additional power can be saved? D 1 0 . 7 A logic-circuit family with zero static-power dissi pation normally operates at V = 5 V. To reduce its dynamic-power dissipation, which is specified by Eq. (10.4), operation at 3.3 V is considered. It is found, however, that the currents available to charge and discharge load capaci tances also decrease. If current is (a) proportional to V , or (b) proportional to Vp , what reductions in maximum operating frequency do you expect in each case? What fractional change in delay-power product do you expect is each case? DD
DD
D
D * 1 0 . 8 Reconsider the situation described in Problem 10.7, for the situation in which a threshold relation exists such that the current depends on (V — V,) rather than V directly. Evaluate the change of current, propagation delay, operating frequency, dynamic power, and delay-power product as a result of decreasing V from 5 V to 3.3 V. Assume that the currents are proportional to (a) (V — V,), or (b) (V — V,) , for V, equal to (i) 1 V and (ii) 0.5 V. DD
DD
DD
DD
DD
0 * 1 0 . 9 Consideration is being given to reducing by 10% all dimensions, including oxide thickness, of a silicon digital CMOS process. Recall that for a MOS device the available current is related to
PHL
1 8 . 5 In a particular logic family, operating with a 3.3-V supply, the basic inverter draws (from the supply) a current of 40 LiA in one state and 0 LlA in the other. When the inverter is switched at the rate of 100 MHz, the average supply current
i =
1
W
2 ^C ^(V -V f 0X
DD
t
where C = e /t . Also assume that the total effective capacitance that determines the propagation delay is divided about equally between MOS capacitances that are propor tional to area and inversely proportional to oxide thickness, and reverse-bias junction capacitances that are proportional to area. Find the factors by which the following parameters change: chip area, current, effective capacitance, propaga tion delay, maximum operating frequency, dynamic power dissipation, delay-power product, and performance (in operations per unit area per second). If the supply voltage is also reduced by 10% (but V, is not), what other changes result? ox
ox
ox
, ,
1 0 0 4
CHAPTER 1 0 D I G I T A L C M O S
LOGIC
CIRCUITS
1 0 . 1 0 Consider an inverter for which t , t , t , and t are 20 ns, 10 ns, 30 ns, and 15 ns, respectively. The ris ing and falling edges of the inverter output can be approxi mated by linear ramps. Two such inverters are connected in tandem and driven by an ideal input having zero rise and fall times. Calculate the time taken for the output voltage to complete 90% of its excursion for (a) a rising input and (b) a falling input. What is the propagation delay for the inverter? PLH
PHL
TLH
THL
1 0 . 1 1 A particular logic gate has t and t of 50 ns and 70 ns, respectively, and dissipates 1 m W with output low and 0.5 m W with output high. Calculate the corre sponding delay-power product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation). PLH
SECTION 1 0 . 2 :
PHL
DESIGN AND PERFORMANCE
PROBLEMS
1 0 . 1 6 Use Eq. (10.8) to explore the variation of V with the ratio r = k /k . Specifically, calculate V for the case V, = \V \ = 0.5 V and V = 2.5 V for r = 0.5, l, 1.5, 2, and 3. Note that V is not a strong function of r around the point r = 1.
1 0 . 2 4 Repeat Problem 10.23 for an inverter for which (W/L) = (W/L) = 0.75 pm/0.5 pm. Find t and the dynamic power dissipation when the circuit is operated at a 250-MHz rate.
D 1 0 . 1 7 Design a "matched" inverter whose area is 15 p in a process for which the minimum length is 0.5 LLXXI and Li /ji = 3. By what factor does the maximum output current available from this inverter exceed that of the minimum-size inverter for which the factor n = 1.5? What is the ratio of their areas? What is the ratio of their output resistances?
D 1 0 . 2 5 Sketch a CMOS realization for the function = A + B(C + D).
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n
n
p
th
tp
DD
th
2
m
n
p
1 0 . 1 8 For a CMOS inverter having k = k = 300 LLA/V V = \V \ = 0.8 V, V - 3.3 V, and X = A = 0.05 V" ' find Vnm OH, V, * m , Vn " OL, VIL, H, NM , V , and the voltage gain at the threshold point M. [Hint: The small-signal voltage gain 2
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tp
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NM
L
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1 0 . 1 2 For a CMOS inverter operating from a 3.3-V supply in a technology for which \V,\ = 0.8 V, and k' = Ak' = 180 LLA/V , evaluate the drain-source resistance asso ciated with minimum-size transistors for which W/L = 0.75 t i m / 0 . 5 /ira. For which ratio (W/W„) will Q and Q , which have equal channel lengths, have equal resistances?
1 0 . 1 9 For a particular matched CMOS inverter, k' = 15pAIN ,{W/L) = 8 pm/O.S pm, p/p = 2.5. The cir cuit has an equivalent output capacitance with two major components, one proportional to device width of 2-fF//xm width for each device, and the other fixed, at 50 fF. What total equivalent capacitance is associated with the output node? Calculate t using Eq. (10.13) for a supply of 3.3 V.
1 0 . 1 3 A CMOS inverter fabricated in the process specified in Problem 10.12 utilizes a p-channel device four times as wide as the n-channel device. If the V supply is subject to very-high-frequency noise and there is an equivalent load capacitance of 1 pF, what is the 3-dB cutoff frequency embodied in each gate for this supply noise?
1 0 . 2 0 Use Eqs. (10.14) to (10.17) to derive an expression for t in which V, is expressed as a fraction a of V (i.e., V, = aV ). Find the value of the multiplier in the numerator of the expression, for a in the range 0.1 to 0.5 (e.g., for a= 0.2 me multiplier is 1.7).
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2
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P
DD
1 0 . 1 4 A CMOS inverter for which k = I0k = 100/iA/V and V, = 0.5 V is connected as shown in Fig. PI 0.14 to a sinu soidal signal source having a Thevenin equivalent voltage of 0.1-V peak amplitude and resistance of 100 kO. What signal voltage appears at node A with v = +1.5 V? With v = -1.5 V? 2
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SECTION 1 0 . 3 :
2
n
P
PHL
CMOS LOGIC-GATE CIRCUITS
Y
p i 0 . 2 6 A CMOS logic gate is required to provide an out put Y = ABC + ABC + ABC. How many transistors does it need? Sketch a suitable PUN and PDN, obtaining each first independently, then one from the other using the dualnetworks idea.
DD
1 0 . 2 1 Find the propagation delay for a minimum-size inverter for which k' = 3k' = 180 pAN and (W/L) = (W/L) = 0.75 JUM/0.5 pm, V = 3.3 V, and the capaci tance is roughly 2 fF/ixm of device width plus 1 fF/device. What does t become if the design is changed to a matched one? 2
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D 1 0 . 3 3 Consider the CMOS gate shown in Fig. 10.14. Specify W/L ratios for all transistors in terms of the ratios n and p of the basic inverter, such that the worst-case t and t of the gate are equal to those of the basic inverter. PHL
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D 1 0 . 2 8 Sketch a CMOS logic circuit that realizes the function Y = AB + AB. This is called the equivalence or coincidence function.
D 1 S . 3 4 Find appropriate sizes for the transistors used in the exclusive-OR circuit of Fig. 10.15(b). Assume that the basic inverter has (W/L) = 0.75 i i m / 0 . 5 pm and (W/L) = 3.0 i i m / 0 . 5 pm. What is the total area, including that of the required inverters? n
D 1 0 . 2 9 Sketch a_CMOS logic circuit that realizes the func tion Y = ABC + ABC.
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(a) Give the Boolean function P . (b) Sketch a PDN directly from the expression for F . Note that it requires 12 transistors in addition to those in the inverters. (c) From inspection of the PDN circuit, reduce the number of transistors to 10.
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1 0 . 3 6 Figure P10.36 shows two approaches to realizing the OR function of six input variables. The circuit in Fig. P10.36(b), though it uses additional transistors, has in fact
1
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6
1 0 . 2 2 A CMOS microprocessor chip containing the equiv alent of 1 million gates operates from a 5-V supply. The power dissipation is found to be 9 W when the chip is operat ing at 120 MHz, and 4.7 W when operating at 50 MHz. What is the power lost in the chip by some clock-independent mechanism, such as leakage and other static currents? If 70% of the gates are assumed to be active at any time, what is the average gate capacitance in such a design? 1 0 . 2 3 A matched CMOS inverter fabricated in a process for which C = 3.7 f F/tzm , p C = 180 pAN , p C = 45 tiA/W V = -V = 0.7 V, and V = 3.3 V, uses W„ = 0.75 pm a n d L L = 0.5 pm. The gate-drain overlap capacitance and effec tive drain-body capacitance per micrometer of gate width are 0.4 fF and 1.0 fF, respectively. The wiring capacitance is C„ = 2 fF. Find t , t , and t . For how much additional capaci tance load does the propagation delay increase by 50%? v
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FIGURE P I 0 . 3 6
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1 0 . 3 5 Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capacitance between the output node and ground. Compare the values of t and t , obtained when the devices are sized as in Fig. 10.17, to the values obtained when all n-channel devices have W/L = n and all p-channel devices have W/L =p.
D10.3Q It is required to design a CMOS logic circuit that realizes a three-input even-parity checker. Specifically, the output Y is to be low when an even number (0 or 2) of the inputs A, B, and C are high.
P
m
m
D 1 0 . 3 2 Design a CMOS full-adder circuit with inputs A, B, and C, and two outputs S and C such that S is 1 if one or three inputs are 1, and C is 1 if two or more inputs are 1.
D 1 0 . 2 7 Give two different realizations of the exclusiveOR function Y = AB + AB in which the PDN and the PUN are dual networks.
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1 0 . 1 5 For a generalized CMOS inverter characterized by V , V , k , and k , derive the relation in Eq. (10.8) for V .
D 1 0 . 3 1 Give a CMOS logic circuit that realizes the func tion of three-input odd-parity checker. Specifically, the output is to be high when an odd number (1 or 3) of the inputs are high. Attempt a design with 10 transistors (not counting those in the inverters) in each of the PUN and the PDN.
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FIGURE P 1 0 . 1 4
(d) Find the PUN as a dual of the PDN in (c), and hence the complete realization.
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ANALYSIS OF THE CMOS INVERTER
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1006
. . V
CHAPTER 10
PROBLEMS
DIGITAL C M O S LOGIC CIRCUITS
D* 1 0 . 3 9 Design a pseudo-NMOS inverter that has equal positive and negative capacitive-driving output currents at v = V /4 for use in a system with V = 5 V, \V,\ = 0.8 V k' = 3k' = 75 flAJV , and (W/L)„ = 1.2 fim/0.8 fim. What are the values of (W/L) , V , V , V , V , V , NM , andNM 7
less total area and lower propagation delay because it uses NOR gates with lower fan-in. Assuming that the transistors in both circuits are properly sized to provide each gate with a current-driving capability equal to that of the basic matched inverter, find the number of transistors and the total area of each circuit. Assume the basic inverter to have a (W/L) ratio of 1.2 i i m / 0 . 8 fim and a (W/L) ratio of n
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1 0 . 4 0 Consider a pseudo-NMOS inverter with r = 2, (W/L) = 1.2 i i m / 0 . 8 ^ m , V = 5 V, \V,\ = 0.8 V, and k' = 3k' = 75 flAJV . Let the device capacitances per micrometer of device width be C = 1 . 5 fF, C = 0.5 fF, and C = 2 f F. Estimate the input and output capacitances and the values of t , t , and t obtained when the inverter is driv ing another identical inverter. Also find the corresponding values for a complementary CMOS inverter with a matched design. n
n
» 1 0 . 3 7 Consider the two-input CMOS NOR gate of Fig. 10.12 whose transistors are properly sized so that the current-driving capability in each direction is equal to that of a matched inverter. For \ V \ = 1 V and V - 5 V, find the gate threshold in the cases for which (a) input terminal A is connected to ground and (b) the two input terminals are tied together. Neglect the body effect in Q .
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* 1 0 . 4 1 Use Eq. (10.41) to find the value of r for which NM is maximized. What is the corresponding value of NM[7 L
SECTION 1 0 . 4 :
PSEUDO-NMOS
LOGIC CIRCUITS
D1 0 . 4 2 Design a pseudo-NMOS inverter that has V = 0.1V. Let V = 2.5 V, | V | = 0.4 V, k' = 4k' = 120 flAN , and (W/L)„ = 0.375 t m i / 0 . 2 5 fim. What is the value of (W/L) 7 Calculate the values of NM and the static power dissipation. 0L
1 0 . 3 8 The purpose of this problem is to compare the value of tp obtained with a resistive load (see Fig. P10.38a) to that obtained with a current-source load (see Fig. P10.38b). For a fair comparison, let the current source I = V /R , which is the initial current available to charge the capacitor in the case of a resistive load. Find t for each case, and hence the percentage reduction obtained when a current-source load is used.
2
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t
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0 * 1 0 . 4 5 It is required to design a minimum-area pseudoNMOS inverter with equal high and low noise margins using 5-V supply and devices for which |V | = 0.8 V, k' = ?,]c' = 7 5 flAJV , and the minimum-size device has (W/L) = 1.2 i i m / 0 . 8 fim. Use r = 2.72 and show that NM — NM . Specify the values of (W/L) and (W/L) . What is the power dissipated in this gate? What is the ratio of propagation delays for high and low transitions? For an external capacitive load of 1 pF, and neglecting the much smaller device capacitances, find t , t , and t . At what frequency of operation would the static and dynamic power levels be equal? Is this speed of operation possible in view of the t value you found? What is the ratio of dynamic power to static power at what you may assume is the maximum usable oper ating frequency [say, l/(2t + 2t )]7 a
fim.
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1 0 . 4 4 For a pseudo-NMOS inverter, what value of r results M = NM„. Let V = 5 V and \V \ = 0.8 V. What is the resulting margin? i n
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D1 0 . 4 6 Sketch a pseudo-NMOS realization of the function Y = A+B(C + D).
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D1 © . 4 8 Consider a four-input pseudo-NMOS NOR gate in which the NMOS devices have (W/L) = (1.8 fim/1.2 fim). It is required to find (W/L) so that the worst-case value n
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FIGURE P I 0 . 4 9
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SECTION 1 0 . 5 :
PASS-TRANSISTOR
LOGIC CIRCUITS
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D 1 0 . 4 7 Sketch a pseudo-NMOS realization of the exclusiveOR function Y = AB + AB.
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1 0 . 4 3 For what value of r does NM of a pseudo-NMOS inverter become zero? Prepare a table of NM versus r, for r= 1 to 16.
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and with ground and V connections interchanged. What do the output functions Y become? DD
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* 1 0 . 4 9 A designer, beginning to experiment with the idea of pass-transistor logic, seizes upon what he sees as two good ideas:
A
A
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v
0
v
0
(a) that a string of minimum-size single MOS transistors can do complex logic functions, but (b) that there must always be a path between output and a supply terminal.
* 1 0 . 5 1 Is the circuit in Fig. P10.51 a satisfactory passtransistor circuit? What are its deficiencies? What is Y as a function of A, B, C, D? What does the output become if the two V connections are driven by a CMOS inverter with input E7 DD
Correspondingly, he first considers two circuits (shown in Fig. P10.49). For each, express Y as a function of A and B. In each case, what can be said about general operation? About the logic levels at Y? About node X7 Do either of these cir cuits look familiar? If in each case the terminal connected to V is instead connected to the output of a CMOS inverter whose input is connected to a signal C, what does the func tion Y become?
* 1 0 . 5 2 An NMOS pass-transistor switch with W/L = 1.2 i i m / 0 . 8 iim, used in a 3.3-V system for which V = 0.8 V, 7 = 0.5 V , 2 ^ = 0.6 V , fi C = 3fi C = 75 fiAN , drives a 100-fF load capacitance at the input of a matched static inverter using (W/L) = 1.2 i i m / 0 . 8 fim. For the switch gate terminal at V , evaluate the switch V and V for inputs at V and 0 V, respectively. For this value of V , what inverter static current results? Estimate t and t for this arrangement as measured from the input to the output of the switch itself.
1 0 . 5 0 Consider the circuits in Fig. P10.49 with all PMOS transistors replaced with NMOS, and all NMOS by PMOS,
* D 1 0 . 5 3 The purpose of this problem is to design the level-restoring circuit of Fig. 10.28 and gain insight into its
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1008
CHAPTER 10
DIGITAL C M O S LOGIC CIRCUITS
PROBLEMS
A, find the longest allowable evaluate time if the decay in output voltage is to be limited to 0.5 V. If the précharge interval is much shorter than the maximum allow able evaluate time, find the minimum clocking frequency required.
1 8 . 6 1 The leakage current in a dynamic-logic gate causes the capacitor C to discharge during the evaluation phase, even if the PDN is not conducting. For C = 30 fF, and
1 0 . 6 2 For the four-input dynamic-logic NAND gate ana lyzed in Exercises 10.10 and 10.11, estimate the maximum clocking frequency allowed.
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operation. Assume that k' = 3k' = 7 5 /.lATV , V = 3.3 v , | V, | = 0.8 V, 7 = 0.5 V , 2
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SECTION 1 0 . 6 :
DYNAMIC-LOGIC CIRCUITS
1 / 2
0
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1
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B
DD
(a) Consider first the situation with v = V . Find the value of the voltage v that causes v to drop a threshold voltage below V D, that is, to 2.5 V so that Q turns on. At this value of v , find V, of'Qi. What is the capacitor-charging cutTent available at this time? What is it at v = 0? What is the aver age current available for charging C? Estimate t from the input to v i(b) Now, to determine a suitable W/L ratio for Q , consider the situation when v is brought down to 0 V and Q conducts and begins to discharge C. The voltage v will begin to drop. Meanwhile, v is still low and Q is conducting. The current that Q conducts subtracts from the current of Q , reducing the current available to discharge C. Find the value of v at which the inverter begins to switch. This is V = |(5V - 2V,). Then, find the current that Q conducts at this value of v . Choose W/L for Q so that the current it conducts is limited to one half the value of the current in Q . What is the W/L you have chosen? Estimate t as the time for v to drop from V to V . A
01
DD
D 1 0 . 5 7 Based on the basic dynamic-logic circuit of Fig. 10.33, sketch complete circuits for NOT, NAND, and NOR gates, the latter two with two inputs, and a circuit for which F = AB + CD.
02
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1 0 . 5 8 In this and the following problem, we investigate the dynamic operation of a two-input NAND gate realized in the dynamic-logic form and fabricated in a CMOS pro cess technology for which k' = 3k' = 7 5 itA/V , V, = -V = 0.8 V , and V = 3 V. To keep C small, minimumsize NMOS devices are used for which W/L = 1.2 i i m / 0 . 8 pm (this includes Q ). The PMOS précharge transistor Q has 2.4 i i m / 0 . 8 /um. The capacitance C is found to be 15 fF. Consider the précharge operation with the gate of Q at 0 V, and assume that at t = 0, C is fully discharged. We wish to calculate the rise time of the output voltage, defined as the time for v to rise from 10% to 90% of the final value of 3 V. Find the current at v = 0.3 V and the current at v = 2.7 V, then compute an approximate value for t , t = C ( 2 . 7 - 0 . 3 ) / / , where 7 is the average value of the two currents. n
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D 1 0 . 5 4 (a) Use the idea embodied in the exclusive-OR realization in Fig. 10.31 to realize Y = AB + AB. That is, find a realization for P using two transmission gates, (b) Now combine the circuit obtained in (a) with the circuit in Fig. 10.31 to obtain a realization of the function Z = YC + YC, where C is a third input. Sketch the complete 12transistor circuit realization of Z. Note that Z is a three-input exclusive-OR. • D 1 0 . 5 5 Using the idea presented in Fig. 10.32, sketch a CPL circuit whose outputs are Y = AB + AB and P = AB + AB. D 1 0 . 5 6 Extend the CPL idea in Fig. 10.32 to three variables to form Z=ABC and Z = ABC = A + B + C.
1 0 . 5 9 For the gate specified in Problem 10.58, evaluate the high-to-low propagation delay, t . To obtain an approximate value of t , replace the three series NMOS transistors with an equivalent device and find the average discharge current. PHL
PHL
* 1 0 . 6 0 In this problem, we wish to calculate the reduction in the output voltage of a dynamic logic gate as a result of charge redistribution. Refer to the circuit in Fig. 10.34(a), and assume that at t = 0 - , v = V , and v - 0. At t = 0,
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m
x
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1009
charge conservation. For V = 1 V, V = 5 V, C = 30 fF, and neglecting the body effect in Q . find the drop in voltage at the output in the two cases: (a) C = 5 fF and (b) C = 10 f F (such that Q remains in saturation during its entire conduc tion interval). m
FIGURE P 1 0 . 5 1
. .
^leakage - 10
CHAPTER 1 1 Memory and Advanced Digital Circuits 1013 INTRODUCTION CHAPTER 12 Filters and Tuned Amplifiers 1083 CHAPTER 13 Signal Generators and Waveform-Shaping Circuits 1165 CHAPTER 14 Output Stages and Power Amplifiers 1 2 2 9
T o r o u n d o u t o u r study of electronic circuits w e h a v e selected, from a m o n g t h e m a n y possible s o m e w h a t - s p e c i a l i z e d topics, four to include in t h e third a n d final part of this b o o k . C h a p t e r 11 deals w i t h t h e i m p o r t a n t subject of digital m e m o r y . In addition, t w o advanced digital-circuit t e c h n o l o g i e s — E C L and B i C M O S — a r e studied. T h e material in Chapter 11 follows naturally t h e study of logic circuits, presented in Chapter 10. Together, these t w o chapters should p r o v i d e a preparation sufficient for a d v a n c e d courses on digital electronics and V L S I design. T h e s u b s e q u e n t t w o chapters, 12 a n d 13, h a v e an applications or s y s t e m s orienta tion: C h a p t e r 12 deals w i t h t h e design of filters, w h i c h are i m p o r t a n t building blocks of c o m m u n i c a t i o n s a n d instrumentation s y s t e m s . Filter design is o n e of t h e rare areas of e n g i n e e r i n g for w h i c h a c o m p l e t e design theory exists, stalling from specification and c u l m i n a t i n g in an actual w o r k i n g circuit. T h e material presented should allow t h e reader to p e r f o r m such a c o m p l e t e design p r o c e s s . In t h e design of electronic systems, t h e n e e d usually arises for signals of various w a v e f o r m s — s i n u s o i d a l , pulse, s q u a r e - w a v e , etc. T h e generation of such signals is the subject of C h a p t e r 1 3 . It will b e seen that s o m e of t h e circuits utilized in w a v e form generation possess m e m o r y a n d a r e in fact t h e analog counterparts of the digital m e m o r y circuits studied in C h a p t e r 1 1 . T h e material i n C h a p t e r s 12 a n d 13 a s s u m e s k n o w l e d g e of o p a m p s (Chapter 2) and m a k e s u s e of frequency r e s p o n s e a n d related s-plane concepts (Chapter 6) a n d of feedback ( C h a p t e r 8). T h e last of the four selected-topics chapters (Chapter 14) deals with the design of amplifiers that are required t o deliver large a m o u n t s of load p o w e r ; for e x a m p l e , t h e amplifier that drives t h e l o u d s p e a k e r in a stereo system. A s will b e seen, t h e design of these h i g h - p o w e r circuits is b a s e d o n different considerations t h a n those for smallsignal amplifiers. M o s t of the material in C h a p t e r 14 should b e accessible to t h e reader w h o h a s studied Part I of this book.
Memory and Advanced Digital Circuits Introduction
1013
11.6
11.1
Latches and Fiip-Flops
11.2
Multivibrator Circuits
1014 1021
Read-Only Memory (ROM)
11.7
Emitter-Coupled Logic (ECL)
11.3
Semiconductor
Random-Access (RAM) Cells
11.5
1052
Memories:
Types and Architectures 11.4
1046
Memory
1031
S e n s e Amplifier and Address Decoders
1028
11.8
B i C M O S Digital C i r c u i t s
11.9
S P I C E Simulation Example Summary
1076
Problems
1077
1067 1071
1038
INTRODUCTION T h e logic circuits studied in Chapter 10 are called c o m b i n a t i o n a l (or combinatorial). Their output depends only on the present value of the input. T h u s these circuits d o not have m e m o r y . Memory is a very important part of digital systems. Its availability in digital computers allows for storing p r o g r a m s and data. Furthermore, it is important for temporary storage of the output produced b y a combinational circuit for use at a later time in the operation of a digital system. L o g i c circuits that incorporate m e m o r y are called sequential circuits; that is, their output d e p e n d s not only o n t h e present value of the input but also o n the i n p u t ' s previous values. S u c h circuits require a t i m i n g generator (a clock) for their operation. T h e r e are basically t w o a p p r o a c h e s for p r o v i d i n g m e m o r y to a digital circuit. T h e first relies o n t h e application of positive feedback that, as will b e seen shortly, can be arranged to p r o v i d e a circuit with t w o stable states. S u c h a bistable circuit can then b e u s e d to store o n e bit of information: O n e stable state would correspond to a stored 0, and the other to a stored 1. A bistable circuit can r e m a i n in either state indefinitely, and thus b e l o n g s to t h e category of static sequential circuits. T h e other a p p r o a c h to realizing m e m o r y utilizes t h e storage of 1 0 1 3
1014
CHAPTER 11
MEMORY
A N D A D V A N C E D
DIGITAL
CIRCUITS
11.1
charge on a capacitor: W h e n t h e capacitor is charged, it w o u l d b e r e g a r d e d as storing a 1w h e n it is discharged, it w o u l d b e storing a 0. Since the inevitable l e a k a g e effects will cause the capacitor to discharge, such a form of m e m o r y requires t h e periodic r e c h a r g i n g of the capacitor, a process k n o w n as refresh. T h u s , like d y n a m i c logic, m e m o r y b a s e d o n charge storage is k n o w n as dynamic memory and the c o r r e s p o n d i n g sequential circuits as dynamic sequential circuits. In a d d i t i o n to t h e study of a v a r i e t y of m e m o r y t y p e s and circuits in this chapter, w e will also learn a b o u t t w o i m p o r t a n t digital-circuit t e c h n o l o g i e s : E m i t t e r - c o u p l e d logic ( E C L ) , w h i c h utilizes b i p o l a r transistors a n d a c h i e v e s v e r y h i g h s p e e d s of o p e r a t i o n ; and B i C M O S , w h i c h c o m b i n e s bipolar transistors and C M O S to great a d v a n t a g e .
LATCHES A N D
As indicated, t h e straight line intersects t h e l o o p transfer c u r v e at three points, A, B , and C. Thus any of these three points can serve as the operating point for the latch. W e shall n o w show that w h i l e points A and C are stable operating points in t h e sense that t h e circuit can remain at either indefinitely, point B is an unstable operating point; t h e latch cannot o p e r a t e at B for any significant period of time. T h e reason point B is unstable can be seen b y considering the latch circuit in Fig. 11.1 (a) to be operating at point B , and taking account of the electrical interference (or noise) that is inev itably present in any circuit. Let the voltage v increase b y a small increment v . T h e voltage at X will increase (in magnitude) by a larger increment, equal to the product of v and the incremental gain of Gj at point B . T h e resulting signal v is applied to G and gives rise to an even larger signal at n o d e Z. T h e voltage v is related to the original increment v b y the loop gain at point B , which is the slope of the curve of v versus v at point B . This gain is usually much greater than unity. Since v is coupled to the input of G it will b e further amplified b y the loop gain. This regenerative process continues, shifting the operating point from B u p w a r d to point C. Since at C the loop gain is zero (or almost zero), n o regeneration can take place. In the description a b o v e , w e a s s u m e d an initial positive voltage i n c r e m e n t at W. H a d w e instead a s s u m e d a n e g a t i v e voltage increment, w e w o u l d h a v e seen that the operating p o i n t m o v e s d o w n w a r d from B to A. Again, since at p o i n t A the slope of t h e transfer c u r v e is z e r o (or almost zero), n o regeneration can take p l a c e . In fact, for regeneration to occur the l o o p gain m u s t b e greater t h a n unity, w h i c h is the c a s e at p o i n t B . T h e discussion a b o v e leads us to c o n c l u d e that t h e latch has t w o stable operating points, A and C. A t p o i n t C, v is high, v is l o w , v is l o w , and v is h i g h . T h e r e v e r s e is true at point A. If w e consider X and Z as the latch outputs, w e see that in o n e of the stable states (say that c o r r e s p o n d i n g to operating point A ) v is h i g h (at V ) and v is l o w (at V ). In t h e other state (corresponding to operating point C) v is l o w (at V ) and v is h i g h (at V ). Thus the latch is a bistable circuit having t w o complementary outputs. T h e stable state in which the latch operates depends on the external excitation that forces it to the particular state. T h e latch t h e n memorizes this external action b y staying indefinitely in t h e acquired state. A s a m e m o r y e l e m e n t t h e latch is c a p a b l e of storing one bit of information. F o r instance, w e can arbitrarily designate t h e state in w h i c h v is h i g h and v is l o w as c o r r e s p o n d i n g to a stored logic 1. T h e other c o m p l e m e n t a r y state t h e n is designated b y a stored logic 0. Finally, it should b e o b v i o u s that the latch circuit described is of the static variety. It n o w r e m a i n s to devise a m e c h a n i s m b y w h i c h t h e latch can b e triggered to c h a n g e state. T h e latch together w i t h the triggering circuitry forms & flip-flop. This will b e discussed next. A n a l o g bistable circuits utilizing o p a m p s will b e presented in C h a p t e r 13. w
w
w
x
2
z
w
z
-"•: 11.1
LATCHES AND FLIP-FLOPS
11.1.1 The Latch T h e basic m e m o r y element, the latch, is s h o w n in Fig. 11.1 (a). It consists of two cross-coupled logic inverters, G and G . T h e inverters form a positive-feedback loop. T o investigate the operation of the latch w e b r e a k the f e e d b a c k l o o p at the input of o n e of t h e inverters, say G and apply an input signal, v , as s h o w n in F i g . 11.1(b). A s s u m i n g that t h e input i m p e d a n c e of G is large, breaking the feedback l o o p will not c h a n g e the loop voltage transfer charac teristic, w h i c h can b e d e t e r m i n e d from t h e circuit of F i g . 11.1(b) b y plotting v versus v . T h i s is t h e v o l t a g e transfer characteristic of t w o c a s c a d e d inverters and thus takes the shape s h o w n in F i g . 11.1(c). O b s e r v e that the transfer characteristic consists of three segments, with the m i d d l e s e g m e n t c o r r e s p o n d i n g to t h e transition region of the inverters. A l s o s h o w n in Fig. 11.1 (c) is a straight line with unity slope. This straight line represents t h e relationship v = v that is realized b y r e c o n n e c t i n g ' Z to W to close t h e f e e d b a c k loop. 1
2
1 ;
w
:
z
w
w
z
In this section, w e shall study the basic m e m o r y element, the latch, and consider a sampling of its applications. B o t h static and d y n a m i c circuits will b e considered.
w
z
FLIP-FLOPS
1 (
w
x
Y
z
x
0H
z
x
x
0L
0L
z
0H
z
11.1.2 TheSR Flip-Flop T h e simplest t y p e of flip-flop is the set/reset (SR) flip-flop s h o w n in Fig. 11.2(a). It is formed b y c r o s s - c o u p l i n g t w o N O R gates, and thus it incorporates a latch. T h e second input
(a)
(b)
( c )
FIGURE 1 1 . 1 (a) Basic latch, (b) The latch with the feedback loop opened, (c) Determining the operating point(s) of the latch.
(a)
R
5
0
0
0
1
1
0
0
1
1
Not used
Qn 1
(b)
FIGURE 1 1 . 2 (a) The set/reset (SR) flipflop and (b) its truth table.
1016
.
> CHAPTER 11 MEMORY AND ADVANCED DIGITAL CIRCUITS
11.1
of e a c h N O R gate together serve as t h e trigger inputs of the flip-flop. T h e s e t w o inputs are labeled S (for set) and R (for reset). T h e outputs are labeled Q and Q, e m p h a s i z i n g their c o m p l e m e n t a r i t y . T h e flip-flop is c o n s i d e r e d to b e set (i.e., storing a logic 1) w h e n Q is high and Q is low. W h e n the flip-flop is in the other state (Q low, Q h i g h ) , it is considered to be reset (storing a logic 0).
02
In the rest or m e m o r y state (i.e., w h e n w e d o not wish to c h a n g e the state of the flip-flop) both the S and R inputs should b e low. Consider the case w h e n the flip-flop is storing a logic 0 S i n c e Q will b e l o w , b o t h inputs to t h e N O R gate G will b e low. Its output will therefore be high. This h i g h is applied to the input of G causing its o u t p u t Q to b e l o w , satisfying the original a s s u m p t i o n . T o set the flip-flop w e raise S to the logic-1 level w h i l e leaving R at 0. T h e 1 at the S terminal will force the output of G , Q, to 0. T h u s the two inputs to G! will be 0 and its output Q will g o to 1. N o w e v e n if S returns to 0, the flip-flop r e m a i n s in the newly acquired set state. Obviously, if w e r a i s e S to 1 again (with R r e m a i n i n g at 0) n o c h a n g e will occur. T o reset the flip-flop w e n e e d to raise R to 1 while leaving 5 = 0. W e can readily show that this forces the flip-flop into the reset state and that the flip-flop r e m a i n s in this state e v e n after R h a s returned to 0. It should b e o b s e r v e d that the trigger signal m e r e l y starts the regenerative action of the positive-feedback loop of t h e latch.
LATCHES AND FLIP-FLOPS
04 Q
13-1
2
Ö8
I—O«
07
I—oR
b
ß
2
FIGURE 1 1 . 3
Finally, w e inquire into w h a t h a p p e n s if b o t h S and R are simultaneously raised to 1. The t w o N O R gates will c a u s e b o t h Q a n d Q to b e c o m e 0 (note that in this c a s e t h e c o m p l e m e n tary labeling of t h e s e t w o variables is incorrect). H o w e v e r , if R and S return to t h e rest state (R = S = Q) simultaneously, the s t a t e o f t h e flip-flop will b e undefined. In other w o r d s , it will b e i m p o s s i b l e to predict t h e final state of the flip-flop. F o r this reason, this input combina tion is usually disallowed (i.e., not u s e d ) . N o t e , h o w e v e r , that this situation arises only in the idealized case, w h e n both R a n d S return to 0 precisely simultaneously. In actual practice o n e of the t w o will return to 0 first, and the final state will b e d e t e r m i n e d b y the input that r e m a i n s h i g h longest.
CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by .
voltage V-Q d o w n . If VQ g o e s b e l o w t h e t h r e s h o l d of t h e (Q , Q ) inverter, the inverter will 3
4
switch states (or at least b e g i n to switch states), a n d its output v
Q
in v is fed b a c k to t h e input of the (Q Q
u
will rise. T h i s i n c r e a s e
Q ) inverter, c a u s i n g its o u t p u t V-Q to g o d o w n even 2
further; t h e r e g e n e r a t i o n p r o c e s s , characteristic of t h e p o s i t i v e - f e e d b a c k latch, is n o w in progress. T h e p r e c e d i n g description of flip-flop switching is predicated on t w o a s s u m p t i o n s : 1. Transistors Q and Q supply sufficient current to pull the n o d e Q d o w n to a voltage at least slightly b e l o w the threshold of t h e ( Q , Q ) inverter. This is essential for the r e g e n e r a t i v e process to begin. W i t h o u t this initial trigger, t h e flip-flop will fail to switch. In E x a m p l e 1 1 . 1 , w e shall investigate the m i n i m u m W/L ratios that Q and Q m u s t h a v e to m e e t this requirement. 5
6
3
T h e operation of the flip-flop is s u m m a r i z e d b y the truth table in Fig. 11.2(b), w h e r e Q d e n o t e s t h e v a l u e of Q at t i m e t j u s t before the application of the R and S signals, and Q d e n o t e s t h e v a l u e of Q at t i m e t after t h e application of the input signals.
n
n
3
4
s
n+l
6
n+l
2. T h e set signal r e m a i n s h i g h for an interval long e n o u g h to cause r e g e n e r a t i o n to take o v e r the switching process. A n estimate of the m i n i m u m w i d t h required for t h e set p u l s e c a n b e o b t a i n e d as the s u m of the interval during w h i c h KG is r e d u c e d from V to V /2, and t h e interval for t h e voltage v to r e s p o n d and rise to V /2.
R a t h e r than u s i n g t w o N O R g a t e s , o n e c a n also i m p l e m e n t an S R flip-flop b y crosscoupling t w o N A N D gates in w h i c h c a s e t h e set and reset functions are active w h e n low and t h e inputs are c o r r e s p o n d i n g l y called S a n d R.
DD
DD
Q
DD
11.1.3 CMOS Implementation of SR Flip-Flops
Finally, n o t e that the s y m m e t r y of the circuit indicates that all t h e p r e c e d i n g r e m a r k s apply
T h e S R flip-flop of Fig. 11.2 can b e directly i m p l e m e n t e d in C M O S b y simply replacing each of the N O R gates by its C M O S circuit realization. W e e n c o u r a g e the r e a d e r to sketch the resulting circuit. A l t h o u g h t h e C M O S circuit thus obtained w o r k s well, it is s o m e w h a t c o m p l e x . A s an alternative, w e consider a simplified circuit that furthermore i m p l e m e n t s additional logic. Specifically, F i g . 11.3 s h o w s a clocked version of an S R flip-flop. Since the clock inputs form A N D functions with t h e set a n d reset inputs, the flip-flop can b e set or reset only w h e n t h e clock
equally well to t h e reset p r o c e s s .
H 11
Q
g
DD
DD
5
6
n
ox
2
p
DD
E x c e p t for t h e addition of c l o c k i n g , t h e S R flip-flop of F i g . 11.3 o p e r a t e s in e x a c t l y the s a m e w a y as its logic a n t e c e d e n t in F i g ^ l l . 2 : T o illustrate, c o n s i d e r w h a t h a p p e n s w h e n the flip-flop is in the reset state (Q = 0, Q = 1, v = 0, w = V ), and a s s u m e that w e w i s h to set it. T o d o so, w e a r r a n g e for a h i g h (V ) signal to a p p e a r on the S i n p u t w h i l e R is h e l d l o w at 0 V . T h e n , w h e n the clock
I'he C M O S SR flip-flop in Fig. 11.3 is fabricated in a process technology for which ]i C = .5 Li C = 50 liA/V , V = |V \ = 1 V, and V = 5 V. The inverters have (W/L) = 4 / a n / 2 /an nd (W/L) = 10 j U m / 2 / a n . The four N M O S transistors in the set-reset circuit have equal W/L itios. Determine the minimum value required for this ratio to ensure that the flip-flop will switch. 0X
tn
tp
DD
n
m MI
H
iolution Igure 11.4 shows the relevant portion of the circuit for our present purposes. Observe that since ^generation has not yet begun, w e assume that v = 0 and thus Q will be conducting. The circuit is in effect a pseudo-NMOS gate, and our task is to select the W/L ratios for Q and Q so that V of this inverter is lower than V /2 (the threshold of the g , Q inverter whose Q and Q are Q
2
s
0L
DD
3
4
6
N
P
lOl^
1 0 1 8
CHAPTER 11
MEMORY A N D A D V A N C E D
% = VDD °—I
DIGITAL
11.1
CIRCUITS
2<
7
FIGURE 1 1 . 4 The relevant portion of the flip-flop circuit of Fig. 11.3 for determining the minimum W/L ratios of Q and Q needed to ensure that the flip-flop will switch. 5
6
matched). T h e m i n i m u m required W/L for Q and Q can b e found b y equating t h e current supplied by Q and Q to the current supplied by Q at = V /2. T o simplify matters, we assume that the series connection of Q and Q is approximately equivalent to a single transistor whose W/L is half the W/L of each of Q and Q . N o w , since at w = V /2 both this equivalent transistor and Q will be operating in the triode region, w e can write 5
5
6
6
2
s
DD
6
5
6
g
DD
2
\2-i
(5-l)x;
50xix 2
= 20 x ^ ( 5 - l ) x ; 2
X
'2 l2
W
= 4
and
W
Recalling that this is an absolute m i n i m u m value, w e would in practice select a ratio of 5 or 6.
IlliiS
Repeat Example 11.1 to determine the minimum required (W/L)< achieved when inputs S and
= (W/L)
6
so thai switching is
DD
11.2
11.1.4 A Simpler CMOS Implementation of the Clocked SR Flip-Flop A simpler implementation of a clocked SR flip-flop is s h o w n in Fig. 11.5. H e r e , pass-transistor logic is e m p l o y e d to i m p l e m e n t t h e clocked s e t - r e s e t functions. This circuit is very p o p u l a r in the design of static r a n d o m - a c c e s s m e m o r y ( S R A M ) chips, w h e r e it is u s e d as t h e basic m e m o r y cell (Section 11.4.1).
11.1.5 D Flip-Flop Circuits
= 4
EXERCISES
FIGURE 1 1 . 5 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips.
2
which leads to
11.1
L A T C H E S A N DFLIP-FLOPS
We wish to determine the minimum required width of the set pulse. Toward that end: (a) llrsfccqnsider the lime for in the circuit of Fig. 11.4 (o fall from V lo V^/2.- Assume thai the total capacitance between ihe Q node and ground is 5 0 f F. Determine the high-to-low propagation delay t by finding the average current available to discharge the capacitance over the voltage range V to V /2. Remember that Q will b e conducting a current that unfortunately reduces the current available to dis charge C. Assume" (W/L) = (W/L) = 8, and use the technology parameters given in Example 11.1. (b) Determine l for v (Fig. 11.3) using the following formula: w>
A variety of flip-flop types exist a n d c a n b e synthesized using logic gates. C M O S circuit implementations c a n b e obtained b y simply r e p l a c i n g t h e gates with their C M O S circuit realizations. T h i s approach, h o w e v e r , usually results in rather c o m p l e x circuits. I n m a n y cases, simpler circuits c a n b e found by taking a circuit-design viewpoint, rather than a logicdesign o n e . T o illustrate this point, w e shall consider t h e C M O S i m p l e m e n t a t i o n of a very important t y p e of flip-flop, t h e data, o r D , flip-flop. T h e D flip-flop is s h o w n in b l o c k - d i a g r a m form in F i g . 11.6. It h a s t w o inputs, t h e data input D a n d t h e clock input (j>. T h e c o m p l e m e n t a r y outputs a r e labeled Q a n d Q. W h e n t h e clock is l o w , t h e flip-flop is in t h e m e m o r y , or rest, state; signal c h a n g e s on t h e D input line have n o effect o n t h e state of t h e flip-flop. A s t h e clock goes high, t h e flip-flop acquires t h e logic level that existed o n t h e D line j u s t before t h e rising e d g e of t h e clock. S u c h a flip-flop is said to b e e d g e - t r i g g e r e d . S o m e i m p l e m e n t a t i o n s of t h e D flip-flop include direct set a n d reset inputs that override t h e clocked operation j u s t described. A simple i m p l e m e n t a t i o n of t h e D flip-flop is s h o w n in F i g . 11.7. T h e circuit consists of two inverters c o n n e c t e d in a positive-feedback loop, j u s t as in the static latch of Fig. 11.1 (a),
PHL
DD
DD
2
5
PLH
6
Q
D o r
L
=. k
7
C
. : 11
T.
Assume a total node capacitance at Q of 50 fF. (c) What is the minimum width required of the set pulse? Ans. (a) 0.11 ns; (b) 0.17 ns; (c) 0.28 ns
i 4> (clock)
FIGURE 1 1 . 6 A block-diagram representation of the D flip-flop.
1
1 0 1 9
CHAPTER 11
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
11.2
MULTIVIBRATOR CIRCUITS
DO
(a)
(b)
FIGURE 1 1 . 7 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase nonoverlapping clock whose waveforms are shown in (b). e x c e p t that h e r e the loop is closed for only part of t h e t i m e . Specifically, the l o o p is closed w h e n t h e clock is l o w (
1n n
2
F r o m the preceding, w e observe that the circuit in Fig. 11.7 combines the positive-feedback technique of static bistable circuits and the charge-storage technique of d y n a m i c circuits. It is i m p o r t a n t to n o t e that the p r o p e r operation of this circuit, and of m a n y circuits that use clocks, is predicated on the assumption that (j) and (j) will not be simultaneously high at any time. This condition is defined by referring to the t w o clock phases as being nonoverlapping. A n inherent d r a w b a c k of the D flip-flop i m p l e m e n t a t i o n of F i g . 11.7 is that d u r i n g fa the output of t h e flip-flop simply follows the signal o n t h e D input line. T h i s can c a u s e p r o b l e m s in certain logic design situations. T h e p r o b l e m is solved very effectively by using the m a s t e r s l a v e c o n f i g u r a t i o n s h o w n in F i g . 1 1 . 8 ( a ) . B e f o r e d i s c u s s i n g its c i r c u i t o p e r a t i o n , w e n o t e that although t h e switches are s h o w n i m p l e m e n t e d with single N M O S transistors, C M O S transmission gates are e m p l o y e d in m a n y applications. W e are simply using the sin gle M O S transistor as a " s h o r t h a n d n o t a t i o n " for a series switch. T h e m a s t e r - s l a v e circuit consists of a pair of circuits of t h e type s h o w n in F i g . 11.7, o p e r a t e d w i t h alternate clock p h a s e s . H e r e , to e m p h a s i z e that the t w o clock p h a s e s m u s t b e nonoverlapping, w e denote t h e m fa and fa, and clearly s h o w the nonoverlap interval in the w a v e f o r m s of F i g . 11.8(b). O p e r a t i o n of t h e circuit is as follows:
L ^ I
n
Nonoverlap interval
I (b) FIGURE 1 1 . 8 (a) A master-slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates, (b) Waveforms of the two-phase nonoverlapping clock required.
F r o m this description, w e note that at the positive transition of c l o c k fa the output Q adopts the value of D that existed on the D line at t h e e n d of the p r e c e d i n g clock p h a s e , fa. This output value r e m a i n s constant for one clock period. Finally, note that during the n o n overlap interval b o t h latches h a v e their f e e d b a c k l o o p s o p e n and w e are relying o n the n o d e capacitances to maintain m o s t of their charge. It follows that t h e n o n o v e r l a p interval should be k e p t r e a s o n a b l y short (perhaps one-tenth or less of t h e clock period, a n d of t h e order of 1 ns or so in current practice).
1. W h e n fa is high and fa is l o w , the input is c o n n e c t e d to the m a s t e r latch w h o s e feed b a c k l o o p is o p e n e d , w h i l e the slave latch is isolated. T h u s , t h e output Q r e m a i n s at t h e value stored previously in t h e slave latch w h o s e l o o p is n o w closed. T h e node
11.2
MULTIVIBRATOR CIRCUITS
capacitances of the master latch are charged to the appropriate voltages corresponding to the p r e s e n t value of D. 2. W h e n fa goes l o w , t h e m a s t e r latch is isolated from the input data line. T h e n , w h e n 0 goes high, the feedback l o o p of the m a s t e r latch is closed, l o c k i n g in the value of D. Further, its output is c o n n e c t e d to t h e slave latch w h o s e f e e d b a c k l o o p is n o w open. T h e n o d e capacitances in t h e slave are appropriately c h a r g e d so that w h e n fa g o e s h i g h again the slave latch locks in t h e n e w v a l u e of D and p r o v i d e s it at t h e out put, Q = D. 2
As m e n t i o n e d before, the flip-flop has two stable states and is called a bistable multivibrator. There are t w o other types of multivibrator: m o n o s t a b l e and astable. T h e m o n o s t a b l e m u l t i vibrator h a s o n e stable state in w h i c h it can r e m a i n indefinitely. It has another quasi-stable state to w h i c h it can be triggered. T h e monostable multivibrator can remain in the quasi-stable state for a p r e d e t e r m i n e d interval T, after w h i c h it automatically reverts to the stable state. In this w a y t h e m o n o s t a b l e multivibrator generates an output p u l s e of duration T. This p u l s e duration is in n o w a y related to the details of the triggering pulse, as is indicated schematically
i \
1021
CHAPTER 11
MEMORY A N D A D V A N C E D
DIGITAL
In In o -
One-shot"
-oOut
CIRCUITS
11.2
MULTIVIBRATOR
CIRCUITS
"DD
11
À
Out
FIGURE 1 1 . 9 The monostable multivibrator (one-shot) as a functional block, shown to be triggered by a positive pulse. In addition, there are one shots diat are triggered by a negative pulse. in Fig. 11.9. T h e monostable multivibrator can therefore be used as a pulse stretcher or, more appropriately, a pulse standardizer. A monostable multivibrator is also referred to as a one-shot. T h e astable m u l t i v i b r a t o r h a s n o stable states. Rather, it h a s t w o quasi-stable states, a n d it r e m a i n s in each for p r e d e t e r m i n e d intervals T, and T . T h u s after 7\ s e c o n d s in one of t h e quasi-stable states the astable switches to the other quasi-stable state and r e m a i n s there for T seconds, after w h i c h it reverts b a c k to the original state, a n d so on. T h e astable multi vibrator thus oscillates with a p e r i o d T = T + T or a f r e q u e n c y / = 1 / T , and it can b e used to g e n e r a t e periodic pulses such as t h o s e r e q u i r e d for clocking. 2
D\
A
D',
î
c-
r (a)
(b)
FIGURE 1 1 . 1 1 (a) Diodes at each input of a two-input CMOS gate, (b) Equivalent diode circuit when the two inputs of the gate are joined together. Note that the diodes are intended to protect the device gates from potentially destructive overvoltages due to static charge accumulation.
2
y
2
- o Out
In C h a p t e r 13 w e will study astable and m o n o s t a b l e multivibrator circuits that use o p a m p s . In the following, w e shall discuss monostable and astable circuits using logic gates. W e also p r e s e n t an alternative, and very popular, oscillator circuit, the ring oscillator.
••Rn. - o Out
(a)
11.2.1 A CMOS Monostable Circuit F i g u r e 11.10 s h o w s a simple and p o p u l a r circuit for a m o n o s t a b l e multivibrator. It is com p o s e d of t w o two-input C M O S N O R gates, Gj and G , a capacitor of c a p a c i t a n c e C, and a resistor of resistance R. T h e input source v supplies the triggering pulses for the monostable multivibrator. 2
1
C o m m e r c i a l l y available C M O S gates h a v e a special a r r a n g e m e n t of diodes connected at their input terminals, as indicated in F i g . 11.11(a). T h e p u r p o s e of t h e s e diodes is to prevent t h e input v o l t a g e signal from rising a b o v e the supply v o l t a g e V (by m o r e than o n e diode drop) a n d from falling b e l o w g r o u n d v o l t a g e (by m o r e t h a n o n e d i o d e drop). T h e s e clamp ing diodes h a v e an important effect o n t h e operation of t h e m o n o s t a b l e circuit. Specifically, w e shall be interested in the effect of these diodes o n the operation of the inverter-connected gate G . In this case, e a c h pair of c o r r e s p o n d i n g diodes appears in parallel, giving rise to the equivalent circuit in Fig. 11.11(b). W h i l e t h e diodes p r o v i d e a low-resistance p a t h to the p o w e r supply for voltages e x c e e d i n g t h e p o w e r supply limits, t h e input current for interme diate voltages is essentially zero. DD
2
FIGURE 1 1 . 1 2 Output equivalent circuit of CMOS gate when the output is (a) low and (b) high.
(b)
T o simplify matters w e shall u s e t h e a p p r o x i m a t e output equivalent circuits of the gate, illustrated in F i g . 11.12. F i g u r e 11.12(a) indicates that w h e n the gate output is l o w , its out put characteristics can b e represented b y a resistance i ? to g r o u n d , w h i c h is n o r m a l l y a few hundred o h m s . In this state, current can flow from the external circuit into the output termi nal of the gate; the gate is said to b e sinking current. Similarly, t h e equivalent output circuit in Fig. 11.12(b) applies w h e n t h e gate output is h i g h . In this state, current c a n flow from V through the output terminal of the gate into the external circuit; the gate is said to be sourcing current. o n
DD
T o see h o w the m o n o s t a b l e circuit of Fig. 11.10 operates, consider t h e timing d i a g r a m given in F i g . 11.13. H e r e a short triggering p u l s e of duration T is s h o w n in Fig. 11.13(a). In the following w e shall neglect the p r o p a g a t i o n delays t h r o u g h G and G . T h e s e delays, however, set a l o w e r limit on the p u l s e w i d t h T, T > {t + tpj). x
2
Pl
C o n s i d e r first t h e stable state of the m o n o s t a b l e circuit—that is, t h e state of t h e circuit before t h e trigger p u l s e is applied. T h e o u t p u t of Gj is h i g h at V , t h e capacitor is dis charged, a n d t h e input voltage to G is h i g h at V . T h u s the output of G is l o w , at g r o u n d voltage. This l o w voltage is fed b a c k to G ^ since v also is low, the output of G is high, as ini tially a s s u m e d . N e x t consider w h a t h a p p e n s as t h e trigger p u l s e is applied. T h e output voltage of Gj will go low. H o w e v e r , b e c a u s e G will be sinking s o m e current and b e c a u s e of i t s finite output resistance R , its output will not g o all the w a y to 0 V . Rather, t h e output of G! drops b y a value AV w h i c h w e shall shortly evaluate. T h e d r o p AV, is c o u p l e d through C (which acts as a short circuit during t h e transient) to the input of G . T h u s t h e input voltage of G d r o p s (from V ) b y an identical a m o u n t AVV Here, w e n o t e that d u r i n g t h e transient there will b e an instantaneous current that flows from DD
2
DD
2
{
OV 2 0
X
t
oa
h
FIGURE 1 1 . 1 0 A monostable circuit using CMOS NOR gâtes. Signal source v, supplies positive trigger puises.
2
2
DD
1 023
11.2 CHAPTER 11
MEMORY
A N D A D V A N C E D
DIGITAL
MULTIVIBRATOR
CIRCUITS
1 © 2 5
CIRCUITS
v ,o 0
(a)
FIGURE 1 1 . 1 4
Time constant = C(R +
Circuit that applies during the discharge of C (at the end of the monostable pulse interval T).
C(R + R ), as indicated in F i g . 11.13(c). T h e v o l t a g e v will c o n t i n u e to rise until it reaches the value of the threshold voltage V* of inverter G . A t this t i m e G will switch and its out put v 2 will g o to 0 V, w h i c h will in turn c a u s e Gj to switch. T h e output of G, will attempt to rise to V , but, as will b e c o m e o b v i o u s shortly, its instantaneous rise will b e limited to an a m o u n t AV . T h i s rise in v is coupled faithfully t h r o u g h C to the input of G . T h u s t h e input of G will rise b y an equal a m o u n t AV . N o t e h e r e that b e c a u s e of d i o d e D b e t w e e n the input of G and V , t h e voltage v can rise only to V + V , w h e r e V (approximately 0.7 V ) is t h e d r o p across D . T h u s from F i g . 11.13(c) w e see that on
R) on
n
th
2
2
0
DD
2
0l
2
2
2
2
(b)
DD
h
12
DD
m
D1
x
AV
=
2
v
DD
(11.2)
+ v
L
T h u s it is d i o d e D that limits t h e size of t h e i n c r e m e n t AV . B e c a u s e n o w v is higher than V (by V ), current will flow from the output of G through C and then through the parallel combination of R and D . This current discharges C until v drops to V and v rises to V . T h e discharging circuit is depicted in Fig. 11.14, from w h i c h w e note that the existence of the diode causes the discharging to be a nonlinear pro cess. Although the details of the transient at the end of the pulse are not of i m m e n s e interest, it is important to note that the monostable circuit should not b e retriggered until the capacitor has been discharged, since otherwise the output obtained will not b e the standard pulse, which the one-shot is intended to provide. T h e capacitor discharge interval is k n o w n as the recovery time. A n expression c a n b e derived for the pulse interval T b y referring to F i g . 11.13(c) and expressing v (t) as x
2
I2
DD
Dl
:
x
I2
(c)
DD
ox
DD
!2
v, (t) 2
/Tl
= V
-AV e"
DD
x
w h e r e x - C(R + R ). Substituting for t • •• Tand gives, after a little m a n i p u l a t i o n : x
on
(d) FIGURE 1 1 . 1 3
V
DD
Timing diagram for the monostable circuit in Fig.
T = C(R + 11.10.
t h r o u g h R and C and into the output t e r m i n a l of G to ground. W e thus h a v e a voltage x
divider f o r m e d b y R and R w h i c h w e can d e t e r m i n e AV
on
X
(note that t h e instantaneous v o l t a g e across C is zero) from
R )ln on
v (T)
= V , and for AV^ from Eq. (11.1)
12
th
V,DD
R R +
R„ V n
n
EXERCISES
as rsMilsssFor V = V lh
AV
X
=
R
V
D
DD
/ 2 and R
l>u
<& R, find an approximate expression for T.
(ll.D
'R + R
n
R e t u r n i n g to G , w e see that t h e d r o p of v o l t a g e at its input causes its output to g o h i g h 2
(to V ). DD
T h i s signal k e e p s t h e output of G l o w e v e n after the triggering p u l s e h a s disap x
peared. T h e circuit is n o w in the quasi-stable state. W e next consider operation in the quasi-stable state. T h e current through R, C, and R causes C to c h a r g e , and t h e v o l t a g e v rises exponentially t o w a r d V w i t h a t i m e constant
on
I2
DD
D11.4 If TXg,, is k n o w n to be less than 1 k£2, use the approximation in Exercise 11.3 to design a one-shot that produces 10-/is pulses. Specify values for C and R. What is the maximum possible error in T due to neglecting R in the design? Arts. Possible values are C = 1 n F , R = 14.5 k Q ; - 3 % w
11.2
I All delays — H
h I
I |-<— I
MULTIVIBRATOR CIRCUITS
!
_ I
*- Time
(b) (a)
(b)
FIGURE 1 1 . 1 5 (a) A simple astable multivibrator circuit using CMOS gates, (b) Waveforms for the astable circuit in (a). The diodes at the gate input are assumed to be ideal and thus to limit the voltage v to 0 and V . n
FIGURE 1 1 . 1 6 (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency \/6t . P
DD
11.2.3 The Ring Oscillator
11.2.2 An Astable Circuit F i g u r e 11.15(a) s h o w s a popular astable circuit c o m p o s e d of t w o inverter-connected N O R gates, a resistor, and a capacitor. W e shall consider its operation, a s s u m i n g that the N O R gates are of the C M O S family. H o w e v e r , to simplify matters w e shall m a k e s o m e further a p p r o x i m a t i o n s , neglecting the finite output resistance of the C M O S gate and a s s u m i n g that the c l a m p i n g diodes are ideal (thus h a v e zero voltage d r o p w h e n c o n d u c t i n g ) . W i t h these simplifying assumptions, the w a v e f o r m s of Fig. 11.15(b) are obtained. The reader is u r g e d to consider the operation of this circuit in a step-by-step m a n n e r and verify that the w a v e f o r m s s h o w n i n d e e d a p p l y . 1
Another type of oscillator c o m m o n l y used in digital circuits is the ring oscillator. It is formed by connecting an odd n u m b e r of inverters in a loop. A l t h o u g h usually at least five inverters are used, w e illustrate the principle of operation using a ring of three inverters, as s h o w n in Fig. 11.16(a). F i g u r e 11.16(b) shows the w a v e f o r m s obtained at the outputs of the three inverters. T h e s e w a v e f o r m s are idealized in the sense that their edges h a v e zero rise and fall times. N e v e r t h e l e s s , they will serve to explain the circuit operation. O b s e r v e that a rising e d g e at n o d e 1 p r o p a g a t e s t h r o u g h gates 1, 2, and 3 to return inverted after a delay of 3t . T h i s falling e d g e t h e n p r o p a g a t e s , and returns with the original (rising) polarity after another 3t interval. It follows that the circuit oscillates with a p e r i o d of 6t or c o r r e s p o n d i n g l y with frequency l/6t . In general, a ring w i t h N inverters ( w h e r e N m u s t b e odd) will oscillate with p e r i o d of 2Nt and frequency \/2Nt . A s a final r e m a r k , w e note that the ring oscillator provides a relatively simple m e a n s for measuring the inverter p r o p a g a t i o n delay. P
P
P
P
P
11.5
P
Using the waveforms in F i g . i 1.15(b), derive an expression for the period T of the astable multivibrator of Fig. 11.15(a). \ V, DD V
Ans.
/
=
( A' in
11.6
Practical circuits often use a large resistance in series with the input to Gj. This limits the effect of diode conduction and allows % to rise to a voltage greater than V and, as well, to fall below zero. DD
Find the frequency of oscillation of a ring of five inverters if the inverter propagation delay is specified to be 1 ns. Ans. K I D M H z
1027
1028
J
CHAPTER 11
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
11.3
11.3 SEMICONDUCTOR MEMORIES: TYPES AND ARCHITECTURES
S E M I C O N D U C T O R MEMORIES: TYPES A N D ARCHITECTURES
Storage cell array
A computer system, whether a large m a c h i n e or a microcomputer, requires m e m o r y for storing data and p r o g r a m instructions. Furthermore, within a given computer system there usually are various types of m e m o r y utilizing a variety of technologies and having different access times. B r o a d l y speaking, computer m e m o r y can b e divided into two types: m a i n m e m o r y and massstorage m e m o r y . T h e main m e m o r y is usually the m o s t rapidly accessible m e m o r y and the o n e from w h i c h most, often all, instructions in p r o g r a m s are executed. T h e m a i n m e m o r y is usually of the random-access type. A r a n d o m - a c c e s s m e m o r y ( R A M ) is one in which the time required for storing (writing) information and for retrieving (reading) information is independent of the physical location (within the m e m o r y ) in which the information is stored. R a n d o m - a c c e s s m e m o r i e s should b e contrasted w i t h serial or sequential m e m o r i e s , such as disks a n d tapes, from w h i c h d a t a are available only in the s e q u e n c e in w h i c h the data w e r e originally stored. T h u s , in a serial m e m o r y t h e t i m e to access particular information d e p e n d s on t h e m e m o r y location in w h i c h t h e required information is stored, and the avera g e access t i m e is longer than the access t i m e of r a n d o m - a c c e s s m e m o r y . In a computer system, serial m e m o r y is u s e d for m a s s storage. I t e m s not frequently accessed, such as large parts of t h e c o m p u t e r operating system, are usually stored in a moving-surface memory such as m a g n e t i c disk. A n o t h e r important classification,of m e m o r y relates to w h e t h e r it is a r e a d / w r i t e or a r e a d - o n l y m e m o r y . Read/write ( R / W ) m e m o r y p e r m i t s data to b e stored and retrieved at c o m p a r a b l e speeds. C o m p u t e r s y s t e m s require r a n d o m - a c c e s s read/write m e m o r y for data and p r o g r a m storage. R e a d - o n l y m e m o r i e s ( R O M ) permit r e a d i n g at the s a m e h i g h speeds as R / W memories (or perhaps higher) but restrict the writing operation. R O M s can b e used to store a microprocessor operating-system p r o g r a m . T h e y are also e m p l o y e d in operations that require table l o o k u p , such as finding the values of m a t h e m a t i c a l functions. A p o p u l a r application of R O M s is their u s e in video g a m e cartridges. It should b e noted that read-only m e m o r y is usually ofthe r a n d o m - a c c e s s type. Nevertheless, in the digital circuit jargon, the a c r o n y m R A M usually refers to read/write, random-access m e m o r y , w h i l e R O M is used for read-only m e m o r y . T h e regular structure of m e m o r y circuits has m a d e t h e m an ideal application for design of t h e circuits of t h e very-large-scale integrated ( V L S I ) type. Indeed, at any m o m e n t , m e m ory chips represent the state of the art in p a c k i n g density a n d h e n c e integration level. Beginn i n g with t h e introduction of the l K - b i t c h i p in 1970, m e m o r y - c h i p density h a s quadrupled about every 3 years. At the p r e s e n t t i m e , chips c o n t a i n i n g 2 5 6 M b i t s are commercially available, w h i l e multigigabit m e m o r y chips are b e i n g tested in r e s e a r c h and d e v e l o p m e n t laboratories. In this and the next t w o sections, w e shall study s o m e of t h e basic circuits e m p l o y e d in V L S I R A M chips. Read-only m e m o r y circuits are studied in Section 11.6. 2
Bit line
A0
Ai-
— K 2£.
Word line
' Storage cell M
2 -l 0w
N
2 -l Sense amplifiers / drivers
A Am+i M
Column address (Ambits)
—
A
Ù+N-
Column decoder
1"
T
I/O data FIGURE 1 1 . 1 7 A 2 -bit M+N
M
memory chip organized as an array of 2 rows
x 2^columns.
( 1 6 M x 4 ) , in w h i c h c a s e a 24-bit address is required. F o r simplicity w e shall a s s u m e in o u r subsequent discussion that all t h e bits on a m e m o r y chip are individually addressable. T h e b u l k of t h e m e m o r y chip consists of t h e cells in w h i c h the bits are stored. E a c h m e m o r y cell is an electronic circuit capable of storing o n e bit. W e shall study m e m o r y - c e l l circuits in Section 11.4. F o r reasons that will b e c o m e clear shortly, it is desirable to p h y s i cally o r g a n i z e t h e storage cells o n a chip in a square or a nearly square matrix. F i g u r e 11.17 illustrates such an organization. T h e cell m a t r i x has 2 r o w s and 2 c o l u m n s , for a total storage capacity of 2 . F o r e x a m p l e , a l M - b i t square m a t r i x w o u l d h a v e 1024 r o w s and 1024 c o l u m n s (M = N= 10). E a c h cell in the array is c o n n e c t e d to o n e of the 2 r o w lines, k n o w n rather loosely, b u t universally, as w o r d lines, and to o n e of the 2 c o l u m n lines, k n o w n as digit lines or, m o r e c o m m o n l y , bit lines. A particular cell is selected for r e a d i n g or writing by activating its w o r d line a n d its bit line. M
N
M+N
11.3.1 Memory-Chip Organization
M
T h e bits o n a m e m o r y chip are a d d r e s s a b l e either individually or in g r o u p s of 4 to 16. A s an e x a m p l e , a 6 4 M - b i t chip in w h i c h all bits are individually addressable is said to b e organized as 6 4 M w o r d s x 1 bit (or s i m p l y 6 4 M x 1). S u c h a chip n e e d s a 26-bit address ( 2 = 67,108,864 = 6 4 M ) . On the other hand, the 64M-bit chip can b e organized as 16M words x 4 bits 2 6
2
The capacity of a memory chip to hold binary information as binary digits (or bits) is measured in K-bit and M-bit units, where IK bit = 1024 bits and 1M bit = 1024 x 1024 = 1,048,576 bits. Thus a 64M-bit chip contains 67,108,864 bits of memory.
N
M
Activating o n e of the 2 word lines is performed b y the r o w decoder, a combinational logic circuit that selects (raises the voltage of) the particular word line w h o s e M-bit address is applied to the decoder input. T h e address bits are denoted A , A A_ W h e n the Kth word line is activated for, say, a read operation, all 2^06118 in r o w /(Twill provide their contents to their respective bit lines. Thus, if the cell in c o l u m n L (Fig. 11.17) is storing a 1, the voltage 0
u
M
V
1030
CHAPTER 11
11.4
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
R A N D O M - A C C E S S M E M O R Y (RAM) CELLS
-wssäsü i»of bit-line n u m b e r L will b e raised, usually b y a small voltage, say 0.1 V to 0.2 V . T h e readout voltage is small b e c a u s e t h e cell is small, a deliberate design decision, since t h e number of cells is very large. T h e small readout signal is applied to a sense amplifier connected to the bit line. A s Fig. 11.17 indicates, there is a sense amplifier for every bit line. T h e sense amplifier provides a full-swing digital signal (from 0 to V ) DD
at its output. This signal, together with the
output signals from all the other cells in t h e selected r o w , is then delivered to the column d e c o d e r . T h e c o l u m n decoder selects t h e signal of t h e particular c o l u m n w h o s e TV-bit address is applied to the decoder input (the address bits are denoted A ,A , M
M+1
...,A _A M+N
and
causes this signal to appear on t h e chip input/output (I/O) data line. A write operation p r o c e e d s in a similar m a n n e r : T h e data bit t o b e stored (1 or 0) is applied t o t h e I / O line. T h e cell in w h i c h t h e data bit is to b e stored is selected through the c o m b i n a t i o n of its r o w address a n d its c o l u m n a d d r e s s . T h e s e n s e amplifier of t h e selected c o l u m n acts as a d r i v e r t o w r i t e t h e applied signal into t h e selected cell. Circuits for sense amplifiers a n d address d e c o d e r s will b e studied in Section 11.5. Before leaving the topic of m e m o r y organization (or m e m o r y - c h i p architecture), w e wish to m e n t i o n a relatively recent innovation in organization dictated b y the exponential increase in chip density. T o appreciate t h e need for a change, note that as the n u m b e r of cells in the array increases, t h e physical lengths of t h e w o r d lines a n d the bit lines increase. This h a s occurred e v e n though for each n e w generation of m e m o r y chips, t h e transistor size h a s decreased (cur
11.4
RANDOM-ACCESS MEMORY (RAM) CELLS
As m e n t i o n e d in S e c t i o n 11.3> t h e major part of t h e m e m o r y chip is t a k e n u p b y t h e storage cells. It follows that t o b e able to p a c k a large n u m b e r of bits on a c h i p , it is i m p e r a t i v e that the cell size b e r e d u c e d t o t h e smallest p o s s i b l e . T h e p o w e r dissipation p e r cell s h o u l d b e m i n i m i z e d also. T h u s , m a n y of t h e flip-flop circuits studied in Section-11.1 are t o o c o m p l e x to b e suitable for i m p l e m e n t i n g t h e storage cells in a R A M chip. There are basically t w o types of M O S R A M : static and dynamic. Static R A M s (called S R A M s for short) utilize static latches as the storage cells. D y n a m i c R A M s (called D R A M s ) , on the other hand, store t h e binary data on capacitors, resulting in further reduction in cell area, but at the expense of m o r e complex read and write circuitry. In particular, while static R A M s can hold their stored data indefinitely, provided the p o w e r supply remains on, dynamic R A M s require periodic
refreshing
to regenerate t h e data stored o n capacitors. This is b e c a u s e t h e stor
age capacitors will d i s c h a r g e , t h o u g h slowly, as a result of t h e l e a k a g e currents inevitably present. B y virtue of their smaller cell size, d y n a m i c m e m o r y chips a r e u s u a l l y four t i m e s as dense as their c o n t e m p o r a r y static chips. B o t h static a n d d y n a m i c R A M s are volatile;
that is,
they r e q u i r e t h e c o n t i n u o u s p r e s e n c e of a p o w e r supply. B y contrast, m o s t R O M s a r e of t h e nonvolatile t y p e , as w e shall s e e in Section 11.6. In t h e following sections, w e shall study basic S R A M a n d D R A M storage cells.
rently, C M O S process technologies with 0 . 1 - 0 . 3 urn feature size are utilized). T h e net increase in word-line and bit-line lengths increases their total resistance and capacitance, and thus slows d o w n their transient response. That is, as t h e lines lengthen, t h e exponential rise of the voltage
11.4.1 Static Memory Cell
of the w o r d line b e c o m e s slower, and it takes longer for t h e cells t o b e activated. This problem
Figure 11.18 s h o w s a typical static m e m o r y cell i n C M O S t e c h n o l o g y . T h e circuit, w h i c h
has b e e n solved b y partitioning t h e m e m o r y chip into a n u m b e r of blocks. E a c h of the blocks
w e e n c o u n t e r e d in S e c t i o n 1 1 . 1 , is a flip-flop c o m p r i s i n g t w o c r o s s - c o u p l e d inverters a n d
has an organization identical to that in Fig. 11.17. T h e r o w and c o l u m n addresses are broadcast
two a c c e s s t r a n s i s t o r s , Q a n d Q . T h e access transistors are t u r n e d o n w h e n t h e w o r d line is
to all blocks, b u t t h e data selected c o m e from only one of t h e blocks. B l o c k selection is
selected a n d its voltage raised to V ,
achieved b y using an appropriate n u m b e r of t h e address bits as a block address. S u c h an archi
line a n d c o l u m n ( b i t or B) line. N o t e that b o t h B a n d B lines are utilized. T h e access tran
tecture can b e thought of as three-dimensional: r o w s , columns, and blocks.
5
6
DD
a n d they c o n n e c t t h e flip-flop t o t h e c o l u m n (bit or B)
sistors act as t r a n s m i s s i o n gates allowing bidirectional current flow b e t w e e n t h e flip-flop and t h e B a n d B lines.
11.3.2 Memory-Chip Timing
The Read Operation
T h e m e m o r y a c c e s s t i m e is t h e t i m e b e t w e e n t h e initiation of a r e a d operation a n d the
In this case, Q will b e high at V , and Q will b e l o w at 0 V . Before the read operation begins,
a p p e a r a n c e of t h e output data. T h e m e m o r y c y c l e t i m e is t h e m i n i m u m t i m e allowed
the B and B lines are préchargea
Consider first a read operation, a n d a s s u m e that t h e cell is storing a 1. DD
to an intermediate voltage, b e t w e e n the l o w and high values,
b e t w e e n t w o c o n s e c u t i v e m e m o r y o p e r a t i o n s . T o b e o n t h e c o n s e r v a t i v e side, a m e m o r y operation is u s u a l l y t a k e n t o i n c l u d e b o t h r e a d a n d w r i t e (in t h e s a m e location). M O S m e m ories h a v e access a n d cycle t i m e s in t h e r a n g e of a few t o few h u n d r e d n a n o s e c o n d s .
11.7
A 4M-bil memory chip is partitioned into 32 blocks, with each block having f 024 rows and 128 columns. Give the number of bits required for the row address, column address, and block address.
11.8
The word lines in a particular MOS memory chip arc fabricated using polysilicon (see Appendix A). The resistance of each word line is estimated to be 5 k Q , and the total capacitance between the line and ground is 2 pF. Find the time for the voltage on the word line to reach V /2 assuming that the line is driven by a voltage \V„„ provided by a low-impedance inverter. (Note: The line is actually a distributed network that we are approximating b \ a lumped circuit consisting of a single resistor and a single capacitor.) np
Ans.
'v'
1
ii-
FIGURE 1 1 . 1 8 A CMOS SRAM memory cell.
1031
CHAPTER 11
MEMORY A N D ADVANCED
B line
V\V
DIGITAL
CIRCUITS
1
= VDD
^
11.4
RANDOM-ACCESS
MEMORY
(RAM) CELLS
Refer to Fig. 11.19 and recall that initially v = V , t> = 0, and v = v = V . W e see immediately that the circuit in Fig. 11.19(b) will not be conducting, and thus v will remain con stant at V . Turning our attention then to the circuit in Fig. 11.19(a), w e observe that since vwill change by only 0.2 V (i.e., from 5 V to 4.8 V) during the readout process, transistor Q will be operating in saturation, and thus C will be discharged with a constant current 7 . For transis tor Qi to conduct, its drain voltage V-Q will have to rise. W e hope, however; that this rise will not exceed the threshold of inverter (Q , 0 ), which is V /2, since the p and n transistors in each inverter are matched. There will be a brief interval during which I will charge the small parasitic capacitance between node Q and ground to a voltage V-Q sufficient to operate Q in the triode mode at a current I equal to I . The current I can then be expressed as Q
BD
DD
g
B
s
DD
B
5 line
DD
1
05
•Cs
5
g
3
06
5
4
DD
5
x
x
(a)
5
x
\v D-Vn)v -\vl
(b)
D
FIGURE 1 1 . 1 9 Relevant parts of the SRAM cell circuit during a read operation when the cell is storing a logic 1. Note that initially v = V and VQ=0. Also note that the B and B lines are usually precharged to a voltage of about V /2. However, in Example 11.2, it is assumed for simplicity that the précharge voltage is V . Q
Q
where we have assumed that v will remain constant at V . Since the source of Q is at ground, V = 1 V and, Q
DD
DD
x
tX
DD
DD
/ , = 50 x 1
usually V /2. ( T h e circuit for p r e c h a r g i n g will b e s h o w n in Section 11.5 in conjunction with t h e sense amplifier.) W h e n t h e w o r d line is selected a n d Q a n d Q are turned on, w e see that current will flow from V t h r o u g h Q a n d Q a n d onto line B, charging t h e capaci tance of line B, C . O n the other side of t h e circuit, current will flow from t h e p r e c h a r g e d B line t h r o u g h Q and Q to ground, thus discharging C . It follows that t h e relevant parts of the circuit during a read operation are those s h o w n in F i g . 11.19. F r o m this description, w e note that during a read " 1 " operation, the voltage across C will rise a n d that across C will fall. T h u s , a differential voltage V d e v e l o p s b e t w e e n line B a n d line B. Usually, only 0.2 V or so is r e q u i r e d for the sense amplifier to detect the pres e n c e of a 1 in t h e cell. O b s e r v e that the cell m u s t b e designed so that the c h a n g e s in v and VQ are small e n o u g h to prevent the flip-flop from c h a n g i n g state during readout. T h e read operation in a n S R A M is nondestructive. Typically, e a c h of t h e inverters is designed so that Q a n d Q are m a t c h e d , thus placing t h e inverter threshold at V /2. T h e access transistors are usually m a d e t w o to three times w i d e r t h a n Q of t h e inverters.
For Q we can write
DD
s
DD
A
(11.3)
2
s
6
6
(V -V -V ) 2
h = \VnC {j-) ox
Q
DD
t5
B
5
x
p
where the threshold voltage V
t5
V
B
B
BS
can be determined from = 1 + 0 . 5 ( ^ + 0.6-706)
t5
(11.4)
Since w e do not yet know v^, we need to solve by iteration. For a first iteration, w e assume that V = 1 V , thus I will b e t5
5
Q
N
P
DD
N
7
5
= 1x50x^(5-^-1)2
'
(11.5)
Now equating I from Eq. (11.3) to 7 from Eq. (11.5) and solving for VQ results in w = 1.86 V. As a second iteration, w e use this value of in Eq. (11.4) to determine V . The result is t5 = 1-4 V. This value is then used in the expression for 7 and the process repeated, with the result that w = 1.6 V. This is close enough to the original value, and no further iteration seems warranted. The current I can now be determined, I = 0.5 m A . Observe that v^ is indeed less than V /2, and thus the flip-flop will not switch state (a relief!). In fact, V for this inverter is 2.125 V; thus the assumption that v stays at V is justified, although v will change somewhat, a point w e shall not pursue any further in this approximate analysis. W e can n o w determine the interval for a 0.2-V decrement to appear on the B line from x
5
g
t5
v
5
g
5
s
DD
The purpose of this example is to analyze the dynamic operation of the C M O S S R A M cell of Fig. 11.18. Assume that the cell is fabricated in a process technology for which p C = 50 pA/V , p C = 20 pA/V , V = - V = 1 V , 2 fa = 0.6 V , y = 0.5 V ^ , and V = 5 V. Let the cell transistors have ( W / L ) = 4 / 2 , (W/L) = 1 0 / 2 , and let the access transistors have (W/L) = 1 0 / 2 . Assuming that the cell is storing a 1 and that the capacitance of each bit line is 1 pF, determine the time required to develop an output voltage of 0.2 V. T o simplify the analysis, assume that the B and B lines are precharged to V . n
2
ox
2
p
ox
ta0
IL
Q
DD
Q
DD
C AV
n
5
At Thus,
DD
. 2 = 0.4 n s At. = 1 x 1 0 - 1 2 x 0 — 0.5 x 10~ A
Solution We note at the outset that the dynamic analysis of this circuit is complex, and w e must therefore make a number of simplifying assumptions. Of course, a precise analysis can always be obtained asing simulation. However, much insight can be gained from even an approximate paper-andpencil analysis.
n
A
3
We should point out that At is only one component of the delay encountered in the read opera tion. Another significant component is due to the finite rise time of the voltage on the word line. Indeed, even the calculation of At is optimistic, since the word line will have only reached a voltage lower than V when the process of discharging C takes place. DD
g
„i
1033
CHAPTER 11
MEMORY A N D A D V A N C E D
DIGITAL
CIRCUITS
RANDOM-ACCESS
11.4
MEMORY
Another even more approximate (but faster) solution can b e obtained by observing that in the
W e shall briefly e x p l a i n t h e o p e r a t i o n of t h e circuits in F i g . 11.20, leaving t h e analysis
circuit of Fig. 11.19(a), Q and Q have equal gate voltages (V ) and are connected in series. W e
for t h e r e a d e r to p e r f o r m in E x e r c i s e 11.9 a n d P r o b l e m s 11.23 a n d 11.24. C o n s i d e r first t h e
X
5
DD
1035
( R A M ) CELLS
circuit in F i g . 11.20(a), a n d n o t e that Q will b e operating in saturation. Initially, its source
may consider that they are approximately equivalent to a single transistor with a W/L ratio,
5
voltage will b e 0, a n d thus its V, will b e e q u a l to V . A l s o initially, Q will b e off b e c a u s e its T0
1
+.
(W/L),
10 7
1
1
(W/L)„ =
? 4
1
(W/L)
5
+
2 10
X
drain v o l t a g e is zero. T h e current I will initially flow into C g , c h a r g i n g it u p , a n d thus 5
X
X
X
from I , r e d u c i n g t h e current available for c h a r g i n g C g . Simultaneously,
as Vq rises, V
5
Q
2
will
5
Fig. 11.20(b) is that v will b e falling from V 1 x 50 x ^ ( 5 - l )
=
T5
increase o w i n g t o t h e b o d y effect, and 7 will r e d u c e . A n o t h e r effect c a u s e d b y t h e circuit in
T h e equivalent transistor will operate in saturation, thus its current I will be I
v-
will rise a n d Q will c o n d u c t . Q will b e i n t h e triode r e g i o n a n d its current I will subtract
= 0.57 m A
DD
t o w a r d V /2. DD
This will c a u s e a c o r r e s p o n d -
ing decrease in t h e current I . D e s p i t e all t h e s e complications, o n e c a n easily calculate a n X
a p p r o x i m a t e a v e r a g e v a l u e for t h e capacitor c h a r g i n g current 7 _ o v e r t h e i n t e r v a l b e g i n 3
C
This is only 14% greater than the value found earlier. T h e voltage V-Q can be found b y multiply-
ning with {v
Q
ing I by the approximate value of r
of Q in the triode region,
DS
6
l/[50xl0- x^x(5-l)]
' DS
= V , DD
= 0 ) a n d e n d i n g w i t h (v
Q
= V /2,
Vq = V /2).
DD
W e c a n then u s e
DD
this current v a l u e t o d e t e r m i n e t h e t i m e for t h e v o l t a g e across C g t o increase b y
X
V /2. DD
T h e circuit in F i g . 11.20(b) operates in m u c h t h e s a m e fashion e x c e p t that neither of t h e
= 2.5 k Q
t w o transistors is susceptible to t h e b o d y effect. T h u s , this circuit will p r o v i d e C
Q
with a
larger d i s c h a r g e current than t h e current p r o v i d e d b y t h e circuit in F i g . 11.20(a) t o c h a r g e
Thus,
Cq. T h e result will b e that C
Q
Vq = 0 . 5 7 x 2 . 5 = 1.4 V
will r e a c h V /2
will d i s c h a r g e faster than C g will c h a r g e . I n other w o r d s , v
Q
before Vq d o e s . It follows that an estimate of this c o m p o n e n t of t h e w r i t e
DD
Again, this is reasonably close to the value found earlier.
delay t i m e c a n b e o b t a i n e d b y c o n s i d e r i n g o n l y t h e circuit in F i g . 11.20(b).
The Write Operation
flop. This c a n b e a p p r o x i m a t e d b y t h e delay t i m e of o n e inverter.
A n o t h e r c o m p o n e n t of write delay is that t a k e n u p b y t h e s w i t c h i n g action of t h e flipnally storing 3L1(v
N e x t w e consider t h e write operation. A s s u m e that t h e cell is origi-
= V
Q
DD
and
= 0 ) a n d that w e w i s h to write a 0. T o d o this, t h e B line is
l o w e r e d to 0 V and t h e B line is raised t o V , and of course the cell is selected b y raising the DD
w o r d line t o V . DD
Figure 11.20 shows t h e relevant parts of the circuit during t h e interval in
w h i c h n o d e Q is being pulled u p toward the threshold voltage V /2
(Fig. 11.20a) and node
DD
Q is b e i n g pulled d o w n toward V /2
(Fig. 11.20b). Capacitors C and C
DD
Q
are t h e parasitic
g
capacitances at nodes Q and Q, respectively. A n approximate analysis c a n b e performed on either circuit t o determine t h e time required for toggling to take place. N o t e that t h e regenera-
K
11.9 Consider the circuit in Fig. 11.20(b). and assume that the device dimensions and process technology ^parameters are as specified in Example 11.2. We wish to determine the interval Ar required for C to discharge, and its voltage to fall from V to V /2. y
DD
tive feedback that causes t h e flip-flop t o switch will begin w h e n either V /2. DD
v
Q
or Vq reaches
DD
(a) At the beginning of interval At, find the values of 7 , 1 , and I . 4
W h e n this happens, the positive feedback takes over, and t h e circuits in F i g . 11.20 no
4
(c) Find an estimate of the average value of I (d) If C
V,DD
Q
4
V; 3 0-
n
I L Ö 4
V ]
V, Oto DP 2
l
n
0 , 0 ^
¿1
O
O
v = 0 B
V
DD
6
1.8 m A ; ( d ) A ? = 69.4 ps
= 2 mA; (b) 7 = 0.11 mA, 7 = 1.72 mA, I 4
C
6
C
= 1.61 mA; (c)
smaller t h a n t h e c o r r e s p o n d i n g c o m p o n e n t in t h e r e a d operation. This is b e c a u s e in t h e write operation, only t h e small c a p a c i t a n c e C n e e d s to b e c h a r g e d (or d i s c h a r g e d ) , w h e r e a s in t h e Q
to
read operation, w e h a v e t o c h a r g e (or d i s c h a r g e ) the m u c h larger c a p a c i t a n c e s of t h e B o r B
01-
lines. I n t h e w r i t e operation, t h e B a n d B line c a p a c i t a n c e s are c h a r g e d (and d i s c h a r g e d ) relatively q u i c k l y b y t h e driver circuitry. T h e e n d result is that t h e delay t i m e in t h e write oper-
Vnn tO
ation is d o m i n a t e d b y t h e w o r d - l i n e delay. (b)
(a)
F I G U R E 1 1 . 2 0 Relevant parts of the SRAM circuit during a write operation. Initially, the SRAM has a stored 1 and a 0 is being written. These equivalent circuits apply before switching takes place, (a) The circuit is pulling node Q up toward V /2. (b) The circuit is pulling node Q down toward V /2. DD
DD
l
C o
\
= U v
•
F r o m t h e results of E x e r c i s e 11.9, w e n o t e that this c o m p o n e n t of w r i t e delay is m u c h
-OV
Vq
CQ
= 50 fF, estimate At.
Ans.- (a) 7 = 0 , 7 = 2 mA, I
x
6
during interval AT.
CQ
i*
CG
(b) A t the e n d o f interval At, find the values of / , 7 , and I .
longer apply.
Vw = V
6
Implicit in this statement is the assumption that both v and V-Q will reach V /2 simultaneously. As will be seen shortly, this is not the case. Nevertheless, it is a reasonable assumption to make for the purpose of obtaining an approximate estimate of the write delay time. Q
DD
1036
?VJ'
CHAPTER 11
MEMORY
A N D A D V A N C E D DIGITAL
CIRCUITS
11.4
RANDOM-ACCESS
MEMORY
(RAM) CELLS
in the v o l t a g e on t h e bit line resulting from c o n n e c t i n g a cell capacitor C to it, let the initial voltage on t h e cell capacitor b e V (V = V - V w h e n a 1 is stored, b u t y = 0 V w h e n a 0 is stored). U s i n g c h a r g e conservation, w e can write s
cs
Word line
T
1
CsVcs I)
+
cs
DD
C ^f =
t
(C
B
B
+
c s
C )[^f + AVJ
.
s
from w h i c h w e can obtain for AV
(
Bit line Cell
(11.6)
I
and since C
B
>
C, s
AV = FIGURE 1 1 . 2 1
£»(v .,-^s)
(11.7)
c
The one-transistor dynamic RAM cell. N o w , if t h e cell is storing a 1, V
= V
cs
- V, and
DD
t
(11.8) C
CB
X
FIGURE 1 1 . 2 2 When the voltage of the selected word line is raised, the transistor conducts, thus connecting the storage capacitor C to the bit-line capacitance C . S
whereas if the cell is storing a 0, V
cs
— 0, and
B
A V ( 0 ) = -g(^)
11.4.2 Dynamic Memory Cell A l t h o u g h a variety of D R A M storage cells h a v e b e e n p r o p o s e d o v e r the years, a particular cell, s h o w n in F i g . 1 1 . 2 1 , h a s b e c o m e t h e i n d u s t r y standard. T h e cell c o n s i s t s of a single n - c h a n n e l M O S F E T , k n o w n as the access transistor, and a storage capacitor C . T h e cell is appropriately k n o w n as the o n e - t r a n s i s t o r c e l l . T h e gate of the transistor is connected to_ the w o r d line, and its source (drain) is c o n n e c t e d to t h e bit line. O b s e r v e that only one bit line is u s e d in D R A M s , w h e r e a s in S R A M s both the bit and bit lines are utilized. T h e D R A M cell stores its bit of information as charge o n the cell capacitor C . W h e n the cell is storing a 1, the capacitor is c h a r g e d to (V - V,); w h e n a 0 is stored, the capacitor is discharged to a z e r o v o l t a g e . B e c a u s e of l e a k a g e effects, the capacitor c h a r g e will leak off, and h e n c e the cell m u s t b e refreshed periodically. D u r i n g refresh, the cell c o n t e n t is read and t h e data bit is rewritten, thus restoring t h e capacitor voltage to its p r o p e r value. The refresh operation m u s t b e performed e v e r y 5 m s to 10 m s . L e t us n o w consider the D R A M operation in m o r e detail. A s in t h e static R A M , the row d e c o d e r selects a particular r o w b y raising t h e v o l t a g e of its w o r d line. This causes all the access transistors in the selected r o w to b e c o m e c o n d u c t i v e , thereby c o n n e c t i n g t h e storage capacitors of all t h e cells in t h e selected r o w to their r e s p e c t i v e bit lines. T h u s t h e cell capac itor C is c o n n e c t e d in parallel with the bit-line c a p a c i t a n c e C , as indicated in F i g . 11.22. H e r e , it should b e noted that C is typically 3 0 f F t o 5 0 f F , w h e r e a s C is 3 0 to 5 0 times larger. N o w , if the operation is a read, the bit line is p r e c h a r g e d to V /2. T o find the change s
4
s
DD
5
s
B
s
B
(11.9)
S i n c e u s u a l l y C is m u c h g r e a t e r t h a n C , t h e s e r e a d o u t v o l t a g e s are v e r y small. F o r e x a m ple, for C = 3 0 C , V = 5 V, a n d V = 1.5 V , AV(0) will b e a b o u t - 8 3 m V , a n d AVT1) will b e 3 3 m V . T h i s is a b e s t - c a s e s c e n a r i o , for t h e 1 l e v e l in t h e cell m i g h t very w e l l b e b e l o w (V - V,). F u r t h e r m o r e , in m o d e r n m e m o r y c h i p s , V is 3.3 V or e v e n l o w e r . In any c a s e , w e see that a stored 1 in t h e cell r e s u l t s in a s m a l l p o s i t i v e i n c r e m e n t in t h e bitline v o l t a g e , w h e r e a s a s t o r e d zero results in a small n e g a t i v e i n c r e m e n t . O b s e r v e also that the r e a d o u t p r o c e s s is destructive, since t h e r e s u l t i n g v o l t a g e across C will n o l o n g e r b e (V ~V )or0. B
B
s
s
DD
t
DD
DD
s
DD
t
T h e c h a n g e of v o l t a g e o n t h e bit line is detected and amplified b y t h e c o l u m n sense amplifier. T h e amplified signal is then i m p r e s s e d on the storage capacitor, thus restoring its signal to t h e p r o p e r level (V - V, or 0). In this w a y , all the cells in the selected r o w are refreshed. S i m u l t a n e o u s l y , the signal at t h e output of the sense amplifier of t h e selected col u m n is fed to the data-output line of the chip t h r o u g h the action of the c o l u m n decoder. DD
T h e write operation p r o c e e d s similarly to t h e r e a d operation, except that the d a t a bit to b e written, w h i c h is i m p r e s s e d on the data input line, is applied b y the c o l u m n d e c o d e r to t h e selected bit line. T h u s , if the data bit to b e written is a 1, the TMine voltage is raised to V (i.e., C is c h a r g e d to V ). W h e n the access transistor of t h e particular cell is turned on, its capacitor C will b e c h a r g e d to V - V ; thus a 1 is written in the cell. S i m u l t a n e o u s l y , all the other cells in the selected r o w are simply refreshed. DD
B
DD
s
DD
t
DD
5
The name was originally used to distinguish this cell from earlier ones utilizing three transistors. The reason that the " 1 " level is less than V by the magnitude of the threshold V is as follows: Con sider a write-1 operation. The word line is at V and the bit line is at V and the transistor is conducting, charging C . The transistor will cease conduction when the voltage on C reaches (V - V,), where V, is higher than V® because of the body effect. We have analyzed this situation at length in Section 10.5 in connection with pass-transistor logic. DD
T
DD
S
DD
S
DD
A l t h o u g h the r e a d and write operations result in automatic refreshing of .all the cells in the selected r o w , provision m u s t b e m a d e for the periodic refreshing of the entire m e m o r y every 5 to 10 m s , as specified for the particular c h i p . T h e refresh operation is carried out in a burst mode, o n e r o w at a time. D u r i n g refresh, the c h i p will n o t b e available for read or write operations. T h i s is n o t a serious matter, h o w e v e r , since the interval required to refresh t h e entire c h i p is typically less than 2% of the t i m e b e t w e e n refresh cycles. In other w o r d s , t h e m e m o r y chip is available for n o r m a l operation m o r e than 9 8 % of t h e t i m e .
!
1
037
1038
ic,.'
CHAPTER 11
MEMORY
A N D A D V A N C E D
DIGITAL
SENSE AMPLIFIERS A N D ADDRESS
11.5
CIRCUITS
EXERCISES
DECODERS
Word line Selected cell
11.10 I n a particular dynamic memory chip. C - 30 fF, C = 1 p F , V = 5 V , Vj (including the body effect) = 1.5 V, find the output readout voltage for a stored 1 and a stored 0. Recall thru in a read operation, the bit lines are precharged to V M. s
B
Cell
DD
nn
Ans. 30 m V : - 7 5 m V
A
11.11 A 64M-bit D R A M chip fabricated in a OA-pm C M O S technology requires 2 pm per cell. If the stor age array i s square,.estimate its dimensions. Further, if the peripheral circuitry (e.g., sense amplifiers, decoders) add about 3 0 % to the chip area, estimate the dimensions of the resulting chip.
VIM
2
o.
Ans. 11.6 m m X 11.6 m m ; 13.2 m m x 13.2 m m
J, - .- ,| ir o
<
v
BO
11.5
i
O
SENSE AMPLIFIERS AND ADDRESS DECODERS "I
I
V
B
Differential sense amplifier
r
H a v i n g studied t h e circuits c o m m o n l y u s e d t o i m p l e m e n t t h e storage cells in S R A M s and D R A M s , w e n o w consider s o m e of the other important circuit b l o c k s in a m e m o r y chip. T h e design of these circuits, c o m m o n l y referred to as t h e m e m o r y peripheral circuits, presents exciting challenges and opportunities t o integrated-circuit designers: I m p r o v i n g t h e perfor m a n c e of peripheral circuits c a n result in d e n s e r a n d faster m e m o r y chips that dissipate less power.
11.5.1 The Sense Amplifier N e x t to t h e storage cells, t h e sense amplifier is t h e m o s t critical c o m p o n e n t in a m e m o r y chip. Sense amplifiers are essential to the proper operation of D R A M s , and t h e n u s e in S R A M s results in s p e e d a n d area i m p r o v e m e n t s . A variety of sense-amplifier designs a r e in u s e , s o m e of w h i c h closely r e s e m b l e the active-load M O S differential amplifier studied in C h a p t e r 7. H e r e , w e describe a differential sense amplifier that employs positive feedback. B e c a u s e t h e circuit is differential, it c a n be e m p l o y e d directly in S R A M s w h e r e t h e S R A M cell utilizes both t h e B a n d B lines. O n the other hand, t h e one-transistor D R A M circuit w e studied i n Section 11.4.2 is a single-ended circuit, utilizing o n e bit line only. T h e D R A M circuit, h o w e v e r , c a n b e m a d e t o resemble a differential signal source t h r o u g h t h e u s e of the " d u m m y cell" technique, w h i c h w e shall dis cuss shortly. Therefore, w e shall a s s u m e that the m e m o r y cell w h o s e output is to b e amplified develops a difference output voltage b e t w e e n t h e B a n d B lines. This signal, w h i c h c a n range b e t w e e n 30 m V and 5 0 0 m V d e p e n d i n g on t h e m e m o r y type a n d cell design, will b e applied to t h e input terminals of the sense amplifier. T h e sense amplifier in turn responds b y provid ing a full-swing (0 to V ) signal at its output terminals. T h e particular amplifier circuit w e shall discuss h e r e h a s a rather unusual property: Its output and input terminals are the same! DD
A Sense Amplifier w i t h Positive F e e d b a c k
Figure 11.23 shows the sense
amplifier
together with s o m e of t h e other c o l u m n circuitry of a R A M chip. N o t e that t h e sense ampli fier is n o t h i n g b u t t h e familiar latch f o r m e d b y c r o s s - c o u p l i n g t w o C M O S inverters: O n e inverter is i m p l e m e n t e d b y transistors Q a n d Q , a n d t h e other b y transistors Q a n d Q Transistors Q a n d Q act as switches that c o n n e c t t h e sense amplifier to g r o u n d a n d V only w h e n data-sensing action is required. O t h e r w i s e ,
5
2
3
6
4
DD
Equalization and précharge circuitry
•-<: ii
I B line
5 line
FIGURE 1 1 . 2 3 A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the "dummy cell" arrangement shown in Fig. 11.25.
that terminals x a n d y a r e both t h e input a n d t h e output terminals of t h e amplifier. A s indi cated, these I / O terminals a r e c o n n e c t e d to t h e B a n d B lines. T h e amplifier is required to detect a small signal appearing b e t w e e n B a n d B, a n d to amplify it to p r o v i d e a full-swing signal at B a n d B. F o r instance, if during a read operation, the cell h a d a stored 1, then a small positive v o l t a g e will d e v e l o p b e t w e e n B and B, with v h i g h e r than v . T h e amplifier will then c a u s e v to rise t o V a n d v to fall to 0 V . This 1 output is t h e n directed t o t h e chip I/O p i n by t h e c o l u m n d e c o d e r (not s h o w n ) and at t h e s a m e t i m e is u s e d to rewrite a 1 in t h e D R A M cell, thus p e r f o r m i n g t h e restore operation that is required b e c a u s e t h e D R A M readout p r o c e s s is destructive. B
B
DD
s
s
s
Figure 11.23 also s h o w s t h e p r é c h a r g e a n d equalization circuit. Operation of this circuit is straightforward: W h e n (j) g o e s high prior to a r e a d operation, all three transistors conduct. p
1 0 3 9
1 0 4 0
!
CHAPTER 11
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
While g
SENSE AMPLIFIERS A N D ADDRESS DECODERS
transistor Q h e l p s speed u p this pro
T h e w a v e f o r m s of t h e signal on t h e B line will b e c o m p l e m e n t a r y t o t h o s e s h o w n in
cess b y equalizing t h e initial voltages o n t h e t w o lines. This equalization is critical to the
F i g . 1 1 . 2 4 for t h e B line. In t h e following, w e quantify t h e p r o c e s s of e x p o n e n t i a l
p r o p e r operation of the sense amplifier. A n y v o l t a g e difference p r e s e n t b e t w e e n B and B
g r o w t h of v a n d v .
8
a n d Q p r é c h a r g e t h e B a n d B lines t o V /2,
11.5
9
DD
7
B
B
prior to c o m m e n c e m e n t of t h e r e a d o p e r a t i o n c a n result in e r r o n e o u s interpretation by the
Look a t t h e O p e r a t i o n of t h e
s e n s e amplifier of its i n p u t signal. In F i g . 11.23, w e s h o w only o n e of t h e cells i n this partic
A Closer
ular c o l u m n , n a m e l y , t h e cell w h o s e w o r d line is activated. T h e cell c a n b e either an S R A M
sion for t h e output signal of t h e sense amplifier s h o w n in F i g . 11.23 is a rather c o m p l e x t a s k
or a D R A M cell. A l l other cells i n this c o l u m n will n o t b e c o n n e c t e d t o t h e B a n d B lines
requiring t h e u s e of large-signal (and t h u s nonlinear) m o d e l s of t h e inverter voltage transfer
( b e c a u s e their w o r d lines will r e m a i n l o w ) .
characteristic, as well as taking t h e positive f e e d b a c k into account. W e will n o t d o this h e r e ;
Let us n o w consider t h e s e q u e n c e of events d u r i n g a read operation:
D e v e l o p i n g a precise expres
Sense Amplifier
rather, w e shall c o n s i d e r t h e operation in a s e m i q u a n t i t a t i v e w a y .
1. T h e p r é c h a r g e a n d e q u a l i z a t i o n circuit is activated b y raising t h e control signal fa. T h i s will c a u s e the B a n d B lines t o b e at e q u a l v o l t a g e s , e q u a l t o V /2.
T h e clock
DD
Recall that at t h e t i m e t h e sense amplifier is activated, each of its t w o inverters is operat ing in t h e transition r e g i o n at V /2. mn
fa then goes l o w , a n d t h e B a n d B lines a r e left t o float for a brief interval.
a n d g , the transconductances of Q and Q , respectively, evaluated at a n mp
input bias of V /2.
N
P
Specifically, a small-signal v superimposed on V /2
DD
2. T h e w o r d line goes u p , c o n n e c t i n g t h e cell to t h e B and B lines. A v o l t a g e t h e n devel
T h u s , for small-signal operation, each inverter c a n b e
DD
modeled u s i n g g
{
mn
o p s b e t w e e n B a n d B, w i t h v h i g h e r t h a n v if t h e a c c e s s e d cell is storing a 1, or v B
B
B
at the input of o n e
DD
of t h e inverters gives rise to an inverter output current signal of (g
+ g )v;
= G v . This out
mp
m
t
put current is delivered t o o n e of t h e capacitors, C or C . T h e voltage thus developed across B
B
l o w e r t h a n v if t h e cell is storing a 0. T o k e e p t h e cell design simple, a n d t o facilitate
the capacitor is then fed b a c k to t h e other inverter a n d is multiplied by its G , w h i c h gives rise
operation at higher speeds, t h e r e a d o u t signal, w h i c h the cell is required t o provide
to an output current feeding t h e other capacitor, a n d so on, in a regenerative process. T h e p o s
b e t w e e n B and B , is k e p t small (typically, 3 0 - 5 0 0 m V ) .
itive feedback in this loop will m e a n that t h e signal around t h e loop, a n d thus v and v , will
B
m
B
3. O n c e an a d e q u a t e difference v o l t a g e signal h a s b e e n d e v e l o p e d b e t w e e n B and B b y t h e storage cell, t h e s e n s e amplifier is turned o n b y c o n n e c t i n g it t o g r o u n d and V
rise or decay
exponentially
(see F i g . 11.24) with a t i m e constant of (C /G ) B
m
B
[or
(C /G ), B
m
since w e h a v e b e e n a s s u m i n g C = C ]. T h u s , for e x a m p l e , in a r e a d - 1 operation w e obtain B
B
t h r o u g h Q a n d Q , activated b y raising t h e sense-control signal fa. B e c a u s e ini
DD
5
6
tially t h e i n p u t terminals of t h e inverters a r e at V /2, DD
t h e inverters will b e operating
V B
= Xm
{GyCs)t
+ AV(l)e
v
(11.10)
DD
in their transition r e g i o n w h e r e t h e gain is h i g h (Section 10.2). It follows that initially t h e latch will b e operating at its u n s t a b l e e q u i l i b r i u m point. T h u s , d e p e n d i n g on the
w h e r e a s in a r e a d - 0 operation,
signal b e t w e e n t h e input t e r m i n a l s , t h e latch will quickly m o v e t o o n e of its t w o sta v
b l e e q u i l i b r i u m p o i n t s (refer t o t h e description of t h e latch operation in Section 11.1).
B
= ?f
- A V ( 0 ) ,
(
W
(11.11)
This is achieved b y the regenerative action, inherent in positive feedback. F i g u r e 11.24 clearly illustrates this p o i n t b y s h o w i n g t h e w a v e f o r m s of t h e signal o n t h e bit line
B e c a u s e these expressions h a v e b e e n derived a s s u m i n g small-signal operation, they describe
for both a r e a d - 1 a n d a r e a d - 0 operation. O b s e r v e that o n c e activated, t h e sense
the e x p o n e n t i a l g r o w t h (decay) of v r e a s o n a b l y accurately only for v a l u e s c l o s e to
amplifier c a u s e s t h e small initial difference, ÀVT1) o r AV(0), p r o v i d e d b y t h e cell, to
N e v e r t h e l e s s , they c a n b e u s e d to obtain a r e a s o n a b l e e s t i m a t e of t h e t i m e r e q u i r e d t o
g r o w exponentially to either V
develop a particular signal level on t h e bit line.
DD
(for a read-1 operation) or 0 (for a r e a d - 0 operation).
B
B A
V
V(l) =
•
V
V /2. DD
..
Consider the sense-amplifier circuit of Fig. 11.23 during the reading of a 1. Assume that the stor
DD
age cell provides a voltage increment on the B line of AV(1) = 0.1 V. If the N M O S devices in the Read 1
amplifiers have (W/L)
n
= 12 pm/4 pm and the P M O S devices have (W/L)
= (30 pm/4 pro), and
assuming that the other parameters of the process technology are as specified in Example 11.2,
V /2 DD
find the time required for v to reach 4.5 V . Assume C = 1 p F . B
ReadO V(0) = 0
B
Solution >
t Word line activated
First, w e determine the transconductances g
mn
Sense amplifier activated
and g
mp
C
Smn = Vn ox{j^J (V - V,) GS
FIGURE 1 1 . 2 4 Waveforms of v before and after the activation of the sense amplifier. In a read-1 opera tion, the sense amplifier causes the initial small increment AV(1) to grow exponentially to V . la a read-0 operation, the negative AV*(0) grows to 0. Complementary signal waveforms develop on the B line. B
DD
= 50 x
^(2.5-1)
= 0.225 m A / V
'
."I
1 0 4 1
CHAPTER 11
1 042
MEMORY A N D ADVANCED
DIGITAL
CIRCUITS
C
= »P OX(J;)
SENSE AMPLIFIERS A N D ADDRESS DECODERS
11.5
)
Basically, e a c h bit line is split into t w o identical h a l v e s . E a c h half-line is c o n n e c t e d to
(V -\V,\) GS
half the cells in the c o l u m n and to an additional cell, k n o w n as a dummy age c a p a c i t o r C
= 20 x ¿2(2.5 - 1) = 0.225 m A W
cell, h a v i n g a stor-
= C . W h e n a w o r d line o n the left side is selected for r e a d i n g , the d u m m y
D
s
cell on t h e right side (controlled b y 0 ) is also selected, a n d v i c e versa; that is, w h e n a w o r d n
Thus, the inverter G,„ is
line on t h e right side is selected, the d u m m y cell on the left (controlled b y
G
= g
m
selected. In effect, then, the d u m m y cell serves as the other half of a differential D R A M cell.
+ 8mp = 0.45 m A / V
mn
W h e n t h e left-half bit line is in operation, t h e right-half bit line acts as its c o m p l e m e n t (or B and the time constant r f o r the exponential growth of v will be
line) a n d v i c e versa.
B
C
1 x 10
m
0.45 x 10
G
O p e r a t i o n of t h e circuit in F i g . 11.25 is as follows: T h e t w o h a l v e s of the line are p r e -
= 2.22 ns
c h a r g e d to V /2
J
a n d their voltages are equalized. A t the s a m e t i m e , t h e capacitors of the
DD
t w o d u m m y cells are p r e c h a r g e d to V /2.
T h e n a w o r d line is selected, and the d u m m y
DD
N o w , the time, At, for v to reach 4.5 V can b e determined from B
cell on the o t h e r side is e n a b l e d (with
4.5 = 2.5 + 0. l e
Aî/2.22
D
DD
T h u s the half-line c o n n e c t e d
to t h e selected cell will d e v e l o p a v o l t a g e i n c r e m e n t (around V /2) DD
of AV(1) or AV(0)
d e p e n d i n g o n w h e t h e r a 1 or a 0 is stored in t h e cell. M e a n w h i l e , t h e other half of t h e l i n e
resulting in
will h a v e its v o l t a g e h e l d e q u a l to that of C
At = 6.65 ns
(i.e., V /2).
D
T h e result is a differential signal
DD
of AV(1) or AV(0) that t h e s e n s e amplifier detects and amplifies w h e n it is enabled. A s u s u a l , b y the e n d of the r e g e n e r a t i v e p r o c e s s , t h e amplifier will c a u s e t h e v o l t a g e o n o n e half of the O b t a i n i n g Differential O p e r a t i o n in D y n a m i c R A M s
The sense amplifier described
line to b e c o m e V
a n d that on t h e other half to b e c o m e 0.
DD
earlier responds to difference signals appearing b e t w e e n the bit lines. T h u s , it is capable of rejecting interference signals that are c o m m o n to both lines, such as those caused b y capacitive coupling from the word lines. For this cpmmon-mode
rejection
to b e effective, great care has to
b e taken to match both sides of the amplifier, taking into account the circuits that feed each side. This is an important consideration in any attempt to m a k e the inherently single-ended output of the D R A M cell appear differential. W e shall n o w discuss a n ingenious s c h e m e for accomplishing this task. Although the technique h a s b e e n around for m a n y years (see the first edition of this book, published in 1982), it is still in u s e today. T h e method is illustrated in Fig. 11.25.
11.12 II is required to reduce the time At of the sense-amplifier circuit in Example 11.3 to 4 ns by increasing g,„ of the transistors (while retaining the matched design of each inverter). What must the (W/L) ratios of the n- and /;-cliannei devices become? , • Ans.
(W/L)
= 5; (W/L)
N
=
P
12.5
11.13 If in the sense amplifier of Example 11.3, the signal available from the cell is only half as large (i.e., o n l y 5 0 m V ) , what will A? b e c o m e ?
and
Ans. 8.19 ns, an increase of 2 3 % Left dummy cell
Right dummy cell
2 inline
11.5.2 The Row-Address Decoder A s d e s c r i b e d in S e c t i o n 11.3, the r o w - a d d r e s s d e c o d e r is r e q u i r e d to select o n e of the
M
2
w o r d lines in r e s p o n s e to an M - b i t address input. A s an e x a m p l e , consider the case M = 3 and d e n o t e t h e t h r e e address bits A , A 0
C o n v e n t i o n a l l y , w o r d line W
U
a n d A , and the eight w o r d lines 2
will b e h i g h w h e n A
0
0
W
0
, W ] , W
.
7
= 0, A , = 0, a n d A = 0, thus w e c a n 2
express W as a B o o l e a n function of A , A , , a n d A , 0
0
W
0
2
= A AiA 0
2
= A
0
+
A +A L
2
T h u s the selection of W c a n b e a c c o m p l i s h e d b y a three-input N O R gate w h o s e three i n p u t s 0
are c o n n e c t e d to A , A , , a n d A and w h o s e output is c o n n e c t e d to w o r d line 0. W o r d line W 0
2
3
will b e h i g h w h e n A = 1, A , = 1, and A = 0, thus 0
Word lines
Equalization and précharge
2
Word lines
W
3
= A AjA 0
2
= A + Ai+A 0
2
T h u s the selection of W c a n b e realized by a three-input N O R gate w h o s e three inputs are 3
FIGURE 1 1 . 2 5 An arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left.
c o n n e c t e d to AQ, A,,
a n d A , a n d w h o s e o u t p u t is c o n n e c t e d to w o r d line 3. W e can thus see 2
that this a d d r e s s d e c o d e r c a n b e realized b y eight three-input N O R gates. E a c h N O R g a t e is
1
CHAPTER 11
11.5
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
fed with the appropriate c o m b i n a t i o n of a d d r e s s bits and their c o m p l e m e n t s , corresponding
SENSE AMPLIFIERS A N D ADDRESS DECODERS
and their c o m p l e m e n t s are applied. O b s e r v e that the N M O S transistors are placed so that the word lines not selected will be discharged. F o r any input combination, only one w o r d line will
to the w o r d line to w h i c h its output is c o n n e c t e d . A s i m p l e a p p r o a c h to realizing t h e s e N O R functions is p r o v i d e d b y t h e m a t r i x structure
not be discharged, and thus its voltage remains high at V .
For instance, r o w 0 will be high
D0
s h o w n in Fig. 11.26. T h e circuit s h o w n is a d y n a m i c o n e (Section 10.6). A t t a c h e d to each
only when A = 0, A
r o w line is a ^ - c h a n n e l d e v i c e that is activated, prior to the d e c o d i n g p r o c e s s , u s i n g the pré-
transistors connected to r o w 0 being cut off. Similarly, r o w 3 has transistors connected to
0
x
= 0, and A = 0; this is the only combination that will result in all three 2
c h a r g e control signal (p . D u r i n g p r é c h a r g e (
Âo,Âu
V .
outputs h a v e stabilized, the output lines are connected to the w o r d lines of the array, usually via
P
DD
P
It is a s s u m e d that at this t i m e the a d d r e s s i n p u t bits h a v e n o t yet b e e n applied and all
and A , and thus it will b e high w h e n A = 1, A = 1, A = 0, and so on. After the decoder 2
0
x
2
t h e i n p u t s are l o w ; h e n c e there is n o n e e d for t h e circuit to include t h e evaluation transistor
clock-controlled transmission gates. This decoder is k n o w n as a N O R decoder. O b s e r v e that
utilized in d y n a m i c logic gates. T h e n , t h e d e c o d i n g operation b e g i n s w h e n the address bits
because of the précharge operation, the decoder circuit does not dissipate static power.
.
. J 11.14 H o w m a n y transistors are needed for a N u R row decoder with an M-bit address'/
i
WF
<
<
<< < < < < < i
<
Ans. M2
M
Row 0
U
NMOS + 2
M
P M O S = 2 (M
+ 1)
11.5.3 The Column-Address Decoder F r o m the description in Section 11.3, the function of the c o l u m n - a d d r e s s d e c o d e r is to c o n -
^pO-oJj
N
• Row 1
nect o n e of t h e 2
bit lines to the data I/O line of the chip. A s such, it is a m u l t i p l e x e r a n d
can b e i m p l e m e n t e d u s i n g pass-transistor logic (Section 10.5) as s h o w n in Fig. 11.27. H e r e , each bit line is c o n n e c t e d to the data I / O line t h r o u g h a n N M O S transistor. T h e gates of t h e N
pass transistors are controlled b y 2
lines, o n e of w h i c h is selected b y a N O R d e c o d e r simi-
lar to that u s e d for d e c o d i n g t h e r o w address. A n alternative i m p l e m e n t a t i o n of the c o l u m n d e c o d e r that u s e s a smaller n u m b e r of tran• Row 2
sistors (but at the e x p e n s e of slower s p e e d of operation) is s h o w n in F i g . 11.28. T h i s circuit, k n o w n as a tree decoder,
has a simple structure of pass transistors. Unfortunately, since a
«
relatively large n u m b e r of transistors c a n exist in t h e signal path, the resistance of t h e bit lines i n c r e a s e s , a n d the s p e e d d e c r e a s e s c o r r e s p o n d i n g l y . 0pC-o|| Bit lines • Row 3
<£pO-0||
• Row 7
AM
o—
AM+I
o—•
iV-bit column address
\< )R decoder
<
Row address FIGURE 1 1 . 2 6 A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address.
0
1 — Pass-transistor multiplexer
v
2< -l L^M+«-I
° —
ô I/O data FIGURE 1 1 . 2 7 A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer.
1046
CHAPTER 11
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
11.6
Bit lines B
0
B
x
B
2
B
3
1 0 4 7
(ROM)
11.6.1 A M O S ROM
A
B
READ-ONLY MEMORY
B
4
B
5
B
6
7
F i g u r e 11.29 s h o w s a simplified 32-bit (or 8-word x 4-bit) M O S R O M . A s indicated, the m e m o r y consists of a n array of n - c h a n n e l M O S F E T s w h o s e gates are c o n n e c t e d to t h e w o r d
A c—1 0
A o—j
A o-j
A c—1
0
0
0
A o—1
A c—j
A o-|
A cH
0
lines, w h o s e sources are g r o u n d e d , and w h o s e drains are c o n n e c t e d to the bit lines. E a c h bit
0
0
0
line is c o n n e c t e d to the p o w e r supply via a P M O S load transistor, in t h e m a n n e r of p s e u d o N M O S logic (Section 10.4). A n N M O S transistor exists in a particular cell if t h e cell is stor ing a 0; a cell storing a 1 h a s n o M O S F E T . T h i s R O M c a n b e t h o u g h t of as 8 w o r d s of 4 bits each. T h e r o w d e c o d e r selects o n e of t h e 8 w o r d s b y raising the v o l t a g e of t h e c o r r e s p o n d i n g A,oH
A,oH
w o r d line. T h e cell transistors c o n n e c t e d to this w o r d line will t h e n c o n d u c t , thus pulling t h e voltage of t h e bit lines (to w h i c h transistors in the selected r o w are c o n n e c t e d ) d o w n from V
DD
to a v o l t a g e c l o s e to g r o u n d voltage (the logic-0 level). T h e bit lines that are c o n n e c t e d
to cells (of t h e selected w o r d ) w i t h o u t transistors (i.e., the cells that are storing I s ) will A o-j
A o—J
r e m a i n at t h e p o w e r - s u p p l y v o l t a g e (logic 1) b e c a u s e of t h e action of t h e p u l l - u p P M O S l o a d
2
2
devices. In this w a y , the bits of the a d d r e s s e d w o r d c a n b e read. A d i s a d v a n t a g e of t h e R O M circuit in F i g . 11.29 is that it d i s s i p a t e s static p o w e r . S p e cifically, w h e n a w o r d is selected, the t r a n s i s t o r s in this p a r t i c u l a r r o w will c o n d u c t static c u r r e n t t h a t is s u p p l i e d b y t h e P M O S l o a d t r a n s i s t o r s . Static p o w e r d i s s i p a t i o n c a n b e e l i m i n a t e d b y a s i m p l e c h a n g e . R a t h e r t h a n g r o u n d i n g t h e g a t e t e r m i n a l s of t h e P M O S
Ô
t r a n s i s t o r s , w e c a n c o n n e c t t h e s e t r a n s i s t o r s to a p r é c h a r g e line 0 that is n o r m a l l y h i g h ,
I/O data FIGURE 1 1 . 2 8 A tree column decoder. Note that the colored path shows the transistors that are conducting when A = 1, A , = 0, and A = 1, the address that results in connecting B to the data line. 0
2
5
V
l u s t b e f o r e a r e a d i n g o p e r a t i o n , (j) is l o w e r e d a n d t h e bit lines are p r é c h a r g e a t o
DD
t h r o u g h t h e P M O S t r a n s i s t o r s . T h e p r é c h a r g e s i g n a l cb t h e n g o e s h i g h , a n d t h e w o r d line is selected. T h e b i t lines that h a v e t r a n s i s t o r s in t h e s e l e c t e d w o r d a r e t h e n d i s c h a r g e d , t h u s i n d i c a t i n g s t o r e d z e r o s , w h e r e a s t h o s e lines for w h i c h n o t r a n s i s t o r is p r e s e n t r e m a i n at V , DD
indicating stored ones.
11.15 How many transistors are needed for a tree decoder when there are 2 bit lines? s
Ans. 2*:'' • 11
11.6
READ-ONLY MEMORY (ROM)
11.16 T h e purpose of this exercise is to estimate the various delay times involved in the operation of a ROM. Consider the R O M in Fig. 11.29 with the gates of the P M O S devices disconnected from ground and connected to a précharge control signal
tt
A s m e n t i o n e d in Section 11.3, r e a d - o n l y m e m o r y ( R O M ) is m e m o r y that contains fixed data patterns. It is used in a variety of digital-system applications. Currently, a very p o p u l a r appli cation is the u s e of R O M in m i c r o p r o c e s s o r s y s t e m s to store the instructions of the s y s t e m ' s b a s i c operating p r o g r a m . R O M is particularly suited for s u c h an application b e c a u s e it is nonvolatile; that is, it retains its contents w h e n the p o w e r supply is s w i t c h e d off. A R O M c a n b e v i e w e d as a c o m b i n a t i o n a l l o g i c circuit for w h i c h the input is t h e collec tion of address bits of t h e R O M and t h e o u t p u t is the set of data bits retrieved from the a d d r e s s e d location. This v i e w p o i n t leads to t h e application of R O M s in c o d e c o n v e r s i o n — that is, in c h a n g i n g the c o d e of t h e signal f r o m o n e s y s t e m (say, binary) to another. C o d e c o n v e r s i o n is e m p l o y e d , for instance, in s e c u r e c o m m u n i c a t i o n s y s t e m s , w h e r e the process is k n o w n as scrambling.
It consists of feeding the c o d e of t h e data to b e transmitted to a
R O M that p r o v i d e s c o r r e s p o n d i n g bits in a ( s u p p o s e d l y ) secret c o d e . T h e r e v e r s e process, w h i c h also u s e s a R O M , is applied at t h e r e c e i v i n g end. In this section w e will study v a r i o u s t y p e s of r e a d - o n l y m e m o r y . T h e s e i n c l u d e fixed R O M , w h i c h w e refer to simply as R O M , p r o g r a m m a b l e R O M ( P R O M ) , and e r a s a b l e pro grammable R O M (EPROM).
m
2
p
x
(a) During the précharge interval, ô is lowered to 0 V. Estimate the time required to charge a bit line from 0 V to 5 V. Use as an average charging current the current supplied by a PMOS transistor at a bitline voltage halfway through the 0-V to 5-V excursion (i.e., 2.5 V). The bit-line capacitance is 2 pF. Note that all N M O S transistors are cut off at this time. (b) After completion of the précharge interval and the return of 0 to V , the row decoder raises voltage of the selected word line. Because of the finite resistance and capacitance of the word line, voltage rises exponentially toward V . If the resistance of each of the polysilicon word lines is 3 and the capacitance between the word line and ground is 3 pF, what is the (10% to 90%) rise time of word-line voltage? What is the voltage reached at the end of one time constant? DD
DD
the the kQ the
(c) W e account for the exponential rise of the word-line voltage by approximating die word-line voltage by a step equal to the voltage reached in one time constant. Find the interval At required for an N M O S transistor to discharge the bit line and lower its voltage by 0.5 V. (It is assumed that the sense amplifier needs a 0.5-V change at its input to detect a low bit value.) Ans. (a) 6.1 ns; (b) 19.8 ns, 3.16 V; (c) 2.9 ns
/4*ii\ 11.6
DD
f-
1
1
r<
ih-'
%
w
w,
MEMORY
11.6.2 Mask-Programmable ROMs
v
l
READ-ONLY
2
1-1
The data stored in t h e R O M s discussed thus far is d e t e r m i n e d at the t i m e of fabrication, according to t h e u s e r ' s specifications. H o w e v e r , to avoid h a v i n g to c u s t o m - d e s i g n e a c h R O M from scratch (which w o u l d b e e x t r e m e l y costly), R O M s are m a n u f a c t u r e d using a process k n o w n as m a s k p r o g r a m m i n g . A s explained in A p p e n d i x A , integrated circuits are fabricated o n a wafer of silicon using a s e q u e n c e of p r o c e s s i n g steps that include p h o t o masking, etching, a n d diffusion. In this w a y , a pattern of j u n c t i o n s and interconnections is created on t h e surface of t h e wafer. O n e of t h e final steps in the fabrication process consists of coating t h e surface of t h e wafer w i t h a layer of a l u m i n u m and then selectively (using a mask) etching a w a y portions of the a l u m i n u m , leaving a l u m i n u m only w h e r e i n t e r c o n n e c tions are desired. T h i s last step can b e u s e d to p r o g r a m (i.e., to store a desired pattern in) a R O M . F o r instance, if t h e R O M is m a d e of M O S transistors as in Fig. 11.29, M O S F E T s c a n be included at all bit locations, but only the gates of those transistors w h e r e Os are to b e stored are connected to the w o r d lines; the gates of transistors where I s are to b e stored are not connected. T h i s pattern is determined b y the m a s k , w h i c h is p r o d u c e d according to the u s e r ' s specifications. T h e e c o n o m i c a d v a n t a g e s of the m a s k p r o g r a m m i n g process should b e o b v i o u s : All R O M s are fabricated similarly; customization occurs only during o n e of t h e final steps in fabrication.
11.6.3 Programmable ROMs (PROMs and EPROMs) «.
1-1
' U
w
it—'
5
w
L
•I—
%
w
P R O M s are R O M s that can b e p r o g r a m m e d b y the user, but only o n c e . A typical arrange ment e m p l o y e d in B J T P R O M s involves u s i n g polysilicon fuses to connect the emitter of each B I T to the c o r r e s p o n d i n g digit line. D e p e n d i n g on the desired content of a R O M cell, the fuse can b e either left intact or b l o w n out u s i n g a large current. T h e p r o g r a m m i n g p r o cess is o b v i o u s l y irreversible. A n erasable p r o g r a m m a b l e R O M , or E P R O M , is a R O M that can b e erased and r e p r o g r a m m e d as m a n y times as the user w i s h e s . It is therefore the m o s t versatile type of read only m e m o r y . It should b e noted, h o w e v e r , that t h e process of erasure and r e p r o g r a m m i n g is t i m e - c o n s u m i n g and is intended to be p e r f o r m e d only infrequently. State-of-the-art E P R O M s use variants of t h e m e m o r y cell w h o s e cross section is s h o w n in Fig. 11.30(a). T h e cell is basically an e n h a n c e m e n t - t y p e n - c h a n n e l M O S F E T with t w o
,i—
_
,|—
6
7
,1—'
if-'
0
06 5,
0
o
(a)
(b)
FIGURE 1 1 . 3 0 (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.
(ROM)
1 0 4 9
CHAPTER 11
MEMORY
A N D A D V A N C E D
DIGITAL
11.6
CIRCUITS
READ-ONLY
MEMORY
+25 V
fa A Programmed (0)
Not programmed (1)
I
<* 1
I
vs G
H FIGURE 1 1 . 3 1 programming.
Illustrating the shift in the i -v D
GS
characteristic of a floating-gate transistor as a result of
6
other part of the circuit; rather, it is left floating a n d is appropriately called a floating gate. T h e other gate, called a select gate, functions i n t h e s a m e m a n n e r as t h e gate of a regular enhancement MOSFET. T h e M O S transistor of Fig. 11.30(a) is k n o w n as a floating-gate transistor a n d is given the circuit s y m b o l s h o w n in F i g . 11.30(b). In this s y m b o l the b r o k e n line denotes the float ing g a t e . T h e m e m o r y cell is k n o w n as the s t a c k e d - g a t e cell. L e t u s n o w e x a m i n e t h e o p e r a t i o n of t h e f l o a t i n g - g a t e transistor. B e f o r e t h e cell is p r o g r a m m e d ( w e will shortly e x p l a i n w h a t this m e a n s ) , n o c h a r g e exists o n t h e floating gate a n d t h e d e v i c e o p e r a t e s as a r e g u l a r ra-channel e n h a n c e m e n t M O S F E T . It thus e x h i b i t s the i -v c h a r a c t e r i s t i c s h o w n as c u r v e (a) i n F i g . 1 1 . 3 1 . N o t e that in this c a s e t h e t h r e s h o l d v o l t a g e (V,) is r a t h e r l o w . T h i s state of t h e t r a n s i s t o r is k n o w n as t h e n o t - p r o g r a m m e d s t a t e . It is o n e of t w o states in w h i c h t h e f l o a t i n g - g a t e transistor c a n exist. L e t u s arbi trarily t a k e t h e n o t - p r o g r a m m e d state to r e p r e s e n t a s t o r e d 1. T h a t is, a floating-gate transistor w h o s e i - GS c h a r a c t e r i s t i c is that s h o w n a s c u r v e ( a ) in F i g . 11.31 w i l l b e said to b e GS
D
U
storing a 1. T o p r o g r a m the floating-gate transistor, a large v o l t a g e ( 1 6 - 2 0 V ) is applied b e t w e e n its drain a n d source. Simultaneously, a large v o l t a g e (about 2 5 V ) is applied to its select gate. F i g u r e 11.32 s h o w s the floating-gate M O S F E T d u r i n g p r o g r a m m i n g . I n the a b s e n c e of any charge o n t h e floating gate the d e v i c e b e h a v e s as a regular w-channel e n h a n c e m e n t M O S F E T : A n n - t y p e inversion layer (channel) is created at t h e wafer surface as a result of the large positive v o l t a g e applied to t h e select gate. B e c a u s e of t h e large positive voltage at the drain, the c h a n n e l h a s a tapered s h a p e . T h e drain-to-source v o l t a g e accelerates electrons t h r o u g h t h e channel. A s these elec trons r e a c h t h e drain e n d of the channel, they acquire large kinetic e n e r g y a n d are referred to as hot electrons. T h e large positive v o l t a g e o n the select gate (greater t h a n t h e drain voltage) establishes an electric field in the insulating oxide. This electric field attracts the h o t electrons
6
"
~ ~
:
FIGURE 1 1 . 3 2 The floating-gate transistor during programming.
Sense voltage
gates m a d e of polysilicon m a t e r i a l . O n e of t h e gates is n o t electrically c o n n e c t e d t o any
D
p Substrate
See Appendix A for a description of silicon-gate technology.
and accelerates t h e m (through t h e oxide) t o w a r d t h e floating gate. In this w a y the floating gate is charged, a n d the c h a r g e that a c c u m u l a t e s o n it b e c o m e s trapped. Fortunately, the process of charging the floating gate is self-limiting. T h e negative charge that accumulates on the floating gate reduces the strength of the electric field in the oxide to the point that it eventually b e c o m e s incapable of accelerating any m o r e of the hot electrons. L e t us n o w inquire about the effect of t h e floating g a t e ' s negative c h a r g e on the o p e r a tion of t h e transistor. T h e n e g a t i v e c h a r g e t r a p p e d o n t h e floating gate will c a u s e electrons to be repelled from the surface of the substrate. This implies that to form a channel, the posi tive v o l t a g e that h a s to b e applied to the select gate will h a v e to b e greater t h a n that required w h e n t h e floating gate is not charged. In other w o r d s , t h e threshold voltage V, of the p r o g r a m m e d transistor will b e higher than that of the n o t - p r o g r a m m e d device. In fact, p r o g r a m m i n g causes t h e i -v characteristic to shift to the c u r v e labeled (b) i n F i g . 11.31. I n this state, k n o w n as t h e programmed state, the cell is said to b e storing a 0. D
GS
O n c e p r o g r a m m e d , t h e floating-gate d e v i c e retains its shifted i-v characteristic (curve b) even w h e n the p o w e r supply is turned off. In fact, extrapolated e x p e r i m e n t a l results indicate that the device c a n r e m a i n in the p r o g r a m m e d state for as long as 100 y e a r s ! R e a d i n g the content of t h e stacked-gate cell is easy: A v o l t a g e V s o m e w h e r e b e t w e e n the low a n d b i g h threshold values (see F i g . 11.31) is applied to t h e selected gate. W h i l e a p r o g r a m m e d d e v i c e ( o n e that is storing a 0) will n o t conduct, a n o t - p r o g r a m m e d device (one that is storing a 1) will c o n d u c t heavily. GS
T o return the floating-gate M O S F E T to its n o t - p r o g r a m m e d state, the c h a r g e stored o n the floating gate h a s to b e returned to t h e substrate. This erasure p r o c e s s c a n b e a c c o m plished b y illuminating t h e cell with ultraviolet light of the correct w a v e l e n g t h (2537 A ) for a specified duration. T h e ultraviolet light imparts sufficient p h o t o n energy to the trapped electrons to allow t h e m to o v e r c o m e the inherent e n e r g y barrier, and thus b e transported through t h e o x i d e , b a c k to the substrate. T o allow this erasure process, t h e E P R O M p a c k a g e contains a q u a r t z w i n d o w . Finally, it should b e n o t e d that the device is extremely durable, and can b e erased a n d p r o g r a m m e d m a n y t i m e s . A m o r e versatile p r o g r a m m a b l e R O M is the electrically erasable P R O M (or E E P R O M ) . A s t h e n a m e i m p l i e s , a n E E P R O M c a n b e e r a s e d a n d r e p r o g r a m m e d electrically w i t h o u t the n e e d for u l t r a v i o l e t i l l u m i n a t i o n . E E P R O M s utilize a variant of t h e floating-gate M O S F E T . A n i m p o r t a n t class of E E P R O M s using a floating gate variant a n d i m p l e m e n t i n g b l o c k e r a s u r e a r e r e f e r r e d to as F l a s h m e m o r i e s .
(ROM)
f.
1 0 5 1
1 0 5 2
.
CHAPTER 1 1
MEMORY A N D A D V A N C E D
DIGITAL
11.7
CIRCUITS
EMITTER-COUPLED
L O G I C (ECL)
1 0 5 3
swing is IR . A n u m b e r of additional r e m a r k s c a n b e m a d e c o n c e r n i n g this circuit: C
11.7
EMITTER-COUPLED LOGIC (ECL) 7
E m i t t e r - c o u p l e d logic (ECL) is the fastest logic circuit f a m i l y . H i g h speed is a c h i e v e d by operating all transistors out of saturation, thus a v o i d i n g storage-time delays, and b y keeping t h e logic signal swings relatively small (about 0.8 V or less), thus r e d u c i n g the t i m e required to c h a r g e and discharge t h e various l o a d a n d parasitic capacitances. Saturation in E C L is avoided b y using the B J T differential pair as a current s w i t c h . T h e B J T differential pair w a s studied in C h a p t e r 7, and w e u r g e t h e r e a d e r to r e v i e w t h e introduction given in Section 7.3 before p r o c e e d i n g with the study of E C L . 8
11.7.1 The Basic Principle
R
x
2
l
T
R
it
C
1
2
I
2. T h e current d r a w n from t h e p o w e r supply r e m a i n s constant d u r i n g switching. T h u s , u n l i k e C M O S (and T T L ) , n o supply current spikes occur in E C L , eliminating an i m p o r t a n t source of noise in digital circuits. This is a definite a d v a n t a g e , especially since E C L is usually designed to operate w i t h small signal s w i n g s and h a s corre s p o n d i n g l y l o w noise m a r g i n s . 3. T h e output signal levels are both referenced to V and thus can b e m a d e particularly stable b y operating the circuit with V = 0, in other words, by utilizing a negative p o w e r supply and connecting the V line to ground. In this case, V = 0 and V = -IR . cc
E m i t t e r - c o u p l e d logic is b a s e d o n t h e u s e of t h e current-steering switch introduced in Sec tion 1.7. S u c h a switch can be* m o s t conveniently realized using the differential pair shown in F i g . 11.33. T h e pair is biased w i t h a constant-current source / , and o n e side is connected to a reference voltage V . A s s h o w n in Section 7 . 3 , the current I can b e steered to either Q or Q u n d e r the control of the input signal vj. Specifically, w h e n v is greater than V b y a b o u t 4V (=100 m V ) , nearly all the current / is c o n d u c t e d by Q and thus for a = l , v = V c ~ IRc- Simultaneously, the current t h r o u g h Q will b e nearly zero, a n d thus v = V . C o n v e r s e l y , w h e n v is l o w e r t h a n V b y a b o u t 4V , m o s t of the current / will flow through Q a n d t h e current through Q will b e nearly z e r o . T h u s v = V and v = V - IR . R
2
1. T h e differential n a t u r e of the circuit m a k e s it less susceptible to p i c k e d - u p noise. In particular, an interfering signal will tend to affect b o t h sides of t h e differential pair similarly a n d thus will not result in current switching. This is t h e c o m m o n - m o d e rejection p r o p e r t y of t h e differential pair (see Section 7.3).
0 l
02
cc
cc
cc
0H
0L
C
4. S o m e m e a n s has to b e p r o v i d e d to m a k e the output signal levels c o m p a t i b l e w i t h t h o s e at t h e i n p u t so that o n e gate can drive another. A s w e shall see shortly, practical E C L gate circuits incorporate a level-shifting a r r a n g e m e n t that serves to center the output signal levels o n t h e value of V . R
5. T h e availability of complementary outputs considerably simplifies logic design with E C L .
T
x
0l
cc
02
cc
C
T h e p r e c e d i n g description suggests that as a logic element, the differential pair realizes an inversion function at v and simultaneously p r o v i d e s the c o m p l e m e n t a r y output signal at v . T h e output logic levels are V = V and V - V - IR , and thus t h e output logic 0l
02
0H
cc
0L
cc
C
11.17 l-oriliccircuii in ITj. I 1.33. lei V,, - U . / - 4 m . \ . R, - 2 2 ( ) i > . \ , - - I . 3 2 V. and assume or-- I. IVlcrminc V and V . By how much should the output levels be shifted so that the values of V and V become centered on V 1 What, will the shifted values of V and V , be? Ans.11: - 1 I > N V: -ii.ss V: n.xs V . - ! . " ( , V ;
OH
0L
0H
R
0ll
0I
11.7.2 ECL Families
FIGURE 1 1 . 3 3 The basic element of ECL is the differential pair. Here, V is a reference voltage. R
Although higher speeds of operation can be obtained with gallium arsenide (GaAs) circuits, the latter are not available as off-the-shelf components for conventional digital system design. GaAs digital cir cuits are not covered in this book; however, a substantial amount of material on this subject can be found on the CD accompanying the book and on the website at www.sedrasmith.org. This is in sharp contrast to the technique utilized in a nonsaturating variant of transistor-transistor logic (TTL) known as Schottky TTL. There, a Schottky diode is placed across the CBJ junction to shunt away some of the base current and, owing to the low voltage drop of the Schottky diode, the CBJ from becoming forward biased.
Currently there are t w o p o p u l a r forms of c o m m e r c i a l l y available E C L — n a m e l y , E C L 10K and E C L 100K. T h e E C L 100K series features gate delays of t h e order of 0.75 ns and dissi pates about 4 0 m W / g a t e , for a d e l a y - p o w e r p r o d u c t of 3 0 pJ. A l t h o u g h its p o w e r dissipation is relatively h i g h , t h e 1 0 0 K series provides the shortest available gate delay. T h e E C L 10K series is slightly slower; it features a gate p r o p a g a t i o n delay of 2 ns and a p o w e r dissipation of 2 5 m W for a d e l a y - p o w e r p r o d u c t of 5 0 pJ. A l t h o u g h the value of DP is h i g h e r t h a n that obtained in the 1 0 0 K series, t h e 10K series is easier to use. This is b e c a u s e the rise and fall t i m e s of the pulse signals are deliberately m a d e longer, thus r e d u c ing signal c o u p l i n g , or crosstalk, b e t w e e n adjacent signal lines. E C L 10K h a s an " e d g e s p e e d " of about 3.5 ns, c o m p a r e d w i t h the a p p r o x i m a t e l y 1 ns of E C L 100K. T o g i v e concreteness to o u r study of E C L , in t h e following w e shall consider t h e p o p u l a r E C L 10K in s o m e detail. T h e s a m e t e c h n i q u e s , h o w e v e r , c a n b e applied to other types of E C L . In addition to its u s a g e in small- and m e d i u m - s c a l e integrated-circuit packages, E C L is also e m p l o y e d in large-scale and V L S I applications. A variant of E C L k n o w n as c u r r e n t m o d e logic ( C M L ) is utilized in V L S I applications [see T r e a d w a y (1989) and Wilson (1990)].
11.7.3 The Basic Gate Circuit T h e basic gate circuit of the E C L 10K family is s h o w n in Fig. 11.34. T h e circuit consists of three parts. T h e n e t w o r k c o m p o s e d of Q
h
D
h
D, R 2
u
R , and R generates a reference voltage 2
3
0I
11-7
EMITTER-COUPLED
LOGIC
(ECL)
C^.
v
Vr w h o s e v a l u e at r o o m temperature is - 1 . 3 2 V . A s will b e shown, the value of this reference v o l t a g e is m a d e to c h a n g e with t e m p e r a t u r e in a p r e d e t e r m i n e d m a n n e r to k e e p the n o i s e m a r g i n s a l m o s t constant. A l s o , t h e reference v o l t a g e V
R
variations in t h e p o w e r - s u p p l y v o l t a g e
is m a d e relatively insensitive to
V . EE
11.18 Figure E l 1.18 shows the circuit that generates the reference voltage V . Assuming that the voltage drop acr«Ks each of D , , D , and llic base -cmiiier junction of Q is u . o \ . calculate ibe \ a l n c of V . Neglect the base current of Q . R
e
2
t
R
x
Q
Q
-a -VvV-
- w — w -
i C >; o u O >- B. %
G
G G
^ O c I! II
E
H o >
a;
/A.
M -—
- V W -
1
Y -5.2 Y
-vw
FIGURE E l l . 1 8
1.32 \
Ans.
>
5.2 \
G G ON
T h e s e c o n d part, a n d the heart of t h e gate, is t h e differential amplifier f o r m e d b y Q
R
either Q II
- V W -
G o
6
B 3 C
B
w a s d o n e in t h e circuit of F i g . 11.33, b u t w i t h a resistance R
c o n n e c t e d to t h e n e g a t i v e
E
¡4
O —
and
or Q . T h i s differential amplifier is b i a s e d n o t b y a c o n s t a n t - c u r r e n t source, as
A
supply -V .
N e v e r t h e l e s s , w e will shortly s h o w that the current in R
EE
E
remains approxi-
m a t e l y c o n s t a n t o v e r t h e n o r m a l r a n g e of operation of the gate. O n e side of t h e differential
G
amplifier consists of the reference transistor Q , w h o s e base is connected to the reference volt-
o
age V . T h e other side consists of a n u m b e r of transistors (two in the case s h o w n ) , connected
R
R
05
in parallel, w i t h separated bases, e a c h c o n n e c t e d to a gate input. If the voltages applied to A G
and B are at the l o g i c - 0 level, w h i c h , as w e will s o o n find out, is a b o u t 0.4 V b e l o w V , both R
Q and Q will b e off and the current I in R will flow through the reference transistor Q . T h e A
E
resulting voltage d r o p across R
ffl
C2
E
R
will cause the collector voltage of Q to b e low. R
O n t h e o t h e r h a n d , w h e n t h e v o l t a g e a p p l i e d to A or B is at t h e l o g i c - 1 level, w h i c h , as
•AAAr
o
B
w e will s h o w shortly, is a b o u t 0.4 V a b o v e V , transistor Q R
or Q , or b o t h , will b e o n a n d
A
Q will b e off. T h u s t h e current I will flow t h r o u g h Q
B
or Q , or b o t h , a n d an a l m o s t e q u a l
UJ K
current flows t h r o u g h R
(3
v o l t a g e to d r o p . M e a n w h i l e , since Q is off, its c o l l e c t o r v o l t a g e r i s e s . W e thus see that t h e
R
E
n
A
B
. T h e r e s u l t i n g v o l t a g e d r o p across R
CI
will c a u s e the c o l l e c t o r
R
v o l t a g e at t h e c o l l e c t o r of Q
R
will b e high if A or B, or b o t h , is h i g h , and t h u s at t h e c o l l e c -
tor of Q t h e O R logic function, A + B, is realized. O n the o t h e r h a n d , the c o m m o n c o l l e c t o r R
of Q
A
1 054 l i i p • 3 »
v
:
a n d Q w i l l b e h i g h only w h e n A a n d B are s i m u l t a n e o u s l y l o w . T h u s , at t h e c o m m o n B
1055
CHAPTER 11
1056
11.7
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
E M I T T E R - C O U P L E D L O G I C (ECL)
collector of Q and Q the logic function AB = A + B i s realized. W e therefore c o n c l u d e that the t w o - i n p u t gate of Fig. 11.34 realizes the O R function and its c o m p l e m e n t , the N O R function. T h e availability of c o m p l e m e n t a r y outputs is an important a d v a n t a g e of E C L ; it simplifies logic design and avoids the u s e of additional inverters with associated t i m e delay. A
B
It should b e noted that the resistance connecting each of the gate input terminals to the negative supply enables the user to leave an u n u s e d input terminal open: A n open input terminal will b e pulled down to the negative, supply voltage, and its associated transistor will b e off. Ï-'NOR»
O^OR
EXERCISE 11.19 With input terminals A and B in Fig. 11.34 left open, find the current l through R . Also find the voltages at the collector of Q and at the c o m m o n collector of (he input transistors Q and Q . Use V*, = - 1 . 3 2 V, V of Qu — 0.75 V. and assume that ß of Q is very high. E
h
K
A
/!/;
Ans. i m V
K
A
R
I
V:UV
V =-2V
- V
T
T h e third part of the E C L gate circuit is c o m p o s e d of the t w o emitter followers, Q and Q . T h e emitter followers do not h a v e o n - c h i p loads, since in m a n y applications of highspeed logic circuits the gate output drives a transmission line terminated at the other end, as indicated in Fig. 11.35. ( M o r e on this later in Section 11.7.6.) T h e emitter followers h a v e t w o p u r p o s e s : First, t h e y shift the level of the output signals b y o n e V drop. T h u s , using the results of E x e r c i s e 11.19, w e see that the output levels b e c o m e approximately - 1 . 7 5 V and - 0 . 7 5 V . T h e s e shifted levels are centered approxim a t e l y around the reference voltage (V = - 1 . 3 2 V ) , w h i c h m e a n s that o n e gate can drive another. T h i s compatibility of logic levels at input and output is an essential r e q u i r e m e n t in the design of gate circuits. T h e s e c o n d function of the output emitter followers is to p r o v i d e the gate w i t h low outp u t resistances and with the large output currents r e q u i r e d for charging load capacitances. Since these large transient currents can c a u s e spikes on the p o w e r - s u p p l y line, the collectors of the emitter followers are c o n n e c t e d to a p o w e r - s u p p l y terminal V separate from that of the differential amplifier and the reference-voltage circuit, V . H e r e w e note that the supply current of the differential amplifier and the reference circuit r e m a i n s almost constant. T h e use o f separate power-supply terminals prevents the coupling o f power-supply spikes from the output circuit to the gate circuit and thus lessens the likelihood of false gate switching. Both V i and V are of course connected to the s a m e system ground, external to the chip.
EE
FIGURE 1 1 . 3 6
( - 5 . 2 V)
V = - 2V T
Simplified version of the ECL gate for the purpose of finding transfer characteristics.
2
3
BE
R
ccl
CC2
CC
11.7.4 Voltage Transfer Characteristics H a v i n g p r o v i d e d a qualitative description of the operation of the E C L gate, w e shall n o w derive its voltage transfer characteristics. T h i s will b e d o n e u n d e r the conditions that the outputs are terminated in the m a n n e r indicated in Fig. 11.35. A s s u m i n g that the B input is l o w and thus Q is off, the circuit simplifies to that s h o w n in Fig. 11.36. W e w i s h to analyze this circuit to d e t e r m i n e v versus Vj and v versus v (where v = v ). B
0R
N0R
r
t
c
r
BE
s
BE
T h e O R T r a n s f e r C u r v e F i g u r e 11.37 is a sketch of the O R transfer characteristic, v versus v w i t h the p a r a m e t e r s V , V , V , and V indicated. H o w e v e r , to simplify the calculation of V and V , w e shall u s e an alternative to the unity-gain definition. Specifically, w e shall a s s u m e that at p o i n t x, transistor Q is c o n d u c t i n g 1% of I while Q is c o n d u c t i n g 9 9 % of I . T h e reverse will be a s s u m e d for point y. T h u s at point x w e h a v e
0R
b
0L
IL
0H
IL
[H
m
A
E
E
CC2
I QR
I ransmission line Using the e x p o n e n t i a l i£-v
BE
99
relationship, w e obtain V. R
= V In 99 = 115 m V T
Iß«
w h i c h gives V=
Y V =-2Y
IL
-1.32-0.115 =-1.435 V
T
FIGURE 1 1 . 3 5 The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the "ringing" that would otherwise corrupt the logic signals. (See Section 11.7.6.)
A
In the analysis to follow w e shall m a k e u s e of the exponential i -v characteristic of the BJT. Since the B J T s u s e d in E C L circuits h a v e small areas (in order to h a v e small c a p a c i tances and h e n c e h i g h / ) , their scale currents I are small. W e will therefore a s s u m e that at an emitter current of 1 m A an E C L transistor has a V drop of 0.75 V .
A s s u m i n g Q a n d Q to b e m a t c h e d , w e can write A
R
v
m
- v
R
=v
R
-V
IL
R
1
0 5 8
CHAPTER 1 1
MEMORY A N D ADVANCED
DIGITAL
CIRCUITS
E M I T T E R - C O U P L E D L O G I C (ECL)
11.7
^OR R
R7
s
= 245 fl
-oVn,
Vi so n •
FIGURE 1 1 . 3 8 Circuit for determining V
-2 v
0
( - 1 . 3 2 V) FIGURE 1 1 . 3 7 The OR transfer characteristic v
0R
versus v for the circuit in Fig. 11.36. h
11.20 For the circuit in Fig. 11.36, determine the values of [ obtained when % = V„. V . and V,„. A l i o , f i n d k
w h i c h c a n b e u s e d to find V
IH
)R
V
1H
T o obtain V
0L
R
the value of i-y corresponding to v, = V . Assume that v
as
K
BE
= 0.75 V at a current of 1 m A .
. :, Ans, 3.97 m A ; 4.00 m . \ ; 4 . l 2 mA; - 1 . 3 1 V v5;
= -1.205 V
:
w e n o t e that Q is off a n d Q carries t h e entire current I , g i v e n b y A
R
E
V„-V
+ V».
n
h
N o i s e M a r g i n s T h e results o f E x e r c i s e 11.20 indicate that the bias current I r e m a i n s approximately constant. A l s o , the output v o l t a g e c o r r e s p o n d i n g to v, = V is a p p r o x i m a t e l y equal to V . N o t i c e further that this is also a p p r o x i m a t e l y the m i d p o i n t of the logic s w i n g ; specifically,
=
E
RE
R
- 1 . 3 2 - 0.75 + 5.2
R
0.779 = 4 mA
VOL+VOH
(If w e wish, w e c a n iterate to d e t e r m i n e a better e s t i m a t e of V \
a n d h e n c e ofI .)
BE QR
E
Assum-
ing that Q h a s a h i g h ¡3 so that its a = 1, its collector current will b e a p p r o x i m a t e l y 4 m A . R
If w e n e g l e c t the b a s e current of Q , w e obtain for the collector v o l t a g e of Q 2
y
R
i
-0.98 V
=-4x0.245
= -1.325 = V
R
Thus the o u t p u t l o g i c levels are centered a r o u n d t h e m i d p o i n t of the i n p u t transition band. This is an ideal situation from the p o i n t of v i e w of n o i s e m a r g i n s , a n d it is o n e of the r e a s o n s for selecting the rather arbitrary-looking n u m b e r s (V = - 1 . 3 2 V a n d V = 5.2 V) for reference a n d supply v o l t a g e s . R
C]
Q
R
T h u s a first a p p r o x i m a t i o n for t h e v a l u e of the o u t p u t v o l t a g e V
0L
is
EE
T h e n o i s e m a r g i n s c a n n o w b e e v a l u a t e d as follows:
- V BE
VOL=V \
V
B i
c
NM
H
= -0.98-0.75 =-1.73 V
=V
- V
0H
NM = V - V
m
L
= - 0 . 8 8 - ( - 1 . 2 0 5 ) = 0.325 V
IL
0L
= - 1 . 4 3 5 - ( - 1 . 7 7 ) = 0.335 V
W e c a n u s e this v a l u e to find t h e emitter current of Q a n d then iterate to d e t e r m i n e a better 2
e s t i m a t e of its b a s e - e m i t t e r v o l t a g e . T h e result is V
EE2
Note that t h e s e values are a p p r o x i m a t e l y equal.
= 0.79 V and, c o r r e s p o n d i n g l y ,
-1.77 V
T h e NOR T r a n s f e r C u r v e
IE
A t this v a l u e of o u t p u t voltage, Q supplies a l o a d current of a b o u t 4.6 m A . 2
T o find t h e v a l u e of V
0H
w e a s s u m e that Q is c o m p l e t e l y cut off ( b e c a u s e v, > V ). R
T h u s t h e circuit for d e t e r m i n i n g V
0H
a s s u m i n g B = 100 results in V 2
BE2
m
simplifies to that in Fig. 11.38. A n a l y s i s of this circuit
= 0.83 V , I
E2
= 22.4 m A , a n d
VH 0
%
0
m
R
versus v for t
are identical to
those found earlier for t h e O R characteristic. T o e m p h a s i z e this w e h a v e labeled t h e threshold points x a n d y, the s a m e letters u s e d in F i g . 11.37. For V[ < y , Q is off a n d the o u t p u t v o l t a g e t ^ / L
A
c o m p o s e d of R
cu
= -0.! ! V
T h e N O R transfer characteristic, w h i c h i s
the circuit in F i g . 11.36, is sketched in Fig. 11.39. T h e values of V a n d V
0 R
c a n b e found by analyzing the circuit
Q , a n d its 5 0 - Q termination. E x c e p t that R 3
C1
is slightly smaller t h a n R , C2
this circuit is identical to that in F i g . 11.38. T h u s t h e o u t p u t v o l t a g e will b e only slightly
1 0 5 9
HAPTER 11
u
MEMORY A N D A D V A N C E D
DIGITAL
CIRCUITS
11.7
EMITTER-COUPLED
L O G I C (ECL)
.
1 0 6 1
T h e slope of the s e g m e n t of the transfer characteristic b e y o n d point z, h o w e v e r , is n o t unity but is about 0.5 b e c a u s e as Q is driven deeper into saturation, a portion of the i n c r e m e n t i n v appears as an i n c r e m e n t in the b a s e - c o l l e c t o r forward-bias voltage. T h e reader is u r g e d to solve E x e r c i s e 1 1 . 2 1 , w h i c h is c o n c e r n e d with the details of the N O R transfer characteristic.
NOR I
A
1
11.21 Consider the circuit in Fig. 11.40. (a) For v, = V = - 1 . 2 0 5 V, find v. - . (b) For v, = V = - 0 . 8 8 V. find ; \ . (c) Find the slope of the transfer characteristic at the point v, = V = - 0 . 8 8 V. (d) Find the value of v, at which Q saturates (i.e., V ). Assume that V = 0.75 V at a current of 1 mA, V~- , = (} 3 V and p= 100. ' " ' m
s
0R
0 R
olt
0H
A
s
BK
Ans. (a) - 1 . 7 0 V; (b) - 1 . 7 9 V; (c) - 0 . 2 4 V/V: (d) - 0 . 5 8 V
FIGURE 1 1 . 3 9 The NOR transfer characteristic, %
0 R
Manufacturers' Specifications E C L manufacturers supply gate transfer characteristics of the form s h o w n in Figs. 11.37 a n d 11.39. A manufacturer usually p r o v i d e s such curves m e a s u r e d at a n u m b e r of temperatures. I n addition, at each relevant temperature, worst-case values for the p a r a m e t e r s V, , V , V , a n d V a r e given. T h e s e worst-case values a r e spec ified w i t h the inevitable c o m p o n e n t tolerances taken into account. A s an e x a m p l e , M o t o r o l a specifies that for M E C L 10,000 at 2 5 ° C the following w o r s t - c a s e values a p p l y :
versus v,, for the circuit in Fig. 11.36.
L
greater t h a n the value V found earlier. I n the sketch of F i g . 11.39 w e h a v e a s s u m e d that the o u t p u t v o l t a g e is approximately e q u a l to V . F o r v, > V , Q is on a n d is c o n d u c t i n g t h e entire bias current. T h e circuit t h e n simpli fies to that in F i g . 11.40. This circuit c a n b e easily analyzed to obtain % versus w for the r a n g e v, > V . A n u m b e r of observations are in order. First, n o t e that v = V results in an output v o l t a g e slightly higher than V . T h i s is b e c a u s e R is smaller t h a n R . I n fact, R is c h o s e n l o w e r in value than R so that with v, equal to the n o r m a l logic-1 v a l u e (i.e., V , w h i c h is a p p r o x i m a t e l y - 0 . 8 8 V ) , t h e o u t p u t will b e equal to the V value found earlier for the O R output. S e c o n d , n o t e that as v e x c e e d s V , transistor Q operates in the active m o d e a n d the cir cuit of F i g . 11.40 can b e a n a l y z e d to find the gain of this amplifier, w h i c h is the slope of the s e g m e n t yz of t h e transfer characteristic. A t p o i n t z, transistor Q saturates. F u r t h e r incre m e n t s i n v, ( b e y o n d the point v, = V ) c a u s e t h e collector voltage a n d h e n c e % to increase. 0H
IH
0L
0H
9
0H
1H
V
A
0
IH
I
0L
cl
R
= -1.475 V
1Lmax
V
IHraia
= -1.105 V
0 f f m i n
= -0.980 V
7
Vk
m a
x = -1-630 V
V
[H
cl
T h e s e values c a n b e u s e d to d e t e r m i n e worst-case noise m a r g i n s ,
cl
C2
0H
NM
t
IH
= 0.155 V
L
0L
NM = 0 . 1 2 5 V H
w h i c h a r e about half the typical values previously calculated.
A
F o r additional information o n M E C L specifications the interested reader is referred to the M o t o r o l a ( 1 9 8 8 , 1989) publications listed in t h e bibliography at the e n d of the b o o k .
A
s
0
R
11.7.5 Fan-Out W h e n the input signal to an E C L gate is l o w , the input current is equal to t h e current that flows in t h e 50-k£2 p u l l - d o w n resistor. T h u s T I l L
=
- 1 . 7 7 + 5.2 — 5 b — -
, 6
.
n 9
A
^
W h e n the input is high, the input current is greater b e c a u s e of t h e b a s e current of the input transistor. T h u s , a s s u m i n g a transistor fi of 100, w e obtain
V[0
, 7
- 0 . 8 8 + 5.2 , 4 ^
=
50^
+
1 0 1 ^
. r\s1
2
6
^
* A
B o t h t h e s e current values a r e quite small, which, coupled with the very small output resistance of t h e E C L gate, ensures that little degradation of logic-signal levels results from the input currents of fan-out gates. It follows that t h e fan-out of E C L gates is n o t limited b y -5.2 V
-5.2 V
FIGURE 1 1 . 4 0 Circuit for finding %
-2V(F ) r
0 R
versus v, for the range v, > V . m
9
MECL is the trade name used by Motorola for its ECL.
1062
CHAPTER 11
11.7
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
logic-level considerations b u t rather b y the degradation of the circuit s p e e d (rise and fall times). This latter effect is d u e to t h e c a p a c i t a n c e that each fan-out gate presents to the driv ing gate (approximately 3 p F ) . T h u s w h i l e t h e dc fan-out can b e as h i g h as 9 0 and thus does n o t r e p r e s e n t a design p r o b l e m , the ac fan-out is limited b y considerations of circuit speed to 10 or so.
11.7.6 Speed of Operation and Signal Transmission T h e speed of operation of a logic family is m e a s u r e d b y t h e delay of its basic gate and by t h e rise and fall t i m e s of the output w a v e f o r m s . T y p i c a l values of these p a r a m e t e r s for E C L h a v e already b e e n given. H e r e w e should n o t e that b e c a u s e the output circuit is an emitter follower, the rise t i m e of the output signal is shorter than its fall time, since o n the rising e d g e of the output pulse the emitter follower functions and p r o v i d e s the output current r e q u i r e d to c h a r g e u p the l o a d and parasitic capacitances. O n the other hand, as the signal at the b a s e of t h e emitter follower falls, the emitter follower cuts off, and the load capacitance discharges t h r o u g h t h e c o m b i n a t i o n of l o a d and p u l l - d o w n resistances. T o take full a d v a n t a g e of the v e r y h i g h s p e e d of operation possible with E C L , special attention s h o u l d b e paid to t h e m e t h o d of interconnecting t h e various logic gates in a system. T o appreciate this point, w e shall briefly discuss the p r o b l e m of signal transmission. E C L deals with signals w h o s e rise t i m e s m a y b e 1 ns or even less, the t i m e it takes for light to travel only 3 0 c m or so. F o r such signals a w i r e and its e n v i r o n m e n t b e c o m e a rela tively c o m p l e x circuit e l e m e n t along w h i c h signals p r o p a g a t e with finite speed (perhaps half t h e speed of light—i.e., 15 c m / n s ) . U n l e s s special care is taken, e n e r g y that r e a c h e s the end of such a w i r e is not absorbed b u t rather returns as a reflection to t h e transmitting end, where (without special care) it m a y b e re-reflected. T h e result of this p r o c e s s of reflection is what can b e observed as r i n g i n g , a d a m p e d oscillatory excursion of the signal about its final value. Unfortunately, E C L is particularly sensitive to ringing b e c a u s e the signal levels are so small. T h u s it is important that transmission of signals b e well controlled, and surplus e n e r g y absorbed, to p r e v e n t reflections. T h e a c c e p t e d t e c h n i q u e is to limit the nature of con necting wires in s o m e w a y . O n e w a y is to insist that they b e very short, w h e r e "short" is t a k e n to m e a n w i t h respect to t h e signal rise t i m e . T h e r e a s o n for this is that if the w i r e con n e c t i o n is so short that reflections return w h i l e t h e input is still rising, the result b e c o m e s only a s o m e w h a t s l o w e d and " b u m p y " rising e d g e . If, h o w e v e r , the reflection returns after t h e rising e d g e , it p r o d u c e s not s i m p l y a modifi cation of t h e initiating e d g e but an independent second event. This is clearly b a d ! T h u s the t i m e t a k e n for a signal to g o from o n e e n d of a line a n d b a c k is restricted to less t h a n the rise t i m e of the driving signal b y s o m e factor—say, 5. T h u s for a signal with a 1-ns rise t i m e and for propagation at the speed of light (30 cm/ns), a double path of only 0.2-ns equivalent length, or 6 cm, w o u l d b e allowed, representing in the limit a wire only 3 c m from end to end. S u c h is t h e restriction on E C L 100K. H o w e v e r , E C L 10K has an intentionally slower rise t i m e of about 3.5 n s . U s i n g the s a m e rules, wires can accordingly b e as long as about 10 c m for E C L 10K. If greater lengths are needed, then t r a n s m i s s i o n lines m u s t b e used. T h e s e are simply w i r e s in a controlled e n v i r o n m e n t in w h i c h the distance to a g r o u n d reference p l a n e or sec ond w i r e is highly controlled. T h u s they m i g h t simply b e twisted pairs of wires, one of w h i c h is g r o u n d e d , or parallel ribbon wires, every s e c o n d of w h i c h is grounded, or so-called microstrip lines on a printed-circuit b o a r d . T h e latter are simply copper strips of controlled g e o m e t r y o n o n e side of a thin printed-circuit board, t h e other side of w h i c h consists of a grounded plane.
E M I T T E R - C O U P L E D L O G I C (ECL)
\Jp
S u c h transmission lines h a v e a characteristic impedance, R , that ranges from a few tens of o h m s to h u n d r e d s of o h m s . Signals p r o p a g a t e o n such lines s o m e w h a t m o r e slowly than the speed of light, p e r h a p s half as fast. W h e n a t r a n s m i s s i o n line is terminated at its receiv ing end in a resistance e q u a l to its characteristic i m p e d a n c e , R , all t h e energy sent o n t h e line is a b s o r b e d at the receiving end, and n o reflections occur (since the termination acts as a limitless length of transmission line). T h u s , signal integrity is maintained. Such transmission lines are said to b e properly terminated. A p r o p e r l y terminated line appears at its sending end as a resistor of value R . T h e followers of E C L 10K with their open emitters and low out put resistances (specified to b e 7 Q m a x i m u m ) are ideally suited for driving transmission lines. E C L is also good as a line receiver. T h e simple gate with its high (50-kCi) pull-down input resistor represents a very high resistance to the line. T h u s a few such gates can b e con nected to a terminated line with little difficulty. Both of these ideas are represented in Fig. 11.35. 0
Q
Q
11.7.7 Power Dissipation B e c a u s e of the differential-amplifier n a t u r e of E C L , the gate current r e m a i n s a p p r o x i m a t e l y constant a n d is s i m p l y steered from one side of the gate to t h e other d e p e n d i n g o n the input logic signals. T h u s , the supply current and h e n c e the gate p o w e r dissipation of u n t e r m i n a t e d E C L r e m a i n relatively constant i n d e p e n d e n t of t h e logic state of t h e gate. It follows that n o voltage spikes are i n t r o d u c e d on t h e supply line. S u c h spikes can b e a d a n g e r o u s source of noise in a digital system. It follows that in E C L t h e n e e d for supply-line b y p a s s i n g is n o t as great as in, say, T T L . T h i s is another a d v a n t a g e of E C L . A t this j u n c t u r e w e should reiterate a p o i n t w e m a d e earlier, n a m e l y , that although an E C L gate w o u l d operate with V = 0 and V = + 5 . 2 V , t h e selection of V = -5.2 V and V = 0 V is r e c o m m e n d e d b e c a u s e in the circuit all signal levels are referenced to V , a n d ground is certainly an excellent reference. EE
cc
cc
EE
cc
11.22 For the E C L gate in Fig. 11.34. calculate an approximate value for the power dissipated in the circuit under the condition that all inputs are low and that the emitters of the output followers are left open. Assume that the reference circuit supplies four identical gates, and hence only a quarter of the power dissipated in the reference circuit should be attributed to a single gate. Afis. 22.4 m \ \
11.7.8 Thermal Effects In our analysis of t h e E C L gate of Fig. 11.34, w e found that at r o o m t e m p e r a t u r e t h e refer e n c e v o l t a g e V is - 1 . 3 2 V . W e h a v e also s h o w n that t h e m i d p o i n t of the output logic s w i n g is a p p r o x i m a t e l y e q u a l to this voltage, w h i c h is an ideal situation in that it results in equal high a n d l o w n o i s e m a r g i n s . In E x a m p l e 11.4, w e shall derive expressions for the t e m p e r a ture coefficients of the reference voltage and of the output l o w and h i g h voltages. In this w a y , it will b e s h o w n that the m i d p o i n t of the output logic s w i n g varies with t e m p e r a t u r e at the s a m e rate as the reference voltage. A s a result, although t h e m a g n i t u d e s of the h i g h and low n o i s e m a r g i n s c h a n g e with t e m p e r a t u r e , their values r e m a i n equal. T h i s is an a d d e d a d v a n t a g e of E C L and p r o v i d e s a demonstration of the h i g h degree of design optimization of this gate circuit. R
1063
CHAPTER 11
MEMORY A N D ADVANCED
DIGITAL
CIRCUITS
11.7
EMITTER-COUPLED
LOGIC
W e wish to determine the temperature coefficient of the reference voltage V and of the midpoint R
between V
0L
and
V . 0H
Solution To determine the temperature coefficient of V^, consider the circuit in Fig. E l 1.18 and assume that the temperature changes by +1°C. Denoting the temperature coefficient of the diode and transistor voltage drops by 5, where 8 —-2 m V / ° C , w e obtain the equivalent circuit shown in Fig. 11.41. In the latter circuit the changes in device voltage drops are considered as signals, and hence the power supply is shown as a signal ground. In the circuit of Fig. 11.41 we have two signal generators, and we wish to analyze tire circuit to determine AV , the change in V . W e shall do so using the principle of superposition. Consider first the branch R , D D , 28, and R , and neglect the signal base current of Q The voltage signal at the base of Q can be easily obtained from R
R
x
u
2
2
v
x
FIGURE 1 1 . 4 2 Equivalent circuit for determining the temperature coefficient of V
(
28 x R, Ri + r i + r d
+ R
d2
2
where r and r denote the incremental resistances of diodes D and D , respectively. The dc bias current through £>, and D is approximately 0.64 m A , and thus r = r = 39.5 £2. Hence v — 0 . 3 5 . Since the gain of the emitter follower Q is approximately unity, it follows that the component of AV due to the generator 28is approximately equal to v , that is, AV = 0.38. Consider next the component of AV due to the generator 8. Reflection into the emitter circuit of the total resistance of the base circuit, [Ri\\(,r + r + R )], by dividing it by ¡5 + 1 (with ¡3 — 100) results in the following component of AV^: dx
d2
x
2
2
dl
bl
d2
x
R
bl
R1
R
dl
d2
2
where R denotes the total resistance in the base circuit, and r denotes the emitter resistance of O ( = 4 0 Q ) . This calculation yields AV — -8. Adding this value to that due to the generator 25gives AV = - 0 . 7 5 . Thus for 5 = - 2 m V / ° C the temperature coefficient of V is +1.4 mV/°C. B
el
x
R2
R
R
W e next consider the determination of the temperature coefficient of V . The circuit on which to perform this analysis is shown in Fig. 11.42. Here we have three generators whose contributions can b e considered separately and the resulting components of AV summed. The result is 0L
0L
AV . nr
R 2
[R /{p+l)] B
+
— AV R K
eR
r +R el
~
r
R c 2
R
+R
t
R +r
E
T
e2
3
ß
-Ä r
eR
J.
_
R
C 2
T
+RR E
+ r
T
e2
«r
5
R +r T
+
e2
R /(3+l) C2
Substituting the values given and those obtained throughout the analysis of this section, we find
r
AV
0L
¿2),
The circuit for determining the temperature coefficient of V which w e obtain AV
0H
R
is shown in Fig. 11.43, from
0H
SÖ2
AV o-
= -0.435
©
20
=-5 — R +
IIJ
-
-0.935
r +R /{ß+l)
T
e2
C2
We n o w can obtain the variation of the midpoint of the logic swing as AV + — ^ 2 nr
FIGURE 1 1 . 4 1 Equivalent circuit for determining the temperature coefficient of the reference voltage V . R
AV ^ = -0.685 nH
which is approximately equal to that of the reference voltage
V (-0.18). R
(ECL)
1 065
1 066
CHAPTER 11
M E M O R Y
A N DA D V A N C E D
DIGITAL
11.8
CIRCUITS
11.8
AVOH
o-
FIGURE 1 1 . 4 3 Equivalent circuit for deter mining the temperature coefficient of V . 0H
11.7.9 The Wired-OR Capability T h e emitter-follower output stage of t h e E C L family allows a n additional level of logic to b e p e r f o r m e d at v e r y l o w cost b y s i m p l y w i r i n g t h e outputs of several gates i n parallel. This is illustrated in F i g . 11.44, w h e r e t h e o u t p u t s of t w o gates a r e wired together. N o t e that t h e b a s e - e m i t t e r diodes of the output followers realize a n O R function: This w i r e d - O R connec tion c a n b e u s e d t o p r o v i d e gates w i t h h i g h fan-in as w e l l as t o increase t h e flexibility of
BICMOS
DIGITAL
CIRCUITS
BiCMOS DIGITAL CIRCUITS
In this section, w e p r o v i d e a n introduction t o a V L S I circuit t e c h n o l o g y that is b e c o m i n g increasingly popular, B i C M O S . A s its n a m e implies, B i C M O S t e c h n o l o g y c o m b i n e s bipolar and CMOS circuits o n o n e I C chip. T h e a i m is t o c o m b i n e the l o w p o w e r , h i g h input i m p e d ance, and w i d e n o i s e m a r g i n s of C M O S with the h i g h current-driving capability of bipolar transistors. Specifically, C M O S , although a nearly ideal logic-circuit t e c h n o l o g y in m a n y respects, h a s a limited current-driving capability. This i s n o t a serious p r o b l e m w h e n t h e C M O S gate h a s t o drive a f e w other C M O S gates. I t b e c o m e s a serious issue, h o w e v e r , w h e n relatively large capacitive loads (e.g., greater than 0.5 p F or s o ) are present. I n s u c h cases, o n e h a s t o either resort t o t h e u s e of elaborate C M O S buffer circuits o r face t h e usu ally u n a c c e p t a b l e c o n s e q u e n c e of long p r o p a g a t i o n delays. O n t h e other h a n d , w e k n o w that by virtue of its m u c h larger t r a n s c o n d u c t a n c e , t h e B J T is c a p a b l e of large output currents. W e h a v e seen a practical illustration of that i n t h e e m i t t e r - f o l l o w e r output stage of E C L . Indeed, t h e h i g h current-driving capability contributes t o m a k i n g E C L t w o t o five times faster than C M O S (under equivalent c o n d i t i o n s ) — o f course, at t h e e x p e n s e of h i g h p o w e r dissipation. In s u m m a r y , then, B i C M O S seeks to c o m b i n e the best of the C M O S and bipolar technologies t o obtain a class of circuits that is particularly useful w h e n output currents that are h i g h e r t h a n p o s s i b l e with C M O S are n e e d e d . F u r t h e r m o r e , since B i C M O S t e c h n o l o g y is well suited for t h e i m p l e m e n t a t i o n of h i g h - p e r f o r m a n c e analog circuits, it m a k e s possible the realization of b o t h analog and digital functions o n the s a m e I C chip, m a k i n g the " s y s t e m on a c h i p " a n attainable goal. T h e price p a i d is a m o r e c o m p l e x , and h e n c e m o r e e x p e n s i v e (than C M O S ) p r o c e s s i n g t e c h n o l o g y .
E C L in logic design.
11.8.1 The BiCMOS Inverter 11.7.10 Final Remarks W e h a v e c h o s e n to study E C L b y focusing o n a c o m m e r c i a l l y available circuit family. As h a s b e e n d e m o n s t r a t e d , a great deal of d e s i g n o p t i m i z a t i o n h a s b e e n applied t o create a v e r y - h i g h - p e r f o r m a n c e family of S S I a n d M S I logic circuits. A s already m e n t i o n e d , E C L a n d s o m e of its variants a r e also u s e d i n V L S I circuit design. A p p l i c a t i o n s i n c l u d e very-
A variety of B i C M O S inverter circuits h a v e b e e n p r o p o s e d and are in use. A l l of these a r e based o n t h e u s e of npn transistors to increase t h e output current available from a C M O S inverter. T h i s can b e m o s t simply achieved b y cascading each of t h e Q and Q devices of the C M O S inverter w i t h an npn transistor, as s h o w n in Fig. 11.45(a). O b s e r v e that this cir cuit can b e t h o u g h t of as utilizing t h e pair of c o m p l e m e n t a r y c o m p o s i t e M O S - B J T devices s h o w n i n F i g . 11.45(b). T h e s e c o m p o s i t e d e v i c e s retain t h e high input i m p e d a n c e of t h e M O S transistor while in effect multiplying its rather low g b y the /? of the B J T . It is also use ful to observe that the output stage formed b y Q and Q has w h a t is k n o w n as the t o t e m - p o l e c o n f i g u r a t i o n utilized b y T T L . N
P
1 0
h i g h - s p e e d p r o c e s s o r s such a s t h o s e u s e d i n s u p e r c o m p u t e r s , a s well as h i g h - s p e e d and h i g h - f r e q u e n c y c o m m u n i c a t i o n s y s t e m s . W h e n e m p l o y e d i n V L S I design, c u r r e n t - s o u r c e b i a s i n g is a l m o s t a l w a y s utilized. Further, a variety of circuit configurations are e m p l o y e d
m
x
2
1 1
[see R a b a e y ( 1 9 9 6 ) ] .
T h e circuit of Fig. 11.45(a) operates a s follows: W h e n vj is l o w , b o t h Q and Q are off while Q c o n d u c t s and supplies <2i with b a s e current, thus turning it on. Transistor Q then provides a large output current t o charge t h e l o a d capacitance. T h e result is a very fast charging of the load c a p a c i t a n c e and c o r r e s p o n d i n g l y a short l o w - t o - h i g h propagation delay, t . Transistor Q turns off w h e n v reaches a v a l u e about V - V , and thus the output high level is l o w e r than V , a disadvantage. W h e n vj g o e s high, Q and Q turn off, and Q turns on, p r o v i d i n g its drain current into t h e b a s e of Q . Transistor Q then turns o n and p r o vides a large output current that quickly discharges t h e l o a d capacitance. H e r e again t h e result is a short high-to-low propagation delay, t . O n the negative side, Q turns off w h e n v reaches a value about V , and thus the output l o w level is greater than zero, a disadvantage. N
P
Gate 1 N O R side
PLH
(A + B)
x
x
0
DD
DD
PHL
Gate 2 OR side
BEX
P
2
To load
2
x
N
2
2
0
BE2
A + B + (X + Y)
1 0
FIGURE 1 1 . 4 4 The wired-OR capability of ECL.
It is interesting to note that these composite devices were proposed as early as 1969 [seeLinetal. (1969)]. Refer to the CD accompanying this book for a description of the basic TTL logic-gate circuit and its totem-pole output stage.
APTER 11
11.8
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
BICMOS DIGITAL CIRCUITS
w h i c h t h e b a s e c h a r g e can b e r e m o v e d . This p r o b l e m can b e solved b y adding a resistor b e t w e e n the b a s e of each of Q and Q and g r o u n d , as s h o w n in F i g . 11.45(c). N o w w h e n either Q or Q is t u r n e d off, its stored b a s e c h a r g e is r e m o v e d to g r o u n d t h r o u g h R or R , respectively. Resistor R provides an additional benefit: W i t h v¡ high, and after Q cuts off, v c o n t i n u e s to fall b e l o w V , and the output n o d e is pulled to g r o u n d through the series path of Q and R . T h u s R functions as a p u l l - d o w n resistor. T h e QN-RI path, h o w e v e r , is a h i g h - i m p e d a n c e o n e w i t h t h e result that pulling v to g r o u n d is a rather slow p r o c e s s . Incorporating t h e resistor R , h o w e v e r , is d i s a d v a n t a g e o u s from a static power-dissipation standpoint: W h e n v¡ is l o w , a dc p a t h exists b e t w e e n V and g r o u n d t h r o u g h the c o n d u c t i n g Q and R . Finally, it should b e noted that R and R take s o m e of the drain currents of Q a n d Q a w a y from t h e b a s e s of Q and Q and thus slightly r e d u c e the gate output current available to c h a r g e and discharge the load capacitance. Fi g u r e 11.45(d) s h o w s t h e w a y in w h i c h R and R are usually i m p l e m e n t e d . A s indicated, N M O S devices Q and Q are u s e d to realize R and R . A s an added innovation, these t w o transistors are m a d e to c o n d u c t only w h e n needed. T h u s , Q will c o n d u c t only w h e n vj rises, at w h i c h t i m e its drain current constitutes a r e v e r s e b a s e current for Q , speeding up its turn-off. Similarly Q will c o n d u c t only w h e n v¡ falls and Q conducts, pulling the gate of Q high. T h e drain current of Q t h e n constitutes a reverse b a s e current for Q , speeding u p its turn-off. A s a final circuit for the B i C M O S inverter, w e show the so-called i?-circuit in Fig. 11.45(e). This circuit differs from that in F i g . 11.45(c) in only o n e respect: Rather t h a n returning R to ground, w e h a v e c o n n e c t e d R to the output n o d e of the inverter. This simple c h a n g e has t w o benefits. First, t h e p r o b l e m of static p o w e r dissipation is n o w solved. S e c o n d , R n o w functions as a p u l l - u p resistor, pulling the output n o d e voltage u p to V (through the c o n d u c t i n g Q ) after Q h a s turned off. T h u s , t h e R circuit in Fig. 11.45(e) does in fact h a v e output levels very close to V a n d ground. A s a final r e m a r k o n t h e B i C M O S inverter, w e note that t h e circuit is d e s i g n e d so that transistors Q a n d Q are never simultaneously c o n d u c t i n g a n d neither is allowed to saturate. Unfortunately, s o m e t i m e s t h e resistance of the collector region of the B J T in conjunction with large capacitive-charging currents causes saturation to occur. Specifically, at large output currents, t h e v o l t a g e d e v e l o p e d across r ( w h i c h can b e of t h e order of 100 Q ) can l o w e r the v o l t a g e at t h e intrinsic collector terminal a n d c a u s e the C B J to b e c o m e forward biased. A s t h e r e a d e r will recall, saturation is a harmful effect for t w o r e a s o n s : It limits the collector current to a value less than BI , and it slows d o w n the transistor turn-off. X
X
2
2
X
2
o—I
2
2
0
BE2
N
2
2
0
X
DD
X
X
N
X
P
2
P
2
X
RX
R2
2
X
2
RX
X
R2
P
R2
R2
2
X
X
X
DD
P
X
DD
X
Ov
0
o
v
0
2
c
B
11.8.2 Dynamic Operation (e)
(d)
(c)
FIGURE 1 1 . 4 5 Development of the BiCMOS inverter circuit, (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of Q and Q of the CMOS inverter, (b) The circuit in (a) can be thought of as utilizing these composite devices, (c) To reduce the turn-off times of g i and Q , "bleeder resistors" R and R are added, (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors, (e) An improved version of the circuit in (c) obtained by connecting the lower end of R to the output node. N
2
x
P
2
x
T h u s , w h i l e t h e circuit of Fig. 11.45(a) features large output currents and short propagation delays, it h a s the d i s a d v a n t a g e of r e d u c e d logic swing, and, c o r r e s p o n d i n g l y , reduced n o i s e m a r g i n s . T h e r e is also another a n d p e r h a p s m o r e serious d i s a d v a n t a g e , n a m e l y , the relatively l o n g turn-off delays of Q a n d Q arising from the absence of circuit paths along X
2
A detailed analysis of the d y n a m i c operation of the B i C M O S inverter circuit is a rather c o m plex u n d e r t a k i n g . N e v e r t h e l e s s , an estimate of its p r o p a g a t i o n delay can b e obtained b y considering only t h e t i m e required to charge a n d discharge a l o a d capacitance C. S u c h an a p p r o x i m a t i o n is justified w h e n C is relatively large and thus its effect o n inverter d y n a m i c s is dominant, in other w o r d s , w h e n w e are able to n e g l e c t the t i m e required to charge the parasitic c a p a c i t a n c e s p r e s e n t at internal circuit n o d e s . Fortunately, this is usually the c a s e in practice, for if the load capacitance is not large, o n e w o u l d u s e the simpler C M O S inverter. In fact, it h a s b e e n s h o w n [Embabi, Bellaouar, and E l m a s r y (1993)] that the speed a d v a n t a g e of B i C M O S (over C M O S ) b e c o m e s evident only w h e n t h e gate is required to drive a large fan-out or a large l o a d capacitance. F o r instance, at a load capacitance of 5 0 fF to 100 fF, B i C M O S a n d C M O S typically feature equal delays. H o w e v e r , at a load capacitance of 1 p F , t of a B i C M O S inverter is 0.3 ns, w h e r e a s that of an otherwise c o m p a r a b l e C M O S inverter is about 1 n s . P
1069
CHAPTER 11
11.9
M E M O R Y A N D A D V A N C E D D I G I T A L CIRCUITS
SPICE S I M U L A T I O N E X A M P L i
: 0 7 1
V
DD
A D11.23 JFhe tliivslinlil \oliauc •>!' the BiCM< )S u n c n c r of Eigw J l.45u-i is ibc v.due of at which both Q and Q are conducting equal currents and operating in the saturation region. At this value of v Q will b e on, causing the voltage at the source of Q to he approximately 0.7 V. It is requiredfe d e s i g a t h e c i r c u i t Hgi.-mmo that (he threshold voltage is equal to V /2. FoV:¥ = 5 V. |V,| = 0.6 V, and assuming equal channel lengths for Q and Q and that u„ ~ 2.5 fi , find the required ratio of widths, W /W . x
4
Qp
P
-o
v k
h
s
DD
Dn
s
0
Ï
DD
p
p
n
Ans. 1
i
v -o
P
1
11.9
SPICE SIMULATION EXAMPLE
(b)
(a)
W e c o n c l u d e this chapter b y p r e s e n t i n g a n e x a m p l e that illustrates t h e u s e of S P I C E i n the
FIGURE 1 1 . 4 6 Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances present at the output node.
analysis of b i p o l a r digital circuits.
Finally, in Fig. 11.46, w e show simplified equivalent circuits that c a n b e employed in obtaining rough estimates of t
PLH
and t
PHL
of the i?-type B i C M O S inverter (see P r o b l e m 11.55).
STATIC AND DYNAMIC OPERATION OF AN ECL GATE
11.8.3 BiCMOS Logic Gates In B i C M O S , t h e logic is p e r f o r m e d b y the C M O S part of the gate, with the b i p o l a r portion
In this example, w e u s e P S p i c e to investigate t h e static and d y n a m i c operation of the E C L
s i m p l y functioning as a n output stage. It follows that B i C M O S logic-gate circuits can b e
gate (studied in Section 11.7) whose Capture schematic is shown in Fig. 11.48. Having no access to the actual values for the SPICE model parameters of the B I T s utilized in
generated following the s a m e approach u s e d i n C M O S . A s an e x a m p l e , w e show in Fig. 11.47
commercially available E C L , w e have selected parameter values representative of the technology
a B i C M O S t w o - i n p u t N A N D gate.
utilized that, from our experience, would lead to reasonable agreement between simulation
A s a final r e m a r k , w e note that B i C M O S t e c h n o l o g y is applied i n a variety of products i n c l u d i n g m i c r o p r o c e s s o r s , static R A M s , a n d g a t e arrays [see A l v a r e z ( 1 9 9 3 ) ] .
Ao—c|
Q
PA
Bo—cj
Logic Circuit FIGURE 1 1 . 4 7
A BiCMOS two-input NAND gate.
-
FIGURE 1 1 . 4 8
Capture schematic of the two-input ECL gate for Example 11.5.
Reference-Voltage Circuit
2
1 0 7 2
iO
CHAPTER 11
11.9
MEMORY A N D A D V A N C E D DIGITAL CIRCUITS
V
EE1
=
SPICE SIMULATION EXAMPLE
-5.2V
FIGURE 1 1 . 4 9 Circuit arrangement for computing the voltage transfer characteristics of the ECL gate in Fig. 11.48. results and the measured performance data supplied by the manufacturer. It should be noted that this problem would not be encountered by an IC designer using SPICE as an aid; presumably, the designer would have full access to the proprietary process parameters and the corresponding device model parameters. In any case, for the simulations w e conducted, w e have utilized the following B J T model parameter v a l u e s : I = 0.26 fA, B = 100; B = 1, T = 0.1 ns, C = 1 pF, C = C = 1.5 pF, and | V | = 100 V. 12
S
JC
P
F
F
R
JE
FIGURE 1 1 . 5 0 Voltage transfer characteristics of the OR and NOR outputs (see Fig. 11.49) for the ECL gate shown in Fig. 11.48. Also indicated is the reference voltage, V = -1.32 V. R
A
W e use the circuit arrangement of Fig. 11.49 to compute the voltage transfer characteristics of the ECL gate, that is, w and % versus v , where v is the input voltage at terminal A. For this investigation, the other input is deactivated by applying a voltage v = V = - 1 . 7 7 V. In PSpice, we perform a dc-analysis simulation with v swept over the range - 2 V to 0 V in 10-mV increments and plot w r and % versus v . The simulation results are shown in Fig. 11.50. W e immediately recognize the VTCs as those we have seen and (partially) verified by manual analysis in Section 11.7. The two transfer curves are symmetrical about an input voltage of - 1 . 3 2 V. PSpice also determined that the voltage V at the base of the reference transistor Q has exactly this value (-1.32 V), which is also identical to the value we determined by hand analysis of the reference-voltage circuit. Utilizing Probe (the graphical interface of PSpice), one can determine the values of the important parameters of the VTC, as follows: OR
O R
A
A
B
0L
A
0
0 R
A
R
R
of the transfer characteristics for the case in which the reference circuit is utilized and Fig. 11.51(b) .'• | shows plots for the case in which a constant reference voltage is employed. Figure 11.51(a) indicates rat as the temperature is varied and V changes, the values of V and V also change but remain | centered on V^. In other words, the low and high noise margins remain nearly equal. As mentioned in Section 11.7 and demonstrated in the analysis of Example 11.4, this is the basic idea behind making V temperature dependent. When V,; is not temperature dependent, the symmetry of V and V around V is no longer maintained, as demonstrated in Fig. 11.51(b). Finally, we show in Table 11.1, some of the values obtained. Observe that for the temperature-compensated case, the R
0H
IL
H
N O R output: V
0L
R
0E
0H
R
PSpice-Computed Parameter Values of t h e ECL Gate; W i t h a n d W i t h o u t T e m p e r a t u r e Compensation, at Two Different Temperatures
n
' -
O R output: VQL = - 1 - 7 7 V, V = - 0 . 8 8 V, V = - 1 . 4 1 V, and V NM = 0.34 V and NM = 0.36 V
0H
1
= - 1 . 2 2 V; thus,
M
Temperature-Compensated
Not Temperature-Compensated
L
0L
= - 1 - 7 8 V, V = - 0 . 8 8 V, V = - 1 . 4 1 V, and V = 0.34 V and NM = 0.37 V 0H
NM
H
IL
[H
= - 1 . 2 2 V; thus,
L
These values are remarkably close to those found by pencil-and-paper analysis in Section 11.6. W e next use PSpice to investigate the temperature dependence of the transfer characteristics. The reader will recall that in Section 11.7 we discussed this point at some length and carried out a hand analysis in Example 11.4. Here, we use PSpice to find the voltage transfer characteristics at two temperatures, 0°C and 70°C (the VTCs shown in Fig. 11.50 were computed at 27°C) for two different cases: the first case with V generated as in Fig. 11.48, and the second with the reference-voltage circuit eliminated and a constant, temperature-independent reference voltage of - 1 . 3 2 V applied to the base of Q . T h e simulation results are displayed in Fig. 11.51. Figure 11.51(a) shows plots R
Temperature
0°C
OR
NOR
VOL
-1.779 V
-1.799 V
-1.786 V
-1.799 V
VOH
-0.9142 V
-0.9092 V
-0.9142 V
-0.9092 V
-1.3466 V
-1.3541V
-1.3501V
-1.3541 V
-1.345 V
-1.345 V
-1.32V
-1.32 V
1.6 mV
9.1 mV
30.1 mV
34.1 mV
VOL
-1.742 V
-1.759 V
-1.729 V
-1.759 V
VOH
-0.8338 V
-0.8285 V
-0.8338 V
-0.8285 V
-1.288 V
-1.294 V
-1.2814 V
-1.294 V
-1.271 V
-1.271 V
-1.32V
-1.32V
17 mV
23 mV
38 mV
26.2 mV
VOL+VO„
V av
1
2
v
R
|V.vg-V | R
70°C
R
v " In PSpice, we have created a part called QECL based on these BJT model parameter values. Readers can find this part in the SEDRA.olb library which is available on the CD accompanying this book as well as on-line at www.sedrasmith.org.
Parameter
VOL + VOH 1
2
v
R
OR
NOR
, ' MÊS'
1073
1074
..'
CHAPTER 11
11.9
M E M O R Y A N D A D V A N C E D DIGITAL CIRCUITS
SPICE SIMULATION EXAMPLE
Transmission line
-0.8 V
-1.0V--
-1.2V
-1.4V V
£ £ 2
= -2V
V =-2V EE2
V
EE2
=
-2V
FIGURE 1 1 . 5 2 Circuit arrangement for investigating the dynamic operation of ECL. Two ECL gates (Fig. 11.48) are connected in cascade via a 1.5-m coaxial cable which has a characteristic impedance Z = 50 Q, and a propagation delay t = 10 ns. Resistor R (50 Q.) provides proper termination for the coaxial cable.
-1.6V
0
d
Ti
-1.8V- =
-2.0 V -2.0 V
50 Q.. The manufacturer specifies that signals propagate along this cable (when it is properly ter minated) at about half the speed of light, or 15 cm/ns. Thus w e would expect the 1.5-m cable w e are using to introduce a delay t of 10 ns. Observe that in this circuit (Fig. 11.52), resistor R pro vides the proper cable termination. The cable is assumed to be lossless and is modeled in PSpice using the transmission line element (the T part in the Analog library) with Z = 50 O and t = 10 ns. A voltage step, rising from - 1 . 7 7 V to - 0 . 8 8 4 V in 1 ns, is applied to the input of the first gate, and a transient analysis over a 30-ns interval is requested. Figure 11.53 shows plots of the waveforms of the input, the voltage at the output of the first gate, the voltage at the input of the second gate, and the output. Observe that despite the very high edge-speeds involved, the waveforms are reasonably clean and free of excessive ringing and reflections. This is particularly remarkable
0.0 V
v(NOR)
d
' (a)
-0.8 V
0
\ *\ r—
-1.0V
-1.2V -
-
-
^
\
^
T1
^
. l (
^
.11,1
-II
d
(
-1.4V
-1.6V
-1.8V x
o°c 1
-2.0 V -2.0V
-1.5V
:
1
:
:
1
-1.0V
:
1
-0.5V
—
!
:
0.0V
• • u(NOR) • • v(OR) T t (R) V
v
A
(b) FIGURE 1 1 . 5 1 Comparing the voltage transfer characteristics of the OR and NOR outputs (see Fig. 11.49) of the ECL gate shown in Fig. 11.48, with the reference voltage V generated using: (a) the temperaturecompensated bias network of Fig. 11.48. (b) a temperature-independent voltage source. R
average value of V and V remains very close to V . The reader is encouraged to compare these results to those obtained in Example 11.4. The dynamic operation of the E C L gate is investigated using the arrangement of Fig. 11.52. Here, two gates are connected by a 1.5-m coaxial cable having a characteristic impedance (Z ) of 0L
0H
R
0
• v(IN)
- KOUT1)
• (m2) v
• w(OUT) Time (ns)
FIGURE 1 1 . 5 3 Transient response of a cascade of two ECL gates interconnected by a 1.5-m coaxial cable having a characteristic impedance of 50 Q. and a delay of 10 ns (see Fig. 11.52).
1076
' _:
CHAPTER 11
M E M O R Y A N D A D V A N C E D DIGITAL
PROBLEMS
CIRCUITS
in a square matrix. A cell is selected for reading or writing by activating its row, via the row-address decoder, and its column, via the column-address decoder. The sense amplifier detects the content of the selected cell and pro vides it to the data-output terminal of the chip.
-0.5 V
•
-1.0V
There are two kinds of MOS RAMs: static and dynamic. Static RAMs (SRAMs) employ flip-flops as the storage cells. In a dynamic R A M (DRAM), data is stored on a capacitor and thus must be periodically refreshed. DRAM chips provide the highest possible storage capacity for a given chip area.
-1.5V B
Although sense amplifiers are utilized in SRAMs to speed up operation, they are essential in DRAMs. A typical sense amplifier is a differential circuit that employs posi tive feedback to obtain an output signal that grows expo nentially toward either V or 0. DD
- 2 . 0 V-l
!
' 1' '
1
1: • : I | I . •
' ' ' I . '
0 50 100 15.0,. 200 • v(lN) • tf(OUTl) • v(JN2) • v(OVT) Time (ns)
250
! , • • • I • •
300
350
transistor saturation and by utilizing small logic-signal swings. •
In ECL the input signals are used to steer a bias current between a reference transistor and an input transistor. The basic gate configuration is that of a differential amplifier.
•
There are two popular commercially available ECL types: ECL 10K, having t = 2 ns, P = 25 mW, and DP = 50 p i ; and ECL 100K, having t = 0.75 ns, P = 40 mW, and DP = 30 pi. ECL 10K is easier to use because the rise and fall times of its signals are deliberately made long (about 3.5 ns). P
H
FIGURE 1 1 . 5 4 Transient response of a cascade of two ECL gates interconnected by a 1.5-m cable having a characteristic impedance of 300 Q.. The termination resistance R (see Fig. 11.52) was kept unchanged at 50 Q. Note the change in time scale of the plot. n
H
Some EPROMS utilize floating-gate MOSFETs as the storage cells. The cell is programmed by applying a high voltage to the select gate. Erasure is achieved by illumi nating the chip by ultraviolet light. Even more versatile, EEPROMs can be erased and reprogrammed electrically.
•
Emitter-coupled logic (ECL) is the fastest logic-circuit family. It achieves its high speed of operation by avoiding
because the signal is being transported over a relatively long distance. A detailed examination of the waveforms reveals that the delay along the cable is indeed 10 ns, and the delay of the second gate is about 1.06 ns. Finally, to verify the need for properly terminating the transmission line, the dynamic analysis is repeated, this time'with the 50-O. coaxial cable replaced with a 300-Q. twisted-pair cable while keeping the termination resistance unchanged. T h e results are the slow rising and falling and
Read-only memory (ROM) contains fixed data patterns that are stored at the time of fabrication and cannot be changed by the user. On the other hand, the contents of an erasable programmable ROM (EPROM) can be changed by the user. The erasure and reprogramming is a timeconsuming process and is performed only infrequently.
D
P
D
8
Because of the very high operating speeds of ECL, care should be taken in connecting the output of one gate to the input of another. Transmission-line techniques are usually employed.
•
The design of the ECL gate is optimized so that the noise margins are equal and remain equal as temperature changes.
•
The ECL gate provides two complementary outputs, real izing the OR and NOR functions.
B
The outputs of ECL gates can be wired together to realize the OR function of the individual output variables.
•
BiCMOS combines the low-power and wide noise margins of CMOS with the high current-driving capability (and thus the short gate delays) of BITs to obtain a technology that is capable of implementing very dense, low-power, high-speed VLSI circuits that can also include analog functions.
1
400
10 7 7
long-delayed waveforms shown in Fig. 11.54. (Note the change of plotting scale.)
PROBLEMS
SUMMARY M
•
•
Flip-flops employ one or more latches. The basic static latch is a bistable circuit implemented using two inverters connected in a positive-feedback loop. The latch can remain in either stable state indefinitely. As an alternative to the positive-feedback approach, memory can be provided through the use of charge stor age. A number of CMOS flip-flops are realized this way, including some master-slave D flip-flops. A monostable multivibrator has one stable state, in which it can remain indefinitely, and one quasi-stable state, which it enters upon triggering and in which it remains for a prede termined interval T. Monostable circuits can be used to gen erate a pulse signal of predetermined height and width.
B
•
An astable multivibrator has no stable states. Rather, it has two quasi-stable states, between which it oscillates. The astable circuit, in its operation, is, in effect, a square-wave generator. A ring oscillator is implemented by connecting an odd number (JV) of inverters in a loop, f = \/2Nt . osc
•
P
A random-access memory (RAM) is one in which the time required for storing (writing) information and for retrieving (reading) information is independent of the physical loca tion (within the memory) in which the information is stored.
SECTION 1 1 . 1 : LATCHES AND FLIP-FLOPS 1 1 . 1 Consider the clocked SR flip-flop of Fig. 11.3 for which a minimum-area design is required. Thus Q , 0 , Cj , and Q are minimum-size devices for which W/L = 2 [im/1 Lira. All the other devices should be sized equally so as to barely ensure regeneration. For this design, V = 5 V, |V,| = 1 V, and k' = 2.5k' = 100 LiA/V . Calculate V for each of the internal inverters. Assuming that all the current from the conducting P device (say, Q ) must be sustained for a moment at this voltage by current in (Q , Q ) while both S and
The major part of a memory chip consists of the cells in which the bits are stored and that are typically organized
3
A
DD
2
n
p
h
4 Lira/1
2
3
Lira, V
4
DD
2
= 5 V, |V,\ = 1 V, k' = 2.5k' = 100 n
LiA/V ,
p
and the total capacitance at each of nodes Q and g is 30 fF. (Hint: Follow the method outlined in Exercise 11.2.)
th
2
s
5
R
2
1 1 . 2 For a flip-flop of the type shown in Fig. 11.3, deter mine the minimum width required of the set and reset pulse. Let Q Q , g , and Q be minimum-size devices for which W/L = 2 Lira/1 Lira and all other devices have W/L =
6
6
5
6
1 1 . 3 Consider another possibility for the circuit in Fig. 11.5: Relabel the R input as S and the S input as 7^. Let S and R normally rest at relatively high voltages under the control of a relatively high-impedance source associated with "reading" the content of the flip-flop without changing its state. For "writ ing," that is, setting or resetting the flip-flop, S or R is brought low to 0 V with praised to V to force g or g low to V /2 at DD
DD
CHAPTER 11
1 0 7 8
MEMORY
A N DADVANCED
DIGITAL
CIRCUITS
PROBLEMS
which point regeneration proceeds rapidly. For Q Q , Q , and Q , all minimum size with (W/L) = 2, find (W/L) so that Q can be lowered to 2.5 V in a 5-V system, when S is brought down to OV. Assume |V,\ = IV, k' = 2>k' = 75 LLA/V .
become? If V is nominally 0.5V but can vary due to pro duction variations in the range 0.4V to 0.6V , find the cor responding variation in T expressed as a percentage of the nominal value.
O i l . 4 The clocked SR flip-flop in Fig. 11.3 is not a fully complementary CMOS circuit. Sketch the fully comple mentary version by augmenting the circuit with the PUN corresponding to the PDN comprising Q , Q , Q , and Q . Note that the fully complementary circuit utilizes 12 tran sistors. Although the circuit is more complex, it switches faster.
* 1 1 . 1 1 The waveforms for the monostable circuit of Fig. 11.10 are given in Fig. 11.13. Let V = 10 V, th = V /2, R = WkQ, C = 0.001 /zF, and R = 200 fi. Find the values of T, AV and AV . By how much does v change during the quasi-stable state? What is the peak current that Gj is required to sink? to source?
u
6
n
3
5
p
2
n
p
s
6
7
g
D 1 1 . S Sketch the complementary CMOS circuit imple mentation of the SR flip-flop of Fig. 11.2.
th
DD
* * 1 1 . 7 Consider the latch of Fig. 11.1 as implemented in CMOS technology. Let Li C = 2\i C = 20 pAIV , W = 2W„ = 24 fim,L„ = L„ = 6 pm,\V,\ = 1 V, and V = 5 V. 2
n
ox
p
ox
p
DD
DD
v
DD
an
h
2
ol
1 5 1 1 . 1 2 Using the circuit of Fig. 11.10 design a monostable circuit with CMOS logic for which R = 100 Q, V = 5 V, and V = 0.4 V . Use C = 1 fxF to generate an output pulse of duration T= 1 s. What value of 7? should be used? m
±
0 1 1 . 6 Sketch the logic gate symbolic representation of an SR flip-flop using NAND gates. Give the truth table and describe the operation. Also sketch a CMOS circuit imple mentation.
DD
DD
DD
0 1 1 . 1 3 (a) Use the expression given in Exercise 11.5 to find an expression for the frequency of oscillation f for the astable multivibrator of Fig. 11.15 under the condition that V* = V /2. (b) Find suitable values fori? and C to obtainf = 100 kHz. 0
x
w
z
Y
z
w
A
1 1 . 8 Two CMOS inverters operating from a 5-V supply have V and V of 2.42 and 2.00 V and corresponding out puts of 0.4 V and 4.6 V, respectively, and are connected as a latch. Approximating the corresponding transfer character istic of each gate by a straight line between the threshold points, sketch the latch open-loop transfer characteristic. What are the coordinates of point B? What is the loop gain atB? IH
1 1 . 2 0 In a particular 1 G-bit memory of the dynamic type (called DRAM) under development by Samsung, using a 0.16-jUm, 2-V technology, the cell array occupies about 50% of the area of the 21 m m x 31 mm chip. Estimate the cell area. If two cells form a square, estimate the cell dimensions.
0
1 1 . 1 4 Variations in manufacturing result in the CMOS gates used in implementing the astable circuit of Fig. 11.15 to have threshold voltages in the range 0.4V to 0.6V with 0.5V being the nominal value. Express the expected corre sponding variation in the value of/ (from nominal) as a per centage of the nominal value. (You may use the expression given in Exercise 11.5.) DD
DD
DD
0
* 1 1 . 1 5 Consider a modification of the circuit of Fig. 11.15 in which a resistor equal to 10 R is inserted between the com mon node of C and R and the input node of G . This resistor allows the voltage labeled v to rise above V and below ground. Sketch the resulting modified waveforms of % and show that the period T is now given by x
n
DD
a
T = CÄln
2Vn
•v,
h
v, _ h
1 1 . 2 1 An experimental 1.5-V, 1 G-bit dynamic RAM (called DRAM) by Hitachi uses a 0.16-,um process with a cell size of 0.38 x 0.76 /urn in a 19 x 38 m m chip. What fraction of the chip is occupied by the I/O connections, peripheral circuits, and interconnect? 2
2
1 1 . 2 2 A 256 M-bit RAM chip with a 16-bit readout employs a 16-block design with square cell arrays. How many address bits are needed for the block decoder, the row decoder, and the column decoder? SECTION 1 1 . 4 : RANDOM-ACCESS MEMORY (RAM) CELLS D 1 1 . 2 3 Consider the write operation of the SRAM cell of Fig. 11.18. Specifically, refer to relevant parts of the circuit, as depicted in Fig. 11.20. Let the process technology be char acterized by Li /Li = 2.5, 7 = 0.5 V , |V \ = 0.8 V, 2ty = 0.6 V, and V = 5 V. Also let each of the two inverters be matched and (W/L\ = (W/L) = n, where n denotes the W/L ratio of a minimum-size device.
PLH
PHL
p
t0
3
(a) Using the circuit in Fig. 11.20(a), find the minimum required (W/L) of Q (in terms of n) so that node Q can be pulled to V /2, that is, at u = 2.5 V, I =Ii. (b) Using the circuit of Fig. 11.20(b), find the minimum required (W/L) ratio of Q (in terms of n) so that node Q can be pulled down to V /2, that is, at v = V /2,1 = I. (c) Since Q and Q axe designed to have equal W/L ratios, which of the two values found in (a) and (b) would you choose for a conservative design? (d) For the value found in (c) and for n = 2, and jJ. C = 50 jUA/V , determine the time for v to reach V /2. Let C = 50 fF. 5
SECTION 1 1 . 2 : MULTIVIBRATOR CIRCUITS 0 1 1 . 9 For the monostable circuit of Fig. 11.11, use the approximate expression derived in Exercise 11.3 to find appropriate values for R and C so that T= 1 ms and the maxi mum error in the value obtained for T as a result of neglecting R in the design is 2%. Assume that R is limited to a maxi mum value of 1 kQ. on
1 1 . 1 7 A ring-of-eleven oscillator is found to oscillate at 20 MHz. Find the propagation delay of the inverter.
TYPES AND ARCHITECTURES
0D
1 1 . 1 0 Consider the monostable circuit of Fig. 11.10 under the condition that R <§ R. What does the expression for T on
g
DD
s
6
SECTION 1 1 . 3 : SEMICONDUCTOR MEMORIES:
1 1 . 1 8 A particular 1 M-bit square memory array has its peripheral circuits reorganized to allow for the readout of a 16-bit word. How many address bits will the new design need?
1 1 . 2 4 Consider the circuit in Fig. 11.20(a), and assume that the device dimensions and process technology parameters are as specified in Example 11.2. W e wish to determine the inter val At required for to charge, and its voltage to rise from 0 to V /2. DD
(a) At the beginning of interval At, find the values of 7 , I and 7 - . (b) At the end of interval At, find the values of I , I and I ~. (c) Find an estimate of the average value of 7 - during interval At. (d) If CQ = 50 fF, estimate At. Compare this value to that found in Exercise 11.9 for v to reach V /2. Recalling that regeneration begins when either v or VQ reaches V /2, what do you estimate the delay to be? 5
u
C
s
lt
c
C
g
DD
Q
DD
1 1 . 2 5 Reconsider the analysis of the read operation of the SRAM cell in Example 11.2. This time, assume that bit and bit lines are precharged to V /2. Also consider the dis charge of C [see Fig. 11.19(a)] to begin at the instant the voltage on the word line reaches V /2. (Recall that the resistance and capacitance of the word line causes its voltage to rise relatively slowly toward V .) Using an approach similar to that in Example 11.2, determine the read delay, defined at the time required to reduce the voltage of the B line by 0.2 V. Assume all technology and device parameters are those specified in Example 11.2. DD
g
DD
1 1 . 2 6 For a particular DRAM design, the cell capacitance C = 50 fF, V = 5 V, and V, (including the body effect) = 1.4 V. Each cell represents a capacitive load on the bit line of 2 fF. The sense amplifier and other circuitry attached to the bit line has a 20-fF capacitance. What is the maximum num ber of cells that can be attached to a bit line while ensuring a minimum bit-line signal of 0.1 V? How many bits of row addressing can be used? If the sense-amplifier gain is in creased by a factor of 5, how many word-line address bits can be accommodated? S
DD
1 / 2
n
DD
1 1 . 1 6 Consider a ring oscillator consisting of five invert ers, each having t = 60 ns and t = 40 ns. Sketch one of the output waveforms, and specify its frequency and the per centage of the cycle during which the output is high.
\ 1 0 7 9
DD
DD
DD
(a) Plot the transfer characteristic of each inverter—that is, v versus v , and v versus v . Determine the output of each inverter at input voltages of 1,1.5,2, 2.25, 2.5, 2.75, 3, 3.5,4, and 5 volts. (b) Use the characteristics in (a) to determine the loop voltagetransfer curve of the latch—that is, v versus v . Find the coordinates of points A, B, and C as defined in Fig. 11.1(c). (c) If the finite output resistance of the saturated MOSFET is taken into account, with | V | = 100 V, find the slope of the loop transfer characteristic at point B. What is the approxi mate width of the transition region?
1 1 . 1 9 For the memory chip described in Problem 11.18, how many word lines must be supplied by the row decoder? How many sense amplifiers/drivers would a straightforward implementation require? If the chip power dissipation is 500 m W with a 5-V supply for continuous operation with a 200-ns cycle time, and that all the power loss is dynamic, estimate the total capacitance of all logic activated in any one cycle. If we assume that 90% of this power loss occurs in array access, and that the major capacitance contributor will be the bit line itself, calculate the capacitance per bit line and per bit for this design. If closer manufacturing control allows the memory array to operate at 3 V, how much larger a mem ory array can be designed in the same technology at about the same power level?
;.,
DD
5
Q
DD
6
4
6
n
2
Q
0
DD
0X
1 1 . 2 7 For a DRAM available for regular use 98% of the time, having a row-to-column ratio of 2 to 1, a cycle time of 20 ns, and a refresh cycle of 8 ms, estimate the total memory capacity. 1 1 . 2 8 In a particular dynamic memory chip, C = 25 fF. the bit-line capacitance per cell is 1 fF and bit-line control cir cuitry involves 12 fF. For a 1 M-bit square array, what bitline signals result when a stored 1 is read? when a stored 0 is read? Assume that V = 5 V, and V, (including the body effect) = 1.5 V. Recall that the bit lines are precharged to V /2. S
DD
DD
1 1 . 2 9 For a DRAM cell utilizing a capacitance of 20 IF, refresh is required within 10 ms. If a signal loss on the capac itor of 1 V can be tolerated, what is the largest acceptable leakage current present at the cell?
1080
:
*'
CHAPTER 11
MEMORY A N D A D V A N C E D DIGITAL CIRCUITS
PROBLEMS
SECTION 1 1 . 5 : SENSE AMPLIFIERS AND ADDRESS DECODERS
will be the amplifier response time when a 0 is read? When a 1 is read?
D 1 1 . 3 0 Consider the operation of the differential sense amplifier of Fig. 11.23 following the rise of the sense control signal
1 1 . 3 4 Consider a 512-row NOR decoder. To how many address bits does this correspond? How many output lines does it have? How many input lines does the NOR array require? How many NMOS and PMOS transistors does such a design need?
s
DD
m
DD
DD
DD
DD
2
n
p
1 1 . 3 1 A particular version of the regenerative sense ampli fier of Fig. 11.23 in a 0.5-mn technology, uses transistors for which \V \ = 0.8 V, k' = 2 . 5 * ; = 100 / W V , V = 3.3 V, with (W/L) = 6 t m i / 1 . 5 Lira and (W/L) = 15 ,um/1.5 Lira. For each inverter, find the value of G . For a bit-line capaci tance of 0.8 pF, and a delay until an output of 0.9V is reached of 2 ns, find the initial difference-voltage required between the two bit lines. If the time can be relaxed by 1 ns, what input signal can be handled? With the increased delay time and with the input signal at the original level, by what percentage can the bit-line capacitance, and correspond ingly the bit-line length, be increased? If the delay time required for the bit-line capacitances to charge by the con stant current available from the storage cell, and thus develop the difference-voltage signal needed by the sense amplifier, was 5 ns, what does it increase to when longer lines are used? 2
t
n
DD
n
p
1 1 . 3 5 For the column decoder shown in Fig. 11.27, how many column-address bits are needed in a 256-K bit square array? How many NMOS pass transistors are needed in the multiplexer? How many NMOS transistors are needed in the NOR decoder? How many PMOS transistors? What is the total number of NMOS and PMOS transistors needed? 1 1 . 3 6 Consider the use of the tree column decoder shown in Fig. 11.28 for application with a square 256-K bit array. How many address bits are involved? How many levels of pass gates are used? How many pass transistors are there in total?
m
DD
D 1 1 . 3 2 (a) For the sense amplifier of Fig. 11.23, show that the time required for the bit lines to reach 0.9V and 0.1V is given by t = ( C / G J l n ( 0 . 8 V / A V ) where AVin the initial difference-voltage between the two bit lines. (b) If the response time of the sense amplifier is to be reduced to one half the value of an original design, by what factor must the width of all transistors be increased? (c) If for a particular design, V = 5 V and AV= 0.2 V, find the factor by which the width of all transistors must be increased so that A Vis reduced by a factor of 4 while keeping t unchanged? DD
DD
d
B
D D
DD
d
D 1 1 . 3 3 It is required to design a sense amplifier of the type shown in Fig. 11.23 to operate with a DRAM using the dummy-cell technique illustrated in Fig. 11.25. The DRAM cell provides readout voltages o f - 1 0 0 mV when a 0 is stored and +40 mV when a 1 is stored. The sense amplifier is required to provide a differential output voltage of 2 V in at most 5 ns. Find the W/L ratios of the transistors in the ampli fier inverters assuming that the processing technology is characterized by k' = 2.5k' = 100 uAN , |V,| = 1 V, and V = 5 V. The capacitance of each half bit-line is 1 pF. What 2
n
DD
p
SECTION 1 1 . 6 :
READ-ONLY MEMORY (ROM)
1 1 . 3 7 Give the eight words stored in the ROM of Fig. 11.29. D 1 1 . 3 8 Design the bit pattern to be stored in a (16 x 4) ROM that provides the 4-bit product of two 2-bit variables. Give a circuit implementation of the ROM array using a form similar to that of Fig. 11.29. 1 1 . 3 9 Consider a dynamic version of the ROM in Fig. 11.29 in which the gates of the PMOS devices are connected to a précharge control signal
SECTION 1 1 . 7 :
BE
(a) Find V and V . (b) For the input at B sufficiently negative for Q to be cut off, what voltage at A causes a current of 7/2 to flow in Cj^? (c) Repeat (b) for a current in Q of 0.997. (d) Repeat (c) for a current in Q of 0.01/. (e) Use the results of (c) and (d) to specify V and V . (f) Find NM and NM . (g) Find the value of IR that makes the noise margins equal to the width of the transition region, V - V . (h) Using the IR value obtained in (g), give numerical values for V , V , V , V , and V for this ECL gate. 0H
0L
B
R
R
IL
H
m
0H
0L
p
m
m
m
IL
R
* 1 1 . 4 1 Three logic inverters are connected in a ring. Specifications for this family of gates indicates a typical propagation delay of 3 ns for high-to-low output transitions and 7 ns for low-to-high transitions. Assume that for some reason the input to one of the gates undergoes a low-to-high transition. By sketching the waveforms at the outputs of the three gates and keeping track of their relative positions, show that the circuit functions as an oscillator. What is the frequency of oscillation of this ring oscillator? In each cycle, how long is the output high? low?
tp
(a) During the précharge interval,
DD
FIGURE P 1 1 . 4 0
1 0 8 1
ECL 100K inverters. Assume that the inverters have linearly rising and falling edges (and thus the waveforms are trapezoidal in shape). Let the 0 to 100% rise and fall times be equal to 1 ns. Also, let the propagation delay (for both transitions) be equal to 1 ns. Provide a labeled sketch of the five output signals, taking care that relevant phase information is provided. What is the frequency of oscillation? * 1 1 . 4 3 Using the logic and circuit flexibility of ECL indi cated by Figs. 11.34 and 11.44, sketch an ECL logic circuit that realizes the exclusive OR function, Y = AB + AB. * 1 1 . 4 4 For the circuit in Fig. 11.36, whose transfer charac teristic is shown in Fig. 11.37, calculate the incremental voltage gain from input to the OR output at points x, m, and y of the transfer characteristic. Assume p = 100. Use the results of Exercise 11.20, and let the output a t * be - 1 . 7 7 V and that aty be -0.88 V. Hint: Recall that x and y are defined by a 1%, 99% current split. 1 1 . 4 5 For the circuit in Fig. 11.36, whose transfer charac teristic is shown in Fig. 11.37, find V and V if x and y are defined as the points at which 1L
IH
(a) 90% of the current I is switched. (b) 99.9% of the current I is switched. E
E
1 1 . 4 6 For the symmetrically loaded circuit of Fig. 11.36 and for typical output signal levels (V = - 0 . 8 8 V and V = -1.77 V), calculate the power lost in both load resistors R and both output followers. What then is the total power 0H
* 1 1 . 4 2 Following the idea of a ring oscillator introduced in Problem 11.41, consider an implementation using a ring of five
D D
(c) If we approximate the exponential rise of the word-line voltage by a step equal to the voltage reached in one timeconstant, find the interval At required for an NMOS transistor to discharge the bit line and lower its voltage by 1 V.
IH
L
2
n
EMITTER-COUPLED LOGIC (ECL)
D 1 1 . 4 0 For the ECL circuit in Fig. P11.40, the transistors exhibit V of 0.75 V at an emitter current I and have very high B.
: _
0L
T
•111 1 0 8 2
CHAPTER 11 M E M O R Y A N D A D V A N C E D D I G I T A L
"
dissipation of a single ECL gate including its symmetrical output terminations? 1 1 . 4 7 Considering the circuit of Fig. 11.38, what is the value of B of Q , for which the high noise margin (NM ) is reduced by 50%? 2
H
* 1 1 . 4 8 Consider an ECL gate whose inverting output is terminated in a 50-Q resistance connected to a - 2 - V supply. Let the total load capacitance be denoted C. As the input of the gate rises, the output emitter follower cuts off and the load capacitance C discharges through the 50-Q load (until the emitter follower conducts again). Find the value of C that will result in a discharge time of 1 ns. Assume that the two output levels are -0.88 V and -1.77 V. 1 1 . 4 9 For signals whose rise and fall times are 3.5 ns, what length of unterminated gate-to-gate wire interconnect can be used if a ratio of rise time to return time of 5 to 1 is required? Assume the environment of the wire to be such that the signal propagates at two-thirds the speed of light (which is 30 cm/ns). * 1 1 . 5 0 For the circuit in Fig. PI 1.50 let the levels of the inputs A, B, C, and D be 0 and +5 V. For all inputs low at 0 V,
CIRCUITS
WËËÈÈ WÊBÈË
what is the voltage at E! If A and C are raised to +5 V, what is the voltage at E! Assume | V \ = 0.7 V and B = 50. Express £ as a logic function of A, B, C, and D.
«•••Il
BE
•ail SECTION 1 1 . 8 : CIRCUITS
BiCMOS DIGITAL
*•
4.
t~*
*
X, **L,j!£:__'
*
-
I
1 1 . 5 1 Consider the conceptual BiCMOS circuit of Fig. 11.45(a), for the conditions that V = 5 V, | V \ = 1 v V = 0.7 V, B = 100, k' = 2.5*; = 100 M / V , and (W/L) = 2 fim/1 fim. For v, = v = V /2, find (W/L) so that I = I Q . What is this totem-pole transient current? DD
t
2
BB
n
n
0
E Q L
E
DD
p
2
1 1 . 5 2 Consider the conceptual BiCMOS circuit of Fig. 11.45(a) for the conditions stated in Problem 11.51. What is the threshold voltage of the inverter if both Q and Q have W/L = 2 /xm/1 /Jm? What totem-pole current flows at equal to the threshold voltage? N
p
0 1 1 . 5 3 Consider the choice of values for 7?, and R in the circuit of Fig. 11.45(c). An important consideration in making this choice is that the loss of base drive current be limited. .This loss becomes particularly acute when the current through Q and Q becomes small. This in turn happens near the end of the output signal swing when the associated MOS device is deeply in triode operation (say at \v \ = |V,|/3). Determine values for 7?, and R so that the loss in base current is limited to 50%. What is the ratio 7q/7? ? Repeat for a 20% loss in base drive.
Filters and Tuned Amplifiers
2
N
Introduction
1083
12.7
12.1
Filter T r a n s m i s s i o n , and Specification
Second-Order
Active
Filters
B a s e d o n t h e Two-Integrator-
P
Types,
Loop Topology
1084
1120
DS
2
12.2
2
12.3
1 1 . 5 4 For the circuit of Fig. 11.45(a) with parameters as in Problem 11.51 and with (W/L) = (W/L) , estimate thé propagation delays t , t and t obtained for a load capacitance of 2 pF. Assume that the internal node capacitances do not contribute much to this result. Use average values for the capacitor charging and discharging currents. p
PLH
PHL
2
NA
NB
12.4
Single-Amplifier Active Filters
Butterworth and Chebyshev Filters
12.8
1091
12.9 12.10
First-Order and
Second-Order
Filter F u n c t i o n s
1098
Sensitivity
Biquadratic 1125
1133
Switched-Capacitor Filters
1136
p
12.5
TheSecond-Order L C R Resonator
12.6
1106
Second-Order
Active
Filters B a s e d o n Inductor Replacement
12.11
Tuned Amplifiers
12.12
SPICE
1141
Simulation
Examples
1152
Summary
1158
Problems
1159
1112
N
0 1 1 . 5 7 Sketch the circuit of a BiCMOS two-input NOR gate. If when loaded with a large capacitance the gate is to have worst case delays equal to the corresponding values of the inverter of Fig. 11.45(e), find W/L of each transistor in terms of (W/L) and (W/L) . n
1088
P
D 1 1 . 5 6 Consider the dynamic response of the NAND gate of Fig. 11.46 with a large external capacitive load. If the worst-case response is to be identical to that of the inverter of Fig. 11.45(e), how must the (W/L) ratios of Q , Q , Q , QPA, QPB: Qp be related?
FIGURE P 1 1 . 5 0
Transfer
Function
n
1 1 . 5 5 Repeat Problem 11.54 for the circuit in Fig. 11.45(e) assuming that R =R = 5 k£l x
T h e Filter
INTRODUCTION In this chapter, w e study the design of a n important building b l o c k of c o m m u n i c a t i o n s and instrumentation s y s t e m s , t h e electronic filter. Filter design is o n e of the very f e w areas of engineering for w h i c h a complete design theory exists, starting from specification and ending with a circuit realization. A detailed study of filter design requires a n entire book, a n d indeed such t e x t b o o k s exist. I n the limited s p a c e available here, w e shall concentrate o n a selection of topics that p r o v i d e an introduction t o the subject as well as a useful arsenal of filter circuits a n d design m e t h o d s . T h e oldest t e c h n o l o g y for realizing filters m a k e s u s e of inductors and capacitors, and t h e resulting circuits are called p a s s i v e L C f i l t e r s . S u c h filters w o r k well at h i g h frequencies; 1083
1 0 8 4
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.1
FILTER T R A N S M I S S I O N , T Y P E S , A N D S P E C I F I C A T I O N
h o w e v e r , in l o w - f r e q u e n c y applications (dc to 100 k H z ) t h e required inductors are large and
12.1.2 Filter Types
p h y s i c a l l y b u l k y , a n d their characteristics are quite n o n i d e a l . F u r t h e r m o r e , such inductors
We are specifically interested here in filters that perform a frequency-selection function:
are i m p o s s i b l e to fabricate in m o n o l i t h i c f o r m and are i n c o m p a t i b l e with a n y of the modern
passing signals w h o s e frequency spectrum lies within a specified r a n g e , a n d s t o p p i n g signals
t e c h n i q u e s for a s s e m b l i n g electronic s y s t e m s . T h e r e f o r e , there has b e e n c o n s i d e r a b l e inter
whose frequency spectrum falls outside this r a n g e . S u c h a filter h a s ideally a frequency b a n d
est in finding filter realizations that d o n o t r e q u i r e i n d u c t o r s . Of the various p o s s i b l e types of i n d u c t o r l e s s filters, w e shall study a e t i v e - R C Filters a n d s w i t c h e d - c a p a c i t o r filters.
(or bands) over w h i c h the m a g n i t u d e of transmission is unity (the filter p a s s b a n d ) a n d a fre quency b a n d (or bands) over w h i c h the transmission is zero (the filter stopband). Figure 12.2
A c t i v e - R C filters utilize o p a m p s together with resistors and capacitors a n d are fabricated
depicts the ideal t r a n s m i s s i o n characteristics of the four major filter t y p e s : l o w - p a s s (LP) in
u s i n g discrete, h y b r i d thick-film, or h y b r i d thin-film t e c h n o l o g y . H o w e v e r , for large-volume
Fig. 12.2(a), h i g h - p a s s (HP) in Fig. 12.2(b), b a n d p a s s (BP) in F i g . 12.2(c), a n d b a n d s t o p
production, such technologies do not yield the e c o n o m i e s achieved by monolithic ( I Q fabrica
(BS) or band-reject in Fig. 12.2(d). T h e s e idealized characteristics, b y virtue of their vertical
tion. A t t h e p r e s e n t t i m e , the m o s t v i a b l e a p p r o a c h for realizing fully integrated monolithic
edges, are k n o w n as b r i c k - w a l l r e s p o n s e s .
filters is t h e switched-capacitor t e c h n i q u e . T h e last t o p i c studied in this chapter is t h e t u n e d amplifier c o m m o n l y e m p l o y e d in the d e s i g n of r a d i o a n d T V receivers. A l t h o u g h t u n e d amplifiers are in effect b a n d p a s s filters t h e y are studied separately b e c a u s e their d e s i g n is b a s e d o n s o m e w h a t different t e c h n i q u e s . '
12.1.3 Filter Specification The filter-design p r o c e s s b e g i n s with the filter u s e r specifying t h e transmission characteris tics r e q u i r e d of the filter. S u c h a specification c a n n o t b e of the f o r m s h o w n in Fig. 12.2 because p h y s i c a l circuits c a n n o t realize these idealized characteristics. F i g u r e 12.3 s h o w s realistic specifications for the transmission characteristics of a l o w - p a s s filter. O b s e r v e that
12.1 FILTER TRANSMISSION, TYPES, AND SPECIFICATION
"
since a p h y s i c a l circuit c a n n o t p r o v i d e constant t r a n s m i s s i o n at all p a s s b a n d frequencies, the specifications a l l o w for deviation of the p a s s b a n d t r a n s m i s s i o n from the ideal 0 d B , b u t
12.1.1 Filter Transmission
places an u p p e r b o u n d , A
T h e filters w e are about to study are linear circuits that c a n b e r e p r e s e n t e d b y t h e general two-port n e t w o r k s h o w n in Fig. 1 2 . 1 . T h e filter transfer function T(s) is the ratio of the out
m a x
(dB), on this deviation. D e p e n d i n g o n the application, A
m a x
typ
ically ranges from 0.05 dB to 3 d B . Also, since a physical circuit cannot provide zero transmis sion at all stopband frequencies, the specifications in Fig. 12.3 allow for s o m e t r a n s m i s s i o n
p u t v o l t a g e V (s) to the input v o l t a g e V (s), a
t
V
(s)
m i
T h e filter t r a n s m i s s i o n is found by e v a l u a t i n g 7Y» for p h y s i c a l frequencies, s =jco, and can b e e x p r e s s e d in t e r m s of its m a g n i t u d e a n d p h a s e as T(jcv)
= \T(jco)\e
mm)
Passband •
Stopband
Stopband •
Passband
(12.2)
T h e m a g n i t u d e of t r a n s m i s s i o n is often e x p r e s s e d in d e c i b e l s in.terms of the g a i n f u n c t i o n G(fl))s201og|7X/fl))|,dB
(12.3)
or, alternatively, in terms of the a t t e n u a t i o n f u n c t i o n A((Q)
(a) Low-pass (LP)
= - 2 0 l o g | r ( j f l ) ) | , dB
(b) High-pass (HP)
(12.4)
A filter shapes the frequency s p e c t r u m of the input signal, \ Vi(jco)\,
a c c o r d i n g to the
\T\k
m a g n i t u d e of the transfer function\T(jco)\, thus providing an output V (jco) with a spectrum 0
\V {jco)\ 0
= \TUco)\\V {jco)\
(12.5)
i
A l s o , the p h a s e characteristics of t h e signal are m o d i f i e d as it p a s s e s t h r o u g h the filter a c c o r d i n g to the filter p h a s e function 0(to).
v,- 0 ) o
Filter circuit
• < — Lower — > • stopband
"pi
+ V {s) 0
FIGURE 1 2 . 1 The filters studied in this chapter are linear circuits represented by the general two-port network shown. The filter transfer function T{s) = V (s)/Vj(s). a
< - Upper stopband
Passband
(c) Bandpass (BP)
"2 P
(d) Bandstop (BS)
FIGURE 1 2 . 2 Ideal transmission characteristics of the four major filter types: (a) low-pass (LP), (b) highpass (HP), (c) bandpass (BP), and (d) bandstop (BS).
1
"i
1085
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.1
\T\, d B
T\, d B h
W(l
over t h e stopband. H o w e v e r , the specifications require t h e stopband signals to b e attenuated b y at least A (dB) relative to the p a s s b a n d signals. D e p e n d i n g on t h e filter application, can r a n g e from 2 0 d B to 100 d B . m i n
Since the transmission of a physical circuit c a n n o t c h a n g e abruptly at the e d g e of the passband, the specifications of Fig. 12.3 provide for a b a n d of frequencies over which the attenuation increases from near 0 d B to A^ . This transition b a n d extends from the passband edge co to the stopband edge co . T h e ratio (O lco is usually used as a m e a s u r e of the sharpness of the l o w - p a s s filter r e s p o n s e and is called t h e selectivity factor. Finally, observe that for c o n v e n i e n c e the passband transmission is specified to b e 0 d B . T h e final filter, however, can b e given a p a s s b a n d gain, if desired, w i t h o u t c h a n g i n g its selectivity characteristics. n
s
s
p
T o s u m m a r i z e , t h e transmission of a l o w - p a s s filter is specified b y four parameters: 1. T h e p a s s b a n d e d g e co
p
2. T h e m a x i m u m allowed variation in p a s s b a n d transmission A 3. T h e s t o p b a n d e d g e co
^ ' V
|
<0(2
FIGURE 1 2 . 3 Specification of the ttansmission characteristics of a low-pass filter. The magnitude response of a filter that just meets specifications is also shown.
p
FILTER T R A N S M I S S I O N , T Y P E S , A N D S P E C I F I C A T I O N
m a x
s
4. T h e m i n i m u m required stopband attenuation A ^ T h e m o r e tightly one specifies a filter—that is, lower A , higher A ^ , and/or a selectivity ratio co/co closer to u n i t y — t h e closer the r e s p o n s e of the resulting filter will b e to t h e ideal. H o w e v e r , t h e resulting filter circuit m u s t b e of h i g h e r order and thus m o r e c o m p l e x and expensive. In addition to specifying the m a g n i t u d e of transmission, there are applications in which t h e p h a s e r e s p o n s e of t h e filter is also of interest. T h e filter-design p r o b l e m , h o w e v e r , is considerably c o m p l i c a t e d w h e n both m a g n i t u d e a n d p h a s e are specified. O n c e t h e filter specifications h a v e b e e n d e c i d e d u p o n , t h e n e x t step in t h e d e s i g n is to find a transfer function w h o s e m a g n i t u d e m e e t s t h e specification. T o m e e t specification, t h e m a g n i t u d e - r e s p o n s e curve m u s t lie in t h e u n s h a d e d area in Fig. 12.3. T h e c u r v e shown in t h e figure is for a filter that just m e e t s specifications. O b s e r v e that for this particular filter, t h e m a g n i t u d e r e s p o n s e ripples t h r o u g h o u t t h e p a s s b a n d w i t h t h e ripple p e a k s b e i n g all
FIGURE 1 2 . 4 Transmission specifications for a bandpass filter. The magnitude response of a filter that just meets specifications is also shown. Note that this particular filter has a monotonically decreasing transmission in the passband on both sides of the peak frequency.
equal. Since the p e a k ripple is equal to A it is usual to refer to A as the p a s s b a n d ripple a n d to co as t h e r i p p l e b a n d w i d t h . T h e particular filter r e s p o n s e s h o w n ripples also in t h e s t o p b a n d , again w i t h the ripple p e a k s all equal and of such a value that the m i n i m u m stopb a n d attenuation a c h i e v e d is equal to the specified v a l u e , A^. T h u s this particular r e s p o n s e is said to b e e q u i r i p p l e in b o t h the p a s s b a n d a n d t h e stopband. T h e p r o c e s s of obtaining a transfer function that m e e t s g i v e n specifications is k n o w n as filter a p p r o x i m a t i o n . Filter a p p r o x i m a t i o n is usually p e r f o r m e d u s i n g c o m p u t e r p r o g r a m s ( S n e l g r o v e , 1982; Ouslis and Sedra, 1995) or filter design tables (Zverev, 1967). In simpler c a s e s , filter a p p r o x i m a t i o n can be p e r f o r m e d using closed-form expressions, as will be seen in Section 1 2 . 3 . m a x
m a x
p
Finally, Fig. 12.4 shows transmission specifications for a bandpass filter and the response of a filter that meets these specifications. F o r this e x a m p l e w e h a v e chosen an approximation function that d o e s not ripple in the p a s s b a n d ; rather, t h e transmission decreases m o n o t o n i cally o n b o t h sides of t h e center frequency, attaining t h e m a x i m u m allowable deviation at t h e t w o e d g e s of the p a s s b a n d .
m a x
p
12.1 Find approximate values of attenuation (in dB) corresponding to filter transmissions of: 1, 0.99. 0.9, 0.8,0.7,0.5,0.1,0. Ans.0. 0 . 1 , 1 , 2 , 3, 6 , 2 0 , ° = ( d B ) 12.2 If the magnitude, of passband transmission is to remain constant to within ± 5 % , and if the stopband transmissionis to: be no greater than 1% of the passband transmission; find A and A . IK1X
Ans. 0.9 d B ; 4 0 dB
m i n
1087
12.2
CHAPTER 12 FILTERS AND TUNED AMPLIFIERS
A jco
• " 12.2 THE FILTER TRANSFER FUNCTION
THE FILTER TRANSFER FUNCTION
J O
x poles O zeros
T h e filter transfer function T(s) c a n b e w r i t t e n as the ratio of t w o p o l y n o m i a l s as M
M-l
a s
+ a _s
u
T
(
S
)
M
0
— + b _s N
%
s plane
()
+ ••• + a
x
=
s
0,
(12.6)
+ ••• + b
x
0
T h e d e g r e e of t h e d e n o m i n a t o r , N, is t h e filter o r d e r . F o r t h e filter circuit t o b e stable, the d e g r e e of t h e n u m e r a t o r m u s t b e less than o r equal t o that of t h e d e n o m i n a t o r ; M
u
. . .,a
M
a n d b , by,...,
b_
0
N
are real n u m
u
b e r s . T h e p o l y n o m i a l s in t h e n u m e r a t o r a n d d e n o m i n a t o r c a n b e factored, and T(s) can b e ()
e x p r e s s e d in t h e form
() (s-p )(s-p ) l
T h e n u m e r a t o r roots, z
1 ;
•••
2
—a>
{2
FIGURE 1 2 . 5 Pole-zero pattern for the lowpass filter whose transmission is sketched in Fig. 12.3. This is a fifth-order filter (N= 5).
(s-p ) N
z , • • •, ^M> a r e t h e t r a n s f e r - f u n c t i o n z e r o s , o r t r a n s m i s s i o n zeros; 2
a n d t h e d e n o m i n a t o r roots, p
h
p , . • • , p , a r e t h e t r a n s f e r - f u n c t i o n p o l e s , o r t h e natural 2
N
1
m o d e s . E a c h transmission zero o r p o l e c a n b e either a real or a c o m p l e x n u m b e r . C o m p l e x zeros a n d p o l e s , h o w e v e r , m u s t o c c u r in conjugate pairs. T h u s , if - 1 + j2 h a p p e n s t o b e a z e r o , then - 1 -j2
A s a n o t h e r e x a m p l e , consider t h e b a n d p a s s filter w h o s e m a g n i t u d e r e s p o n s e is s h o w n in Fig. 12.4. This filter h a s transmission zeros at s = ± jco
also m u s t b e a zero.
n
S i n c e in t h e filter stopband t h e t r a n s m i s s i o n is r e q u i r e d t o b e zero or small, the filter
zeros at s = 0 a n d o n e o r m o r e zeros at 5 =
and s = ±jco . l2
It also h a s o n e or m o r e
( b e c a u s e t h e t r a n s m i s s i o n decreases t o w a r d 0
t r a n s m i s s i o n zeros are usually p l a c e d o n t h e jco axis at s t o p b a n d frequencies. This indeed is
as co a p p r o a c h e s 0 a n d 00). A s s u m i n g that only o n e z e r o exists at e a c h of s - 0 and s = °°, t h e
t h e case for t h e filter w h o s e transmission function is sketched i n F i g . 1 2 . 3 . This particular
filter m u s t b e of sixth order, a n d its transfer function takes t h e form
filter c a n b e seen t o h a v e infinite attenuation (zero transmission) at t w o s t o p b a n d frequen cies: a>n a n d (O . T h e filter then m u s t h a v e t r a n s m i s s i o n zeros at s = +/<% a n d s =
+j(O .
l2
l2
T(s)
,
=
H o w e v e r , since c o m p l e x zeros o c c u r in conjugate pairs, t h e r e m u s t also b e transmission
a s(s 5
+ cof,)(s
s + bs 5
zeros at s = -jco
a n d s = -jco .
factors (s + jco )(s
- jcOn)(s + jCDn)(s - jco ),
n
cof ) 7
(12.9)
0
T h u s t h e n u m e r a t o r p o l y n o m i a l of this filter will h a v e the
L2
n
+
^ ^ + •••+ b
2
w h i c h can b e written as (s
l2
2
2
2
+ (0 {)(s
2
+ co ).
For
l2
A typical p o l e - z e r o plot for such a filter is s h o w n i n F i g . 12.6.
2
s = jco (physical frequencies) t h e n u m e r a t o r b e c o m e s (-co + c o ^ X - c o + cof ), w h i c h indeed 2
is zero at ft) = co a n d co = co . n
i2
kjco
C o n t i n u i n g with t h e e x a m p l e in F i g . 1 2 . 3 , w e o b s e r v e that t h e transmission decreases
t
t o w a r d - ° ° as co a p p r o a c h e s °°. T h u s t h e filter m u s t h a v e o n e o r m o r e t r a n s m i s s i o n zeros at
o
s = °°. In general, the n u m b e r of t r a n s m i s s i o n zeros at 5 = °° is t h e difference b e t w e e n the
<»p2
d e g r e e of t h e n u m e r a t o r p o l y n o m i a l , M, a n d t h e d e g r e e of t h e d e n o m i n a t o r p o l y n o m i a l , N, of t h e transfer function in E q . ( 1 2 . 6 ) . T h i s is b e c a u s e as s a p p r o a c h e s °°, T(s) a p p r o a c h e s N
M
a /s ~ and M
thus is said to h a v e N-Mzeros
at s = <».
F o r a filter circuit t o b e stable, all its p o l e s m u s t lie in t h e left half of t h e s p l a n e , a n d thus Pi, p , . . . , p 2
N
m u s t all h a v e n e g a t i v e real parts. F i g u r e 12.5 s h o w s typical p o l e a n d zero
plane
X poles O zeros ()
locations for t h e low-pass filter w h o s e t r a n s m i s s i o n function is d e p i c t e d in F i g . 1 2 . 3 . W e h a v e a s s u m e d that this filter is of fifth o r d e r (N= 5 ) . It h a s t w o pairs of c o m p l e x - c o n j u g a t e 0
poles and o n e real-axis pole, for a total of five poles. A l l the poles h e in the vicinity of the passband, w h i c h is w h a t g i v e s t h e filter its h i g h t r a n s m i s s i o n at p a s s b a n d f r e q u e n c i e s . T h e five t r a n s m i s s i o n zeros are at s = +j(O ,
s = ±jco ,
tl
and s = °°. T h u s , t h e transfer function for this
[2
(P - < u
a €1
filter is of t h e f o r m r
(
j
)
2
_
a (s 4
5
s
4
+ bs 4
2
2
+ co )(s
+ coj )
n
3
+ bs 3
2
2
+ bs 2
(
1
2
8
)
+ bs + b v
0
Throughout this chapter, we use the names poles and natural modes interchangeably.
0
FIGURE 1 2 . 6 Pole-zero pattern for the band pass filter whose transmission function is shown in Fig. 12.4. This is a sixth-order filter (N= 6).
1 089
1 090
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.3
B U T T E R W O R T H A N D C H E B Y S H E V FILTERS
".' .'
1091
l | r L dB 12.4
i i j(0
A fourth-order filter has zero transmission at co = 0, co = 2 rad/s, and co = » . T h e natural m o d e s a r e - 0 . 1 ±jO.% and - 0 . 1 ± j l . 2 . Find T(s).
Five O at < a
Ans. f , , ) - =
x poles O zeros
.12.5
^
2
+ 4)
2
(s + 0.2s + 0 . 6 5 ) ( / + 0 . 2 5 + 1.45)
'
Find the transfer function 71?) of a third-order all-pole low-pass filter whose poles are at a radial distance of 1 rad/s from die origin and whose complex poles are at 30° angles from the jco axis. T h e dc gain is unity. Show that | T(jco)] = \/J\ +co . Find » and the attenuation at co= 3 rad/s. 6
? d B
2
Ans. T(s) = 1 / ( 5 + 1 )(.s + .v + 1); 1 rad/s; 28.6 dB
- I
In this section, w e present two functions that are frequently used in approximating the transmission characteristics of low-pass filters. Closed-form expressions are available for the parameters of t h e s e f u n c t i o n s , a n d thus o n e can u s e t h e m in filter design w i t h o u t the n e e d for c o m p u t e r s or f i l t e r - d e s i g n tables. T h e i r utility, h o w e v e r , is Hmited t o relatively simple applications.
(b)
(a)
FIGURE 1 2 . 7 (a) Transmission characteristics of a fifth-order low-pass filter having all transmission zeros at infinity, (b) Pole-zero pattern for the filter in (a). A s a third and final e x a m p l e , consider t h e l o w - p a s s filter w h o s e transmission function is depicted in Fig. 12.7(a). W e o b s e r v e that in this c a s e there are n o finite values of co at which the attenuation is infinite (zero transmission). T h u s it is possible that all t h e transmission zeros of this filter are at s = <*>. If this is t h e case, t h e filter transfer function takes the form T(s) = N
s
+ b N-l S
N-l
, +
12.3 BUTTERWORTH AND CHEBYSHEV FILTERS
(12.10)
A l t h o u g h in this section w e discuss t h e design of l o w - p a s s filters only, t h e a p p r o x i m a tion f u n c t i o n s p r e s e n t e d can b e applied to t h e design of other filter types t h r o u g h the u s e of frequency t r a n s f o r m a t i o n s [see S e d r a and B r a c k e t t ( 1 9 7 8 ) ] .
12.3.1 The Butterworth Filter 3
F i g u r e 1 2 . 8 s h o w s a sketch of the m a g n i t u d e r e s p o n s e of a B u t t e r w o r t h filter. This filter exhibits a m o n o t o n i c a l l y decreasing transmission with all t h e transmission zeros at co = «>., m a k i n g it a n all-pole filter. T h e m a g n i t u d e function for an M h - o r d e r B u t t e r w o r t h filter w i t h a p a s s b a n d e d g e co is g i v e n b y p
+ b
0
S u c h a filter is k n o w n as a n a l l - p o l e filter. T y p i c a l p o l e - z e r o locations for a fifth-order allp o l e l o w - p a s s filter are s h o w n in F i g . 12.7(b). A l m o s t all t h e filters studied i n this c h a p t e r h a v e all their t r a n s m i s s i o n zeros o n the jco axis, in t h e filter stopband(s), i n c l u d i n g c o = 0 and co= °°. A l s o , to obtain h i g h selectivity, all the natural m o d e s will b e c o m p l e x conjugate (except for the c a s e of o d d - o r d e r filters, where o n e natural m o d e m u s t b e o n t h e real axis). Finally w e n o t e that t h e m o r e selective the r e q u i r e d filter r e s p o n s e is, t h e h i g h e r its order m u s t b e , and the closer its natural m o d e s are to t h e jco axis. 2
\T(jco)\=-—è==
(12.11) 2N
1 + e
2
_CO] co J p
At co = co , p
\T{jco )\ p
= — 2 Jl
(12.12)
= 2
+ e
T h u s , t h e p a r a m e t e r e d e t e r m i n e s t h e m a x i m u m variation in p a s s b a n d transmission, A according t o 2
4 ™ = 2 0 log V l + e 12.3 A second-order filter has its poles at s = - ( 1 / 2 ) ± j{j3/2). e & y a a d i s unity at dc {co ~ 0). Find the transfer function.
The transmission is zero at co- 2 rad/s
Conversely, given A
m a x
Ans. / - ( , )
^1 4
2
V-
-f±±-r ,V -r 1
Obviously, a low-pass filter should not have a transmission zero at co= 0, and, similarly, a high-pass filter should not have a transmission zero at co = °°.
,
(12.13)
, t h e v a l u e of e can b e d e t e r m i n e d from £=A/10
'•
_
m a x
- 1
'
(12.14)
O b s e r v e t h a t i n t h e B u t t e r w o r t h r e s p o n s e the m a x i m u m deviation in p a s s b a n d transmission (from t h e i d e a l v a l u e of unity) occurs at the p a s s b a n d e d g e only. It can b e s h o w n that the first
The Butterworth filter approximation is named after S. Butterworth, a British engineer who in 1930 was among the first to employ it.
1092
CHAPTER 12
FILTERS A N D T U N E D
AMPLIFIERS
12.3
B U T T E R W O R T H A N D C H E B Y S H E V FILTERS
A t t h e e d g e of the stopband, co = co , t h e attenuation of the B u t t e r w o r t h filter is given b y s
A{co ) = - 2 0 1 o g [ l / 7 l
2
+ e (ft)/© )
s
2 A r
p
= loiogu + .W^f"]
] (12J5)
This equation c a n b e u s e d to d e t e r m i n e t h e filter order required, w h i c h is t h e lowest integer value of N that yields A(co ) > A . T h e natural m o d e s of an M h - o r d e r B u t t e r w o r t h filter c a n b e d e t e r m i n e d from t h e g r a p h ical construction s h o w n in Fig. 12.10(a). O b s e r v e that t h e natural m o d e s lie on a circle of s
min
2N - 1 derivatives of | J | relative to co are zero at co = 0 [see V a n V a l k e n b u r g (1980)]. This property m a k e s the Butterworth r e s p o n s e very flat near co= 0 and gives t h e r e s p o n s e t h e n a m e m a x i m a l l y flat response. T h e degree of p a s s b a n d flatness increases as the order N is increased, as c a n b e seen from Fig. 12.9. This figure indicates also that, as should b e expected, as the order N is increased the filter r e s p o n s e approaches t h e ideal brick-wall type of response.
\T\i
FIGURE 1 2 . 9
Magnitude response for Butterworth filters o f various order with e = 1 . Note that as the
FIGURE 1 2 . 1 0 Graphical construction for determining the poles of a Butterworth filter of order N. A l l the poles lie i n the left half of the 5 plane on a circle of radius co = m (Ve) , where e is the passband deviation parameter ( =Jin
0
order increases, the response approaches the ideal brick-wall type of transmission.
e
1 ) :
a ) t
h
e g
e
n
e
r
a
l
c a s e !
p
1 0 9 3
1 0 9 4
,
CHAPTER 12
r a d i u s co (l/e)
a n d are spaced b y e q u a l angles of n/N,
p
K/2N
12.3
FILTERS A N D T U N E D AMPLIFIERS
B U T T E R W O R T H A N D C H E B Y S H E V FILTERS
with t h e first m o d e at an angle
from t h e +jco axis. S i n c e t h e natural m o d e s all h a v e e q u a l radial distance from VN
t h e origin t h e y all h a v e t h e s a m e frequency co = co (l/e) . 0
F i g u r e 12.10(b), (c), a n d (d)
p
s h o w s t h e natural m o d e s of B u t t e r w o r t h filters of order N = 2 , 3 , a n d 4 , respectively. Once the N natural modes p , p , . . . , p x
2
h a v e b e e n f o u n d , t h e transfer function c a n b e
N
w r i t t e n as
T(s)
=
* f (s-p )(s-p ) 1
(12.16) •••
2
(s-p ) N
w h e r e K is a c o n s t a n t e q u a l t o t h e r e q u i r e d d c gain of t h e filter. T o s u m m a r i z e , t o find a B u t t e r w o r t h transfer function that m e e t s t r a n s m i s s i o n specifications of t h e f o r m in Fig. 12.3 w e p e r f o r m t h e following p r o c e d u r e : 1. D e t e r m i n e e from E q . (12.14). 2. U s e E q . (12.15) to d e t e r m i n e t h e r e q u i r e d filter order as t h e l o w e s t integer v a l u e of N that results i n A(co ) > s
A^.
3. U s e Fig. 12.10(a) to d e t e r m i n e t h e N n a t u r a l m o d e s . 4. U s e E q . (12.16) t o d e t e r m i n e T(s).
12.3.2 The Chebyshev Filter Fi gure 12.12 s h o w s r e p r e s e n t a t i v e transmission functions for C h e b y s h e v
4
filters of e v e n
and o d d order. T h e Chebyshev filter exhibits an equiripple response in the passband and a m o n o .,
I i n d t h e Butterworth transfer function that meets the following low-pass filter specifications: /, = 10 k H z , A
m a x
= 1 dB,f = 15 kHz, A^ s
= 25 d B , dc gain = 1.
tonically d e c r e a s i n g t r a n s m i s s i o n in t h e stopband. W h i l e t h e o d d - o r d e r filter h a s
|r(0)| = 1,
the even-order filter exhibits its m a x i m u m m a g n i t u d e deviation at co= 0. In both cases the total n u m b e r of p a s s b a n d m a x i m a a n d m i n i m a equals t h e o r d e r of t h e filter, N. A l l t h e t r a n s m i s -
"olution
sion zeros of t h e C h e b y s h e v filter are at co = °°, m a k i n g it an all-pole filter.
Bill Substituting A ,
m a x
= 1 dB into Eq. (12.14) yields e = 0.5088. Equation (12.15) is then used to
determine the filter order by trying various values for N. W e find that TV = 8 yields A(co ) =
T h e m a g n i t u d e of t h e transfer function of an Nth-order C h e b y s h e v filter with a p a s s b a n d edge (ripple b a n d w i d t h ) co is g i v e n b y p
s
22.3 d B a n d N = 9 gives 25.8 dB. W e thus select N= 9. N
Hie same frequency co = co (l/ef Q
irst pole pi is given by = P l
Combining p
x
p
ffl (-cos80° 0
3
= 2nxl0x
10 (1/0.5088)
1 / 9
1
lH/tp)l = —
Figure 12.11 shows the graphical construction for determining the poles. T h e poles all have
2
2
= 6.773 x 1 0 rad/s. The
for co
t 2
Jl +
4
(12.18)
p
2
€ cos [Ncos~\co/co )] p
and
+ j s i n 8 0 ° ) = < a ( - 0 . 1 7 3 6 + jO.9848) 0
with its complex conjugate p
g
yields the factor (s~ + J 0 . 3 4 7 2 o ) + aQ 0
in the
\T{jco)\
1
= 2
denominator of the transfer function. T h e same can be done for the other complex poles, and the
2
— -
A/1 + e c o s h [A/cosh
omplete transfer function is obtained using Eq. (12.16),
mni
for cv> co
p
(12.19)
1
(co/co )] p
A t t h e p a s s b a n d e d g e , co = co , t h e m a g n i t u d e function is g i v e n b y
ill
p
\T(j(O )\
SI
p
2
VT77
9
T(s) = (s + co )(s Q
-— 1 + yl.8794ft) + co )(s 0
=
0
~ + ¿1.5321 w + fl) ) 0
0
(12.17)
Named after the Russian mathematician P. L. Chebyshev, who in 1899 used these functions in studying the construction of steam engines.
12.3 1096
CHAPTER 12
BUTTERWORTH AND CHEBYSHEV FILTERS
^"l
FILTERS AND TUNED AMPLIFIERS T o s u m m a r i z e , given low-pass transmission specifications of t h e type s h o w n in Fig. 12.3, t h e transfer function of a C h e b y s h e v filter that m e e t s t h e s e specifications c a n b e found as follows: 1. D e t e r m i n e e from E q . (12.21). 2. U s e E q . (12.22) t o d e t e r m i n e the order required. 3. D e t e r m i n e the poles u s i n g E q . (12.23). 4. D e t e r m i n e t h e transfer function u s i n g E q . (12.24). T h e C h e b y s h e v filter p r o v i d e s a m o r e efficient a p p r o x i m a t i o n than t h e B u t t e r w o r t h filter. T h u s , for t h e s a m e o r d e r a n d t h e s a m e A
m a x
, t h e C h e b y s h e v filter p r o v i d e s greater s t o p b a n d
attenuation t h a n t h e B u t t e r w o r t h filter. Alternatively, to m e e t identical specifications, o n e requires a l o w e r o r d e r for t h e C h e b y s h e v than for the B u t t e r w o r t h filter. This p o i n t will b e illustrated b y t h e following e x a m p l e .
f
Find the Chebyshev transfer function that meets the same low-pass filter specifications given in Example 12.1: namely, f = 10 kHz, A p
= 1 dB, f = 15 kHz, A ^ = 25 d B , dc gain = 1.
m a x
s
Solution Substituting A
T h u s , t h e p a r a m e t e r e d e t e r m i n e s t h e p a s s b a n d ripple a c c o r d i n g t o
m a x
= 1 dB into Eq. (12.21) yields e = 0.5088. B y trying various values for N in
Eq. (12.22) w e find that N = 4 yields A(co ) = 21.6 dB and N = 5 provides 29.9 d B . W e thus s
A C o n v e r s e l y , given A
m a x
m a x m a x
= 101og(l + +
2 e
e
))
(12.20)
2
select N = 5. Recall that w e required a ninth-order Butterworth filter to meet the same specifica tions in E x a m p l e 1 2 . 1 .
, t h e v a l u e of e is d e t e r m i n e d f r o m
The poles are obtained by substituting in Eq. (12.23) as
Wl
e
= 7lO ° - 1
(12.21)
•
P l >
T h e attenuation achieved b y t h e C h e b y s h e v filter at t h e s t o p b a n d e d g e (co = co ) is found
P
P ,p
s
2
u s i n g E q . ( 1 2 . 1 9 ) as A(co )
2
_ 1
= 10 l o g f l + e c o s h ( r V c o s h ( f f l / e ) ) ) ]
s
(12.22)
p
= o ( - 0 . 0 8 9 5 ± 70.9901) p
=
4
P 2
s
s
fl) (-0.2342±j0.6119) p
= ^(-0.2895)
fci - T h e transfer function is obtained by substituting these values in Eq. (12.24) as
W i t h t h e a i d of a calculator this e q u a t i o n c a n b e used t o d e t e r m i n e the order N required to obtain a specified A
m i n
m a g n i t u d e function t o a p p r o a c h t h e ideal b r i c k - w a l l l o w - p a s s r e s p o n s e . T h e p o l e s of t h e C h e b y s h e v filter a r e g i v e n b y
k
-
=
s
in t h e c a s e of t h e B u t t e r w o r t h filter, i n c r e a s i n g t h e order N of t h e C h e b y s h e v filter causes its
P
T(s)
b y finding t h e l o w e s t i n t e g e r v a l u e of N that yields A(co ) > A ^ . As
LOpSUl^
2J
N
KM
(12.23)
€
- ^ c o s ^ g c o s h ^ s i n h -
1
I
: 8 . 1 4 0 8 ( 5 + 0.2895
^ ftjji/+ s0.4684
2
+ 0.4293© ,)
(1225)
2
5 + 5 0 . 1 7 8 9 ^ + 0 . 9 8 8 3 cop where co = 2K X 10 rad/s. p
EXERCISES
k=l,2,...,N
! )
| "
F i n a l l y , t h e transfer function of t h e C h e b y s h e v filter c a n b e w r i t t e n as
D12.6 Determine the order N of a Butterworth filter for which A = 1 d B , co/co„ = 1.5 . and A = 30 dB. What is the actual value of minimum stopband attenuation realized? If A „ is to be exactly 30 d B . to what value can A, be reduced? m a x
min
rli
T
(
s
)
(12.24)
=
11JK
Ans. \ - I I : \ N
e2
\s-p )(s-p ) l
2
•••
w h e r e K is t h e d c gain that t h e filter is r e q u i r e d t o h a v e .
(S-PN)
- -:>"dB:U.5l
1097
1098
12.7:
£_L.i
CHAPTER 12 FILTERS AND TUNED AMPLIFIERS
Find the natural m o d e s and the transfer function of a Butterworth filter with co = 1 rad/s, A ( e = 1). and,V---.3. ' p
Ans. - 0 . 5
maK
= 3 dB
:
x jJi/2
and •- 1; 7i.v) = 1 / (,v i- 1)(,v -i- ,v i 1)
12.8 Observe that Eq. (12.18) can be used to find the frequencies in the passband at which\T\ is at its peaks and at its valleys. (The peaks are reached when the c o s t ' ] term is zero, and the valleys correspond to the cos'f 1 term equal to unity.) Find these frequencies for a fifth-order filler. Ans. Peaks at w-0, 0.59a),, and 0.95u) : the valleys at ft)- 0.31ft).,and 0.81ft) D12.9 Find the attenuation provided at ft) = 2co by a seventh-order Chebyshev filter with a 0.5-dB passband ripple. If the passband ripple is allowed lo increase to 1 d B , by how much does the stopband attenuation increase? ()
H
p
Ans. o k ' ) dIJ: 5.3 dli #12*10 It is required to design a low-pass filter having f = I kHz, A = 1 dB,/,, - 1.5 kHz, A = 50 dB. (a) Find the required order of a Chebyshev filter. What is the excess stopband attenuation obtained? •• (b) Repeat for a Butterworth filter. • v
milx
mil!
Ans. (a) N= 8, 5 d B : (b) N= 16, 0.5 dB
12.4 FIRST-ORDER AND SECOND-ORDER A * FILTER FUNCTIONS In this section, w e shall study the simplest filter transfer functions, those of first and second order. T h e s e functions are useful in their o w n right in the design of simple filters. First- and s e c o n d - o r d e r filters can also b e c a s c a d e d to realize a h i g h - o r d e r filter. C a s c a d e design is in fact o n e of the m o s t p o p u l a r m e t h o d s for the design of active filters (those utilizing op amps and R C circuits). B e c a u s e t h e filter poles occur in c o m p l e x - c o n j u g a t e pairs, a high-order transfer function T(s) is factored into the p r o d u c t of second-order functions. If T(s) is odd, there will also b e a first-order function in the factorization. E a c h of the second-order func tions [and the first-order function w h e n T(s) is odd] is then realized u s i n g one of the o p a m p - R C circuits that will b e studied in this chapter, and t h e resulting blocks are placed in c a s c a d e . If t h e output of each b l o c k is t a k e n at t h e output terminal of an o p a m p w h e r e the i m p e d a n c e level is l o w (ideally zero), cascading does n o t c h a n g e t h e transfer functions of the individual blocks. T h u s t h e overall transfer function of t h e c a s c a d e is simply t h e product of t h e transfer functions of t h e individual b l o c k s , w h i c h is the original T(s).
12.4.1 First-Order Filters T h e general first-order transfer function is g i v e n b y fl,£+flo
=
(
1
Z
2
6
)
S + C0
Q
T h i s b i l i n e a r t r a n s f e r f u n c t i o n c h a r a c t e r i z e s a f i r s t - o r d e r filter w i t h a n a t u r a l m o d e at s = -ft) , a transmission zero at s - -a /a and a high-frequency gain that approaches
0
0
u
lt
1 0 9 9
12.4
FIRST-ORDER AND SECOND-ORDER FILTER FUNCTIONS
< 1
.
A n i m p o r t a n t special c a s e of t h e first-order filter function is the all-pass filter s h o w n in Fig. 12.14. H e r e , t h e t r a n s m i s s i o n zero and the natural m o d e are symmetrically located rela tive to t h e jco axis. ( T h e y are said to display m i r r o r - i m a g e s y m m e t r y with r e s p e c t to t h e jco axis.) O b s e r v e that a l t h o u g h t h e t r a n s m i s s i o n of t h e all-pass filter is (ideally) c o n s t a n t at all f r e q u e n c i e s , its p h a s e s h o w s frequency selectivity. A l l - p a s s filters are u s e d as p h a s e shifters a n d in s y s t e m s that r e q u i r e p h a s e s h a p i n g (e.g., in t h e d e s i g n of circuits c a l l e d delay equalizers,
w h i c h c a u s e t h e overall t i m e delay of a t r a n s m i s s i o n s y s t e m to be c o n s t a n t
with f r e q u e n c y ) .
EXERCISES •
«
•
•
•
•
H
H
I
A
H
R
A
N
N
A
B
A
H
N
N
B
H
I
N
I
H
N
B
A
N
H
N
I
-M
012.11 Using = 10 kil, design the op a m p - R G circuit of Fig. 12.13(b) lo realize a high-pass filter with a cor nel" frequency of I 0 rad/s and a high-frequency gain of 10. 4
Ans. A' • Hid M i : (
<>.(.| ,u\
:
012.12 Design the op a m p - R C circuit of Fig. 12.14 to realize an all-pass filter with a 90° phase shift at Kf rad/s. Select suitable component values. Ans. Possible choices: l< • A ! , - R = \ 0 kQ; C = 0.1 uF 2
12.4.2 Second-Order Filter Functions T h e g e n e r a l s e c o n d - o r d e r (or b i q u a d r a t i c ) filter transfer function is usually e x p r e s s e d in t h e standard f o r m as 2
T(s)--
+a,s
+ ao (co /Q)s+(ol
2
s +
(12.27)
0
w h e r e co and Q d e t e r m i n e the natural m o d e s (poles) a c c o r d i n g to 0
Pi, Pi
(12.28)
2
-JC0
{
(l/4ß )
~2Q
W e are usually interested in the case of complex-conjugate natural m o d e s , obtained for Q > 0.5. Figure 12.15 s h o w s the location of the pair of complex-conjugate poles in the 5 plane. O b s e r v e that t h e r a d i a l distance of t h e natural m o d e s (from the origin) is e q u a l to cv , w h i c h is k n o w n 0
JOJ,v
W
k 0
5 plane
a
<»a\ 2QI X
F I G U R E 1 2 . 1 5 Definition of the parameters cut, and Q of a pair of complex-conjugate poles.
1 10 2
¿^3
CHAPTER 12 FILTERS AND TUNED AMPLIFIERS as t h e p o l e f r e q u e n c y . T h e p a r a m e t e r Q determines the distance of t h e poles from the jco axis: t h e h i g h e r the value of Q, the closer the poles are to the jco axis, a n d t h e m o r e selective the filter r e s p o n s e b e c o m e s . A n infinite v a l u e for Q locates the poles o n the jco axis and can yield sustained oscillations in t h e circuit realization. A negative v a l u e of Q implies that the poles are in the right half of the s plane, w h i c h certainly produces oscillations. T h e parameter Q is called t h e p o l e quality factor, or simply, p o l e Q. T h e transmission zeros of t h e second-order filter are determined b y the n u m e r a t o r coefficients, a , a a n d a . It follows that t h e n u m e r a t o r coefficients d e t e r m i n e t h e type of s e c o n d - o r d e r filter function (i.e., L P , H P , etc.). S e v e n special cases of interest are illustrated in F i g . 12.16. F o r e a c h case w e give the transfer function, t h e s-plane locations of the transfer-function singularities, a n d t h e m a g n i t u d e response. Circuit realizations for t h e various second-order filter functions will b e given in s u b s e q u e n t sections. 0
u
2
All seven special second-order filters h a v e a pair of c o m p l e x - c o n j u g a t e natural m o d e s characterized b y a frequency co a n d a quality factor, Q. 0
In t h e l o w - p a s s ( L P ) c a s e , s h o w n in F i g . 1 2 . 1 6 ( a ) , t h e t w o t r a n s m i s s i o n z e r o s are at s = oo. T h e m a g n i t u d e r e s p o n s e c a n exhibit a p e a k w i t h t h e details indicated. It c a n b e s h o w n that t h e p e a k occurs only for Q > l/Jl. T h e r e s p o n s e obtained for Q = is the B u t t e r w o r t h , or m a x i m a l l y flat, response. T h e high-pass (HP) function shown in Fig. 12.16(b) has both transmission zeros at s = 0 (dc). T h e m a g n i t u d e r e s p o n s e shows a p e a k for Q > 1/J2, w i t h the details of t h e r e s p o n s e as indicated. O b s e r v e t h e duality b e t w e e n the L P a n d H P responses. N e x t consider the bandpass (BP) filter function shown in Fig. 12.16(c). Here, o n e transmission zero is at s = 0 (dc), and the other is at s = °°. T h e m a g n i t u d e r e s p o n s e p e a k s at co = co . T h u s the c e n t e r f r e q u e n c y of the b a n d p a s s filter is equal to the pole frequency C0Q. T h e selectivity of t h e second-order bandpass fdter is usually measured by its 3-dB bandwidth. This is the difference b e t w e e n the t w o frequencies o>i a n d at w h i c h t h e m a g n i t u d e response is 3 d B b e l o w its m a x i m u m value (at <%). It c a n b e s h o w n that 0
co co = coJ{ h
+ (l/4Q ) 2
2
± ^
(12.29) -
Thus,
BW=co -co 2
= co /Q
x
Q
(12.30)
O b s e r v e that as Q increases, the b a n d w i d t h decreases a n d the b a n d p a s s filter b e c o m e s m o r e selective. If t h e transmission zeros are located o n t h e jco axis, at t h e c o m p l e x - c o n j u g a t e locations ±jcon, t h e n t h e m a g n i t u d e r e s p o n s e exhibits zero transmission at co= con. T h u s a n o t c h in the m a g n i t u d e r e s p o n s e occurs at co= co„, a n d co is k n o w n as t h e n o t c h f r e q u e n c y . T h r e e cases of t h e s e c o n d - o r d e r n o t c h filter a r e p o s s i b l e : t h e r e g u l a r n o t c h , o b t a i n e d w h e n co„ = co (Fig. 12.16d); t h e l o w - p a s s notch, obtained w h e n co > c% (Fig. 12.16e); a n d t h e high-pass notch, obtained w h e n co < COQ (Fig. 12.16f). T h e reader is u r g e d to verify the response details given in these figures (a rather tedious task, t h o u g h ! ) . O b s e r v e that in all notch cases, the transmission at d c a n d at s = °° is finite. T h i s is so b e c a u s e there are n o transmission zeros at either s = 0 or s = °°. T h e last special case of interest is the all-pass ( A P ) filter w h o s e characteristics are illustrated in Fig. 12.16(g). H e r e the t w o transmission zeros are in the right half of t h e s plane, at the m i r r o r - i m a g e locations of t h e p o l e s . (This is the c a s e for all-pass functions of any order.) T h e m a g n i t u d e r e s p o n s e of the all-pass function is constant over all frequencies; the flat gain, as it is called, is in our case equal to \a \. T h e frequency selectivity of t h e all-pass function is in its p h a s e response. n
Q
n
n
2
11 0 3
Filter Type and T(s)
s-Plane Singularities
\T\
(d) Notch
1
X \
s +CO,
T(s) = a 2
m
0
,
,
WO I
\
2
2
\
I
0
DC gain = High-frequency gain = a
2
0
2Q
X
0-
(e) Low-pass notch (LPN)
S
T(s) = a
2 ,
1
2
+ ftL
2
2
f
t
2
co >co n
0
0
I
2
DC gain = a - 2 2
COQ_
High-frequency gain = a
2
X 22 0-
(f ) High-pass notch (HPN)
S
T(s) = a
2 ,
X V)
0-
2
+ ftL
2
0
\ co„ DCgain=a -» COn High-frequency gain = a
~k
0
l«2l
j
2
2
FIGURE 1 2 . 1 6
(Continued)
FIGURE 1 2 . 1 6 (Continued)
22 X
I
Jf
11
CHAPTER 12
06
FILTERS A N D T U N E D
12.5
AMPLIFIERS
T H ES E C O N D - O R D E R
LCRRESONATOR
is excited with a current s o u r c e I c o n n e c t e d in parallel. Since, as far as t h e natural r e s p o n s e of a circuit is c o n c e r n e d , an i n d e p e n d e n t ideal current source is equivalent to an o p e n circuit, the excitation o f Fig. 12.17(b) d o e s n o t alter the natural structure of t h e resonator. T h u s t h e 12.13 For a maximally Flat second-order low-pass filter (Q response is 3 dB below the value at dc.
\/fl). . ..
show that at ft) = COQ the magnitude ..
circuit in Fig. 12.17(b) c a n b e u s e d to d e t e r m i n e the natural m o d e s of the resonator b y simply finding t h e p o l e s of a n y r e s p o n s e function. W e c a n for instance t a k e t h e v o l t a g e V across 0
the r e s o n a t o r as t h e r e s p o n s e a n d thus obtain t h e r e s p o n s e function V /I
5
12.14 Give the transfer function of a second-order bandpass filter with a center frequency of 1 0 rad/s, a center-frequency gain of 10, and a 3-dB bandwidth of 1 0 rad/s.
0
= Z , w h e r e Z is
the i m p e d a n c e of t h e parallel r e s o n a n c e circuit. It is o b v i o u s l y m o r e c o n v e n i e n t , h o w e v e r , to
3
w o r k in t e r m s of t h e a d m i t t a n c e Y; thus,
.r(5)'=
Am
s' + 10 .v • 10 12.15 (a) F o r the second-order notch function with o>„ = ( % show that for the attenuation to be greater tharr; A dB over a frequency band BW , the value of Q is given by
Y
1 (l/sL)
+
2
s + s(l/CR) /
l
0
sC+(l/R)
' s/C
_
(On A
1
1
0
a
B w J w
V
(12.31) +
- \
(l/LC)
2 0
(Hint: First, show that any two frequencies, ft)i and ah, a t which | T\ is the same, are related b y co co <3)Q.) (b) U s e the result of (a) to show that the 3-dB bandwidth is ft) /ß, as indicated in Fig. 12.16(d). x
2
E q u a t i n g the d e n o m i n a t o r t o the standard form [s + s(co /Q)
+ a> ] leads to 0
2
co\=\/LC
0
12.16 Consider a low-pass notch with co = 1 rad/s, Q = 10, co„ = 1.2 rad/s, and a d c gain of unity. Find t h e frequency and magnitude of the transmission peak. Also find the high-frequency transmission.
(12.32)
and
0
(O /Q=l/CR
Ans. 0.986 rad/s; 3. ¡7: 0.69
(12.33)
0
Thus, (O =l/JLC
(12.34)
0
t 12.5
THE SECOND-ORDER LCR RESONATOR
Q = co CR
(12.35)
0
In this section w e shall study t h e s e c o n d - o r d e r L C R r e s o n a t o r s h o w n in F i g . 12.17(a). T h e
T h e s e e x p r e s s i o n s should b e familiar to t h e r e a d e r from studies of parallel r e s o n a n c e circuits
use of this resonator to derive circuit realizations for the various second-order filter functions
in introductory c o u r s e s o n circuit theory.
will b e d e m o n s t r a t e d . It will b e s h o w n in t h e n e x t section that r e p l a c i n g the i n d u c t o r L b y a
A n alternative w a y of exciting t h e parallel L C R r e s o n a t o r for the p u r p o s e of d e t e r m i n i n g
simulated inductance obtained using an o p a m p - R C circuit results in an o p a m p - R C resonator.
its natural m o d e s is shown in Fig. 12.17(c). Here, n o d e x of inductor L h a s b e e n disconnected
T h e latter forms the basis of an important class of active-RC filters to b e studied in Section 12.6.
from g r o u n d a n d c o n n e c t e d to a n ideal v o l t a g e s o u r c e V . N o w , since a s far a s t h e natural t
r e s p o n s e of a circuit is c o n c e r n e d , a n ideal i n d e p e n d e n t v o l t a g e s o u r c e is equivalent to a
12.5.1 The Resonator Natural Modes
short circuit, t h e excitation of Fig. 12.17(c) d o e s n o t alter t h e natural structure of t h e r e s -
T h e n a t u r a l m o d e s of t h e parallel r e s o n a n c e circuit of F i g . 12.17(a) c a n b e d e t e r m i n e d b y
onator. T h u s w e c a n u s e t h e circuit in Fig. 12.17(c) to d e t e r m i n e t h e natural m o d e s of t h e
applying an excitation
resonator. T h e s e a r e t h e p o l e s of a n y r e s p o n s e function. F o r instance, w e c a n select V as
that does not change
the natural
structure
of the circuit. T w o possible
w a y s of exciting the circuit are s h o w n in Fig. 12.17(b) a n d (c). I n F i g . 12.17(b) t h e r e s o n a t o r
0
the r e s p o n s e variable a n d find the transfer function V /V . 0
i
T h e r e a d e r c a n easily verify that
this will lead t o the natural m o d e s d e t e r m i n e d earlier. In a d e s i g n p r o b l e m , w e will b e given C0Q a n d Q a n d will b e asked to d e t e r m i n e L, C, -o +
a n d R. E q u a t i o n s (12.34) a n d (12.35) a r e t w o e q u a t i o n s in t h e three u n k n o w n s . T h e o n e available degree-of-freedom c a n b e utilized t o set t h e i m p e d a n c e , level of t h e circuit to a v a l u e that results in practical c o m p o n e n t v a l u e s .
V
12.5.2 Realization of Transmission Zeros H a v i n g selected the component values of the L C R resonator t o realize a given pair of complexconjugate natural m o d e s , w e n o w consider the u s e of the r e s o n a t o r t o realize a desired filter (a)
(b)
(c)
t y p e (e.g., L P , H P , etc.). Specifically, w e w i s h to find o u t w h e r e to inject t h e i n p u t v o l t a g e
FIGURE 1 2 . 1 7 (a) The second-order parallel LCR resonator, (b, c) Two ways of exciting the resonator of (a) without changing its natural structure: resonator poles are those poles of V /I and V /V . a
0
i
signal Vj s o that the transfer function V / V,- is the desired o n e . T o w a r d that end, note that in 0
the r e s o n a t o r circuit in Fig. 12.17(a), a n y of the n o d e s labeled x, y, or z c a n b e d i s c o n n e c t e d
1107
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
from g r o u n d a n d c o n n e c t e d to Vj- w i t h o u t altering t h e c i r c u i t ' s natural m o d e s . W h e n this is
c:
RZ
d o n e the circuit takes the f o r m of a v o l t a g e divider, as s h o w n in Fig. 12.18(a). T h u s the transfer function realized is
Afl,\
T(s) Yg\ = V (s)
= Z (s) 7 +
t
1
(12-36)
Z (s)
(b)LP
2
(a) General structure W e o b s e r v e that the transmission Z (s) is not simultaneously is not simultaneously
zeros are the values of s at which Z (s)
is zero,
2
zero, and the values ofs at which Z (s)
x
is infinite, provided
x
provided Z (s) 2
z
R
- O - W r
C
-o +
infinite. This statement m a k e s p h y s i c a l sense: T h e output will b e zero
either w h e n Z (s) b e h a v e s as a short circuit or w h e n Z (s) b e h a v e s as an o p e n circuit. If there 2
x
C:
is a v a l u e of s at w h i c h b o t h Z a n d Z are z e r o , t h e n V / V will b e finite a n d n o transmission x
2
0
L
zero is obtained. Similarly, if there is a v a l u e of s at w h i c h both Z a n d Z are infinite, then x
V„/V
;
2
will b e finite a n d n o t r a n s m i s s i o n z e r o is realized. (d) BP
12.5.3 Realization of the Low-Pass Function x
U s i n g the s c h e m e j u s t outlined w e see that to realize a l o w - p a s s function, n o d e x is dis-
L
i
connected f r o m g r o u n d and c o n n e c t e d to V , as s h o w n in Fig. 12.18(b). T h e transmission t
zeros of this circuit will b e at the value of 5 for w h i c h the series i m p e d a n c e b e c o m e s infinite (sL b e c o m e s infinite at s - °°) a n d the v a l u e of s at w h i c h the shunt i m p e d a n c e b e c o m e s zero (l/[sC
+ (1/R)]
+
y
b e c o m e s zero at s = °°). T h u s this circuit h a s t w o t r a n s m i s s i o n zeros
R
¿2
v„
at s = °°, as a n L P is s u p p o s e d to. T h e transfer function c a n b e written either b y inspection or b y u s i n g the voltage-divider rule. F o l l o w i n g the latter a p p r o a c h , w e obtain -o T(s)
=
V
0
Vf
_
Z
_
2
t
Z,+Z
Y, + Y
0
1
1/sL
Y
(l/sL)
2
2
1
+
sC+(l/R)
2
(f) General notch
(12.37)
1/LC 2
s + s{l/CR)
+
(l/LC)
12.5.4 Realization of the High-Pass Function T o realize the s e c o n d - o r d e r h i g h - p a s s function, n o d e y is d i s c o n n e c t e d from g r o u n d and connected to V , as s h o w n in Fig. 12.18(c). H e r e the series capacitor introduces a transmission ;
zero at s = 0 (dc), a n d the shunt i n d u c t o r i n t r o d u c e s a n o t h e r t r a n s m i s s i o n zero at s = 0 (dc). T h u s , b y inspection, the transfer function m a y b e w r i t t e n as v T(s) = 12. = 2l£ i s +s(co /Q) v
0
2
. + co
(12.38)
0
w h e r e CVQ a n d Q are t h e natural m o d e p a r a m e t e r s g i v e n b y E q s . (12.34) a n d (12.35) a n d a is 2
the h i g h - f r e q u e n c y transmission. T h e v a l u e of a
2
c a n b e d e t e r m i n e d from t h e circuit by
(g)
LPN (co > co ) n
0
o b s e r v i n g that as s a p p r o a c h e s °°, t h e c a p a c i t o r a p p r o a c h e s a short circuit a n d V a p p r o a c h e s 0
V , resulting in a = 1. t
2
12.5.5 Realization of the Bandpass Function
( i ) HPN (o>„ < w ) 0
T h e b a n d p a s s function is realized b y d i s c o n n e c t i n g n o d e z from g r o u n d and c o n n e c t i n g it to V
b
as s h o w n in Fig. 12.18(d). H e r e the series i m p e d a n c e is resistive a n d thus d o e s not
i n t r o d u c e a n y t r a n s m i s s i o n zeros. T h e s e are o b t a i n e d as follows: O n e zero at s = 0 is
FIGURE 1 2 . 1 8 Realization of various second-order filter functions using the LCR resonator of Fig. 12.17(b): (a) general structure, (b) LP, (c) HP, (d) BP, (e) notch at <% (f) general notch, (g) LPN (co > co ), (h) LPN as s -> ~ , (i) HPN (a < co ). n
0
n
0
1 1
0 9
1110
.'
CHAPTER 12
FILTERS AND TUNED AMPLIFIERS
12.5
realized b y t h e shunt inductor, and o n e z e r o at 5 = <» is realized b y the shunt capacitor. A t
THE SECOND-ORDER LCR RESONATOR
and thus
the center frequency C0Q, the parallel L C - t u n e d circuit exhibits an infinite ^ p p e d a n c e , and *
t h u s n o c u r r e n t f l o w s in t h e circuit. It f o l l o w s that at 0 = C0Q, V = V . In o t h e r w o r d s , the 0
center-frequency gain of t h e b a n d p a s s filter is unity. Its transfer function c a n b e obtained as follows:
_
YR
T(s)
L
X
X
(l/R)
C
+ (l/sL)
X
2
V
V
T(s)= f
+ sC
2
(
s(l/CR) +
1
1
3
9
x
2
s + co °" s + s(co /Q) + co S
= a
2
+
C
(12.44)
i
2
i
s + s(l/CR)
2
2
y
2
+ C)
X
This condition can b e satisfied with L eliminated (i.e., L = °° and L = L), resulting in the L P N circuit in F i g . 12.18(g). T h e transfer function c a n b e written b y inspection as
l/R
Y +Y +Y R
L C <(L \\L )(C
t
2
0
0
)
(l/LQ
2
2
where co„ = 1/LC ,
co -
X
1/L(C
0
+ C ),
X
co /Q
2
= l/CR,
0
gain. F r o m the circuit w e see that as 5 —>
and a
2
is the high-frequency
the circuit r e d u c e s to that in F i g . 12.18(h), for
which
12.5.6 Realization of the Notch Functions
Yo_
T o o b t a i n a pair of t r a n s m i s s i o n z e r o s o n t h e jco axis w e u s e a parallel r e s o n a n c e circuit in t h e series a r m , as s h o w n in F i g . 1 2 . 1 8 ( e ) . O b s e r v e that this circuit is o b t a i n e d b y
c
=
x
V
C + C
t
Thus
x
2
d i s c o n n e c t i n g b o t h n o d e s x a n d y f r o m g r o u n d a n d c o n n e c t i n g t h e m t o g e t h e r to V,-. T h e i m p e d a n c e of t h e L C circuit b e c o m e s infinite at co = co = l/jLC, 0
thus causing zero trans-
a2
( 1 2
= c^c
2
'
4 5 )
m i s s i o n at this f r e q u e n c y . T h e s h u n t i m p e d a n c e is r e s i s t i v e a n d t h u s d o e s n o t i n t r o d u c e t r a n s m i s s i o n zeros. It follows that t h e circuit in F i g . 12.18(e) will realize t h e n o t c h transfer
T o obtain an H P N realization w e start with the circuit of F i g . 12.18(f) and u s e t h e fact that co < co to obtain
function
n
0
LC> X
T{s)
= a
s2+C
2
°"° s + s(co /Q)
(12.40)
l
0
(L \\L )(C
X
X
2
+ C)
X
2
which c a n b e satisfied w h i l e selecting C = 0 (i.e., C = C). T h u s w e obtain t h e r e d u c e d 2
+ co
0
x
circuit s h o w n in F i g . 12.18(i). O b s e r v e that as 5 — > ° ° , V a p p r o a c h e s V,- and thus the high0
frequency gain is unity. T h u s , the transfer function c a n be e x p r e s s e d as
T h e v a l u e of t h e high-frequency gain a c a n b e found from t h e circuit to b e unity. 2
T o obtain a notch-filter realization in w h i c h the n o t c h frequency co„ is arbitrarily placed relative to co , w e a d o p t a variation o n t h e s c h e m e a b o v e . W e still u s e a parallel L C circuit in
7X5)
0
^
s
v
t h e series b r a n c h , as s h o w n in Fig. 12.18(f) w h e r e L and C are selected so that x
LC X
Thus the L C X
X
x
= \/co\
X
(12.41)
t a n k circuit will i n t r o d u c e a pair of t r a n s m i s s i o n zeros at ±jco , n
the L2C2 t a n k is not r e s o n a n t at co . A p a r t from this restriction, the values of ¿ 2 n
provided ar
>d
(
1
/
L
C
)
(12.46)
2
T h e all-pass transfer function
C
2
2
= ° -
+ °\
5 +s(co /Q)
( 1 2
.
4 7 )
+ co
0
(12.42)
2
+
1
T(s)
C + C = C
/
* 5 + 5 ( 1 / C 7 v ) + [1/(L II L ) C ]
12.5.7 Realization of the All-Pass Function
m u s t b e selected to e n s u r e that the natural m o d e s h a v e not b e e n altered; thus, x
= i
0
can b e written as L \\L X
=L
2
(12.43)
In other w o r d s , w h e n V is r e p l a c e d b y a short circuit, t h e circuit should r e d u c e to the
7X5) = 1 -
;
S
2
/
^ 5 +s(co /Q)
Q
)
2
original L C R resonator. A n o t h e r w a y of t h i n k i n g a b o u t t h e circuit of F i g . 12.18(f) is that
(12.48)
2
+ G)
0
0
it is obtained from the original L C R r e s o n a t o r b y lifting part of L and part of C off g r o u n d
The second t e r m on t h e right-hand side is a b a n d p a s s function with a center-frequency gain
a n d c o n n e c t i n g t h e m to V .
of 2. W e already h a v e a b a n d p a s s circuit (Fig. 12.18d) b u t with a center-frequency gain of
;
It s h o u l d b e n o t e d that in t h e c i r c u i t of F i g . 1 2 . 1 8 ( f ) , L
2
5 = 0 b e c a u s e at 5 = 0, the L C X
d o e s not i n t r o d u c e a z e r o at
unity. W e shall therefore a t t e m p t an all-pass realization with a flat gain of 0.5, that is,
circuit also h a s a zero. In fact, at 5 = 0 t h e circuit r e d u c e s
X
to an i n d u c t i v e voltage divider w i t h t h e d c t r a n s m i s s i o n b e i n g L /(L 2
x
+ L ). 2
Similar
c o m m e n t s c a n b e m a d e a b o u t C a n d t h e fact that it does not i n t r o d u c e a z e r o at 5 = ° ° . 2
7X5) = 0.5
S
{
C
°° s + s(co /Q) 2
Q
/
Q
)
2
+ co
0
T h e L P N a n d H P N filter realizations are special c a s e s of t h e g e n e r a l n o t c h circuit of This function c a n b e r e a l i z e d u s i n g a v o l t a g e divider w i t h a t r a n s m i s s i o n ratio of 0.5
F i g . 1 2 . 1 8 ( f ) . Specifically, for the L P N ,
together with the b a n d p a s s circuit of Fig. 12.18(d). T o effect the subtraction, the output of cv >co n
0
the all-pass circuit is taken b e t w e e n the output t e r m i n a l of the voltage divider and that of the
1112
I-
v
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
©
-o
12.6
S E C O N D - O R D E R ACTIVE FILTERS B A S E D O N I N D U C T O R
REPLACEMENT
V„o-
C:
FIGURE 1 2 . 1 9 Realization of the second-order all-pass transfer function using a voltage divider and an LCR resonator.
F T
b a n d p a s s filter, as s h o w n in F i g . 12.19. U n f o r t u n a t e l y this circuit h a s t h e d i s a d v a n t a g e of lacking a c o m m o n g r o u n d t e r m i n a l b e t w e e n t h e i n p u t a n d t h e output. A n o p a m p - R C realization of t h e all-pass function will b e p r e s e n t e d in t h e n e x t section.
Zm = y
=
sCtRfoRs/R.
(a)
EXERCISES 12.17 Use the circuit of Fig. 12.18(b) to realize a second-order low-pass function of the maximally flat type will) a 3-d U iivi]iiciic\ i i f Kill kHz. Ans. Selecting R = 1 k Q , we obtain C = 1125 pF and /. = 2.25 mH. 12.18 Use the circuit of Fig. 12.18(e) to design a notch filter to eliminate a bothersome power-supply hum at a 60-Hz frequency. T h e filter is to have a 3 - d B bandwidth of 10 Hz ( i . e . j A e attenuation is greater than 3 dB over a 10-Hz band around the 60-Hz center frequency; see Lxercise 12.15 and Fig. 12.16d). Use R - 10 ki>. Ans. C = 1.6 /JF and L = 4.42 H (Note.:the large inductor required. This is the reason passive filters are not practical in low-frequency applications.)
,'
r
12.6 SECOND-ORDER ACTIVE FILTERS BASED ON INDUCTOR REPLACEMENT
In this section, w e study a family of o p a m p - R C circuits that realize t h e various second-order filter functions. T h e circuits are b a s e d o n a n o p a m p - R C r e s o n a t o r o b t a i n e d b y r e p l a c i n g t h e
Z¡„ = y± = sCiR^Rs/Rz
(g (b)
i n d u c t o r L in t h e L C R r e s o n a t o r with a n o p a m p - R C circuit that h a s a n i n d u c t i v e input impedance.
FIGURE 1 2 . 2 0 (a) The Antoniou inductance-simulation circuit, (b) Analysis of the circuit assuming ideal op amps. The order of the analysis steps is indicated by the circled numbers.
12.6.1 The Antoniou Inductance-Simulation Circuit O v e r t h e y e a r s , m a n y op a m p - R C circuits h a v e b e e n p r o p o s e d for simulating t h e operation of an inductor. Of these, o n e circuit i n v e n t e d b y A . A n t o n i o u
5
op a m p s t h e i n p u t i m p e d a n c e can b e s h o w n t o b e
[see A n t o n i o u ( 1 9 6 9 ) ] h a s z
p r o v e d to b e t h e " b e s t . " B y " b e s t " w e m e a n that t h e operation of t h e circuit is v e r y tolerant of t h e n o n i d e a l properties of t h e o p a m p s , in particular their finite gain a n d b a n d w i d t h .
=sC R R R /R
i n = Vi/h
4
1
3
5
2
(12.49)
which is that of an i n d u c t a n c e L given b y
F i g u r e 12.20(a) s h o w s t h e A n t o n i o u i n d u c t a n c e - s i m u l a t i o n circuit. If t h e circuit is fed at its i n p u t (node 1) w i t h a v o l t a g e source V a n d t h e input current is d e n o t e d I x
u
t h e n for ideal
L
~
C R R R^/Rr, 4
X
3
(12.50)
F i g u r e 12.20(b) s h o w s t h e analysis of t h e circuit a s s u m i n g that the o p a m p s are ideal a n d 5
Andreas Antoniou is a Canadian academic, currently (2003) a member of the faculty of the University of Victoria, British Columbia.
thus that a virtual short circuit appears b e t w e e n t h e t w o input terminals of e a c h o p a m p , a n d a s s u m i n g also that t h e input currents of the o p a m p s are zero. T h e analysis b e g i n s at n o d e 1,
I
1 1 1 3
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
2.6
w h i c h is a s s u m e d to b e fed b y a voltage s o u r c e V
S E C O N D - O R D E R ACTIVE FILTERS B A S E D O N I N D U C T O R R E P L A C E M E N T
and p r o c e e d s step b y step, with the order
h
of t h e steps indicated b y the circled n u m b e r s . T h e result of the analysis is the expression s h o w n for the i n p u t current 7j from w h i c h Z
i n
is found.
T h e d e s i g n of this circuit is usually b a s e d on selecting R = x
R2
R = R = R and C = C, 3
5
4
2
w h i c h leads to L = CR . C o n v e n i e n t v a l u e s are then selected for C and R to yield t h e desired i n d u c t a n c e v a l u e L. M o r e details on this circuit and the effect of the nonidealities of the o p a m p s on its p e r f o r m a n c e c a n b e found in S e d r a and Brackett (1978).
12.6.2 The Op Amp-RC Resonator F i g u r e 12.21(a) s h o w s the L C R r e s o n a t o r w e studied in detail in Section 12.5. R e p l a c i n g the i n d u c t o r L with a simulated i n d u c t a n c e realized b y the A n t o n i o u circuit of Fig. 12.20(a) results in t h e o p a m p - R C r e s o n a t o r of Fig. 12.21(b). (Ignore for the m o m e n t t h e additional amplifier d r a w n with b r o k e n lines.) T h e circuit of Fig. 12.21(b) is a s e c o n d - o r d e r resonator h a v i n g a p o l e frequency co
0
= 1/JLC
= l / J C ^ ^ R ^ / R ,
6
(12.51)
w h e r e w e h a v e u s e d the expression for L given in Eq. (12.50), and a p o l e Q factor, e
-
U s u a l l y o n e selects C = C = C and R =R 4
<
=
6
1
= R =R
2
3
i
2
5
2
)
= R, w h i c h results in
5
co =l/CR
(12.53)
0
Q = R /R
(12.54)
6
T h u s , if w e select a practically c o n v e n i e n t v a l u e for C, w e can u s e E q . (12.53) to d e t e r m i n e the v a l u e of R to realize a given co , and t h e n u s e E q . (12.54) to d e t e r m i n e t h e v a l u e of R to 0
6
realize a given Q.
r
2
12.6.3 Realization of the Various Filter Types T h e o p a m p - R C resonator of F i g . 12.21(b) c a n b e u s e d to generate circuit realizations for t h e v a r i o u s s e c o n d - o r d e r filter functions b y following the a p p r o a c h d e s c r i b e d in detail in Section 12.5 in c o n n e c t i o n with the L C R r e s o n a t o r . T h u s to obtain a b a n d p a s s function w e d i s c o n n e c t n o d e z from g r o u n d a n d c o n n e c t it to t h e signal s o u r c e V;. A h i g h - p a s s function is obtained b y injecting V to n o d e y. T o realize a l o w - p a s s function u s i n g the L C R resonator, t
the inductor terminal x is d i s c o n n e c t e d from g r o u n d and c o n n e c t e d to V> T h e c o r r e s p o n d i n g 6
n o d e in the active resonator is the n o d e at w h i c h R is c o n n e c t e d to g r o u n d , labeled as n o d e
FIGURE 1 2 . 2 1 (a) An LCR resonator, (b) An op amp-RC resonator obtained by replacing the inductor L in the LCR resonator of (a) with a simulated inductance realized by the Antoniou circuit of Fig. 12.20(a). (c) Implementation of the buffer amplifier K.
5
x in F i g . 12.21(b). A regular n o t c h function (co = ft) ) is obtained b y feeding V to n o d e s x n
0
t
a n d y. In all cases the output c a n b e t a k e n as t h e voltage across the r e s o n a n c e circuit, V . r
H o w e v e r , this is not a convenient n o d e to u s e as the filter output terminal b e c a u s e connecting a
F i g u r e 12.21(c) s h o w s h o w this amplifier c a n b e s i m p l y i m p l e m e n t e d u s i n g an o p a m p
load there w o u l d change the filter characteristics. T h e p r o b l e m can b e solved easily b y utiliz
c o n n e c t e d in the n o n i n v e r t i n g configuration. N o t e that not only does the amplifier K buffer
ing a buffer amplifier. This is the amplifier of gain K, drawn with broken lines in Fig. 12.21(b).
the output of the filter, but it also allows the d e s i g n e r to set the filter gain to a n y desired value b y appropriately selecting the v a l u e of K.
6
T h i s point might not be obvious! The reader, however, can show that when Vj is fed to this node the function V*/Vj is indeed low pass. r
F i g u r e 12.22 s h o w s the various s e c o n d - o r d e r filter circuits obtained from the r e s o n a t o r of Fig. 12.21(b). T h e transfer functions and d e s i g n equations for these circuits are g i v e n in
1 1 1 5
1 1 1 6
CHAPTER 1 2
FILTERS A N D T U N E D AMPLIFIERS
12.6
S E C O N D - O R D E R ACTIVE FILTERS B A S E D O N I N D U C T O R R E P L A C E M E N T
(d) Notch at co
0
(e) LPN, co„ > co
a
(C)
BP (f) HPN, co
a
FIGURE 1 2 . 2 2
0
Realizations for the various second-order filter functions using the op amp-RC resonator
of Fig. 12.21(b): (a) LP, (b) HP, (c) BP,
FIGURE 1 2 . 2 2 (Continued) (d) notch at <% (e) LPN, C0„ > co , (f) HPN, CO,, < C0 , and 0
0
¿1*
1 1 1 7
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
"\A.A
Design Data fc
= Circuits of Fig. 12.22
Circuit
Transk .-unction and Other Parameters
Resonator Fig. 12.21(b)
COQ = Q
Design Equations
C = C = C (practical value)
\/JC^C^R J ~R 7R 1
5
4
2
6
1
I
= R
3
R =R
E6
=R =
2
i
R =
Q/co C
K=DC
gain
6
y
Low-pass (LP) Fig. 12.22(a)
T(s)
4
T
3
=
2/C,CeRiR R 3
R
6
CCRRR
6
4
6
X
3
}
K = High-frequency gain
Ks'
= 1 S +SCR 6
T(s)
5
+ s-
2
Bandpass (BP) Fig. 12.22(c)
0
5
KR
C
T(s)
5
0
CRRR
S
High-pass (HP) Fig. 12.22(b)
R =l/co C
3
R
R, CCRRR
+• 6
4
6
1
3
5
Ks/C R 6
=
K = Center-frequency gain
6
R, C C RR R
2
s +s ^ - +. CR 6
6
4
6
l
3
5
(g) All-pass FIGURE 1 2 . 2 2 (Continued) (g) all pass. The circuits are based on the LCR circuits in Fig. 12.18. Design equations are given in Table 12.1.
Regular notch (N) Fig. 12.22(d) •
T(s)
_ =
R C C RR R
2
s +s ^ - +. Çè 6
2
R
T a b l e 1 2 . 1 . N o t e that the transfer functions c a n b e w r i t t e n b y a n a l o g y to t h o s e of the L C R resonator. W e h a v e already c o m m e n t e d o n t h e L P , H P , B P , a n d r e g u l a r - n o t c h circuits given
Low-pass notch (LPN) Fig. 12.22(e)
K = Low- and high-frequency gain
K[s^(R^C^C^R^s)]
4
6
l
3
s
T(s) = K Ca
CM +
in F i g . 12.22(a) to (d). T h e L P N a n d H P N circuits in F i g . 12.22(e) a n d (f) are o b t a i n e d by s +
direct a n a l o g y to their L C R counterparts in F i g . 12.18(g) a n d (i), respectively. T h e all-pass circuit in F i g . 12.22(g), h o w e v e r , d e s e r v e s s o m e explanation.
s + s-(C
61
12.6.4 The All-Pass Circuit
C0 =
A n all-pass function with a flat gain of unity c a n b e written as
C0 = l/JC (C
(R /C C R R R ) 2
1 + C )R
2 ,
62
4
6l
1
4
K=DC
5
R-> + C )i?ii? i?
C (C
6
3
62
61
3
5
l/^C C R R R /R
N
4
0
4
6l
l
3
5
+
61
Qi + Q 2
2
C )R R R /R S2
l
3
s
2
C
(12.55)
Q =
ß
c
jQi +
R RiR R
62
2
C
4
3
c =c
=
6
2
=
a
A P = 1 - ( B P with a center-frequency gain of 2)
gain
C(co /co ) n
n
Cei — C— C i 6
5
(see E q . 12.48). T w o circuits w h o s e transfer functions are related in this fashion are said to 7
b e c o m p l e m e n t a r y . T h u s the all-pass circuit w i t h unity flat gain is the c o m p l e m e n t of the b a n d p a s s circuit w i t h a center-frequency gain of 2 . A s i m p l e p r o c e d u r e exists for obtaining
High-pass notch (HPN) Fig. 12.22(f)
T(s)
s' +
= K-
(R /C C R R R ) 2
4
6
1
3
R 1 s +s - ^ - +CR C C Ä i? VÄ 2
t h e c o m p l e m e n t of a given linear circuit: D i s c o n n e c t all t h e circuit n o d e s that are c o n n e c t e d
sl
6
6
4
6
1
3
K = High-frequency gain 1
2
+ 51
R
S2
to g r o u n d a n d c o n n e c t t h e m to V , a n d d i s c o n n e c t all the n o d e s that are c o n n e c t e d to V,- and t
a circuit w h o s e transfer function is the c o m p l e m e n t of that of the original circuit.
1 ^ 1 1 — + — = — = co C
\/JC C R R R /R
co„
c o n n e c t t h e m to g r o u n d . T h a t is, i n t e r c h a n g i n g i n p u t a n d g r o u n d in a linear circuit generates
4
6
l
3
5l
n
2
0
R
1
COr, =
+
C C R\R \R 4
6
3
5l
5
1
R
with a gain of 2 b y simply selecting K = 2 and implementing the buffer amplifier with the circuit of Fig. 12.21(c) with r = r . W e then interchange input and ground and thus obtain the all-pass
c
Q = R
2
(
circuit of F i g . 12.22(g). Finally, in addition to b e i n g simple to design, the circuits in Fig. 12.22 exhibit excellent p e r f o r m a n c e . T h e y can b e u s e d o n their o w n to realize s e c o n d - o r d e r filter functions, or they c a n b e c a s c a d e d to i m p l e m e n t h i g h - o r d e r filters.
R ( l 6 C i? Ä vA 5 2
,
4
All-pass (AP) Fig. 12.22(g),,
1
3
2
T(s)
=
6
1
6
CO.
R
0)
Q
6
Z
x
2
51
=
R
52
=
R (co /co r 5
0
n
R /[l-(o} /co y] 5
n
0
R, C C RR R 4
6
l
3
s
R-> +• C+CsR&Rs
Q = Q(r /r )
R
S2
r
1 5 +s-— CR More about complementary circuits will be presented later in conjunction with Fig. 12.31.
1
2 1 r s -s^r^—+• CçR r 2
7
R
52
:
R e t u r n i n g to the p r o b l e m at h a n d , w e first u s e the circuit of Fig. 12.22(c) to realize a B P
x
R
5l
Flat gain = 1
i
=
r
2 ~
r
(arbitrary)
Adjust r to make Q, = Q 2
1 1 1 9
1120
CHAPTER 12
FILTERS A N D T U N E D
12.7
AMPLIFIERS
S E C O N D - O R D E R ACTIVE FILTERS B A S E D O N THE T W O - I N T E G R A T O R - L O O P
TOPOLOGY
•MISTS'
EXERCISES 012.19 Use the circuit of Fig. 12.22(c) to design a second-order bandpass filter w i t h a e e n t e r frequency of 10 kHz; a 3-dB bandwidth of 5 0 0 Hz. and a center-frequency gain of 10. U s c C = 1.2 nF: < Ans. A' - A' - A' - R - I3.2f> 111; l\
-
. > 5 kli: (
C. - 1.2 til : k
•
- H»kl». /•_ • '«> k«2
D12.20 Realize the Chebyshev filter of Example 12.2. whose transfer function is given in Eq. (12.25), as thescas* cade connection of uiree circuits: two of the type shown in Fig. 12.22(a) and one first-order op a m p RC circuit of the type shown in Fig. 12.13(a). Note that you can make the dc gain of all sections equal to unity. Do so. Use as many .10-kQ resistors as possible. 4
Ans. I ' i M - o l d e r * c i i n i i : A'. - A' - Id kQ. f ' - 5 . 5 i i I - _ mv«muI-i>hIci- m v i h a with to, • 4.1 F • l d r a d / s a n d ( ? = 1.4: = = 10 k Q . R„ = 14 k Q , C = C „ = 2.43 nF, =<». r = (): second-order sec tion with o) = 6.246 x 1() rad/s and Q = 5.56: R, = R = R = R = 10 k Q , R = 55.6 k Q , C =:€ M 1.6 n l . r ~ c o . r • 0 4
2
4
0
2
3
5
b
4
6
;
:
12.7 SECOND-ORDER ACTIVE FILTERS BASED ON THE TWO-INTEGRATOR-LOOP TOPOLOGY In this section, w e study a n o t h e r family of o p a m p - R C circuits that r e a l i z e s e c o n d - o r d e r filter functions. T h e circuits are b a s e d o n the u s e of t w o integrators c o n n e c t e d in c a s c a d e in an overall f e e d b a c k loop a n d are thus k n o w n as t w o - i n t e g r a t o r - l o o p circuits. "-°
12.7.1 Derivation of the Two-Integrator-Loop Biquad
^
- Vh
bp
FIGURE 1 2 . 2 3 Derivation of a block diagram realization of the two-integrator-loop biquad.
Ks
(12.56)
2
i
V
2
_
P
v
Vhp =
(c)
T o d e r i v e the t w o - i n t e g r a t o r - l o o p b i q u a d r a t i c circuit, or b i q u a d as it is c o m m o n l y k n o w n , c o n s i d e r t h e s e c o n d - o r d e r h i g h - p a s s transfer function
—
s + s(co /Q)
+ a>l
0
h p
w h e r e K is t h e high-frequency gain. C r o s s - m u l t i p l y i n g E q . (12.56) a n d dividing b o t h sides 2
of t h e resulting equation by s (to get all t h e t e r m s i n v o l v i n g s in t h e f o r m l/s,
w h i c h is the
transfer function of an integrator) gives (
2 2
\ h
In this equation w e observe that the signal ( c o / s ) V 0
(12.57)
J hp
In the realization of F i g . 12.23(c), V , o b t a i n e d at the o u t p u t of the s u m m e r , realizes t h e high-pass transfer function T = V ^ / V ; of E q . (12.56). T h e signal at the o u t p u t of the first integrator i s - ( c o / s ) V , w h i c h is a b a n d p a s s function, bp
KV;
P
S
w h i c h suggests that V c a n b e obtained b y u s i n g t h e w e i g h t e d s u m m e r of Fig. 12.23(b). N o w it s h o u l d b e e a s y to see that a c o m p l e t e b l o c k d i a g r a m realization c a n b e o b t a i n e d b y c o m b i n i n g t h e integrator b l o c k s of Fig. 12.23(a) with the s u m m e r b l o c k of Fig. 12.23(b), as s h o w n in F i g . 12.23(c).
hv
0
can b e obtained b y passing V
hp
through an
h p
(-co /s)V 0
integrator with a time constant equal to 1 / co . Furthermore, passing the resulting signal through another identical integrator results in the third signal involving V
hp
_
hp
Ko) s 0
77
0
2
; =
7
b (^) P
(12.59)
in Eq. (12.57)—namely,
( & > o / / ) V . Figure 12.23(a) shows a block d i a g r a m for such a two-integrator arrangement.
Therefore the signal at the output of the first integrator is labeled V . N o t e that the center-
N o t e that in anticipation of the use of the inverting o p - a m p Miller integrator circuit to imple
frequency gain of t h e b a n d p a s s filter realized is equal to
h p
m e n t e a c h integrator, the integrator blocks in Fig. 12.23(a) h a v e b e e n assigned negative signs. T h e p r o b l e m still r e m a i n s , h o w e v e r , of h o w to f o r m V p, the i n p u t signal feeding the t w o h
bp
-KQ.
In a similar fashion, w e can s h o w that the transfer function realized at the output of the second integrator is the l o w - p a s s function,
c a s c a d e d integrators. T o w a r d that end, w e r e a r r a n g e E q . ( 1 2 . 5 7 ) , e x p r e s s i n g V* in terms of hp
its single- a n d d o u b l e - i n t e g r a t e d v e r s i o n s a n d of V, as
\
2 V
h
=
K
V
. - l ^ v
h
-^V
h
(12.58)
P
= -
2
-
-
;
= T (s) lv
(12.60)
T h u s the o u t p u t of t h e second integrator is labeled V . N o t e that t h e d c gain of the l o w - p a s s lp
filter r e a l i z e d is e q u a l to K. 8
The name biquad stems from the fact that this circuit in its most general form is capable of realizing a biquadratic transfer function, that is, one that is the ratio of two quadratic polynomials.
W e c o n c l u d e that t h e t w o - i n t e g r a t o r - l o o p b i q u a d s h o w n in b l o c k d i a g r a m f o r m in F i g . 1 2 . 2 3 ( c ) realizes the t h r e e basic s e c o n d - o r d e r filtering functions, L P , B P , a n d H P ,
CHAPTER 12
12.7 FILTERS A N D T U N E D
S E C O N D - O R D E R ACTIVE FILTERS B A S E D O N T H E T W O - I N T E G R A T O R - L O O P T O P O L O G Y
AMPLIFIERS
simultaneously. T h i s versatility h a s m a d e t h e circuit very p o p u l a r a n d h a s g i v e n it the n a m e universal active filter.
w h i c h implies that w e can select arbitrary but practically convenient equal values for R and Rf. Then, equating the second-to-last terms on the right-hand side of E q s . (12.61) and (12.58) and setting R = R yields the ratio R /R required to realize a given Q as x
x
f
3
2
R /R
12.7.2 Circuit Implementation
3
T o obtain an o p - a m p circuit implementation of the two-integrator-loop biquad of Fig. 12.23(c), w e replace e a c h integrator w i t h a Miller integrator circuit h a v i n g CR = l / f t ) , and w e r e p l a c e the s u m m e r b l o c k w i t h an o p - a m p s u m m i n g circuit that is c a p a b l e of assigning both positive a n d negative w e i g h t s to its i n p u t s . T h e resulting circuit, k n o w n as the K e r w i n H u e l s m a n - N e w c o m b or K H N b i q u a d after its inventors, is s h o w n in Fig. 12.24(a). Given values for co , Q, and K, the design of t h e circuit is straightforward: W e select suitably practical v a l u e s for the c o m p o n e n t s of the i n t e g r a t o r s C a n d R so that CR =l/co . To d e t e r m i n e t h e v a l u e s of the resistors a s s o c i a t e d w i t h t h e s u m m e r , w e first u s e s u p e r p o s i tion to e x p r e s s t h e output of the s u m m e r V in t e r m s of its i n p u t s , V = -(co /s)V and V =(co /s )V ,a 0
= 2Q-1
2
(12.63)
Thus an arbitrary b u t convenient value can b e selected for either R or R , and the value of the other resistance can b e determined using Eq. (12.63). Finally, equating the coefficients of V, in E q s . (12.61) a n d (12.58) and substituting R =R and for R /R from Eq. (12.63) results in 2
f
£
t
3
3
2
= 2-(1/0
(12.64)
0
0
h p
2
lp
b p
0
hp
2
0
hp
Thus the gain parameter K is fixed to this value. T h e K H N b i q u a d can b e used to realize notch and all-pass functions by s u m m i n g w e i g h t e d versions of the three outputs, L P , B P , and H P . S u c h an o p - a m p s u m m e r is s h o w n in Fig. 12.24(b); for this s u m m e r w e can write
S
R
v =-( ^v
+^v
h
\R
rn hp
'\R = 1
L
R bp
R
H
1
lp
R
R
E q u a t i n g the last right-hand-side t e r m s of E q s . (12.61) a n d (12.58) gives f
bp
R„
H
R /R
+^v,
h
hp
B
(
^
1
2
-
6
5
)
ip
R
J
L
(12.62) Substituting for T , T , and T the overall transfer function hp
Ri AAAr
bp
Ip
from E q s . (12.56), (12.59), and (12.60), respectively, gives
2
V
v
—
= -K
0
(R /R )s F
- s(R /R )co
H
F
B
0
2
(R /R )co
+
F
L
0
-
v
'
s +s(co /Q) 0
(12.66)
+ co
0
from w h i c h w e can see that different transmission zeros can b e obtained b y the appropriate selection of the v a l u e s of the s u m m i n g resistors. F o r instance, a notch is obtained by select ing R = °° and B
§*
R
L
= M
(12.67)
KcoJ
12.7.3 An Alternative Two-1ntegrator-Loop Biquad Circuit
(b) FIGURE 1 2 . 2 4 (a) The KHN biquad circuit, obtained as a direct implementation of the b l o d j d i a g r a m ^ n, T ,, toee basic filtering functions, HP, BP, and LP, are simultaneously realized, (b) l o obtain the three outputs are summed with appropriate weights using this op-amp summer.
rSiSailSSS. 2 2 3 ( c
T h e
A n alternative two-integrator-loop biquad circuit in w h i c h all three op a m p s are u s e d in a single-ended m o d e can b e d e v e l o p e d as follows: R a t h e r than using the input s u m m e r to add signals with positive a n d negative coefficients, w e can introduce an additional inverter, as shown in Fig. 12.25(a). N o w all the coefficients of the s u m m e r h a v e the s a m e sign, and w e can d i s p e n s e w i t h the s u m m i n g amplifier a l t o g e t h e r a n d p e r f o r m the s u m m a t i o n at t h e virtual-ground input of the first integrator. T h e resulting circuit is s h o w n in Fig. 12.25(b), from w h i c h w e o b s e r v e that the high-pass function is n o longer available! This is the price paid for obtaining a circuit that utilizes all op a m p s in a single-ended m o d e . T h e circuit of Fig. 12.25(b) is k n o w n as the T o w - T h o m a s b i q u a d , after its originators. R a t h e r than u s i n g a fourth op a m p to realize the finite transmission zeros required for the notch and all-pass functions, as w a s d o n e w i t h the K H N biquad, an e c o n o m i c a l feedforward scheme can b e e m p l o y e d with the T o w - T h o m a s circuit. Specifically, the virtual g r o u n d available at the input of each of the three o p a m p s in the T o w - T h o m a s circuit permits the input signal to b e fed to all three op a m p s , as s h o w n in Fig. 12.26. If V is taken at the output 0
.
1 1 2 3
APTER 12
FILTERS A N D T U N E D
12.8
AMPLIFIERS
TABLE 12,2
i V
s
Vbp
All cases
C = arbitrary, R = l/co C,r= Ci Ci C C
AP
B I Q U A D R A T I C ACTIVE FILTERS
Design Data for t h e Circuit in Fig. 12.26
LP Positive BP Negative BP
0
HP Notch (all types)
(a)
SINGLE-AMPLIFIER
x
x
arbitrary
= 0,Ri = °°, R = R/dc gain, R = ~ = 0, /?! = °°, R = °°, R = <2r/center-frequency gain = 0, R = QR/center-frequency gain, R = °°, R = <>= = C x high-frequency gain, R =œ,R = o°,R = oo 2
3
2
3
X
2
X
3
2
3
Cj = C X high-frequency gain, i?j = °°, = R(co /co ) /high-frequency gain,R = °° Q = C x flat gain, = 00,^2 = /v/gain, # = 2
Q
n
3
Qr/gam
3
12.7.4 Final Remarks T w o - i n t e g r a t o r - l o o p b i q u a d s are e x t r e m e l y versatile a n d e a s y to d e s i g n . H o w e v e r , their pery. o
f o r m a n c e is a d v e r s e l y affected b y the finite b a n d w i d t h of the o p a m p s . Special t e c h n i q u e s
W V
O
'
exist for c o m p e n s a t i n g the circuit for such effects [see the S P I C E simulation in Section 12.12
-Vu,
and Sedra and Brackett (1978)].
(b)
D12.21 Design the KHN circuit to realize a high-pass function with/,', = 10 kHz and Q = 2. Choose C = 1 nF. What is the value of high-frequency gain obtained? What is the center-frequency gain of the bandpass function that is simultaneously available at the output of the first integrator?
FIGURE 1 2 . 2 5 (a) Derivation of an alternative two-integrator-loop biquad in which all op amps are used in a single-ended fashion, (b) The resulting circuit, known as the Tow-Thomas biquad.
A n s . A ' = WikLl.R.^R
-R_
-•
IPU2 larhiiruryi:
R ^3i)ki>: I
.<
D12.22 Use the KHN circuit together with an output summing amplifier to design a low-pass notch filter with ./o = 5 k H z , / , = 8 kHz, Q = 5, and a dc gain of 3. Select C = 1 nF and R = 10 k Q . L
Ans. A> = 31 .S3 k Q ; R, = /?, = fl = 10 k i i ( a r b i i r a n •: A'- -
k i > : A!.. - 25.6 k i i : R, -
2
I n . " k Q : A',. --
D12.23 U s e the T o w - T h o m a s biquad (Fig. 12.25b) to design a second-order bandpass filler w i t h / = 10 kHz, Q = 20, and unity center-frequency gain. If R = 10 k Q , give the values of C, R,,, and R 0
Ans. 1.59 nF: 2 u u k Q : 200 k Q D12.24 U s e the data of Table 12.2 to design the biquad circuit of Fig. 12.26 to realize an all-pass filter with Oh = H F r a d / s . g = 5, and flat gain = 1. Use C= 10 nF and ;=~10 k Q . :
Ans. R= 10 k i i : (2-determiningre>iMor = 5(i kL2: C ^ | i ) n l : W -• ••: A'- - l o k Q : R ^ 5 u k i i
FIGURE 1 2 . 2 6 The Tow-Thomas biquad with feedforward. The transfer function of Eq. (12.68) is realized by feeding the input signal through appropriate components to the inputs of the three op amps. This circuit can realize all special second-order functions. The design equations are given in Table 12.2. of t h e d a m p e d integrator, straightforward analysis yields t h e filter transfer function
2^ ;
1
s +s—^ QCR
12.8 SINGLE-AMPLIFIER BIQUADRATIC ACTIVE FILTERS
T h e o p a m p - R C b i q u a d r a t i c circuits studied in t h e t w o p r e c e d i n g sections p r o v i d e g o o d perf o r m a n c e , are versatile, a n d are e a s y to design a n d to adjust (tune) after final a s s e m b l y .
"tcO^cvi v
^
Unfortunately, h o w e v e r , they are n o t e c o n o m i c in their u s e of o p a m p s , r e q u i r i n g t h r e e or R R )
+
C
2
R R
1
^
+• C
2
2
(12.68)
four amplifiers p e r s e c o n d - o r d e r section. This c a n b e a p r o b l e m , especially in applications w h e r e p o w e r - s u p p l y current is to b e conserved: for instance, in a battery-operated instru-
R
2
w h i c h c a n b e u s e d to obtain t h e design d a t a g i v e n in Table 12.2.
m e n t . In this section w e shall study a class of s e c o n d - o r d e r filter circuits that requires only o n e o p a m p p e r b i q u a d . T h e s e m i n i m a l realizations, h o w e v e r , suffer a greater d e p e n d e n c e
1125
1126
I
~\
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.8
on t h e limited gain and b a n d w i d t h of t h e o p a m p and can also b e m o r e sensitive to the u n a v o i d a b l e tolerances in t h e values of resistors and capacitors than t h e multiple-op-amp b i q u a d s of t h e p r e c e d i n g sections. T h e s i n g l e - a m p l i f i e r b i q u a d s ( S A B s ) are therefore lim ited to the less stringent filter specifications—for e x a m p l e , p o l e Q factors less t h a n about 10. T h e synthesis of S A B circuits is b a s e d o n t h e u s e of f e e d b a c k to m o v e the poles of an R C circuit from t h e negative real axis, w h e r e t h e y naturally lie, to t h e complex-conjugate locations r e q u i r e d to p r o v i d e selective filter r e s p o n s e . T h e synthesis of S A B s follows a twostep p r o c e s s : 1. Synthesis of a feedback l o o p that realizes a pair of c o m p l e x - c o n j u g a t e poles charac terized b y a frequency co and a Q factor Q. Q
2. Injecting the input signal in a w a y that realizes t h e desired transmission zeros.
SINGLE-AMPLIFIER B I Q U A D R A T I C ACTIVE FILTERS
results in t h e p o l e s s of t h e closed-loop circuit o b t a i n e d as solutions to the equation P
^)
= "I
{12.11)
In the ideal case, A = ° o and the poles are obtained from N(s )=0 P
That is, the filter poles are identical
to the zeros of the RC
( 1 2
.
7 2
Since our objective is to realize a pair of complex-conjugate poles, w e should select an R C network that can h a v e complex-conjugate transmission zeros. T h e simplest such networks are the bridged-T networks s h o w n in Fig. 12.28 together with their transfer functions t(s) from b to a, with a open-circuited. A s an example, consider the circuit generated by placing the bridged-T network of Fig. 12.28(a) in the negative-feedback path of an o p amp, as s h o w n in Fig. 12.29.
12.8.1 Synthesis of the Feedback Loop
l
W v — — I
C o n s i d e r the circuit s h o w n in F i g . 12.27(a), w h i c h consists of a t w o - p o r t R C network n p l a c e d in t h e negative-feedback p a t h of an o p a m p . W e shall a s s u m e that, except for having a finite gain A, the o p a m p is ideal. W e shall denote b y t(s) t h e open-circuit v o l t a g e transfer function of the R C n e t w o r k n, w h e r e t h e definition of t(s) is illustrated in F i g . 12.27(b). The transfer function t(s) can in general b e written as t h e ratio of t w o p o l y n o m i a l s N(s) and D(s):
•
«•>"
^
T h e roots of N(s) are the transmission zeros of t h e R C n e t w o r k , and t h e roots of D(s) are its p o l e s . Study of n e t w o r k theory s h o w s that w h i l e the poles of an R C n e t w o r k are restricted to lie o n the n e g a t i v e real axis, the zeros can in general lie a n y w h e r e in the s plane. T h e l o o p gain L(s) of the f e e d b a c k circuit in F i g . 12.27(a) can b e determined using t h e m e t h o d of Section 8.7. It is simply t h e p r o d u c t of t h e o p - a m p gain A a n d t h e transfer function t(s), L(s)
= At(s)
=
(12.69) D(s)
Substituting for L(s) into the characteristic e q u a t i o n 1+L(s) = 0
(b)
(12.70)
FIGURE 1 2 . 2 8 Two RC networks (called bridged-T networks) that can have complex transmission The transfer functions given are from b to a, with a open-circuited.
Hh
FIGURE 1 2 . 2 7 (a) Feedback loop obtained by placing a two-port RC network n in the feedback path of an op amp. (b) Definition of the open-circuit transfer function t(s) of the RC network.
)
network.
1
'-il- -! FIGURE 1 2 . 2 9 An active-filter feedback loop generated using the bridged-T network of Fig. 12.28(a).
128
....
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
SINGLE-AMPLIFIER B I Q U A D R A T I C ACTIVE FILTERS
T h e p o l e p o l y n o m i a l of the active-filter circuit will b e e q u a l to t h e n u m e r a t o r p o l y n o m i a l of
different transmission zeros are obtained. This is, of course, the s a m e m e t h o d w e used in Section 12.5 with the L C R resonator and in Section 12.6 with the biquads based on the L C R resonator.
t h e b r i d g e d - T n e t w o r k ; thus, ®0
2
(
2 ,
2
1 ^
\ \
1 ^
1
A s an e x a m p l e , c o n s i d e r the feedback l o o p of Fig. 12.29. H e r e w e h a v e t w o g r o u n d e d n o d e s (one t e r m i n a l of R a n d t h e p o s i t i v e i n p u t t e r m i n a l of the o p a m p ) that can serve for injecting t h e i n p u t signal. F i g u r e 12.30(a) s h o w s t h e circuit w i t h the i n p u t signal injected through p a r t of the r e s i s t a n c e R . N o t e that the t w o resistances R /a a n d R /( 1 - a) h a v e a parallel e q u i v a l e n t of R . 4
w h i c h e n a b l e s u s to obtain co a n d Q as 0
4
(12.73) JC C R R 1
2
3
4
4
4
A n a l y s i s of t h e circuit to d e t e r m i n e its v o l t a g e transfer function T(s) = V {s)/V (s)
4
0
i
is
illustrated in Fig. 12.30(b). N o t e that w e h a v e a s s u m e d t h e o p a m p to b e ideal, a n d h a v e JC,C R R r
Q
2
3
t?
4
3
1 vCj
+
_J_
c
(12.74)
indicated t h e order of t h e analysis steps b y t h e circled n u m b e r s . T h e final step, n u m b e r 9,
2
If w e are d e s i g n i n g this circuit, co a n d Q are given a n d E q s . (12.73) a n d (12.74) c a n b e used 0
to d e t e r m i n e C
u
C , R , a n d R . It follows that t h e r e are t w o d e g r e e s of freedom. Let us 2
3
4
e x h a u s t o n e of t h e s e b y selecting Ci = C = C. L e t u s also d e n o t e R = R a n d R 2
3
4
= R/m.
By
substituting in E q s . (12.73) a n d (12.74) a n d w i t h s o m e m a n i p u l a t i o n , w e obtain m =
4Q
(12.75)
CR =
&
(12.76)
COn
T h u s if w e are g i v e n t h e v a l u e of Q, E q . (12.75) c a n b e u s e d to d e t e r m i n e t h e ratio of the two r e s i s t a n c e s R a n d R . T h e n t h e given v a l u e s of COQ a n d Q c a n b e substituted in E q . (12.76) to 3
4
d e t e r m i n e the t i m e constant CR. T h e r e r e m a i n s o n e d e g r e e of f r e e d o m — t h e v a l u e of C or R c a n b e arbitrarily c h o s e n . In a n actual design, this v a l u e , w h i c h sets t h e impedance
level of
the circuit, s h o u l d b e c h o s e n so that t h e resulting c o m p o n e n t v a l u e s are practical.
©V /R 0
D12.25 Design ihe circuit of Fig. 12.29 to realize a pair of poles with ft*, = 1 0 rad/s and Q = 1. Select C, = 4
1
3
.(5)V
Alls. W . - 2 ( > i J k « > : A ' . - 5 i > k l >
©
12.26 For the circuit designed in Exercise 12.25, find the location of the poles of the RC network in the feed-
= - - ^ x
0
sC R 2
(y /R )ç
3
3
back loop. Ans. - 0 . 3 8 2 X 1 0 and - 2 . 6 1 8 x L0 rad/s 4
4
R /(l 4
+
12.8.2 Injecting the Input Signal
_
YLZI (7)
© O A I ®
0
- a)
@
Node equation at X
®JM-ï)
V
H a v i n g synthesized a f e e d b a c k l o o p that realizes a given p a i r of p o l e s , w e n o w consider connecting the input signal source to the circuit. W e w i s h to d o this, of course, without altering the poles. S i n c e , for t h e p u r p o s e of finding t h e p o l e s of a circuit, an ideal v o l t a g e s o u r c e is equivalent to a short circuit, it follows that a n y circuit n o d e that is c o n n e c t e d to g r o u n d c a n instead (b)
b e c o n n e c t e d to t h e i n p u t v o l t a g e s o u r c e w i t h o u t c a u s i n g the p o l e s to c h a n g e . T h u s the m e t h o d of injecting the input v o l t a g e signal i n t o t h e f e e d b a c k l o o p is s i m p l y to disconnect a c o m p o n e n t (or several c o m p o n e n t s ) that is (are) c o n n e c t e d to g r o u n d a n d c o n n e c t it (them) to the input source. D e p e n d i n g o n the c o m p o n e n t ( s ) through w h i c h the input signal is injected,
FIGURE 1 2 . 3 0 (a) The feedback loop of Fig. 12.29 with the input signal injected through part of resistance R . This circuit realizes the bandpass function, (b) Analysis of the circuit in (a) to determine its voltage transfer function T(s) with the order of the analysis steps indicated by the circled numbers. 4
1129
1130
...
CHAPTER 12
12.8
FILTERS A N D T U N E D AMPLIFIERS
S I N G L E - A M P L I F I E R B I Q U A D R A T I C A C T I V E FL
consists of writing a n o d e equation at X and substituting for V b y t h e value determined in step 5. T h e result is the transfer function x
Ys. = V,
sja/C.R,) 2
s ^+ s I — u_ + 1
1
-U.
1
W e r e c o g n i z e this as a b a n d p a s s function w h o s e center-frequency gain can b e controlled b y the value of a. A s expected, t h e d e n o m i n a t o r p o l y n o m i a l is identical to t h e numerator p o l y n o m i a l of t(s) given in Fig. 12.28(a).
12.2? Use the component values obtained in Exercise 12.25 to design the bandpass circuit of Fig, 12.30(a). . D e t e r m i n e the values of (R^/cx) and K / ( l -a) to obtain a center-frequency gain of unity. 4
FIGURE 1 2 . 3 2 Application of the complementary transformation to the feedback loop in (a) results in the equivalent loop (same poles) shown in (b).
Ans. 100 k Q : l u n k Q
12.8.3 Generation of Equivalent Feedback Loops T h e c o m p l e m e n t a r y transformation of feedback loops is based on the property of linear net w o r k s illustrated in Fig. 12.31 for the two-port (three-terminal) n e t w o r k n. In Fig. 12.31(a), terminal c is grounded and a signal V is applied to terminal b. T h e transfer function from b to a with c g r o u n d e d is denoted t. T h e n , in Fig. 12.31(b), terminal b is g r o u n d e d and the input signal is applied to terminal c. T h e transfer function from c to a with b grounded can b e shown to b e the c o m p l e m e n t of t—that is, 1 - t. (Recall that w e used this property in generating a circuit realization for the all-pass function in Section 12.6.) A p p l i c a t i o n of the c o m p l e m e n t a r y transformation to a feedback l o o p to generate an e q u i v a l e n t feedback l o o p is a t w o - s t e p p r o c e s s : b
1. N o d e s of the feedback network and any of the o p - a m p inputs that are connected to ground should b e disconnected from ground and connected to the o p - a m p output. Con versely, those nodes that were connected to the op-amp output should be n o w connected to ground. That is, w e simply interchange the o p - a m p output tenninal with ground. 2. T h e t w o input terminals of t h e op a m p should b e interchanged.
T h e f e e d b a c k l o o p generated b y this transformation h a s the s a m e characteristic equation, and h e n c e t h e s a m e p o l e s , as t h e original l o o p . T o illustrate, w e s h o w in Fig. 12.32(a) the feedback loop formed b y connecting a two-port R C n e t w o r k in the negative-feedback path of an op a m p . A p p l i c a t i o n of the c o m p l e m e n t a r y transformation to this l o o p results in the feedback l o o p of Fig. 12.32(b). N o t e that in the latter l o o p t h e op a m p is u s e d in the unity-gain follower configuration. W e shall n o w s h o w that the t w o l o o p s of Fig. 12.32 are equivalent. If t h e op a m p h a s an o p e n - l o o p gain A, the follower in t h e circuit of Fig. 12.32(b) will h a v e a gain of A/(A + 1 ) . T h i s , together with the fact that t h e transfer function of n e t w o r k n from c to a is 1 - t (see Fig. 12.31), enables us to write for the circuit in Fig. 12.32(b) t h e characteristic e q u a t i o n
i - ^ ( i - 0
This e q u a t i o n can b e m a n i p u l a t e d to the form 1 +At
a o-
+
Linear network n
= 0
w h i c h is the characteristic equation of the l o o p in Fig. 12.32(a). A s an e x a m p l e , consider the application of t h e c o m p l e m e n t a r y transformation t o t h e feedback l o o p of Fig. 12.29: T h e feedback l o o p of Fig. 12.33(a) results. Injecting t h e input signal through C results in the cir cuit in Fig. 12.33(b), w h i c h can b e s h o w n (by direct analysis) to realize a second-order h i g h pass function. T h i s circuit is o n e of a family of S A B s k n o w n as the S a l i e n - a n d - K e y circuits, after their originators. T h e design of the circuit in Fig. 12.33(b) is based o n E q s . (12.73) through (12.76); n a m e l y , R = R, R = R/4Q , C = C = C, CR = 2Q/co , and the value of C is arbitrarily c h o s e n to b e practically convenient.
4)
V„
= o
x
2
3
(a)
(b)
FIGURE 1 2 . 3 1 Interchanging input and ground results in the complement of the transfer function.
4
X
2
0
A s a n o t h e r e x a m p l e , Fig. 12.34(a) s h o w s t h e feedback l o o p generated b y placing t h e two-port R C n e t w o r k of Fig. 12.28(b) in the negative-feedback p a t h of an op a m p . F o r an ideal o p a m p , this feedback loop realizes a pair of complex-Conjugate natural m o d e s h a v i n g the s a m e location as t h e zeros of t(s) of the R C n e t w o r k . T h u s , u s i n g the expression for
1132
V
W
_ ' ' CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.9
SENSITIVITY
1
given in Fig. 12.28(b), w e c a n write for the active-filter p o l e s co
0
=
1/JC C R,R 3
4
(12.77)
2
JC C R R r 3
Q =
4
t
C
1
2
+
\
\R
4
(12.78)
R
X
2
N o r m a l l y t h e design of this circuit is b a s e d on selecting R =R X
2
= R, C = C, and C = Clm. 4
3
W h e n substituted in E q s . (12.77) and (12.78), t h e s e yield m = 4Q~ CR = (a)
(12.79)
2Q/co
(12.80)
0
(b)
FIGURE 1 2 . 3 3 (a) Feedback loop obtained by applying the complementary fransformation to the loop in Fig. 12.29. (b) Injecting the input signal through Q realizes the high-pass function. This is one of the Sallenand-Key family of circuits.
with t h e r e m a i n i n g d e g r e e of f r e e d o m (the v a l u e of C or R) left to the d e s i g n e r to c h o o s e . Injecting t h e i n p u t signal to the C terminal that is c o n n e c t e d to g r o u n d can b e s h o w n to 4
result in a b a n d p a s s realization. If, h o w e v e r , w e apply the c o m p l e m e n t a r y transformation to the f e e d b a c k l o o p in Fig. 12.34(a), w e obtain the e q u i v a l e n t loop in F i g . 12.34(b). T h e l o o p e q u i v a l e n c e m e a n s that t h e circuit of F i g . 12.34(b) h a s t h e s a m e p o l e s and thus t h e s a m e C0 a n d Q a n d the s a m e design equations ( E q s . 12.77 t h r o u g h 12.80). T h e n e w l o o p in 0
Fig. 12.34(b) c a n b e u s e d to realize a l o w - p a s s function b y injecting t h e input signal as s h o w n in F i g . 12.34(c).
12.28 Analyze the circuit in Fig. 12.34(c) to determine its transfer function V (.«)/V (s) and thus show that co and Q arc indeed those in Eqs. (12.77) and (12.78). Also show that the dc gain is unity. u
;
0
D12.29 Design the circuit in Fig. 12.34(c) to realize a low-pass filter with./;, = 4 kHz and Q = l/Jl. 10-kQ resistors. Ans. R -R.
• 12.9
i n k l > : f". - 2 . S I n l ' : f -•- : \ f . 5 n r
SENSITIVITY
B e c a u s e of the tolerances in c o m p o n e n t values and b e c a u s e of t h e finite o p - a m p gain, the r e s p o n s e of the actual a s s e m b l e d filter will deviate from the ideal r e s p o n s e . A s a m e a n s for p r e d i c t i n g s u c h deviations, the filter d e s i g n e r e m p l o y s the c o n c e p t of sensitivity. Specifi cally, for second-order filters o n e is usually interested in finding h o w sensitive
their poles are
relative to variations (both initial tolerances and future drifts) in R C c o m p o n e n t v a l u e s and amplifier gain. T h e s e sensitivities c a n b e quantified u s i n g t h e classical sensitivity f u n c t i o n Si, defined as c>' = L i m Ay/}'
FIGURE 1 2 . 3 4 (a) Feedback loop obtained by placing the bridged-T network of Fig. 12.28(b) in the negative-feedback path of an op amp. (b) Equivalent feedback loop generated by applying the complementary transformation to the loop in (a), (c) A low-pass filter obtained by injecting V through R into the loop in (b). T
T
'
H 2 81)
Thus, y
S
x
= ^ dxy
(12.82)
Use
133
1 1 3 4
. .
CHAPTER 12
FILTERS A N D T U N E D
AMPLIFIERS
12.9
H e r e , x d e n o t e s the v a l u e of a c o m p o n e n t (a resistor, a capacitor, or an amplifier gain) and y d e n o t e s a circuit p a r a m e t e r of interest (say, co or Q). F o r small c h a n g e s
e a r l i e r
_ n a m e l y , C = C = C, R = R,R x
2
3
= R/4-Q,
4
and CR = 2Q/co —we 0
SENSITIVITY
get
0
2
s + s(co /Q) - ^ s + s{co /Q)(2Q
+ col °, + l ) + ©o
n
t(s)
=
L
-
J
L
2
0
y
T h u s w e c a n u s e t h e v a l u e of S to d e t e r m i n e the p e r - u n i t c h a n g e in y d u e to a given perunit c h a n g e in x. F o r instance, if t h e sensitivity of Q relative to a particular resistance R is 5 then a 1% increase in R results in a 5 % i n c r e a s e in the v a l u e of Q. x
(12.85)
where COQ and Q denote the nominal or design values of the pole frequency and Q factor. T h e actual values are obtained by substituting for t(s) in Eq. (12.84):
x
x
a
2
0,n^
, ^ , ^ 2 , ^ 2 ,
„ ^ 0 . „,2
Assuming the gain A to be real and dividing both sides by A + 1, w e get
For the feedback loop of Fig. 12.29, find the sensitivities of co and Q relative to all the passive components and the op-amp gain. Evaluate these sensitivities for the design considered in the preceding section for which Q = C .
/
+
1
+
^|t
a
+
l f l )
OJ
o = 0
(12.86)
From this equation we see that the actual pole frequency, co , and the pole Q, Q , are 0a
a
2
co
Solution
0a
To find the sensitivities with respect to the passive components, called passive sensitivities, we
Q
a
issume that the op-amp gain is infinite. In this case, co and Q are given by Eqs. (12.73) and 0
(12.87)
¥
(12-88)
0
= 1 +2Q
0
12.74). Thus for co w e have
= co
/ ( A + 1)
Thus 1
co = 0
S>
JC C R R 1
2
3
= 0
4
„Q
vhich can be used together with the sensitivity definition of Eq. (12.82) to obtain
_
A
~
C\
R^
Ct
RQ
2
For A > 2Q
2
2
A
2Q /(A+\)
A + 1 1 +2Q V ( A + 1) 2
and A > 1 we obtain
For Q we have ¿ 7 -
A
It is usual to drop the subscript a in this expression and write to which we apply the sensitivity definition to obtain
2 Q
S
A
=
(12.89) A 9
v
^- -'V
1
M ^ 2' ^ ^ 1
Note that if Q is high ( g > 5 ) , its sensitivity relative to the amplifier gain can be quite high.
A/L- / 2
For the design with Q = C we see that S q = 0. Similarly, w e can show that 2
Q
S
=0,
C L
2
Q
S
R
«3
= 1 2'
12.9.1 A Concluding Remark
5? = -1 «4
T h e results of E x a m p l e 12.3 indicate a serious d i s a d v a n t a g e of single-amplifier b i q u a d s —
2
It is important to remember that the sensitivity expression should be derived before values corre-
the sensitivity of Q relative to the amplifier gain is quite high. A l t h o u g h a t e c h n i q u e exists Q
for r e d u c i n g S
sponding to a particular design are substituted. Next w e consider the sensitivities relative to the amplifier gain. If w e assume the op amp to
A
in S A B s [see Sedra et al. ( 1 9 8 0 ) ] , this is d o n e at the e x p e n s e of i n c r e a s e d
p a s s i v e sensitivities. N e v e r t h e l e s s , the resulting S A B s are u s e d extensively in m a n y applications. H o w e v e r , for filters w i t h Q factors greater t h a n about 10, o n e u s u a l l y opts for o n e
have a finite gain A, the characteristic equation for the loop becomes
of t h e multiamplifier b i q u a d s studied in S e c t i o n s 12.6 and 12.7. F o r t h e s e circuits S
A
1+Ari» = 0
(12.84)
is
2
p r o p o r t i o n a l to Q, rather than to Q as in the S A B c a s e (Eq. 12.89).
where t(s) is given in Fig. 12.28(a). To simplify matters w e can substitute for the passive components by their design values. This causes no errors in evaluating sensitivities, since we are now Lmm finding the sensitivity with respect to the amplifier gain. Using the design values obtained
9
Because the open-loop gain A of op amps usually has wide tolerance, it is important to keep Sf very small.
and
1 1 3 6
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.10
S W I T C H E D - C A P A C I T O R FILTERS
together w i t h t w o M O S transistors acting as s w i t c h e s . In s o m e circuits, m o r e elaborate switch configurations a r e u s e d , b u t s u c h details a r e b e y o n d o u r p r e s e n t n e e d . T h e t w o M O S s w i t c h e s in F i g . 12.35(b) are d r i v e n b y a nonoverlapping 12.30 In a particular filter utilizing the feedback loop of Fig. 12.29, with C, = C , find the expected percent a. change in a*, and Q under the conditions that (a) R, is 2% high, (b) R is 2 % high, (c) both R and /?, ...2% high, and (d) both capacitors are 2% low and hodi resistors are 2% high. " Arts, (a) - 1 % , + 1 % ; ( b ) - W o , - 1 % ; (e) - 2 % , 0 % ; ( d ) 0 % , 0 % 2
4
t
a
two-phase
clock. F i g u r e 12.35(c) s h o w s t h e c l o c k w a v e f o r m s . W e shall a s s u m e in this i n t r o d u c t o r y exposition that t h e c l o c k f r e q u e n c y f
(f
c
— l/T )
c
is m u c h h i g h e r than t h e frequency of
c
the signal b e i n g filtered. T h u s d u r i n g c l o c k p h a s e fa, w h e n C is c o n n e c t e d across t h e i n p u t x
signal s o u r c e v t h e v a r i a t i o n s in t h e i n p u t signal a r e negligibly small. It follows that d u r i n g b
0j c a p a c i t o r C c h a r g e s u p t o t h e v o l t a g e v x
b
lei
12.10
SWSTCHED-CAPACITOR FILTERS
C
=
v
l i
T h e n , d u r i n g c l o c k p h a s e fa, c a p a c i t o r C is c o n n e c t e d t o t h e v i r t u a l - g r o u n d i n p u t of t h e x
op a m p , as i n d i c a t e d in F i g . 12.35(d). C a p a c i t o r C is thus forced to d i s c h a r g e , a n d its p r e v i x
T h e a c t i v e - R C filter circuits p r e s e n t e d a b o v e h a v e t w o properties that m a k e their production
ous c h a r g e q
in m o n o l i t h i c I C form difficult, if n o t practically i m p o s s i b l e ; t h e s e are t h e n e e d for large-
c l
is transferred t o C , in t h e direction indicated in F i g . 12.35(d). 2
F r o m t h e description a b o v e w e see that during e a c h clock period T an a m o u n t of c h a r g e c
v a l u e d capacitors a n d the r e q u i r e m e n t of a c c u r a t e R C t i m e constants. T h e search therefore
q
h a s c o n t i n u e d for a m e t h o d of filter d e s i g n that w o u l d lend itself m o r e naturally t o I C imple
the a v e r a g e current flowing b e t w e e n the input n o d e (IN) and t h e virtual-ground n o d e ( V G ) is
c l
= Civ, is extracted from t h e input source a n d supplied to the integrator capacitor C . T h u s 2
m e n t a t i o n . I n this section w e shall i n t r o d u c e o n e such m e t h o d .
,• = £i3 ^c
12.10.1 The Basic Principle
If T is sufficiently short, o n e c a n t h i n k of this p r o c e s s as a l m o s t c o n t i n u o u s a n d define a n c
T h e s w i t c h e d - c a p a c i t o r filter t e c h n i q u e is b a s e d on t h e realization that a capacitor switched
e q u i v a l e n t r e s i s t a n c e 7? that is i n effect p r e s e n t b e t w e e n n o d e s I N a n d V G : eq
b e t w e e n t w o circuit n o d e s at a sufficiently h i g h rate is e q u i v a l e n t to a resistor connecting t h e s e t w o n o d e s . T o b e specific, c o n s i d e r t h e a c t i v e - R C i n t e g r a t o r of F i g . 12.35(a). This is t h e f a m i l i a r M i l l e r integrator, w h i c h w e u s e d in t h e t w o - i n t e g r a t o r - l o o p b i q u a d i n Sec tion 1 2 . 7 . In F i g . 12.35(b) w e h a v e r e p l a c e d t h e input resistor R b y a g r o u n d e d capacitor C,
Thus,
x
R
eq
Using R
tq
= T /C c
(12.90)
x
w e obtain an e q u i v a l e n t t i m e constant for t h e integrator: t i m e constant = C R 2
eq
=
(12.91) C
x
T h u s t h e t i m e c o n s t a n t that d e t e r m i n e s t h e frequency r e s p o n s e of the filter is e s t a b l i s h e d b y the c l o c k p e r i o d T a n d t h e capacitor ratio C /C . c
2
x
B o t h these p a r a m e t e r s c a n b e w e l l c o n -
- trolled in an I C p r o c e s s . Specifically, n o t e t h e d e p e n d e n c e on capacitor ratios rather than on absolute v a l u e s of c a p a c i t o r s . T h e accuracy of c a p a c i t o r ratios in M O S t e c h n o l o g y can b e controlled to within 0 . 1 % . A n o t h e r p o i n t w o r t h o b s e r v i n g is that w i t h a r e a s o n a b l e clocking frequency (such as 100 k H z ) a n d n o t - t o o - l a r g e c a p a c i t o r ratios (say, 10), o n e c a n obtain r e a s o n a b l y l a r g e t i m e 4
c o n s t a n t s (such as 1 0 ~ s) suitable for a u d i o applications. S i n c e capacitors typically o c c u p y relatively l a r g e areas o n t h e I C chip, o n e a t t e m p t s t o m i n i m i z e their values. In this context, it is i m p o r t a n t to n o t e that t h e ratio accuracies q u o t e d earlier are obtainable with t h e s m a l l e r c a p a c i t o r v a l u e as l o w as 0.1 p F .
12.10.2 Practical Circuits T h e s w i t c h e d - c a p a c i t o r ( S C ) circuit in F i g . 12.35(b) realizes an inverting integrator (note the d i r e c t i o n of c h a r g e flow t h r o u g h C in F i g . 12.35d). A s w e s a w i n S e c t i o n 12.7, a t w o 2
(c)
(d)
i n t e g r a t o r - l o o p active filter is c o m p o s e d of o n e inverting a n d o n e n o n i n v e r t i n g i n t e g r a t o r .
FIGURE 1 2 . 3 5 Basic principle of the switched-capacitor filter technique, (a) Active-RC integrator, (b) Switched-capacitor integrator, (c) Two-phase clock (nonoverlapping). (d) During fa, C charges up to the current value of v, and then, during fa, discharges into C . x
2
10
In the two-integrator loop of Fig. 12.25(b) the noninverting integrator is realized by the cascade of a Miller integrator and an inverting amplifier.
1137
1 1 38
J
CHAPTER 12
FILTERS A N D T U N E D
AMPLIFIERS
c,
i
1
T J
+ z|i—o<^»
2
Hi—o0,
-JF
[>-L
(a)
1
1
C,
o-
+
ri
+
(b) FIGURE 1 2 . 3 6 A pair of complementary stray-insensitive switched-capacitor integrators, (a) Noninverting switched-capacitor integrator, (b) Inverting switched-capacitor integrator.
T o realize a switched-capacitor b i q u a d filter w e therefore n e e d a pair of c o m p l e m e n t a r y switched-capacitor integrators. F i g u r e 12.36(a) s h o w s a noninverting, or positive, integrator circuit. T h e r e a d e r is u r g e d to follow the operation of this circuit during t h e t w o clock phases and thus s h o w that it operates in m u c h t h e s a m e w a y as t h e basic circuit of F i g . 12.35(b), except for a sign reversal. In addition to realizing a noninverting integrator function, t h e circuit in Fig. 12.36(a) is insensitive to stray capacitances; h o w e v e r , w e shall not e x p l o r e this point any further. T h e interested r e a d e r is referred to S c h a u m a n n , G h a u s i , a n d L a k e r (1990). B y reversal of the clock p h a s e s o n t w o of the switches, the circuit in F i g . 12.36(b) is obtained. T h i s circuit real izes t h e inverting integrator function, like t h e circuit of F i g . 12.35(b), b u t is insensitive to stray capacitances ( w h i c h the original circuit of F i g . 12.35b is not). T h e pair of c o m p l e m e n tary integrators of Fig. 12.36 has b e c o m e the standard building b l o c k in t h e design of switched-capacitor filters. L e t u s n o w consider the realization of a c o m p l e t e b i q u a d circuit. F i g u r e 12.37(a) s h o w s t h e a c t i v e - R C two-integrator-loop circuit studied earlier. B y considering the c a s c a d e of inte grator 2 and the inverter as a positive integrator, a n d then simply replacing e a c h resistor b y its switched-capacitor equivalent, w e obtain t h e circuit in F i g . 12.37(b). I g n o r e t h e d a m p i n g a r o u n d t h e first integrator (i.e., the s w i t c h e d capacitor C ) for t h e t i m e being a n d note that the feedback loop indeed consists of o n e inverting and o n e noninverting integrator. T h e n n o t e the p h a s i n g of t h e switched capacitor u s e d for d a m p i n g . R e v e r s i n g the p h a s e s h e r e w o u l d convert t h e feedback to positive a n d m o v e t h e p o l e s to the right half of t h e s plane. 5
1140
CHAPTER 12
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12.11
O n the other hand, t h e p h a s i n g of the feed-in switched capacitor ( C ) is n o t that important- a reversal of p h a s e s w o u l d result only in an inversion in the sign of the function realized. 6
H a v i n g identified the c o r r e s p o n d e n c e s b e t w e e n the a c t i v e - R C b i q u a d a n d the switchedcapacitor biquad, w e can n o w derive design equations. Analysis of the circuit in Fig. 12.37(a) yields
T U N E D AMPLIFIERS
12.10.3 A Final Remark W e h a v e a t t e m p t e d to p r o v i d e only an introduction to switched-capacitor filters. W e h a v e m a d e m a n y simplifying a s s u m p t i o n s , t h e m o s t important b e i n g t h e s w i t c h e d - c a p a c i t o r resistor e q u i v a l e n c e (Eq. 12.90). T h i s e q u i v a l e n c e is correct only a t / = °° a n d is a p p r o x i mately correct for f > f. S w i t c h e d - c a p a c i t o r filters are, in fact, s a m p l e d - d a t a n e t w o r k s w h o s e analysis a n d design c a n b e carried o u t exactly using z-transform techniques. T h e interested r e a d e r is referred to t h e b i b l i o g r a p h y . e
c
1 (12.92)
JC C R R t
2
3
4
R e p l a c i n g R a n d R with their S C equivalent values, that is, 2
4
R
3
= T /C c
and
3
R =
12.11
T /C
4
c
gives ft> of the S C b i q u a d as 0
(12.93)
T i\j C C c
2
X
It is u s u a l to select the time constants of t h e t w o integrators to b e equal; that is, T -^C
T i ^ d
=
2
c
c
3
(12.94)
1 4 2
=
=
C
C
2
In this section, w e study a special k i n d of frequency-selective n e t w o r k , the L C - t u n e d a m p l i fier. F i g u r e 12.38 s h o w s the general s h a p e of t h e frequency r e s p o n s e of a tuned amplifier. T h e t e c h n i q u e s discussed apply to amplifiers w i t h center frequencies in t h e r a n g e of a few h u n d r e d kilohertz to a few h u n d r e d m e g a h e r t z . T u n e d amplifiers find application in t h e radio-frequency ( R F ) a n d intermediate-frequency (IF) sections of c o m m u n i c a t i o n s receivers and i n a variety of other s y s t e m s . It s h o u l d b e n o t e d that t h e t u n e d - a m p l i f i e r r e s p o n s e of Fig. 12.38 is similar to that of t h e b a n d p a s s filter d i s c u s s e d i n earlier sections. A s indicated in F i g . 12.38, t h e r e s p o n s e is characterized b y the center frequency G) , t h e 3-dB b a n d w i d t h B, a n d t h e skirt selectivity, w h i c h is u s u a l l y m e a s u r e d as t h e ratio of t h e 30-dB b a n d w i d t h to the 3-dB b a n d w i d t h . I n m a n y applications, t h e 3-dB b a n d w i d t h is less than 5 % of co . This n a r r o w - b a n d p r o p e r t y m a k e s possible certain a p p r o x i m a t i o n s that c a n simplify the design p r o c e s s , as will b e e x p l a i n e d later. 0
If, further, w e select the t w o integrating capacitors C, a n d C to b e equal, ('
T U N E D AMPLIFIERS
4
(12.95)
0
then C
— C
3
= KC
4
(12.96)
w h e r e from E q . (12.93) K =
co T 0
(12.97)
c
F o r the c a s e of equal t i m e constants, t h e Q factor of the circuit in F i g . 12.37(a) is given by R /R . T h u s t h e Q factor of the c o r r e s p o n d i n g S C circuit in F i g . 12.37(b) is g i v e n b y 5
4
T /C c
5
(12.98)
Q T h u s C should b e selected from 5
c
4
KC
Q
Q
C
co T n
T h e tuned amplifiers studied i n this section are small-signal v o l t a g e amplifiers in w h i c h the transistors o p e r a t e in the "class A " m o d e that is, t h e transistors c o n d u c t at all t i m e s . T u n e d p o w e r amplifiers b a s e d o n class C a n d other switching m o d e s of operation a r e n o t studied in this b o o k . (For a discussion on the classification of amplifiers, refer to Section 14.1.)
12.11.1 The Basic Principle T h e basic principle underlying the design of tuned amplifiers is the u s e of a parallel L C R cir cuit as the load, or at t h e input, of a B J T or a F E T amplifier. This is illustrated in F i g . 12.39 with a M O S F E T amplifier h a v i n g a tuned-circuit load. F o r simplicity, t h e bias details are not included. S i n c e this circuit u s e s a single t u n e d circuit, it is k n o w n as a s i n g l e - t u n e d amplifier. T h e amplifier equivalent circuit is s h o w n in F i g . 12.39(b). H e r e R denotes t h e
(12.99)
r
~«-"Q
Gain (dB) A
Finally, t h e center-frequency gain of the b a n d p a s s function is given b y C Center-frequency gain = — = Q
C 6
co T C Q
(12.100)
c
D12.31 Use C\ = C = 20 p F and design the circuit in Fig. 12.37(b) to realize a bandpass function with , / O = 10 kHz, 0 = 20, and unity center-frequency gain. Use a clock f r e q u e n c y / ; = 200 kHz. Find the values of C . C . C«. and Q . 2
3
4
Ans. 6.283 p F ; 6.283 p F ; 0.314 pF; 0.314 pF
0
FT>O
FIGURE 1 2 . 3 8 Frequency response of a tuned amplifier.
CD
1 1 4 1
1142
'
CHAPTER 12
FILTERS A N D T U N E D
12.11
AMPLIFIERS
T U N E D AMPLIFIERS
s required to design a tuned amplifier of the type shown in Fig. 12.39, h a v i n g / = 1 MHz, 3-dB idwidth = 10 kHz, and center-frequency gain = - 1 0 V/V. The F E T available has at the bias int g - 5 mAAV and r = 10 tel. The output capacitance is negligibly small. Determine the [ues of R , C , and L. 0
m
0
L
L
ilution
(a)
nter-frequency gain = - 1 0 = -5R. Thus R = 2 k Q . Since R = R \\r , L
0
then R = 2.5 k Q . L
D 4
B = In x 1 0 = —
+
CR
us C = 2_KX ZL
ice co
0
= 2n x 1 0
6
=
\/JLC,
i 10 x 2 x 10
= 7958 p F
w e obtain
(b)
= 3.18 yjH FIGURE 1 2 . 3 9 The basic principle of tuned amplifiers is illustrated using a MOSFET with a tuned-circuit load. Bias details are not shown. parallel equivalent of R and the output resistance r„ of t h e F E T , a n d C is the parallel equivalent o f C and the F E T output capacitance (usually very small). F r o m the equivalent circuit w e can write L
L
y
8m Y
sC+l/R
L
x 7958 x 10
1 2
12.11.2 Inductor Losses s
s
2o - ^
(12.106)
Typically, Q is in t h e r a n g e of 5 0 t o 2 0 0 . T h e analysis of a t u n e d amplifier is greatly simplified b y representing t h e inductor loss b y a parallel resistance R , as s h o w n in Fig. 12.40(b). T h e relationship b e t w e e n R a n d Q can b e found b y writing, for t h e admittance of t h e circuit in Fig. 12.40(a), 0
8m c
1 2
T h e p o w e r loss in t h e i n d u c t o r is usually represented b y a series resistance r as s h o w n in Fig. 12.40(a). H o w e v e r , rather than specifying the value of r , the u s u a l practice is to specify the inductor Q factor at t h e frequency of interest,
+ l/sL
T h u s the voltage gain can b e expressed as VQ
An x l 0
S 2
s
(12.101)
+ s(l/CR)+
1/LC
p
p
w h i c h is a second-order bandpass function. T h u s the tuned amplifier has a center frequency of Y(jco ) 0
co
=
0
\/JL~C
r + JO) L
(12.102)
s
=
a 3-dB b a n d w i d t h of
1
=
0
1 jco L 0
J_
B
1
_
1- ; ( 1 /Go)
1 Jco L 0
l+7(l/6o) 1+ (l/Qo)
(12.103)
CR a Q factor of Q = œ /B 0
=
co CR
(12.104)
-g R
(12.105)
0
a n d a center-frequency gain of V„(jco ) 0
=
m
N o t e that the expression for the center-frequency g a i n could h a v e b e e n written b y inspection; A t r e s o n a n c e t h e reactances of L a n d C c a n c e l o u t a n d t h e i m p e d a n c e of t h e parallel L C R circuit r e d u c e s to R.
FIGURE 1 2 . 4 0 Inductor equivalent circuits.
0
1 1 4 3
1144
*
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.11
T U N E D AMPLIFIERS
:
££-|
F o r g o > 1, Y(jco ) 0
jco L\
(12.107)
Q.
0
0
E q u a t i n g this to the a d m i t t a n c e of the circuit in F i g . 12.40(b) gives Go =
(12.108)
co L 0
or, equivalently, (12.109) Finally, it should b e noted that t h e coil Q factor p o s e s an u p p e r limit o n the value of Q a c h i e v e d b y the t u n e d circuit.
12.32 If the inductor in Example 12.4 has Q = 150, find R,, and then find the value to which R should be changed to keep the overall Q, and hence the bandwidth, unchanged. 0
L
Ans. 3 kQ: 15 kQ (b)
12.11.3 Use of Transformers In m a n y cases it is found that t h e required v a l u e of i n d u c t a n c e is not practical, in t h e sense that coils w i t h t h e required i n d u c t a n c e m i g h t n o t b e available w i t h the required h i g h values of Q . A simple solution is to u s e a transformer to effect an i m p e d a n c e c h a n g e . Alterna tively, a t a p p e d coil, k n o w n as an a u t o t r a n s f o r m e r , can b e used, as s h o w n in F i g . 12.41. P r o v i d e d t h e t w o parts of the inductor are tightly coupled, w h i c h can b e achieved b y wind ing on a ferrite core, the transformation relationships s h o w n hold. T h e result is that t h e tuned circuit seen b e t w e e n terminals 1 and 1' is e q u i v a l e n t to that in F i g . 12.39(b). F o r e x a m p l e , if a turns ratio n = 3 is u s e d in t h e amplifier of E x a m p l e 12.4, then a coil w i t h inductance L' = 9 X 3.18 = 2 8 . 6 and a c a p a c i t a n c e C" = 7 9 5 8 / 9 = 884 p F will b e required. Both t h e s e values are m o r e practical than t h e original o n e s . In applications that involve coupling t h e output of a tuned amplifier to t h e input of another amplifier, the tapped coil can b e u s e d to raise t h e effective input resistance of the latter amplifier stage. In this w a y , o n e can avoid reduction of the overall Q. T h i s point is illustrated in F i g . 12.42 and in the following exercises.
FIGURE 1 2 . 4 2 (a) The output of a tuned amplifier is coupled to the input of another amplifier via a tapped coil, (b) An equivalent circuit. Note that the use of a tapped coil increases the effective input impedance of the second amplifier stage.
0
D12.33 Consider the circuit in Fig. 12.42(a), first without lapping the coil. Let 1 = 5 pVt and assume thai /?, is fixed a t ! k Q . W e wish to design a tuned amplifier w i t h / = 455 kHz and a 3-dB bandwidth of 10 kHz (this is the Intermediate Frequency (IF) amplifier of an A M radio). If the B I T has R = 1 k Q and C = 200 pF, find the actual bandwidth obtained and the required value of C,. Ans. ! 5 k l ! / : l-\.2~ nl 0
w
D12.34 Since the bandwidth realized in Exercise 12.33 is greater than desired, find an alternative design utilize ing a tapped coil as in Fig. 12.42(a). Find the value of n t h a t allows the specifications to be just metAlso find the new required value of C, and the current gain I,./] at resonance. Assume that at the bias point the BJT has g,„ = 4 0 mA/V. Ans. 1.36; 24.36 n F : 19.1 A/A
12.11.4 Amplifiers with Multiple Tuned Circuits T h e selectivity a c h i e v e d with the single-tuned circuit of Fig. 12.39 is not sufficient in m a n y applications—for instance, in t h e IF amplifier of a r a d i o or a T V receiver. Greater selectivity is obtained b y u s i n g additional t u n e d stages. F i g u r e 12.43 s h o w s a B I T with tuned circuits at b o t h the input a n d t h e o u t p u t . In this circuit t h e bias details are s h o w n , from w h i c h w e n o t e t h a t b i a s i n g is quite similar to the classical a r r a n g e m e n t e m p l o y e d in low-frequency 11
FIGURE 1 2 . 4 1 A tapped inductor is used as an impedance transformer to allow using a higher inductance, V, and a smaller capacitance, C.
m
Note that because the input circuit is a parallel resonant circuit, an input current source (rather than voltage source) signal is utilized.
1145
CHAPTER 12
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12.11
TUNED AMPLIFIERS
FIGURE 1 2 . 4 3 A BJT amplifier with tuned circuits at the input and the output. discrete-circuit design. H o w e v e r , to avoid t h e l o a d i n g effect of the bias resistors R and R on the input tuned circuit, a r a d i o - f r e q u e n c y c h o k e ( R F C ) is inserted in series with each resistor. S u c h c h o k e s h a v e high i m p e d a n c e s at the frequencies of interest. T h e u s e of R F C s in biasing tuned R F amplifiers is c o m m o n practice. m
B2
T h e analysis and design of the d o u b l e - t u n e d amplifier of Fig. 12.43 is c o m p l i c a t e d by t h e Miller e f f e c t d u e to capacitance C^. S i n c e the l o a d is not simply resistive, as w a s the c a s e in the amplifiers studied in Section 6.4.4, t h e M i l l e r i m p e d a n c e at the input will be complex. This reflected impedance will cause detuning of the input circuit as well as "skewing" of the r e s p o n s e of the input circuit. N e e d l e s s to say, the coupling introduced b y C m a k e s t u n i n g (or aligning) t h e amplifier quite difficult. W o r s e still, t h e capacitor C can cause oscillations to occur [see G r a y and Searle (1969) a n d P r o b l e m 12.75]. M e t h o d s exist for n e u t r a l i z i n g t h e effect of C using additional circuits arranged to feed b a c k a current equal and opposite to that t h r o u g h C^. A n alternative, and preferred, a p p r o a c h is to u s e circuit configurations that d o n o t suffer from the Miller effect. T h e s e are discussed later. Before leaving this section, h o w e v e r , w e w i s h to point out that circuits of the t y p e s h o w n in F i g . 12.43 are usually d e s i g n e d utilizing the y-parameter m o d e l of t h e B J T (see A p p e n d i x B ) . T h i s is d o n e b e c a u s e here, in v i e w of t h e fact that C plays a significant role, t h e y - p a r a m e t e r m o d e l m a k e s t h e analysis simpler (in c o m p a r i s o n to that u s i n g the hybrid-;r m o d e l ) . A l s o , the y p a r a m e t e r s can easily b e m e a s u r e d at t h e particular frequency of interest, co . F o r n a r r o w - b a n d amplifiers, the a s s u m p t i o n is usually m a d e that the y p a r a m eters r e m a i n a p p r o x i m a t e l y constant o v e r the p a s s b a n d . 12
M
M
(b)
p
M
0
FIGURE 1 2 . 4 4 Two tuned-amplifier configurations that do not suffer from the Miller effect: (a) cascode and (b) common-collector common-base cascade. (Note mat bias details of the cascode circuit are not shown.) the c o m m o n - c o l l e c t o r c o m m o n - b a s e cascade. F i g u r e 12.44 s h o w s tuned amplifiers b a s e d o n these t w o configurations. T h e C C - C B cascade is usually preferred in I C i m p l e m e n t a t i o n s b e c a u s e its differential structure m a k e s it suitable for I C biasing techniques. (Note that t h e biasing details of the c a s c o d e circuit are not s h o w n in Fig. 12.44(a). Biasing can b e d o n e u s i n g a r r a n g e m e n t s similar to those discussed in earlier chapters.)
12.11.6 Synchronous Tuning 12.11.5 The Cascode and the CC-CB Cascade F r o m o u r study of amplifier frequency r e s p o n s e in C h a p t e r 6 w e k n o w that t w o amplifier configurations d o not suffer from the M i l l e r effect. T h e s e are the c a s c o d e configuration and 1 2
Here we use "Miller effect" to refer to the effect of the feedback capacitance C in reflecting back an input impedance that is a function of the amplifier load impedance. fl
In the design of a tuned amplifier with multiple t u n e d circuits the question of the frequency to w h i c h e a c h circuit should be tuned arises. T h e objective, of course, is for the overall r e s p o n s e to exhibit high p a s s b a n d flatness and skirt selectivity. T o investigate this question, w e shall a s s u m e that the overall response is the p r o d u c t of the individual responses: in other w o r d s , that the stages d o not interact. This can easily b e achieved using circuits such as those in F i g . 12.44.
11
4 7
CHAPTER 12
1 1 4 8
FILTERS A N D T U N E D AMPLIFIERS
12.11
W
T U N E D AMPLIFIERS
CO
0
FIGURE 1 2 . 4 6 Stagger-tuning the individual resonant circuits can result in an overall response with a passband flatter than that obtained with synchronous tuning (Fig. 12.45). FIGURE 1 2 . 4 5 Frequency response of a synchronously tuned amplifier. Consider first the case of N identical resonant circuits, k n o w n case. Figure 12.45 shows the response of an individual stage and the b a n d w i d t h "shrinkage" of the overall response. T h e 3-dB amplifier is related to that of the individual tuned circuits, co /Q, 0
as the synchronously tuned that of the cascade. Observe b a n d w i d t h B of the overall b y (see P r o b l e m 12.77)
For a narrow-band filter, Q $> 1, and for values of s in the neighborhood of +joh (see Fig. 12.47b) the second factor in the denominator is approximately (s + joh — 2s). H e n c e Eq. (12.111) can be a p p r o x i m a t e d in t h e n e i g h b o r h o o d of joh b y ™, x T(s) =
a,/2 !
0
B = ^ 2
l
/
N
- \
=
s+co /2Q-jco
Q
l
{s-jco ) 0
-
a,/2 +
(12.112)
co /2Q 0
(12.110) 13
T h e factor — 1 is k n o w n as the b a n d w i d t h - s h r i n k a g e factor. G i v e n B and N, w e can u s e Eq. (12.110) to d e t e r m i n e the b a n d w i d t h required of t h e individual stages, co /Q. 0
This is k n o w n as the n a r r o w - b a n d a p p r o x i m a t i o n . N o t e that the m a g n i t u d e r e s p o n s e , for s =j(0, h a s a p e a k v a l u e of a Q/co at co = co , as expected. N o w consider a first-order low-pass n e t w o r k w i t h a single p o l e at p = -co /2Q (we u s e p to denote the c o m p l e x frequency variable for t h e l o w - p a s s filter). Its transfer function is x
0
0
0
EXERCISE Tip) D12.35 Consider the design of an IF amplifier for an FM radio receiver. Using two synchronously luned stages w i t h / , = 10.7 M H z , find the 3-dB bandwidth of each stage so that the overall bandwidth is 200 kHz. Using 3-/JH inductors find C and R for each stage. Ans.
HO.S
=
^ p +
K
, co /2Q n
(12.113)
n
0
_ w h e r e K is a constant. C o m p a r i n g E q s . (12.112) a n d (12.113) w e note that they are identical — s -JCOQ or, equivalently,
for/7
s=P+jto
73.7 pi . o.';5 kU
(12.114)
0
This result i m p l i e s that t h e r e s p o n s e of t h e s e c o n d - o r d e r b a n d p a s s filter in the neighborhood of its center frequency s = jco is identical to t h e r e s p o n s e of a first-order l o w - p a s s filter with a p o l e at (-co /2Q) in the neighborhood of p = 0. T h u s the b a n d p a s s r e s p o n s e can b e o b t a i n e d b y shifting t h e pole of the low-pass p r o t o t y p e and a d d i n g the c o m p l e x - c o n j u g a t e pole, as illustrated in F i g . 12.47(b). T h i s is called a l o w p a s s - t o - b a n d p a s s t r a n s f o r m a t i o n for narrow-band filters. T h e transformation p = s -joh can b e applied to low-pass filters of order greater than one. For instance, w e can transform a m a x i m a l l y flat second-order low-pass filter (Q = 1/J2) to 0
12.11.7 Stagger-Tuning
0
A m u c h better overall r e s p o n s e is obtained b y stagger-tuning the individual stages, as illusu-ated in Fig. 12.46. Stagger-tuned amplifiers are usually designed so that the overall response exhibits maximal flatness around the center frequency f . S u c h a r e s p o n s e can b e obtained b y transforming the response of a maximally flat (Butterworth) low-pass filter up the frequency axis to co . W e s h o w h e r e h o w this can b e d o n e . T h e transfer function of a s e c o n d - o r d e r b a n d p a s s filter can b e e x p r e s s e d in t e r m s of its poles as 0
0
1 3
The bandpass response is geometrically symmetrical around the center frequency (OQ. That is, each pair of frequencies co and 0% at which the magnitude response is equal are related by co^ = CO ,. For high Q, the symmetry becomes almost arithmetic for frequencies close to (On. That is, two frequencies with the same magnitude response are almost equally spaced from co . The same is true for higherorder bandpass filters designed using the transformation presented in this section. 2
t
T(s)
=
^
(12.111)
0
1149
1150
f.
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.11
Low-pass filter
T U N E D AMPLIFIERS
Bandpass filter
Bandpass filter
lm(p) k
p plane s plane s = p + jco
0
-x-
Re(p)
>
COQ ~2Q
*>0
2Q 1/
X
(a)
(b)
FIGURE 1 2 . 4 7 Obtaining a second-order narrow-band bandpass filter by transforming a first-order lowpass filter, (a) Pole of the first-order filter in the p plane, (b) Applying the transformation s = p + ja>o and adding a complex-conjugate pole results in the poles of the second-order bandpass filter, (c) Magnitude response of the first-order low-pass filter, (d) Magnitude response of the second-order bandpass filter.
obtain a m a x i m a l l y flat bandpass filter. If t h e 3-dB b a n d w i d t h of the bandpass filter is to be B rad/s, then the low-pass filter should h a v e a 3-dB frequency (and thus a p o l e frequency) of (B/2) rad/s, as illustrated in Fig. 12.48. T h e resulting foitrth-order b a n d p a s s filter will be a stagger-tuned one, with its t w o toned circuits (refer to Fig. 12.48) h a v i n g
~U1
R -
~~u •
j -
2j2
COo
Q
2
J2
(12.115)
B
72
B
2j2
J2
B
- 72 FT>O B
(c) (12.116)
(d)
FIGURE 1 2 . 4 8 Obtaining the poles and the frequency response of a fourth-order stagger-tuned narrow band bandpass amplifier by transforming a second-order low-pass maximally flat response.
'"
!
1151
1 1 5 2
y^'J
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.12
SPICE SIMULATION EXAMPLES
N o t e that for the overall r e s p o n s e to h a v e a n o r m a l i z e d center-frequency gain of unity, the individual r e s p o n s e s to h a v e equal center-frequency gains of as s h o w n in Fig. 12.48(d)
72,
012.36 A stagger-tuned design for the IF amplifier specified in Exercise 12.35 is required. F i n d j o B JQ , and B . Also give the value of C and R for each of the two stages. (Recall that 3-,uH inductors arc to be "•' used.).. U
h
2
2
Ans. 10.77 M H z : 141.4kHz: 10.63 M H z : 141.4kHz: 72.8 p F : 15.5 k Q : 74.7 pF; 15.1 k Q 12.37 Using the fact that the voltage gain at resonance is proportional to the value of R, find the ratio of the gain at 10.7 M H z of the stagger-tuned amplifier designed in Exercise 12.36 a n d the synchronously tuned amplifier designed i n Exercise 12.35. (Hint: For the stagger-tuned amplifier, note that the gain at On is equal to the product of the gains of the individual stages at their 3-dB frequencies.) Ans.
2.42
_"' 12.12
SPICE SIMULATION EXAMPLES
C i r c u i t s i m u l a t i o n is e m p l o y e d i n filter d e s i g n for at least t h r e e p u r p o s e s : (1) to verify the correctness of the design using ideal c o m p o n e n t s , (2) to investigate the effects of the nonideal characteristics of the o p a m p s on t h e filter r e s p o n s e , a n d (3) to d e t e r m i n e t h e percentage of circuits fabricated with practical c o m p o n e n t s , w h o s e values h a v e specified tolerance statis tics, that m e e t the design specifications (this p e r c e n t a g e is k n o w n as the yield). I n this sec tion, w e p r e s e n t t w o e x a m p l e s that illustrate t h e u s e of S P I C E for the first t w o purposes. The third area of c o m p u t e r - a i d e d design, t h o u g h very important, is a rather specialized topic, and is c o n s i d e r e d b e y o n d the scope of this textbook.
VERIFICATION OF THE DESIGN OF A FIFTH-ORDER CHEBYSHEV FILTER Our first example shows how SPICE can be utilized to verify the design of a fifth-order Chebyshev filter. Specifically, w e simulate the operation of the circuit whose component values were obtained in Exercise 12.20. The complete circuit is shown in Fig. 12.49(a). It consists of a cascade of two second-order simulated-LCR resonators using the Antoniou circuit and a firstorder op a m p - R C circuit. Using PSpice, we would like to compare the magnitude of the filter response with that computed directly from its transfer function. Here, we note that PSpice can also be used to perform the latter task by using the Laplace transfer-function block in the analogbehavioral-modeling (ABM) library. Since the purpose of the simulation is simply to verify the design, we assume ideal compo nents. For the op amps, we utilize a near-ideal model, namely, a voltage-controlled voltage source ( V C V S ) with a gain of 1 0 V/V, as shown in Fig. 1 2 . 4 9 ( b ) . 6
SPICE models for the op amp are described in Section 2.9.
14
(b) FIGURE 1 2 . 4 9 Circuits for Example 12.5. (a) Fifth-order Chebyshev filter circuit implemented as a cascade of two second-order simulated LCR resonator circuits and a single first-order op amp-RC circuit, (b) VCVS representation of an ideal op amp with gain A. In S P I C E , w e apply a 1-V ac signal at the filter input, perform an ac-analysis simulation over the range 1 H z to 2 0 k H z , and plot the output voltage magnitude versus frequency, as shown in Fig. 12.50. B o t h an expanded view of the passband and a view of the entire magnitude response are s h o w n . T h e s e results are almost identical to those computed directly from the ideal transfer function, thereby verifying the correctness of the design.
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
12.12
I
SPICE SIMULATION EXAMPLES
: 2R„
+ id
A
0
-
G
mR\
c
<*b =
VRb b
FIGURE 1 2 . 5 1 One-pole equivalent circuit macromodel of an op amp operated within its linear region.
i?! = 10 kfl
—Wv— R=
200 kfl
d
>
VA
Q = 1.59 nF
out
FIGURE 1 2 . 5 2 Circuit for Example 11.6. Second-order bandpass filter implemented with a TowThomas biquad circuit having/ = 10 kHz, Q = 20, and unity center-frequency gain. 0
INVESTIGATING THE EFFECT OF FINITE OP-AMP BANDWIDTH ON THE OPERATION OF THE TWO-INTEGRATOR-LOOP FILTER
These values result in the specified input and output resistances of the 741-type op amp. Further, they provide a dc gain A = 2.52 x 1 0 V/V and a 3-dB frequency/,, of 4 Hz, again equal to the values specified for the 7 4 1 . Note that the selection of the individual values of G , R , and C is immaterial as long as G R = A and C R = 1 / 2 nf . 5
In this example, we investigate the effect of the finite bandwidth of practical op amps on the response of a two-integrator-loop bandpass filter utilizing the T o w - T h o m a s biquad circuit of Fig. 12.25(b). The circuit is designed to provide a bandpass response w i t h / = 10 kHz, Q = 20, and a unity center-frequency gain. The op amps are assumed to be of the 741 type. Specifically, we model the terminal behavior of the op amp with the single-time-constant linear network shown in Fig. 12.51. Since the analysis performed here is a small-signal (ac) analysis that ignores nonlinearities, n o nonlinearities are included in this o p - a m p m a c r o m o d e l . (If the effects of o p - a m p nonlinearities are to be investigated, a transient analysis should be performed.) The fol lowing values are used for the parameters of the op-amp macromodel in Fig. 12.51:
0
m
m
b
0
b
b
b
b
b
0
R, =2MQ
R
G,„ = 0 . 1 9 m A / V
R = 1.323 x 1 0 Q
d
icm
= 500 rVlQ
R = 15Q. 0
9
b
Q = 30pF
The T o w - T h o m a s circuit simulated is shown in Fig. 12.52. The circuit is simulated in PSpice for two cases: (1) assuming 741-type op amps and using the linear macromodel in Fig. 12.51; and (2) assuming ideal op amps with dc gain of A = 1 0 V / V and using the near-ideal model in Fig. 12.49. In both cases, w e apply a 1-V ac signal at the filter input, perform an ac-analysis simulation over the range 8 kHz to 12 k H z , and plot the output-voltage magnitude versus frequency. 6
0
The simulation results are shown in Fig. 12.53, from which we observe the significant deviation between the response of the filter using the 741 op amp and that using the near-ideal op-amp model. Specifically, the response with practical op amps shows a deviation in the center
:)
1155
CHAPTER 12
FILTERS A N D T U N E D A M P L I F I E R S 12.12
Frequency (kHz) FIGURE 1 2 . 5 3 Comparing the magnitude response of the Tow-Thomas biquad circuit (shown in Fig. 12.52) constructed with 741-type op amps, with the ideal magnitude response. These results illustrate the effect of the finite dc gain and bandwidth of the 741 op amp on the frequency response of the TowThomas biquad circuit.
frequency of about - 1 0 0 Hz, and a reduction in the 3-dB bandwidth from 500 Hz to about 110 Hz. Thus, in effect, the filter Q factor has increased from the ideal value of 2 0 to about 90. This phenomenon, known as Q-enhancement, is predictable from an analysis of the two-integratorloop biquad with the finite op-amp bandwidth taken into account [see Sedra and Brackett (1978)]. Such an analysis shows that g - e n h a n c e m e n t occurs as a res ult of the excess phase lag introduced by the finite op-amp bandwidth. T h e theory also shows that the g-enhancement effect can be compensated for by introducing phase lead around the feedback loop. This can be accomplished by connecting a small capacitor, C , across resistor R . T o investigate the poten tial of such a compensation technique, w e repeat the PSpice simulation with various capaci tance values. T h e results are displayed in Fig. 12.54(a). W e observe that as the compensation capacitance is increased from 0 p F , both the filter Q and the resonance peak of the filter response m o v e closer to the desired values. It is evident, however, that a compensation capaci tance of 80 p F causes the response to deviate further from the ideal. Thus, o p t i m u m compensa tion is obtained with a capacitance value between 60 and 80 pF. Further experimentation using PSpice enabled us to determine that such an optimum is obtained with a compensation capacitance of 64 p F . T h e corresponding response is shown, together with the ideal response, in Fig. 12.54(b). W e note that although the filter Q has been restored to its ideal value, there remains a deviation in the center frequency. W e shall not pursue this matter any further here; our objective is not to present a detailed study of the design of two-integrator-loop biquads; rather, it is to illustrate the application of S P I C E in investigating the nonideal performance of active-filter circuits, generally. c
2
SPICE S I M U L A T I O N E X A M P L E S
1157
1158
CHAPTER 12
,
FILTERS A N D T U N E D
AMPLIFIERS PROBLEMS
SUMMARY B
A filter is a linear two-port network with a transfer function T(s) = V (s)/Vj(s). For physical frequencies, the filter transmission is expressed as T(jco) = \T(jco)\e ' ' . The magnitude of transmission can be expressed in decibels us ing either the gain function G(co) = 20 log|T| or the atten uation function A(co) = - 2 0 log|T\.
Fig. 12.20(a), the op amp-RC resonator of Fig. 12.21(b) is obtained. This resonator can be used to realize the various second-order filter functions as shown in Fig. 12.22. The design equations for these circuits are given in Table 12.1.
Jlf ( Cl)
fi
The transmission characteristics of a filter are specified in terms of the edges of the passband(s) and the stopband(s); the maximum allowed variation in passband transmission, A (dB): and the minimum attenuation required in the stopband, A (dB). In some applications, the phase char acteristics are also specified. m a x
Ma
B
a
B
B
S
•
•
•
1 1 5 9
PROBLEMS
B
•
_
The filter transfer function can be expressed as the ratio of two polynomials in s; the degree of the denominator poly nomial, N, is the filter order. The N roots of the denomi nator polynomial are the poles (natural modes). To obtain a highly selective response, the poles are com plex and occur in conjugate pairs (except for one real pole when N is odd). The zeros are placed on the jco axis in the stopband(s) including co = 0 and co = °o. The Butterworth filter approximation provides alow-pass response that is maximally flat at ft) = 0. The transmission decreases monotonically as co increases, reaching 0 (infi nite attenuation) at co = <*=, where all N transmission zeros lie. Eq. (12.11) gives \T\, where e is given by Eq. (12.14) and the order Nis determined using Eq. (12.15). The poles are found using the graphical construction of Fig. 12.10, and the transfer function is given by Eq. (12.16). The Chebyshev filter approximation provides a low-pass response that is equiripple in the passband with the trans mission decreasing monotonically in the stopband. All the transmission zeros are at.? = Eq. (12.18) gives \T\ in the passband and Eq. (12.19) gives \T\ in the stopband, where e is given by Eq. (12.21). The order N can be determined using Eq. (12.22). The poles are given by Eq. (12.23) and the transfer function by Eq. (12.24).
•
•
The second-order LCR resonator of Fig. 12.17(a) realizes a pair of complex-conjugate poles with cog = 1/JL~C and Q = cOnCR. This resonator can be used to realize the various spe cial second-order filtering functions, as shown in Fig. 12.18. By replacing the inductor of an LCR resonator with a sim ulated inductance obtained using the Antoniou circuit of
Single-amplifier biquads (SABs) are obtained by placing a bridged-T network in the negative-feedback path of an op amp. If the op amp is ideal, the poles realized are at the same locations as the zeros of the RC network. The com plementary transformation can be applied to the feedback loop to obtain another feedback loop having identical poles. Different transmission zeros are realized by feeding the input signal to circuit nodes that are connected to ground. SABs are economic in their use of op amps but are sensitive to the op-amp nonidealities and are thus lim ited to l o w - g applications (Q < 10).
of the following cases: (a) The transmission zeros are all at 5 = 0 ° and the dc gain is unity.
12.1 The transfer function of a first-order low-pass filter (such as that realized by an R C circuit) can be expressed as T(s) = co /(s+ a ), where co is the 3-dB frequency of the filter. Give in table form the values of | 7 j , (j>, G, and A at co = 0, 0.5ft) , co , Icon, 5co , 10G) , and 100ft> . 0
0
0
0
(b) T h e transmission zeros are all at s = 0 and the highfrequency gain is unity.
0
0
0
What type of filter results in each case?
0
* 1 2 . 2 A filter has the transfer function T(s) = \/[(s + 1) ( s + s + I)]. Show that \T\ - Jl + co and find an expres sion for its phase response (pica). Calculate the values of \T\ and
12.9 A third-order low-pass filter has transmission zeros at ( 0 = 2 rad/s and co = °°. Its natural modes are at s = - 1 and s = - 0 . 5 + 7O.8. The dc gain is unity. Find T(s).
6
(a) 2 sin 0.If (volts) (b) 2 sin t (volts) (c) 2 sin 10f (volts)
1 2 . 1 0 Find the order N and the form of T(s) of a bandpass filter having transmission zeros as follows: one at 0 ) = 0, one at CO = 1 0 rad/s, one at 3 X 1 0 rad/s, one at 6 X 1 0 rad/s, and one at ft) = If this filter has a monotonically decreas ing passband transmission with a peak at the center frequency of 2 X 1 0 rad/s, and equiripple response in the stopbands, sketch the shape of its 3
3
3
3
12.3 For the filter whose magnitude response is sketched (as the colored curve) in Fig. 12.3 find \T\ at co = 0, co = co , and co = co . A = 0.5 dB, and A ^ = 40 dB. p
s
m a x
0 1 2 . 4 A low-pass filter is required to pass all signals within its passband, extending from 0 to 4 kHz, with a trans mission variation of at most 10% (i.e., the ratio of the maxi mum to minimum ttansmission in the passband should not exceed 1.1). The transmission in the stopband, which extends from 5 kHz to °°, should not exceed 0.1 % of the maximum passband transmission. What are the values of A , A^, and the selectivity factor for this filter?
• 1 2 . 1 1 Analyze the RLC network of Fig. P 1 2 . l l to deter mine its transfer function VJs)/V {s) and hence its poles and zeros. (Hint: Begin the analysis at the output and work your way back to the input.) t
m a x
V,
The classical sensitivity function 12.5 A low-pass filter is specified to have A = 1 dB and Ami,, = 10 dB. It is found that these specifications can be just met with a single-time-constant RC circuit having a time con stant of 1 s and a dc transmission of unity. What must co and co of this filter be? What is the selectivity factor? m a x
y
dy/y dx/x
=
s
x
is a very useful tool in investigating how tolerant a filter circuit is to the unavoidable inaccuracies in component values and to the nonidealities of the op amps. a
Figures 12.13 and 12.14 provide a summary of first-order filter functions and their realizations. Figure 12.16 provides the characteristics of seven special second-order filtering functions.
Biquads based on the two-integrator-loop topology are the most versatile and popular second-order filter real izations. There are two varieties: the K H N circuit of Fig. 12.24(a), which realizes the LP, BP, and H P func tions simultaneously and can be combined with the output summing amplifier of Fig. 12.28(b) to realize the notch and all-pass functions; and the Tow-Thomas circuit of Fig. 12.250?), which realizes the BP and LP functions simul taneously. Feedforward can be applied to the Tow-Thomas circuit to obtain the circuit of Fig. 12.26, which can be de signed to realize any of the second-order functions (see Table 12.2).
SECTION 1 2 . 1 : FILTER T R A N S M I S S I O N , TYPES AND SPECIFICATION
Switched-capacitor (SC) filters are based on the principle that a capacitor C, periodically switched between two cir cuit nodes at a high rate,/ , is equivalent to a resistance R = \ICf connecting the two circuit nodes. SC filters can be fabricated in monolithic form using CMOS IC technology. c
c
FIGURE P I 2 . 1 1
p
s
12.6 Sketch transmission specifications for a high-pass fil ter having a passband defined by / > 2 kHz and a stopband defined by f< 1 kHz. A = 0.5 dB, and A = 50 dB. m 3 x
min
SECTION 1 2 . 3 : BUTTERWORTH A N D CHEBYSHEV FILTERS D12.12 Determine the order N of the Butterworth filter for which A = 1 dB, A^ > 20 dB, and the selectivity ratio co /co = 1.3. What is the actual value of minimum stopband attenuation realized? If A is to be exactly 20 dB, to what m a x
s
12.7 Sketch transmission specifications for a bandstop filter that is required to pass signals over the bands 0 < / < 10 kHz and 20 kHz with A of 1 dB. The stopband extends from / = 12 kHz to / = 16 kHz, with a minimum required attenuation of 40 dB.
p
m i n
m a x
•
Tuned amplifiers utilize LC-tuned circuits^as loads, or at the input, of transistor amplifiers. They are used in the design of the R F tuner and the IF amplifier of communi cation receivers. The cascode and the C C - C B cascade configurations are frequently used in the design of tuned amplifiers. Stagger-tuning the individual tuned circuits re sults in a flatter passband response (in comparison to that obtained with all the tuned circuits synchronously tuned).
SECTION 1 2 . 2 : THE FILTER TRANSFER FUNCTION 12.8 Consider a fifth-order filter whose poles are all at a radial distance from the origin of 10 rad/s. One pair of com plex conjugate poles is at 18° angles from the jco axis, and the other pair is at 54° angles. Give the transfer function in each 3
1 2 . 1 3 Calculate the value of attenuation obtained at a frequency 1.6 times the 3-dB frequency of a seventh-order Butterworth filter. 1 2 . 1 4 Find the natural modes of a Butterworth filter with a 1-dB bandwidth of 10 rad/s and JV = 5. 3
0 1 2 . 1 5 Design a Butterworth filter that meets the follow ing low-pass specifications:^ = 10 kHz, A = 2 dB,/ = 15 kHz, and A = 15 dB. Find N, the natural modes, and T(s). What is the attenuation provided at 20 kHz? m a x
mia
s
1160
I
CHAPTER 12
FILTERS A N D T U N E D AMPLIFIERS
» 1 2 . 1 6 Sketch |T| for a seventh-order low-pass Chebyshev filter with co = 1 rad/s and A = 1 dB. Use Eq. (12.18) to determine the values of co at which \T\ = 1 and the values of co at which \T\ = l/Jl+~e . Indicate these values on your sketch. Use Eq. (12.19) to determine|7j at ft) = 2 rad/s, and indicate this point on your sketch. For large values of co, at what rate (in dB/octave) does the transmission decrease? p
m a x
2
1 2 . 1 7 Contrast the attenuation provided by a fifth-order Chebyshev filter at co = 2co to that provided by a Butterworth filter of equal order. For both, A = 1 dB. Sketch \T\ for both filters on the same axes. s
p
m a x
PROBLEMS
range 0 to 180° (with 0° at high frequencies and 180° at low frequencies). 1 2 . 2 5 Use the information in Fig. 12.16(a) to obtain the transfer function of a second-order low-pass filter with 0% = 10 rad/s, Q = 1, and dc gain = 1. At what frequency does |T| peak? What is the peak transmission? 3
0 * * * 1 2 . 2 6 Use the information in Fig. 12.16(a) to obtain the transfer function of a second-order low-pass filter that just meets the specifications defined in Fig. 12.3 with co = l rad/s and A = 3 dB. Note that there are two possible solutions. For each, find CQn and Q. Also, if co = 2 rad/s, find the value of A obtained in each case. p
m a x
s
D * l 2 . 1 8 It is required to design a low-pass filter to meet the following specifications: f = 3.4 kHz, A = 1 dB,/ = 4kHz,A = 35 dB. p
m a x
s
m i n
(a) Find the required order of Chebyshev filter. What is the excess (above 35 dB) stopband attenuation obtained? (b) Find the poles and the transfer function. SECTION 1 2 . 4 : FIRST-ORDER AND
1Ilin
D * * 1 2 . 2 7 Use two first-order op amp-RC all-pass circuits in cascade to design a circuit that provides a set of threephase 60-Hz voltages, each separated by 120° and equal in magnitude, as shown in the phasor diagram of Fig. P12.27. These voltages simulate those used in three-phase power transmission systems. Use 1-LLF capacitors.
zeros being slightly lower than that of the poles. Roughly sketch the expected |71. Repeat for the case of the frequency of the zeros slightly higher than the frequency of the poles. 1 2 . 3 2 Consider a second-order all-pass filter in which errors in the component values result in the Q factor of the zeros being greater than the Q factor of the poles. Roughly sketch the expected |T|. Repeat for the case of the Q factor of the zeros lower than the Q factor of the poles. SECTION 1 2 . 5 : THE SECOND-ORDER LCR RESONATOR 4
1 2 . 3 4 For the LCR resonator of Fig. 12.17(a) find the change in C0Q that results from: (a) increasing L by 1% (b) increasing C by 1% (c) increasing 7? by 1% a
D 1 2 . 1 9 Use the information displayed in Fig. 12.13 to design a first-order bp amp-RC low-pass filter having a 3-dB frequency of 10 kHz, a dc gain magnitude of 10, and'an input resistance of 10 kQ. D 1 2 . 2 0 Use the information given in Fig. 12.13 to design a first-order op amp-RC high-pass filter with a 3-dB frequency of 100 Hz, a high-frequency input resistance of 100 kQ, and a high-frequency gain magnitude of unity.
D * 1 2 . 2 2 By cascading a first-order op amp-RC low-pass cir- cuit with a first-order op amp-RC high-pass circuit one can design a wideband bandpass filter. Provide such a design for the case in which the midband gain is 12 dB and the 3-dB bandwidth extends from 100 Hz to 10 kHz. Select appropriate component values under the constraint that no resistors higher than 100 kQ are to be used, and that the input resistance is to be as high as possible. D 1 2 . 2 3 Derive T(s) for the op amp-RC circuit in Fig. 12.14. We wish to use this circuit as a variable phase shifter by adjusting R. If the input signal frequency is 10 rad/s and if C = 10 nF, find the values of R required to obtain phase shifts of -30°, -60°, - 9 0 ° , -120°, and -150°. 4
1 2 . 2 4 Show that by interchanging R and C in the op a m p RC circuit of Fig. 12.14, the resulting phase shift covers the
t
of the high-pass
D 1 2 . 3 6 Use the circuit of Fig. 12.18(b) to design a lowpass filter with COQ = 1 0 rad/s and Q = 1/J2. Utilize a 0.1-/ZF capacitor. 5
D 1 2 . 3 7 Modify the bandpass circuit of Fig. 12.18(d) to change its center-frequency gain from 1 to 0.5 without chang ing co or Q. 0
V
2
D * 1 2 . 2 1 Use the information given in Fig. 12.13 to design a first-order op amp-RC spectrum-shaping network with a transmission zero frequency of 1 kHz, a pole frequency of 100 kHz, and a dc gain magnitude of unity. The low-frequency input resistance is to be 1 kQ. What is the high-frequency gain that results? Sketch the magnitude of the transfer function versus frequency.
FIGURE P I 2 . 2 7
D 1 2 . 4 3 Design the circuit of Fig. 12.22(e) to realize an LPN function w i t h / = 4 kHz,/„ = 5 kHz, Q = 10, and a unity dc gain. Select C = 10 nF. 0
4
D 1 2 . 4 4 Design the all-pass circuit of Fig. 12.22(g) to pro vide a phase shift of 180° a t / = 1 kHz and to have Q = 1. Use 1-nF capacitors. 1 2 . 4 5 Consider the Antoniou circuit of Fig. 12.20(a) with R eliminated, a capacitor C connected between node 1 and ground, and a voltage source V" connected to node 2. Show that the input impedance seen by V is R /s C C R R . How does this impedance behave for physical frequencies (s =jco)l (This impedance is known as a frequency-dependent nega 6
2
2
2
2
4
6
1
i
tive resistance, or FDNR.)
D 1 2 . 4 6 Using the transfer function of the LPN filter, given in Table 12.1, derive the design equations also given.
1 2 . 3 5 Derive an expression for V (s)/V (s) circuit in Fig. 12.18(c).
SECOND-ORDER FILTER FUNCTIONS
1161
Fig. 12.22(a) and a first-order op amp-RC circuit of the type shown in Fig. 12.13(a). Select appropriate component values.
s
D 1 2 . 3 3 Design the LCR resonator of Fig. 12.17(a) to obtain natural modes with cog = 10 rad/s and Q = 2. Use R = 10 kQ.
i _ |
1 2 . 1 8 Consider the LCR resonator of Fig. 12.17(a) with node x disconnected from ground and connected to an input signal source V , node y disconnected from ground and con nected to another input signal source V , and node z discon nected from ground and connected to a third input signal source V.. Use superposition to find the voltage that develops across the resonator, V„, in terms of V , V , and V .
D 1 2 . 4 7 Using the transfer function of the HPN filter, given in Table 12.1, derive the design equations also given. 0 * * 1 2 . 4 8 It is required to design a third-order low-pass filter whose \T\ is equiripple in both the passband and the stopband (in the manner shown in Fig. 12.3, except that the response shown is for N = 5). The filter passband extends from co = 0 to co = 1 rad/s and the passband transmission var ies between 1 and 0.9. The stopband edge is at co = 1.2 rad/s. The following transfer function was obtained using filter design tables: r
(
j
)
0 . 4 5 0 8 ( / + 1.6996)
=
x
1 2 . 2 8 Use the information given in Fig. 12.16(b) to find the transfer function of a second-order high-pass filter with natural modes at - 0 . 5 + jj3/2 and a high-frequency gain of unity. D * * 1 2 . 2 9 (a) Show that |7j of a second-order bandpass function is geometrically symmetrical around the center fre quency con- That is, the members of each pair of frequencies C0i and ft> for which \T(jC0i)\ = \T(ja>2)\ are related by co co = co\. 2
x
2
(b) Find the transfer function of the second-order bandpass filter that meets specifications of the form in Fig. 12.4 where co = 8100 rad/s, co = 10,000 rad/s, and A = 1 dB. If co = 3000 rad/s find A and co . pl
p2
Mn
m a x
sl
2
( J + 0.7294)(.j + ^0.2786 + 1.0504)
y
x
y
z
4
The actual filter realized is to have co = 10 rad/s. p
(a) Obtain the transfer function of the actual filter by replac ing s by s / 1 0 . 03) Realize this filter as the cascade connection of a first-order LP op amp-RC circuit of the type shown in Fig. 12.13(a) and a second-order LPN circuit of the type shown in Fig. 12.22(e). Each section is to have a dc gain of unity. Select appropri ate component values. (Note: A filter with an equiripple response in both the passband and the stopband is known as 4
1 2 . 3 9 Consider the notch circuit shown in Fig. 12.18(f). For what ratio of L to L does the notch occur at 0 . 9 o ? For this case, what is the magnitude of the transmission at fre quencies
0
SECTION 1 2 . 6 :
2
0
0
SECOND-ORDER ACTIVE
FILTERS BASED ON INDUCTOR REPLACEMENT
an elliptic
filter.)
s2
D * 1 2 . 3 0 Use the result of Exercise 12.15 to find the trans fer function of a notch filter that is required to eliminate a both ersome interference of 60-Hz frequency. Since the frequency of the interference is not stable, the filter should be designed to provide attenuation >20 dB over a 6-Hz band centered around 60 Hz. The dc transmission of the filter is to be unity. 1 2 . 3 1 Consider a second-order all-pass circuit in which errors in the component values result in the frequency of the
D 1 2 . 4 0 Design the circuit of Fig. 12.20 (utilizing suitable component values) to realize an inductance of (a) 10 H, (b) 1 H, and (c) 0.1 H. * 1 2 . 4 1 Starting from first principles and assuming ideal op amps, derive the transfer function of the circuit in Fig. 12.22(a). D * 1 2 . 4 2 It is required to design a fifth-order Butterworth filter having a 3-dB bandwidth of 1 0 rad/s and a unity dc gain. Use a cascade of two circuits of the type shown in 4
SECTION 1 2 . 7 : SECOND-ORDER ACTIVE FILTERS BASED ON THE TWO-INTEGRATORLOOP TOPOLOGY D 1 2 . 4 9 Design the KHN circuit of Fig. 12.24(a) to realize a bandpass filter with a center frequency of 1 kHz and a 3-dB bandwidth of 50 Hz. Use 10-nF capacitors. Give the complete circuit and specify all component values. What value of centerfrequency gain is obtained?
11
CHAPTER 12
6 2
FILTERS A N D T U N E D AMPLIFIERS
D 1 2 . 5 0 (a) Using the KHN biquad with the output summing amplifier of Fig. 12.24(b) show that an all-pass function is realized by selecting R = R = R /Q . Also show that the flat gain obtained is KR /R . (b) Design the all-pass circuit to obtain C0 = 10 rad/s, 2 = 2, and flat gain = 10. Select appropriate component values. L
H
F
B
H
PROBLEMS
frequency gain of the circuit? Design the circuit for a maximally flat response with a 3-dB frequency of 10 rad/s. Use Cj = C = 10 nF. (Hint: For a maximally flat response, Q = 1//2 and ft) = ft*,.) 3
2
3dB
4
0
D 1 2 . 5 1 Consider a notch filter with co„ = ah realized using the KHN biquad with an output summing amplifier. If the summing resistors used have 1% tolerances, what is the worst-case percentage deviation between co and ft) ? n
0
D 1 2 . 5 2 Design the circuit of Fig. 12.26 to realize a lowpass notch filter with cth = 1 0 rad/s, Q = 10, dc gain = 1, and co = 1.2 x 1 0 rad/s. Use C = 10 nF and r = 20 kii. 4
4
n
D 1 2 . 5 3 In the all-pass realization using the circuit of Fig. 12.26, which component(s) does one need to trim to adjust (a) only co and (b) only Q l z
SECTION 1 2 . 8 :
0
2
1 2 . 5 6 Consider the bridged-T network of Fig. 12.28(a) with R =R = R and C = C = C, and denote CR = T. Find the zeros and poles of the bridged-T network. If the network is placed in the negative-feedback path of an ideal infinite-gain op amp, as in Fig. 12.29, find the poles of the closed-loop amplifier. 2
* 1 2 . 5 7 Consider the bridged-T network of Fig. 12.28(b) with Ri = R = R, C = C, and C = C / 1 6 . Let the network be placed in the negative-feedback path of an infinite-gain op amp and let C be disconnected from ground and connected to the input signal source V . Analyze the resulting circuit to determine its transfer function V (s)/V,(s), where V (s) is the voltage at the op-amp output. Show that the circuit realized is a bandpass filter and find its cth, Q, and the center-frequency gain. 2
4
3
4
t
0
0
D * * 1 2 . 5 8 Consider the bandpass circuit shown in Fig. 12.30. Let Q = C = C, R = R,R = R/4Q , CR = 2Q/co , and a = 1. Disconnect the positive input terminal of the op amp from ground and apply V through a voltage divider R R to the positive input terminal. Analyze the circuit to find its transfer function V /V-i. Find the voltage divider ratio R /(R +R ) so that the circuit realizes (a) an all-pass function and (b) a notch function. Assume the op amp to be ideal. 2
3
4
;
0
1 2 . 6 2 Evaluate the sensitivities of ah and Q relative to R, L, and C of the bandpass circuit in Fig. 12.18(d).
y
4
x
SENSITIVITY
(a) If y = uv, then S
D 1 2 . 5 5 Design the circuit of Fig. 12.29 to realize a pair of poles with ft) = 1 0 rad/s and Q = 1 A / 2 . Use Q = C = 1 nF.
2
SECTION 1 2 . 9 :
* 1 2 . 6 3 Verify the following sensitivity identities:
SINGLE-AMPLIFIER
BIQUADRATIC ACTIVE FILTERS
2
1 2 . 6 1 The process of obtaining the complement of a transfer function by interchanging input and ground, as illustrated in Fig. 12.31, applies to any general network (not just RC networks as shown). Show that if the network n is a bandpass with a center-frequency gain of unity, then the complement obtained is a notch. Verify this by using the RLC circuits of Fig. 12.18(d) and (e).
would you expect in the output for each cycle of the clock? For an amplifier that saturates at ±10 V and the feedback capacitor initially discharged, how many clock cycles would it take to saturate the amplifier? What is the average slope of the staircase output voltage produced?
(b) Use the result obtained in (a) to show that the 3-dB bandwidth B, of N synchronously tuned sections connected in cascade, is
D 1 2 . 6 9 Repeat Exercise 12.31 for a clock frequency of 400 kHz.
* * 1 2 . 7 7 (a) Using the fact that for Q > 1 the secondorder bandpass response in the neighborhood of co is the same as the response of a first-order low-pass with 3-dB frequency of (co /2Q), show that the bandpass response at ft) = O) + 5ft), for Sa> < co , is given by
P 1 2 . 7 0 Repeat Exercise 12.31 for Q = 40.
u
v
= S + S.
x
x
y
(b) If y = u/v, then S
x
= S" -
x
x
x
3
4
5
3iB
0
SECTION 1 2 . 1 1 : TUNED AMPLIFIERS
=
x
(d) If y = u", where n is a constant, then S
S. x
= nS" .
x
x
2
2
l
2
D* 1 2 . 5 9 Derive the transfer function of the circuit in Fig. 12.33(b) assuming the op amp to be ideal. Thus show that the circuit realizes a high-pass function. What is the high-
p
1 2 . 7 3 A coil having an inductance of 10 LtH is intended for applications around 1-MHz frequency. Its Q is specified to be 200. Find the equivalent parallel resistance R . What is the value of the capacitor required to produce resonance at 1 MHz? What additional parallel resistance is required to produce a 3-dB bandwidth of 10 kHz? p
y
(e) If y =f (u) and u =f (x), then S 1
2
y
x
= S -S . u
x
* 1 2 . 6 4 For the high-pass filter of Fig. 12.33(b), what are the sensitivities of ah and Q to amplifier gain A? * 1 2 . 6 5 For the feedback loop of Fig. 12.34(a), use the expressions in Eqs. (12.77) and (12.78) to determine the sensitivities of (On and Q relative to all passive components for the design in which R = R . x
1 2 . 7 4 An inductance of 36 u\\ is resonated with a 1000-pF capacitor. If the inductor is tapped at one-third of its turns and a 1-kQ resistor is connected across the one-third part, f i n d / and Q of the resonator.
1 2 . 6 6 For the op a m p - R C resonator of Fig. 12.21(b), use the expressions for Oh and Q given in the top row of Table 12.1 to determine the sensitivities of Oh and Q to all resistors and capacitors.
* 1 2 . 7 5 Consider a common-emitter transistor amplifier loaded with an inductance L. Ignoring r and r„ show that for coC^ 1/coL, the amplifier input admittance is given by a
2
^--(o C Lg ) p
SECTION 1 2 . 1 0 :
0
\T(jCOn)\
\T(jCO)\
2
2
Jl+4Q (8co/co ) 0
(b) Use the relationship derived in (a) together with Eq. (12.110) to show that a bandpass amplifier with a 3-dB bandwidth B, designed using N synchronously tuned stages, has an overall transfer function given by \T(Jco )\ 0
\T(jco) [1+4(2
c
2 /2
-l)(Sco/B) f
(c) Use the relationship derived in (b) to find the attenuation (in decibels) obtained at a bandwidth 2B for N= 1 to 5. Also find the ratio of the 30-dB bandwidth to the 3-dB bandwidth for/V=lto5. * 1 2 . 7 8 This problem investigates the selectivity of maximally flat stagger-tuned amplifiers derived in the manner illustrated in Fig. 12.48. (a) The low-pass maximally flat (Butterworth) filter having a 3-dB bandwidth B/2 and order N has the magnitude response |Z1 =
1/1
KB/2J
0
2
+
m
jco(C +C ) n
where Q = Im(p) is the frequency in the low-pass domain. (This relationship can be obtained using the information provided in Section 12.3 on Butterworth filters.) Use this expression to obtain for the corresponding bandpass filter at co = co + 8a>, where 8co < co , the relationship 0
0
1
fl
SWITCHED-CAPACITOR
FILTERS
0
u
* 1 2 . 7 2 A voltage signal source with a resistance A\ = 10 kQ is connected to the input of a common-emitter BJT amplifier. Between base and emitter is connected a tuned circuit w i t h i = 1 uH and C = 200 pF. The transistor is biased at 1 mA and has ¡5 = 200, C„ = 10 pF, and C = 1 pF. The transistor load is a resistance of 5 kO. Find Oh, Q, the 3-dB bandwidth, and the center-frequency gain of this single-tuned amplifier.
x
y
0
2
6
v
y
n
Q
4
S.
(c) If y = ku, where k is a constant, then S
((O /Q)W^- 1
B =
0
P 1 2 . 7 1 Design the circuit of Fig. 12.37(b) to realize, at the output of the second (noninverting) integrator, a maximally flat low-pass function with OhdB = 1 0 rad/s and unity dc gain. Use a clock frequency/,. = 100 kHz and select C = C = 10 pF. Give the values of C , C , C , and C . (Hint: For a maximally flat response, Q = 1/72 and w = a> .)
z
D * * 1 2 . 5 4 Repeat Problem 12.48 using the Tow-Thomas biquad of Fig. 12.26 to realize the second-order section in the cascade.
x
D* 1 2 . 6 0 Design a fifth-order Butterworth low-pass filter with a 3-dB bandwidth of 5 kHz and a dc gain of unity using the cascade connection of two Sallen-and-Key circuits (Fig. 12.34c) and a first-order section (Fig. 12.13a). Use a 10-kQ value for all resistors.
1163
1 2 . 6 7 For the switched-capacitor input circuit of Fig. 12.35(b), in which a clock frequency of 100 kHz is used, what input resistances correspond to capacitance C values of 1 pF and 10 pF? x
Note: The real part of the input admittance can be negative. This can lead to oscillations. * 1 2 . 7 6 (a) Substituting s = jco in the transfer function T(s) of a second-order bandpass filter (see Fig. 12.16c), find \T(jm)\. For o in the vicinity of con [i.e., co= ch+ 8co= ah(l + 8co/co ), where 8co/co ^ 1 so that ft) = a>l(l +28co/co )], show that, for Q > 1, 0
2
1 2 . 6 8 For a dc voltage of 1 V applied to the input of the circuit of Fig. 12.35(b), in which Q is 1 pF, what charge is transferred for each cycle of the two-phase clock? For a 100-kHz clock, what is the average current drawn from the input source? For a feedback capacitance of 10 pF, what change
a
0
\T(jco)\
\T(jco )\ 0
= JI +
2
4Q (8co/co ) 0
(b) Use the transfer function in (a) to find the attenuation (in decibels) obtained at a bandwidth of IB forN= 1 to 5. Also find the ratio of the 30-dB bandwidth to the 3-dB bandwidth f o r / v = 1 to 5. * * 1 2 . 7 9 Consider a sixth-order stagger-tuned bandpass amplifier with center frequency co and 3-dB bandwidth B. The poles are to be obtained by shifting those of the thirdorder maximally flat low-pass filter, given in Fig. 12.10(c). For the three resonant circuits, find ah, the 3-dB bandwidth, andCJ. Q
Signal Generators and Waveform-Shaping Circuits Introduction 13.1
13.7
1166
Op-Amp-RC Circuits
13.S
1171
13.9
13.3
L C and Crystal Oscillators
13.4
Bistable Multivibrators
13.5
G e n e r a t i o n of S q u a r e and
1179 1185
Triangular W a v e f o r m s Using
13.6
1198
Nonlinear WavclorinShaping Circuits
Oscillator
Astable Multivibrators
Integrated-Circuit Timers
B a s i c P r i n c i p l e s of S i n u s o i d a l Oscillators
13.2
1165
1192
1203
Precision Rectifier Circuits
1206
13.10 S P I C E Simulation Examples
1214
Summary
1219
Problems
1220
G e n e r a t i o n of a S t a n d a r d i z e d Pulse—The Monostable Multivibrator
1196
INTRODUCTION In the design of electronic s y s t e m s the n e e d frequently arises for signals h a v i n g p r e s c r i b e d standard w a v e f o r m s , for e x a m p l e , sinusoidal, square, triangular, or pulse. S y s t e m s in w h i c h standard signals are required include computer-and control s y s t e m s w h e r e clock pulses are n e e d e d for, a m o n g other things, timing"; c o m m u n i c a t i o n s y s t e m s w h e r e signals of a variety of w a v e f o r m s are utilized as information carriers; and test a n d m e a s u r e m e n t systems w h e r e signals, again of a variety of w a v e f o r m s , are e m p l o y e d for testing and characterizing e l e c tronic devices a n d circuits. In this chapter w e study signal-generator circuits. T h e r e are t w o distinctly different a p p r o a c h e s for t h e generation of sinusoids, p e r h a p s t h e m o s t c o m m o n l y u s e d of the standard waveforms. T h e first approach, studied in Sections 13.1
1 1 6 5
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
13.1
to 1 3 . 3 , e m p l o y s a p o s i t i v e - f e e d b a c k l o o p c o n s i s t i n g of a n amplifier a n d a n R C o r L C f r e q u e n c y - s e l e c t i v e n e t w o r k . T h e a m p l i t u d e of t h e g e n e r a t e d sine w a v e s is limited, or set, u s i n g a nonlinear m e c h a n i s m , i m p l e m e n t e d either w i t h a separate circuit or u s i n g t h e nonlinearities of t h e amplifying device itself. I n spite of this, these circuits, w h i c h generate sine w a v e s utilizing r e s o n a n c e p h e n o m e n a , are k n o w n as linear oscillators. T h e n a m e clearly distinguishes t h e m from t h e circuits that g e n e r a t e sinusoids b y w a y of t h e s e c o n d approach. In these circuits, a sine w a v e is obtained b y appropriately shaping a triangular waveform. W e study w a v e f o r m - s h a p i n g circuits i n Section 13.9, following t h e study of triangularw a v e f o r m generators. C i r c u i t s that g e n e r a t e s q u a r e , t r i a n g u l a r , p u l s e (etc.) w a v e f o r m s , c a l l e d n o n l i n e a r oscillators or function generators, e m p l o y circuit building blocks k n o w n as multivibrators. T h e r e are three types of multivibrator: t h e bistable (Section 13.4), t h e astable (Section 13.5), and t h e m o n o s t a b l e (Section 13.6). T h e multivibrator circuits presented in this chapter e m p l o y o p a m p s a n d a r e i n t e n d e d for p r e c i s i o n a n a l o g a p p l i c a t i o n s . M u l t i v i b r a t o r circuits u s i n g digital logic gates w e r e studied i n C h a p t e r 1 1 . A general a n d versatile s c h e m e for t h e generation of square a n d triangular w a v e f o r m s is o b t a i n e d b y c o n n e c t i n g a bistable multivibrator a n d an o p - a m p integrator in a feedback loop (Section 13.5). Similar results c a n b e o b t a i n e d u s i n g a c o m m e r c i a l l y available versatile I C chip, t h e 5 5 5 timer (Section 13.7). T h e chapter includes also a study of precision circuits that i m p l e m e n t t h e rectifier functions i n t r o d u c e d i n /Chapter 3 . T h e circuits studied here (Section 13.9), h o w e v e r , a r e i n t e n d e d for applications that d e m a n d precision, such as in instrumeijtation s y s t e m s , including w a v e f o r m generation. T h e chapter c o n c l u d e s with e x a m p l e s Illustrating t h e u s e of S P I C E i n t h e simulation of oscillator circuits.
:* ^ r-J +
.\n:p!!!!^i
^
1
—*
network ft FIGURE 13.1 The basic structure of a sinusoidal oscillator. A positive-feedback loop is formed by an amplifier and a frequency-selective network. In an actual oscillator circuit, no input signal will be present; here an input signal x is employed to help explain the principle of operation. s
A c c o r d i n g t o t h e definition of l o o p g a i n i n C h a p t e r 8, t h e l o o p g a i n of t h e circuit in F i g . 13.1 is -A(s)B(s). H o w e v e r , for o u r p u r p o s e s h e r e it is m o r e c o n v e n i e n t t o d r o p t h e m i n u s sign a n d define t h e l o o p gain L(s) as L(s) ^ A(s)B(s) T h e characteristic equation thus b e c o m e s 1-/J» = 0
13.1.1 The Oscillator Feedback Loop
1
N o t e that this n e w definition of loop g a i n corresponds directly to t h e actual gain seen a r o u n d the feedback l o o p of F i g . 1 3 . 1 .
If at a specific frequency f t h e l o o p gain Aj5 is equal t o unity, it follows from Eq. (13.1) that Ay, will b e infinite. T h a t is, at this frequency t h e circuit will have a finite output for zero i n p u t signal. S u c h a circuit is b y definition an oscillator. T h u s t h e condition for t h e feedback l o o p of F i g . 13.1 t o p r o v i d e sinusoidal oscillations of frequency co is 0
L(jco )=A(jco )B(jco ) 0
0
(13.4)
0
0
T h e b a s i c structure of a s i n u s o i d a l oscillator c o n s i s t s of an amplifier a n d a f r e q u e n c y s e l e c t i v e n e t w o r k c o n n e c t e d i n a positive-feedback l o o p , such as that s h o w n in b l o c k d i a g r a m form in F i g . 1 3 . 1 . A l t h o u g h i n an actual oscillator circuit, n o input signal will b e present, w e include an input signal h e r e t o h e l p explain t h e principle of operation. It is i m p o r t a n t t o n o t e that u n l i k e t h e n e g a t i v e - f e e d b a c k l o o p of Fig. 8.1, h e r e t h e f e e d b a c k signal is s u m m e d w i t h a positive sign. T h u s t h e gain-wifh-feedback is g i v e n b y )
^ ,
w h e r e w e n o t e t h e n e g a t i v e sign in t h e d e n o m i n a t o r .
(13.1)
f
"
-V
- fix.,
should b e sufficiently large that w h e n multiplied b y . \ it p r o d u c e s x , that i s , 0
AXJ
1 (
=l
0
T h a t is, at (0 the phase of the loop gain should be zero and the magnitude of the loop gain should be unity. T h i s is k n o w n as t h e B a r k h a u s e n criterion. N o t e that for t h e circuit t o oscillate at o n e frequency, t h e oscillation criterion should b e satisfied only at o n e frequency (i.e., (On); o t h e r w i s e t h e resulting w a v e f o r m will n o t b e a s i m p l e sinusoid. A n intuitive feeling for t h e B a r k h a u s e n criterion c a n b e gained b y considering o n c e m o r e t h e f e e d b a c k l o o p of F i g . 1 3 . 1 . F o r this l o o p to produce a n d sustain an output x w i t h n o input applied (x = 0), t h e feedback signal x s
A
(13.3)
0
In this section, w e study t h e basic principles of t h e design of linear s i n e - w a v e oscillators. In spite of t h e n a m e linear oscillator, s o m e f o r m of nonlinearity h a s t o b e e m p l o y e d t o p r o v i d e control of t h e a m p l i t u d e of t h e output sine w a v e . I n fact, all oscillators a r e essentially non linear circuits. This complicates t h e task of analysis a n d design of oscillators; n o longer is o n e able to apply transform (s-plane) m e t h o d s directly. N e v e r t h e l e s s , techniques h a v e b e e n d e v e l o p e d b y w h i c h t h e design of sinusoidal oscillators c a n b e p e r f o r m e d in t w o steps: T h e first step is a" linear o n e , a n d f r e q u e n c y - d o m a i n m e t h o d s of feedback circuit analysis c a n b e readily e m p l o y e d . S u b s e q u e n t l y , a nonlinear m e c h a n i s m for a m p l i t u d e control c a n b e provided.
=
(13.2)
13.1.2 The Oscillation Criterion
13.1 BASIC PRINCIPLES OF SINUSOIDAL OSCILLATORS
AAs)
BASIC PRINCIPLES O F SINUSOIDAL OSCILLATO
— x
0
For both the negative-feedback loop in Fig. 8.1 and the positive-feedback loop in Fig. 13.1, the loop gain L=Ap. However, the negative sign with which the feedback signal is summed in the negativefeedback loop results in the characteristic equation being 1 + L = 0. In the positive-feedback loop, the feedback signal is summed with a positive sign, thus resulting in the characteristic equation 1 — L = 0.
1 68
CHAPTER 1 3
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
13.1
BASIC PRINCIPLES O F SINUSOIDAL OSCILLATORS
if A/3 exceeds unity, oscillations will g r o w in a m p l i t u d e . W e therefore n e e d a m e c h a n i s m for forcing AB to r e m a i n equal to unity at the desired value of output a m p l i t u d e . This task is a c c o m p l i s h e d b y providing a nonlinear circuit for gain control. Basically, the function of the gain-control m e c h a n i s m is as follows: First, to ensure that oscillations will start, one designs the circuit such that AB is slightly greater than unity. This corresponds to designing the circuit so that the poles are in the right half of the s plane. T h u s as the p o w e r supply is turned on, oscillations will g r o w in amplitude. W h e n the amplitude reaches the desired level, the nonlinear network c o m e s into action and causes the loop gain to be reduced to exactly unity.^In other words, the poles will b e "pulled b a c k " to the jco axis. This action will cause the circuit to sustain oscillations at this desired amplitude. If, for s o m e reason, the loop gain is reduced below unity, the amplitude of the sine w a v e will diminish. This will b e detected b y the nonlinear network, which will cause the loop gain to increase to exactly unity. A s will b e seen, there a r e t w o basic a p p r o a c h e s to the i m p l e m e n t a t i o n of the n o n l i n e a r amplitude-stabilization m e c h a n i s m . T h e first a p p r o a c h m a k e s u s e of a limiter circuit (see Chapter 3). Oscillations are allowed to g r o w until the a m p l i t u d e reaches t h e level to w h i c h the limiter is set. W h e n the limiter c o m e s into operation, t h e a m p l i t u d e r e m a i n s constant. Obviously, the limiter should b e "soft" to m i n i m i z e nonlinear distortion. S u c h distortion, however, is r e d u c e d b y t h e filtering action of the frequency-selective n e t w o r k in the feedback loop. In fact, in one of the oscillator circuits studied in Section 13.2, the sine w a v e s are hard limited, and the resulting square w a v e s are applied to a b a n d p a s s filter present in the feedback loop. T h e "purity" of the output sine w a v e s will b e a function of t h e selectivity of this filter. That is, the higher the Q of t h e filter, the less the h a r m o n i c content of the sine-wave output.
FIGURE 1 3 . 2 Dependence of the oscillator-frequency stability on the slope of the phase response. A steep phase response (i.e., large dty/dcù) results in a small Aco for a given change in phase Acp (resulting from a change (due, for example, to temperature) in a circuit component). 0
that is, Afixg — x
0
w h i c h results in AB = l It should b e n o t e d that the frequency of oscillation co is d e t e r m i n e d solely b y the phase characteristics of the feedback loop; the l o o p oscillates at the frequency for w h i c h the phase is zero. It follows that t h e stability of t h e frequency of oscillation will b e d e t e r m i n e d b y the m a n n e r in w h i c h t h e p h a s e
T h e other m e c h a n i s m for amplitude control utilizes an element w h o s e resistance can b e controlled by the a m p l i t u d e of the output sinusoid. B y placing this element in the feedback circuit so that its resistance determines the l o o p gain, the circuit can b e designed to ensure that the loop gain reaches unity at the desired output amplitude. D i o d e s , or .TFETs operated in the triode r e g i o n , are c o m m o n l y e m p l o y e d to i m p l e m e n t the controlled-resistance element.
0
0
2
13.1.4 A Popular Limiter Circuit for Amplitude Control W e c o n c l u d e this section by presenting a limiter circuit that is frequently e m p l o y e d for the a m p l i t u d e control of o p - a m p oscillators, as well as in a variety of other applications. T h e circuit is m o r e precise and versatile than t h o s e p r e s e n t e d in C h a p t e r 3 .
2
T h e limiter circuit is s h o w n in Fig. 13.3(a), and its transfer characteristic is depicted in Fig. 13.3(b). T o see h o w the transfer characteristic is obtained, consider first the case of a small (close to zero) input signal v, and a small output voltage v , so that v is positive and vg is negative. It can be easily seen that both diodes D and D will be off. T h u s all of the input current v /R flows through the feedback resistance Rp and the output voltage is given b y 0
{
13.1
Consider a sinusoidal oscillator formed of an amplifier with again of 2 and a second-order bandpass filter.
I
1
Find the pole frequency and the center-frequency gain of the filter needed to produce sustained oscillations al 1 kHz. Ans. 1
A
2
v
= -(Rf/R^vt
0
(13.5)
This is t h e linear p o r t i o n of the limiter transfer characteristic in Fig. 13.3(b). W e n o w can use superposition to find the voltages at n o d e s A and B in t e r m s of ±V a n d v as
kHz: (i.5
0
v
A
0
B
°R
3
(13.6)
+ R
2
3
= - V - ^ ± - + i/ —^_ 7?4 + R R + R$ 0
s
2
l
0
2
v
R
+v
R +R
13.1.3 Nonlinear Amplitude Control T h e oscillation condition, t h e B a r k h a u s e n criterion, j u s t discussed, guarantees sustained oscillations in a m a t h e m a t i c a l sense. It is w e l l k n o w n , h o w e v e r , that the p a r a m e t e r s of any p h y s i c a l s y s t e m c a n n o t b e m a i n t a i n e d constant for any length of time. In other w o r d s , supp o s e w e w o r k h a r d to m a k e AB = 1 at ft) = co , a n d t h e n t h e t e m p e r a t u r e c h a n g e s and AB b e c o m e s slightly less than unity. O b v i o u s l y , oscillations will cease in this c a s e . Conversely,
R ? :
= V
(13.7)
A
We have not studied IFETs in this book. However, the CD accompanying the book includes material on JFETs and IFET circuits. The same material can also be found on the book's website.
*
>
1169
13.2 1 1 7 0
J
CHAPTER 13
SIGNAL GENERATORS AND WAVEFORM-SHAPING
O P A M P - R C OSCILLATOR CIRCUITS
I _
'
1 1 7 1
CIRCUITS
T h e corresponding value of v, can b e found b y dividing L_ b y the Hmiter gain ~R /R . If v is increased b e y o n d this value, m o r e current is injected into D , and v remains at approximately -V . T h u s the current through R remains constant, and the additional diode current flows through R . T h u s R appears in effect in parallel w i t h R , and the incremental gain (ignoring the diode resistance) is -(R \\R )/Ri. T o m a k e the slope of the transfer characteristic small in the Umiting region, a l o w value should b e selected for R . f
x
D
x
l
A
2
3
3
f
f
3
3
T h e transfer characteristic for n e g a t i v e v, can b e found in a m a n n e r identical to that j u s t e m p l o y e d . It can b e easily seen that for n e g a t i v e v d i o d e D plays an identical role to that played b y d i o d e D for positive Vj. T h e positive limiting level L can b e found to be h
2
x
+
(13.9) and the slope of the transfer characteristic in the positive limiting region is -iRfliR^/Ri. W e thus see that the circuit of Fig. 13.3(a) functions as a soft limiter, with the Umiting levels L and L_, and the limiting gains, independently adjustable b y the selection of appropriate resistor values. Finally, w e n o t e that increasing R results in a h i g h e r g a i n in the linear region w h i l e k e e p i n g L and L_ u n c h a n g e d . In t h e Emit, r e m o v i n g ^ a l t o g e t h e r results in t h e transfer char acteristic of Fig. 13.3(c), w h i c h is that of a comparator. T h a t is, t h e circuit c o m p a r e s Vj with the c o m p a r a t o r reference value of 0 V: v > 0 results in v = L_, and vj < 0 yields v — L . +
f
+
t
13.2
0
0
+
1 or i he ciivuii ol' l i g . I V . - . U uiih I - 15 V. R - ?n ki>. R • f»n k i l . R •- A'. • <> kil. and A'. • R, 3 1
Ans. 5.')5 \ : : 2 . T \ : 2: (>.'W5
' 13.2 OP A M P - R C OSCILLATOR CIRCUITS In this section w e shall study s o m e practical oscillator circuits utilizing op amps and R C networks.
13.2.1 The Wien-Bridge Oscillator O n e of the simplest oscillator circuits is b a s e d o n the W i e n b r i d g e . F i g u r e 13.4 s h o w s a W i e n - b r i d g e oscillator w i t h o u t t h e nonlinear gain-control n e t w o r k . T h e circuit consists of an o p a m p c o n n e c t e d in t h e noninverting configuration, with a c l o s e d - l o o p gain of 1 + R /R . In the feedback p a t h of this positive-gain amplifier an R C n e t w o r k is connected. T h e l o o p gain can b e easily o b t a i n e d b y multiplying t h e transfer function V (s)/V (s) of the f e e d b a c k n e t w o r k b y the amplifier gain, 2
A s vj goes positive, v goes n e g a t i v e (Eq. 13.5), and w e see from Eq. (13.7) that v% will b e c o m e m o r e negative, thus k e e p i n g D off. E q u a t i o n (13.6) s h o w s , h o w e v e r , that v b e c o m e s less positive. T h e n , if w e c o n t i n u e to increase v a n e g a t i v e value of v will b e r e a c h e d at w h i c h v b e c o m e s - 0 . 7 V or so and d i o d e D c o n d u c t s . If w e u s e t h e constantv o l t a g e - d r o p m o d e l for D and denote the v o l t a g e d r o p V , the value of v at w h i c h D con ducts can b e found from Eq. (13.6). T h i s is t h e n e g a t i v e limiting level, w h i c h w e d e n o t e L_, 0
2
A
b
A
a
D
0
L(s)
x
2
1+R,.
2
V
R
2
z +z P
s
Thus, 1 +
R
a
0
x
x
x
3 +
R /R 2
x
sCR+l/sCR
(13.10)
1 1 72
CHAPTER
13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
CIRCUITS
3.2
OP AMP-RC
+15
OSCILLATOR
V
R = 3 3
kn
OK
FIGURE 1 3 . 4 A Wien-bridge oscillator without amplitude stabilization.
Substituting s = jco results in
LU
1 + 3+
R /R 2
(13.11)
x
j(coCR-\/coCR)
T h e l o o p gain will b e a real n u m b e r (i.e., the p h a s e will b e zero) at o n e frequency given b y co CR
=
0
1 -15 V
co CR 0
FIGURE 1 3 . 5 A Wien-bridge oscillator with a limiter used for amplitude control.
T h a t is, co = 0
l/CR
(13.12)
T o obtain sustained oscillations at this frequency, o n e should set the m a g n i t u d e of the loop
-o
gain to unity. T h i s can b e a c h i e v e d b y selecting R /R 2
x
(13.13)
= 2
50 kfl
T o e n s u r e that oscillations will start, o n e c h o o s e s R /R slightly greater than 2. T h e r e a d e r can easily verify that if R /R = 2 + 5, w h e r e 8 is a small n u m b e r , t h e roots of the characteristic equation 1 - L(s) = 0 will b e in t h e right half of the s plane. T h e amplitude of oscillation can b e determined and stabilized b y using a nonlinear control network. T w o different implementations of the ampUtade-controlhng function are shown in Figs. 13.5 and 13.6. T h e circuit in Fig. 13.5 e m p l o y s a symmetrical feedback limiter of the type studied in Section 13.1.3. It is formed b y diodes D and D together with resistors R , R , R , and R , T h e limiter operates in the following manner: A t the positive p e a k of the output voltage v , the voltage at node b will exceed the voltage v (which is about 1 v ), and diode D conducts. This will clamp the positive p e a k to a value determined by R , R , and the negative p o w e r supply. T h e value of the positive output p e a k can b e calculated b y setting v = v + V and writing a n o d e equation at n o d e b while neglecting the current through D . Similarly, the negative peak of the output sine w a v e will b e c l a m p e d to the value that causes diode D to conduct. T h e value of the negative p e a k can b e determined b y setting v = v - V and writ ing an equation at n o d e a while neglecting the current through D . Finally, note that to obtain a symmetrical output waveform, R is chosen equal to R , and R equal to R . 2
2
io kn
x
x
5
O
- W r
I—vw-
x
v
2
3
4
6
0
x
0
s
16 n F
^>
2
— j |
6
b
x
C.
D2
2
C
P
.
16 nF '
R
P
WAr-
io kn
e io kn
x
a
x
D1
x
3
6
4
5
FIGURE 1 3 . 6 A Wien-bridge oscillator with an alternative method for amplitude stabilization.
CIRCUITS
1 1 7 3
1 1
CHAPTER 13
7 4
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
CIRCUITS 13.2
OP AMP-RC
OSCILLATOR
CIRCUITS
EXERCISE 50 kH
13.3
100 kft
For the circuit in Fig. 13.5: (a) Disregarding the limiter circuit, find the location of the closed-loop poles,
r—VW
(b) Find the frequency of oscillation, (c) With the limiter in place, find the amplitude of the output sine
I
VW
'
wave (assume that the diode drop is 0.7 V ) . Ans. (10 /16)(0.015 ± f)\ 1 k H z ; 21.36 V (peak-to-peak) 5
T h e circuit of Fig. 13.6 employs an inexpensive implementation of the parameter-variation m e c h a n i s m of amplitude control. Potentiometer P is adjusted until oscillations just start to grow. A s the oscillations g r o w , the diodes start to conduct, causing the effective resistance between a and b to decrease. EquiHbrium will b e reached at the output amplitude that causes the loop gain 16 n F
to b e exactly unity. T h e output amplitude can b e varied by adjusting potentiometer P.
16 n F
16 n F
C
C
A s i n d i c a t e d in F i g . 13.6, the o u t p u t is t a k e n at p o i n t b rather than at the o p - a m p output t e r m i n a l b e c a u s e t h e signal at b h a s l o w e r distortion than that at a. T o appreciate this point,
~ov
0
note that the v o l t a g e at b is p r o p o r t i o n a l to the v o l t a g e at t h e o p - a m p input terminals and that the latter is a filtered (by the R C n e t w o r k ) version of t h e v o l t a g e at n o d e a. N o d e b, how ever, is a h i g h - i m p e d a n c e n o d e , a n d a buffer will b e n e e d e d if a l o a d is to b e connected.
EXERCISE 13.4
For the circuit in Fig. 13.6 find the following: (a) The setting of potentiometer P at which oscillations just start, (b) T h e frequency of oscillation. Ans. (a) 20 k O to ground; (b) 1 kHz
13.2.2 The Phase-Shift Oscillator T h e basic structure of the phase-shift oscillator is s h o w n in Fig. 13.7. It consists of a negative-
FIGURE 1 3 . 8 A practical phase-shift oscillator with a limiter for amplitude stabilization.
that satisfies t h e u n i t y - l o o p - g a i n condition. O s c i l l a t i o n s will then g r o w in m a g n i t u d e until limited b y s o m e n o n l i n e a r control m e c h a n i s m . F i g u r e 13.8 s h o w s a practical phase-shift oscillator with a f e e d b a c k limiter, c o n s i s t i n g of
gain amplifier (~K) with a three-section (third-order) R C ladder n e t w o r k in the feedback. The
diodes Di a n d D a n d resistors R
circuit will oscillate at the frequency for w h i c h the p h a s e shift of t h e R C n e t w o r k is 180°. Only
tions, Rf h a s to b e m a d e slightly greater than the m i n i m u m required v a l u e . A l t h o u g h t h e cir
2
u
R , R , and R for a m p l i t u d e stabilization. T o start oscilla 2
3
4
at this frequency will the total p h a s e shift around the loop b e 0° or 360°. H e r e w e should note
cuit stabilizes m o r e rapidly, a n d p r o v i d e s sine w a v e s w i t h m o r e stable a m p l i t u d e , if R is
that the reason for using a three-section R C n e t w o r k is that three is the m i n i m u m number of
m a d e m u c h larger than this m i n i m u m , t h e p r i c e p a i d is a n i n c r e a s e d o u t p u t distortion.
f
sections (i.e., lowest order) that is capable of p r o d u c i n g a 180° p h a s e shift at a finite frequency. F o r oscillations to b e sustained, the v a l u e of K s h o u l d b e e q u a l to the i n v e r s e of the magnitudc of the R C n e t w o r k transfer function at the frequency of oscillation. H o w e v e r , to
EXERCISES
e n s u r e that oscillations start, the v a l u e of K h a s to b e c h o s e n slightly h i g h e r than the value 13.5
Consider the circuit of Fig. 13.8 without the limiter. Break the feedback loop at X and find the loop gain AB= V, (jco)/V (./ft)). T o do this, it is easier to start at the output and work backward, finding the vari ous currents and voltages, and eventually V, in terms of V„. x
Ans
1
4 = /i3wCA'
I
-itCRi
13.6 Use the expression derived in Exercise 13.5 to find the frequency of o s c i l l a t i o n a n d the minimum required value of R, for oscillations to start in the circuit of Fig. 13.8. Ans. 574.3 II/-. i : n k i 2 FIGURE 1 3 . 7 A phase-shift oscillator.
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
3.2
13.2.3 The Quadrature Oscillator T h e q u a d r a t u r e o s c i l l a t o r is b a s e d on t h e two-integrator l o o p studied i n Section 12.7. As an active filter, t h e l o o p is d a m p e d to locate t h e poles in the left half of t h e s p l a n e . H e r e , no such d a m p i n g will b e used, since w e w i s h to locate t h e poles o n the jcv axis to p r o v i d e sus tained oscillations. In fact, to ensure that oscillations start, t h e poles are initially located in the right half-plane a n d then "pulled b a c k " b y the n o n l i n e a r g a i n control. Figure 13.9 s h o w s a practical q u a d r a t u r e oscillator. Amplifier 1 is c o n n e c t e d as an inverting M i l l e r integrator with a limiter i n t h e feedback for a m p l i t u d e control. Amplifier 2 is c o n n e c t e d as a noninverting integrator (thus r e p l a c i n g t h e c a s c a d e c o n n e c t i o n of the Miller integrator a n d the inverter in the two-integrator l o o p of Fig. 12.25b). T o understand the operation of this noninverting integrator, consider the equivalent circuit s h o w n in Fig. 13.9(b). H e r e , w e h a v e r e p l a c e d the integrator input v o l t a g e v a n d the series resistance 2R b y the N o r t o n e q u i v a l e n t c o m p o s e d of a current source v /2R a n d a parallel resistance 2R. N o w , since v = 2v, w h e r e v is t h e v o l t a g e at t h e input of o p a m p 2 , the current t h r o u g h R will be (2v - v)/R = v/R i n the direction from output to input. T h u s R gives rise to a negative input resistance, -R , as indicated i n the equivalent circuit of F i g . 13.9(b). N o m i n a l l y , R is m a d e equal to 2R, a n d thus - f y cancels 2R, a n d at t h e input w e are left w i t h a current source v /2R feeding a capacitor C. T h e result is that v=^' ^dt a n d v = 2v = ±gv dt. T h a t is, f o r R = 2R, t h e circuit functions as a perfect n o n i n v e r t i n g integrator. If, however, R is m a d e smaller t h a n 2R, a n e t n e g a t i v e resistance appears i n parallel with C.
O P A M P - R C OSCILLATOR CIRCUITS
R e t u r n i n g to t h e oscillator circuit in F i g . 13.9(a), w e n o t e t h a t t h e r e s i s t a n c e ^ i n t h e p o s i t i v e - f e e d b a c k p a t h of o p a m p 2 is m a d e v a r i a b l e , w i t h a n o m i n a l v a l u e of 2R. D e c r e a s ing t h e v a l u e of R m o v e s t h e p o l e s to t h e right h a l f - p l a n e ( P r o b l e m 13.19) and e n s u r e s that t h e oscillations start. T o o m u c h p o s i t i v e feedback, a l t h o u g h it results in better a m p l i t u d e stability, also results i n h i g h e r o u t p u t distortion ( b e c a u s e t h e limiter h a s to o p e r a t e " h a r d e r " ) . In this r e g a r d , n o t e that t h e o u t p u t v will b e " p u r e r " than v b e c a u s e of t h e filtering action p r o v i d e d by t h e s e c o n d i n t e g r a t o r o n t h e p e a k - l i m i t e d output of t h e first integrator. f
02
01
If w e disregard t h e limiter a n d b r e a k t h e loop at X, t h e l o o p gain c a n b e obtained as
L(s)
y, = -2^ = V x
i
— sCR 2
2
2
(13 14) '
K
01
0l
0 2
T h u s t h e l o o p will oscillate at frequency co , g i v e n b y 0
f
f
f
0)
o
f
f
= ~
(13.15)
f
0l
0
02
01
f
f
Finally, it should b e p o i n t e d out that the n a m e quadrature oscillator is u s e d b e c a u s e the circuit p r o v i d e s t w o sinusoids with 90° p h a s e difference. This should b e obvious, since v is the integral of v . T h e r e are m a n y applications for w h i c h q u a d r a t u r e sinusoids are required. , 0 2
0 l
13.2.4 The Active-Filter-Tuned Oscillator
:C
<-R
f
T h e last oscillator circuit that w e shall discuss is quite simple b o t h i n principle a n d in design. N e v e r t h e l e s s , the a p p r o a c h is general a n d versatile a n d c a n result in high-quality (i.e., low-distortion) output sine w a v e s . T h e basic principle is illustrated in F i g . 13.10. T h e circuit consists of a high-Q b a n d p a s s filter c o n n e c t e d in a positive-feedback loop with a h a r d limiter. T o u n d e r s t a n d h o w this circuit w o r k s , a s s u m e that oscillations h a v e already started. T h e output of the b a n d p a s s filter will b e a sine w a v e w h o s e frequency is equal to t h e center frequency of the filter, f . T h e s i n e - w a v e signal «y, is fed to the limiter, which p r o d u c e s at its output a square w a v e w h o s e levels are d e t e r m i n e d b y the limiting levels a n d w h o s e 0
^
(Nominally 2R)
(A) F I G U R E 13.9
(a) A QUADRATURE-OSCILLATOR CIRCUIT, (b) EQUIVALENT CIRCUIT AT THE INPUT OF OP AMP 2 .
T ^ S
1 1 7 7
1 1 7 8
'
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
13.3
CIRCUITS
LC A N D CRYSTAL O S C I L L A T O
13.2.5 A Final Remark T h e o p a m p - R C oscillator circuits studied are useful for operation in t h e r a n g e 10 H z to 100 k H z (or p e r h a p s 1 M H z at m o s t ) . W h e r e a s the l o w e r frequency limit is dictated by the size of p a s s i v e c o m p o n e n t s required, t h e u p p e r limit is g o v e r n e d b y the frequency-response and slew-rate limitations of o p a m p s . F o r h i g h e r frequencies, circuits that e m p l o y transistors t o g e t h e r w i t h L C t u n e d circuits or crystals are frequently u s e d .
3
T h e s e are discussed in
Section 13.3.
^
13.3 LC AND CRYSTAL OSCILLATORS
Oscillators utilizing transistors ( F E T s or B J T s ) , with L C - t u n e d circuits or crystals as feed b a c k e l e m e n t s , are u s e d in the frequency r a n g e of 100 k H z to h u n d r e d s of m e g a h e r t z . T h e y exhibit h i g h e r Q than the R C types. H o w e v e r , L C oscillators are difficult to tune o v e r w i d e r a n g e s , and crystal oscillators operate at a single frequency.
13.3.1 LC-Tuned Oscillators F i g u r e 13.12 s h o w s t w o c o m m o n l y u s e d configurations of L C - t u n e d oscillators. T h e y are FIGURE 1 3 . 1 1
A practical implementation of the active-filter-tuned oscillator.
k n o w n as t h e C o l p i t t s oscillator and t h e H a r t l e y oscillator. B o t h utilize a parallel L C cir cuit c o n n e c t e d b e t w e e n collector and b a s e (or b e t w e e n drain a n d gate if a F E T is u s e d ) w i t h a fraction of t h e tuned-circuit v o l t a g e fed to t h e emitter (the s o u r c e in a F E T ) . This f e e d b a c k
frequency is / . T h e square w a v e in turn is fed to the b a n d p a s s filter, w h i c h filters out the
is a c h i e v e d b y w a y of a c a p a c i t i v e divider in the Colpitts oscillator and b y w a y of an i n d u c
h a r m o n i c s and p r o v i d e s a sinusoidal output v at t h e f u n d a m e n t a l frequency f . O b v i o u s l y ,
tive divider in t h e H a r t l e y circuit. T o focus attention o n t h e o s c i l l a t o r ' s structure, t h e bias
0
x
Q
the purity of t h e output sine w a v e will b e a direct function of the selectivity (or Q factor) of
details are not s h o w n . In b o t h circuits, the resistor R m o d e l s t h e c o m b i n a t i o n of t h e losses of
the b a n d p a s s filter^
the i n d u c t o r s , t h e l o a d resistance of the oscillator, and the output resistance of t h e transistor.
T h e simplicity of this a p p r o a c h to oscillator design should b e apparent. W e h a v e inde
If the f r e q u e n c y of operation is sufficiently l o w that w e c a n neglect the transistor c a p a c
p e n d e n t control of frequency and a m p l i t u d e as w e l l as of distortion of t h e output sinusoid.
itances, the frequency of oscillation will b e d e t e r m i n e d b y the r e s o n a n c e frequency of t h e
A n y filter circuit with positive gain can b e u s e d to i m p l e m e n t t h e b a n d p a s s filter. T h e fre
parallel-tuned circuit (also k n o w n as a tank circuit
b e c a u s e it b e h a v e s as a reservoir for
q u e n c y stability of t h e oscillator will b e directly d e t e r m i n e d b y the frequency stability of the bandpass-filter circuit. A l s o , a variety of limiter circuits (see C h a p t e r 3) w i t h different d e g r e e s of sophistication c a n be u s e d to i m p l e m e n t t h e h m i t e r block. F i g u r e 13.11 s h o w s o n e p o s s i b l e i m p l e m e n t a t i o n of t h e active-filter-tuned oscillator. T h i s circuit u s e s a v a r i a t i o n o n t h e b a n d p a s s circuit b a s e d o n t h e A n t o n i o u i n d u c t a n c e -
R < IL, •
s i m u l a t i o n circuit (see Fig. 12.22c). H e r e resistor R and c a p a c i t o r C are i n t e r c h a n g e d . This 2
4
m a k e s the output of the l o w e r o p a m p directly p r o p o r t i o n a l to (in fact, t w i c e as large as) the :C
v o l t a g e across t h e resonator, and w e c a n therefore d i s p e n s e with the buffer amplifier K. T h e limiter u s e d is a very s i m p l e o n e consisting of a resistance R and t w o diodes. x
C,
(a) 13.7
(b)
Using C = 16 nF. find the value of R such that the circuit of Fig. 13.11 produces 1 -kHz sine waves. If llie diode d i o p IK d." \ . I i n d llic |v.ik-io pe.ik amplitude nl die o u i p u i M M C
illim:
with peak-to-peak amplitude of V volts has a fundamental component with AV/K
A -qamc w n \ e
FIGURE 1 3 . 1 2
Two commonly used configurations of LC-tuned oscillators: (a) Colpitts and (b) Hartley.
volts peak-to-peak
amplitude.) Ans. 10 k<2: 3.6 V
3
Of course, transistors can be used in place of the op amps in the circuits just studied. At higher frequencies, however, better results are obtained with LC-tuned circuits and crystals.
13.3 CHAPTER 13
LC A N D CRYSTAL O S C I L L A T O R S
SIGNAL GENERATORS A N D W A V E F O R M - S H A P I N G CIRCUITS
F o r oscillations to start, both the real a n d imaginary parts m u s t b e zero. Equating the i m a g i nary part to zero gives the frequency of oscillation as
sC VV 2
L
c 4
w h i c h is t h e r e s o n a n c e frequency of the tank circuit, as a n t i c i p a t e d . E q u a t i n g the real part to zero together with u s i n g E q . (13.20) gives
sC V. 2
T
C /C 2
(13.21)
m
w h i c h h a s a simple p h y s i c a l interpretation: F o r sustained oscillations, t h e m a g n i t u d e of t h e gain from b a s e to collector (gji) m u s t b e equal to the inverse of the voltage ratio p r o v i d e d b y t h e capacitive divider, w h i c h from F i g . 13.12(a) c a n b e seen to b e v /v = C /C . Of course, for oscillations to start, t h e loop gain m u s t b e m a d e greater t h a n unity, a condition that c a n b e stated in t h e equivalent form
FIGURE 1 3 . 1 3 Equivalent circuit of the Colpitts oscrllator of Fig. 13 12(a) To simplify the analysis, C„ and " l e neglected We can consider C, to be part of C , and we can tnclude r m «. 2
= gR
x
0
eb
e n e r g y storage). T h u s for t h e Colpitts oscillator w e h a v e (13.16)
g R>C /C m
a n d for t h e H a r t l e y oscillator w e h a v e L
T h e ratio L /L x
or C , / C
2
2
C
d e t e r m i n e s t h e f e e d b a c k factor and t h u s m u s t b e adjusted in
conjunction w i t h t h e transistor gain t o e n s u r e that oscillations will $tart. T o d e t e r m i n e the oscillation condition for t h e Colpitts oscillator, w e r e p l a c e t h e transistor w i t h its equivalent circuit, as s h o w n i n F i g . 13.13. T o simplify t h e analysis w e h a v e n e g l e c t e d t h e transistor capacitance
(C
gd
for a F E T ) . C a p a c i t a n c e C„ (C
gs
for a F E T ) , although n o t shown, can
be c o n s i d e r e d to b e a p a r t of C . T h e i n p u t resistance r„ (infinite for a F E T ) h a s also been 2
neglected, a s s u m i n g that at the frequency of oscillation r„ S> (\/coC ). 2
Finally, as men
t i o n e d earlier, the resistance R i n c l u d e s r of t h e transistor. T o find the l o o p gain, w e b r e a k t h e l o o p at t h e transistor b a s e , apply an input voltage V , K
a n d find t h e returned voltage that appears across t h e i n p u t terminals of the transistor. W e t h e n e q u a t e t h e l o o p g a i n to unity. A n alternative a p p r o a c h is t o a n a l y z e the circuit and elim i n a t e all current and voltage variables, a n d t h u s obtain o n e equation that g o v e r n s circuit operation. Oscillations will start if this e q u a t i o n is satisfied. T h u s the resulting equation will g i v e u s t h e conditions for oscillation. >, A n o d e equation at t h e transistor collector ( n o d e C ) i n t h e circuit of F i g . 13.13 yields
2
m
2
+ sC^
n
1 + s LC )
V =0
2
2
+ s (LC /R)
2
+ s(C + C ) + (g +Q
2
l
0
T
2
c
BE
D
m
- 0
(13.19)
If r is taken into account, the frequency of oscillation can be shown to shift slightly from the value given by Eq. (13.20).
Substituting s = jco gives
n
g
m
l _ o f L ^ R R J
+
j
[
(
u
{
C
x
+
C )-ofLC C ] 2
l
2
GS
(13.18)
n
1
As oscillations g r o w in amplitude, the transistor's nonlinear characteristics r e d u c e the effec tive v a l u e of g and, correspondingly, r e d u c e the l o o p gain to unity, thus sustaining t h e oscillations. A n a l y s i s similar to t h e foregoing c a n b e carried out for t h e Hartley circuit (see laterExercise 13.8). A t h i g h frequencies, m o r e accurate transistor m o d e l s m u s t b e used. Alterna tively, t h e y p a r a m e t e r s of t h e transistor c a n b e m e a s u r e d at t h e i n t e n d e d frequency ft) , a n d the analysis can t h e n b e carried out using t h e y - p a r a m e t e r m o d e l (see A p p e n d i x B ) . T h i s is usually simpler a n d m o r e accurate, especially at frequencies a b o v e about 3 0 % of t h e transistor f . A s an e x a m p l e of a practical L C oscillator w e s h o w in F i g . 13.14 the circuit of a Colpitts oscillator, c o m p l e t e with bias details. H e r e the radio-frequency c h o k e ( R F C ) provides a h i g h reactance at co but a low d c resistance. Finally, a f e w w o r d s are i n order on the m e c h a n i s m that d e t e r m i n e s the a m p l i t u d e of oscillations i n t h e L C - t u n e d oscillators discussed a b o v e . U n l i k e the o p - a m p oscillators that incorporate special amplitude-control circuitry, L C - t u n e d oscillators utilize the nonlinear i -v characteristics of t h e B J T (the i -v characteristics of t h e F E T ) for a m p l i t u d e control. T h u s t h e s e L C - t u n e d oscillators are k n o w n as self-limiting oscillators. Specifically, as the oscillations g r o w in amplitude, t h e effective gain of t h e transistor is r e d u c e d b e l o w its small-signal value. E v e n t u a l l y , an a m p l i t u d e is r e a c h e d at w h i c h t h e effective gain is reduced to the p o i n t that t h e B a r k h a u s e n criterion is satisfied exactly. T h e a m p l i t u d e then remains constant at this value. R e l i a n c e o n t h e n o n l i n e a r characteristics of the B J T (or t h e F E T ) i m p l i e s that the c o l l e c tor (drain) c u r r e n t w a v e f o r m will b e nonlinearly distorted. N e v e r t h e l e s s , the output v o l t a g e signal will still b e a sinusoid of h i g h purity b e c a u s e of t h e filtering action of the L C tuned circuit. D e t a i l e d analysis of a m p l i t u d e control, w h i c h m a k e s u s e of nonlinear-circuit tech niques, is b e y o n d the s c o p e of this b o o k .
r a n g e d in t h e form 3
(13.22)
K
S i n c e V ^ 0 (oscillations h a v e started), it c a n b e eliminated, a n d t h e equation c a n b e rear
s LC C
2
0
0
sC V, + g V +
l
1
m
(13.17) W ( £ i + 2 )
©O =
2
ce
= 0
' V
1 1 8 1
iji*
11 8 2
CHAPTER 13
SIGNAL GENERATORS
A N D WAVEFORM-SHAPING
CIRCUITS 13.3
LC A N D CRYSTAL O S C I L L A T O R S
Crystal | reactance
Vcc
FIGURE 1 3 . 1 4 Complete circuit for a Colpitts oscillator.
6
6
(a)
(b)
(c)
FIGURE 1 3 . 1 5 A piezoelectric crystal, (a) Circuit symbol, (b) Equivalent circuit, (c) Crystal reactance versus frequency [note that, neglecting the small resistance r, Z =jX(co)]. crystal
S i n c e t h e Q factor is very high, w e m a y neglect the resistance r and express the crystal i m p e d a n c e as
EXERCISES Z( )
=
S
13.8 D13.9
Show thai for the Hartley oscillator of Fig. 13.12(b), t h e frequency of oscillation is given by Eq. (13.17) and that for oscil lations to start g,„R > (L/L,). Using a BJT biased at l = 1 inA, design a Colpitts oscillator to operate at cq, = 10 rad/s. Use C = 0.01 uV, and assume that the coil available has a O of 100 (this can be represented by a resistance in parallel with C| given by Q/ahCi). Also assume that there is a load resistance at the collector of 2 k£z and that for the BJT, r„ = 100 k Q . Find C and L.
Y
sC„ + . "
- sL+l/sCA
w h i c h can b e m a n i p u l a t e d to the form
6
c
{
Z(s)
j
1 sC,PS
+(l/LC ) f
(13.23) +[{C
p
+
C )/LC C ] s
s
p
2
Ans. 0.66 ,uF; 100 ,/Jll (a sotnewbal smaller C • amplitude)
2
would be used to allow oscillations to grow in
F r o m Eq. (13.23) a n d from F i g . 13.15(b) w e see t h a t t h e crystal has t w o r e s o n a n c e freque cies: a series r e s o n a n c e at co, :i
co =
Ï/JLC
s
(13.24)
and a parallel r e s o n a n c e at co
B
13.3.2 Crystal Oscillators A piezoelectric crystal, such as quartz, exhibits e l e c t r o m e c h a n i c a l - r e s o n a n c e characteristics that are very stable (with t i m e a n d t e m p e r a t u r e ) and highly selective (having very h i g h Q factors). T h e circuit s y m b o l of a crystal is s h o w n in F i g . 13.15(a), and its e q u i v a l e n t circuit m o d e l is given in Fig. 13.15(b). T h e r e s o n a n c e properties are characterized b y a large inductance L (as h i g h as h u n d r e d s of h e n r y s ) , a very small series c a p a c i t a n c e C (as small as 0 . 0 0 0 5 p F ) , a series resistance r representing a Q factor co L/r that can b e as h i g h as a few h u n d r e d t h o u s a n d , and a parallel c a p a c i t a n c e C (a few picofarads). Capacitor C represents the electrostatic c a p a c i t a n c e b e t w e e n the t w o parallel plates of t h e crystal. N o t e that C > C,.
(13.25) T h u s for s = jco w e can write ( 2 2\ CO - CO
s
0
p
p
p
Z(jco)
=
s
-j
coC, \co
(13.26) -
CO
pJ
F r o m E q s . (13.24) and (13.25) w e note that co > co . H o w e v e r , since C > C , the t w o r e s o n a n c e frequencies are very close. E x p r e s s i n g Z(jco) =jX(co), the crystal reactance X(co) will p
s
p
s
L„
-,-j
8 3
13.4 ,
CHAPTER 13
BISTABLE MULTIVIBRATO
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
1 1 84
13.4 BISTABLE MULTIVIBRATORS In this section w e begin the study of waveform-generating circuits of the other type—nonlinear oscillators or function generators. These devices m a k e use of a special class of circuits k n o w n as multivibrators. A s m e n t i o n e d earlier, there are three types of multivibrator: bistable, monostable, and astable. This section is concerned with the first, the bistable multivibrator. 5
A s its n a m e indicates, t h e bistable m u l t i v i b r a t o r has two stable states. T h e circuit can r e m a i n in either stable state indefinitely and m o v e s to t h e other stable state only w h e n appropriately triggered.
13.4.1 The Feedback Loop Bistability can b e obtained b y connecting a dc amplifier in a positive-feedback loop h a v i n g a loop gain greater t h a n unity. S u c h a feedback loop is s h o w n in Fig. 13.17; it consists of an op a m p and a resistive voltage divider in the positive-feedback path. T o see h o w bistability is FIGURE 1 3 . 1 6 A Pierce crystal oscillator utilizing a CMOS inverter as an amplifier.
obtained, c o n s i d e r operation with the positive input terminal of the o p a m p near g r o u n d potential. This is a r e a s o n a b l e starting point, since the circuit has n o external excitation. A s s u m e that the electrical noise that is inevitably present in every electronic circuit causes a small positive i n c r e m e n t in t h e voltage v . This incremental signal will b e amplified b y t h e +
h a v e t h e s h a p e s h o w n in F i g . 13.15(c). W e o b s e r v e that the crystal r e a c t a n c e is inductive
large o p e n - l o o p gain A of the o p a m p , with t h e result that a m u c h greater signal will appear
o v e r t h e v e r y n a r r o w frequency b a n d b e t w e e n co a n d co . F o r a g i v e n crystal, this frequency
in t h e o p a m p ' s o u t p u t v o l t a g e v .
b a n d is w e l l defined. T h u s w e m a y u s e t h e crystal to r e p l a c e the inductor of the Colpitts
R = R /(R
oscillator (Fig. 13.12a). T h e resulting circuit will oscillate at t h e r e s o n a n c e frequency of the
A/3 is greater than unity, as is usually the case, the fed-back signal will b e greater than t h e
s
p
c i y s t a l i n d u c t a n c e L w i t h t h e series e q u i v a l e n t of C a n d ( C + C C /(C s
X
2
1
+ C Y). Since C, 2
0
1
+ R)
1
T h e v o l t a g e d i v i d e r (R
u
original i n c r e m e n t in v+. T h i s regenerative
+
+
s
w i l l feed a fraction
process continues until eventually the op a m p sat-
age at t h e positive input terminal, v , b e c o m e s L R /(R =
2
urates w i t h its output v o l t a g e at t h e positive saturation level, L . W h e n this h a p p e n s , the volt-
is m u c h s m a l l e r than t h e three other c a p a c i t a n c e s , it will b e d o m i n a n t a n d \/JLC
R)
of t h e output signal b a c k to the positive input terminal of the o p a m p . If
2
(13.27)
œ,
+
1
1
+ R ), 2
w h i c h is positive and thus
keeps t h e o p a m p in positive saturation. This is o n e of the t w o stable states of the circuit. In t h e description a b o v e w e a s s u m e d that w h e n v w a s n e a r zero volts, a positive incre+
I n a d d i t i o n t o t h e b a s i c C o l p i t t s oscillator, a v a r i e t y of c o n f i g u r a t i o n s exist for crystal
m e n t o c c u r r e d in v . H a d w e a s s u m e d t h e equally p r o b a b l e situation of a negative incre-
o s c i l l a t o r s . F i g u r e 13.16 s h o w s a p o p u l a r c o n f i g u r a t i o n (called t h e P i e r c e oscillator)
ment, the, o p a m p w o u l d h a v e e n d e d u p saturated in the n e g a t i v e direction with v = L_ and
u t i l i z i n g a C M O S i n v e r t e r ( s e e S e c t i o n 4 . 1 0 ) a s a m p l i f i e r . R e s i s t o r ^ d e t e r m i n e s a dc
v = L_R /(R
+
0
+
X
x
+ R ). 2
T h i s is t h e other stable state.
o p e r a t i n g p o i n t in t h e h i g h - g a i n r e g i o n of t h e C M O S i n v e r t e r . R e s i s t o r i ? t o g e t h e r with
W e thus c o n c l u d e that the circuit of Fig. 13.17 has t w o stable states, one,with the op a m p
capacitor C provides a l o w- p ass filter that discourages t h e circuit from oscillating at a higher
in positive saturation and t h e other with the op a m p in negative saturation. T h e circuit can
h a r m o n i c of t h e c r y s t a l f r e q u e n c y . N o t e t h a t this c i r c u i t a l s o is b a s e d o n t h e Colpitts
exist in either of these t w o states indefinitely. W e also n o t e that t h e circuit cannot exist in the
x
x
state for w h i c h v = 0 and v = 0 for any length of time. This is a state of unstable
configuration.
+
T h e e x t r e m e l y s t a b l e r e s o n a n c e c h a r a c t e r i s t i c s and t h e v e r y h i g h Q factors of quartz
0
equilibrium
(also k n o w n as a m e t a s t a b l e state); any disturbance, such as that caused b y electrical noise,
crystals result in oscillators w i t h v e r y a c c u r a t e a n d stable frequencies. C r y s t a l s a r e available w i t h r e s o n a n c e frequencies in t h e r a n g e of few kilohertz to h u n d r e d s of megahertz. T e m p e r a t u r e coefficients of C0Q of 1 or 2 p a r t s p e r m i l l i o n ( p p m ) p e r d e g r e e Celsius are a c h i e v a b l e . Unfortunately, h o w e v e r , crystal oscillators, b e i n g m e c h a n i c a l resonators, are
v+
fixed-frequency circuits. -O
Vq_
FIGURE 1 3 . 1 7 A positive-feedback loop capable of bistable operation. 1 3
, 0 A 2-MHz quartz crystal is specified to have L = 0.52 H. C , = 0.012 F . C, = 4 F , and r = 120 ft Find P
f f„. and Q. . : . ( ) | . s \ l l l / : 2 . i ) l s M I I / : 55.i)i)n A n s
P
Digital implementations of multivibrators were presented in Chapter 11. Here, we are interested in implementations utilizing op amps.
1186
CHAPTER 13
SIGNAL GENERATORS A N D W A V E F O R M - S H A P I N G CIRCUITS 13.4
BISTABLE MULTIVIBRATORS
A O V
F I G U R E 1 3 . 1 8 A physical analogy for the operation of the bistable circuit. The ball cannot remain at the top of the hill for any length of time (a state of unstable equiUbrium or metastability); the inevitably present disturbance w i l l cause the ball to fall to one side or the other, where it can remain indefinitely (the two stable states).
7-
V,
VTH
O V
0
causes the bistable circuit to switch to o n e of its t w o stable states. This is in sharp contrast to t h e case w h e n the feedback is negative, causing a virtual short circuit to appear b e t w e e n the o p a m p ' s input terminals and maintaining this virtual short circuit in the face of disturbances. A physical analogy for the operation of the bistable circuit is depicted in Fig. 13.18.
18"
BB»
13.4.2 Transfer Characteristics of the Bistable Circuit T h e question naturally arises as to h o w w e can m a k e the bistable circuit of Fig. 13.17 c h a n g e state. T o h e l p a n s w e r this crucial question, w e derive t h e transfer characteristics of t h e bistable. R e f e r e n c e to Fig. 13.17 indicates that either of t h e t w o circuit n o d e s that are c o n n e c t e d t o g r o u n d can serve as an input terminal. W e investigate b o t h possibilities. F i g u r e 13.19(a) shows the bistable circuit with a voltage Vj applied to the inverting input terminal of the o p amp". T o derive the transfer characteristic v -v a s s u m e that v is at one of its t w o possible levels, say L , and thus v = BL . N o w as v is increased from 0 V w e can see from t h e circuit that nothing h a p p e n s until v reaches a value equal to v (i.e., BL ). A s v, b e g i n s to e x c e e d this value, a net negative voltage develops b e t w e e n the input terminals of the op a m p . This voltage is amplified b y the o p e n - l o o p gain of t h e o p a m p , and thus v goes negative. T h e voltage divider in turn causes v to g o negative, thus increasing the net negative input to the o p a m p and keeping the regenerative process going. This process culminates in the o p a m p saturating in the negative direction: that is, with v = L_ and, correspondingly, v = /3L_. It is e a s y t o see that i n c r e a s i n g v, further h a s n o effect o n the a c q u i r e d state of the bistable circuit. Figure 13.19(b) shows the transfer characteristic for increasing v O b s e r v e that the characteristic is that of a comparator with a threshold voltage denoted V , w h e r e V = fiL . N e x t consider w h a t h a p p e n s as v, is decreased. S i n c e n o w .v = f3L_, w e see that the cir cuit r e m a i n s in the negative-saturation state until v, goes negative to t h e point that it equals /?L_. A s v, g o e s b e l o w this value, a net positive voltage appears b e t w e e n t h e o p a m p ' s input terminals. T h i s voltage is amplified b y the o p - a m p gain and thus gives rise to a positive volt a g e at the o p a m p ' s output. T h e regenerative action of the positive-feedback l o o p then sets in a n d causes t h e circuit eventually to g o to its positive-saturation state, in w h i c h v = L+ and v = BL . T h e transfer characteristic for decreasing v is s h o w n in Fig. 13.19(c). H e r e again w e observe that the characteristic is that of a comparator, but with a threshold voltage = BL_. T h e complete transfer characteristics, v -v,, of the circuit in Fig. 13.19(a) can b e obtained b y combining the characteristics in Fig. 13.19(b) and (c), as shown in Fig. 13.19(d). A s indi cated, the circuit changes state at different values of v depending o n whether v, is increasing or decreasing. T h u s the circuit is said to exhibit hysteresis; the width of the hysteresis is the dif ference b e t w e e n the high threshold V and the l o w threshold V . Also note that the bistable circuit is in effect a comparator with hysteresis. A s will b e s h o w n shortly, adding hysteresis to a comparator's characteristics can be very beneficial in certain applications. Finally, observe that because tire bistable circuit of Fig. 13.19 switches from the positive state (v = L ) to the negative state (v = L_) as v is increased past the positive threshold V , the circuit is said to be inverting. A bistable circuit with a noninverting transfer characteristic will b e presented shortly. 0
+
+
+
h
(a)
(b)
0
l
{
+
+
•
0
0
Vl
+
0
+
L -
L_
-ga
t
TH
TH
+
+
te)
(d)
F I G U R E 1 3 . 1 9 (a) The bistable circuit of Fig. 13.17 with the negative input terminal of the op amp dis connected from ground and connected to an input signal vj. (b) The transfer characteristic of the circuit in (a) for increasing . (c) The transfer characteristic for decreasing v,. (d) The complete transfer characteristics. V[
0
+
+
r
0
b
TH
TL
0
0
r
m
+
13.4.3 Triggering the Bistable Circuit Returning n o w to the question of-how to m a k e the bistable circuit c h a n g e state, w e observe from the transfer characteristics of Fig. 13.19(d) that if the circuit is in the L state it can b e switched to the L_ state b y applying an input v, of value greater than V = fiL . Such an input causes a net negative voltage to appear between the input terminals of the op amp, which ini tiates the regenerative cycle that culminates in the circuit switching to the L_ stable state. Here it is important to note that the input v, merely initiates or triggers regeneration. Thus w e can r e m o v e v, with n o effect o n the regeneration process. In other words, v, can be simply a pulse of short duration. T h e input signal v is thus referred to as a trigger signal, or simply a trigger. +
TH
+
l
T h e characteristics of F i g . 13.19(d) indicate also that the bistable circuit can b e switched to the positive state (v = L ) b y applying a negative trigger signal Vj of m a g n i t u d e greater than that of the n e g a t i v e threshold V . 0
+
TL
n
S
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
13.4 B I S T A B L E M U L T I V I B R A T O R S
13.4.4 The Bistable Circuit as a Memory Element W e o b s e r v e from F i g . 13.19(d) that for i n p u t voltages in the r a n g e V
;
TH
to g o slightly positive. T h e value of v, that causes this to h a p p e n is t h e h i g h threshold volt a g e V , w b t c h can be found b y substituting in Eq. (13.28) v = L_ and f o ! ^ ^ " TH
0
+
V
TH
=
(13.30)
T h e complete transfer characteristic of the circuit of Fig. 13.20(a) is displayed in Fig. 13.20(b). O b s e r v e that a p o s i t i v e triggering signal v (of v a l u e greater t h a n V ) causes the circuit to switch t o t h e positive state (v g o e s from L_ to L+). T h u s the transfer characteristic of this circuit is noninverting. I
TH
0
13.4.5 A Bistable Circuit with Noninverting Transfer Characteristics T h e b a s i c bistable feedback loop of F i g . 13.17 can b e u s e d to derive a circuit with noninverting transfer characteristics b y applying t h e i n p u t signal vj (the trigger signal) to the terminal of R that is c o n n e c t e d to g r o u n d . T h e resulting circuit is s h o w n in Fig. 13.20(a). T o obtain the transfer characteristics w e first e m p l o y superposition to t h e linear circuit f o r m e d by R a n d R , t h u s e x p r e s s i n g v in terms of Vj and v as {
x
2
+
0
Rx + R,
+
(13.28)
v
0
13.4.6 Application of the Bistable Circuit as a Comparator T h e c o m p a r a t o r is an analog-circuit b u i l d i n g b l o c k that is u s e d in a variety of applications r a n g i n g from d e t e c t i n g t h e level of a n i n p u t signal r e l a t i v e t o a p r e s e t threshold value, to t h e design of analog-to-digital ( A / D ) converters (see Section 9.1). A l t h o u g h one n o r m a l l y thinks o f t h e c o m p a r a t o r as h a v i n g a single threshold value (see F i g . 13.21a), it is useful in m a n y applications t o add hysteresis t o t h e c o m p a r a t o r characteristics. If this is d o n e , the c o m p a r a t o r exhibits t w o threshold values, V and V , symmetrically p l a c e d about t h e TL
m
Ri+R
2
F r o m this equation w e see that if the circuit is in t h e positive stable state w i t h v = L , positive v a l u e s for v will h a v e n o effect. T o trigger the circuit into the L_ state, V; m u s t b e m a d e n e g a t i v e and of such a v a l u e as to m a k e v d e c r e a s e b e l o w zero. T h u s the l o w threshold V can b e found b y substituting in Eq. (13.28) v = L , v = 0, and w = V . T h e result is 0
+
Vol
t
+
TL
0
V
TL
=
+
+
7
TL
(13.29)
-L (R /R ) +
l
2
Shnilarly, Eq. (13.28) indicates that w h e n the circuit is in the negative-output state (v = L_), n e g a t i v e values of v will m a k e v+ m o r e n e g a t i v e w i t h n o effect on operation. T o initiate the r e g e n e r a t i o n p r o c e s s that causes t h e circuit to s w i t c h ' t o the positive state, v m u s t b e m a d e 0
l
+
(a)
-—u
Vol
— Hysteresis riÇ Bin
V
v,
TH
o
(a)
v
0
L_
(b)
FIGURE 1 3 . 2 0 (a) A bistable circuit derived from the positive-feedback loop of Fig. 13.17 by applying Vi through R (b) The transfer characteristic of the circuit in (a) is noninverting. (Compare it to the inverting characteristic in Fig. 13.19d.) v
Jtn
(b)
S ofteeshS
B
d
r
e p r e S e n t a t i 0 n
v o t T Z characteristic for a comparator having a rereience, or threshold, voltage V . (b) Comparator characteristic with hysteresis. r
R
£\
l
l
g
g
1190
.
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS 13.4
BISTABLE MULTIVIBRATORS
1 '-TV-
W
(b)
FIGURE 1 3 . 2 3 Limiter circuits are used to obtain more precise output levels for the bistable circuit Tn (b) J W For ror this mis circuit circuit L
+
-- V V \+ vV z
1+ Z V
D
D
z
,7, andATL_ = ~ -(V
1 2
d )
+* V
7
n
^
w h e r e
+ ' V„ )
V
°
I S
t h e
f o r w a r d
&°P-
IJ^
13.4.7 Making the Output Levels More Precise
FIGURE 1 3 . 2 2 Illustrating the use of hysteresis in the comparator characteristics as a means of rejecting interference.
desired reference level, as indicated in F i g . 13.21(b). U s u a l l y V and V are separated b y a small a m o u n t , say 100 m V . T o d e m o n s t r a t e the n e e d for hysteresis w e consider a c o m m o n application of compara tors. It is required to design a circuit that detects and counts t h e zero crossings of an arbi trary w a v e f o r m . S u c h a function c a n b e i m p l e m e n t e d using a c o m p a r a t o r w h o s e threshold is set to 0 V. T h e c o m p a r a t o r provides a step c h a n g e at its output e v e r y t i m e a z e r o crossing occurs. E a c h step c h a n g e can b e u s e d to g e n e r a t e a p u l s e , and t h e pulses are fed to a counter circuit. m
TL
I m a g i n e n o w w h a t h a p p e n s if the signal b e i n g p r o c e s s e d h a s — a s it usually does h a v e — interference s u p e r i m p o s e d on it, say of a frequency m u c h h i g h e r t h a n that of t h e signal. It follows that t h e signal m i g h t cross the zero axis a n u m b e r of t i m e s a r o u n d e a c h of the zerocrossing points w e are trying to detect, as s h o w n in Fig. 13.22. T h e c o m p a r a t o r w o u l d thus c h a n g e state a n u m b e r of times at each of the zero crossings, and our count would obviously be in error. H o w e v e r , if w e h a v e an i d e a of t h e e x p e c t e d p e a k - t o - p e a k a m p l i t u d e of t h e interfer ence, t h e p r o b l e m can b e solved b y introducing hysteresis of appropriate w i d t h in the com parator characteristics. T h e n , if t h e input signal is increasing in m a g n i t u d e , the c o m p a r a t o r w i t h hysteresis will r e m a i n in the l o w state until the input level e x c e e d s the high threshold V . S u b s e q u e n t l y t h e c o m p a r a t o r will r e m a i n in t h e h i g h state even if, o w i n g to interfer e n c e , t h e signal decreases b e l o w V . T h e c o m p a r a t o r will switch to the l o w state only if the input signal is decreased below the low threshold V . T h e situation is illustrated in Fig. 13.22, from w h i c h w e see that including hysteresis in t h e c o m p a r a t o r characteristics p r o v i d e s an effective m e a n s for rejecting interference (thus p r o v i d i n g a n o t h e r f o r m of filtering).
T h e output levels of the bistable circuit can be m a d e m o r e precise t h a n the saturation volt ages of the o p a m p are b y cascading the o p a m p with a limiter circuit (see Section 3 6 for a discussion of limiter circuits). T w o such a r r a n g e m e n t s are s h o w n in F i g 13 2 3
EXERCISES D13.11 The op amp in the bistable circuit of Fig. 13.19(a) has output saturation voltages of ± 1 3 V. Design the circuit to obtain threshold voltages ol ± 5 V. For A , = 10 kil, find the value required lor AS. 1
D13.12 If the op amp in the circuit of Fig. 13.20(a) has ±10-V output saturation levels, design the circuit to obtain ±5-V thresholds. Give suitable component values. >. Ans. Possible choice: A\ = 10 k U and A', - 20 kii 13.13 Consider a bistable circuit with a noninverting transfer characteristic, and let U = -L_ = H) V and V = -V = 5 V. If Vj is a triangular wave with a U-V average, a 10-V peak amplitude, and a l - n i s period, sketch the waveform of v . Find the lime interval between the zero crossings of v, and v . m
n
(}
0
Ans. i' . is a square wave with 0-V average, 10-V amplitude, and 1-ms period and is delayed by 125 ,us •.relative lo <
13.14 Consider an o p a m p having saturation levels of ± 1 2 V used without feedback, with the inverting input terminal connected to +3 V and the noninverting input terminal connected to v,. Characterize its opera tion as a comparator. What are L , L , and V^, as defined in 1-ig. 13.21 ia):' t
Ans. -12 V :
12 \ :
;
V
m
TH
TL
13.15 Tn the circuit of Fig. 13.20(a) let /,., = -L. = 10 V and /?, = 1 kO. Find a value for R that gives a hysteresis of 100-mV width. 2
Ans.
200 t o
CHAPTER 13
S I G N A L G E N E R A T O R S A N DW A V E F O R M - S H A P I N G
CIRCUITS 13.5
•
WAVEFORM
GENERATION
USING ASTABLE M U
LTI V I B R A T O R S
13.5 GENERATION OF SQUARE AND TRIANGULAR ' WAVEFORMS USING ASTABLE MULTIVIBRATORS
A square w a v e f o r m c a n b e generated b y arranging for a bistable multivibrator to switch states periodically. T h i s can b e d o n e b y c o n n e c t i n g the bistable multivibrator with an R C circuit in a feedback loop, as shown in Fig. 13.24(a). Observe that the bistable multivibrator has an inverting transfer characteristic and can thus b e realized using the circuit of Fig. 13.19(a). This results in the circuit of Fig. 13.24(b). W e shall s h o w shortly that this circuit h a s no stab l e states and thus is appropriately n a m e d a n a s t a b l e m u l t i v i b r a t o r .
13.5.1 Operation of the Astable Multivibrator T o see h o w the astable multivibrator operates, refer to F i g . 13.24(b) a n d let the output of the bistable multivibrator b e at o n e of its t w o possible levels, say L . Capacitor C will charge t o w a r d this level t h r o u g h resistor R. T h u s the voltage across C, w h i c b i s applied to the negative input terminal of the o p a m p and thus is d e n o t e d v_, will rise exponentially toward L with a time constant r = CR. Meanwhile, the voltage at the positive input terminal of the op amp is v+ = /3L . This situation will continue until t h e capacitor voltage r e a c h e s t h e positive threshold V - fiL at w h i c h point the bistable multivibrator will switch t o the other stable state i n w h i c h v = L_ and v = pL_. T h e capacitor will t h e n start discharging, and its voltage, v_, will d e c r e a s e exponentially t o w a r d L_. T h i s n e w state will prevail until v_ reaches the negative threshold V = J3LJ, at w h i c h t i m e t h e bistable multivibrator switches to t h e positive-output state, the capacitor b e g i n s t o charge, and the cycle repeats itself. F r o m the p r e c e d i n g description w e see that the astable circuit oscillates and produces a square w a v e f o r m at the output of the op a m p . T h i s w a v e f o r m , and the w a v e f o r m s at the two i n p u t terminals of the o p a m p , a r e displayed i n Fig. 13.24(c). T h e period T of the square +
+
+
TH
+
0
+
TL
I—*»
j—AW
J'
iilllj llililll WÊÊÊ WÊÊÊÊÊÊ
-
v
2
--
(b)
•-
ËÈÈÈI *- i
r - - T o L_
(c)
FIGURE 1 3 . 2 4 (Continued) (b) The circuit obtained when the bistable multivibrator is implemented with the circuit of Fig. 13.19(a). (c) Waveforms at various nodes of the circuit in (b). This circuit is called an astable multivibrator.
w a v e c a n b e found as follows: D u r i n g t h e charging interval T t h e voltage v across t h e capacitor at any time t, with t = 0 at the beginning of T is given by (see A p p e n d i x D ) x
lt
v
= /..-(/...
w h e r e T = CR. Substituting v_ = /3L itt=T +
/, =
(il. )e
-t/T
gives
x
r h t ' - ^ - ^ J
1-/3 (a) FIGURE 1 3 . 2 4 (a) Connecting a bistable multivibrator with inverting transfer characteristics in a feedback loop with an RC circuit results in a square-wave generator.
(13.31)
Similarly, during t h e discharge interval T t h e voltage v_ at a n y time t, with t = 0 at t h e b e g i n n i n g o f T , is given b y 2
2
W- =
L_-(L_-RL )e +
-t/T
94
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
CIRCUITS 13.5
WAVEFORM GENERATION US,NG ASTABLE
MULTIVIBRATO
Substituting v_ - j$L_ at t = T gives 2
.
-.r^ld^Ll
(13
Tl
32)
E q u a t i o n s (13.31) a n d (13.32) c a n b e c o m b i n e d t o obtain t h e p e r i o d T= T + T . N o r m a l l y , L = - L _ , resulting in s y m m e t r i c a l square w a v e s of period T given b y X
2
+
T
= 2T lni-±J
(13.33)
N o t e that this s q u a r e - w a v e generator c a n b e m a d e t o h a v e variable frequency b y switch ing different capacitors C (usually in decades) a n d b y continuously adjusting R (to obtain continuous frequency control within each d e c a d e of frequency). A l s o , t h e w a v e f o r m across C can b e m a d e almost triangular by using a small value for t h e parameteL/J. H o w e v e r , triangu lar w a v e f o r m s of superior linearity c a n b e easily generated using t h e s c h e m e discussed next. Before leaving this section, h o w e v e r , n o t e that a l t h o u g h t h e astable circuit h a s n o stable states, it h a s t w o quasi-stable states a n d r e m a i n s in e a c h for a time interval d e t e r m i n e d b y t h e t i m e constant of t h e R C n e t w o r k a n d t h e thresholds of t h e bistable multivibrator.
13.15 For the circuit in Fig. 13.24(b), let the op-amp saturation voltages be ±10 V, 7?, =100 k Q , R =R = 1 M£2, and C = 0.01 ,uF. Find the frequency of oscillation. 2
IBiPKSSM 13.17 Consider a modification of ihe circuit of Fig. 13.24(b) in which i? is replaced by a pair of diodes con nected in parallel in opposite directions. For L . = -L_ = 12 V, R = R = 10 k Q , C = 0.1 LLF, and the diode voltage a constant denoted V0md an expression for frequency as a Junction or V .ii:V = 0.70 V at 2 5 C with a TC of - 2 mV/°C, find the frequency at 0°C. 25°C, 50?C, and 100°C. Note that the output of this circuit can be sent to a remotely connected frequency meter to provide a digital readout of icmivmiuiv. 1
2
D
u
C
A n s . / = 5 0 0 / l n [ ( l 2 + V ) / ( 1 2 - V ) ] H z ; 3995 Hz, 4281 Hz, 4611 H z , 5451 Hz u
D
F I G U R E 1 3 . 2 5 A general scheme for generating triangular and square waveforms.
L_. A t this m o m e n t t h e current t h r o u g h R a n d C will r e v e r s e direction, a n d its value will b e c o m e e q u a l to \L_\/R. I t follows t h a t t h e integrator o u t p u t will start to increase linearly with a p o s i t i v e s l o p e e q u a l t o \L_\/CR. T h i s will c o n t i n u e until the integrator output voltage reaches t h e p o s i t i v e threshold of t h e bistable circuit, V . A t this point t h e bistable circuit switches, its output b e c o m e s positive ( L ) , t h e current into t h e integrator r e v e r s e s direction, a n d t h e o u t p u t o f t h e integrator starts t o d e c r e a s e linearly, b e g i n n i n g a n e w cycle. TH
13.5.2 Generation of Triangular Waveforms
+
T h e e x p o n e n t i a l w a v e f o r m s g e n e r a t e d i n t h e astable circuit of Fig. 13.24 c a n b e c h a n g e d to triangular b y replacing t h e l o w - p a s s R C circuit w i t h a n integrator. ( T h e integrator is, after all, a l o w - p a s s circuit with a corner frequency at dc.) T h e integrator causes linear charging and d i s c h a r g i n g of t h e capacitor, thus p r o v i d i n g a triangular w a v e f o r m . T h e resulting circuit is s h o w n in F i g . 13.25(a). O b s e r v e that b e c a u s e t h e integrator is inverting, it is necessary to invert t h e characteristics of t h e bistable circuit. T h u s t h e bistable circuit required h e r e is of t h e n o n i n v e r t i n g t y p e and c a n b e i m p l e m e n t e d u s i n g t h e circuit of F i g . 13.2. . W e n o w p r o c e e d t o s h o w h o w t h e f e e d b a c k l o o p of F i g . 13.25(a) oscillates a n d gener ates a triangular w a v e f o r m v at t h e output of t h e integrator and a square w a v e f o r m v at the output o f t h e bistable circuit: L e t t h e o u t p u t o f the bistable circuit b e at L+. A current equal to L /R will flow into t h e resistor R a n d t h r o u g h capacitor C, causing t h e output of the inte grator t o linearly decrease with a slope of —L+/CR, a s s h o w n in F i g . 13.25(c). This will c o n t i n u e until t h e integrator output r e a c h e s t h e l o w e r threshold V of t h e bistable circuit, at w h i c h point t h e bistable circuit will switch states, its o u t p u t b e c o m i n g n e g a t i v e a n d equal to x
F r o m t h e discussion a b o v e it is relatively easy t o derive an expression for t h e period T of the square a n d triangular w a v e f o r m s . D u r i n g t h e interval T, w e h a v e , from Fig. 13.25(c), VTH
=
K CR
from w h i c h w e obtain
r, =
2
+
~ VTL 7\
^
CR-^S-
Similarly, d u r i n g T w e h a v e 2
TL
VTH-VTL
T
2
=
CR
,
(133.4)
11
9 6
CHAPTER 1 3
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
13.6
GENERATION O F A STANDARDIZED P U L S E - T H E MONOSTABLE MULTIVIBRATOR 1 1 9 7
from w h i c h w e obtain T
2
= CR
V
T
H
_~
V
T
L
(13.35)
L
T h u s to obtain s y m m e t r i c a l square w a v e s w e d e s i g n t h e bistable circuit to h a v e L = —L_. +
D13.18 Consider the circuit of Pig. 13.25(a) with the bistable circuit realized by the circuit in; Fig. 13.20(a). If the op amps have saturation voltages of ±10 V and if a capacitor C= 0.01 fjF and a resistor R-, = 10 k Q are used, find the values of R and R (note that R and R arc associated with the bistable circuit of Fig. 13.20a) such that the frequency of oscillation is 1 kHz and the triangular waveform has a 10-V peak-to-pcak amplitude. 2
x
2
Ans.5Hki>:2Hki2
13.6 GENERATION OF A STANDARDIZED P U L S E - T H E MONOSTABLE MULTIVIBRATOR In s o m e applications t h e n e e d arises for a p u l s e of k n o w n h e i g h t a n d w i d t h g e n e r a t e d in r e s p o n s e to a trigger signal. B e c a u s e the w i d t h of t h e p u l s e is predictable, its trailing e d g e c a n b e u s e d for t i m i n g p u r p o s e s — t h a t is, to initiate a particular t a s k at a specified t i m e . Such a s t a n d a r d i z e d p u l s e c a n b e g e n e r a t e d b y the third t y p e of multivibrator, t h e m o n o s t a b l e
FIGURE 1 3 . 2 5
(a) A n op-amp monostable circuit, (b) Signal waveforms i n the circuit o f (a).
multivibrator. T h e m o n o s t a b l e multivibrator h a s o n e stable state in w h i c h it c a n r e m a i n indefinitely. It also h a s a quasi-stable state to w h i c h it c a n b e triggered a n d in w h i c h it stays for a predeter m i n e d interval e q u a l to t h e desired w i d t h of t h e o u t p u t p u l s e . W h e n this interval expires, the m o n o s t a b l e m u l t i v i b r a t o r returns to its stable state a n d r e m a i n s there, awaiting a n o t h e r trig g e r i n g signal. T h e action of t h e m o n o s t a b l e m u l t i v i b r a t o r h a s given rise to its alternative
T h e n e g a t i v e v o l t a g e at A causes D to cut off, a n d C, b e g i n s to d i s c h a r g e exponentially t o w a r d L_ w i t h a t i m e constant C R . T h e m o n o s t a b l e m u l t i v i b r a t o r is n o w in its quasistable state, w h i c h will p r e v a i l until t h e declining v g o e s b e l o w the v o l t a g e at n o d e C, w h i c h is BL_. A t t h i s i n s t a n t t h e o p - a m p o u t p u t s w i t c h e s b a c k to L a n d t h e v o l t a g e at n o d e C g o e s b a c k to RL . C a p a c i t o r C then c h a r g e s t o w a r d L until d i o d e D turns o n a n d the circuit returns to its stable state. X
X
3
B
+
+
n a m e , t h e one
shot.
X
+
X
F i g u r e 13.26(a) s h o w s an o p - a m p m o n o s t a b l e circuit. W e o b s e r v e that this circuit is an a u g m e n t e d f o r m of the astable circuit of F i g . 13.24(b). Specifically, a c l a m p i n g d i o d e D
X
a d d e d across t h e capacitor Q , a n d a trigger circuit c o m p o s e d of capacitor C , resistor
is R,
2
4
F r o m F i g . 13.26(b), w e o b s e r v e that a n e g a t i v e p u l s e is g e n e r a t e d at the o u t p u t d u r i n g the quasi-stable state. T h e duration T of the o u t p u t p u l s e is d e t e r m i n e d from the e x p o n e n t i a l w a v e f o r m of v , B
a n d d i o d e D is c o n n e c t e d to t h e n o n i n v e r t i n g i n p u t t e r m i n a l of the o p a m p . T h e circuit oper 2
ates as follows: In the stable state, w h i c h p r e v a i l s in the a b s e n c e of the triggering signal, the o u t p u t of t h e o p a m p is at L a n d d i o d e D +
X
B
2
4
c
m i n e d b y t h e v o l t a g e divider R , R . T h u s v X
4
2
c
is greater t h a n
so that diode
U
will b e c o n d u c t i n g a v e r y small current a n d the v o l t a g e v
state is m a i n t a i n e d b e c a u s e BL
B
=
L_-(L_-V
m
) -'
/
C
A
e
3
v o l t a g e v to o n e d i o d e d r o p a b o v e g r o u n d . W e select R m u c h larger t h a n R D
v (t)
is c o n d u c t i n g t h r o u g h R a n d thus c l a m p i n g the will b e v e r y closely deter
= BL , w h e r e B = R /(R + +
L
R ).
L
b y substituting v (T) B
T h e stable
2
= RL_, PL_
V.
=
L_-(L_-VV,>
_ r / C l
*
3
m
N o w c o n s i d e r t h e application of a n e g a t i v e - g o i n g step at t h e trigger i n p u t a n d refer to the
which yields
signal w a v e f o r m s s h o w n in F i g . 13.26(b). T h e n e g a t i v e triggering e d g e will b e c o u p l e d to t h e c a t h o d e of d i o d e D
2
via capacitor C , a n d thus D 2
2
c o n d u c t s h e a v i l y a n d pulls n o d e C 1
d o w n . If the trigger signal is of sufficient h e i g h t to c a u s e v to g o b e l o w v , t h e o p a m p will c
3
\BL_-L_
(13.36)
B
see a n e t n e g a t i v e i n p u t v o l t a g e a n d its o u t p u t will s w i t c h to L_. T h i s in turn will c a u s e v
c
g o n e g a t i v e to fiL_, k e e p i n g the o p a m p in its n e w l y a c q u i r e d state. N o t e that D
2
to
For V
m
<é | L J , this e q u a t i o n can b e a p p r o x i m a t e d b y
will then
cut off, t h u s isolating t h e circuit from a n y further c h a n g e s at the trigger i n p u t terminal.
J - C ^ l n ^ )
(13.37)
1 1 9 8
CHAPTER 1 3
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS 13.7
Finally note that the m o n o s t a b l e circuit should n o t b e triggered again until capacitor C, has b e e n r e c h a r g e d to V ; m
otherwise the resulting output p u l s e will b e shorter t h a n normal. This
recharging t i m e is k n o w n as the r e c o v e r y p e r i o d . Circuit t e c h n i q u e s exist for shortening the
and a transistor Q that operates as a switch. O n e p o w e r supply (V ) is required for opera tion, w i t h the supply voltage typically 5 V . A resistive voltage divider, consisting of the three equal-valued resistors labeled R is connected across V a n d establishes the reference (threshold) voltages for the t w o c o m p a r a t o r s . T h e s e are V = | V for c o m p a r a t o r 1 and V = \V for c o m p a r a t o r 2. W e s t u d i e d S R flip-flops in C h a p t e r 1 1 . F o r o u r p u r p o s e s h e r e w e n o t e that an S R flip-flop (also c a l l e d a latch) is a b i s t a b l e circuit h a v i n g c o m p l e m e n t a r y o u t p u t s , d e n o t e d <2 a n d Q. I n t h e set state, t h e o u t p u t at Q is " h i g h " ( a p p r o x i m a t e l y e q u a l to V ) a n d that at Q is " l o w " ( a p p r o x i m a t e l y e q u a l to 0 V ) . I n t h e o t h e r s t a b l e state, t e r m e d the reset state, t h e o u t p u t at Q is l o w a n d that at Q is h i g h . T h e flip-flop is set b y a p p l y i n g a h i g h level (V ) to its set input terminal, labeled S. T o reset the flip-flop, a h i g h level is applied to the r e s e t i n p u t t e r m i n a l , l a b e l e d R. N o t e t h a t t h e r e s e t a n d set i n p u t t e r m i n a l s of t h e flipflop in t h e 555 circuit are c o n n e c t e d t o t h e o u t p u t s of c o m p a r a t o r 1 a n d c o m p a r a t o r 2 , respectively. T h e positive-input terminal of c o m p a r a t o r 1 is b r o u g h t out to an external terminal of the 555 p a c k a g e , labeled Threshold. Similarly, the negative-input terminal of c o m p a r a t o r 2 is c o n n e c t e d to an external terminal labeled Trigger, and the collector of transistor Q is con nected to a terminal labeled Discharge. Finally, the Q output of the flip-flop is connected to the output t e r m i n a l of the timer p a c k a g e , labeled Out. x
cc
h
cc
TH
recovery period.
INTEGRATED-CIRCUIT TIMERS
TL
cc
CC
cc
13 19 For the monostable circuit of Fig. 13.26(a) find the value of R that will result in a lOO-us output pulse 3
for C, = 0.1 ,u F. ß = 0,1, V„ = 0.7 V, and L. = - L _ = 12 V.
cc
A n s . t . r i L>
13.7
INTEGRATED-CIRCUIT TIMERS
Commercially available integrated-circuit packages exist that contain the b u l k of the circuitry n e e d e d to i m p l e m e n t m o n o s t a b l e and astable multivibrators with precise characteristics. In this section w e discuss the m o s t popular of such ICs, the 5 5 5 timer. Introduced in 1972 by the Signetics Corporation as a bipolar integrated circuit, the 555 is also available in C M O S technology and from a n u m b e r of manufacturers.
13.7.1 The 555 Circuit F i g u r e 13.27 s h o w s a b l o c k - d i a g r a m representation of the 555 timer circuit [ t o the actual , refer to G r e h e n e ( 1 9 8 4 ) ] . T h e circuit consists of two c o m p a r a t o r s , an S R flip-flop, circuit
l
13.7.2 Implementing a Monostable Multivibrator Using the 555 IC F i g u r e 13.28(a) s h o w s a m o n o s t a b l e m u l t i v i b r a t o r i m p l e m e n t e d u s i n g the 555 I C t o g e t h e r w i t h an e x t e r n a l r e s i s t o r R a n d an e x t e r n a l c a p a c i t o r C. In the stable state the flip-flop will b e in t h e reset state, a n d thus its Q o u t p u t will b e h i g h , t u r n i n g on transistor <2i- T r a n s i s t o r <2i w i l l b e saturated, a n d t h u s v w i l l b e c l o s e t o 0 V , r e s u l t i n g in a l o w level at the output of c o m p a r a t o r 1. T h e voltage at the trigger input terminal, labeled v , is k e p t h i g h ( g r e a t e r t h a n V ), a n d t h u s the o u t p u t of c o m p a r a t o r 2 also will b e l o w . F i n a l l y , n o t e t h a t s i n c e the flip-flop is in the reset state, Q w i l l b e l o w a n d t h u s v w i l l b e close to 0 V . T o trigger the m o n o s t a b l e multivibrator, a negative input p u l s e is applied to the trigger input terminal. A s t r i g g e r g ° b e l o w V , the output of c o m p a r a t o r 2 goes to the h i g h level, thus setting the flip-flop. O u t p u t Q of the flip-flop goes high, and thus v goes high, and out put Q goes low, turning off transistor Q . Capacitor C n o w begins to charge up t h r o u g h resistor R, and its voltage v rises exponentially t o w a r d V , as s h o w n in Fig. 13.28(b). T h e m o n o s t a b l e multivibrator is n o w in its quasi-stable state. This state prevails until v reaches, and b e g i n s to exceed, the threshold of c o m p a r a t o r 1, V , at w h i c h t i m e the output of c o m parator 1 g o e s high, resetting the flip-flop. O u t p u t Q of the flip-flop n o w goes high and turns on transistor Q . In turn, transistor Q rapidly discharges capacitor C, causing v to go to 0 V. A l s o , w h e n the flip-flop is reset its Q output goes low, a n d thus v goes b a c k to 0 V . T h e m o n o s t a b l e multivibrator is n o w b a c k in its stable state and is ready to receive a n e w triggering pulse. ,, c
tTiggei
TL
0
e s
TL
Threshold
0
R
I)
Out —o
x
c
i l . .
Comparator 2
rlip -Hop
cc
c
TH
S
Trigger
x
x
c
0
Discharge
;
100 il
F r o m the description a b o v e w e see that the m o n o s t a b l e multivibrator p r o d u c e s an output pulse v as indicated in Fig. 13.28(b). T h e w i d t h of the pulse, T, is the time interval that the m o n o s t a b l e multivibrator spends in the quasi-stable state; it can b e determined by reference to the w a v e f o r m s in Fig. 13.28(b) as follows: D e n o t i n g the instant at w h i c h the trigger p u l s e is applied as t = 0, the exponential w a v e f o r m of v can b e expressed as 0
c
Ground v =V (l-e-' ) /CR
FIGURE
13.27
A block diagram representation of the internal circuit of the 555 integrated-circuit timer.
c
cc
(13.38)
|Ö
1 1 9 9
13.7 CHAPTER 13
SIGNAL GENERATORS AND WAVEFORM-SHAPING
INTEGRATED-CIRCUIT
TIME
CIRCUITS
Substituting v
=V
c
= |V
TH
C C
at t = T gives
A Vc C
T = C 7 ? l n 3 = I.ICR
(13.39)
T h u s the p u l s e w i d t h is d e t e r m i n e d by the external c o m p o n e n t s C a n d R, w h i c h carl b e selected to h a v e values as precise as desired.
13.7.3 An Astable Multivibrator Using the 555 IC F i g u r e 13.29(a) s h o w s the circuit of an astable multivibrator e m p l o y i n g a 5 5 5 IC, t w o exter nal resistors, R and R , and an external capacitor C. T o see h o w the circuit operates refer to the w a v e f o r m s depicted in Fig. 13.29(b). A s s u m e that initially C is discharged and the flipflop is set. T h u s v is h i g h and Q is off. Capacitor C will charge u p t h r o u g h the series c o m bination of R and R , and the voltage across it, v , will rise exponentially t o w a r d V . A s v crosses the J e v e l equal to V , the output of c o m p a r a t o r 2 g o e s low. This, h o w e v e r , h a s no effect on the circuit operation, and the flip-flop r e m a i n s set. Indeed, this state continues until v r e a c h e s and b e g i n s to exceed the threshold of c o m p a r a t o r 1, V . A t this instant of time, the output of c o m p a r a t o r 1 g o e s h i g h and resets the flip-flop. T h u s v g o e s low, O g o e s high, and transistor Q is turned on. T h e saturated transistor Q causes a voltage of approxi mately zero volts to a p p e a r at the c o m m o n n o d e of R and R . T h u s C begins to discharge t h r o u g h R a n d the collector of Q . T h e voltage v decreases exponentially with a t i m e con stant CR t o w a r d 0 V. W h e n v reaches the threshold of c o m p a r a t o r 2, V , the output of c o m p a r a t o r 2 , goes h i g h and sets the flip-flop. T h e output v then goes high, and Q goes low, turning off Q . C a p a c i t o r C begins to charge t h r o u g h the series equivalent of R and R , and its voltage rises exponentially t o w a r d V with a t i m e constant C(R + R ). T h i s rise continues until v r e a c h e s V , at w h i c h time the output of c o m p a r a t o r 1 goes high, resetting the flip-flop, and the cycle continues. F r o m the description a b o v e w e see that the circuit of Fig. 13.29(a) oscillates and p r o duces a square w a v e f o r m at the output. T h e frequency of oscillation can b e determined as follows. R e f e r e n c e to Fig. 13.29(b) indicates that the output will b e high during the interval T , in w h i c h v rises from V to V . T h e exponential rise of v can b e described by A
B
0
A
x
B
c
cc
c
TL
c
m
0
l
x
A
B
x
B
B
c
c
TL
0
x
A
cc
c
(a) +~ t to
V
cc
H
-
A
m
c
TL
V
TH
v
w
c
= V
cc
c
/C(Ri+RB)
- (V
cc
- V )e~'
(13.40)
TL
w h e r e t = 0 is the instant at w h i c h the interval T begins. Substituting v t=T andV = \V results in H
H
TL
B
B
=V
c
= \V
TH
CC
T
H
= C(R
+ R )\n
A
B
2 = 0.69 C(R
+ R)
A
(13.41)
B
W e also n o t e from Fig. 13.29(b) that v will b e low during the interval T , in w h i c h v from V to V . T h e exponential fall of v can b e described by 0
m
L
TL
c
(
(13.42)
ul
w h e r e w e h a v e taken t = 0 as the b e g i n n i n g of the interval T . Substituting v at t = T and V = | V results in L
TH
c
=V
TL
=
\V
CC
C C
7V = CR In 2 = 0.69 CR B
(b) FIGURE 1 3 . 2 8 (a) The 555 timer connected to implement a monostable multivibrator, (b) Wave: of the circuit in (a).
falls
c
,, . = v c
L
at
CC
'
B
(13.43)
E q u a t i o n s (13.41) and (13.43) can be c o m b i n e d to obtain the period T of the output square w a v e as T=
T +T H
L
= 0.69C(R
A
+
2R ) B
(13.44)
CHAPTER 1 3
13.8
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
NONLINEAR WAVEFORM-SHAPING CIRCUITS
1 2 0 3
A l s o , the d u t y cycle of t h e output square w a v e can b e f o u n d from E q s . (13.41) and (13.43): —
,
Tt/
D u t y c y c l e = ^
RA + =
RR
^ _ i L
(13.45)
N o t e that t h e duty cycle will a l w a y s b e greater than 0.5 ( 5 0 % ) ; it a p p r o a c h e s 0.5 if R selected to b e m u c h smaller than R (unfortunately, at the e x p e n s e of supply current).
A
is
B
13.20 Using a 10-nF capacitor C, find the value of R that yields an output pulse of 1.00 ,us in ihe monostable circuit of Fig. 13.28(a). Ans. ' U k<>
D13.21 For the circuit in Fig. 13.29(a), with a 1000-pF capacitor, and find the values of R oscillation frequency of 100 kHz and a duty cycle of 7 5 % .
A
and R that result in an
Ans. 7.2 k Q . 3.6 k Q
13.8 NONLINEAR WAVEFORM-SHAPING CIRCUITS D i o d e s or transistors can b e c o m b i n e d with resistors to synthesize t w o - p o r t n e t w o r k s h a v i n g arbitrary n o n l i n e a r transfer characteristics. S u c h t w o - p o r t n e t w o r k s can b e e m p l o y e d in w a v e f o r m s h a p i n g — t h a t is, c h a n g i n g t h e w a v e f o r m of an input signal in a prescribed m a n ner to p r o d u c e a w a v e f o r m of a desired s h a p e at the output. In this section w e illustrate this application b y a c o n c r e t e e x a m p l e : t h e s i n e - w a v e s h a p e r . T h i s is a circuit w h o s e p u r p o s e is to c h a n g e the w a v e f o r m of an input t r i a n g u l a r - w a v e signal to a sine w a v e . T h o u g h simple, the s i n e - w a v e s h a p e r is a practical building b l o c k u s e d extensively in function generators. T h i s m e t h o d of g e n e r a t i n g sine w a v e s should b e contrasted to that u s i n g linear oscillators (Sections 1 3 . 1 - 1 3 . 3 ) . A l t h o u g h linear oscillators p r o d u c e sine w a v e s of h i g h purity, they are not c o n v e n i e n t at very l o w frequencies. A l s o , linear oscillators are in general m o r e difficult to t u n e o v e r w i d e frequency ranges. In the following w e discuss t w o distinctly different techniques for d e s i g n i n g s i n e - w a v e shapers.
13.8.1 The Breakpoint Method In the b r e a k p o i n t m e t h o d the desired nonlinear transfer characteristic (in our c a s e the sine function s h o w n in F i g . 13.30) is i m p l e m e n t e d as a p i e c e w i s e linear c u r v e . D i o d e s are uti lized as switches that turn on at the various breakpoints of t h e transfer characteristic, t h u s switching into the circuit additional resistors that c a u s e the transfer characteristic to c h a n g e slope. C o n s i d e r the circuit s h o w n in Fig. 13.31(a). It consists of a c h a i n of resistors c o n n e c t e d across t h e entire s y m m e t r i c a l voltage supply +V, -V. T h e p u r p o s e of this v o l t a g e divider is to g e n e r a t e reference voltages that will serve to d e t e r m i n e t h e b r e a k p o i n t s in t h e transfer characteristic. In o u r e x a m p l e these reference voltages are denoted +V , . + V -V -V . N o t e that the entire circuit is symmetrical, driven b y a s y m m e t r i c a l triangular w a v e and generat ing a s y m m e t r i c a l s i n e - w a v e output. T h e circuit a p p r o x i m a t e s each quarter-cycle of the sine w a v e b y three straight-line s e g m e n t s ; the breakpoints b e t w e e n these s e g m e n t s are deter m i n e d b y t h e reference voltages V and V . 2
1
2
b
h
2
B
13.8
NONLINEAR WAVEFORM-SHAPING CIRCUITS
jT*"-' •"CV
T h e circuit works as follows: Let the input be the triangular w a v e s h o w n in Fig. 13.31(b), a n d consider first t h e quarter-cycle defined b y the t w o points labeled 0 and 1. W h e n the input signal is less in m a g n i t u d e than V n o n e of t h e diodes c o n d u c t s . T h u s zero current flows t h r o u g h R , and the output voltage at B will b e equal to t h e input voltage. B u t as the input rises to Vj and above, D ( a s s u m e d ideal) begins to conduct. A s s u m i n g that the c o n d u c t i n g D b e h a v e s as a short circuit, w e see that, for vj > V , u
4
2
2
x
v
0
= V + (v -V )1
l
R
s
l
T h i s implies that as t h e input continues to rise a b o v e V t h e output follows b u t with a r e d u c e d slope. T h i s gives rise to the s e c o n d s e g m e n t in t h e output w a v e f o r m , as s h o w n in F i g . 13.31(b). N o t e that in d e v e l o p i n g the equation a b o v e w e h a v e a s s u m e d that the resis t a n c e s in the v o l t a g e divider are l o w e n o u g h in value to c a u s e t h e voltages V and V to b e c o n s t a n t i n d e p e n d e n t of the current c o m i n g from the input. x
x
2
N e x t c o n s i d e r w h a t h a p p e n s as t h e v o l t a g e at p o i n t B r e a c h e s t h e s e c o n d b r e a k p o i n t d e t e r m i n e d b y V . A t this point, D c o n d u c t s , thus l i m i t i n g t h e o u t p u t v to V ( p l u s , of c o u r s e , the v o l t a g e drop across D if it is n o t a s s u m e d to b e ideal). This gives rise to the third s e g m e n t , w h i c h is flat, in t h e o u t p u t w a v e f o r m . T h e o v e r a l l r e s u l t is t o " b e n d " t h e w a v e f o r m a n d s h a p e it into an a p p r o x i m a t i o n of t h e first q u a r t e r - c y c l e of a sine w a v e . T h e n , b e y o n d t h e p e a k of t h e input t r i a n g u l a r w a v e , as t h e input v o l t a g e d e c r e a s e s , t h e p r o c e s s u n f o l d s , t h e o u t p u t b e c o m i n g p r o g r e s s i v e l y m o r e like t h e i n p u t . F i n a l l y , w h e n t h e i n p u t g o e s sufficiently n e g a t i v e , t h e p r o c e s s b e g i n s to r e p e a t at -V a n d -V for t h e n e g a t i v e half-cycle. 2
{
0
2
x
l
2
A l t h o u g h the circuit is relatively s i m p l e , its p e r f o r m a n c e is surprisingly good. A m e a sure of g o o d n e s s usually t a k e n is to quantify the purity of the output sine w a v e b y specifying t h e p e r c e n t a g e total h a r m o n i c distortion ( T H D ) . This is t h e p e r c e n t a g e ratio of t h e r m s v o l t a g e of all h a r m o n i c c o m p o n e n t s a b o v e t h e fundamental frequency (which is the fre q u e n c y of the triangular w a v e ) to the r m s v o l t a g e of the fundamental (see also C h a p t e r 14). Interestingly, o n e r e a s o n for the g o o d p e r f o r m a n c e of t h e d i o d e shaper is the beneficial effects p r o d u c e d b y t h e n o n i d e a l i-v characteristics of the d i o d e s — t h a t is, t h e e x p o n e n t i a l k n e e of t h e j u n c t i o n d i o d e as it goes into forward conduction. T h e c o n s e q u e n c e is a rela tively s m o o t h transition from o n e line s e g m e n t to the next. Practical i m p l e m e n t a t i o n s of the b r e a k p o i n t sine-wave shaper e m p l o y six to eight seg m e n t s ( c o m p a r e d w i t h t h e three u s e d in t h e e x a m p l e a b o v e ) . A l s o , transistors are u s u a l l y e m p l o y e d to p r o v i d e m o r e versatility in t h e design, w i t h the goal b e i n g increased precision a n d l o w e r T H D . [See G r e b e n e (1984), p a g e s 5 9 2 - 5 9 5 . ]
13.8.2 The Nonlinear-Amplification Method T h e other m e t h o d w e discuss for the c o n v e r s i o n of a triangular w a v e into a sine w a v e is b a s e d on feeding t h e triangular w a v e to the input of an amplifier h a v i n g a nonlinear transfer characteristic that a p p r o x i m a t e s the sine function. O n e such amplifier circuit consists of a differential pair with a resistance connected b e t w e e n the t w o emitters, as s h o w n in Fig. 13.32. W i t h a p p r o p r i a t e c h o i c e of t h e v a l u e s of t h e bias current / a n d t h e r e s i s t a n c e R, t h e differ ential amplifier can b e m a d e to h a v e a transfer characteristic that closely a p p r o x i m a t e s that s h o w n in F i g . 13.30. O b s e r v e that for s m a l l v t h e transfer c h a r a c t e r i s t i c of t h e circuit of Fig. 13.32 is almost linear, as a sine w a v e f o r m is near its zero crossings. A t large values of v, t h e n o n l i n e a r characteristics of the B J T s r e d u c e t h e gain of t h e amplifier and c a u s e t h e transfer characteristic to b e n d , a p p r o x i m a t i n g the sine w a v e as it a p p r o a c h e s its peak. [ M o r e details o n this circuit can b e found in G r e b e n e (1984), p a g e s 5 9 5 - 5 9 7 . ] v
}
FIGURE 1 3 . 3 1 (a) A three-segment sine-wave shaper. (b) The input triangular waveform and the output approximately sinusoidal waveform.
1 2 0 5
1
CHAPTER 13
206
13.9
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
P R E C I S I O N RECTIFIER CIRCUITS
the case. F o r instance, in instrumentation applications, the signal to b e rectified can b e of a very small a m p l i t u d e , say 0.1 V , m a k i n g it i m p o s s i b l e to e m p l o y t h e c o n v e n t i o n a l rectifier circuits. A l s o , in i n s t r u m e n t a t i o n applications the n e e d arises for rectifier circuits w i t h v e r y precise transfer characteristics. In this section w e study circuits that c o m b i n e diodes a n d o p a m p s to i m p l e m e n t a variety of rectifier circuits w i t h precise characteristics. Precision rectifiers, w h i c h c a n b e c o n s i d e r e d a special class of w a v e - s h a p i n g circuits, find application i n t h e design of instrumentation systems. A n introduction to precision rectifiers w a s p r e s e n t e d in C h a p t e r 3 . This material, however, is r e p e a t e d h e r e for t h e r e a d e r ' s c o n v e n i e n c e .
Vj o
(Triangular wave) FIGURE 1 3 . 3 2 A differential pair with an emit ter degeneration resistance used to implement a triangular-wave to sine-wave converter. Opera tion of the circuit can be graphically described by Fig. 13.30.
13.9.1 Precision Half-Wave Rectifier-The "Superdiode" Figure 13.33(a) s h o w s a precision half-wave-rectifier circuit consisting of a d i o d e p l a c e d i n the negative-feedback p a t h of an o p a m p , w i t h R b e i n g t h e rectifier l o a d resistance. T h e circuit w o r k s as follows: If Vj goes positive, t h e output v o l t a g e v of t h e o p a m p will g o positive a n d t h e d i o d e will conduct, thus establishing a closed f e e d b a c k p a t h b e t w e e n t h e op a m p ' s output terminal a n d t h e n e g a t i v e input terminal. T h i s negative-feedback p a t h will cause a virtual short circuit to appear b e t w e e n t h e t w o input terminals of t h e o p a m p . T h u s the voltage at t h e n e g a t i v e input terminal, w h i c h is also the output v o l t a g e v , will e q u a l (to within a few millivolts) that at t h e positive input terminal, w h i c h is t h e input voltage v A
0
D13 22 The circuit in Fig. El 3.22 is required to provide a three-segment approximation to the nonlinear i-v char acteristic i = 0.1 j ' . where v is the voltage in volts and / is the current in tnilliamperes. Find the values of R R„ and R, such thai the approximation is perfect at v = 2 V. 4 V, and 8 V. Calculate the error in current value"at v= 3 V, 5 V, 7 V. and 10 V. Assume ideal diodes.
h
2
v
0
= Vj
Vj>0
lt
Note that t h e offset v o l t a g e (— 0.5 V ) exhibited in the simple h a l f - w a v e rectifier circuit is n o longer present. F o r t h e o p - a m p circuit to start operation, Vj h a s to e x c e e d only a negligibly small voltage e q u a l t o the d i o d e drop d i v i d e d b y t h e o p a m p ' s o p e n - l o o p gain. In other words, t h e straight-line transfer characteristic v — vj almost passes t h r o u g h t h e origin. T h i s makes this circuit suitable for applications i n v o l v i n g very small signals. C o n s i d e r n o w t h e c a s e w h e n v, goes n e g a t i v e . T h e o p a m p ' s output v o l t a g e v will t e n d to follow a n d g o n e g a t i v e . T h i s will reverse-bias t h e diode, a n d n o current will flow t h r o u g h resistance R, c a u s i n g v to r e m a i n equal to 0 V . T h u s for v
A
0
FIGURE E l 3.22 Ans. 5 k Q . 1.25 k Q . .1.25 k Q ; - 0 . 3 mA, +0.1 mA. - 0 . 3 n A . 0 13 23 A detailed analvsis of the circuit in Fig. 13.32 shows that its optimum performance occurs when the values of / and R are selected so that 7?/ = 2.5 V „ where V is the thermal voltage. For this design, the peak ampli tude of the input triansiular wave should be 6.6V-,-, and the corresponding sine wave across R has a peak value of 2.42V . For / = 0.25 m A and R = 10 k Q , find the peak amplitude of the sine-wave output v . Assume a — 1. Ans. 4.s i \ 7
r
0
7
c
13.9
t
u
PRECISION RECTIFIER CIRCUITS
Rectifier circuits w e r e studied in C h a p t e r 3 , w h e r e t h e e m p h a s i s w a s o n their application m p o w e r - s u p p l y design. I n such applications t h e v o l t a g e s b e i n g rectified are usually much greater t h a n t h e d i o d e voltage drop, r e n d e r i n g t h e exact v a l u e of t h e d i o d e drop unimportan to t h e p r o p e r operation of t h e rectifier. O t h e r applications exist, h o w e v e r , w h e r e this is no
(a)
(b)
FIGURE 1 3 . 3 3 (a) The "superdiode" precision half-wave rectifier and (b) its almost ideal transfer characteristic. Note that when v, > 0 and the diode conducts, the op amp supplies the load current, and the source is conveniently buffered, an added advantage.
CHAPTER 13
13.9
SIGNAL GENERATORS A N D W A V E F O R M - S H A P I N G CIRCUITS
characteristics h a v e been almost completely m a s k e d b y placing the diode in the negativefeedback p a t h of an o p a m p . T h i s is another d r a m a t i c application of n e g a t i v e feedback. T h e c o m b i n a t i o n of d i o d e and o p a m p , s h o w n in t h e d a s h e d b o x in F i g . 13.33(a), is appropriately referred to as a " s u p e r d i o d e . " A s u s u a l , t h o u g h , n o t all is w e l l . T h e circuit of F i g . 13.33 h a s s o m e d i s a d v a n t a g e s : W h e n v, g o e s n e g a t i v e a n d v = 0, t h e entire m a g n i t u d e of v, a p p e a r s b e t w e e n t h e t w o i n p u t t e r m i n a l s of t h e o p a m p . If this m a g n i t u d e is g r e a t e r t h a n few volts, t h e o p a m p may b e d a m a g e d u n l e s s it is e q u i p p e d w i t h w h a t is c a l l e d " o v e r v o l t a g e p r o t e c t i o n " (a feature that m o s t m o d e r n I C o p a m p s h a v e ) . A n o t h e r d i s a d v a n t a g e is that w h e n v, is n e g a t i v e , t h e o p a m p will b e saturated. A l t h o u g h n o t h a r m f u l t o t h e o p a m p , saturation s h o u l d usu ally b e a v o i d e d , s i n c e g e t t i n g t h e o p a m p o u t of t h e s a t u r a t i o n r e g i o n a n d b a c k into its linear r e g i o n of operation r e q u i r e s s o m e t i m e . T h i s t i m e d e l a y will o b v i o u s l y slow d o w n circuit o p e r a t i o n a n d limit the f r e q u e n c y of o p e r a t i o n of t h e s u p e r d i o d e half-wave-rectifier circuit. 0
PRECISION RECTIFIER CIRCUITS
T h e transfer characteristic of the circuit is s h o w n in F i g . 13.34(b). N o t e that unlike the situation for t h e circuit s h o w n in Fig. 13.33, h e r e the slope of the characteristic can b e set to any desired v a l u e , i n c l u d i n g unity, b y selecting appropriate values for R and R . x
2
2
13.9.3 An Application: Measuring AC Voltages A s o n e of t h e m a n y p o s s i b l e a p p l i c a t i o n s of t h e p r e c i s i o n rectifier circuits d i s c u s s e d in this section, c o n s i d e r t h e b a s i c ac v o l t m e t e r circuit s h o w n in F i g . 13.35. T h e circuit c o n sists of a h a l f - w a v e r e c t i f i e r — f o r m e d b y o p a m p A , d i o d e s D a n d D , a n d resistors R and R —and a first-order l o w - p a s s f i l t e r — f o r m e d b y o p a m p A , resistors R a n d R , and c a p a c i t o r C. F o r an i n p u t s i n u s o i d h a v i n g a p e a k a m p l i t u d e V t h e o u t p u t v of t h e rectifier will consist of a half sine w a v e h a v i n g a p e a k amplitude of V R /R . It can b e s h o w n using Fourier series analysis that t h e w a v e f o r m of v has an average value of CV /n)(R /R ) in addition to h a r m o n i c s of the frequency co o f t h e input signal. T o r e d u c e the a m p l i t u d e s of all t h e s e h a r m o n i c s t o n e g l i g i b l e levels, the c o r n e r f r e q u e n c y of t h e l o w - p a s s filter s h o u l d b e c h o s e n m u c h s m a l l e r than t h e l o w e s t e x p e c t e d f r e q u e n c y co^ of t h e i n p u t sine w a v e . This leads to x
x
2
13.9.2 An Alternative Circuit
2
A s m e n t i o n e d before, the major a d v a n t a g e of the i m p r o v e d half-wave-rectifier circuit is that t h e f e e d b a c k l o o p a r o u n d the op a m p r e m a i n s closed at all t i m e s . H e n c e t h e o p a m p r e m a i n s in its linear operating region, avoiding the possibility of saturation and the associ ated time delay r e q u i r e d to "get o u t " of saturation. D i o d e D " c a t c h e s " the o p - a m p output voltage as it g o e s n e g a t i v e a n d c l a m p s it to o n e d i o d e d r o p b e l o w ground; h e n c e D is called a "catching d i o d e . "
2
x
2
3
p
A n alternative precision rectifier circuit that d o e s n o t suffer from the disadvantages m e n tioned a b o v e is s h o w n in F i g . 13.34. T h e circuit operates in the following m a n n e r : For positive V[, d i o d e D c o n d u c t s a n d closes t h e negative-feedback l o o p a r o u n d the o p a m p . A virtual g r o u n d therefore will a p p e a r at the inverting input terminal, and t h e op a m p ' s output will b e clamped at o n e d i o d e d r o p b e l o w ground. T h i s n e g a t i v e voltage will k e e p diode D off, a n d n o current will flow in the f e e d b a c k resistance R . It follows that the rectifier output voltage will b e zero. 2
x
2
A s vj g o e s n e g a t i v e , t h e v o l t a g e at t h e i n v e r t i n g i n p u t t e r m i n a l w i l l t e n d to g o nega tive, c a u s i n g t h e v o l t a g e at t h e o p a m p ' s o u t p u t t e r m i n a l to g o p o s i t i v e . T h i s will c a u s e D to b e r e v e r s e - b i a s e d a n d h e n c e c u t off. D i o d e D , h o w e v e r , w i l l c o n d u c t t h r o u g h R , thus e s t a b l i s h i n g a n e g a t i v e - f e e d b a c k p a t h a r o u n d t h e o p a m p a n d forcing a v i r t u a l g r o u n d to a p p e a r at t h e i n v e r t i n g i n p u t t e r m i n a l . T h e c u r r e n t t h r o u g h t h e f e e d b a c k r e s i s t a n c e R will b e e q u a l to t h e c u r r e n t t h r o u g h t h e i n p u t r e s i s t a n c e R . T h u s for R = R t h e o u t p u t v o l t a g e v will be
p
x
2
x
x
1 CR
4
p
2
x
< co„
A
2
x
2
T h e n the output v o l t a g e v will be m o s t l y dc, w i t h a value 2
2
x
x
2
2
nR R x
3
0
w h e r e R /R is the dc gain of the low-pass filter. N o t e that this voltmeter essentially m e a sures the a v e r a g e value of the negative parts of the input signal but can b e calibrated to p r o v i d e r m s r e a d i n g s for input sinusoids. 4
v
0
= -Vj
V[<0
3
R
2
A/W
o v
2
(a)
(b)
FIGURE 1 3 . 3 4 (a) An improved version of the precision half-wave rectifier: Diode D is included to keep the feedback loop closed around the op amp during the off times of the rectifier diode D , thus preventing the op amp from saturating, (b) The transfer characteristic for R = R . 2
x
2
X
FIGURE 1 3 . 3 5 A simple ac voltmeter consisting of a precision half-wave rectifier followed by a firstorder low-pass filter.
1 2 0 9
13.9 10
CHAPTER 13
Lj§
PRECISION RECTIFIER CIRCUITS
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
D
A
13.24 Consider the operaiional lvclil'ier
OR M I P C R D I O D C circuil o i l ig. 13.3 v a i. vrith R - I kQ. l ' O I .•. 11» m \ . I V. and - 1 V what are (he voltages that result at the rectifier output and at the output of.the op amp? A s s u m e that the o p amp is ideal and that its output saturates at ±12 V. The diode has a 0.7-V drop at 1-mA current, attd the voltage drop changes by 0.1. V per decade of current change.
-w-
Ao-
:
C
Ans. I i » m \ . n . 5 l V : I \ . I." \ : i» \ . -12 \
RL
13.25 If the diode in the circuit of Fig. 13.33(a) is reversed, what is the transfer characteristic v„ as a function
AAA,
Off.'
I
I
Ans. v0 = 0 for v, > 0; vl} = v, for v, < 0
13.26 Consider the circuit in Fig. 13.34(a) with R = 1 k Q and R = 10 k Q . Find v and the voltage at the amplifier output for v, = +1 V, - 1 0 m V , and - 1 V. A s s u m e the op a m p to be ideal with saturation voltages of ±12 V. T h e diodes have 0.7-V voltage drops al 1 m A , and the voltage drop changes by 0.1 V per decade of current change. x
2
FIGURE 1 3 . 3 6 Principle of full-wave rectification.
0
A n s . n \ . - l C ? \ : i ) . l V.u.r. \ : 10 V. 1(1.7 \ 13.27 If the diodes in the circuit of Fig. 13.34(a) are reversed, what is the transfer characteristic v as a func0
iS|||i©ri|r^^ Ans. v = -{R /R )v, 0
2
x
for v, > 0: v = 0 for v,< 0 0
13.28 Find the transfer characteristic for the circuit in Fig. E l 3.28.
FIGURE 1 3 . 3 7 (a) Precision full-wave rectifier based on the conceptual circuit of Fig. 13.36. (b) Transfer characteristic of the circuit in (a). FIGURE E l 3 . 2 8
the t w o i n p u t t e r m i n a l s of A , and the v o l t a g e at the negative-input terminal, w h i c h is t h e 2
Ans. v., • 0 for vt > - 5 V : v0 = ^
- 5 for v, < - 5 V
output v o l t a g e of t h e circuit, will b e c o m e e q u a l to the input. T h u s n o current will flow t h r o u g h R a n d R , a n d the v o l t a g e at the inverting input of A will b e e q u a l to the i n p u t and x
2
:
h e n c e positive. Therefore t h e output t e r m i n a l (F) of A[ will g o n e g a t i v e until A
x
saturates.
This causes D to b e t u r n e d off. x
13.9.4 Precision Full-Wave Rectifier
N e x t c o n s i d e r w h a t h a p p e n s w h e n A g o e s negative. T h e t e n d e n c y for a negative voltage
W e n o w derive a circuit for a precision full-wave rectifier. F r o m C h a p t e r 3 w e k n o w that full-
at the n e g a t i v e input of A , causes F to rise, m a k i n g D c o n d u c t to supply R and a l l o w i n g the
w a v e rectification is achieved b y inverting t h e negative h a l v e s of the input-signal w a v e f o r m
f e e d b a c k l o o p a r o u n d A j to b e closed. T h u s a virtual g r o u n d appears at t h e n e g a t i v e input of
and applying the resulting signal to another d i o d e rectifier. T h e outputs of the t w o rectifiers
A
are then j o i n e d to a c o m m o n load. Such an a r r a n g e m e n t is depicted in Fig. 13.36, w h i c h also
a g e , to b e e q u a l to t h e negative of t h e i n p u t \ o l t a g e at A and thus positive. T h e c o m b i n a t i o n
s h o w s the w a v e f o r m s at various n o d e s . N o w replacing d i o d e D
A
with a superdiode, and
replacing diode Z) and the inverting amplifier with the inverting precision half-wave rectifier B
of Fig. 13.34 b u t without the catching diode, w e obtain the precision
full-wave-rectifier
x
l 5
L
and t h e t w o e q u a l resistances R and R force the v o l t a g e at C, w h i c h is the output volt x
2
of positive v o l t a g e at C and n e g a t i v e voltage at A c a u s e s t h e output of A to saturate in t h e 2
negative direction, thus k e e p i n g D
2
off.
T h e overall result is perfect full-wave rectification, as r e p r e s e n t e d b y the transfer c h a r a c teristic in F i g . 13.37(b). T h i s precision is, of c o u r s e , a result of p l a c i n g t h e diodes in o p - a m p
circuit of Fig. 13.37(a). T o see h o w the circuit of F i g . 13.37(a) o p e r a t e s , c o n s i d e r first t h e c a s e of p o s i t i v e input
f e e d b a c k l o o p s , thus m a s k i n g their nonidealities. T h i s circuit is o n e of m a n y possible p r e c i
at A. T h e output of A will g o positive, m i n i n g D on, w h i c h will c o n d u c t t h r o u g h R and thus
sion full-wave-rectifier or a b s o l u t e - v a l u e c i r c u i t s . A n o t h e r related i m p l e m e n t a t i o n of this
close the f e e d b a c k loop a r o u n d A . A virtual short circuit will t h u s b e established b e t w e e n
function is e x a m i n e d in E x e r c i s e 13.30.
2
2
2
L
' F ^
1211
I
1 2 1 2
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
13.9
CIRCUITS
PRECISION RECTIFIER CIRCUITS
& | |
1 2 1 3
a r e a d i n g that is p r o p o r t i o n a l to t h e a v e r a g e of t h e absolute v a l u e of t h e i n p u t voltage v . A l l A
the n o n i d e a l i t i e s of t h e m e t e r a n d of t h e d i o d e s are m a s k e d b y p l a c i n g t h e b r i d g e circuit in the n e g a t i v e - f e e d b a c k l o o p of t h e o p a m p . O b s e r v e that w h e n v is positive, current flows A
13 29 In the full-wave rectifier circuit of Fig. 13.37(a) let R =R = R = 10 k Q and assume the op amps to be ideal except for output saturation at ± 1 2 V. W h e n conducting a current of 1 m A , each diode exhibits a voltage drop of 0.7 V, and this voltage changes by 0.1 V per decade of current change. Find v , v , and ^ c o r r e s p o n d i n g t o w = +0.1 V . + l V, + 1 0 V . - 0 . 1 V , a n d - 1 0 V. t
2
L
0
E
from t h e o p - a m p o u t p u t t h r o u g h D
h
M , Z) , a n d R. W h e n v is n e g a t i v e , current flows into 3
A
the o p - a m p o u t p u t t h r o u g h R, D , M , a n d Z) . T h u s t h e f e e d b a c k l o o p r e m a i n s closed for 2
4
both p o l a r i t i e s of v . T h e resulting virtual short circuit at t h e i n p u t terminals of the o p a m p A
causes a r e p l i c a of v to a p p e a r across R. T h e circuit of F i g . 13.38 p r o v i d e s a relatively accu A
7
Ans. +0.1 V, +0.6 V . - 1 2 V : +1 V. - 1 . 6 V . - 1 2 V; +10 V . +10.7 V, - 1 2 V ; +0.1 V, - 1 2 V , +0.63 V : + 1 V .
rate h i g h - i n p u t - i m p e d a n c e ac voltmeter u s i n g an i n e x p e n s i v e m o v i n g - c o i l meter.
- 1 2 \ . - 1.63 V ; + 1 0 V . - i : Y . - - l 11.7? \
D13 30 T h e block diagram shown in Fig. E13.30(a) gives another possible arrangement for implementing the absolute-value or full-wave-rectifier operation depicted symbolically in Fig. HI 3.30(b). T h e block diagram consists of t w o boxes: a half-wave rectifier, which can b e i m p l e m e n t e d * y # e circuit in o T i 3 34(a) after reversing both d i o d e s , and a weighted inverting summer. C o n p n | e j y o u r s e l f that thfs block diagram does in fact realize the absolute-value operation. Then draw a complete circuit diagram, giving reasonable values for all resistors.
EXERCISE D13.31 In the circuit of Fig. 13.38, find the value of R that would cause the meter to provide a full-scale read ing when the input voltage is a sine wave of 5 V rms. Let meter M have a 1-mA, 5 0 - Q movement (i.e., its resistance is 50 LI, and it provides full-scale deflection when the average current through it is 1 m A ) . W h a t are the approximate maximum and minimum voltages at m e op a m p ' s output? Assume that the diodes have constant 0.7-V drops when conducting.
F i
v
0
=
Ans. 4.5 kit
v °
V
t
vi (b)
13.9.6 Precision Peak Rectifiers Including t h e d i o d e of t h e p e a k rectifier studied in Chapter 3 inside the negative-feedback loop of an op a m p , as s h o w n in F i g . 13.39, results in a precision p e a k rectifier. T h e d i o d e - o p - a m p
(a)
combination will b e r e c o g n i z e d as the superdiode of F i g . 13.33(a). Operation of t h e circuit in Fig. 13.39 is q u i t e straightforward. F o r v greater than t h e output voltage, the o p a m p will {
FiGURE E l 3 . 3 0
drive t h e d i o d e o n , thus closing t h e negative-feedback path and causing the o p a m p to act as a follower. T h e o u t p u t voltage will therefore follow that of t h e input, with t h e o p a m p sup
13.9.5 A Precision Bridge Rectifier for Instrumentation Applications
plying t h e c a p a c i t o r - c h a r g i n g current. This process continues until t h e input reaches its p e a k
T h e b r i d g e rectifier circuit studied in C h a p t e r 3 c a n b e c o m b i n e d with a n o p a m p to provide
terminals. T h u s its output will g o negative t o t h e saturation level and the diode will turn off.
useful p r e c i s i o n circuits. O n e such a r r a n g e m e n t is s h o w n in F i g . 13.38. T h i s circuit causes a current e q u a l t o \v \/R A
t o flow t h r o u g h t h e m o v i n g - c o i l m e t e r M . T h u s t h e m e t e r provides
value. B e y o n d t h e positive peak, the o p a m p will see a negative voltage b e t w e e n its input Except for p o s s i b l e discharge through t h e load resistance, t h e capacitor will retain a voltage equal to t h e p o s i t i v e p e a k of t h e input. Inclusion of a load resistance is essential if the circuit is required t o d e t e c t reductions in the m a g n i t u d e of the positive peak.
13.9.7 A Buffered Precision Peak Detector W h e n t h e p e a k d e t e c t o r is r e q u i r e d to h o l d t h e v a l u e of t h e p e a k for a l o n g t i m e , t h e c a p a c i tor should b e buffered, as s h o w n in t h e circuit of F i g . 13.40. H e r e o p a m p A , w h i c h s h o u l d 2
have h i g h i n p u t i m p e d a n c e a n d l o w input bias current, is c o n n e c t e d as a voltage follower. The r e m a i n d e r of t h e circuit is quite similar t o t h e half-wave-rectifier circuit of F i g . 13.34.
"Superdiode" + v
i
FIGURE 1 3 . 3 8 an ac voltmeter.
j I I
Cn
—
?
Use of the diode bridge in the design of FIGURE 1 3 . 3 9 A precision peak rectifier obtained by placing the diode in the feedback loop of an op amp.
1214
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
CIRCUITS
SPICE S I M U L A T I O N
13.10
EXAMPLES
R A/W
WIEN-BRIDGE OSCILLATOR For our first example, wc shall simulate the operation of the Wien-bridge oscillator whose Capture schematic is shown in Fig. 13.42. The component values are selected to yield oscillations at 1 kHz. W e would like to investigate the operation of the circuit for different settings ofRy, and R , with R + R = 50 k Q . Since oscillation just starts when (R + R )/R = 2 (see Exercise 13.4), that is, when R = 20 k Q and R = 30 k Q , w e consider three possible settings: (a) R =l5 kQ, R = 35 k Q ; (b) R =U k Q , R = 32 k Q ; and (c) R = 25 k Q , R = 25 k Q . These settings correspond to loop gains of 1.33,1.1, and 0.8, respectively. lb
la
lb
2
la
la
lb
lb
FIGUREI 3.40
lb
la
la
lb
la
lb
In PSpice, a 741-type op amp and lN4148-type diodes are used to simulate the circuit in Fig. 13.42. A transient-analysis simulation is performed with the capacitor voltages initially set to zero. This demonstrates that the op-amp offset voltage is sufficient to cause the oscillations to start without the need for special start-up circuitry. Figure 13.43 shows the simulation results.
A buffered precision peak rectifier.
OOUT
FIGURE 13.41
PARAMETERS: C3 = 16n C4 = 16n
A precision clamping circuit.
W h i l e d i o d e D is the essential d i o d e for the peak-rectification operation, d i o d e D acts as a catching d i o d e to p r e v e n t negative saturation, and t h e associated delays, of o p a m p A . D u r i n g the h o l d i n g state, follower A supplies D w i t h a small current t h r o u g h R. T h e output of o p a m p A j will t h e n b e c l a m p e d at o n e d i o d e d r o p b e l o w t h e input voltage. N o w if the input v, increases above the value stored on C, w h i c h is equal to the output voltage v , o p amp Aj sees a net positive input that drives its output t o w a r d t h e positive saturation level, turning off d i o d e D . D i o d e D is t h e n turned o n and capacitor C is c h a r g e d to the n e w positive p e a k of t h e input, after w h i c h t i m e t h e circuit returns to the h o l d i n g state. Finally, note that this circuit has a l o w - i m p e d a n c e output. {
Ria Rlb R2 R3
2
x
2
2
0
2
= = = =
18K {50K-{Rla} 10K 10K
R4 = 10K D1N4148
VCC = 15 VEE = - 1 5
x
OS2 VCC A
VEE
A
-OA
13.9.8 A Precision Clamping Circuit OS1
B y r e p l a c i n g t h e d i o d e in t h e c l a m p i n g circuit studied in C h a p t e r 3 w i t h a " s u p e r d i o d e , " uA741
t h e p r e c i s i o n c l a m p of F i g . 13.41 is o b t a i n e d . O p e r a t i o n of this circuit s h o u l d b e selfexplanatory.
{VCC}.
VEE
{VEE}.
{C4}
13.10 SPICE SIMULATION EXAMPLES
IC = 0 {C3}:
T h e circuits studied in this chapter m a k e u s e of t h e nonlinear operation of devices to perform a variety of tasks, such as the stabilization of the amplitude of a sine-wave oscillator and the shaping of a triangular w a v e f o r m into a sinusoid. A l t h o u g h w e h a v e b e e n able to devise simplified m e t h o d s for the analysis and design of these circuits, a complete pencil-and-paper analysis is nearly impossible. T h e designer m u s t therefore rely on c o m p u t e r simulation to obtain greater insight into detailed circuit operation, to e x p e r i m e n t with different c o m p o n e n t values, and to optimize the design. In this section, w e present t w o e x a m p l e s that illustrate the u s e of S P I C E in the simulation of oscillator circuits.
{R4}
;{R3}
IC = 0
FIGURE 1 3 . 4 2
Example 13.1: Capture schematic of a Wien-bridge oscillator.
The SPICE models for the 741 op amp and the 1N4148 diode are available in PSpice. The 741 op amp was characterized in Example 2.9. The 1N4148 diode was used in Example 3.10.
13.10
L GENERATORS A N D W A V E F O R M - S H A P I N G CIRCUITS 1216
$1^
CHAPTER 1 3
SPICE SIMULATION EXAMPLES
SIGNA
1
The graph in Fig. 13.43(a) shows the output waveform obtained for a loop gain of 1.33. Observe that although the oscillations grow and stabilize rapidly, the distortion is considerable. The output obtained for a loop gain of 1.1, shown in Fig. 13.43(b), is much less distorted. However, as expected, as the loop gain is reduced toward unity, it takes longer for the oscillations to build up and for the amplitude to stabilize. For this case, the frequency is 986.6 Hz, which is reasonably j close to the design value of 1 kHz, and the amplitude is 7.37 V. Finally, for a loop gain of 0.8, the j output shown in Fig. 13.43(c) confirms our expectation that sustained oscillations cannot be obtained when the loop gain is less than unity. j PSpice can be used to investigate the spectral purity of the output sine wave. This is achieved using the Fourier analysis facility. It is found that in the steady state the output for the case of a loop gain of 1.1 has a T H D figure of 1.88%. When the oscillator output is taken at the op-amp output (voltage v ), a T H D of 2.57% is obtained, which as expected is higher than that for the voltage
15V 10V
OV
I
-10V -15V 0 • V(OUT)
A
20
15
10
;
Time (ms) (a) R
n o t
W UT) b u t by very much. The output terminal of the op amp is of course a much more convenient place to take the output. 0
= 15kft, Loop Gain = 1.33
l a
i
ACTIVE-FILTER-TUNED OSCILLATOR In this example, w e use PSpice to verify our contention that a superior op amp-oscillator can be realized using the active-filter-tuned circuit of Fig. 13.11. W e also investigate the effect of changing the value of the filter Q factor on the spectral purity of the output sine wave. Consider the circuit whose Capture schematic is shown in Fig. 13.44. For this circuit, the center frequency is 1 kHz, and the filter Q is 5 when R = 50 k Q and 20 when R = 200 k Q . As in the case of the Wien-bridge circuit in Example 13.1, 741-type op amps and lN4148-type diodes are utilized. In PSpice a transient-analysis simulation is performed with the capacitor voltages initially set to zero. To be able to compute the Fourier components of the output, the analysis interval chosen must be long enough to allow the oscillator to reach a steady state. The time to reach a steady state is in turn determined by the value of the filter Q; the higher the Q, the longer it takes the output to settle. For Q = 5, it was determined, through a combination of approximate calculations and experimenta tion using PSpice, that 50 m s is a reasonable estimate for the analysis interval. For plotting purposes, w e use 200 points per period of oscillation. {
1.0V
0 • V(OUT)
10
5
15
Time (ms) (b) R
l a
= 18kii, Loop Gain = 1 . 1
5.0mV
x
T h e results of the transient analysis are plotted in Fig. 13.45. T h e upper graph shows the sinusoidal w a v e f o r m at the output of op a m p Aj (voltage v ). T h e l o w e r graph shows the waveform across the d i o d e limiter (voltage v ). T h e frequency of oscillation is found to be very close to the design value of 1 k H z . T h e amplitude of the sine w a v e is determined using Probe (the graphical interface of PSpice) to be 1.15 V (or 2.3 V p - p ) . N o t e that this is l o w e r than the 3.6 V estimated in Exercise 13.7. T h e latter value, h o w e v e r , was based on an estimate of 0.7-V drop across each conducting diode in the limiter. T h e lower waveform in Fig. 13.45 indicates that the diode drop is closer to 0.5 V, for a 1-V peak-to-peak amplitude of the p s e u d o - s q u a r e Wave. W e should therefore-esxpect the peak-to-peak amplitude of the output sinusoid to be lower than 3.6 V b y the same factor, and indeed it is approximately the case. }
2
2.5mV
OV-
-2.5mV-. 0 • V(OUT)
, 5
1 0
1 5
Time (ms) (c) R
l a
= 25kiî, Loop Gain = 0.8
FIGURE 1 3 . 4 3 Start-up transient behavior of the Wien-bridge oscillator shown in Fig. 13.42 for various values of loop gain.
In PSpice, the Fourier analysis of the output sine w a v e indicates that T H D = 1.61%. Repeating the simulation with Q increased to 20 (by increasing R^ to 200 k Q ) , we find that the value of T H D is reduced to 1.01%. Thus, our expectations that the value of the filter Q can be used as an effective means for constrolling the T H D of the output waveform are confirmed.
1217
SUMMARY
1 2 1 9
2.0V
W V
||l
as 6»
3
o Ol
Time (ms) FIGURE 1 3 . 4 5 Output waveforms of the active-filter-tuned oscillator shown in Fig. 13.44 for Q = 5 (7q = 50kQ). o •a
SUMMARY •
• W W • > w
H W
<
0 o o o © II h
II II M m
II
o
II II m o &
01 Pi & & &
I t
> 2
T
u u >
w w >
u u • >
A linear oscillator can be realized by placing a frequencyselective network in the feedback path of an amplifier (an op amp or a transistor). The circuit will oscillate at the frequency at which the total phase shift around the loop is zero, provided that the magnitude of loop gain at this frequency is equal to, or greater than, unity.
H
If in an oscillator the magnitude of loop gain is greater than unity, the amplitude will increase until a nonlinear amplitude-control mechanism is activated.
•
The Wien-bridge oscillator, the phase-shift oscillator, the quadrature oscillator, and the active-filter-tuned oscillator are popular configurations for frequencies up to about 1 MHz. These circuits employ RC networks together with op amps or transistors. For higher frequencies, LC-tuned or crystal-tuned oscillators are utilized. A popular configura tion is the Colpitts circuit.
1' s u u >
There are two distinctly different types of signal genera tor: linear oscillators, which utilize some form of reso nance, and nonlinear oscillators or function generators, which employ a switching mechanism implemented with a multivibrator circuit.
•
Crystal oscillators provide the highest possible frequency accuracy and stability.
E
There are three types of multivibrator: bistable, monostable, and astable. Op-amp circuit implementa tions of multivibrators are useful in analog-circuit appli cations that require high precision. Implementations using digital logic gates are studied in Chapter 11.
•
The bistable multivibrator has two stable states and can remain in either state indefinitely. It changes state when triggered. A comparator with hysteresis is bistable.
•
A monostable multivibrator, also known as a one-shot multivibrator, has one stable state, in which it can remain indefinitely. When triggered, it goes into a quasistable state in which it remains for a predetermined interval, thus generating, at its output, a pulse of known width.
•
An astable multivibrator has no stable state. It oscillates between two quasi-stable states, remaining in each for a predetermined interval. It thus generates a periodic wave form at the output.
:
1 2 1 8
1220
||g|
CHAPTER 13
SIGNAL G E N E R A T O R S AN
9
A feedback loop consisting of an integrator and a bistable multivibrator can be used to generate triangular and square waveforms.
•
The 555 timer, a commercially available IC, can be used with external resistors and a capacitor to implement highquality monostable and astable multivibrators.
•
WAVEFORM-SHAPING CIRCUITS
PROBLEMS
1221
can be implemented either by using diodes (or transistors) and resistors, or by using an amplifier having a nonlinear transfer characteristic that approximates the sine function. •
A sine waveform can be generated by feeding a triangular waveform to a sine-wave shaper. A sine-wave shaper
Diodes can be combined with op amps to implement precision rectifier circuits in which negative feedback serves to mask the nonidealities of the diode characteristics.
(a)
PROBLEMS
(b)
FIGURE P 1 3 . 8
transconductance G frequency?
SECTION 1 3 . 1 : BASIC PRINCIPLES OF
m
SINUSOIDAL OSCILLATORS * 1 3 . 1 Consider a sinusoidal oscillator consisting of an amplifier having a frequency-independent gain A (where A is positive) and a second-order bandpass filter with a pole frequency ft)b, a pole Q denoted Q, and a center-frequency gain K. (a) Find the frequency of oscillation, and the condition that A and K must satisfy for sustained oscillation. (b) Derive an expression for dQ/dco, evaluated at CO = Oh. (c) Use the result of (b) to find an expression for the per-unit change in frequency of oscillation resulting from a phaseangle change of A(j>, in the amplifier transfer function. Hint: - f (tan-'y) = ax i + ax 1 3 . 2 For the oscillator described in Problem 13.1, show that, independent of the value of A and K, the poles of the circuit lie at a radial distance of Oh. Find the value of AK that results in poles appearing (a) on the jco axis, and (b) in the right-half of the s plane, at a horizontal distance from the j o axis of co /(2Q). z
v
0
will the circuit oscillate? At what a
1 3 . 5 In a particular oscillator characterized by the structure of Fig. 13.1, the frequency-selective network exhibits a loss of 20 dB and a phase shift of 180° at Oh. What is the minimum gain and the phase shift that the amplifier must have, for oscillation to begin? D 1 3 . 6 Consider the circuit of Fig. 13.3(a) with R removed to realize the comparator function. Find suitable values for all resistors so that the comparator output levels are ±6 V and the slope of the Umiting characteristic is 0.1. Use power supply voltages of ±10 V and assume the voltage drop of a conducting diode to be 0.7 V. f
D 1 3 . 7 Consider the circuit of Fig. 13.3(a) with /^removed to realize the comparator function. Sketch the transfer characteristic. Show that by connecting a dc source V to the virtual ground of the op amp through a resistor R , the transfer characteristic is shifted along the v, axis to the point = ~(R /R )V . Utilizing available +15-V dc supplies for ± 7 and for V , find suitable component values so that the limiting levels are +5 V and the comparator threshold is at v = +5 V. Neglect the diode voltage drop (i.e., assume that V = 0). The input resistance of the comparator is to be 100 kQ, and the slope in the limiting regions is to be <0.05 V/V. Use standard 5% resistors (see Appendix G). . B
B
V l
X
B
B
0
1 3 . 1 4 Repeat Problem 13.13 for the circuit in Fig. P13.14.
1 3 . 1 0 For the Wien-bridge oscillator of Fig. 13.4. let the closed-loop amplifier (formed by the op amp and the resistors R and R ) exhibit a phase shift of - 0 . 1 rad in the neighborhood of co= 1/CR. Find the frequency at which oscillations can occur in this case, in terms of CR. (Hint: Use Eq. 13.11.) x
2
1 3 . 1 1 For the Wien-bridge oscillator of Fig. 13.4, use the expression for loop gain in Eq. (13.10) to find the poles of the closed-loop system. Give the expression for the pole Q, and use it to show that to locate the poles in the right half of the j plane, R /R must be selected to be greater than 2. 2
x
FIGURE P 1 3 . 1 4
0 * 1 3 . 1 2 Reconsider Exercise 13.3 with /?, and R increased to reduce the output voltage. What values are required for a peak-to-peak output of 10 V? What results if R and R are open-circuited? 6
3
6
1 3 . 1 3 For the circuit in Fig. P13.13 find L(s), L(jco), the frequency for zero loop phase, and R /R for oscillation. 2
x
* 1 3 . 1 5 Consider the circuit of Fig. 13.6 with the 50-kQ potentiometer replaced by two fixed resistors: 10 kQ between the op amp's negative input and ground, and 18 kQ. Modeling each diode as a 0.65-V battery in series with a 100-Q resistance, find the peak-to-peak amplitude of the output sinusoid.
D
0 * * 1 3 . 1 6 Redesign the circuit of Fig. 13.6 for operation at 10 kHz using the same values of resistance. If at 10 kHz the op amp provides an excess phase shift (lag) of 5.7°, what will be the frequency of oscillation? (Assume that the phase shift introduced by the op amp remains constant for frequencies around 10 kHz.) To restore operation to 10 kHz, what change must be made in the shunt resistor of the Wien bridge? Also, to what value must R /R be changed?
1 3 . 8 Denoting the zener voltages of Z and Z by V and and assuming that in the forward direction the voltage drop is approximately 0.7 V, sketch and clearly label the transfer characteristics v -v of the circuits in Fig. P13.8. Assume the op amps to be ideal. t
0
1 3 . 4 An oscillator is formed by loading a transconductance amplifier having, a positive gain with a parallel RLC circuit and connecting the output directly to the input (thus applying positive feedback with a factor ¡5=1). Let the transconductance amplifier have an input resistance of 10 kQ and an output resistance of 10 kQ. The LC resonator has L = 10 LiU, C = 1000 pF, and Q = 100. For what value of
0
B
t
D l 3 . 3 Sketch a circuit for a sinusoidal oscillator formed by an op amp connected in the noninverting configuration and a bandpass filter implemented by an RLC resonator (such as that in Fig. 12.18d). What should the amplifier gain be to obtain sustained oscillation? What is the frequency of oscillation? Find the percentage change in co , resulting from a change of + 1 % in the value of (a) L, (b) C, and (c) R.
[V (s)/V (s)] is that of a bandpass filter. Find C0n and Q of the poles, and find the center-frequency gain.
SECTION 1 3 . 2 :
2
zl
I
2
0 P - A M P - R C OSCILLATOR
CIRCUITS 1 3 . 9 For the Wien-bridge oscillator circuit in Fig. 13.4, show that the transfer function of the feedback network
FIGURE P 1 3 . 1 3
x
* 1 3.1 7 For the circuit of Fig. 13.8, connect an additional R = 10 k Q resistor in series with the rightmost capacitor C. For this modification (and ignoring the amplitude stabilization circuitry) find the loop gain AB by breaking the circuit at node X. Find A^for oscillation to begin, and f i n d / . 0
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
CIRCUITS PROBLEMS
t
. I
1 2 2 3
C-,
D 1 3 . 1 8 For the circuit in Fig. P13.18. break the loop at node X and find the loop gain (working backward for simplicity 10 kQ, find C and R to to find V in terms of V ). For R obtain sinusoidal oscillations at 10 kHz x
f
* 1 3 . 2 0 Assuming that the diode-clipped waveform in Exercise 13.7 is nearly an ideal square wave and that the resonator Q is 20, provide an estimate of the distortion in the output sine wave by calculating the magnitude (relative to the fundamental) of the second harmonic the third harmonic the fifth harmonic the rms of harmonics to the tenth
1
+ — W W
f
0
* 1 3 . 1 9 Consider the quadrature-oscillator circuit of Fig. 13.9 without the limiter. Let the resistance R be equal to 2R/(1 + A), where A < 1. Show that the poles of the characteristic equation are in the right-half j plane and given by' s = (l/C7?)[(A/4)±;'].
(a) (b) (c) (d)
Note that a square wave of amplitude V and frequency to is represented by the series 4V7
1 cos cot - -cosltot 3
SECTION 1 3 . 3 :
1 +, -cos5cot 5
1 - -cos! 7
C
\RL
R,
(Assume R > co L) f
LC AND CRYSTAL OSCILLATORS
* * 1 3 . 2 1 Figure P13.2Lshows four oscillator circuits of the Colpitts type, complete with bias detail. For each circuit, derive an equation governing circuit operation, and find the frequency of oscillation and the gain condition that ensures that oscillations start. **13.22
£
2
cot + • •
Consider the oscillator circuit in Fig. P13.22, and
(c)
(d)
FIGURE P I 3 . 2 1 (Continued)
(b) If R is selected equal to (1/7) kQ, where 7 is in milliamperes, convince yourself that oscillations will start. If oscillations grow to the point that V is large enough to turn the BJTs on and off, show that the voltage at the collector of Q will be a square wave of 1 V peak to peak. Estimate the peak-to-peak amplitude of the output sine wave V . c
a
assume for simplicity that ¡5= <*>. (a) Find the frequency of oscillation and the minimum
2
0
value of R
c
0
(in terms of the bias current 7) for oscillation
1 3 . 2 3 Consider the Pierce crystal oscillator of Fig. 13.16 with the crystal as specified in Exercise 13.10. Let C be variable in the range 1 pF to 10 pF, and let C be fixed at 10 pF. Find the range over which the oscillation frequency can be tuned. (Hint: Use the result in the statement leading to the expression in Eq. 13.27.) x
2
to start. SECTION 1 3 . 4 :
BISTABLE MULTIVIBRATORS
1 3 . 2 4 Consider the bistable circuit of Fig. 13.19(a) with the op amp's positive-input terminal connected to a positivevoltage source V through a resistor i? . 3
(a) Derive expressions for the threshold voltages V and V in terms of the op amp's saturation levels L and L_, R R , R , and V. (b) Let L = -7__ = 13 V, V = 15 V, and 7?, = 10 k Q . Find the values of R and R that result in V = +4.9 V and F = +5.1V. TL
m
+
u
2
3
+
2
3
TL
r a
1 3 . 2 5 Consider the bistable circuit of Fig. 13.20(a) with the op amp's negative-input terminal disconnected from ground and connected to a reference voltage V . R
(a) Derive expressions for the threshold voltages V and V in terms of the op amp's saturation levels L and L_, R , R , and V . (b) Let L = -L_=V and R = 10 k Q . Find R and V that result in threshold voltages of 0 and V710. TL
+
(a)
(b)
R
+
FIGURE P I 3.21
TH
x
FIGURE P 1 3 . 2 2
x
2
R
2
CHAPTER 1 3
1 2 2 4
SIGNAL GENERATORS A N D WAVEFORM-SHAPING
1 3 . 2 6 For the circuit in Fig. P13.26, sketch and label the transfer characteristic v -w . The diodes are assumed to have a constant 0.7-V drop when conducting, and the op amp saturates at ±12 V. What is the maximum diode current? 0
7
R - 60 kfl VW
1 3 . 2 7 Consider the circuit of Fig. nated and R short-circuited. Sketch characteristic v -vj. Assume that the 0.7-V drop when conducting and that ±12 V. 2
0
P13.26 with R elimiand label the transfer diodes have a constant the op amp saturates at x
* 1 3 . 2 8 Consider a bistable circuit having a noninverting transfer characteristic with L = -L_ = 12 V, V = - 1 V, and V = +1 V. +
TL
TH
(a) For a 0.5-V-amplitude sine-wave input having zero average, what is the output? (b) Describe the output if a sinusoid of frequency / and amplitude of 1.1 V is applied at the input. By how much can the average of this sinusoidal input shift before the output becomes a constant value? D 1 3 . 2 9 Design the circuit of Fig. 13.23(a) to realize a transfer characteristic with +7.5-V output levels and ±7.5-V
wave at the output of the bistable multivibrator of 15-V peakto-peak amplitude and 10-KHz frequency. Sketch and label the waveform at the integrator output. Assuming ±13-V op-amp saturation levels, design for a minimum zener current of 1 mA. Specify the zener voltage required, and give the values of all resistors.
GENERATION OF SQUARE AND
TRIANGULAR WAVEFORMS USING ASTABLE
SECTION 1 3 . 6 :
MULTIVIBRATORS
STANDARDIZED PULSE—THE
1 3 . 3 0 Find the frequency of oscillation of the circuit in Fig. 13.24(b) for the case R = 10 Ml, R = 16 kfl, C = 10 nF, andfl = 62k£2.
M0N0STABLE MULTIVIBRATOR
t
FIGURE P I 3.26
PROBLEMS
threshold values. Design so that when »/ = 0 V a current of 0.1 mA flows in the feedback resistor and a current of 1 mA flows through the zener diodes. Assume that the output saturation levels of the op amp are ±12 V. Specify the voltages of the zener diodes and give the values of all resistors. SECTION 1 3 . 5 :
2
CIRCUITS
2
D 1 3 . 3 1 Augment the astable multivibrator circuit of Fig. 13.24(b) with an output limiter of the type shown in Fig. 13.23(b). Design the. circuit to obtain an output square wave with 5-V amplitude and 1-kHz frequency using a 10-nF capacitor C. Use ¡5 = 0.462, and design for a current in the resistive divider approximately equal to the average current in the RC network over a half-cycle. Assuming±13-V op-amp saturation voltages, arrange for the zener to operate at a current of 1 mA.
GENERATION OF A
+
A
B
ref
ref
x
0
x
A
T = CR In
L -L_ +
V„
cc
TH
cc
1 3 . 3 8 (a) Using a 1-nF capacitor C in the circuit of Fig. 13.28(a), find the value of R that results in an output pulse of 10-jUs duration. (b) If the 555 timer used in (a) is powered with V = 15 V, and assuming that V can be varied externally (i.e., it need not remain equal to | V ), find its required value so that the pulse width is increased to 20 pis, with other conditions the same as in (a). cc
D 1 3 . 3 9 Using a 680-pF capacitor, design the astable circuit of Fig. 13.29(a) to obtain a square wave with a 50-kHz frequency and a 75% duty cycle. Specify the values oíR and AV * 1 3 . 4 0 The node in the 555 timer at which the voltage is V (i.e., the inverting input terminal of comparator 1) is usually connected to an external terminal. This allows the user to change V externally (i.e., V no longer remains at | V ). Note, however, that whatever the value of V becomes, V always remains \V . TH
f
Note that this circuit has the interesting property that the pulse width can be controlled by changing y .
m
TH
cc
TH
TL
TH
Ci
(a) For the astable circuit of Fig. 13.29, rederive the expressions for T and T , expressing them in terms of V and V . (b) For the case C = 1 nF, R = 7.2 kQ, R = 3.6 kQ, and Vcc - 5 V, find the frequency of oscillation and the duty cycle of the resulting square wave when no external voltage is applied to the terminal V . (c) For the design in (b), let a sine-wave signal of a much lower frequency than that found in (b) and of 1-V peak amplitude be capacitively coupled to the circuit node V . This signal will cause V to change around its quiescent value of I V , and thus T will change correspondingly—a modulation process. Find T , and find the frequency of oscillation and the duty cycle at the two extreme values of V . H
Trigger o
|j-
L
TH
A
o
v
0
TL
B
TH
TH
m
cc
7
H
H
FIGURE P I 3.34
TH
A4 1 3 . 3 5 For the monostable circuit considered in Exercise 13.19, calculate the recovery time. D * 1 3 . 3 6 Using the circuit of Fig. 13.26, with a nearly ideal op amp for which the saturation levels are ±13 V, design a monostable multivibrator to provide & negative output pulse of 100-jUs duration. Use capacitors of 0.1 nF and 1 nF. Wherever possible, choose resistors of 100 kQ in your design. Diodes have a drop of 0.7 V. What is the minimum input step size that will ensure triggering? How long does the circuit take to recover to a state in which retriggering is possible with a normal output? SECTION 1 3 . 7 : FIGURE P 1 3 . 3 3
TL
cc
A
D*1 3 . 3 3 The circuit of Fig. PI 3.33 consists of an inverting bistable multivibrator with an output limiter and a noninverting integrator. Using equal values for all resistors except R and a 0.5-nF capacitor, design the circuit to obtain a square
AAAr
0
cc
ref
D 1 3 . 3 2 Using the scheme of Fig. 13.25, design a circuit that provides square waves of 10 V peak to peak and triangular waves of 10 V peak to peak. The frequency is to be 1 kHz. Implement the bistable circuit with the circuit of Fig. 13.23(b). Use a 0.01-tfF capacitor, and specify the values of all resistors and the required zener voltage. Design for a minimum zener current of 1 mA and for a maximum current in the resistive divider of 0.2 mA. Assume that the output saturation levels of the op amps are ±13 V.
and connected to an input voltage v,. Verify that the transfer characteristic v -v, is that of an inverting bistable circuit with thresholds V = | V and V = \ V and output levels of 0 and V .
TH
* 1 3 . 3 4 Figure PI3.34 shows a monostable multivibrator circuit. In the stable state, v = L , v = 0, and v = - V . The circuit can be triggered by applying a positive input pulse of height greater than V . For normal operation, C R < CR. Show the resulting waveforms of v and v . Also, show that the pulse generated at the output will have a width T given by 0
1 2 2 5
INTEGRATED-CIRCUIT TIMERS
1 3 . 3 7 Consider the 555 circuit of Fig. 13.27 when the Threshold and the Trigger input terminals are joined together
SECTION 1 3 . 8 :
NONLINEAR WAVEFORM-
SHAPING CIRCUITS 0 * 1 3 . 4 1 The two-diode circuit shown in Fig. P13.41 can provide a crude approximation to a sine-wave output when driven by a triangular waveform. To obtain a good approximation, we select the peak of,the triangular waveform, V, so that the slope of the desired sine wave at the zero crossings is equal to that of the triangular wave. Also, the value of R is selected so that when v, is at its peak the output voltage is equal to the desired peak of the sine wave. If the diodes exhibit a voltage drop of 0.7 V at 1-mA current, changing at the rate of 0.1 V per decade, find the values of V and R that will yield an approximation to a sine waveform of 0.7-V peak amplitude. Then find the angles 0 (where 6 = 90° when v, is at its peak) at which the output of the circuit, in volts, is 0.7, 0.65, 0.6, 0.55, 0.5, 0.4, 0.3, 0.2, 0.1, and 0. Use the angle
CHAPTER 13
1 2 2 6
SIGNAL GENERATORS A N D W A V E F O R M - S H A P I N G CIRCUITS
values obtained to determine the values of the exact sine wave (i.e., 0.7 sin 0), and thus find the percentage error of this circuit as a sine shaper. Provide your results in tabular form. R
PROBLEMS
thermal voltage. Since the output voltage i s proportional to the logarithm of the input voltage, the circuit is known as a logarithmic amplifier. Such amplifiers find application in situations where it is desired to compress the signal range.
1 2 2 7
* * 1 3 . 4 5 Detailed analysis of the circuit in Fig. 13.32 shows that optimum performance (as a sine shaper) occurs when the values of I and R are selected so that RI = 2.5V , where V is the thermal voltage, and the peak ampli tude of the input triangular wave is 6.6V . If the output is taken across R (i.e., between the two emitters), find v, corre sponding to v = 0.25V , 0.5V , V , 1.5V , 2V , 2.4V , and 2.42 V . Plot v -v and compare to the ideal curve given T
T
T
0
T
T
0
T
T
T
T
T
r
by
V[ o
ov
0
FIGURE P I 3.41
= 2.42 V
T
D 1 3 . 4 2 Design a two-segment sine-wave shaper using a 10-kQ input resistor, two diodes, and two clamping voltages. The circuit, fed by a 10-V peak-to-peak triangular wave, should limit the amplitude of the output signal via a 0.7-V diode to a value corresponding to that of a sine wave whose zero-crossing slope matches that of the triangle. What are the clamping voltages you have chosen? 1 3 . 4 3 Show that the output voltage of the circuit in Fig. P13.43 is given by v = -nV \n[jLj 0
T
o
Vl>
where 7 and n are the diode parameters and V S
T
is the
sin
6.6 W
x90<
FIGURE P I 3.43
SECTION 1 3 . 9 : CIRCUITS
1 3 . 4 4 Verify that the circuit in Fig. P13.44 implements the transfer characteristic v = v v for v v > 0. Such a circuit is known as an analog multiplier. Check the circuit's perfor mance for various combinations of input voltage of values, say, 0.5 V, 1 V, 2 V, and 3 V. Assume all diodes to be iden tical, with 700-mV drop at 1-mA current and n = 2. Note that a squarer can easily be produced using a single input (e.g., v{) connected via a 0.5-kQ resistor (rather than the 1-kfl resistor shown).
1 3 . 4 6 Two superdiode circuits connected to a commonload resistor and having the same input signal have their diodes reversed, one with cathode to the load, the other with anode to the load. For a sine-wave input of 10 V peak to peak, what is the output waveform? Note that each halfcycle of the load current is provided by a separate amplifier, and that while one amplifier supplies the load current, the other amplifier idles. This idea, called class-B operation (see Chapter 14), is important in the implementation of power amplifiers.
0
x
2
lt
2
PRECISION RECTIFIER FIGURE P I 3 . 5 0
0 1 3 . 4 7 The superdiode circuit of Fig. 13.33(a) can be made to have gain by connecting a resistor R in place of the short circuit between the cathode of the diode and the negativeinput terminal of the op amp, and a resistor R between the negative-input terminal and ground. Design the circuit for a gain of 2. For a 10-V peak-to-peak input sine wave, what is the average output voltage resulting?
1 3 . 5 1 Plot the transfer characteristics v -v, the circuit in Fig. PI3.51. R
v
x
O V
Q
~ R —VSA,
-A
\
R
A vA V — J
0
FIGURE P 1 3 . 5 1
1 3 . 5 2 Sketch the transfer characteristics of the circuit in Fig. P13.52. 10 kfl W V
2
0 * 1 3 . 4 9 Provide a design for a voltmeter circuit similar to the one in Fig. 13.35, which is intended to function at fre quencies of 10 Hz and above. It should be calibrated for sine-wave input signals to provide ah output of+10 V for an input of 1 V rms. The input resistance should be as high as possible. To extend the bandwidth of operation, keep the gain in the ac part of the circuit reasonably small. As well, the design should result in reduction of the size of the capacitor C required. The largest value of resistor available is 1 MQ. 1 3 . 5 0 Plot the transfer characteristic of the circuit in Fig. P13.50.
L1
W V — j ^
1-
V2
1
FIGURE P 1 3 . 4 4
of
•VC—WV
0 1 3 . 4 8 Provide a design of the inverting precision rectifier shown in Fig. 13.34(a) in which the gain is - 2 for negative inputs and zero otherwise, and the input resistance is 100 kQ. What values of R and R do you Choose? x
m
R
01
A/W
2
0i
and v -vi
m
FIGURE P I 3.52
:
CHAPTER 13
SIGNAL GENERATORS A N D WAVEFORM-SHAPING CIRCUITS
1 228
D1 3 . 5 3 A circuit related to that in Fig. 13.38 is to be used to provide a current proportional to v (v > 0 ) to a light-emitting diode (LED). The value of the current is to be independent of the diode's nonlinearities and variability. Indicate how this may be done easily. A
calculated?
A
* 1 3 . 5 4 In the precision rectifier of Fig. 13.38, the resistor R is replaced by a capacitor C. What happens? For equiva lent performance with a sine-wave input of 60-Hz fre quency with R = 1 k Q , what value of C should be used? What is the response of the modified circuit at 120 Hz? At 180 Hz? If the amplitude of v is kept fixed, what new func tion does this circuit perform? Now consider the effect of a waveform change on both circuits (the one with R and the one with C). For a triangular-wave input of 60-Hz fre quency that produces an average meter current of 1 mA in the circuit with R, what does the average meter current A
become when R is replaced with the C whose value was just
* 1 3 . 5 5 A positive-peak rectifier utilizing a fast op amp and a junction diode in a superdiode configuration, and a 10-/xF capacitor initially uncharged, is driven by a series of 10-V pulses of W-ps duration. If the maximum output current that the op amp can supply is 10 mA, what is the voltage on the capacitor following one pulse? Two pulses? Ten pulses? How many pulses are required to reach 0.5 V? 1.0 V? 2.0 V? D 1 3 . 5 6 Consider the buffered precision peak rectifier shown in Fig. 13.40 when connected to a triangular input of 1-V peak-to-peak amplitude and 1000-Hz frequency. It uti lizes an op amp whose bias current (directed into A ) is 10 nA and diodes whose reverse leakage current is 1 nA. What is the smallest capacitor that can be used to guarantee an output ripple less than 1%? 2
Output Stages and Power Amplifiers Introduction 14.1
1229
Classification of Stages
14.7
Variations o n the C l a s s Configuration
Output
1230
14.8
IC Power Amplifiers
14.2
Class A Output
Stage
1231
14.9
M O S P o w e r Transistors
14.3
Class B Output
Stage
1235
14.10
SPICE
14.4
Class A B Output
Stage
14.5
Biasing the Class
AB
Circuit 14.6
1244
P o w e r BJTs
1241
AB
1256 1261 1266
Simulation
Example
1271
Summary
1276
Problems
1277
1249
INTRODUCTION A n important function of t h e output stage is to p r o v i d e the amplifier w i t h a l o w output resis tance so that it c a n deliver t h e output signal to the load w i t h o u t loss of gain. Since the o u t p u t stage is t h e final stage of the amplifier, it usually deals w i t h relatively large signals. T h u s t h e small-signal a p p r o x i m a t i o n s and m o d e l s either are n o t a p p l i c a b l e or m u s t b e u s e d w i t h c a r e . Nevertheless, linearity r e m a i n s a very i m p o r t a n t r e q u i r e m e n t . In fact, a m e a s u r e of g o o d n e s s of the design of t h e o u t p u t stage is t h e total h a r m o n i c d i s t o r t i o n ( T H D ) it introduces. T h i s is the r m s value of the h a r m o n i c c o m p o n e n t s of the output signal, excluding the fundamental, expressed as a percentage of the r m s of the fundamental. A high-fidelity audio p o w e r amplifier features a T H D of t h e order of a fraction of a percent. T h e m o s t c h a l l e n g i n g r e q u i r e m e n t in t h e design of the o u t p u t stage is that it deliver the required a m o u n t of p o w e r to the l o a d in an efficient m a n n e r . T h i s i m p l i e s that t h e p o w e r dis sipated in t h e output-stage transistors m u s t b e as l o w as p o s s i b l e . T h i s r e q u i r e m e n t s t e m s mainly from t h e fact that t h e p o w e r dissipated in a transistor raises its internal j u n c t i o n t e m p e r a t u r e , a n d there is a m a x i m u m t e m p e r a t u r e (in the r a n g e o f 1 5 0 ° C to 2 0 0 ° C for silicon
CHAPTER 14
O U T P U T STAGES A N D P O W E R A M P L I F I E R S
14.2
CLASS A O U T P U T STAGE
f "'X'
~
14.1 CLASSIFICATION OF OUTPUT STAGES Output stages are classified according to t h e collector current w a v e f o r m that results w h e n an input signal is applied. F i g u r e 14.1 illustrates t h e classification for the case of a sinusoidal input signal. T h e class A stage, w h o s e asspciated w a v e f o r m is s h o w n in Fig. 14.1(a), is biased at a current I greater than the amplitude of the signal current, I . T h u s the transistor in a class A stage conducts for the entire cycle of the input signal; that is, the conduction angle is 3 6 0 ° . In contrast, the class B stage, w h o s e associated waveform is s h o w n in Fig. 14.1(b), is biased at zero dc current. T h u s a transistor in a class B stage c o n d u c t s for only half the cycle of the input sine w a v e , resulting in a c o n d u c t i o n angle of 180°. A s will b e seen later, t h e n e g a t i v e h a l v e s of the sinusoid will b e supplied b y another transistor that also operates in t h e class B m o d e and conducts during t h e alternate half-cycles. c
c
A n i n t e r m e d i a t e class b e t w e e n A and B , appropriately n a m e d class A B , involves biasing the transistor at a n o n z e r o dc current m u c h smaller t h a n t h e p e a k current of the sine-wave signal. A s a result, the transistor c o n d u c t s for an interval slightly greater than half a cycle, as illustrated in Fig. 14.1(c). T h e resulting c o n d u c t i o n angle is greater than 180° but m u c h less t h a n 3 6 0 ° . T h e class A B stage has a n o t h e r transistor that conducts for an interval slightly greater t h a n that of t h e n e g a t i v e half-cycle, a n d the currents from t h e t w o transistors are c o m b i n e d in t h e load. It follows that, d u r i n g t h e intervals n e a r t h e zero crossings of the input sinusoid, b o t h transistors conduct: Figure 14.1(d) s h o w s the collector-current w a v e f o r m for a transistor operated as a class C amplifier. O b s e r v e that t h e transistor c o n d u c t s for an interval shorter than that of a halfcycle; that is, the c o n d u c t i o n angle is less t h a n 180°. T h e result is t h e periodically pulsating current w a v e f o r m s h o w n . T o obtain a sinusoidal o u t p u t voltage, this current is passed t h r o u g h a parallel L C circuit, tuned to the frequency of t h e input sinusoid. T h e tuned circuit acts as a b a n d p a s s filter and p r o v i d e s an output v o l t a g e proportional to the a m p l i t u d e of the fundamental c o m p o n e n t in the Fourier-series representation of t h e current w a v e f o r m . Class A, A B , a n d B amplifiers are studied in this chapter. T h e y are e m p l o y e d as output stages of o p a m p s and audio p o w e r amplifiers. In t h e latter application, class A B is the pre ferred c h o i c e , for reasons that will b e e x p l a i n e d in the following sections. C l a s s C amplifiers are usually e m p l o y e d for radio-frequency (RF) p o w e r amplification (required, e.g., in mobile phones and radio and T V transmitters). T h e design of class C amplifiers is a rather specialized topic a n d is not included in this b o o k .
(c)
(d)
F I G U R E 14.1 Collector current waveforms for transistors operating in (a) class A , (b) class B. (c) class A B , and (d) class C amplifier stages.
A l t h o u g h t h e B I T has b e e n used to illustrate the definition of the various output-stage classes, the s a m e classification applies to output stages implemented with M O S F E T s . Further m o r e , the classification a b o v e extends to amplifier stages other than those used at the output. In this regard, all the c o m m o n - e m i t t e r , c o m m o n - b a s e , and c o m m o n - c o l l e c t o r amplifiers (and their F E T counterparts) studied in earlier chapters fall into the class A category.
14.2
CLASS A OUTPUT STAGE
B e c a u s e of its l o w output resistance, the e m i t t e r follower is the m o s t p o p u l a r class A output stage. W e h a v e already studied the emitter follower in C h a p t e r s 5 and 6 ; in the following w e consider its large-signal operation.
14.2.1 Transfer Characteristic F i g u r e 14.2 s h o w s an emitter follower Q b i a s e d w i t h a constant current I supplied b y tran sistor Q . S i n c e t h e emitter current i = I + i , the bias current I m u s t b e greater than t h e l
2
E1
L
1231
14.2
CHAPTER 14 O U T P U T S T A G E S A N D P O W E R A M P L I F I E R S
CLASS A OUTPUT STAGE
1 2 3 3
In the negative direction, d e p e n d i n g o n the values of / and R , the limit of the linear region is d e t e r m i n e d either b y Q turning off, L
+
V
CC
x
= -IRL
(14.3)
or b y Q saturating, 2
%min = -V
+
CC
(14.4)
V 2szt CE
T h e absolutely l o w e s t output voltage is that given b y Eq. (14.4) and is a c h i e v e d p r o v i d e d the bias current / is greater than the m a g n i t u d e of the c o r r e s p o n d i n g l o a d current,
R
L
F I G U R E 1 4 . 2 A n emitter follower (Q ) biased with a constant current I supplied by transistor Q . x
D14.1
2
For the emitter follower in Fig. i 4.2, V - 1 5 V , V = 0.2 V, V = 0.7 V and constant, and B is very f high. Find the value of R that will establish a bias current sufficiently large to allowithe largest possible output signal swing for R = 1 kQ. Determine the resulting output signal swing and the minimum and maximum emitter currents. CC
LDAI
BE
L
largest n e g a t i v e load current; o t h e r w i s e , Q , cuts off and class A operation will n o longer b e maintained. T h e transfer characteristic of t h e emitter follower of F i g . 14.2 is described b y v =v,-v 0
where v
BE1
d e p e n d s o n the emitter current i
El
t h e relatively small c h a n g e s in v
BEl
B
E
Ans. 0.97 k Q ; - 1 4 . 8 V to +14.8 V: U to 29.6 m A 14.2 (14.1)
l
For the emitter follower of Exercise 14.1. in which / = 14.8 mA, consider the case in which v is limited to,fhc r a n g e - 1 0 V t o + 10 V. Let Q have v = 0.6 V at••£•<-= 1 mA, and assume c/.~ 1. Find T> correspond* ing to v = - 1 OA/, 0 V, and +10 V. At each of these points, use small-signal analysis to determine the volt: age gain v /Vj. Note that the incremental voltage gain gives the slope of the w ,-versus-r^ characteristic. Ans. - 9 . 3 6 V. 0.67 V. 10.6s \ : 11.995 V/V, O.'J'W V \ . d . ' W V7V 0
t
a n d t h u s o n t h e load current i . If w e neglect
BE
0
L
0
( 6 0 m V for every factor-of-10 c h a n g e in emitter cur
rent), the linear transfer curve shown in Fig. 14.3 results. A s indicated, the positive h m i t of the
r
linear r e g i o n is d e t e r m i n e d b y the saturation of Q ; t h u s x
14.2.2 Signal Waveforms C o n s i d e r t h e operation of t h e emitter-follower circuit of F i g . 14.2 for s i n e - w a v e input. N e g l e c t i n g V i , w e see that if the bias current I is properly selected, the output v o l t a g e can s w i n g from - V t o +V w i t h t h e q u i e s c e n t v a l u e b e i n g z e r o , as s h o w n in F i g . 14.4(a). F i g u r e 14.4(b) s h o w s t h e c o r r e s p o n d i n g w a v e f o r m of v \ = V - v . N o w , a s s u m i n g that the bias current / is selected t o allow a m a x i m u m n e g a t i v e l o a d current of V /R , t h e col lector current of Q will h a v e t h e w a v e f o r m s h o w n in Fig. 14.4(c). Finally, Fig. 14.4(d) shows the w a v e f o r m of the i n s t a n t a n e o u s p o w e r d i s s i p a t i o n in Q , C£sa
(V
CC
—
V
)
CELSAX
c c
CC
CE
cc
0
CC
L
x
x
PDI = v
C E 1
i
(14.6)
c l
14.2.3 Power Dissipation F i g u r e 14.4(d) indicates that t h e m a x i m u m instantaneous p o w e r dissipation in Q is V I. This is equal t o t h e quiescent p o w e r dissipation in (J . T h u s t h e emitter-follower transistor dissipates t h e largest a m o u n t of p o w e r w h e n v = 0. S i n c e this condition (no input signal) can easily prevail for p r o l o n g e d periods of time, transistor Q m u s t b e able to withstand a c o n t i n u o u s p o w e r dissipation of V I. x
CC
{
0
x
CC
T h e p o w e r dissipation in Q d e p e n d s o n the value of R . C o n s i d e r the e x t r e m e case of an output o p e n circuit, that is, R = °°. In this case, i = I is constant a n d t h e instantaneous p o w e r dissipation in Q will d e p e n d o n the instantaneous v a l u e of v . T h e m a x i m u m p o w e r dissipation will occur w h e n v = -V , for i n this case v is a m a x i m u m of 2V and p = 2 V 7 . T h i s condition, h o w e v e r , w o u l d n o t n o r m a l l y persist for a p r o l o n g e d interval, s o t h e x
L
L
FIGURE 14.3
Transfer characteristic o f the emitter follower i n Fig. 14.2. This linear characteristic is
c l
x
obtained by neglecting the change i n v
BEl
with i . The maximum positive output is determined by me saturation L
0
0
of g i - I n the negative direction, the limit o f the linear region is determined either by Q turning off or by t>2 x
saturating, depending on the values of I and R . L
CC
cc
CEl
CC
m
1 2 3 4
CHAPTER 1 4 O U T P U T S T A G E S A N D P O W E R A M P L I F I E R S
14.3
CLASS B OUTPUT STAGE
£ ¿ 1
1 2 3
14.2.4 Power-Conversion Efficiency T h e p o w e r - c o n v e r s i o n efficiency of a n output stage is defined as V
L o a d p o w e r (P,) « S u p p l y p o w e r (P )
s
(14.7)
s
For t h e emitter follower of F i g . 14.2, a s s u m i n g that t h e output v o l t a g e is a sinusoid with t h e p e a k v a l u e V , t h e a v e r a g e l o a d p o w e r will b e 0
(V /J2f
=
0
lyL
=
1
Since the c u r r e n t in Q
2
4
is c o n s t a n t ( / ) , t h e p o w e r d r a w n from t h e n e g a t i v e s u p p l y is
V I. CC
current in Q is e q u a l t o I, a n d t h u s t h e a v e r a g e p o w e r d r a w n from t h e positive x
supply is V I.
PD\
1
L
L
T h e average
(
2R
R
T h u s t h e total a v e r a g e s u p p l y p o w e r is
CC
Ps = 2
y
(14-9)
Equations (14.8) a n d (14.9) c a n b e c o m b i n e d t o yield VrrI 4
IR V L
CC
(14.10) 4{IRJ{V J
(d)
CC
F I G U R E 1 4 . 4 M a x i m u m signal waveforms i n the class A output stage of Fig. 14.2 under the condition 7 = V /R or,equivalently, R = V /I. CC
L
L
Since V ^ V 0
cc
a n d V < IR , 0
L
m a x i m u m efficiency is obtained w h e n
CC
V
0
= V
CC
= IR
(14.11)
L
design n e e d n o t b e that c o n s e r v a t i v e . O b s e r v e that w i t h an open-circuit load t h e average
T h e m a x i m u m efficiency attainable is 2 5 % . B e c a u s e this is a rather l o w figure, t h e class A
p b w e r dissipation in Q is V I.
output stage is rarely u s e d in h i g h - p o w e r applications ( > 1 W ) . N o t e also that i n practice t h e
x
of R —specifically,
A far m o r e d a n g e r o u s situation occurs at t h e other extreme
CC
R = 0. In t h e e v e n t of an o u t p u t short circuit, a p o s i t i v e input voltage
L
L
w o u l d theoretically result i n an infinite load current. In practice, a very large current m a y flow t h r o u g h Q
u
output voltage swing is limited to l o w e r values t o avoid transistor saturation a n d associated nonlinear distortion. T h u s t h e efficiency a c h i e v e d is u s u a l l y in t h e 1 0 % t o 2 0 % r a n g e .
a n d if t h e short-circuit c o n d i t i o n persists, t h e resulting large p o w e r dissipa-
tion i n Q] Can raise its j u n c t i o n t e m p e r a t u r e b e y o n d t h e specified m a x i m u m , causing Q to x
b u r n u p . T o g u a r d against such a situation, output stages a r e usually e q u i p p e d with shortcircuit protection,
as will b e e x p l a i n e d later.
T h e p o w e r d i s s i p a t i o n i n Q a l s o m u s t b e t a k e n i n t o a c c o u n t i n d e s i g n i n g a n emitter2
f o l l o w e r output stage. S i n c e Q c o n d u c t s a c o n s t a n t current I, a n d t h e m a x i m u m value of 2
v
CE2
is 2V , CC
t h e m a x i m u m i n s t a n t a n e o u s p o w e r dissipation in Q is 2V I. 2
however, occurs when v = V , 0
CC
This m a x i m u m ,
a condition that w o u l d n o t n o r m a l l y prevail for a prolonged
cc
period of time. A m o r e significant quantity for design purposes is the average p o w e r dissipation in Q , w h i c h is 2
14.4
For the emitter follower of Fig. 14.2, let V = 10 V. / = 100 m A , and R = 100 Q . If ihe output voltage is an 8-V-peak sinusoid, find the following: (a) the power delivered to the load: (b) the average power drawn from the supplies; (c) the power-conversion efficiency. . Ignore ihe l o s - i n ß ? and. A?RC
!
Ans. 0.32 W ; 2 \ \ : lo'/c
V I. CC
14.3 14.3
L
G m - i d e r ihe ciniilcr follower in l-'ig. 14.2 with V. . -• 10 \ . / - |(i() m . \ . and R,•••••100 SI. find the power dissipated in (J and (J- under quiescent condition* i I)i. |-or a sinusoidal output voilage of m a x i m u m possible amplitude (neglecting V ), find the average power dissipation in Q and 0 . \ K o lind ihe load power. Ans I W . I \\ : 0.5 \ \ . I \ \ : 0.5 \\ CEsM
x
CLASS B OUTPUT S T A G E
Figure 14.5 s h o w s a class B o u t p u t stage. It consists of a c o m p l e m e n t a r y pair of transistors (an npn a n d a pnp) c o n n e c t e d in s u c h a w a y that b o t h c a n n o t c o n d u c t simultaneously.
2
This does not include the power d r a w n b y the biasing resistor R and the diode-connected transistor Q . 3
CHAPTER 14
O U T P U T STAGES A N DPOWER
AMPLIFIERS
14.3
CLASS B O U T P U T STAGE
+ V
CC
V
( CC
(-V + cc
Vncm-
V ) EBP
IcfiVsat)
I
vi I
(Ice
*C£JVsat +
V ) BEN
+0.5 V
(-v +
V
cc
FIGURE 1 4 . 5
—V
cc
A class B output stage.
)
ECPsM
FIGURE 1 4 . 6 Transfer characteristic for the class B output stage in Fig. 14.5.
14.3.1 Circuit Operation W h e n t h e input voltage v is zero, b o t h transistors a r e c u t off a n d t h e output voltage v is zero. A s v g o e s positive a n d e x c e e d s about 0.5 V , Q c o n d u c t s a n d operates as a n emitter follower. In this case v follows w '(i.e., v = v ~ v ) a n d Q supplies the l o a d current. M e a n w h i l e , t h e e m i t t e r - b a s e j u n c t i o n of Q will b e reverse-biased b y the V of Q , which is a p p r o x i m a t e l y 0.7 V . T h u s Q will b e c u t off. If t h e input goes n e g a t i v e b y m o r e t h a n about 0.5 V , Q turns o n a n d acts as a n emitter follower. A g a i n v follows v (i.e., v = v + v ), b u t i n this c a s e Q supplies t h e load cur rent a n d Q will b e c u t off. W e c o n c l u d e that t h e transistors in t h e class B stage of F i g . 14.5 are biased at zero cur rent a n d c o n d u c t only w h e n t h e input signal is present. T h e circuit operates in a p u s h - p u l l fashion: Q pushes (sources) current into t h e l o a d w h e n v, is positive, a n d Q pulls (sinks) current from t h e load w h e n v, is negative. 1
0
t
N
0
7
0
r
BEN
N
P
BE
N
P
P
0
I
0
1
EBP
P
N
N
P
14.3.2 Transfer Characteristic A sketch of t h e transfer characteristic of the class B stage is s h o w n in F i g . 14.6. N o t e that there exists a r a n g e of vj centered a r o u n d zero w h e r e b o t h transistors are cut off a n d v is zero. T h i s d e a d b a n d results in t h e c r o s s o v e r distortion illustrated in Fig. 14.7 for the case of a n input sine w a v e . T h e effect of crossover distortion will b e m o s t p r o n o u n c e d w h e n the a m p l i t u d e of t h e input signal is small. C r o s s o v e r distortion i n audio p o w e r amplifiers gives rise t o u n p l e a s a n t s o u n d s . 0
14.3.3 Power-Conversion Efficiency
FIGURE 1 4 . 7 Illustrating how the dead band in the class B transfer characteristic results in crossover distortion.
% /KR . It f o l l o w s t h a t t h e a v e r a g e p o w e r d r a w n from each of the t w o p o w e r supplies will be t h e s a m e , L
T o calculate t h e p o w e r - c o n v e r s i o n efficiency, rj, of the class B stage, w e neglect t h e cross over distortion a n d consider the c a s e of a n output sinusoid of p e a k a m p l i t u d e V - T h e aver 0
age, l o a d p o w e r will b e
(14.13) (14.12)
T h e current d r a w n from each supply will consist of half-sine w a v e s of p e a k amplitude (V /R ). T h u s t h e average current d r a w n from e a c h o f t h e t w o p o w e r supplies will be 0
L
and the total s u p p l y p o w e r will b e 7V KR
T
cc
(14.14)
CHAPTER 14
O U T P U T STAGES A N DPOWER
14.3
AMPLIFIERS
CLASS B OUTPUT STAGE
Pnk
Thus the efficiency will b e given b y
It follows that the m a x i m u m efficiency is obtained w h e n ft is at its m a x i m u m . T h i s maxi m u m is limited b y t h e saturation of Q and Q t o V ~ V ccof p e a k output voltage, the p o w e r - c o n v e r s i o n efficiency is v
N
r,
P
cc
A
t
m
= J = 78.5%
m a x
i
s
v
a
l
u
e
CEsit
V =
78.5%
(14.16)
T h i s value is m u c h larger than that obtained in the class A stage ( 2 5 % ) . Finally, w e note that the m a x i m u m a v e r a g e p o w e r available from a class B output stage is obtained b y substitut ing ft = V
cc
in Eq. (14.12), F I G U R E 1 4 . 8 Power dissipation o f the class B output stage versus amplitude o f the output sinusoid.
2
K
L
stage w h i l e increasing t h e load power. T h e price paid is a n increase in nonlinear distortion as a result of approaching the saturation region of operation of CT^and Q . Transistor satura tion flattens the peaks of the output sine waveform. Unfortunately, this type of distortion cannot b e significantly reduced b y the application of negative feedback (see Section 8.2), a n d thus transistor saturation should b e avoided i n applications requiring l o w T H D .
14.3.4 Power Dissipation
P
Unlike the class A stage, which dissipates m a x i m u m p o w e r under quiescent conditions (v = 0), the quiescent p o w e r dissipation of the class B stage is zero. W h e n an input signal is applied, the average p o w e r dissipated in the class B stage is given b y 0
P
= P -PL
D
(14-18)
S
Substituting for P from Eq. (14.14) and for P from Eq. (14.12) results in s
L
P
=2V, D
IVJ, C
KR
C
(14.19)
2R
L
It is required to design a class B output stage to deliver an average power of 20 W to an 8-Q load. The power supply is to be selected such that V is about 5 V greater than the peak output voltage. This avoids transistor saturation and the associated nonlinear distortion, and allows for including short-circuit protection circuitry. (The latter will be discussed in Section 14.7.) Determine the supply voltage required, the peak current drawn from each supply, the total supply power, and the power-conversion efficiency. Also determine the maximum power that each transistor must be able to dissipate safely.
L
F r o m s y m m e t r y w e see that half of P is dissipated i n Q a n d t h e other half in g p . Thus QNand QP m u s t b e c a p a b l e of safely dissipating \P watts. Since P d e p e n d s o n ft, w e m u s t find t h e w o r s t - c a s e p o w e r dissipation, P . Differentiating E q . (14.19) with respect to ft a n d equating the derivative to zero gives t h e v a l u e of ft that results in m a x i m u m aver age p o w e r dissipation as
cc
N
D
D
D
Dmm
ft I P.
= -Vcc
4
a -
2 0
Substituting this v a l u e in E q . (14.19) gives
)
Solution Since
2
P 1
2
Dmax
V
c
c
(14.21)
P
_
L
iVl
~2Y
2
nR.
L
T
Thus,
then = YknR
ft = 42P J
(14.22)
l
.
L
? ; a
= 7 2 x 2 0 x 8 = 17.9 V
L
A t the point of m a x i m u m p o w e r dissipation t h e efficiency can b e evaluated b y substituting for \/ from Eq. (14.20) into Eq. (14.15); h e n c e , r\ = 5 0 % . F i g u r e 14.8 s h o w s a sketch of P (Eq. 14.19) versus the p e a k output voltage ft. C u r v e s such as this are usually given on the data sheets of I C p o w e r amplifiers. (Usually, however, P is plotted versus P , as P = \{vl/R ), rather than ft). A n interesting observation follows from Fig. 14.8: Increasing ft b e y o n d 2V /n decreases the p o w e r dissipated i n the class B 0
D
Therefore w e select V = 23 V. The peak current drawn from each supply is cc
D
L
L
L
cc
;
0
= ^ R
L
=
iL9 8
=
2
.
2
4
A
1 2 3 9
CHAPTER 14
O U T P U T STAGES A N D POWER
AMPLIFIERS
14.4
2
The average power drawn from each supply is
CLASS AB O U T P U T STAGE
¿"3
1 2 4 1
Vcc A
i>
= Pc
= -x
2 . 2 4 x 2 3 = 16.4 W
for a total supply power of 32.8 W . The power-conversion efficiency is r, '
=
!1±
=
x
P
100 = 6 1 %
32.8
s
The maximum power dissipated in each transistor is given by Eq. (14.22); thus P
-
p
V
-
c
FIGURE 1 4 . 1 0 Class B output stage operated with a single power supply.
c
2
KR
L
= i23_L
=
6
7
w
•ix%
14.5
14.3.5 Reducing Crossover Distortion T h e crossover distortion of a class B output stage can b e r e d u c e d substantially by employing a high-gain op a m p and overall negative feedback, as s h o w n in Fig. 14.9. T h e ± 0 . 7 - V dead b a n d is r e d u c e d to ± 0 . 7 / A volt, w h e r e A is the dc gain of the op a m p . Nevertheless, the slew-rate limitation of the op a m p will c a u s e the alternate turning on and off of the output transistors t o b e noticeable, especially at h i g h frequencies. A m o r e practical m e t h o d for r e d u c i n g and a l m o s t eliminating crossover distortion is found in the class A B stage, which will b e studied in the next section. 0
For the class ß output stage of Fig. 14.5. let V, = 6 V and R , = 4 LI. If die output is a sinusoid with 4.5-V peak amplitude, find (a) the output power: (b) the average power drawn from each supply; (c) the power efficiency obtained at this output voltage; (d) the peak currents supplied by v assuming that y3. = ß = 50; (e) the maximum power that each transistor must be capable of dissipating safely. x
h
v
P
Ans.
(a) 2.53 W ; (b) 2.15 W; (c) 5 9 % : (d) 22.1 m A : (e) 0.91 W
0
14.3.6 Single-Supply Operation T h e class B stage can b e operated from a single p o w e r supply, in w h i c h case the load is capacitively coupled, as s h o w n in Fig. 14.10. N o t e that to m a k e the formulas derived in Section 14.3.4 directly applicable, the single p o w e r supply is denoted 2V -
'
14.4
CLASS AB OUTPUT STAGE
C r o s s o v e r distortion c a n b e virtually eliminated by biasing the c o m p l e m e n t a r y output transistors at a small n o n z e r o current. T h e result is the class A B output stage shown in Fig. 14.11. A bias voltage V is applied b e t w e e n the bases of Q and Q . F o r v, = 0, v = 0, a n d a voltage V /2 appears across the b a s e - e m i t t e r j u n c t i o n of each of Q and Q . A s s u m i n g BB
N
P
BB
0
N
P
CC
F I G U R E 1 4 . 1 1 Class A B output stage. A bias voltage V is applied between the bases of Q and Q , giving rise to a bias current I given by Eq. (14.23). Thus, for small v both transistors conduct and crossover distortion is almost completely eliminated. BB
FIGURE 14.9 distortion.
Class B circuit w i t h an op amp connected in a negative-feedback loop to reduce crossover
Q
N
h
P
1242
CHAPTER 1 4
OUTPUT STAGES A N D POWER
AMPLIFIERS
14.4
CLASS AB OUTPUTSTAGE
matched devices, V
•
i
= i = I
N
T h e v a l u e of V
P
/2V
BB T
= le
Q
(14.23)
s
is selected to yield t h e r e q u i r e d q u i e s c e n t current I .
BB
Q
14.4.1 Circuit Operation W h e n v g o e s p o s i t i v e b y a certain a m o u n t , t h e v o l t a g e at t h e b a s e of Q increases by the l
N
s a m e a m o u n t a n d t h e output b e c o m e s positive at a n a l m o s t e q u a l value,
v
= Vi+-f--v N
0
(14.24)
BE
T h e p o s i t i v e v c a u s e s a current i t o flow t h r o u g h R , a n d thus i m u s t increase; that is, 0
L
L
i
= i +i
N
P
N
(above t h e quies
BEN
FIGURE 1 4 . 1 2 Transfer characteristic of the class AB stage in Fig. 14.11.
H o w e v e r , since t h e v o l t a g e b e t w e e n t h e t w o b a s e s r e m a i n s constant at
BB
V , the increase in v BB
Vecrut)
(14.25)
L
T h e i n c r e a s e i n i will b e a c c o m p a n i e d b y a c o r r e s p o n d i n g i n c r e a s e in v c e n t v a l u e of V /2).
(-Vcc+
N
will result i n an e q u a l d e c r e a s e in v
BEN
EBP
a n d h e n c e in i . T h e relation P
ship b e t w e e n i and i c a n b e derived as follows: N
P
V
+
V
BEN
=
EBP 1
V \n^+V \n±=2V \n f T
T
T
i i N
T h u s , as i
N
2
P
= I
(14,26)
Q
i n c r e a s e s , i d e c r e a s e s b y t h e s a m e ratio w h i l e t h e p r o d u c t r e m a i n s constant. P
Rm
E q u a t i o n s (14.25) a n d (14.26) c a n b e c o m b i n e d t o yield i for a g i v e n i as t h e solution to N
L
the q u a d r a t i c e q u a t i o n i
2 N
-i i -I L
N
= 0
2 Q
FIGURE 1 4 . 1 3 Determining the small-signal output resistance of the class AB circuit of Fig. 14.11.
(14.27)
F r o m t h e equations above, w e c a n see that for positive output voltages, the load current is supplied by Q , which acts as the output emitter follower. M e a n w h i l e , Q will b e conducting a N
P
current that decreases as v increases; for large v t h e current in Q c a n b e ignored altogether. 0
0
P
F o r n e g a t i v e i n p u t voltages the opposite o c c u r s : T h e load current will b e supplied b y Q , P
w h i c h acts as t h e output emitter follower, w h i l e Q c o n d u c t s a current that gets smaller as v N
14.4.2 Output Resistance If w e a s s u m e that t h e s o u r c e supplying v, is ideal, then the output resistance of t h e class A B s t a g e c a n b e d e t e r m i n e d f r o m the circuit in F i g . 14.13 as
t
b e c o m e s m o r e negative. E q u a t i o n (14.26), relating i a n d i , holds for negative inputs as well. N
v
P
W e c o n c l u d e that t h e class A B stage operates i n m u c h t h e s a m e m a n n e r as t h e class B circuit, w i t h o n e i m p o r t a n t e x c e p t i o n : F o r small v
b
b o t h transistors conduct, and as v, is
i n c r e a s e d o r decreased, o n e of t h e t w o transistors takes o v e r t h e operation. S i n c e the transi
where r
eN
and r
eP
out
(14.28)
' eN " ' eP
a r e t h e small-signal e m i t t e r resistances of Q
N
a n d Q , respectively. A t a P
g i v e n i n p u t v o l t a g e , t h e currents i and i c a n b e d e t e r m i n e d , and r N
P
eN
and r
eP
are given b y
tion is a s m o o t h o n e , crossover distortion will b e a l m o s t totally eliminated. F i g u r e 14.12 (14.29)
' eN
s h o w s t h e transfer characteristic of t h e class A B stage. T h e p o w e r relationships in t h e class A B stage a r e a l m o s t identical to t h o s e derived for t h e class B circuit in Section 14.3. T h e only difference is that u n d e r q u i e s c e n t conditions the class A B circuit dissipates a p o w e r of V I CC
Q
p e r transistor. S i n c e I
Q
(14.30)
is usually m u c h smaller
than t h e p e a k load current, t h e q u i e s c e n t p o w e r dissipation is usually small. Nevertheless, it
Thus
can b e t a k e n into a c c o u n t easily. Specifically, w e c a n simply a d d t h e q u i e s c e n t dissipation p e r transistor t o its m a x i m u m p o w e r dissipation with a n input signal applied, t o obtain the total p o w e r dissipation that t h e transistor m u s t b e able t o h a n d l e safely.
R
-
V
r
V,T lp
(14.31) lp + l
N
fi*'!
1
243
\l
CHAPTER 14
O U T P U T STAGES A N D POWER AMPLIFIERS
14.5
BIASING THE CLASS AB CIRCUIT
S i n c e as i increases, i decreases, and v i c e versa, t h e output resistance r e m a i n s approxiN
P
m a t e l y c o n s t a n t in t h e r e g i o n a r o u n d v, = 0. T h i s , i n effect, i s t h e r e a s o n for the virtual a b s e n c e of c r o s s o v e r distortion. A t larger load currents, either i or i will b e significant, and N
R
oM
.6
P
d e c r e a s e s as t h e l o a d current i n c r e a s e s .
Consider a ela>s AB chcuil with \ \ . - 15 V . I., - 2 m \ . and A' - 100 Q . Delennine V ,.. COUMILM a table giving i,. i . i . v . v . v„ v /v,. R„ . and v /Vf versus v for v = 0, 0 . 1 , 0.2. 0.5. 1, 5, 10, - 0 . 1 . -0.2."-0'.5. - 1 , - 5 and - 1 0 V. Note that v /v -\s Ihe large-signal voltage gain and v /v- is the incremental gain obtained as R /(R + R „l The incremental gain is equal to the slope of the transfer curve at the operating point. Assume Q and Q to be matched, with I = 1 0 " A . x
P
Hhy
EBP
()
ui
0
0
L
L
0
0
r
0
N
t
P
P
x
—V
n
N
FIGURE 1 4 . 1 4 A class AB output stage utilizing diodes for biasing. If the junction area of the output devices, Q and Q , is n times that of the biasing devices D and D , and a quiescent current I = nI flows in the output devices.
cc
Q
2
mAS
s
W h e n t h e output stage of Fig. 14.14 is s o u r c i n g current to the load, the b a s e current of Q
N
increases from I /ji Q
v
(mA)
(V)
100
100.04
0.04
0.691
0.495
+5.0
50
50.08
0.08
0.673 .
0.513
+1.0
10
10.39
0.39
0.634
+0.5
5
5.70
0.70
0.619
+0.2
2
3.24
1.24
0.605
0.581
0.599
0.587
/. (mA)
+10.0
+0.1 I'
-0.1
/
' '2
0
1.56
-1
-0.2
-2
-0.5
-5 •
-1.0
10 -50
-5.0 -10.0
1.56
2.56
1
v /v,
WIÊm
0
11111
drive m u s t b e supplied b y the current s o u r c e 7
B I A S
. It follows that 7
B I A S
This base current
N
m u s t be greater than
5.08
0.98
0.552
1.041
0.567
0.526
0.96 o.wr
0.212
0.94
5.58
0.95
0.106
0.94
6.07
0.94
w h e n the output stage is sourcing c u r r e n t t o t h e load. T h u s the bias voltage V
-
6.25
0.94
decrease, and the analysis of Section 14.4 m u s t b e modified to take this effect into account.
0.94
6.07
0.94
T h e d i o d e b i a s i n g a r r a n g e m e n t h a s a n i m p o r t a n t a d v a n t a g e : It c a n p r o v i d e t h e r m a l stabi-
0.95
lization of t h e q u i e s c e n t c u r r e n t in t h e o u t p u t stage. T o appreciate this point recall that t h e
0.96
2
0.593
0.593
0.587
0.599
0 -0.106
1.00
the m a x i m u m anticipated b a s e drive for Q . T h i s sets a l o w e r limit o n the value of 7
0.50
1.00
since I = nI
2.32
0.98
see that w e c a n n o t m a k e n a large n u m b e r . In other w o r d s , w e cannot m a k e the diodes m u c h
4.03
0.96
smaller than the output devices. T h i s is a d i s a d v a n t a g e of the diode biasing scheme.
: 1.24
3.24
0.581
0.605
-0.212
0.94
0.70
5.70
0.567
0.619
-0.526
0.95
4.03
0.39
10.39
0.552
0.634
-.1.041
0.96
2.32
0.98
0.08
50.08
0.513
0.673
-5.08
0.98
0.50
1.00
0.495
L
0.25
2.56
100.04
( w h i c h i s u s u a l l y s m a l l ) t o approximately i //3 .
0.99
10.1
5.58
0.04
-100
£ B P
i/,(V)
(V)
'inAi
*b(V)
N
0.691
-10.1
0.25
0.99
N
g
B I A S
. Now,
and since I is u s u a l l y m u c h smaller than the p e a k load current ( < 1 0 % ) , w e
BlAS
Q
F r o m the discussion a b o v e w e see that t h e current through the biasing diodes will decrease BB
will also
class A B o u t p u t stage dissipates p o w e r u n d e r q u i e s c e n t condi t i ons . P o w e r dissipation raises the internal t e m p e r a t u r e of t h e B J T s . F r o m C h a p t e r 5 w e k n o w that a rise in transistor t e m perature results in a d e c r e a s e in its V
BE
held constant. Al t ernat i vel y, if V
BE
1.00
( a p p r o x i m a t e l y - 2 m V / ° C ) if t h e collector current is
is h e l d c o n s t a n t and the t e m p e r a t u r e increases, t h e c o l -
lector current i n c r e a s e s . T h e i n c r e a s e i n c o l l e c t o r current increases the p o w e r dissipation, w h i c h i n turn i ncreas es t h e collector c u r r e n t . T h u s a positive-feedback m e c h a n i s m exists that can result in a p h e n o m e n o n called t h e r m a l r u n a w a y . U n l e s s c h e c k e d , t h e r m a l r u n a w a y can lead to t h e u l t i m a t e d e s t r u c t i o n of t h e B J T . D i o d e bi as i ng can b e arranged to p r o v i d e a c o m p e n s a t i n g effect that c a n p r o t e c t t h e o u t p u t transistors against t h e r m a l r u n a w a y u n d e r
14.5 ,~ BIASING" THE CLASS AB CIRCUIT
quiescent c o n d i t i o n s . Specifically, if t h e d i o d e s are in close t h e r m a l contact w i t h the output transistors, their t e m p e r a t u r e will i n c r e a s e b y t h e s a m e a m o u n t as that of Q and Q . T h u s N
In this section w e discuss t w o a p p r o a c h e s for generating t h e v o l t a g e V
BB
required for biasing
the class A B output stage.
V
BB
will d e c r e a s e at t h e s a m e rate as V
BEN
P
+ V , w i t h the result that I r e m a i n s constant. EBP
Q
Close t h e r m a l c o n t a c t is easily a c h i e v e d i n I C fabrication. It is obtained in discrete circuits by m o u n t i n g t h e b i a s d i o d e s o n t h e m e t a l c a s e of Q or Q . N
P
14.5.1 Biasing Using Diodes F i g u r e 14.14 s h o w s a class A B circuit in w h i c h t h e b i a s v o l t a g e V
BB
a constant current 7
B I A S
is g e n e r a t e d b y passing
t h r o u g h a pair of d i o d e s , or d i o d e - c o n n e c t e d transistors, D and D x
2
In circuits that supply large a m o u n t s o f p o w e r , t h e output transistors are large-geometry d e v i c e s . T h e b ias in g diodes, h o w e v e r , n e e d m o t b e large d e v i c e s , and thus the quiescent current I
Q
e s t a b l i s h e d in Q a n d Q w i l l b e I = « / N
P
Q
B I A S
, w h e r e n i s t h e ratio of t h e e m i t t e r -
j u n c t i o n area of t h e output devices to the j u n c t i o n area of the b i asi n g d i o d e s . In other words, t h e saturation (or scale) current 7 o f t h e output transistors i s n times that of the biasing S
d i o d e s . A r e a ratioing is s i m p l e to i m p l e m e n t in integrated circuits but difficult to realize in discrete-circuit designs.
Consider the class AB output stage under the conditions that V = 15 V, R = 100 Q , and the output is sinusoidal with a m a x i m u m a m p l i t u d e of 10 V. Let Q and Q be matched with I s = 10 A and ¡5 = 5 0 . A s s u m e that the biasing diodes have one-third the junction area of the output devices. Find the value of 7 that guarantees a m i n i m u m of 1 m A through the diodes at all times. Determine the quiescent current and the quiescent power dissipation in the output transistors (i.e., at v = 0). Also find V for v = 0, + 1 0 V , and - 1 0 V . cc
L
N
B I A S
0
BB
0
P
^
1 2 4 5
1246
.
CHAPTER 14
14.5
O U T P U T STAGES A N D POWER AMPLIFIERS
BIASING THE CLASS AB CIRCUIT
Solution I lie m a x i m u m current through 0 is approximately equal to ; ' = 1 0 V/0.1 k f i = 1 0 0 m A I hus the m a x i m u m base current in Q is approximately 2 m A . To maintain a minimum of 1 mA through the diodes, we select / j = 3 m A . T h e area ratio of 3 yields a quiescent current of ' iiiA through Q and Q . The quiescent power dissipation is N
i m a x
N
B
A S
l
N
P
P
= 2 x 15 x 9 = 270 m W
DQ
I or v = 0, the base current of Q is 9 / 5 1 — 0.18 mA, leaving a current of 3 - 0.18 = 2.82 mA IK How through the diodes. Since the diodes have I = | x 10~ A, the voltage V will be 0
N
13
s
2
V
BB
= 2V In '
8
BB
2
m
A
T
= 1.26 V
h \\ VQ = + 1 0 V , the current through the diodes will decrease to 1 m A , resulting in V = 1 . 2 1 V. \i the other extreme of v = - 1 0 V , Q will be conducting a very small current; thus its base BB
0
N
rent will be negligibly small and all of /
B I A S
(3 m A ) flows through the diodes, resulting in
, = 1 . 2 6 V.
EXERCISES 14.7
for i he circuit <>f I.\amplc 14.2. find /• and i,. lor
14.8
If the collector current of a transistor is held constant, its v decreases by 2 mV for every 1°C rise in temperature. A l i e m a i n c l } . if N held constant, then /', i n c i v a ^ In uppioxiiiiaicb y. '>• 2 n i \ for every 1 °C rise in temperature. For a device operating at I = 10 mA, find the change in collector current resulting from an increase in temperature of 5°C.
-
\ and
- -1 u \ .
BE
c
Ans. 4
mA
14.5.2 Biasing Using the V
BE
Multiplier
A n alternative biasing a r r a n g e m e n t that p r o v i d e s t h e designer w i t h considerably m o r e flexi bility in b o t h discrete a n d integrated designs is s h o w n in F i g . 14.15. T h e bias circuit consists of transistor Q w i t h a resistor R c o n n e c t e d b e t w e e n b a s e and emitter and a feedback resis tor R c o n n e c t e d b e t w e e n collector and b a s e . T h e resulting t w o - t e r m i n a l n e t w o r k is fed with a constant-current source / . If w e n e g l e c t t h e b a s e current of Q t h e n R and R will carry the s a m e current I , g i v e n b y 1
:
2
B I A S
u
x
2
R
I
R
= ^ 1 R
(14.32)
x
and t h e v o l t a g e V
BB
across t h e bias n e t w o r k will b e
F I G U R E 1 4 . 1 6 A discrete-circuit class AB output stage with a potentiometer used in the V The potentiometer is adjusted to yield the desired value of quiescent current in Q and Q .
BE
V
BB
= IniRi
+ Rt)
N
multiplier.
P
(14.33) = V 1 BE1
1 +
BB
T h u s the circuit simply multiplies V b y the factor ( 1 + R /R ) and is k n o w n as the "V multiplier." T h e multiplication factor is o b v i o u s l y u n d e r t h e d e s i g n e r ' s control and can be BE1
u s e d t o e s t a b l i s h t h e v a l u e of V r e q u i r e d t o yield a desired quiescent current I . In I C d e s i g n it is r e l a t i v e l y e a s y t o control accurately the ratio of t w o resistances. In discretecircuit d e s i g n , a p o t e n t i o m e t e r c a n b e used, as s h o w n in F i g . 14.16, a n d is m a n u a l l y set to p r o d u c e t h e d e s i r e d v a l u e of I .
2
x
BE
0
Q
1 2 4 7
14.6
CHAPTER 1 4 O U T P U T S T A G E S A N D P O W E R A M P L I F I E R S
T h e v a l u e of V
BE1
in E q . (14.33) is d e t e r m i n e d b y t h e p o r t i o n of 7
B I A S
that flows through
P O W E R BJTs
W e can now determine R + R as follows: X
t h e collector of Q ; that is,
2
VBB _ 1.19 R + Ä , = - ^ = — = 2.38 k Q I 0.5
x
1
R
1 4
ICA = I*IAS-IR
( -34)
At a collector current of 2.5 m A , Q has x
I
V
= V ln f±
BEl
(14.35)
T
V
BEX
h i
= V ln
1
5 X
1
0 3
r
= 0.66 V
10"
w h e r e w e h a v e n e g l e c t e d the b a s e current of Q , w h i c h is n o r m a l l y small b o t h u n d e r quies N
The value of R can now be determined as X
cent conditions a n d w h e n t h e output v o l t a g e is s w i n g i n g n e g a t i v e . H o w e v e r , for positive v , 0
especially a t a n d n e a r its p e a k value, t h e b a s e current of 0 r e d u c e t h e current available for t h e V
BE
N
= 1.32 k Q
=
R
c a n b e c o m e sizable a n d will
1
multiplier. N e v e r t h e l e s s , since large c h a n g e s in I
CI
c o r r e s p o n d t o only small c h a n g e s in V , the d e c r e a s e in current will b e m o s t l y absorbed b y
and R as 2
BEX
<2i, leaving I , and h e n c e V , a l m o s t constant. R
R
BB
2
' 9
Consider a V multiplier with R = R = 1 2 k Q . utilizing a transistor that has V = 0.6 V at I = 1 mA, and a very high j3, (a) Find the value of the current / that should b e supplied to the multiplier to obtain a terminal voltage of 1.2 V. .(b) Find the value o f / t h a t will result in the terminal voltage changing (from the 1.2-V value) by +50 mV, +100 m V , +200 mV, - 5 0 mV, - 1 0 0 m V , - 2 0 0 mV. Ans. iai 1.5 n.A; (b) 3.24 m A , 7.93 m A , 55.18 m A , 0.85 m A , 0.59 m A , 0.43 m A BE
X
2
BE
C
= 2 . 3 8 - 1.32 = 1.06 k Q
14.6 POWER BJTs
Transistors that a r e r e q u i r e d t o c o n d u c t currents i n t h e a m p e r e r a n g e a n d w i t h s t a n d p o w e r dissipation i n t h e w a t t s a n d tens-of-watts r a n g e s differ i n their p h y s i c a l structure, p a c k a g ing, a n d specification from t h e small-signal transistors c o n s i d e r e d i n earlier c h a p t e r s . I n this section w e c o n s i d e r s o m e of th& i m p o r t a n t p r o p e r t i e s of p o w e r transistors, especially t h o s e aspects that p e r t a i n t o t h e d e s i g n of circuits of t h e t y p e d i s c u s s e d earlier. T h e r e a r e , of c o u r s e , other i m p o r t a n t applications of p o w e r transistors, such a s their u s e as s wi t chi ng e l e m e n t s in p o w e r inverters and m o t o r - c o n t r o l circuits. S u c h applications are n o t studied in
L i k e t h e d i o d e b i as in g n e t w o r k , t h e V - multiplier circuit c a n p r o v i d e t h e r m a l stabiliza
this b o o k .
BE
tion of I . T h i s is especially true if R = R a n d Q is i n close t h e r m a l contact with t h e output Q
X
2
x
14.6.1 Junction Temperature
transistors.
P o w e r transistors dissipate large a m o u n t s of p o w e r i n their c o l l e c t o r - b a s e j u n c t i o n s . T h e dissipated p o w e r is c o n v e r t e d into heat, w h i c h raises the j u n c t i o n t e m p e r a t u r e . H o w e v e r , t h e j u n c t i o n t e m p e r a t u r e Tj m u s t n o t b e a l l o w e d t o e x c e e d a specified m a x i m u m , 7 / w i s e the transistor c o u l d suffer p e r m a n e n t d a m a g e . F o r silicon devices, T
Jimx
It is required to redesign the output stage of E x a m p l e 14.2 utilizing a V
BE
U
ing. U s e a small-geometry transistor for Q, with I = VT S
I
Q
multiplier for bias
m a x
; other
is i n the r a n g e
of 150°C t o 2 0 0 ° C .
A and design for a quiescent current
14.6.2 Thermal Resistance
= 2 mA.
C o n s i d e r first t h e situation o f a transistor operating i n free air—that i s , with n o special
Solution
a r r a n g e m e n t s for c o o l i n g . T h e heat dissipated i n t h e transistor j u n c t i o n will b e c o n d u c t e d
Since the peak positive current is 100 mA, the base current of Q can be as high as 2 mA. W e shall
a w a y from t h e j u n c t i o n to the transistor case, a n d from the case t o t h e surrounding environ
therefore select 7
ment. In a steady state i n w h i c h the transistor is dissipating P watts, t h e temperature rise of
N
B I A S
= 3 mA, thus providing the multiplier with a minimum current of 1 mA.
Under quiescent conditions (v = 0 and i = 0) the base current of Q can be neglected and all 0
of 7
B I A S
E
D
the j u n c t i o n relative t o the surrounding a m b i e n c e can b e expressed as
N
flows through the multiplier. W e now must decide on how this current (3 m A ) is to b e
Tj^T
A
divided between I
CX
= 0 P JA
(14.36)
D
and I . If w e select 7^ greater than 1 m A , the transistor will b e almost cut off R
at the positive peak of v . Therefore, w e shall select I = 0 . 5 mA, leaving 2.5 m A for I . 0
R
CX
T o obtain a quiescent current of 2 m A in the output transistors, V
BB
V
BB
=2 V
T
l n ^ l =
1.19 V
should b e
w h e r e 9 i s t h e t h e r m a l r e s i s t a n c e b e t w e e n j u n c t i o n a n d a m b i e n c e , having t h e units of degrees Celsius p e r watt. N o t e that 6 simply gives the rise in j u n c t i o n t e m p e r a t u r e over t h e ambient t e m p e r a t u r e for each watt of dissipated p o w e r . Since w e w i s h t o b e able to dissipate large a m o u n t s of p o w e r without raising the j u n c t i o n t e m p e r a t u r e a b o v e T , it is desirable to h a v e , for t h e t h e r m a l resistance 9 , as small a v a l u e as possible. For operation in free air, JA
JA
Jmax
JA
CHAPTER 14
OUTPUT STAGES A N D POWER
AMPLIFIERS
14.6
P O W E R BJTS
O b s e r v e that a s T a p p r o a c h e s T , the a l l o w a b l e p o w e r dissipation decreases; t h e l o w e r t h e r m a l gradient limits t h e a m o u n t of heat that c a n b e r e m o v e d from t h e j u n c t i o n . I n t h e e x t r e m e situation of T = T , n o p o w e r c a n b e dissipated b e c a u s e n o heat c a n b e r e m o v e d from the j u n c t i o n . A
Jmax
A
o TA
FIGURE 1 4 . 1 7 Electrical equivalent circuit of the thermalconduction process; Tj-TA = P &JAD
6
d e p e n d s primarily o n t h e t y p e of case i n w h i c h t h e transistor is p a c k a g e d . T h e value of
d
is usually specified o n t h e transistor d a t a sheet.
JA
JA
Jmax
A B I T is specified to have a m a x i m u m power dissipation P of 2 W at an ambient temperature T of 25°C, and a m a x i m u m junction temperature T , of 150°C. Find the following:
E q u a t i o n (14.36), w h i c h describes t h e t h e r m a l - c o n d u c t i o n p r o c e s s , is analogous t o O h m ' s l a w ; w h i c h describes t h e electrical-conduction p r o c e s s . I n this analogy, p o w e r dissi pation c o r r e s p o n d s t o current, t e m p e r a t u r e difference c o r r e s p o n d s t o voltage difference, and t h e r m a l resistance c o r r e s p o n d s to electrical resistance. T h u s , w e m a y represent t h e thermalc o n d u c t i o n p r o c e s s b y the electric circuit s h o w n i n F i g . 14.17.
M
A0
m a x
(a) T h e thermal resistance 6 . JA
(b) T h e m a x i m u m power that can be safely dissipated at an ambient temperature of 50°C. (c) The junction temperature if the device is operating at T = 25°C and is dissipating 1 W . A
14.6.3 Power Dissipation Versus Temperature T h e transistor manufacturer usually specifies t h e m a x i m u m j u n c t i o n t e m p e r a t u r e 7 / , the m a x i m u m p o w e r dissipation at a particular a m b i e n t t e m p e r a t u r e T (usually, 25°C), and t h e t h e r m a l resistance 9 . I n addition, a g r a p h such a s that s h o w n i n F i g . 14.18 is usually pro vided. T h e g r a p h simply states that for operation at a m b i e n t temperatures b e l o w 7/ , the device c a n safely dissipate t h e rated value of P watts. H o w e v e r , if the device is to b e oper ated at higher ambient temperatures, t h e m a x i m u m allowable p o w e r dissipation must b e d e r a t e d according t o t h e straight line s h o w n i n Fig. 14.18. T h e power-derating curve is a graphical representation of Eq. (14.36). Specifically, n o t e that if t h e a m b i e n t temperature is T a n d t h e p o w e r dissipation is at t h e m a x i m u m allowed (P ), then the junction temperature will b e r / m a x . Substituting these quantities in E q . (14.36) results in 7max
A0
I I
Solution (a)
e
/u\
p
(b)
^
(c)
7} = T +e P
= J™*~ ^ T
JA
=
T
1
5
0
-
2
5
= 62.5°CAV
JA
A0
_
^Jroax ~ TA
_ 150 — 5 0
* , ,,
r
D0
A0
~ A
JA
D
a
r =
i-«w
= ,25 + 62.5 x 1 = 8 7 . 5 ° C
m
Q
7}
=
m a x
- T
(14.37)
A0
14.6.4 Transistor Case and Heat Sink T h e t h e r m a l resistance b e t w e e n j u n c t i o n a n d a m b i e n c e , 6 , can b e e x p r e s s e d as JA
0jA=0 +e JC
w h i c h is t h e inverse of t h e slope of t h e p o w e r - d e r a t i n g straight line. A t an a m b i e n t tempera ture T , h i g h e r than T , t h e m a x i m u m a l l o w a b l e p o w e r dissipation P A
AQ
Dmm
from E q . (14.36) b y substituting T = T x
p
^Dmax k
/ m a x
c a n b e obtained
; thus,
w h e r e 0 is t h e t h e r m a l resistance b e t w e e n j u n c t i o n a n d transistor c a s e (package) a n d 8 is t h e t h e r m a l resistance b e t w e e n c a s e and a m b i e n c e . F o r a given transistor, 6 is fixed b y t h e d e v i c e design a n d p a c k a g i n g . T h e device manufacturer can r e d u c e 6 b y encapsulating t h e d e v i c e i n a relatively large metal case a n d placing t h e collector ( w h e r e m o s t of t h e heat is dissipated) i n direct contact with t h e case. M o s t h i g h - p o w e r transistors a r e p a c k a g e d in this fashion. F i g u r e 14.19 s h o w s a sketch of a typical p a c k a g e . JC
CA
]C
JC
T
=
(14.39)
CA
^/max ~ A
(14.38)
y
A l t h o u g h t h e circuit designer h a s n o control o v e r G (once a particular transistor h a s b e e n selected), t h e designer c a n considerably r e d u c e 9 b e l o w its free-air value (specified by t h e m a n u f a c t u r e r as part of 6 ). R e d u c t i o n of 0 c a n b e effected b y p r o v i d i n g m e a n s t o facilitate h e a t transfer from case to a m b i e n c e . A p o p u l a r a p p r o a c h is t o bolt t h e transistor t o the chassis or t o a n e x t e n d e d metal surface. S u c h a m e t a l surface t h e n functions a s a h e a t s i n k . H e a t is easily c o n d u c t e d from t h e transistor case t o t h e heat sink; that is, t h e t h e r m a l resistance 6 is usually very small. A l s o , heat is efficiently transferred (by c o n v e c t i o n a n d JC
CA
JA
CA
CS
FIGURE 1 4 . 1 8 Maximum allowable power dissipation versus ambient temperature for a BIT operated n free air. This is known as a "power-derating" curve.
FIGURE 1 4 . 1 9 The popular T 0 3 package for power transistors. The case is metal with a diameter of about 2.2 cm; the outside dimension of the "seating plane" is about 4 cm. The seating plane has two holes for screws to bolt it to a heat sink. The collector is electrically connected to the case. Therefore an electtically insulating but thermally conducting spacer is used between the transistor case and the "heat sink."
1251
1252
CHAPTER 1 4 O U T P U T S T A G E S A N D P O W E R
14.6
AMPLIFIERS
p o w e r dissipation at a case temperature ambient
temperature
ature T , T T T _= T c
±
±
I
T
c0
T
7}
c
co
(usually 2 5 ° C ) is m u c h greater than that at an
(usually 25 °C). If t h e d e v i c e c a n b e m a i n t a i n e d at a case t e m p e r
A0
< T<
T
P O W E R BJTS
m a x
, t h e n t h e m a x i m u m safe p o w e r d i s s i p a t i o n is o b t a i n e d w h e n
/max' •^/max T.
Dmax -
A B I T is specified to have r follows:
T
c
(14.42)
= 150°C and to b e capable of dissipating m a x i m u m power as
J m a x
40 W at T
c
= 25°C
2 Wat T
= 25°C
A
Above 25°C, the m a x i m u m power dissipation is to b e derated linearly with 9 9 = 62.5°C/W. Find the following:
JC
= 3.12°C/W and
JA
(a) T h e m a x i m u m power that can b e dissipated safely by this transistor w h e n operated in free air at T = 50°C. A
(b) T h e m a x i m u m power that can be dissipated safely by this transistor when operated at an ambient temperature of 50°C, but with a heat sink for which 9 = 0.5°C/W and 9 = 4 ° C / W . Find the temperature of the case'and of the heat sink. CS
SA
(c) The maximum power that can be dissipated safely if an infinite heat sink is used and T = 50°C. A
Solution FIGURE 1 4 . 2 1
(a)
M a x i m u m allowable power dissipation versus transistor-case temperature.
p Dmnx
r
_ ~
2}max 7,
TA
=
150-50
. ^ „j = 1-0 W
62.5
JA radiation) f r o m t h e h e a t sink to t h e a m b i e n c e , resulting i n a l o w t h e r m a l r e s i s t a n c e 9 . T h u s , SA
(b) With a heat sink, 8
if a h e a t sink is utilized, t h e c a s e - t o - a m b i e n c e t h e r m a l r e s i s t a n c e g i v e n b y e
CA
= e
c
8
s +
JA
becomes
(14.40)
SA
= 3.12 + 0.5 + 4 = 7.62°CAV
c a n b e s m a l l b e c a u s e its t w o c o m p o n e n t s c a n b e m a d e s m a l l b y t h e c h o i c e of a n appropriate 2
h e a t s i n k . F o r e x a m p l e , in very h i g h - p o w e r applications t h e h e a t sink is u s u a l l y equipped
' + 9f r + 9 c
JA
Thus,
w i t h fins that further facilitate cooling b y r a d i a t i o n a n d c o n v e c t i o n . T h e electrical a n a l o g of t h e t h e r m a l - c o n d u c t i o n p r o c e s s w h e n a h e a t sink is e m p l o y e d is
* W
=
= 13.1 W
s h o w n in F i g . 14.20, from w h i c h w e c a n w r i t e Tj-T
= P (6 +e +e )
A
D
JC
cs
SA
(14-41)
Figure 14.22 shows the thermal equivalent circuit With the various temperatures indicated! (c) A n infinite heat sink, if it existed, would cause the case temperature T to equal the ambient c
A s w e l l as specifying 9 , t h e d e v i c e m a n u f a c t u r e r u s u a l l y supplies a derating c u r v e for
temperature T . T h e infinite heat sink has 9
P
sink; nevertheless, this terminology is used b y some manufacturers to describe the power-derating
JC
A
D m a x
versus' t h e c a s e t e m p e r a t u r e , T . S u c h a c u r v e is s h o w n i n F i g . 1 4 . 2 1 . N o t e that the c
s l o p e of t h e p o w e r - d e r a t i n g s t r a i g h t l i n e i s -\I9 . JC
F o r a given transistor, the m a x i m u m
CA
= 0. Obviously, one cannot b u y an infinite heat
curve of Fig. 14.21. T h e abscissa is then labeled T and the curve is called "power dissipation A
versus ambient temperature with an infinite heat sink." For our example, with infinite heat sink, As noted earlier, the metal case of a power transistor is electrically connected to the collector. Thu electrically insulating material such as mica is usually placed between the metal case and the metal sink. Also, insulating bushings and washers are generally used in bolting the transistor to the heat s
D D m a x
_
"
T/max
9
TA _ l r
150 — 50
- ~3ÂT
:
~rx
=
3
2
W
C H A P T E R 14
1 2 5 4
OUTPUT STAGES A N D POWER
AMPLIFIERS
-oT,=
>e
/
c
=
3.12°C/W
,,
P= D
150° C
o T = 109°C C
: e „ = o.5°c/w
13.1 W |
,
oT = s
102.4°C
:e = 4°c/w S/4
- o L = 50°C j
FIGURE 1 4 . 2 2 Thermal equivalent circuit for Example 14.5. T h e a d v a n t a g e of u s i n g a heat sink is clearly evident from E x a m p l e 14.5: W i t h a heat
3. T h e s e c o n d - b r e a k d o w n limit. S e c o n d b r e a k d o w n is a p h e n o m e n o n that results
sink, t h e m a x i m u m allowable p o w e r dissipation increases f r o m 1.6 W t o 13.1 W . A l s o note
b e c a u s e current flow across t h e e m i t t e r - b a s e j u n c t i o n is n o t uniform. Rather, t h e cur
that a l t h o u g h t h e transistor c o n s i d e r e d c a n b e called a " 4 0 - W transistor," this level of p o w e r
r e n t density is greatest n e a r the p e r i p h e r y of t h e j u n c t i o n . This "current c r o w d i n g "
dissipation c a n n o t b e a c h i e v e d i n p r a c t i c e ; it w o u l d require a n infinite h e a t sink a n d an
g i v e s r i s e t o i n c r e a s e d localized p o w e r dissipation a n d h e n c e t e m p e r a t u r e r i s e (at
ambient temperature T < 25°C.
locations called h o t spots). Since a t e m p e r a t u r e rise c a u s e s an increase in current, a
A
l o c a l i z e d f o r m of t h e r m a l r u n a w a y c a n occur, leading to j u n c t i o n destruction. 4 . T h e collector-to-emitter b r e a k d o w n v o l t a g e , BV . T h e i n s t a n t a n e o u s v a l u e of v s h o u l d n e v e r b e a l l o w e d t o e x c e e d BV ; o t h e r w i s e , a v a l a n c h e b r e a k d o w n of t h e c o l l e c t o r - b a s e j u n c t i o n m a y o c c u r ( s e e Section 5.2.5). CE0
EXERCISE 14.10 T h e 2N6306 power transistor is specified t o have T
Jmm
T
CE
CE0
C
> 15 C
e= K
= 2(Xr
= 125 W for T < 25°C. For
Dm K
c
Finally, it s h o u l d b e m e n t i o n e d that l o g a r i t h m i c scales are u s u a l l y u s e d for i a n d leading t o an S O A b o u n d a r y that consists of straight lines.
1 4 ' C / W . If in a particular application this device is to dissipate D 0 W and operate at 0
an amWcit temperature of 25°C, find the m a x i m u m thermal resistance of the heat sink that must be used (i.e., 8 ). A s s u m e # SA
c s
v ,
c
CE
= 0.6°C/W. What is the case temperature, T l c
Ans. 1.5°C/W; 130°C
14.6.6 Parameter Values of Power Transistors O w i n g to t h e k large g e o m e t r y a n d h i g h operating currents, p o w e r transistors display typical p a r a m e t e r values that c a n b e quite different from t h o s e of small-signal transistors. T h e i m p o r t a n t differences a r e as follows:
14.6.5 The BJT Safe Operating Area In a d d i t i o n to specifying t h e m a x i m u m p o w e r d i s s i p a t i o n at different c a s e t e m p e r a t u r e s , p o w e r - t r a n s i s t o r m a n u f a c t u r e r s u s u a l l y p r o v i d e a p l o t of t h e b o u n d a r y of t h e safe operat ing area ( S O A ) in the i - v c
C E
p l a n e . T h e S O A specification t a k e s t h e f o r m illustrated b y
t h e s k e t c h i n F i g . 1 4 . 2 3 ; t h e f o l l o w i n g p a r a g r a p h n u m b e r s c o r r e s p o n d t o the b o u n d a r i e s on the sketch.
1. A t h i g h currents, t h e e x p o n e n t i a l i - v c
l
c -
1
S
B E
relationship exhibits a c o n s t a n t n = 2; that is,
e
2. B is l o w , typically 3 0 t o 80, b u t c a n b e as l o w as 5. H e r e , it is i m p o r t a n t t o note that B h a s a p o s i t i v e t e m p e r a t u r e coefficient. 3. A t h i g h c u r r e n t s , r b e c o m e s very small (a f e w o h m s ) a n d r b e c o m e s i m p o r t a n t (r is defined a n d e x p l a i n e d i n Section 5.8.4). n
1. T h e m a x i m u m allowable current /
C m a x
. E x c e e d i n g this current o n a c o n t i n u o u s basis
c a n result in melting the wires that b o n d t h e d e v i c e to t h e p a c k a g e terminals.
V
CE^C
— ^Dmax
(at T ).
For temperatures T
c0
c
> T, c0
the p o w e r - d e r a t i n g
d e s c r i b e d in Section 14.6.4 should b e u s e d to obtain t h e applicable Puma*
a n
curves
d thus
a
c o r r e s p o n d i n g l y l o w e r h y p e r b o l a . A l t h o u g h d i e o p e r a t i n g p o i n t c a n b e a l l o w e d to m o v e t e m p o r a r i l y a b o v e t h e h y p e r b o l a , t h e average allowed to exceed
P
.
DmlLK
p o w e r dissipation s h o u l d n o t b e
x
4 . f is l o w ( a f e w m e g a h e r t z ) , C , i s ' l a r g e ( h u n d r e d s of picofarads), a n d C larger. ( T h e s e p a r a m e t e r s are defined a n d explained in Section 5.8). T
2. T h e m a x i m u m p o w e r dissipation h y p e r b o l a . T h i s is t h e locus of t h e p o i n t s for w h i c h
x
;
K
is e v e n
5. I is l a r g e (a f e w tens of m i c r o a m p s ) and, as usual, d o u b l e s for every 10°C rise in temperature. CB0
6. BV
CE0
7. 7
C m a x
is typically 5 0 t o 1 0 0 V b u t c a n b e as h i g h as 5 0 0 V . is typically i n t h e a m p e r e r a n g e b u t c a n b e as h i g h as 1 0 0 A .
CHAPTER 14
OUTPUT STAGES A N D POWER
14.7
AMPLIFIERS
14.7
VARIATIONS O N THE CLASS AB
C O N F I G U R A T E
ijLÏ
p r o v i d e i n c r e a s e d o u t p u t driving capability. T h e latter a p p l i c a t i o n will b e discussed in t h e next section.
VARIATIONS ON THE CLASS AB CONFIGURATION
In this section, w e discuss a n u m b e r of circuit i m p r o v e m e n t s and protection techniques for
EXERCISE
the class A B output stage.
14.7.1 Use of Input Emitter Followers
14.11 (iVc.'t : Although e e , instructive, this exercise is rather long.ï Ç ^ s i d e r ^ ^ of R f r 1 « 4 w i t h * , = " • ' ^ F - ' J k Q S . = fl.=0fl, and V = 15 V. Let the transistors be matched with I — J . J / S 10 A„i-1, " t d S t e are the values used in the L H 0 0 2 manufactured by National Semtconductor. except . T, 1 1i 12 a there ) For t,v = 0 a n d / ? , = ^ , find the quiescent current m each ot the iour transis-
F i g u r e 14.24 s h o w s a class A B circuit b i a s e d using transistors Q and Q , w h i c h also funcx
cc
2
s
S
tion as e m i t t e r followers, t h u s p r o v i d i n g t h e circuit w i t h a h i g h input resistance. In effect, the circuit functions as a unity-gain buffer amplifier. Since all four transistors are usually m a t c h e d , the q u i e s c e n t current (vj = 0, R
= °°) in Q and Q is e q u a l to that in Q and Q .
L
3
4
x
2
Resistors R and R are usually very small and a r e i n c l u d e d to c o m p e n s a t e for p o s s i b l e mis3
4
-
m a t c h e s b e t w e e n Q and Q and to g u a r d against the possibility of t h e r m a l r u n a w a y due to 3
! l " , ! o s 7 m A ' 0 V fblfor TA = + 1 0 V: 0.88 mA, 4.87 m A , 1.95 mA. 1.95 m A . - 9 . 9 8 V ; for i ^ - 1 0 V :
4
t e m p e r a t u r e differences b e t w e e n t h e input- and output-stage transistors. T h e latter point can
- + 9 . 8 6 V; fort-; = - 1 0 V : 4.87 m A , 0.38 mA, 0.02 mA, 100 m A . - 9 . 8 6 V
b e appreciated by noting that an increase in the current of, say, Q causes an increase in the 3
v o l t a g e d r o p across R
3
and a c o r r e s p o n d i n g d e c r e a s e in V . T h u s R BE3
f e e d b a c k that h e l p s stabilize t h e current t h r o u g h
3
p r o v i d e s negative
Q. 3
B e c a u s e the circuit of Fig. 14.24 requires high-quality pnp transistors, it is not suitable for i m p l e m e n t a t i o n in c o n v e n t i o n a l m o n o l i t h i c I C t e c h n o l o g y . H o w e v e r , excellent results h a v e been obtained with this circuit i m p l e m e n t e d in h y b r i d thick-film t e c h n o l o g y ( W o n g and S h e r w i n , 1979). This t e c h n o l o g y p e r m i t s c o m p o n e n t t r i m m i n g , for instance, to minim i z e t h e o u t p u t offset voltage. T h e circuit c a n b e u s e d a l o n e o r together w i t h a n o p a m p to
14.7.2 Use of Compound Devices T o i n c r e a s e t h e c u r r e n t gain of t h e output-stage transistors, a n d t h u s r e d u c e the r e q u i r e d b a s e current drive, the D a r l i n g t o n configuration s h o w n in F i g . 14.25 is frequently used to r e p l a c e the npn transistor of t h e class A B stage. T h e D a r l i n g t o n c o n f i g u r a t i o n (Section 6.11.2) is equivalent t o a single npn transistor h a v i n g /3 = /3 /3 , b u t a l m o s t t w i c e the v a l u e of V . 1
2
BE
T h e D a r l i n g t o n configuration can b e also u s e d for pnp transistors, and this is i n d e e d done in discrete-circuit design. In I C design, h o w e v e r , the l a c k of good-quality pnp transistors p r o m p t e d the u s e of the alternative c o m p o u n d c o n f i g u r a t i o n s h o w n in Fig. 14.26. T h i s c o m p o u n d d e v i c e is e q u i v a l e n t to a single pnp transistor h a v i n g ¡5 — J5 [$2- W h e n fabricated with standard I C t e c h n o l o g y , Q is usually a lateral pnp h a v i n g a l o w ¡5 (fl = 5 - 10) and p o o r high-frequency r e s p o n s e (f — 5 M H z ) ; see A p p e n d i x A . T h e c o m p o u n d device, although it has a relatively high e q u i v a l e n t ¡5, still suffers from a p o o r h i g h - f r e q u e n c y r e s p o n s e . It also suffers from a n o t h e r p r o b l e m : T h e feedback l o o p f o r m e d b y Q a n d Q is p r o n e to highfrequency oscillations (with frequency n e a r / of the pnp device, i.e., about 5 M H z ) . M e t h o d s exist for p r e v e n t i n g such oscillations. T h e subject of f e e d b a c k - a m p l i f i e r stability w a s studied in C h a p t e r 8.
+V
RT
X
4 4 4
x
T
x
r
R
3
-V
V,
O-
+
IL
CC
-ov
0
C
C
?
V
CC
BoBo-
Ô
-v ce f
E
F I G U R E 1 4 . 2 4 A class A B output stage w i t h an input buffer. In addition to providing a high input resistance, the buffer transistors Q and Q bias the output transistors Q and Q . x
2
3
4
FIGURE 1 4 . 2 5
The Darlington configuration.
4
2
1257
1258
:... •.
CHAPTER 14
O U T P U T STAGES A N D P O W E R A M P L I F I E R S
14.7
V A R I A T I O N S O N T H E CLASS AB C O N F I G U R A T I O N
"'i':
1
E
E
o
o
14.12 I a.) Refer to Fig. 1.4:26. S l u w llial. I'm the c o m p o r t e pnp transistor.
1 Bo-
Bo-
ß~
ßißi
4'
Hence show that
and thus the transistor has an effective scale current
o
C FIGURE 14.26
The compound-pnp configuration.
where / „ , is the saturation current of the pnp transistor Q . t
(b) For B = 20, B = 50, J = 1 0 " ; ;... w hen i = 100 m A. Lei // - I. p
N
SH
1 4
A , find the effective current gain of the compound device and its
c
T o illustrate the application of the Darlington configuration and of the c o m p o u n d pnp, w e s h o w in Fig. 14.27 an output stage utilizing b o t h . Class A B biasing is achieved using a multiplier. N o t e that the D a r l i n g t o n npn a d d s o n e m o r e V
BE
d r o p , and thus t h e V
BE
BE
multiplier
is required to p r o v i d e a bias v o l t a g e of about 2 V . T h e design of this class A B stage is inves tigated in P r o b l e m 14.39.
+
Ans. -b) 1000; 0.651 V
V
14.7.3 Short-Circuit Protection Figure 14.28 shows a class A B output stage equipped with protection against the effect of short-circuiting the output while the stage is sourcing current. T h e large current that flows through Q in the event of a short circuit will develop a voltage d r o p across R of sufficient
V
x
E1
C(
-oVo
R,
ov
0
-V
RI
FIGURE 1 4 . 2 7
A c)ass A B output stage utilizing a Darlington npn and a compound pnp. Biasing is
obtained using aV
BE
multiplier.
F I G U R E 1 4 . 2 8 A class A B output stage with short-circuit protection. The protection circuit shown oper ates in the event of an output short circuit while v is positive. 0
1 2 5 9
1
CHAPTER 14
260
OUTPUT STAGES A N D POWER
14.8
AMPLIFIERS
value t o turn Q on. T h e collector of Q will then conduct m o s t of the current 7 , robbing Q of its b a s e drive. T h e current through Q will thus b e reduced to a safe operating level. T h i s m e t h o d of short-circuit protection is effective i n ensuring d e v i c e safety, b u t it h a s t h e d i s a d v a n t a g e that u n d e r n o r m a l operation about 0.5 V d r o p m i g h t appear across each R . T h i s m e a n s that t h e v o l t a g e s w i n g at t h e output will b e r e d u c e d b y that m u c h , in each direc tion. O n t h e other hand, t h e inclusion of emitter resistors p r o v i d e s t h e additional benefit of protecting t h e o u t p u t transistors against t h e r m a l r u n a w a y . 5
5
B I A S
14.8
l
IC POWER
AMPLIFIERS
IC POWER AMPLIFIERS
x
A variety of I C p o w e r amplifiers are available. M o s t consist of a h i g h - g a i n small-signal amplifier followed b y a class A B output stage. S o m e h a v e overall n e g a t i v e feedback already applied, resulting in a fixed closed-loop voltage gain. Others d o n o t h a v e on-chip feedback and a r e , in effect, o p a m p s with large o u t p u t - p o w e r capability. In fact, t h e output currentdriving capability of a n y general-purpose o p a m p c a n b e increased b y cascading it with a class B or class A B output stage a n d applying overall n e g a t i v e feedback. T h e additional out put stage c a n b e either a discrete circuit o r a h y b r i d I C such as t h e buffer discussed i n t h e p r e c e d i n g section. In' t h e following w e discuss s o m e p o w e r amplifier e x a m p l e s .
E
causes & t c . t u r n e d absorb •dl 2 m A when ihe output current being sourced reaches 1 5 0 m A . F o r Q , I - 1 0 A and n I. it tne n S m d p e a k output current is 100 m A . find the voltage drop across R and the collector current
14.8.1 A Fixed-Gain IC Power Amplifier
D14.13 In the circuit of Fig. 14.28 let / B I A S = 2 mA. Find the v ^ e o ^ h a t
s
s
n
of
ih.
Ans. 4.3
O u r first e x a m p l e is t h e L M 3 8 0 (a p r o d u c t of National S e m i c o n d u c t o r Corporation), w h i c h is a fixed-gain m o n o l i t h i c p o w e r amplifier. A simplified v e r s i o n of t h e internal circuit of t h e amplifier is s h o w n in Fig. 14.30. T h e circuit consists of an input differential amplifier utiliz ing <2i a n d Q as emitter followers for input buffering, a n d Q a n d Q as a differential pair with a n emitter resistor R . T h e t w o resistors R a n d R p r o v i d e dc paths to g r o u n d for t h e b a s e currents of Q a n d Q , thus enabling t h e i n p u t signal source t o b e capacitively c o u p l e d to either of the t w o input terminals. 3
LI; 430 mV; 0.3 ,uA
2
3
3
x
14.7.4 Thermal Shutdown In addition t o short-circuit protection, m o s t I C p o w e r amplifiers are usually e q u i p p e d with a circuit that senses t h e t e m p e r a t u r e of t h e c h i p a n d turns o n a transistor i n t h e event that t h e t e m p e r a t u r e e x c e e d s a safe preset value. T h e t u r n e d - o n transistor is c o n n e c t e d i n such a way that it absorbs t h e bias current of the amplifier, thus virtually shutting d o w n its operation. F i g u r e 14.29 s h o w s a t h e r m a l - s h u t d o w n circuit. H e r e , t r a n s i s t o r Q i s n o r m a l l y off. A s
4
4
5
2
T h e differential amplifier transistors Q and Q are biased b y t w o separate direct currents: Q is biased b y a current from the dc supply V through the diode-connected transistor Q , and resistor R ; Q is biased b y a dc current from the output terminal through R . Under quiescent conditions (i.e., with n o input signal applied) the t w o bias currents will b e equal, and the current through and t h e voltage across R will b e zero. F o r the emitter current of Q w e can write 3
4
3
s
x
10
4
2
3
3
2
t h e c h i p t e m p e r a t u r e rises, t h e c o m b i n a t i o n of t h e p o s i t i v e t e m p e r a t u r e coefficient of zener d i o d e Z a n d t h e n e g a t i v e t e m p e r a t u r e coefficient of V x
BEl
„ , s ~ VEBW ~~ VEB3 ~ VEBI
c a u s e s t h e v o l t a g e at the
e m i t t e r of Q to rise. T h i s i n turn r a i s e s t h e v o l t a g e at t h e b a s e of Q t o t h e p o i n t at w h i c h x
j
y
2
w h e r e w e h a v e n e g l e c t e d t h e small d c voltage drop across R . A s s u m i n g , for simplicity, all V t o b e equal, 4
Q turns on. 2
EB
h
V -3V
=
S
EB
(
1
4
4
3
)
Ri F o r t h e emitter current of Q w e h a v e 4
4 R,
h
C
Vp ~
VEB4
~
V B2
Ri
E
(14.44)
V -2V 0
EB
R,
4
w h e r e V is t h e d c v o l t a g e at t h e output and w e h a v e neglected t h e small d r o p across R . E q u a t i n g I a n d I a n d u s i n g t h e fact that R = 2R results in 0
5
3
4
x
2
VO = \VS + \VEB
(14-45)
T h u s t h e o u t p u t is biased at approximately half t h e p o w e r - s u p p l y voltage, as desired for m a x i m u m o u t p u t v o l t a g e s w i n g . A n important feature is t h e d c feedback from t h e output t o
3
t Vc
=
FIGURE 1 4 . 2 9 Thermal-shutdown circuit.
The main objective of showing this circuit is to point out some interesting design features. The circuit is not a detailed schematic diagram of what is actually on the chip.
1 2 6 2
Y;
CHAPTER 14
O U T P U T STAGES A N D POWER AMPLIFIERS
14.8
IC P O W E R A M P L I F I E R S
£*J
External bypass
FIGURE 1 4 . 3 1 Small-signal analysis of the circuit in Fig. 14.30. The circled numbers indicate the order of the analysis steps. FIGURE 1 4 . 3 0 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semiconductor Corporation.)
t e r m i n a l . T h e order o f t h e analysis steps is indicated by the circled numbers. Note that since the i n p u t differential a m p l i f i e r h a s a relatively large resistance, R , in t h e emitter circuit, m o s t of t h e a p p l i e d i n p u t v o l t a g e appears across R . In other w o r d s , t h e signal voltages across the e m i t t e r - b a s e j u n c t i o n s of Q Q , Q , and Q are small in comparison to the voltage across R . A c c o r d i n g l y , t h e v o l t a g e gain c a n b e found b y writing a n o d e equation at the collector of Q : 3
t h e emitter of Q , t h r o u g h R . This d c f e e d b a c k acts to stabilize the output d c bias voltage at the value i n E q . (14.45). Qualitatively, the d c feedback functions as follows: If for s o m e rea son V i n c r e a s e s , a c o r r e s p o n d i n g current i n c r e m e n t will flow t h r o u g h R a n d into the emit ter of Q . T h u s the collector current of Q increases, resulting in a positive i n c r e m e n t in the voltage at t h e b a s e of Q . This, in turn, causes t h e collector current of Q to increase, thus b r i n g i n g d o w n t h e v o l t a g e at t h e b a s e of j 2 a n d h e n c e V . 4
2
0
2
4
3
u
2
3
4
3
6
4
l2
12
7
C o n t i n u i n g with the description o f the circuit in F i g . 14.30, w e o b s e r v e that the differen tial amplifier (Q , Q ) h a s a current mirror l o a d c o m p o s e d of Q and Q (refer to Section 7.5.5 for a discussion of active loads). T h e single-ended output v o l t a g e signal of t h e first stage appears at t h e collector of Q and thus is applied to t h e b a s e of t h e second-stage c o m m o n emitter amplifier Q . Transistor Q is b i a s e d b y the constant-current source Q , w h i c h also acts as its active load. In actual operation, h o w e v e r , the load of Q will b e d o m i n a t e d b y the reflected resistance d u e to R . Capacitor C provides frequency compensation (see Chapter 8). 3
R
3
0
4
5
2
R
3
which yields
6
2e v,
6
12
R
12
2*2
-50
Y/V
u
l2
L
T h e o u t p u t stage is class A B , utilizing a c o m p o u n d pnp transistor (g a n d Q ). Negative feedback is applied from the output to the emitter of Q via resistor R . T o find the closed-loop gain consider the small-signal equivalent circuit s h o w n in F i g . 14.31. Here, w e h a v e replaced the s e c o n d - s t a g e c o m m o n - e m i t t e r amplifier a n d the output stage with a n inverting amplifier b l o c k w i t h gain A. W e shall a s s u m e that t h e amplifier A h a s high gain and h i g h input resis t a n c e , a n d thus t h e input signal current into A is negligibly small. U n d e r this assumption, Fig. 14.31 s h o w s the analysis details with an input signal v applied to the inverting input 8
4
2
t
EXERCISE
9
14.14 D e n o t i n g t h e total resistance between die collector of Q and ground by R, show, using Fi< b
I - i A' which reduces to (-2R,/R ) 3
\R\
under the condition that AR >
I I , that
1 2 6 3
1 2 6 4
CHAPTER 14
O U T P U T STAGES A N D POWER
14.8
AMPLIFIERS
IC P O W E R AMPLIFIERS
+ V, r
3.5 22 3.0 20 V £
2.5 18 V
o '3
2.0
'•o
1.5
—.—
16 V
V " ' \ ' 3 % d istoi lion
14 V
o
level
1? V ,
1.0
i
i
\10< Vc distorti on to 'el
*
0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output power (W)
F I G U R E 1 4 . 3 2 Power dissipation (P ) versus output power ( P ) f o r the L M 3 8 0 with R =8L~l. L
D
National Semiconductor
(Courtesy
L
Corporation.)
A s w a s d e m o n s t r a t e d in C h a p t e r 8, o n e of t h e a d v a n t a g e s of negative feedback is the r e d u c t i o n of n o n l i n e a r distortion. This is t h e case in t h e circuit of t h e L M 3 8 0 . T h e L M 3 8 0 is d e s i g n e d to operate from a single s u p p l y V in t h e r a n g e of 12 V to 2 2 V . s
T h e selection of supply voltage depends on the value of R and the required output p o w e r P . L
L
T h e m a n u f a c t u r e r s u p p l i e s c u r v e s for t h e d e v i c e p o w e r d i s s i p a t i o n v e r s u s o u t p u t p o w e r for a given load resistance a n d various supply voltages. O n e such set of curves for R = 8 Q. L
is s h o w n in Fig. 14.32. N o t e t h e similarity to the class B p o w e r dissipation curve of Fig. 14.8. In fact, t h e r e a d e r c a n easily verify that t h e l o c a t i o n a n d v a l u e of t h e p e a k s of t h e curves in F i g . 14.32 a r e accurately predicted b y E q s . (14.20) a n d (14.21), respectively (where y
cc
= ly ). s
Structure o f a power op amp. The circuit consists of an op amp followed by a class A B
FIGURE 1 4 . 3 3
buffer similar to that discussed i n Section 14.7.1. The output current capability of the buffer, consisting of a
Qi> 22> Qi> n d <2 , is further boosted by Q and Q . 4
5
6
T h e line labeled " 3 % distortion l e v e l " in F i g . 14.32 is t h e locus of t h e points on
the v a r i o u s c u r v e s at w h i c h t h e distortion ( T H D ) r e a c h e s 3 % . A T H D of 3 % represents t h e
14.8.2 Power Op Amps
onset of p e a k clipping d u e t o output-transistor saturation.
F i g u r e 14.33 s h o w s t h e general structure of a p o w e r op a m p . It consists of a l o w - p o w e r o p amp*
T h e manufacturer also supplies curves for m a x i m u m p o w e r dissipation versus temperature (derating curves) similar to those discussed i n Section 14.6 for discrete p o w e r transistors.
followed b y a class A B buffer similar to that discussed in Section 14.7.1. T h e buffer consists of transistors Q
u
Q , Q , and Q , with bias resistors i?, and R and emitter degeneration resistors R 2
3
4
2
5
and R . T h e buffer supplies the required load current until t h e current increases to t h e point that 6
t h e v o l t a g e d r o p across R (in the current-sourcing m o d e ) b e c o m e s sufficiently large t o turn
EXERCISES
3
Q on. Transistor Q then supplies the additional load current required. In the cun-ent-sinking 5
;
14.15 T h e manufacturer specifies that for ambient temperatures below 25°C the LIV1380 can dissipate a maxi; S f i 5 * ? i n i i m of 3.6 W . Thi<; is obtained under the condition that its dual-in-line package be soldered onlo a . printed-circuit board in close thermal contact with 6 square inches of 2-ounce copper foil. Above T = 25°C, the thermal resistance is B = 35°CAV. T is specified to b e 150°C. Find the maximum power , , , dissipationpossible if the ambient temperature is,, to b e 5 0 ° C . , . . ,,„, A
M
5
m o d e , Q supplies t h e load current until sufficient voltage develops across R to turn Q on. 4
4
6
T h e n , Q sinks t h e additional load current. T h u s the stage formed b y Q and Q$ acts as a c u r r e n t 6
5
b o o s t e r . T h e p o w e r op a m p is intended t o b e used with negative feedback in the usual closedloop configurations. A circuit based o n t h e structure of Fig. 14.33 is commercially available
Jmax
from N a t i o n a l Semiconductor as L H 0 1 0 1 . This op a m p is capable of providing a continuous output current of 2 A , and with appropriate heat sinking can provide 4 0 W of output p o w e r
Ans. 2.9 W 014; 16 If is required to use the LM380 to drive an 8-£2 loudspeaker. Use the curves of Fig. 14.32 to determine,the/, maximum power supply possible while limiting the maximum power dissipation to the 2.9 W determined in Exercise 14.15. If for this application a 3 % T H D i s allowed, find P and the peak-to-pcak output voltage:
( W o n g a n d Johnson, 1981). T h e L H 0 1 0 1 is fabricated using hybrid thick-film technology.
14.8.3 The Bridge Amplifier
L
Ans. 2<) \ : 4.2 W: Id. I \
W e c o n c l u d e this section with a discussion of a circuit configuration that is p o p u l a r in h i g h p o w e r a p p l i c a t i o n s . T h i s is t h e b r i d g e amplifier configuration s h o w n i n Fig. 14.34 utilizing
1 2 6 5
CHAPTER
14
14.9
O U T P U T STAGES A N D POWER AMPLIFIERS
M O S POWER TRANSISTORS
Source
7
Current flow FIGURE 1 4 . 3 4
o Drain
The bridge amplifier configuration. FIGURE 1 4 . 3 5 Double-diffused vertical MOS transistor (DMOS).
two power op amps, Aj and A . While A 2
with a gain K= 1 + (R /R ), 2
4
A is c o n n e c t e d as a n inverting amplifier with a gain of equal
l
m a g n i t u d e K - R /R . 3
x
is c o n n e c t e d in t h e noninverting configuration
2
o p e r a t i n g in t h e s a t u r a t i o n r e g i o n is g i v e n b y
T h e l o a d R is/floating a n d is c o n n e c t e d b e t w e e n t h e output termi L
i
nals of t h e t w o o p a m p s .
D
=
)(*
G 5
- y,f
(14-46)
If v, is a sinusoid with a m p l i t u d e % t h e v o l t a g e s w i n g at t h e output of e a c h o p a m p will b e ±KVi,
a n d that across t h e l o a d will b e ±2KVi.
T h u s , w i t h o p a m p s operated from ± 1 5 - V
supplies a n d c a p a b l e of providing, say a ± 1 2 - V o u t p u t s w i n g , an output s w i n g of ± 2 4 V is obtained across t h e l o a d of the bridge amplifier. In designing b r i d g e amplifiers, n o t e should b e taken of t h e fact that t h e p e a k current d r a w n from each o p a m p is 2KV~ /R . i
L
T h i s effect c a n b e t a k e n into account b y considering
the load seen b y e a c h o p a m p (to g r o u n d ) to b e
R /2. L
EXERCISE • ••
—
:
:
„
m u m m
mil
11 I inliiiiil liininiTililnTBrrrrii—ntiMTTi
14.17 Consider lhc circuii of H g . I 4..U n u l l R , - R ~ In 111. A'_. -- > k U R . •- 15 111. and R - * 11. Find llic
It follows that to increase t h e current capability of the M O S F E T , its width W should b e m a d e large a n d its c h a n n e l length L should b e m a d e as small as possible. Unfortunately, h o w e v e r , r e d u c i n g t h e c h a n n e l length of the standard M O S F E T structure results i n a drastic reduction i n its b r e a k d o w n voltage. Specifically, t h e depletion r e g i o n of t h e reverse-biased b o d y - t o - d r a i n j u n c t i o n spreads into t h e short channel, resulting in b r e a k d o w n at a relatively l o w voltage. T h u s t h e resulting device w o u l d n o t b e capable of h a n d l i n g t h e h i g h v o l t a g e s typical of p o w e r - t r a n s i s t o r applications. F o r this reason, n e w structures h a d t o b e f o u n d for fabricating short-channel ( 1 - to 2-/mi) M O S F E T s with high b r e a k d o w n voltages. A t the present time t h e m o s t popular structure for a p o w e r M O S F E T is the double-diffused or D M O S transistor s h o w n in Fig. 14.35. A s indicated, the device is fabricated on a lightly d o p e d n-type substrate with a heavily doped region at the b o t t o m for t h e drain contact. T w o diffusions are employed, o n e to form the p-type body region and another to form the re-type source region. T h e D M O S device operates as follows. Application of a positive gate voltage, v , greater than the threshold voltage V„ induces a lateral re channel i n t h e p - t y p e b o d y region under neath t h e g a t e o x i d e . T h e r e s u l t i n g c h a n n e l is short; its l e n g t h is d e n o t e d L i n F i g . 1 4 . 3 5 . C u r r e n t is then c o n d u c t e d b y electrons from t h e source m o v i n g t h r o u g h t h e resulting short c h a n n e l to t h e substrate a n d then vertically d o w n t h e substrate to t h e drain. T h i s should b e contrasted with t h e lateral current flow in t h e standard small-signal M O S F E T structure (Chapter 4 ) . 4
voltage gain and the input resistance. The power supply used is ±18 V. If v, is a 20-V peak-to-peak sine wave, what is the peak-to-peak output voltage? What is the peak load current? W h a t is the load power? Ans. 3 V/V; 10 k Q : 60 V: 3.^5 V >d.25 \ \
14.9
MOS POWER TRANSISTORS
Although, thus far in this chapter w e h a v e dealt exclusively with B I T circuits there exist M O S p o w e r transistors w i t h specifications that are quite competitive with those of B J T s . In this section w e consider t h e structure, characteristics, a n d application of p o w e r M O S F E T s .
14.9.1 Structure of the Power MOSFET
GS
E v e n t h o u g h the D M O S transistor has a short channel, its b r e a k d o w n voltage c a n b e very h i g h (as h i g h as 6 0 0 V ) . T h i s is b e c a u s e t h e depletion region b e t w e e n t h e substrate a n d t h e b o d y extends mostly i n the lightly d o p e d substrate a n d does n o t spread into the channel. T h e result is a M O S transistor that simultaneously h a s a high current capability (50 A is possible)
T h e M O S F E T structure studied i n C h a p t e r 4 ( F i g . 4 . 1 ) is n o t suitable for h i g h - p o w e r applications. T o appreciate this fact, recall that the drain current of an re-channel M O S F E T
4
See Appendix A for a description of the IC fabrication process.
CHAPTER 14
O U T P U T STAGES A N D POWER AMPLIFIERS
14.9
as well as t h e h i g h b r e a k d o w n voltage j u s t m e n t i o n e d . Finally, w e n o t e that t h e vertical struc ture of the device provides efficient utilization of the silicon area.
i
D
M O S POWER TRANSISTORS
(A) |
A n earlier structure used for p o w e r M O S transistors deserves mention. This is the V-groove M O S device [see Severns (1984)]. Although still in use, the V - g r o o v e M O S F E T has lost appli cation ground to the vertical D M O S structure of Fig. 14.35, except possibly for high-frequency applications. B e c a u s e of space limitations, w e shall not describe the V-groove M O S F E T .
14.9.2 Characteristics of Power MOSFETs In spite of their radically different structure, p o w e r M O S F E T s exhibit characteristics that are quite similar to t h o s e of the small-signal M O S F E T s studied in Chapter 4 . I m p o r t a n t dif ferences exist, h o w e v e r , a n d these are discussed next. ; P o w e r M O S F E T s h a v e threshold voltages i n the r a n g e of 2 V to 4 V . In saturation, the drain current is related to v b y the square-law characteristic of E q . (14.46). H o w e v e r , as s h o w n in F i g . 14.36, the i -v characteristic b e c o m e s linear for larger values of v : T h e linear portion of t h e characteristic occurs as a result of the h i g h electric field along t h e short c h a n n e l , causing t h e velocity of c h a r g e carriers to r e a c h a n u p p e r limit, a p h e n o m e n o n k n o w n as velocity s a t u r a t i o n . T h e drain current is t h e n g i y e n b y GS
D
GS
GS
i
D
= \C WU Jv -%) 0X
s
GS
(14.47)
6
w h e r e £7 is the saturated velocity value ( 5 x 1 0 c m / s for electrons i n silicon). T h e linear i -v r e l a t i o n s h i p i m p l i e s a constant g in the velocity-saturation region. It is interesting to n o t e that g is proportional to W, w h i c h is usually large for p o w e r devices; thus p o w e r M O S F E T s exhibit relatively h i g h t r a n s c o n d u c t a n c e values.
FIGURE 1 4 . 3 7 The i -v characteristic curve of a power MOS transistor (ERF 630, Siliconix) at case temperatures of-55°C, +25°C, and +125°C. (Courtesy Siliconix Inc.)
T h e i -v characteristic s h o w n in F i g . 14.36 includes a s e g m e n t labeled "subthreshold." T h o u g h of little significance for p o w e r devices, the subthreshold region of operation is of interest in v e r y - l o w - p o w e r applications (see Section 4.1.9).
14.9.3 Temperature Effects
sat
D
GS
m
D
GS
m
D
GS
Of considerable interest in the design of M O S p o w e r circuits is the variation of the M O S F E T characteristics with temperature, illustrated in Fig. 14.37. Observe titat there is a value of v (in the r a n g e of 4 V to 6 V for most power M O S F E T s ) at which the temperature coefficient of i is zero. A t higher values of v , i exhibits a negative temperature coefficient. This is a significant property: It implies that a M O S F E T operating beyond the zero-temperature-coefficient point does not suffer from the possibility of thermal runaway. This is not the case, however, at l o w currents (i.e., l o w e r than the zero-temperature-coefficient point). In the (relatively) low-current region, the temperature coefficient of i is positive, and the p o w e r M O S F E T can easily suffer thermal r u n a w a y (with unhappy consequences). Since class A B output stages are biased at l o w currents, m e a n s m u s t b e provided to guard against thermal runaway. GS
D
GS
D
D
T h e r e a s o n for t h e p o s i t i v e t e m p e r a t u r e coefficient of i at l o w c u r r e n t s is that v = (%s V,) is relatively l o w , a n d the t e m p e r a t u r e d e p e n d e n c e is d o m i n a t e d b y the n e g a t i v e t e m p e r a t u r e coefficient of V- (in the r a n g e of - 3 m V / ° C to - 6 m V / ° C ) w h i c h causes v to rise w i t h t e m p e r a t u r e . D
o v
_
t
o v
14.9.4 Comparison with BJTs
FIGURE 1 4 . 3 6 Typical i -v D
GS
characteristic for a power MOSFET.
T h e p o w e r M O S F E T does not suffer from second breakdown, which limits the safe operating area of B J T s . A l s o , p o w e r M O S F E T s d o n o t require t h e large d c base-drive currents of p o w e r B J T s . Note, however, that the driver stage in a M O S p o w e r amplifier should b e capable of s u p p l y i n g sufficient current to c h a r g e a n d discharge t h e M O S F E T ' s large a n d nonlinear input c a p a c i t a n c e i n t h e t i m e allotted. Finally, the p o w e r M O S F E T features, in general, a
CHAPTER 14
OUTPUT STAGES AND POWER
AMPLIFIERS
14.10
SPICE SIMULATION EXAMPLE
^"i
of the output M O S F E T s . In this w a y the quiescent current of the output transistors can be stabilized against t e m p e r a t u r e variations. Analytically, V is g i v e n b y
higher speed of operation than the p o w e r B J T . This m a k e s M O S p o w e r transistors especially suited to switching applications—for instance, in m o t o r - c o n t r o l circuits.
GG
14.9.5 A Class AB Output Stage Utilizing MOSFETs
R-. GC
A s an application of p o w e r M O S F E T s , w e s h o w in F i g . 14.38 a class A B output stage utilizing a pair of c o m p l e m e n t a r y M O S F E T s and e m p l o y i n g B J T s for biasing and in t h e driver
W
+ [ 1 + R-^ | "BE5 V „ - 4 V"BE ,
BE6
Ré
(14.48)
R
Since V is t h e r m a l l y c o u p l e d to the output devices w h i l e the other B J T s r e m a i n at constant t e m p e r a t u r e , w e h a v e BE6
stage. T h e latter consists of c o m p l e m e n t a r y D a r l i n g t o n emitter followers f o r m e d b y through g
4
Q
x
and h a s t h e l o w output resistance n e c e s s a r y for driving t h e output M O S F E T s at
high s p e e d s . Of special interest in t h e circuit of F i g . 14.38 is t h e bias circuit utilizing two V multipliers f o r m e d b y Q and Q and their associated resistors. Transistor Q is placed in direct t h e r m a l c o n t a c t w i t h t h e output transistors; this is a c h i e v e d by simply m o u n t i n g Q on their c o m m o n heat sink. T h u s , b y the appropriate c h o i c e of t h e V multiplication factor of g , the bias v o l t a g e V ( b e t w e e n t h e gates of t h e output transistors) c a n b e m a d e to decrease w i t h t e m p e r a t u r e at t h e s a m e rate as that of the s u m of the threshold voltages (V +\V \)
dT
BE
5
6
6
Rj
(14.49)
dT
w h i c h is t h e relationship n e e d e d to d e t e r m i n e R /R so that dV /dT = d(V + \ V \)/dT. T h e other V multiplier is then adjusted to yield t h e v a l u e of V , required for the desired quiescent current in Q a n d Q . 3
6
A
BE
6
BE
{
GG
tN
tP
GG
N
P
GG
m
tP
EXERCISES + Vcc 14.18 For t h e c i r c u i t in Fig. I -1.3S. J in J t h e r a t i o R
R t h a t pto\ i d c - i c i n p c r a t i i t c M u b i l i / a l i o n o f i h c current in Q and Q . Assume that |V,| changes at - 3 mV/°C and that dV /dT = - 2 mV/°C. N
;/
P
quiesccni
BE
|f|g;|l|2^^ 14.19 Foi i h c c i r c u i t in f i g . I 4.3S a - M i i n c d i a l I h c IJ.I \ \ h a v e a n o m i n a l \ .,, o l d . ~ V and that i h c M O S F E I *
have |V,: = 3 V and LL C„ {\V/L) H
X
in I h c o u t p u t M a g e a n i l 2 " i n \ A'
A'
= 2A/V". It is required to establish a quiescent current of 100 m A in the
d r i \ e r -i.igc. I ind
\.,
. \\„
. R. a n d
A',
R . L'sc the \ a l u c ol
l o u i k l in l : \ c i v i \ e I 4. IS.
Ans. 3.32 Y: h.ft4 \ : - 2 11.
• -. 14.10
SPICE SIMULATION EXAMPLE
W e conclude this chapter b y presenting an e x a m p l e that illustrates the u s e of S P I C E in the analysis of output circuits.
CLASS B OUTPUT STAGE W c investigate the operation of the class B output stage whose Capture schematic is shown in b i g . 14.39. For the power transistors, we use the discrete BJTs M J E 2 4 3 and MJE253 (from O N Semiconductor) which are rated for a m a x i m u m continuous collector current 7 = 4 A and a d m u m collector-emitter voltage of V £- ax = 100 V. To permit comparison with the hand analysis . .formed in Example 14.1, w e use, in the simulation, component and voltage values identical 5
C m a x
C
m
r
FIGURE 1 4 . 3 8 A class AB amplifier with MOS output transistors and BJT drivers. Resistor R is adjusted to provide temperature compensation while R is adjusted to yield the desired value of quiescent current in the output transistors. Resistors R are used to suppress parasitic oscillations at high frequencies. Typically, 3
T
G
R
G
=
too
a.
In PSpice, we have created BJT parts for these power transistors based on the values of the SPICE model parameters available on the data sheets available from ON Semiconductor. Readers can find these parts (labelled QMJE243 and QMJE253) in the SEDRA.olb library which is available on the CD accompanying this book as well as at www.sedrasmith.org.
1271
1272
CHAPTER 14
OUTPUT STAGES AND POWER
14.10
AMPLIFIERS
SPICE SIMULATION EXAMPLE
VCC
PARAMETERS:
VCC
QN
RL = 8
QMJE243
VCC = 23 IN
{VCC}^ VOFF = 0
I
~ 1 Vin
{VCC}-=-
-^"0
OUT
1 1
14.39
> {RL}
QP|
] _
FREQ = IK
-VCC
-VCC FIGURE
V 1j^QMJE253
Capture schematic of the class B output stage in Example 14.6.
(or close) to those of the circuit designed in Example 14.1. Specifically, we use a load resistance of 8 Q , an input sine-wave signal of 17.9-V peak and 1-kHz frequency, and 23-V power supplies. In PSpice, a transient-analysis simulation is, performed over the.interval 0 ms to 3 ms, and the waveforms of various node voltages and branch currents are plotted. In this example, Probe (the graphical interface of PSpice) is utilized to compute various power-dissipation values. S o m e of the resulting waveforms are displayed in Fig. 14.40. T h e upper and middle graphs show the load voltage and current, respectively. T h e peak voltage amplitude is 16.9 V, and the peak current amplitude is 2.1 A. If one looks carefully, one can observe that both exhibit crossover distortion. The b o t t o m graph displays the instantaneous and the average p o w e r dissipated in the load resistance as c o m p u t e d using Probe by multiplying the voltage and current values to obtain the instantaneous power, and taking a running average for the average load power P . T h e transient behavior of the average load power, which eventually settles into a quasiconstant steady state of about 17.6 W , is an artifact of the PSpice algorithm used to compute the running average of a waveform.
20V
L
The upper two graphs of Fig. 14.41 show the voltage and current waveforms, respectively, of the positive supply, +V . The bottom graph shows the instantaneous and average power supplied by +V . Similar waveforms can be plotted for the negative supply, -V . The average power provided b y each supply is found to be about 15 W , for a total supply power P of 30 W . Thus, the power-conversion efficiency can be computed to be CC
CC
cc
s
77 = P /Po L
-
= — x 100% = 58.6% 30
jjj
0
0.5 I ( R L ) *V (OUT)
1.0
1.5
2.0
2.5
3.0
P
o AVG (I (RL) *V (OUT)) Time (ms)
FIGURE 1 4 . 4 0 Several waveforms associated with the class B output stage (shown in Fig. 14.39) when excited by a 17.9-V, 1-kHz sinusoidal signal. The upper graph displays the voltage across the load resistance the middle graph displays the load current, and the lower graph displays the instantaneous and average power dissipated by the load.
Figure 14.42 shows plots of the voltage, current, and power waveforms associated with transistor Q . Similar waveforms can b e obtained for Q . As expected, the voltage waveform is a sinusoid, and the current waveform consists of half-sinusoids. T h e waveform of the instantaneous power, however, is rather unusual. It indicates the presence of some distortion as a result of driving the transistors rather hard. This can be verified by reducing the amplitude of the input signal. Specifically, b y reducing the amplitude to about 17 V, the "dip" in the power waveform vanishes. The average p o w e r dissipated in each of Q and Q can be computed by Probe and are found to be approximately 6 W . N
N
_
P
fi-'Ù
1 2 7 3
CHAPTER 14
14.10
O U T P U T STAGES A N D POWER AMPLIFIERS
SPICE SIMULATION EXAMPLE
10V
• IC (QP) * (V (QP:C) - V (QP:E))
-10V -10 • V (OUT)
o AVG (IC (QP) * (V (QP:C) - V (QP:E)))
0
10
5
V V i n (V)
Time (ms) FIGURE 1 4 . 4 3 Transfer characteristic of the class B output stage of Fig. 14.39. FIGURE 1 4 . 4 2 Waveforms of the voltage across, the current through, and the power dissipated in the pnp transistor Q of the output stage shown in Fig. 14.39. P
fT-tCLc
,4.1
Various Power Terms Associated w i t h t h e Class B O u t p u t Sta.je Shown in pig. 14,39 as C o m p u t e d b y H a n d a n d by PSpice Analysis
Probe w e determine that the slope of the V T C is nearly unity and that the dead band extends from - 0 . 6 0 to +0.58 V . T h e effect of the crossover distortion can b e quantified by performing a Fourier analysis on the output voltage waveform in PSpice. This analysis decomposes the waveform generated through a transient analysis into its Fourier-series components. Further, PSpice c o m p u t e s t h e total h a r m o n i c distortion ( T H D ) of the output waveform. T h e results obtained from the simulation output file are as follows:
.
Hand Analysis Power/Efficiency
Equation
Ps
(Example 14.1)
PSpice
31.2W
30.0 W
4
13.0 W
12.4 W
4.6
18.2 W
17.6 W
3.3
FOURIER COMPONENTS OF TRANSIENT RESPONSE V(OUT) DC COMPONENT = -1.525229E-02
PD
ivl PI
HARMONIC NO 1
2 3 4 5 6 7 8 9 10
2R
L
"-i x 100% Ps
n 1
58.3%
58.6%
-0.5
Relative percentage error between the values predicted by hand and by PSpice.
Table 14.1 provides a comparison of the results found from the PSpice simulation and the corresponding values obtained using hand analysis in Example 14.1. Observe that the two sets of
FREQUENCY (HZ) 1 2 3 4 5 6 7 8 9
000E+03 000E+03 000E+03 OOOE+03 000E+03 OOOE+03 OOOE+03 OOOE+03 OOOE+03 1 OO0E+04
FOURIER COMPONENT 1 .674E+01 9 .088E-03 2 .747E-01 4 .074E-03 1 .739E-01 5 833E-04 1 .195E-01 5 750E-04 9 090E-02 3 243E-04
NORMALIZED COMPONENT 1
5 1 2 1 3 7 3 5 1
000E+00 428E-04 641E-02 433E-04 039E-02 484E-05 140E-03 435E-05 429E-03 937E-05
PHASE (DEG) -2 9 -1 9 -1 9
292E-03 044E+01 799E+02 035E+01 799E+02 159E+01 - 1 800E+02 9 128E+01 - 1 800E+02 9 120E+01
NORMALIZED PHASE (DEG) 0 000E+00 9 044E+01 - 1 799E+02 9 036E+01 - 1 799E+02 9 161E+01 -1 799E+02 9 129E+01 - 1 799E+02 9 122E+01
TOTAL HARMONIC DISTORTION = 2.140017E+00 PERCENT
results are quite close. To investigate the crossover distortion further, w e present in Fig. 14.43 a plot of the voltage transfer characteristic (VTC) of t h e class B output stage. This plot is obtained through a dcanalysis simulation with m, swept over the range - 1 0 V to + 1 0 V in 1.0-mV increments. Using
._
These Fourier components are used to plot the line spectrum shown in Fig. 14.44. W e note that the output waveform is rather rich in odd harmonics and that the resulting T H D is rather high (2.14%).
1275
PROBLEMS 1276
CHAPTER 14
g
Output stages are usually equipped with circuitry that, in the event of a short circuit, can turn on and limit the basecurrent drive, and hence the emitter current, of the output transistors.
o-10T3
SI o
g
IC power amplifiers consist of a small-signal voltage amplifier cascaded with a high-power output stage. Overall feedback is applied either on-chip or externally.
g
The bridge amplifier configuration provides, across a floating load, a peak^to-peak output voltage which is
-20-
o "2
: _ ;
1277
O U T P U T STAGES A N D POWER AMPLIFIERS
-30
twice that possible from a single amplifier with a grounded load. S
The DMOS transistor is a short-channel power device capable of both high-current and high-voltage operation.
•
The drain current of a power MOSFET exhibits a positive temperature coefficient at low currents, and thus the device can suffer thermal runaway. At high currents the temperature coefficient of i is negative. D
-40 -50 -60
-80
PROBLEMS
-90
SECTION 1 4 . 2 : 4
5
6
10
7
CLASS A OUTPUT STAGE
1 4 . 1 A class A emitter follower, biased using the circuit shown in Fig. 14.2, uses V = 5 V , i f = ^ = l WD., with all transistors (including Q ) identical. Assume V = 0.7 V, V = 0.3 V, and ¡5 to be very large. For linear operation, what are the upper and lower limits of output voltage, and the corresponding inputs? How do these values change if the emitter-base junction area of Q is made twice as big as that of 2 ? Half as big? c c
,
Frequency [kHz]
3
BE
FcEsat)- For this situation, sketch the equivalent of Fig. 14.4 for v , i , a n d p . Repeat for a square-wave output that has peak levels of ± V / 2 . What is the average power dissipation in g i in each case? Compare these results to those for sine waves of peak amplitude V and F / 2 , respectively. 0
cl
m
c c
cc
c c
C £ s a t
FIGURE 1 4 . 4 4 Fourier-series components of the output waveform of the class B output stage in Fig. 14.39.
3
2
SUMMARY
1 4 . 2 A source-follower circuit using NMOS transistors is constructed following the pattern shown in Fig. 14.2. All three transistors used are identical, with V, = 1 V and fi C W/L = 20 mA/V ; V = 5V,R = R =l kQ. For linear operation, what are the upper and lower limits of the output voltage, and the corresponding inputs? n
ox
2
•
Output stages are classified according to the transistor
8
Except for an additional small quiescent power dissipation, the power relationships of the class AB stage are
conduction angle: class A (360°), class AB (slightly
similar to those in class B.
more than 180°), class B (180°), and class C (less than •
The most common class A output stage is the emitter folcurrent. The class A output stage dissipates its maximum power under quiescent conditions (v = 0). It achieves a maximum power-conversion efficiency of 2 5 % .
S
To guard against the possibility of thermal runaway, the bias voltage of the class AB circuit is made to vary with temperature in the same manner as does V of the output transistors.
maximum power that can be safely dissipated in the device is given by
p
The class B stage can achieve a power conversion effi-
_
=
(2/n)V . cc
•
The class B stage suffers from crossover distortion.
•
The class AB output stage is biased at a small current; thus both transistors conduct for small input signals, and crossover distortion is virtually eliminated.
-T
Vmax
"M
where 7 } and 9 are specified by the manufacturer, while 0 and 0 depend on the heat-sink design. m a x
0
T
VjC + °CS + °SA
ciency as high as 78.5%. It dissipates its maximum power for V
1 4 . 7 Reconsider the situation described in Exercise 14.4 for variation in V —specifically for V = 16 V, 12 V, 10 V, and 8 V. Assume V* is nearly zero. What is the powerconversion efficiency in each case? cc
cc
CEiat
1 4 . 8 The BiCMOS follower shown in Fig. P14.8 uses devices for which V = 0.7 V, V = 0.3 V, l^C^W/L = 20 m A / V ,
CS
•
0 1 4 . 4 An emitter follower using the circuit of Fig. 14.2, for which the output voltage range is ±5 V, is required using V = 10 V. The circuit is to be designed such that the current variation in the emitter-follower transistor is no greater than a factor of 10, for load resistances as low as 100 £1 What is the value of R required? Find the incremental-voltage gain of the resulting follower at v = +5, 0, and - 5 V, with a 100-D. load. What is the percentage change in gain over this range of v 7
C£sat
+5 V
He
cc
The class B stage is biased at zero current, and thus dissi- pates no power in quiescence.
S
D 1 4 . 3 Using the follower configuration shown in Fig. 14.2 with +9-V supplies, provide a design capable of ±7-V outputs with a 1-kQ. load, using the smallest possible total supply current. You are provided with four identical, high-/} BJTs and a resistor of your choice.
To facilitate the removal of heat from the silicon chip, power devices are usually mounted on heat sinks. The
0
•
2
2
BE
lower. It is biased at a current greater than the peak load
H
L
CC
cc
BE
B
180°).
cc
1 4 . 6 Consider the situation described in Problem 14.5. For square-wave outputs having peak-to-peak values of 2V and V , and for sine waves of the same peak-to-peak values, find the average power loss in the current-source transistor Q .
JC
SA
Use of the Darlington configuration in the class AB output stage reduces the base-current drive requirement. In integrated circuits, the compound pnp configuration is commonly used.
-O
0
0
* 1 4 . 5 Consider the operation of the follower circuit of Fig. 14.2 for which R = V /I, when driven by a square wave such that the output ranges from + F to L
-5 V
cc
C C
FIGURE P 1 4 . 8
v
0
78
CHAPTER 14
O U T P U T STAGES A N D POWER AMPLIFIERS
PROBLEMS
and v = - 2 V. For linear operation, what is the range of output voltages obtained with R = °°? With R = 100 Q? What is the smallest load resistor allowed for which a 1-V peak sine-wave output is available? What is the corresponding power-conversion efficiency?
smallest value of load resistance that can be tolerated, if operation is always at full output voltage? If operation is allowed at half the full output voltage, what is the smallest load permitted? What is the greatest possible output power available, in each case?
SECTION 1 4 . 3 :
D 1 4 . 1 4 A class B output stage is required to deliver an average power of 100 W into a 16-Q, load. The power supply should be 4 V greater than the corresponding peak sine-wave output voltage. Determine the power-supply voltage required (to the nearest volt in the appropriate direction), the peak current from each supply, the total supply power, and the power-conversion efficiency. Also, determine the maximum possible power dissipation in each transistor for a sine-wave input.
L
L
CLASS B OUTPUT STAGE
1 4 . 9 Consider the circuit of a complementary-BJT class B output stage. For what amplitude of input signal does the crossover distortion represent a 10% loss in peak amplitude? 1 4 . 1 0 Consider the feedback configuration with a class B output stage shown in Fig. 14.9. Let the amplifier g a i n A = 100 W V . Derive an expression for v versus v,, assuming that \V \ = 0.7 V. Sketch the transfer characteristic v versus v and compare it with that without feedback. 0
0
BE
0
h
1 4 . 1 1 Consider the class B output stage, using enhancement MOSFETs, shown in Fig. P 1 4 . l l . Let the devices have \V,\
= 1V
and LIC W/L 0X
2
= 200 L>A/V
. With a 10-kHz
sine-wave input of 5-V peak and a high value of load resistance, what peak output would you expect? What fraction of the sine-wave period does the crossover interval represent? For what value of load resistor is the peak output voltage reduced to half theinput? + 10 V A
0 * 1 4 . 2 0 A class AB output stage using a two-diode bias network as shown in Fig. 14.14 utilizes diodes having the same junction area as the output transistors. For V = 10 V, 7 = 0.5 mA, R = 100 £2, B = 50, and | V | = 0 V, what is the quiescent current? What are the largest possible positive and negative output signal levels? To achieve a positive peak output level equal to the negative peak level, what value of B is needed if I is not changed? What value of 7BIAS needed if B is held at 50? For this value, what does I become? cc
B I A S
L
N
N
C £ s a t
B1AS
i s
N
Q
* * 1 4 . 2 1 A class AB output stage using a two-diode bias network as shown in Fig. 14.14 utilizes diodes having the same junction area as the output transistors. At a room temperature of about 20°C the quiescent current is 1 m A and I V | = 0.6 V. Through a manufacturing error, the thermal coupling between the output transistors and the biasing diode-connected transistors is omitted. After some output activity, the output devices heat up to 70°C while the biasing devices remain at 20°C. Thus while the V of each device remains unchanged, the quiescent current in the output devices increases. To calculate the new current value, recall that there are two effects: I increases by about 1 4 % / ° C and V = kT/q changes, where T = (273° + temperature in °C), and V = 25 mV only at 20°C. However, you may assume that B remains almost constant. This assumption is based on the fact that B increases with temperature but decreases with current (see Fig. 5.22). What is the new value of 7 ? If the power supply is +20 V, what additional power is dissipated? If thermal runaway occurs, and the temperature of the output transistors increases by 10°C for every watt of additional power dissipation, what additional temperature rise and current increase result?
1 4 . 1 5 Consider the class B B JT output stage with a squarewave output voltage of amplitude V across a load R and employing power supplies ±V . Neglecting the effects of finite V and V , determine the load power, the supply power, the power-conversion efficiency, the maximum attainable power-conversion efficiency and the corresponding value of Vo, and"the maximum available load power. Also find the value of Vo at which the power dissipation in the transistors reaches its peak, and the corresponding value of powerconversion efficiency. a
L
SS
BE
C£sat
CLASS AB OUTPUT STAGE
BE
s
T
T
N
e
D 1 4 . 1 6 Design the quiescent current of a class AB BJT output stage so that the incremental voltage gain for Vj in the vicinity of the origin is in excess of 0.99 V7V for loads larger than 100 Q.. Assume that the BJTs have V of 0.7 V at a current of 100 mA and determine the value of V required. BE
BB
D 1 4 . 1 7 The design of a class AB MOS output stage is being considered. The available devices have |V,| = 1 V and LiC W/L = 200 m A / V . What value of gate-to-gate bias voltage, V , is required to reduce the incremental output resistance in the quiescent state to 10 Q.1
© 1 4 . 2 2 Figure P14.22 shows a MOSFET class AB output stage. All transistors have \V,\ = 1 V and k = = nk = nk , t
3
4
2
GG
+ 15 V
A
FIGURE P 1 4 . 1 1
1 4 . 1 2 Consider the complementary-BJT class B output stage and neglect the effects of finite V and V . For ±10-V power supplies and a 100-C2 load resistance, what is the maximum sine-wave output power available? What supply power corresponds? What is the power-conversion efficiency? For output signals of half this amplitude, find the output power, the supply power, and the power-conversion efficiency. BE
C£sat
D 1 4 . 1 3 A class B output stage operates from ±5-V supplies. Assuming relatively ideal transistors, what is the output voltage for maximum power-conversion efficiency? What is the output voltage for maximum device dissipation? If each of the output devices is individually rated for 1-W dissipation, and a factor-of-2 safety margin is to be used, what is the
1 2 7 9
where k = L
2
3
B I A S
L
Q
0 1 4 . 2 3 Repeat Example 14.3 for the situation in which the peak positive output current is 200 mA. Use the same general approach to safety margins. What are the values of R and R you have chosen? Y
2
* * 1 4 . 2 4 A V multiplier is designed with equal resistances for nominal operation at a terminal current of 1 mA, with half the current flowing in the bias network. The initial design is based on B = «> and V = 0.7 V at 1 mA. BE
BE
* 1 4 . 1 8 A class AB output stage, resembling that in Fig. 14.11 but utilizing a single supply of +10 V and biased at V, = 6 V, is capacitively coupled to a 100-fi load. For transistors for which | V | = 0.7 V at 1 m A and for a bias voltage V = 1.4 V, what quiescent current results? For a step change in output from 0 to - 1 V, what input step is required? Assuming transistor saturation voltages of zero, find the largest possible positive-going and negative-going steps at the output. BE
D 1 4 . 1 9 Consider the diode-biased class AB circuit of Fig. 14.14. For 7 i = 100 LLA, find the relative size («) that should be used for the output devices (in comparison to the biasing devices) to ensure an output resistance of 10 Q. or less. B
SECTION 1 4 . 6 :
POWER BJTs
0 1 4 . 2 5 A particular transistor having a thermal resistance 9 = 2°C/W is operating at an ambient temperature of 30°C with a collector-emitter voltage of 20 V. If long life requires a maximum junction temperature of 130°C, what is the corresponding device power rating? What is the greatest average collector current that should be considered? ]A
1 4 . 2 6 A particular transistor has a power rating at 25°C of 200 mW, and a maximum junction temperature of 150°C. What is its thermal resistance? What is its power rating when operated at an ambient temperature of 70°C? What is its junction temperature when dissipating 100 m W at an ambient temperature of 50°C?
BE
BE
fi
3
BB
SECTION 1 4 . 5 : BIASING THE CLASS AB CIRCUIT
(a) Find the required resistor values and the terminal voltage. (b) Find the terminal voltage that results when the terminal current increases to 2 mA. Assume ¡5= ~. (c) Repeat (b) for the case the terminal current becomes 10 mA. (d) Repeat (c) using the more realistic value of ¡3= 100.
1 4 . 2 7 A power transistor operating at an ambient temperature of 50°C, and an average emitter current of 3 A, dissipates 30 W. If the thermal resistance of the transistor is known to be less than 3°C/W, what is the greatest junction temperature you would expect? If the transistor V measured using a pulsed emitter current of 3 A at a junction temperature of 25°C is 0.80 V, what average V would you expect under normal operating conditions? (Use a temperature coefficient of-2mV/°C.)
0X
-10 V
\
BE
SECTION 1 4 . 4 :
t
L£
-o
y -15 V FIGURE P 1 4 . 2 2
0
1 4 . 2 8 For a particular application of the transistor specified in Example 14.4, extreme reliability is essential. To improve reliability the maximum junction temperature is to be limited to 100°C. What are the consequences of this decision for the conditions specified?
Vl o -
AS
v
1 4 . 2 9 A power transistor is specified to have a maximum junction temperature of 130°C. When the device is operated at this junction temperature with a heat sink, the case temperature
1280
CHAPTER 14
O U T P U T STAGES A N D POWER AMPLIFIERS PROBLEMS
is found to be 90°C. The case is attached to the heat sink with a bond having a thermal resistance 8 = 0.5°C/W and the thermal resistance of the heat sink d = 0.1°C/W. If the ambient temperature is 30°C what is the power being dissipated in the device? What is the thermal resistance of the device, 6 , from junction to case? CS
SA
]C
the input transistors? Where does it flow? What is the net input current (the offset current) for a B mismatch of 10%? For a load resistance R = 100 Q, what is the input resistance? What is the small-signal voltage gain? L
Jmax
c
(b) Replacing each BJT with its hybrid-^ model, show that
eq
BEeq
K£q
m e q
~ ^ g ,[r \\B {r m
oX
N
\\R )]
o2
f
BE
meq
0
t
in
+5 V A
(c) Find the values of v /v 0
andi? .
i
ta
W A S
5
3
EB
BE
4
5
BIAS
5
0 1 4 . 4 3 Consider the thermal shutdown circuit shown in Fig. 14.29. At 25°C, Z is a 6.8-V zener diode with a TC of 2 mV/°C, and Q and Q are BJTs that display V of 0.7 V at a current of 100 /JA and have a TC of - 2 mV/°C. Design the circuit so that at 125°C, a current of 100 pA flows in each of Q and Q . What is the current in Q, at 25°C? X
x
x
Vi
o
x
1 4 . 4 1 Repeat Exercise 14.13 for a design in which the limiting output current and normal peak current are 50 mA and 33.3 mA, respectively.
c
0 1 4 . 4 2 The circuit shown in Fig. P14.42 operates in a manner analogous to that in Fig. 14.28 to limit the output
C
FIGURE P 1 4 . 3 7
0 1 4 . 4 4 In the power-amplifier circuit of Fig. 14.30 two resistors are important in controlling the overall voltage gain. Which are they? Which controls the gain alone? Which affects both the dc output level and the gain? A new design is being considered in which the output dc level is approximately 1 V (rather than approximately ±V ) with a gain of 50 (as before). What changes are needed? s
S
1 4 . 4 5 Consider the front end of the circuit in Fig. 14.30. For V = 20 V, calculate approximate values for the bias currents in Q through Q . Assume B = 100, B = 20, and \V \ = 0.7 V. Also find the dc voltage at the output. x
BE
A
in
+ 10 Y
0 6 ÖS
cc
x
01
3A
2
Vj o -
Hi
BE
1 4 . 3 5 A circuit resembling that in Fig. 14.24 uses four matched transistors for which | V \ = 0.7 V at 10 mA, n = 1, and B> 50. Resistors R and R are replaced by 2-mA current sources, and R =R = 0. What quiescent current flows in the output transistors? What bias current flows in the bases of
t -10 V
BE
x
3
s
pnp
4
3
x2
npn
6
X2
4
2
4
* 1 4 . 4 6 Assume that the output voltage of the circuit of Fig. 14.30 is at signal ground (and thus the signal feedback is deactivated) and find the differential and common-mode input resistances. For this purpose do not include R and R . Let V = 20 V, B = 100, and B = 20. Also find the transconductance from the input to the output of the first stage (at the connection of the collectors of Q and Q and the base of Q ). s
4
3
pnp
4
4
x
npn
P
N
x
3
6
BE
* * 1 4 . 3 8 The BJTs in the circuit of Fig. P14.38 have ß = 10, ß = 100, \V \ = 0.7 V, and | V | = 100 V.
0 * * * 1 4 . 3 4 Consider the circuit of Fig. 14.24 in which Q and Q are matched, and Q and Q are matched but have three times the junction area of the others. For V = 10 V, find values for resistors R through R which allow for a base current of at least 10 mA in Q and Q at u, = + 5 V (when a load demands it) with at most a 2-to-l variation in currents in Q and Q , and a no-load quiescent current of 40 mA in Q and Q ; B > 150, and B > 50. For input voltages around 0 V, estimate the output resistance of the overall follower driven by a source having zero resistance. For an input voltage of +1 V and a load resistance of 2 Q, what output voltage results? Gi and Q have [ V | of 0.7 V at a current of 10 mA and exhibit a constant n = 1. 2
2
s
Vcc
SECTION 1 4 . 7 : VARIATIONS ON THE CLASS AB 1 4 . 3 3 Use the results given in the answer to Exercise 14.11 to determine the input current of the circuit in Fig. 14.24 for vi = 0 and ±10 V with infinite and 100-Q loads.
BE
SECTION 1 4 . 8 : IC POWER AMPLIFIERS 1 4 . 4 0 Repeat Exercise 14.13 for a design variation in which transistor Q is increased in size by a factor of 10, all other conditions remaining the same. ' 5
CONFIGURATION
2
cc
x
1 4 . 3 2 A base spreading resistance (r ) of 0.8 Q. has been measured for an npn power transistor operating at I = 5 A, with a base-emitter voltage of 1.05 V and a base current of 190 mA. Assuming that n = 2 for high-current-density operation, what base-emitter voltage would you expect for operation at 7 = 2 A?
3
4
BE
x
2
1 kil
c
1
8
5
0 * * 1 4 . 3 9 Consider the compound-transistor class AB output stage shown in Fig. 14.27 in which Q and Q are matched transistors with V — 0.7 V at 10 mA and B = 100, Q and Q have V = 0.7 V at 1-mA currents and B= 100, and Q has V = 0.7 V at a 1-mA current and B = 10. All transistors have n = 1. Design the circuit for a quiescent current of 2 mA in Q and Q , I that is 100 times the standby base current in Q and a current in Q that is nine times that in the associated resistors. Find the values of the input voltage required to produce outputs of ±10 V for a l-ki2 load. Use V of 15 V. h
1 4 . 3 1 An npn power transistor operating at I = 10 A is found to have a base current of 0.5 A and an incremental base input resistance of 0.95 Q. What value of r do you suspect? (At this high current density, n = 2.)
2
s
2
1 4 . 3 7 For the circuit in Fig. P14.37 in which the transistors have V = 0.7 V and B = 100, find/.. g , v /v , and R .
1
current from Q in the event of a short circuit or other mishap. It has the advantage that the current-sensing resistor R does not appear directly at the output. Find the value of R that causes Q to turn on and absorb all of 7 = 2 mA when the current being sourced reaches 150 mA. For g , I = 10 A and n = 1. If the normal peak output current is 100 mA, find the voltage drop across R and the collector current in Q . 5
1 4 . 3 6 Characterize a Darlington compound transistor formed from two npn BJTs for which B > 50, V = 0.7 V at 1 mA, and n = 1. For operation at 10 mA, what values would you expect for /3 , V , r , and g . BE
1 4 . 3 0 A power transistor for which T = 180°C can dissipate 50 W at a case temperature of 50°C. If it is connected to a heat sink using an insulating washer for which the thermal resistance is 0.6°C/W, what heat-sink temperature is necessary to ensure safe operation at 30 W? For an ambient temperature of 39°C, what heat-sink thermal resistance is required? If, for a particular extruded-aluminum-finned heat sink, the thermal resistance in still air is 4.5°C/W per centimeter of length, how long a heat sink is needed?
(a) Find the dc collector current of each transistor and the value of V .
O
2
4
FIGURE P 1 4 . 3 8
FIGURE P I 4 . 4 2
1 4 . 4 7 It is required to use the LM380 power amplifier to drive an 8-Q loudspeaker while limiting the maximum possible device dissipation to 1.5 W. Use the graph of Fig. 14.32 to determine the maximum possible power-supply voltage that can be used. (Use only the given graphs; do not interpolate.) If the maximum allowed THD is to be 3 % , what is the maximum possible load power? To deliver this power to the load what' peak-to-peak output sinusoidal voltage is required? 1 4 . 4 8 Consider the LM380 amplifier. Assume that when the amplifier is operated with a 20-V supply, the transconductance of the first stage is 1.6 mAA^. Find the unity-gain
1282
J
CHAPTER 14
O U T P U T STAGES A N D POWER AMPLIFIERS PROBLEMS
+ V
of drain current does velocity saturation begin? For electrons in silicon, £/ = 5 x 10 cm/s and pi = 500 c m / V s . What is g for this device at high currents?
r
6
2
sat
n
m
R = R , the temperature coefficient of V = -2 mV/°C and the temperature coefficient of V = - 3 mV/°C in the 'lowcurrent region. Find the values of R, R j?„ # Assume Q , Q , and Q to be thermally coupled. (A> , used to suppress parasitic oscillation at high frequency, is usually 100 Q. or so.) 2
4
BB
t
u
6
B 1 4 . 5 4 Consider the design of the class AB amplifier of Fig. 14.38 under the following conditions: \V,\ = 2 V, pC W/L = 200 mA/V , \V \ = 0.7 V, B is high, I = I = I = 10 mA, / = 100 fiA, I = I = 7 /2, 2
m
QP
FIGURE P 1 4 . 5 0
bandwidth (f ). Since the closed-loop gain is approximately 50 V/V, find its 3-dB bandwidth. t
D 1 4 . 4 9 Consider the power-op-amp output stage shown in Fig. 14.33. Using a ±15-V supply, provide a design that provides an output of ±11 V or more, with currents up to ±20 mA provided primarily by Q and Q with a 10% contribution by Q and Q , and peak output currents of 1 A at full output (+11 V). As the basis of an initial design, use ¡5=50 and \V E\ ~ 0-7 V for all devices at all currents. Also use R = R = 0. 3
5
A
6
B
s
6
1 4 . 5 0 For the circuit in Fig. P 14.50. assuming all transistors to have large ¡3, show that i = v,/R. [This voltageto-current converter is an application of a versatile circuit building block known as the current conveyor; see Sedra and Roberts (1990)]. For ¡3 = 100, by what approximate percentage is i actually lower than this ideal value? 0
F I G U R E PI
4.52
0
D 1 4 . 5 1 For the bridge amplifier of Fig. 14.34, let /?, = R, = 10 k£X Find R and R to obtain an overall gain of 10. 2
4
D 1 4 . 5 2 An alternative bridge amplifier configuration, with high input resistance, is shown in Fig. P14.52. (Note the similarity of this circuit to the front end of the instrumentation amplifier circuit shown in Fig. 2.20(b).) What is the gain v /vp. For op amps (using ±15-V supplies) mat limit at+13 V, what is the largest sine wave you can provide across R 1 0
L
Using 1 kfl as the smallest resistor, find resistor values that make v /v = 10 V/V. 0
[
SECTION 1 4 . 9 : MOS POWER TRANSISTORS 1 4 . 5 3 A particular power DMOS device for which C is 400 /zF/m , Wis 10 pm, and V = 2 V, enters velocity saturation at v = 5 V. Use Eqs. (14.46) and (14.47) to find an expression for L and its value for this transistor. At what value ox
2
s
t
GS
BE
R
B I A S
QN
Q5
Q6
B I A S
:
p
N
3 >
a
n
d
G
R
APPENDIXES APPENDIX E s-Domain Analysis: Poles, Zeros, and Bode Plots
APPENDIX A VLSI Fabrication Technology
A-1 APPENDIX F Bibliography F-1
APPENDIX B Two-Port Network Parameters
B-1
APPENDIX G Standard Resistance Values and Unit Prefixes
APPENDIX C Some Useful Network Theorems APPENDIX D Single-Time-Constant Circuits
E-1
C-1
D-1
APPENDIX H Answers to Selected Problems
H-1
G-1
VLSI Fabrication Technology INTRODUCTION T h e p u r p o s e of this a p p e n d i x is to familiarize the reader with V L S I (very-large-scale inte grated circuit) fabrication technology. Brief explanations of standard silicon V L S I processing steps are given. T h e characteristics of devices available in C M O S and B i C M O S fabrication technologies are also presented. In particular, the aspects of I C (integrated-circuit) design that are distinct from discrete-circuit design will b e discussed. T o take p r o p e r advantage of the e c o n o m i c s of integrated circuits, designers h a v e h a d to o v e r c o m e s o m e serious device limita tions (such as p o o r tolerances) while exploiting device advantages (such as g o o d c o m p o n e n t matching). A n understanding of device characteristics is therefore essential in designing g o o d c u s t o m V L S I s or application-specific ICs (ASICs). This understanding is also very helpful w h e n selecting c o m m e r c i a l l y available ICs to i m p l e m e n t a s y s t e m design. This a p p e n d i x will consider only silicon-based technologies. A l t h o u g h gallium arsenide ( G a A s ) is also u s e d to i m p l e m e n t V L S I chips, silicon (Si) is b y far the m o s t popular material, featuring a w i d e r a n g e of c o s t - p e r f o r m a n c e trade-offs. R e c e n t d e v e l o p m e n t in S i G e and strained-silicon technologies will further strengthen the position of Si-based fabrication processes in t h e microelectronics industry in t h e c o m i n g years. Silicon is an a b u n d a n t element, which occurs naturally in the form of sand. It can b e refined u s i n g well-established techniques of purification and crystal g r o w t h . Silicon also exhibits suitable p h y s i c a l properties for fabricating active devices with g o o d electrical char acteristics. M o r e o v e r , silicon can b e easily oxidized to f o r m an excellent insulator, S i 0 (glass). T h i s native o x i d e is useful for constructing capacitors and M O S F E T s . It also serves as a diffusion barrier that can m a s k against t h e diffusion of u n w a n t e d impurities into nearby high-purity silicon material. T h i s m a s k i n g p r o p e r t y of silicon o x i d e allows the electrical properties of silicon to b e easily altered in predefined areas. Therefore, active and p a s s i v e e l e m e n t s can b e built o n t h e s a m e piece of material (or, substrate). T h e c o m p o n e n t s c a n t h e n b e i n t e r c o n n e c t e d u s i n g m e t a l layers (similar to those u s e d in printed-circuit boards) to form a so-called m o n o l i t h i c I C , w h i c h is essentially a single p i e c e of material (rock!). 2
-
A.1
IC FABRICATION STEPS
T h e basic I C fabrication steps will be described in the following subsections. S o m e of these steps m a y b e carried out m a n y times, in different combinations and under different processing conditions d u r i n g a c o m p l e t e fabrication run.
DIX A
VLSI F A B R I C A T I O N T E C H N O L O G Y
A.l
IC F A B R I C A T I O N S T E P
d e d u c e t h e thickness of the o x i d e layer. T h e s a m e principle is u s e d b y sophisticated optical inferometers to m e a s u r e film thickness. O n a p r o c e s s e d wafer, there will b e regions w i t h different o x i d e t h i c k n e s s e s . T h e c o r r e s p o n d i n g colors can b e quite vivid, and thickness vari ations are i m m e d i a t e l y o b v i o u s w h e n a finished wafer is v i e w e d with the n a k e d eye FIGURE A . I Silicon ingot and wafer slices.
A.1.1 Wafer Preparation T h e starting material for m o d e r n integrated circuits is very-high-purity silicon. T h e material is g r o w n as a single-crystal ingot. It takes the form of a steel gray solid cylinder 10 c m to 30 cm in diameter (Fig. A . l ) and can b e 1 m to 2 m in length. This crystal is then sawed (like a loaf of bread) to produce circular wafers that are 4 0 0 t a n to 600 pm thick (a micrometer or micron is a millionth of a meter). T h e surface of the wafer is then polished to a mirror finish using chemical and mechanical polishing ( C M P ) techniques. Semiconductor manufacturers usually purchase ready-made silicon wafers from a supplier and rarely start their process at the ingot stage. T h e basic electrical and mechanical properties of the wafer depend o n the orientation of the crystaUine planes, as well as the concentration and type of impurities present. These variables are strictly controlled during crystal growth. Controlled amounts of impurities can be added to the pure silicon in a process k n o w n as doping. This allows the alteration of the electrical properties of the silicon, in particular its resistivity. It is also possible to control the conduction-carrier type, either holes (in p-type silicon) or electrons (in n-type silicon), that is responsible for electrical conduction. If a large n u m b e r of impurity atoms is added, then the silicon is said to b e heavily doped (e.g., concentration > 1 0 a t o m s / c m ) . W h e n designating the relative doping concentra tions in semiconductor device structures, it is c o m m o n to use + and - symbols. A heavily doped (low-resistivity) w-type silicon wafer would be referred to as n+ material, while a lightly doped region m a y be referred to as n- T h e ability to control the type of impurity and the doping con centration in the silicon permits the formation of diodes, transistors, and resistors in flexible integrated-circuit form. 1 8
3
A.1.2 Oxidation O x i d a t i o n refers to t h e c h e m i c a l p r o c e s s of silicon reacting w i t h o x y g e n to form silicon dioxide ( S i 0 ) . T o speed u p the reaction, it is n e c e s s a r y to u s e special high-temperature (e.g., 1 0 0 0 - 1 2 0 0 ° C ) ultraclean furnaces. T o avoid t h e introduction of even small quantities of c o n t a m i n a n t s ( w h i c h could significantly alter t h e electrical properties of the silicon), it is n e c e s s a r y to m a i n t a i n a clean e n v i r o n m e n t . This is true for all p r o c e s s i n g steps i n v o l v e d in the fabrication of an integrated circuit. Specially filtered air is circulated in t h e processing area, and all p e r s o n n e l m u s t w e a r special lint-free clothing. 2
T h e oxygen used in the reaction can b e introduced either as a high-purity gas (in a process referred to as a "dry oxidation") or as steam (for "wet oxidation"). In general, w e t oxidation has a faster growth rate, but dry oxidation gives better electrical characteristics. In either case, the ther mally grown oxide layer has excellent electrical insulation properties. T h e dielectric strength for S i 0 is approximately 1 0 V/cm. It has a dielectric constant of about 3.9 and can be used to form excellent capacitors. A s noted, silicon dioxide serves as an effective mask against m a n y impuri ties, allowing the introduction of dopants into the silicon only in regions that are not covered with oxide. This masking property is one of the essential enablers of mass fabrication of V L S I devices. Silicon d i o x i d e is a thin transparent film, a n d t h e silicon surface is highly reflective. If w h i t e light is s h o n e on an o x i d i z e d wafer, constructive and destructive interference will c a u s e certain colors to b e reflected. T h e w a v e l e n g t h s of the reflected light d e p e n d on the thickness of t h e o x i d e layer. In fact, b y c a t e g o r i z i n g the color of the wafer surface, o n e can 7
2
A.1.3 Diffusion Diffusion is t h e p r o c e s s b y w h i c h atoms m o v e from a h i g h - c o n c e n t r a t i o n region to a l o w concentration r e g i o n t h r o u g h the s e m i c o n d u c t o r crystal. T h e diffusion p r o c e s s is very m u c h like a d r o p of ink dispersing t h r o u g h a glass of water except that it occurs m u c h m o r e s l o w l y in solids. In fabrication, diffusion is a m e t h o d b y w h i c h to introduce impurity a t o m s (dopants) into silicon to c h a n g e its resistivity. T h e rate at w h i c h dopants diffuse in silicon is a strong function of t e m p e r a t u r e . T h u s , for speed, diffusion of impurities is usually carried out at h i g h t e m p e r a t u r e s ( 1 0 0 0 - 1 2 0 0 ° C ) to obtain the desired d o p i n g profile. W h e n the wafer is cooled to r o o m t e m p e r a t u r e , the impurities are essentially "frozen" in position. T h e diffusion p r o c e s s is p e r f o r m e d in furnaces similar to those u s e d for oxidation. T h e d e p t h to w h i c h t h e impurities diffuse d e p e n d s on both t h e t e m p e r a t u r e and t h e t i m e allocated. T h e m o s t c o m m o n impurities u s e d as dopants are b o r o n , p h o s p h o r u s , and arsenic. B o r o n is a p-type dopant, w h i l e p h o s p h o r u s and arsenic are n-type d o p a n t s . T h e s e dopants can b e effectively m a s k e d b y thin silicon dioxide layers. B y diffusing b o r o n into an n-type s u b strate, a pn j u n c t i o n (diode) is formed. If the d o p i n g concentration is h e a v y e n o u g h , t h e dif fused layer can also b e u s e d as a conductor.
A. 1.4 Ion Implantation I o n implantation is another m e t h o d used to introduce impurity atoms into the semiconductor crystal. A n ion i m p l a n t e r p r o d u c e s ions of the desired dopant, accelerates t h e m b y an elec tric field, and allows t h e m to strike t h e s e m i c o n d u c t o r surface. T h e ions b e c o m e e m b e d d e d in t h e crystal lattice. T h e depth of penetration is related to the energy of the ion b e a m , w h i c h can b e controlled b y the accelerating-field voltage. T h e quantity of ions i m p l a n t e d can be controlled b y v a r y i n g the b e a m current (flow of ions). S i n c e both voltage and current can be accurately m e a s u r e d a n d controlled, ion implantation results in m u c h m o r e accurate and reproducible impurity profiles than can be obtained b y diffusion. In addition, ion implantation can b e p e r f o r m e d at r o o m t e m p e r a t u r e . Ion implantation normally is used w h e n accurate control of t h e d o p i n g profile is essential for device operation.
A.1.5 Chemical-Vapor Deposition C h e m i c a l - v a p o r d e p o s i t i o n ( C V D ) is a p r o c e s s by w h i c h gases or v a p o r s are c h e m i c a l l y reacted, leading to the formation of solids on a substrate. C V D can b e used to deposit vari ous materials o n a silicon substrate including S i 0 , S i N , and polysilicon. F o r instance, if silane gas and o x y g e n are allowed to react a b o v e a silicon substrate, the end product, silicon dioxide, will b e deposited as a solid film on t h e silicon wafer surface. T h e properties of the C V D o x i d e layer are not as g o o d as those of a thermally g r o w n oxide, but such a layer is sufficient to act as an electrical i n s u l a t o r . ' T h e a d v a n t a g e of a C V D layer is that t h e o x i d e deposits at a fast rate and a l o w t e m p e r a t u r e (below 5 0 0 ° C ) . 2
3
4
If silane gas alone is used, then a silicon layer will be deposited o n the wafer. If the r e a c tion t e m p e r a t u r e is h i g h e n o u g h (above 1000°C), the layer deposited will b e a crystalline layer ( a s s u m i n g that there is an e x p o s e d crystalline silicon substrate). S u c h a layer is called an epitaxial layer, and t h e deposition p r o c e s s is referred to as epitaxy, rather than C V D . A t l o w e r t e m p e r a t u r e s , or if the substrate surface is n o t single-crystal silicon, the a t o m s will n o t b e able to align in t h e s a m e crystalline direction. S u c h a layer is called polycrystalline
A
_ 4
APPENDIX A
VLSI F A B R I C A T I O N T E C H N O L O G Y
A.2
VLSI P R O C E S S E S
silicon ( p o l y Si), since it consists of m a n y s m a l l crystals of silicon w h o s e crystalline axes are oriented in r a n d o m directions. T h e s e layers are n o r m a l l y d o p e d very h e a v i l y to f o r m h i g h l y c o n d u c t i v e r e g i o n s that c a n be u s e d for electrical i n t e r c o n n e c t i o n s .
A. 1.6 Metallization
FIGURE A . 2 (a) An 8-pin plastic dual-in line IC package (DIP), (b) A 16-pin surface mount IC package (SOC), shown on a much larger scale than (a).
T h e purpose of metallization is to interconnect the various c o m p o n e n t s (transistors, capacitors, etc.) to form the desired integrated circuit. Metallization involves the initial deposition of a metal over the entire surface of the silicon. T h e required interconnection pattern is t h e n selec tively etched. T h e m e t a l layer is normally deposited via a sputtering process. A pure metal disk (e.g., 9 9 . 9 9 % a l u m i n u m ) is placed u n d e r an argon (Ar) ion gun inside a v a c u u m chamber. T h e wafers are also m o u n t e d inside the c h a m b e r a b o v e the target. T h e A r ions will not react with
• j A.2 VLSI PROCESSES
the metal, since A r is a noble gas. H o w e v e r , their ions are m a d e to physically b o m b a r d the tar get and literally k n o c k metal atoms out of it. T h e s e metal atoms will then coat all the surface
Integrated-circuit fabrication w a s originally d o m i n a t e d b y bipolar t e c h n o l o g y . B u t , b y the
inside the c h a m b e r , including the wafers. T h e thickness of the m e t a l film can b e controlled b y
late 1970s m e t a l - o x i d e - s e m i c o n d u c t o r ( M O S ) t e c h n o l o g y w a s p e r c e i v e d to b e m o r e p r o m i s
t h e length of t i m e for sputtering, which is normally in the range of 1 to 2 minutes.
i n g for V L S I i m p l e m e n t a t i o n , o w i n g to its h i g h e r p a c k i n g density and l o w e r p o w e r c o n
A.1.7 Photolithography
p r o d i g i o u s l y to a l m o s t c o m p l e t e l y d o m i n a t e the V L S I scene, leaving b i p o l a r t e c h n o l o g y to
T h e surface geometry of the various integrated-circuit c o m p o n e n t s is defined photographically.
fill specialized functions such as digital and h i g h - s p e e d a n a l o g and R F circuits. C M O S tech
s u m p t i o n . S i n c e the early 1980s, c o m p l e m e n t a r y M O S ( C M O S ) t e c h n o l o g y h a s g r o w n
First, the wafer surface is coated with a photosensitive layer (called photoresist) using a spin-on
n o l o g i e s c o n t i n u e to evolve, and in the late 1980s, t h e incorporation of b i p o l a r devices led to
technique. After this, a photographic plate with d r a w n patterns (e.g., a quartz plate with a chro
the e m e r g e n c e of h i g h - p e r f o r m a n c e b i p o l a r - C M O S ( B i - C M O S ) fabrication p r o c e s s e s that
m i u m pattern) will b e used to selectively expose the photoresist under ultraviolet (UV) illumi
p r o v i d e d t h e b e s t of b o t h t e c h n o l o g i e s . H o w e v e r , B i C M O S p r o c e s s e s are often very c o m p l i
nation. T h e exposed areas will b e c o m e softened (for positive photoresist). T h e exposed layer
cated and costly, since they require u p w a r d of 15 to 2 0 m a s k i n g levels p e r i m p l e m e n t a t i o n —
can then be r e m o v e d using a chemical developer, causing the m a s k pattern to appear on the
b y c o m p a r i s o n , standard C M O S p r o c e s s e s r e q u i r e only 10 to 12 m a s k i n g levels.
wafer. V e r y fine surface geometries can b e reproduced accurately b y this technique. Photoli
T h e p e r f o r m a n c e of C M O S and B i C M O S p r o c e s s e s continues to i m p r o v e , offering finer
thography requires some of the m o s t expensive equipment in V L S I fabrication. Currently, w e
lithographic resolution. H o w e v e r , f u n d a m e n t a l limitations on p r o c e s s i n g t e c h n i q u e s a n d
are already approaching the physical limits of the photolithographic process. D e e p U V light or
s e m i c o n d u c t o r properties h a v e p r o m p t e d the n e e d to e x p l o r e alternate materials. Silicon-
electron b e a m can b e used to define patterns with resolution as fine as 50 ran. However, another
g e r m a n i u m (SiGe) and strained-Si t e c h n o l o g i e s h a v e e m e r g e d as g o o d c o m p r o m i s e s w h i c h
technological breakthrough will b e needed to achieve further geometry downscaiing.
i m p r o v e p e r f o r m a n c e w h i l e m a i n t a i n i n g m a n u f a c t u r i n g compatibility ( h e n c e l o w cost) with
T h e p a t t e r n e d photoresist layer c a n b e u s e d as an effective m a s k i n g layer to protect
existing silicon-based C M O S fabrication e q u i p m e n t .
m a t e r i a l s b e l o w f r o m wet c h e m i c a l etching or r e a c t i v e ion e t c h i n g . C o r r e s p o n d i n g l y , silicon
In the subsections that follow, w e will e x a m i n e , in turn, three aspects of m o d e r n I C fabri
dioxide, silicon nitride, polysilicon, and m e t a l layers can b e selectively r e m o v e d using the
cation, n a m e l y ; a typical C M O S p r o c e s s flow, t h e p e r f o r m a n c e of the available c o m p o n e n t s ,
appropriate etching methods. After the etching step(s), the photoresist is stripped away, leaving
and the inclusion of b i p o l a r devices to form a B i C M O S p r o c e s s .
behind a p e r m a n e n t pattern, a n i m a g e of t h e p h o t o m a s k , o n the wafer surface. T o m a k e this p r o c e s s e v e n m o r e c h a l l e n g i n g , m u l t i p l e m a s k i n g layers (there c a n b e m o r e t h a n 2 0 layers in a d v a n c e d V L S I fabrication p r o c e s s e s ) m u s t b e aligned precisely o n top of p r e v i o u s l a y e r s . This m u s t b e d o n e w i t h e v e n greater precision than is associated w i t h t h e m i n i m u m d i m e n s i o n s of t h e m a s k i n g p a t t e r n s . T h i s r e q u i r e m e n t i m p o s e s very critical m e c h a n i c a l and optical constraints o n t h e p h o t o l i t h o g r a p h y e q u i p m e n t .
A.2.1 n-Well CMOS Process D e p e n d i n g o n the choice of starting material (substrate), C M O S processes can be identified as 77-weII,/7-well, or t w i n - w e l l processes, the latter being the m o s t complicated but also the m o s t flexible in the optimization of both the n- and ^ - c h a n n e l devices. In addition, m a n y advanced C M O S p r o c e s s e s m a y m a k e use of trench isolation, and silicon-on-insulator (SOI) technol ogy, to r e d u c e parasitic capacitance (to achieve h i g h e r speed) and to i m p r o v e p a c k i n g density.
A.1.8 Packaging
F o r simplicity, an re-well C M O S p r o c e s s is c h o s e n for discussion. A n o t h e r benefit of this
A finished silicon wafer m a y contain several h u n d r e d or m o r e finished circuits or chips. E a c h
c h o i c e is t h a t it c a n also b e easily e x t e n d e d into a B i C M O S p r o c e s s . T h e typical p r o c e s s
chip m a y contain from 10 to 1 0 or m o r e transistors in a rectangular shape, typically b e t w e e n
flow is as s h o w n in F i g . A . 3 . A m i n i m u m of 7 m a s k i n g layers is n e c e s s a r y . H o w e v e r , in
1 m m and 10 m m on a side. T h e circuits are first tested electrically (while still in wafer form)
p r a c t i c e m o s t C M O S p r o c e s s e s will also r e q u i r e additional layers s u c h as re a n d / ? g u a r d s for
8
using an automatic probing station. B a d circuits are m a r k e d for later identification. T h e circuits
better l a t c h u p i m m u n i t y , a second polysilicon layer for capacitors, and m u l t i l a y e r m e t a l s for
are then separated from each other (by dicing), and the good circuits (called dies) are m o u n t e d
h i g h - d e n s i t y i n t e r c o n n e c t i o n s . T h e inclusion of t h e s e layers w o u l d increase the total n u m b e r
in packages (or headers). E x a m p l e s of such I C packages are given in Fig. A.2. Fine gold wires
of m a s k i n g layers from 15 to 20.
are normally used to connect the pins of the package to the metallization pattern on the die. Finally, the p a c k a g e is sealed using plastic or epoxy under v a c u u m or in an inert atmosphere.
T h e starting m a t e r i a l for the re-well C M O S is a / 7 - t y p e substrate. T h e p r o c e s s begins with an re-well diffusion (Fig. A . 3 a ) . T h e re w e l l is r e q u i r e d w h e r e v e r p - t y p e M O S F E T s are to be
' " 3
A-5
APPENDIX A V L S I F A B R I C A T I O N
A.2
TECHNOLOGY
placed. A t h i c k silicon d i o x i d e layer is etched t o e x p o s e t h e r e g i o n s for n - w e l l diffusion. T h e
(e) n+ diffusion (mask #4)
(a) Define «-well diffusion (mask #1)
VLSI P R O C E S S E S
u n e x p o s e d r e g i o n s will b e protected from t h e n - t y p e p h o s p h o r u s impurity. P h o s p h o r u s is usually u s e d for d e e p diffusions b e c a u s e it h a s a large diffusion coefficient a n d c a n diffuse
Arsenic implant
faster t h a n arsenic into t h e substrate.
Phosphorus diffusion
T h e s e c o n d step is t o define t h e active r e g i o n ( w h e r e transistors a r e t o b e placed) u s i n g a -, Photoresist, ; |
Sl61
I
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T
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t
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,
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3
4
p a t t e r n e d relative t o t h e p r e v i o u s n - w e l l r e g i o n s (Fig. A . 3 b ) . T h e nitride-covered regions
-
n Well silicon substrate
t e c h n i q u e called l o c a l o x i d a t i o n ( L O C O S ) . A silicon nitride ( S i N ) layer is deposited a n d will n o t b e oxidized. After a l o n g w e t oxidation step, thick-field o x i d e will appear in regions b e t w e e n transistors (Fig. A.3c). This thick-field oxide is necessary for isolating t h e transistors. It also allow interconnection layers to b e routed o n top of the field oxide without inadvertently
p Substrate
forming a c o n d u c t i o n c h a n n e l at t h e silicon surface. T h e n e x t step is t h e formation of the polysilicon g a t e (Fig. A , 3 d ) . This is o n e of t h e m o s t critical steps in t h e C M O S p r o c e s s . T h e thin o x i d e layer i n t h e active regi on is first r e m o v e d using w e t e t c h i n g followed b y t h e g r o w t h of a high-quality thin gate o x i d e . Current 0.13 pm
(f) p+ diffusion (mask #5)
(b) Define active regions (mask #2)
and 0.18 pirn p r o c e s s e s routinely u s e o x i d e thicknesses as thin as 2 0 A t o 5 0 A (1 a n g s t r o m — 10
Boron implant
c m ) . A polysilicon layer, usually arsenic d o p e d in type), is t h e n deposited a n d pat
terned. T h e p h o t o l i t h o g r a p h y is m o s t d e m a n d i n g in this step, since t h e finest resolution is SÍ3N4
SiO,
r e q u i r e d t o p r o d u c e t h e shortest p o s s i b l e M O S c h a n n e l length.
Active region
Photoresist ',-\
T h e p o l y s i l i c o n g a t e is a self-aligned structure a n d is preferred over t h e older t y p e of m e t a l g a t e structure. A h e a v y arsenic i m p l a n t c a n b e u s e d t o f o r m t h e n+ source a n d drain n Well
n Well
p r o t e c t t h e c h a n n e l r e g i o n . A l a y e r of p h o t o r e s i s t c a n b e u s e d t o b l o c k t h e r e g i o n s w h e r e p - M O S F E T s are t o b e formed (Fig. A.3e). T h e thick-field oxide stops t h e implant a n d pre
/; Substrate
p Substrate
regions of t h e n - M O S F E T s . T h e polysilicon gate also acts as a barrier for this i m p l a n t t o
vents n+ regions from forming outside t h e active regions. A reversed photolithography step can b e u s e d to protect t h e re-MOSFETs during the p+ b o r o n source a n d drain implant for t h e p - M O S F E T s (Fig. A.3f). In both cases the separation between the source and drain diffusions— the channel length—is defined b y the polysilicon gate m a s k alone, hence the self-alignment.
(g) Contact holes (mask # 6 )
(c) L O C O S oxidation
B e f o r e c o n t a c t h o l e s are o p e n e d , a thick layer of C V D o x i d e is d e p o s i t e d over t h e entire wafer. A p h o t o m a s k is u s e d to'define t h e contact w i n d o w o p e n i n g (Fig. A . 3 g ) followed b y a
CVD oxide Si0
w e t or d r y o x i d e etch. A thin a l u m i n u m layer is then e v a p o r a t e d o r sputtered onto t h e wafer.
SiO,
2
A final m a s k i n g a n d e t c h i n g step is u s e d t o pattern t h e interconnection (Fig. A . 3 h ) .
y
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N o t s h o w n in t h e p r o c e s s flow is t h e final passivation step prior t o p a c k a g i n g a n d w i r e
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Wc I
p Substrate
p Substrate
b o n d i n g . A t h i c k C V D o x i d e o r p y r o x glass is usually d e p o s i t e d o n t h e wafer to serve as a p r o t e c t i v e layer.
A.2.2 Integrated Devices B e s i d e s t h e o b v i o u s , n- a n d /^-channel M O S F E T s , there a r e other devices that c a n b e o b t a i n e d b y m a n i p u l a t i n g t h e m a s k i n g layers. T h e s e i n c l u d e pn j u n c t i o n diodes, M O S
(d) Polysilicon gate (mask #3)
Polysilicon gate Si0
i Substrate
2
ill
FIGURE A . 3 A typical n-well CMOS process flow.
(h) Metallization (mask #7) w-MOSFET
capacitors, a n d resistors. p-MOSFET_
A.2.3 MOSFETs T h e ra-channel M O S F E T is preferred over t h e p - M O S F E T (Fig. A . 4 ) . T h e electron surface mobility of t h e n - c h a n n e l device is t w o to four t i m e s h i g h e r t h a n that for h o l e s . Therefore, with t h e s a m e device size (W a n d L), t h e n - M O S F E T offers h i g h e r current drive (or l o w e r on-resistance) as well as h i g h e r t r a n s c o n d u c t a n c e . In a n integrated-circuit design environment, M O S F E T s are characterized b y their thresh old voltage a n d device sizes. Usually the n- and /7-channel devices are designed to h a v e thresh old voltages of similar magnitude for a particular process. T h e transconductance can b e adjusted
A-8
ï ' à
APPENDIX A
VLSI F A B R I C A T I O N T E C H N O L O G Y
A.2
p-MOSFET
«-MOSFET S
Interpoly capacitor
,
M
O
S
ca
VLSI P R O C E S S E S
a
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D
w
SiO,
• Well
p Substrate
p Substrate
j
P a r a < ; i t i c
capacitance
FIGURE A . 6 Interpoly and MOS capacitors in an n-well CMOS process.
FIGURE A . 4 Cross-sectional diagram of an n- and p-MOSFET.
h e n c e m o r e accurate resistor ratios. F u r t h e r m o r e , the p o l y resistor is physically separated from the substrate, resulting in m u c h l o w e r parasitic c a p a c i t a n c e and voltage coefficient.
by changing the device surface dimensions ( W a n d L). This feature is not available for bipolar
A.2.5 Capacitors
transistors; thus integrated M O S F E T circuits are m u c h m o r e flexible in their design.
T w o types of capacitor structure are available in C M O S p r o c e s s e s , M O S and interpoly capacitors (also M I M — m e t a l - i n s u l a t o r - m e t a l ) . T h e cross sections of these structures are as s h o w n in F i g . A . 6 . T h e M O S gate capacitance, depicted in the center structure, is basically the gate-to-source c a p a c i t a n c e of a M O S F E T . T h e capacitance v a l u e is d e p e n d e n t o n t h e gate area. T h e o x i d e thickness is the s a m e as t h e gate o x i d e thickness in t h e M O S F E T s . This capacitor exhibits a large voltage d e p e n d e n c e . T o eliminate this p r o b l e m , an additional n+ i m p l a n t is r e q u i r e d to f o r m t h e b o t t o m plate of the capacitors, as s h o w n in t h e structure o n t h e right. B o t h these M O S capacitors are physically in contact w i t h t h e substrate, resulting in a large parasitic pn j u n c t i o n capacitance at the b o t t o m plate.
A.2.4 Resistors Resistors in integrated form are not very precise. T h e y can b e m a d e from various diffusion r e g i o n s as s h o w n in F i g . A . 5 . Different diffusion r e g i o n s h a v e different resistivity. T h e n well is usually u s e d for m e d i u m - v a l u e resistors, w h i l e t h e n+ a n d p+ diffusions are useful for l o w - v a l u e resistors. T h e actual resistance v a l u e c a n b e defined b y c h a n g i n g t h e length and w i d t h of diffused regions. T h e tolerance of t h e resistor v a l u e is v e r y p o o r ( 2 0 - 5 0 % ) , b u t t h e m a t c h i n g of t w o similar resistor values is quite g o o d ( 5 % ) . T h u s circuit designers should design circuits that exploit resistor m a t c h i n g a n d avoid designs that require a specific resistor value. All diffused resistors are self-isolated b y the r e v e r s e d - b i a s e d pn j u n c t i o n s . H o w e v e r , a serious d r a w b a c k for these resistors is that they are a c c o m p a n i e d b y a substantial parasitic j u n c t i o n capacitance, m a k i n g t h e m not very useful for high-frequency applications. T h e r e v e r s e d - b i a s e d pn j u n c t i o n s also exhibit a J F E T effect, leading to a variation in the resistance v a l u e as the applied voltage is c h a n g e d (a large v o l t a g e coefficient is undesirable). S i n c e t h e m o b i l i t i e s of carriers v a r y w i t h t e m p e r a t u r e , diffused resistors also exhibit a significant t e m p e r a t u r e coefficient. A m o r e useful resistor can b e fabricated u s i n g the polysilicon layer that is placed o n top of the thick-field o x i d e . T h e thin polysilicon layer p r o v i d e s better surface area m a t c h i n g and
Polyresistor <> j W o
n+ Diffusion resistor AAA
S.(
p + Diffusion resistor o - W - o
1
T h e interpoly capacitor exhibits near ideal characteristics but at t h e e x p e n s e of the inclusion of a s e c o n d polysilicon layer to t h e C M O S p r o c e s s . Since this capacitor is placed o n top of the thick-field oxide, parasitic effects are k e p t to a m i n i m u m . A third and less often u s e d capacitor is the j u n c t i o n capacitor. A n y pn j u n c t i o n u n d e r r e v e r s e d bias p r o d u c e s a depletion r e g i o n that acts as a dielectric b e t w e e n the p and the n r e g i o n s . T h e c a p a c i t a n c e is d e t e r m i n e d b y g e o m e t r y and d o p i n g levels a n d has a large voltage coefficient. T h i s t y p e of capacitor is often u s e d as a variactor (variable capacitor) for tuning circuits. H o w e v e r , this capacitor w o r k s only with reversed-bias voltages. F o r interpoly and M O S capacitors, t h e capacitance values can b e controlled to within 1%. Practical c a p a c i t a n c e values r a n g e from 0.5 p F to a few 10s of picofarads. T h e m a t c h i n g b e t w e e n similar-size capacitors can b e within 0 . 1 % . T h i s p r o p e r t y is e x t r e m e l y useful for designing p r e c i s i o n a n a l o g C M O S circuits.
A.2.6 pn Junction Diodes W h e n e v e r n - t y p e and £>-type diffusion r e g i o n s are p l a c e d n e x t to e a c h other, a pn j u n c t i o n d i o d e results. A useful structure is the n-well d i o d e s h o w n in F i g . A . 7 . T h e d i o d e fabricated in an n well can p r o v i d e a h i g h b r e a k d o w n voltage. This d i o d e is essential for the input c l a m p i n g circuits for protection against electrostatic discharge. T h e d i o d e is also very useful as an o n - c h i p t e m p e r a t u r e sensor b y m o n i t o r i n g the variation of its forward voltage d r o p .
A.2.7 BiCMOS Process FIGURE A . 5 Cross sections of resistors of various types available from a typical n-well CMOS process.
A n npn vertical bipolar transistor can b e integrated into t h e n-well C M O S process w i t h the addition of a />-base diffusion region (Fig. A . 8 ) . T h e characteristics of this device d e p e n d o n
£¿¿
A-9
APPENDIX A
A.2
VLSI F A B R I C A T I O N T E C H N O L O G Y
p-Base resistor
pn Junction diode
p Substrate
VLSI P R O C E S S E S
Pinched-base
FIGURE A . 7 A pn junction diode in an rc-well CMOS process; FIGURE A . 1 0 p-Base and pinched p-base resistors. npn Bipolar transistor
p-MOSFET
n-MOSFET
E -
B
C
b a s e w i d t h is limited b y t h e m i n i m u m photolithographic resolution, t h e p e r f o r m a n c e of this d e v i c e is not very g o o d — t y p i c a l l y , ¡3 of a r o u n d 10, with a l o w cutoff frequency.
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jäsA—-
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I
L
p Base
n Well I
j
p Substrate FIGURE A . 8 Cross-sectional diagram of a BiCMOS process.
the b a s e width and the emitter area. T h e b a s e width is determined by the difference i n j u n c t i o n depth b e t w e e n the n+ and the p - b a s e diffusions. T h e emitter area is d e t e r m i n e d b y t h e j u n c tion area of the n+ diffusion at t h e emitter. T h e n w e l l serves as the collector for the npn transistor. Typically, the npn transistor has a B in the r a n g e of 5 0 to 100 and a cutoff frequency greater t h a n 10 G H z . Normally, an n+ buried layer is used to reduce the series resistance of the collector, since the n well has a very high resistivity. However, this would further complicate the process with the introduction of p - t y p e epitaxy and one m o r e masking step. Other variations on the bipolar transistor include the u s e of a polyemitter and self-aligned base contact to minimize parasitic effects.
A.2.8 Lateral pnp Transistor T h e fact that m o s t B i C M O S p r o c e s s e s d o not h a v e o p t i m i z e d pnp transistors m a k e s circuit design s o m e w h a t difficult. H o w e v e r , in noncritical situations, a parasitic lateral pnp transistor can b e u s e d (Fig. A . 9 ) . In this case, the n w e l l serves as the n - b a s e region, with p+ diffusions as t h e emitter and the collector. T h e b a s e w i d t h is d e t e r m i n e d b y t h e separation b e t w e e n the t w o p+ diffusions. Since t h e d o p i n g profile is not optimized for t h e b a s e - c o l l e c t o r j u n c t i o n s , and b e c a u s e the
E
C
B
FIGURE A . 9 A lateral pnp transistor.
A.2.9 p-Base and Pinched-Base Resistors W i t h the additional p-base diffusion in the B i C M O S process, two additional resistor structures are available. T h e p - b a s e diffusion can b e used to form a straightforward p - b a s e resistor as shown in Fig. A. 10. Since the base region is usually of a relatively l o w doping level and with a moderate junction depth, it is suitable for medium-value resistors (a few kilohms). If a large resistor value is required, the pinched-base resistor can be used. In this structure, the p - b a s e region is encroached by the n+ diffusion, restricting the conduction path. Resistor values in the range of 10 kQ. to 100 ki2 can be obtained. As with the diffusion resistors discussed earlier, these resistors exhibit poor tolerance and temperature coefficients but relatively good matching.
A.2.10 The SiGe BiCMOS Process W i t h t h e a d v e n t of wireless applications, t h e d e m a n d for h i g h - p e r f o r m a n c e , high-frequency R F integrated circuits is enjoying a t r e m e n d o u s g r o w t h . T h e fundamental limitations of physical material properties initially p r e v e n t e d silicon-based t e c h n o l o g y from c o m p e t i n g with m o r e e x p e n s i v e I I I - V c o m p o u n d t e c h n o l o g i e s such G a A s . B y incorporating a controlled a m o u n t (typically n o m o r e than 15 m o l e %) of g e r m a n i u m (Ge) into crystalline silicon (Si), the e n e r g y b a n d g a p can b e altered. T h e specific concentration profile of the G e can b e e n g i n e e r e d in such a w a y that t h e energy b a n d g a p can b e gradually r e d u c e d from that in the p u r e Si r e g i o n to a l o w e r value in t h e S i G e region. This e n e r g y - b a n d g a p reduction p r o d u c e s a built-in electrical field that can assist t h e m o v e m e n t of carriers, h e n c e giving faster o p e r a t i n g s p e e d . T h e r e f o r e , S i G e b i p o l a r t r a n s i s t o r s c a n a c h i e v e significant h i g h e r cutoff f r e q u e n c y (e.g., in t h e 5 0 - 7 0 G H z r a n g e ) . A n o t h e r benefit is that t h e S i G e p r o c e s s is c o m p a t i b l e w i t h e x i s t i n g S i - b a s e d fabrication t e c h n o l o g y , e n s u r i n g a v e r y f a v o r a b l e cost/ performance ratio. T o take advantage of the SiGe material characteristics, the basic bipolar transistor structure must also b e modify to further reduce parasitic capacitance (for higher speed) and to improve the injection efficiency (for higher gain). A symmetrical bipolar device structure is shown in Fig. A . 1 1 . T h e device m a k e s use of trench isolation to reduce the collector sidewall capacitance between the n-well/n+ buried layer and the p substrate. T h e emitter size and the.p+ base contact size are defined b y a self-aligned process to minimize the base-collector junction (Miller) capacitance. This type of device is called a heterojunction bipolar transistor (HBT), since the emitter-base junction is formed from two different types of material, polysilicon emitter and SiGe base. T h e injection efficiency is significantly better than a homojunction device (as in a
A-11
A - 1 2
?"
'<
APPENDIX A
VLSI F A B R I C A T I O N T E C H N O L O G Y
SiGe p base
n+ Poly silicon emitter
A.3
VLSI L A Y O U T
p+ Poly silicon
Polysilicon refill
Trench isolation
FIGURE A . 1 1 Cross-sectional diagram of a symmetrical self-aligned npn SiGe heterojunction bipolar transistor (HBT). conventional BJT). Coupled with the fact that base width is typically only around 50 nm, it is easy to achieve a current gain of more than 100. In addition, not shown in Fig. A . l 1, multiple lay ers of metallization can be used to further reduce the device size and interconnect resistance. All these device features are necessary to complement the speed performance of the SiGe material. V77Á Metal 1
-
! A.3
VLSI LAYOUT
E a c h d e s i g n e d circuit s c h e m a t i c m u s t b e transformed into a layout that consists of t h e g e o metric representation of the circuit c o m p o n e n t s and interconnections. W i t h the advent of c o m p u t e r - a i d e d design ( C A D ) tools, m a n y of the c o n v e r s i o n steps from s c h e m a t i c to layout can b e carried out semi- or fully automatically. H o w e v e r , any g o o d m i x e d - s i g n a l I C designer m u s t h a v e practiced full-custom l a y o u t at o n e p o i n t or another. T o illustrate such a p r o c e d u r e w e will consider t h e layout of a C M O S inverter. Similar to the requirement in a printed-circuit-board layout to reduce crossover paths, the circuit m u s t first be "flattened" and redrawn to eliminate any interconnection crossovers. E a c h process is m a d e up of a specific set of m a s k i n g layers. In this case, 7 layers are used. E a c h layer is usually assigned a u n i q u e color and fill pattern for ease of identification on a computer screen or on a printed color plot. T h e layout begins with the p l a c e m e n t of the transistors. For illustration purposes (Fig. A . 12), the p- and re-MOSFETs are placed in arrangements similar to that of the schematic. In practice, the designer is free to choose the most area-efficient layout that she can identify. T h e M O S F E T s are defined b y the active areas overlapped b y the "Poly 1" layer. T h e M O S channel length and width are defined b y the width of the "Poly 1" strip and that of the active region, respectively. T h e p - M O S F E T is enclosed in an re well. For more com plex circuits, multiple re wells can b e used for different groups of p - M O S F E T s . T h e re-MOSFET is enclosed b y the re+ diffusion m a s k to form the source and drain, while the />-MOSFET is enclosed b y the p+ diffusion mask. Contact holes are placed in regions that require connection to the metal layer. Finally, the " M e t a l 1" layer completes the interconnections. T h e c o r r e s p o n d i n g cross-sectional d i a g r a m of t h e C M O S inverter, v i e w e d along the A A ' plane is s h o w n in Fig. A. 13. T h e p o l y - S i gates for b o t h transistor are c o n n e c t e d together to f o r m t h e input terminal, X. T h e drains of b o t h transistors are tied together via " M e t a l 1" to form the o u t p u t terminal, Y. T h e sources of t h e re- a n d p - M O S F E T s are c o n n e c t e d to G N D and V , respectively. N o t e that butting contacts consisting of side-by-side n+lp+ diffusions are u s e d to tie the b o d y potential of t h e re- and ^ - M O S F E T s to t h e appropriate v o l t a g e levels. DD
FIGURE A . l 2 A CMOS inverter schematic and its layout.
FIGURE A . l 3 The cross section along the plane AA' of a CMOS inverter. W h e n the layout is completed, the circuit must b e verified using appropriate C A D tools including circuit extractor, design-rule checker ( D R C ) , and circuit simulator. O n c e these verifi cations have been satisfied, the design can be "taped out" to a m a s k - m a k i n g facility. A pattern generator ( P G machine) can then draw the geometries on a glass or quartz photoplate using electronically driven shutters. Layers are drawn one-by-one onto different photoplates. W h e n these plates h a v e been developed, clear and dark patterns depicting the geometries on the layout will appear. A set of the photoplates for the C M O S inverter example is s h o w n in Fig. A. 14. D e p e n d i n g on whether the drawn geometries are meant to b e opened as w i n d o w s or kept as pat terns, the plates can be "positive" or "negative" images with c l e a r or d a r k fields. Note that these layers m u s t be processed in sequence. In the steps of this sequence, they must be aligned within very fine tolerances to form the transistors and interconnections. Naturally, the greater the n u m ber of layers, the m o r e difficult it is to maintain the alignment. A process with m o r e layers also requires better photolithography equipment and possibly results in lower yield. Hence, each additional m a s k will b e reflected in an increase in the final cost of the I C chip.
A-14
APPENDIX A
(a) ft Well
VLSI F A B R I C A T I O N T E C H N O L O G Y
(b) Active region
(c) Poly 1
(d) ft+ Diffusion
, Photographic plate
•
Two-Port Network Parameters INTRODUCTION A t v a r i o u s points t h r o u g h o u t t h e text, w e m a k e u s e of s o m e of t h e different possible w a y s to characterize linear t w o - p o r t n e t w o r k s . A s u m m a r y of this topic is p r e s e n t e d in this a p p e n d i x .
S.1 CHARACTERIZATION OF LINEAR TWO-PORT NETWORKS , (e) p+ Diffusion
(f) Contact hole
(g) Metal 1
FIGURE A.I 4 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate: (a), (d), (e), and (f) are dark-field masks; (b), (c), and (g) are clear-field masks.
A two-port n e t w o r k (Fig. B . 1) has four port variables: V I V , and I . If the two-port network is linear, w e can u s e t w o of the variables as excitation variables and t h e other t w o as r e s p o n s e variables. F o r instance, the n e t w o r k can b e excited b y a v o l t a g e Vj at port 1 and a v o l t a g e V at port 2, a n d t h e t w o currents, I and I , can b e m e a s u r e d to represent t h e n e t w o r k response. In this case Vj and V are independent variables and I and I are dependent variables, a n d the n e t w o r k operation can b e described b y t h e t w o equations h
2
x
x
h h
SUMMARY VLSI technologies. Interested readers should consult reference textbooks on this subject for more detailed discussions.
2
2
2
2
This appendix presented an overview of the various as pects of VLSI fabrication procedures. This includes com ponent characteristics, process flows, and layouts. This is by no means a complete account of state-of-the-art
h
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12
22
2
2
2
(B.i) (B.2)
H e r e , the four p a r a m e t e r s y , y , y , and y are a d m i t t a n c e s , and their values c o m p l e t e l y characterize t h e linear t w o - p o r t n e t w o r k . D e p e n d i n g o n w h i c h t w o of t h e four port variables are u s e d to represent the n e t w o r k excitation, a different set of equations (and a c o r r e s p o n d i n g l y different set of parameters) is o b t a i n e d for characterizing t h e n e t w o r k . W e shall p r e s e n t t h e four p a r a m e t e r sets c o m m o n l y u s e d in electronics. n
Linear two-port network
12
2l
22
+ V
2
FIGURE B.I The reference directions of the four port variables in a linear two-port network.
DIX B
TWO-PORT NETWORK
B.l
PARAMETERS
T h e definition of y
B.1.1 y Parameters {
NETWOR
can b e obtained from Eq. (B.2) as
21
T h e short-circuit admittance (or y-parameter) characterization is based on exciting the network b y V and V , as s h o w n in Fig. B.2(a). T h e describing equations are E q s . ( B . l ) and (B.2). T h e four admittance parameters can b e defined according to their roles in E q s . ( B . l ) and (B.2). Specifically, from E q . ( B . l ) w e see that y „ is defined as
C H A R A C T E R I Z A T I O N O F LINEAR T W O - P O R T
yr
(B.5)
2
Vi
2
T h u s y represents t r a n s m i s s i o n from port 1 to port 2. If port 1 is t h e input port and port 2 t h e output port of an amplifier, then y provides a m e a s u r e of the forward gain o r transmis sion. F i g u r e B . 2 ( d ) illustrates t h e definition and the m e t h o d for m e a s u r i n g y . T h e p a r a m e t e r y c a n b e defined, b a s e d o n Eq. (B.2), as 2l
2l
(B.3)
2 1
2 2
T h u s >•„ is the input a d m i t t a n c e at port 1 with port 2 short-circuited. T h i s definition is illus
(B.6)
trated in F i g . B.2(b), w h i c h also p r o v i d e s a c o n c e p t u a l m e t h o d for m e a s u r i n g t h e input short-circuit a d m i t t a n c e y . T h e definition of y can b e o b t a i n e d from Eq. ( B . l ) as
T h u s y is t h e a d m i t t a n c e l o o k i n g into port 2 w h i l e port 1 is short-circuited. F o r amplifiers, y is the o u t p u t short-circuit admittance. F i g u r e B.2(e) illustrates the definition a n d t h e m e t h o d for m e a s u r i n g y .
n
2 2
12
2 2
22
03.4)
v,=o
B.1.2 z Parameters
T h u s y represents t r a n s m i s s i o n from port 2 to port 1. S i n c e in amplifiers, port 1 represents the input p o r t and port 2 t h e output port, y represents internal feedback in t h e network. F i g u r e B.2(c) illustrates t h e definition and t h e m e t h o d for m e a s u r i n g y . 1 2
n
T h e open-circuit i m p e d a n c e (or z-parameter) characterization of t w o - p o r t n e t w o r k s is b a s e d o n exciting t h e n e t w o r k b y f and I , as s h o w n in Fig. B.3(a). T h e describing equations are 2
12
Zuh
+
2
(B.7)
Z2lh
+ ^22-^2
(B.8)
zI l2
Two-port
CD
NETWORK
+
.Two-port ;
h
-
yi\V\
+
V F 2 2
NELWNRK
v
\ = z Ii+
2
zI
u
(a)
V = z I, 2
2t
]2
+
2
zI 22
7
(a)
(b)
(c) (b)
^21
(d)
(e)
FIGURE B.2 Definition and conceptual measurement circuits for the y parameters.
Z
22
h ' i2 = o (d)
(e)
FIGURE B.3 Definition and conceptual measurement circuits for the z parameters.
B.I DIX B
C H A R A C T E R I Z A T I O N O F LINEAR T W O - P O R T N E T W O R K S
TWO-PORT NETWORK PARAMETERS
O w i n g to t h e duality b e t w e e n t h e z- a n d ^ p a r a m e t e r characterizations, w e shall n o t give a detailed discussion of z p a r a m e t e r s . T h e definition a n d m e t h o d of m e a s u r i n g each of t h e four
T h u s , h is t h e input i m p e d a n c e at port 1 w i t h port 2 short-circuited. T h e p a r a m e t e r h represents t h e r e v e r s e or f e e d b a c k v o l t a g e ratio of the n e t w o r k , m e a s u r e d with t h e input port open-circuited. T h e forward-transmission p a r a m e t e r h represents t h e current gain of t h e n e t w o r k w i t h t h e output p o r t short-circuited; for this reason, h is called t h e short-circuit current gain. Finally, h is t h e output a d m i t t a n c e with t h e input port open-circuited. n
l2
21
z p a r a m e t e r s a r e g i v e n in F i g . B . 3 .
21
22
B.1.3 h Parameters
T h e definitions a n d conceptual measuring setups of the h parameters are given i n Fig. B.4.
T h e h y b r i d ( o r re-parameter) characterization of t w o - p o r t n e t w o r k s is b a s e d o n exciting t h e n e t w o r k b y l a n d V , as s h o w n i n F i g . B . 4 ( a ) (note t h e r e a s o n behind t h e n a m e hybrid). r
2
The
B.1.4 g Parameters T h e i n v e r s e - h y b r i d (or g - p a r a m e t e r ) c h a r a c t e r i z a t i o n of t w o - p o r t n e t w o r k s is b a s e d o n
describing equations are
e x c i t a t i o n of the n e t w o r k b y Vi a n d 7 , as s h o w n in Fig. B.5(a). T h e describing equations a r e 2
V, = h I,+h V n
/,
12
= hI 2l
l
(B.9)
2
+hV 22
(B.ll)
(B.10)
2
Vi
=
(B.12)
82iVi+g I 22
2
from w h i c h t h e definition of t h e four h p a r a m e t e r s can b e o b t a i n e d a s V
h" 1 1 --
T h e definitions a n d c o n c e p t u a l m e a s u r i n g setups are given in F i g . B . 5 .
h h
l
— ' l
B.1.5 Equivalent-Circuit Representation
i «22 =
0
A two-port network can b e represented b y an equivalent circuit based on the set of parameters u s e d for its characterization. Figure B . 6 shows four possible equivalent circuits corresponding
^
V , j,=o
i,=o
v
2
Jw o-port network
V, ®
••h h
+
hV
re,,/, +
hV
u
n
22
v
I\ =8u \
2
V
2
V\ o 1
'
22
2
(D
0
_ v\ x
Y\
gI
o
~V\ ®
hn -
2 = gl\ Vi + (a)
(a) o
+ g\ih
hn - y \
0
:
(c)
(c)
(b)
- | h ' v, = o
h 0
h(X)
o
®
® o
0
V£21 hn
(d)
-
77
Vl I / = 0 2
(e)
FIGURE B .4 Definition and conceptual measurement circuits for the h parameters.
(d)
g22
'2
1
V,
=0
(e)
FIGURE B.S Definition and conceptual measurement circuits for the g parameters.
APPENDIX B
TWO-PORT NETWORK PARAMETERS
PROBLEMS
B-7
PROBLEMS B . l (a) An amplifier characterized by the A-parameter equi valent circuit of Fig. B.6(c) is fed with a source having a voltage V and a resistance R , and is loaded in a resistance R . Show that its voltage gain is given by s
s
YJ
V
s
=
L
~h + R )(h +
B.3 Figure PB.3 shows the high-frequency equivalent cir cuit of a BJT. (For simplicity, r has been omitted.) Find the y parameters.
2l
(h
u
s
22
the current in the output is 0.2 mA and the voltage measured at the input is 2.5 mV. Find values for the h parameters of this network.
x
l/R )-h h L
l2
2l
(b) Use the expression derived in (a) to find the voltage gain of the transistor in Exercise B . l for R = 1 k Q and R = lOkil s
L
B . 2 The terminal properties of a two-port network are mea sured with the following results: With the output shortcircuited and an input current of 0.01 mA, the output current is 1.0 mA and the input voltage is 26 mV. With the input open-circuited and a voltage of 10 V applied to the output,
(d) FIGURE B.6 Equivalent circuits for two-port networks in terms of (a) y, (b) z, (c) h, and (d) g parameters. to t h e four p a r a m e t e r types just discussed. E a c h of these equivalent circuits is a direct pictorial representation of the c o r r e s p o n d i n g t w o e q u a t i o n s describing t h e n e t w o r k in t e r m s of the particular p a r a m e t e r set. Finally, it should b e mentioned that other parameter sets exist for characterizing two-port n e t w o r k s , b u t these are not d i s c u s s e d or u s e d in this b o o k .
B.T Figure E B . 1 shows the small-signal equivalent-circuit model of a transistor. Calculate the values h parameters. m
Ans. h
u
4
= 2.6 k Q ; h
r. - 1 0 0 il
l2
«'
= 2.5 x U F ; h • • Id
s
2l
= 100; A , , = 2 x 10~ Q C
„ = 40 mA V
F I G U R E EB.'i
F I G U R E PB.3
(b)
(With independent sources reduced to zero)
Some Useful Network Theorems
(c) FIGURE C I
-o a' Z,
(A)
Thévenin's theorem.
INTRODUCTION In this appendix w e review three network theorems that are useful in simplifying the analysis of electronic circuits: T h é v e n i n ' s theorem, N o r t o n ' s theorem, and the source-absorption theorem.
' ; C.1
THEVENIN'S THEOREM (b)
T h e v e n i n ' s t h e o r e m is u s e d to represent a part of a n e t w o r k by a voltage source V, and a series i m p e d a n c e Z„ as s h o w n in F i g . C . l . F i g u r e C . l ( a ) s h o w s a n e t w o r k divided into two parts, A a n d B . In Fig. C . l ( b ) part A of the n e t w o r k h a s b e e n replaced b y its T h e v e n i n equivalent: a v o l t a g e source V, and a series i m p e d a n c e Z . F i g u r e C . l ( c ) illustrates h o w V is to b e d e t e r m i n e d : S i m p l y open-circuit the t w o terminals of n e t w o r k A and m e a s u r e (or cal culate) t h e voltage that appears b e t w e e n these t w o terminals. T o d e t e r m i n e Z, w e reduce all external (i.e., i n d e p e n d e n t ) sources in n e t w o r k A to z e r o b y short-circuiting v o l t a g e sources and open-circuiting current sources. T h e i m p e d a n c e Z, will b e equal to the input i m p e d a n c e of n e t w o r k A after this reduction h a s b e e n performed, as illustrated in F i g . C . l ( d ) . t
C.2
(With independent sources reduced to zero)
t
(c)
id)
FIGURE C.2 Norton's theorem.
NORTON'S THEOREM
N o r t o n ' s theorem is the dual of T h é v e n i n ' s theorem. It is used to represent a part of a network b y a current source /„ and a parallel i m p e d a n c e Z„, as s h o w n in Fig. C.2. F i g u r e C.2(a) s h o w s a n e t w o r k divided into t w o parts, A and B . In F i g . C.2(b) part A has b e e n r e p l a c e d by its N o r t o n ' s equivalent: a current source /„ and a parallel i m p e d a n c e Z . T h e N o r t o n ' s cur rent s o u r c e l c a n b e m e a s u r e d (or calculated) as s h o w n in F i g . C.2(c). T h e terminals of the n e t w o r k b e i n g r e d u c e d (network A ) are shorted, and the current /„ will b e equal simply to the short-circuit current. T o determine the i m p e d a n c e Z„ w e first reduce the external excitation in n e t w o r k A to zero: T h a t is, w e short-circuit i n d e p e n d e n t v o l t a g e sources and open-circuit i n d e p e n d e n t c u r r e n t s o u r c e s . T h e i m p e d a n c e Z w i l l b e e q u a l t o t h e i n p u t i m p e d a n c e of n e t w o r k A after this source-elimination p r o c e s s has taken place. T h u s the N o r t o n i m p e d a n c e Z„ is equal to the T h é v e n i n i m p e d a n c e Z . Finally, n o t e that / „ = V /Z, where Z=Z = Z. n
Figure C.3(a) shows a bipolar junction transistor circuit. with the terminals labeled E (emitter), B (base), and C nected to the dc power supply V via the voltage divider connected to the dc supply V through R and to ground wish to apply Thevenin's theorem to reduce the circuit. +
+
3
The transistor is a three-terminal device (collector). As shown, the base is con composed of R and R . T h e collector is through R . To simplify the analysis we x
2
4
n
Solution +
Thevenin's theorem can be used at the base side to reduce the network composed of V , R R to a dc voltage source V ,
h
2
BB
n
t
t
n
t
V
BB
=
R
2
A
V
R +R x
2
and
APPENDIX C
SOME USEFUL NETWORK
THEOREMS C3
SOURCE-ABSORPTION THEOREM
H. Figure C.5(a) shows the small-signal equivalent-circuit model of a transistor. W e want to find the -eststance * "looking into" the emitter termmal E - t h a t is, the resistance between t i e m i t t md ground—with the base B and collector C grounded. i n
K.
B
91
(a)
B
C
(b)
FIGURE C.3 Thévenin's theorem applied to simplify the circuit of (a) to that in (b). (See Example C.l.) and a resistance R , B
R — 7^|//i?2 B
where // denotes "in parallel with." At thé collector side, Thévenin's theorem can b e applied to 1
reduce the network composed of V ", R , and R to a dc voltage source V , 3
4
CC
( a )
+
V
= V
cc
(b)
RA, R
+ R
3
4
and a resistance i?<-
FIGURE C.5 Circuit for Example C.2.
Solution R
=
C
R IIR 3
A
F r o m Fig. C.5(a) w e see that the voltage v„ will b e equal to ~v . Thus looking between E and ground w e see a resistance r in parallel with a current source drawing a current g v away from terminal E. T h e latter source can be replaced by a resistance ( l / g ) , resulting in the input resis tance R given by e
T h e reduced circuit is shown in Fig. C.3(b).
n
m
e
m
in
f |
C.3
SOURCE-ABSORPTION THEOREM as illustrated in Fig. C.5(b).
Consider the situation s h o w n in Fig. C.4. In t h e course of analyzing a network w e find a con trolled current source I appearing between t w o nodes w h o s e voltage difference is the control x
ling voltage V . T h a t is, l = g V x
x
m
w h e r e g is a c o n d u c t a n c e . W e c a n r e p l a c e this controlled
x
m
source b y a n i m p e d a n c e Z = V /I x
x
x
= l/g , m
a s s h o w n in F i g . C.4, b e c a u s e t h e current
d r a w n b y this i m p e d a n c e will b e equal t o t h e current of the controlled source that w e h a v e replaced.
EXERCISES C.1 A source is measured and found to have a.lO-V open-circuit voltage and to provide 1 m \ into a short circuit. Calculate its Thevenin and Norton equivalent source parameters, .s / Ans.A-, - 10 V; 2, = / „ - 10 k i i ; /„ = I niA s ? ?
C.2 In (he circuit shown in Fig. EC.2 the diode has a voltage drop V',„ - 0.7 V. Use T h e v e n u f s theorem t o simplify the circuit and hence calculate the diode current / „ . Ans. 1 tnA FIGURE C.4 The source-absorption theorem.
t-^
CS
!
APPENDIX C
SOME USEFUL NETWORK
THEOREMS PROBLEMS
1 kft
+20 V
l kn
A
r
l kn
-vw-
- A W
J' •"•)
-o
+ 10 V |
•6 kii In
i kn
l kn.
l k n * 2 kn:
Diode
f-vvv4.9 kO
+
^ 4 k O
II
F I G U R E PC.4
V
D
• FIGURE EC.2 C.3 The two-terminal device M in the circuit of Fig. E C . 3 has a current I = 1 m A independent of the volt age V across it. Use N o r t o n ' s theorem to simplify the circuit and hence calculate the voltage V . M
M
C.6 Figure PC.6(a) shows the circuit symbol of a device known as the p-channel junction field-effect transistor (JFET). As indicated, the JFET has three terminals. When the gate ter minal G is connected to the source terminal S, the two-terminal device shown in Fig. PC.6(b) is obtained. Its i-v characteristic is given by
M
where I and V are positive constants for the particular JFET. Now consider the circuit shown in Fig. PC.6(c) and let V = 2 V and I = 2 mA. For V = 10 V show that the JFET is operating in the constant-current mode and find the voltage across it. What is the minimum value of V for which this mode of operation is maintained? For V = 2 V find the values of I and V. oss
P
+
P
DSS
+
+
Ans. 5 V
i =
\2l
I
for v<
n
V
V
P
t
+20 V
for v > V
'DSS
A
P
lOkfi
S
(Source) i T
^10
G (Gate)
+
mm Vu.
kit
+
2.5 k n
c
:
F I G U R E EC.3
D ' (Drain) (a) FIGURE PC.6
C. 1 Consider the Thevenin equivalent circuit characterized by V, and Z,. Find the open-circuit voltage V and the shortcircuit current (i.e., the current that flows when the terminals are shorted together) / . Express Z, in terms of V and I . oc
What output voltage results if it is loaded with 1 kD? Cal culate this two ways: directly and using your Thevenin equivalent.
C.2 Repeat Problem C.l for a Norton equivalent circuit characterized by /„ and Z .
C.4 Find the output voltage and output resistance of the cir cuit shown in Fig. PC.4 by considering a succession of Thevenin equivalent circuits.
C.3 A voltage divider consists of a 9-k£2 resistor con nected to +10 V and a resistor of 1 kQ connected to ground. What is the Thevenin equivalent of this voltage divider?
C . 5 Repeat Example C.2 with a resistance R connected between B and ground in Fig. C.5 (i.e., rather than directly grounding the base B as indicated in Fig. C.5).
sc
oc
sc
n
B
2.5 k n
+
a d
(b)
(c)
fi
D.l
R
4
|| [R + (R, ||
EVALUATING THE TIME CONSTANT
R )]
3
2
w\
Single-Time-Constant Circuits
\Ri
+ Rj
\ R
4
+ R
+
3
2
)
)
C
INTRODUCTION Single-time-constant ( S T C ) circuits are those circuits that are c o m p o s e d of, or can b e r educed to, o n e reactive c o m p o n e n t (inductance or capacitance) a n d o n e resistance. A n S T C circuit formed of an i n d u c t a n c e L a n d a resistance R h a s a t i m e c o n s t a n t T = L/R.
T h e time constant
011
otrS's
f
t0th£STC
(c)
j ; ^ °^ " " ^ ~ *
the repeated apphcation
T of an S T C circuit c o m p o s e d of a capacitance C a n d a r e s i s t a n c e R is given by r= CR. A l t h o u g h S T C circuits are quite s i m p l e , t h e y p l a y an i m p o r t a n t r o l e in t h e d e s i g n a n d a n a l y s i s of linear a n d digital circuits. F o r instance, the analysis of an amplifier circuit can usually b e r e d u c e d to the analysis of o n e or m o r e S T C circuits. F o r this r e a s o n , w e will r e v i e w in this a p p e n d i x the p r o c e s s of evaluating the r e s p o n s e of S T C circuits to sinusoidal and other i n p u t signals such as step a n d p u l s e w a v e f o r m s . T h e latter signal w a v e f o r m s are e n c o u n t e r e d i n s o m e amplifier applications but are m o r e i m p o r t a n t in sw i t ch i n g circuits,
source, o p e n it. T h e n if t h e circuit h a s o n e r e a c t i v e c o m p o n e n t a n d a n u m b e r of resistances, " g r a b h o l d " of t h e t w o t e r m i n a l s of the reactive c o m p o n e n t ( c a p a c i t a n c e or i n d u c t a n c e ) a n d find t h e e q u i v a l e n t r e s i s t a n c e R seen b y t h e c o m p o n e n t . T h e t i m e c o n s t a n t is then either L/R or Ci? . A s an e x a m p l e , i n the circuit o f F i g . D . l (a) w e find t h a t t h e capacitor C " s e e s " a r e s i s t a n c e R i n parallel w i t h t h e series c o m b i n a t i o n of R a n d (R in parallel w i t h R ). T h u s eq
eq
eq
4
3
2
x
including digital circuits.
/? = /? //[/? + ( « / / « ) ] eq
a n d the time constant is
' j D.1
EVALUATING THE TIME CONSTANT
T h e first step i n the analysis of an S T C circuit is to e v a l u a t e its t i m e constant r.
4
3
2
1
CR . eq
In s o m e c a s e s it m a y b e f o u n d that the circuit h a s o n e r e s i s t a n c e a n d a n u m b e r of c a p a c itances o r i n d u c t a n c e s . I n s u c h a c a s e t h e p r o c e d u r e s houl d b e inverted; that is, " g r a b h o l d " of the resistance t e r m i n a l s a n d find t h e e q u i v a l e n t c a p a c i t a n c e C , or e q u i v a l e n t i n d u c t a n c e L , s e e n b y this r e s i s t a n c e . T h e t i m e c o n s t a n t is t h e n f o u n d as C R o r L /R. T h i s is illus trated i n E x a m p l e D . 2 . s q
e q
eq
i n d u c e the circuit in Fig. D . l ( a ) to an S T C circuit, and find its time constant. Find the time constant of the circuit in Fig. D.2.
Solution I lie reduction process is illustrated in Fig. D . l and consists of repeated applications of Thevenin's lhcorem. F r o m the final circuit (Fig. D . l c ) , we obtain the time constant as T=C{R //[R i
3
+
(R //R ))} l
2
D.1.1 Rapid Evaluation of r In m a n y i n s t a n c e s , it will b e i m p o r t a n t t o b e able to evaluate r a p i d l y the t i m e constant T of a
4> C
' 2
R
<
V
0
g i v e n S T C circuit. A simple m e t h o d for a c c o m p l i s h i n g this goal consists first of reducing the excitation to zero; that is, if the excitation is b y a voltage source, short it, and if b y a current
F I G U R E D . 2 Circuit for Example D.2.
tq
1
D.2 APPENDIX D S I N G L E - T I M E - C O N S T A N T
• ' Solution
. ,.
|
of the circuits in Fig. D.3(a) and D.3(b). T h e "trick" employed to obtain the arrangement in
I
Fig. D.3(b) is a very useful one.
After reducing the excitation to zero by short-circuiting the voltage source w e see that the résis-
j
ta
|
«
CLASSIFICATION O F STC CIRCUITS
CIRCUITS
sees" an é g a l e n t capacitance Q
C , Thus the time constant n s given by
+
x={C
the response m a y b e obtained using the principle of superposition. Specifically, the output
+ C )R
l
Application of T h e v e n i n ' s theorem to t h e circuit to the left of the line XX' and then to the circuit to t h e right of that line result in t h e circuit of Fig. D.3(c). Since this is a linear circuit,
2
voltage v will b e t h e sum of the t w o components v 0
, „ „ ç t p r-IRNIIT h a s m o r e t h a n o n e resistance a n d m o r e than o n e
and v . T h e first component, v , is t h e
ol
02
o l
output due to t h e left-hand-side voltage source with t h e other voltage source reduced to zero. T h e circuit for calculating v
ol
is shown in Fig. D.3(d). It is an S T C circuit with a time constant
given b y t h e circuit, as illustrated b y E x a m p l e D . 3 .
1 = (Ci + C )(7? //A ) 1
2
Similarly, the second component v
02
1
2
is the output obtained with the left-hand-side voltage source
reduced to zero. It can b e calculated from the circuit of Fig. D.3(e), which is an STC circuit with of the circuit in Fig. D.3(a) can b e obtained using the method of
Here w e show that the response
the same time constant x. Finally, it should b e observed that the fact that the circuit is an STC one can also b e ascertained b y setting the independent source Vj in Fig. D.3(a) to zero. Also, the time constant is then
analysis of S T C circuits.
immediately obvious.
Solution
. ,, j • i~ m
t
t „ Bin r> Ifht w e show the circuit excited by two sep-
D.2
1 Vl
©
CLASSIFICATION OF STC CIRCUITS
S T C circuits c a n b e classified into t w o categories, low-pass
( L P ) a n d high-pass
( H P ) types,
w i t h e a c h c a t e g o r y d i s p l a y i n g distinctly different signal r e s p o n s e s . T h e task of finding
c.
X
w h e t h e r a n S T C circuit is of L P o r H P t y p e m a y b e a c c o m p l i s h e d i n a n u m b e r of w a y s , t h e simplest of w h i c h u s e s t h e f r e q u e n c y - d o m a i n r e s p o n s e . Specifically, l o w - p a s s circuits p a s s
+ :C
:R*
2
d c (i.e., signals w i t h z e r o frequency) and attenuate h i g h frequencies, with t h e t r a n s m i s s i o n
'Ri
v
0
b e i n g z e r o at co = °°. T h u s w e c a n test for t h e c i r c u i t t y p e e i t h e r at ft) = 0 o r at co = °°. A t
1
co = 0 capacitors s h o u l d b e replaced b y open circuits (1/jcoC=°°) a n d inductors should b e
X'
replaced b y short circuits
(a)
(jcoL -
0). T h e n if t h e output is zero, the circuit is of t h e high-pass
type, while if t h e output is finite, the circuit is of t h e low-pass type. Alternatively, w e m a y test
(b)
at co - °° b y replacing capacitors b y short circuits (1/jcoC - 0 ) and inductors b y open circuits
(JcoL = (*I H
R
2)
I
X
oo).
T h e n if the output is finite, t h e circuit is of t h e H P type, w h e r e a s if the output is
zero, t h e circuit is of the L P type. In Table D . l , w h i c h provides a s u m m a r y of these results, s.c. stands for short circuit and o.c. for open circuit. F i g u r e D . 4 s h o w s e x a m p l e s of l o w - p a s s S T C circuits, a n d F i g . D . 5 s h o w s e x a m p l e s of high-pass S T C circuits. F o r e a c h circuit w e h a v e indicated t h e input a n d output variables of interest. N o t e that a g i v e n circuit c a n b e of either category, d e p e n d i n g o n t h e i n p u t a n d outp u t variables. T h e reader is u r g e d to verify, u s i n g t h e rales of T a b l e D . l , that t h e circuits of Figs. D . 4 a n d D . 5 a r e correctly classified.
Rules for Finding t h e T y p e of STC Circuit Ci Test At
ÛJ=0 (d) FIGURE D.3 The response of the circuit in (a) can be responses of the circuits in (d) and (e).
(e) found by superposition, that is, by summing the
Replace
C b y o.c.
Circuit Is HP If
output is finite
output is zero
output is zero
output is finite
L by s.c. C b y s.c.
C0=
Circuit Is LP If
oo
L by o.c.
D-4
D.3 D-5
APPENDIX D
SINGLE-TIME-CONSTANT
FREQUENCY RESPONSE OF STC
CIRCUITS
CIRCUITS
L
R D.2
R>
Classify the following circuits as S T C high-pass or low-pass: Fig. D.4(a) with output i in C to ground; a
Fig, D.4(b) with output i in R to ground; Fig. D.4(d) with output i in C to ground; Fig. D.4(e) with 0
v
0
W / ( ±
0
output i in R to ground; Fig. D.5(b) with output i in L to ground; and Fig. D.5(d) with output % across C. 0
Q
Ans. I l l ' : I P : 111': 111': I . I ' . L I '
(c)
(b)
(a)
D.3
R.
FREQUENCY RESPONSE OF STC CIRCUITS
D.3.1 Low-Pass Circuits (e)
(d)
T h e transfer function T(s) of an S T C l o w - p a s s circuit a l w a y s c a n b e written in the f o r m
FIGURE D.4 STC circuits of the low-pass type.
7*0) =
R WVr-
I
-4—vw-
which, for physical-frequencies, w h e r e s = jco, b e c o m e s
+ v, (+)
R$
(D.l)
T(jco)
=
v
0
-
-
1 +j(co/
(D.2) co ) 0
w h e r e K is t h e m a g n i t u d e of the transfer function at co = 0 (dc) and C0Q is defined b y (c)
(b)
(a)
/o
I )
L'
1
1 (f)
(e)
(d)
C0Q =
1/T
w i t h T b e i n g the t i m e constant. T h u s the m a g n i t u d e r e s p o n s e is g i v e n b y \T(j(0)\
K
=
Vl +
(D.3)
(co/co f 0
a n d t h e p h a s e r e s p o n s e is given by _ 1
ep(co) = - t a n ( f t ) / © )
(D.4)
0
F i g u r e D . 6 sketches the m a g n i t u d e a n d p h a s e r e s p o n s e s for an S T C l o w - p a s s circuit. T h e m a g n i t u d e r e s p o n s e s h o w n in Fig. D . 6 ( a ) is s i m p l y a g r a p h of t h e function in E q . (D.3).
F I G U R E D.5 STC circuits of the high-pass type.
T h e m a g n i t u d e is n o r m a l i z e d w i t h respect to t h e d c gain K a n d is e x p r e s s e d in decibels; that is, t h e plot is for 2 0 \og\T{jco)/K\,
w i t h a l o g a r i t h m i c scale u s e d for the frequency axis.
F u r t h e r m o r e , the frequency variable h a s b e e n n o r m a l i z e d w i t h respect to co . A s s h o w n , t h e 0
m a g n i t u d e c u r v e is closely defined by t w o straight-line a s y m p t o t e s . T h e low-frequency a s y m p t o t e is a h o r i z o n t a l straight line at 0 d B . T o find the slope of the h i g h - f r e q u e n c y
D.1 Find the time constants for the circuits shown in Fig. E D . 1.
a s y m p t o t e c o n s i d e r E q . (D.3) a n d let co/ co > 1, resulting in 0
i
!
;
Ans.(a) - ^" -
< b )
(Ä //«2) 1
|rufi»| CO
-o
It follows that if co doubles in value, the m a g n i t u d e is halved. O n a logarithmic frequency axis,
+
-VV\
0
doublings of co represent equally spaced points, with each interval called an octave. Halving the magnitude function corresponds to a 6-dB reduction in transmission (20 log 0.5 = - 6 dB). T h u s the slope of the lrigh-frequency asymptote is - 6 dB/octave. This can b e equivalently expressed as - 2 0 dB/decade, w h e r e " d e c a d e " indicates an increase in frequency b y a factor of 10.
(a)
(b)
T h e t w o straight-line a s y m p t o t e s of the m a g n i t u d e - r e s p o n s e c u r v e m e e t at the " c o r n e r f r e q u e n c y " or " b r e a k f r e q u e n c y " co . T h e difference b e t w e e n the actual m a g n i t u d e - r e s p o n s e Q
FIGURE ED.1
curve and the asymptotic response is largest at the c o m e r frequency, w h e r e its value is 3 d B .
D-6
APPENDIX D
SINGLE-TIME-CONSTANT
CIRCUITS FREQUENCY
D.3
RESPONSE O F STCCIRCUITS
•^/(Hz) —
3
= 1.6 x 10 Hz
fo
( 3 )
(b)
FIGURE D.7 (a) An amplifier circuit and (b) a sketch of the magnitude of its transfer function.
Solution Direct analysis of the circuit in Fig. D.7(a) results in the transfer function
V,
l+sRC (-fi
+ l)
f
which can b e seen to be that of a low-pass S T C circuit with a dc gain ¡1 = - 1 0 0 (or, equivalently, 4 0 dB) and a time constant r=RC (-Li + 1) = 100 x 1 0 x 10 x 1 0 " x 101 - 10~ s, 3
1 2
4
f
which corresponds to a frequency co = 1/r-
4
1 0 rad/s. T h e magnitude response is sketched in
0
Fig. D.7(b). FIGURE D . 6 (a) Magnitude and (b) phase response of STC circuits of the low-pass type.
D.3.2 High-Pass Circuits T o verify that this v a l u e is correct, s i m p l y s u b s t i t u t e co = co i n E q . ( D . 3 ) to obtain Q
T h e transfer function T(s) of a n S T C h i g h - p a s s circuit a l w a y s c a n b e e x p r e s s e d in t h e form
\T(jco )\ = K/Jl 0
T(s)
T h u s a t co = co t h e g a i n drops b y a factor of JÏ relative t o t h e d c gain, w h i c h c o r r e s p o n d s to 0
a 3-dB r e d u c t i o n in g a i n . ' T h e corner frequency co is appropriately referred to as t h e 3-dB 0
frequency.
=
s
(D.5)
+ co
0
w h i c h for p h y s i c a l frequencies s = jco b e c o m e s
Similar to t h e m a g n i t u d e r e s p o n s e , t h e p h a s e - r e s p o n s e c u r v e , s h o w n in F i g . E.6(b), is
T(jco) =
c l o s e l y defined b y straight-line a s y m p t o t e s . N o t e that at t h e c o r n e r f r e q u e n c y t h e p h a s e is
K
(D.6)
l-jco /co Q
- 4 5 ° , a n d that for co > co t h e p h a s e approaches - 9 0 ° . A l s o n o t e that t h e - 4 5 ° / d e c a d e straight 0
line a p p r o x i m a t e s t h e p h a s e function, with a m a x i m u m error of 5.7°, over t h e frequency
w h e r e K d e n o t e s t h e g a i n a s s o r co a p p r o a c h e s infinity a n d Oh i s t h e i n v e r s e of t h e t i m e constant T,
r a n g e 0.1ft) to 10û> . 0
0
co = 0
1/T
The magnitude response
\T(jco)\ =
j
Consider the circuit shown in Fig. D.7(a), where an ideal voltage amplifier of gain fi = - 1 0 0 has a small (10-pF) capacitance connected in its feedback path. T h e amplifier is fed by a voltage J source having a source resistance of 100 k Q . Show that the frequency response V /V of this j amplifier is equivalent to that of an STC circuit, and sketch the magnitude response. 0
K
*
(D.7)
2
Jl + {co /co) Q
and the phase response
s
(D.8)
'g|
D
_
8
)
D-9
APPENDIX D
SINGLE-TIME-CONSTANT
STEP RESPONSE OF STC CIRCUITS
D.4
CIRCUITS
D.5 For the situation discussed in Exercise D.4, if R = 10 k Q , find the capacitor values that result in the circuit having a high-frequency transmission of 0.5 V7V and a corner frequency co = 10 rad/s. 0
Ans. C, = C = 5 2
/IF
D.6 Find the high-frequency gain, the 3-dB frequency f , and the gain a t / ' = 1 Hz of the capacitively coupled amplifier shown i n Fig. ED.6. Assume the voltage amplifier to be ideal. 0
-10 +20 dB/decade -20, * - — (log scale) F I G U R E ED.S
(a) Ans. 4 D i l B : 1 5 . " I I / : I f ' J U
d>(a>) 1
1
1
90°
t
D.4
1 5.7°
STEP RESPONSE OF STC CIRCUITS
- 4 5 ° /decade
45°
In this section w e c o n s i d e r t h e r e s p o n s e of S T C circuits to the step-function signal s h o w n in 1 * % ^
J
5.7°
'
Fig. D . 9 . K n o w l e d g e of t h e step r e s p o n s e e n a b l e s rapid evaluation of the r e s p o n s e t o other s w i t c h i n g - s i g n a l w a v e f o r m s , s u c h as p u l s e s a n d s q u a r e w a v e s .
0
!
10
0.1
———•
(log scale) cu
0
(b) FIGURE D.8 (a) Magnitude and (b) phase response of STC circuits of the high-pass type.
D.4.1 Low-Pass Circuits In r e s p o n s e t o an input step signal of height S, a low-pass S T C circuit (with a dc gain K = 1) produces the waveform s h o w n in Fig. D.10. N o t e that while the input rises from 0 to 5 at t = 0, the output d o e s not r e s p o n d immediately to this transient and simply begins to rise e x p o n e n dc value of the input, 5. In the long t e r m — t h a t is, for t > T — t h e output
are s k e t c h e d in F i g . D . 8 . A s in t h e l o w - p a s s case, t h e m a g n i t u d e a n d p h a s e curves are w e l l
tially toward the final
defined b y straight-line asymptotes. B e c a u s e of the similarity (or, m o r e appropriately, duality)
approaches the d c value S, a manifestation of the fact that low-pass circuits faithfully pass d c .
w i t h the l o w - p a s s case, n o further e x p l a n a t i o n will b e given.
T h e equation of the output w a v e f o r m c a n b e o b t a i n e d f r o m the e x p r e s s i o n y(t) w h e r e Y^ d e n o t e s the final
=
Y„-(Y„-Y )e
(D.9)
0+
value or t h e value t o w a r d w h i c h t h e o u t p u t is h e a d i n g a n d
d e n o t e s t h e v a l u e of t h e o u t p u t i m m e d i a t e l y after t = 0. This e q u a t i o n states that the output 03
Find the dc transmission, the corner frequency /„, a n d the transmission a t . / = 2 M H z for the low-pass
any time t is equal to the difference
S T C circuit shown in Fig. E D . 3 .
value ofY
x
- Y
0+
and is "shrinking"
10 kO
t
( l )
x(t),
i
10 k û > 100 p F ^ = FIGURE E D . 3
Ans.-6dB;318kHz;-22dB D.4 Find the transfer function T(s) of the circuit in Fig. D.2. What type of S T C network is it? Ans. T(s) ••
; HP C +C i
the final
exponentially. y(r) = 5(1
+ V
between
2
^ + [ 1 / ( C + C )7v] 1
2
FIGURE D.9 A step-function signal of height S.
value
F
M
and a gap that has an
In o u r case, Y^ = S a n d F -t/T.
0 +
Y
0+
at
initial
= 0; t h u s , (D.10)
D-IO
p.!
!
£\
APPENDIX D
SINGLE-TIME-CONSTANT
At)
D.5
CIRCUITS
PULSE RESPONSE OF STC CIRCUITS
'{'^
where
I
r
Rl+R
2
and Tangent v
/r
=
O2
k (10e~' ) c
where
C
FIGURE D . 1 0 The output y(f) of a low-pass STC circuit excited by a step of height S.
1
+
C
2
and y(t)n
Thus Vg =
V
Ql
+
=
V
02
10k +10e^\k -k ) r
c
r
It follows that the output can be made a perfect step of height Wk volts if we arrange that r
FIGURE D . 1 1
The output y(t) of a high-pass STC circuit excited by a step of height S.
K=K
T h e r e a d e r ' s attention is d r a w n to the slope of the tangent to y(t) at t = 0, w h i c h is indicated in Fig. D . 1 0 .
D.4.2 High-Pass Circuits
that is, if the resistive voltage-divider ratio is made equal to the capacitive voltage divider ratio. This example illustrates an important technique, namely, that of the "compensated attenuator." An application of this technique is found in the design of the oscilloscope probe. The oscilloscope probe problem is investigated in Problem D.3.
T h e r e s p o n s e of an S T C high-pass circuit (with a high-frequency gain K= 1) to an input step of height S is s h o w n in Fig. D . 11. T h e high-pass circuit faithfully transmits the transient part of the input signal (the step change) but blocks the dc. T h u s the output at t = 0 follows the input, Y
0+
D.7 For the circuit of Fig. D.4(f) find % i f f i s a 3-mA step, R=l
= S
;
Ans. 3 ( 1 -e
and then it d e c a y s t o w a r d zero,
kQ, and C = lOOpF.
'"'')
D.8 In the circuit of Fig. D.5(£) find v (t) if i, is a 2 - r t A step; R=2 Am. 4 c ' 0
y. = o Substituting for Y
0+
and F J i n Eq. (D.9) results i m t h e output y(t),
k i i . and / . = W-iM> '
D.9 The amplifier circuit of Fig. ED.6 is fed with a signal source that delivers a 20-mV step. If the source resistance is 100 k Q . find the time constant r and v (i). :
y(t)
/T
= Se-'
(D.ll)
0
Ans. i = 2 x l 0 T h e r e a d e r ' s attention is drawn to the slope of the tangent to y(t) at t = 0, indicated in Fig. D . 11.
1
s; v (i) = 1 x e ()
D.10 For the circuit in Fig. D.2 with C, = C, = 0.5 /.iF,R = 1 M Q , find v (t) if v,(t)is a 10-V step. Ans. 5e~' 0
D.11 Show that the area under the exponcniial of Fig. D.11 is equal to that of the rectangle of height 5 and width T. This example is a continuation of the problem considered in Example D.3. For an input « that is 7
a 10-V step, find the condition under which the output v is a perfect step. 0
D.5
PULSE RESPONSE OF STC CIRCUITS
'
Solution Following the analysis in Example D.3, which is illustrated in Fig. D.3, we have v
01
=
t/T
k [lO(l-e- )] r
F i g u r e D . 1 2 s h o w s a p u l s e signal w h o s e height is P and w h o s e width is T. W e wish to find the response of S T C circuits to input signals of this form. N o t e at the outset that a pulse can b e considered as the s u m of t w o steps: a positive o n e of height P occurring at t = 0 and a
D-12
-13
APPENDIX D
X(f)i
D.5
SINGLE-TIME-CONSTANT CIRCUITS
T h e distortion of a p u l s e signal b y a parasitic (i.e., u n w a n t e d ) l o w - p a s s circuit is m e a sured b y its rise time a n d fall time. T h e rise t i m e is conventionally defined as the t i m e t a k e n b y t h e a m p l i t u d e to increase from 1 0 % to 9 0 % of t h e final value. Similarly, the fall t i m e is t h e t i m e d u r i n g w h i c h t h e p u l s e a m p l i t u d e falls from 9 0 % to 1 0 % of t h e m a x i m u m value. T h e s e definitions are illustrated in Fig. D . 1 3 ( b ) . B y u s e of the e x p o n e n t i a l equations of t h e rising and falling e d g e s of t h e output w a v e f o r m , it can b e easily s h o w n that
I
f
-*í
T 1
•> —
t P
\
mi "
PULSE RESPONSE OF STC CIRCUITS
t
f
FIGURE D . I 2 A pulse signal with height /' and width T.
0
f r
signal can b e obtained b y s u m m i n g t h e r e s p o n s e s to t h e t w o step signals.
D.5.1 Low-Pass Circuits
A low-pass effect usually occurs w h e n a pulse signal from one part of an electronic sys t e m is connected to another. T h e low-pass circuit in this case is formed b y the output resis tance ( T h e v e n i n ' s equivalent resistance) of the s y s t e m part from w h i c h the signal originates and the input capacitance of the system part to w h i c h the signal is fed. This unavoidable lowpass filter will cause distortion—of the t y p e s h o w n in Fig. D . 13(a)—of the pulse signal. In a well-designed system such distortion is k e p t to a l o w value b y arranging that the time constant X b e m u c h smaller than the pulse w i d t h T. In this case the result will b e a slight rounding of the pulse edges, as s h o w n in Fig. D.13(b). N o t e , h o w e v e r , that the edges are still exponential.
f
w h i c h can b e also e x p r e s s e d in terms of f
n e g a t i v e o n e of h e i g h t P occurring at t = T. T h u s t h e r e s p o n s e of a linear circuit to the pulse
F i g u r e D . 13(a) s h o w s the r e s p o n s e of a l o w - p a s s S T C circuit (having unity dc gain) to an input p u l s e of t h e f o r m s h o w n in F i g . D . 1 2 . I n this c a s e w e h a v e a s s u m e d that t h e t i m e con stant T i s in t h e s a m e r a n g e as t h e pulse w i d t h T. A s s h o w n , t h e L P circuit does n o t r e s p o n d i m m e d i a t e l y to t h e step c h a n g e at the leading e d g e of t h e p u l s e ; rather, t h e output starts to rise exponentially t o w a r d a final value of P. This e x p o n e n t i a l rise, h o w e v e r , will b e stopped at t i m e t = T, that is, at t h e trailing edge,of the p u l s e w h e n t h e input u n d e r g o e s a negative step c h a n g e . A g a i n t h e output will r e s p o n d b y starting an e x p o n e n t i a l d e c a y t o w a r d t h e final value of t h e input, w h i c h is zero. Finally, n o t e that t h e area u n d e r t h e output w a v e f o r m will b e equal to the area u n d e r the input pulse waveform, since t h e L P circuit faithfully passes dc.
= t
r
= 2.2 T
= co /2n=
= h -
0
0 35 ~ ^
(D.12) V2nx&s
(D.13)
Jo
F i n a l l y , w e n o t e t h a t t h e effect of t h e p a r a s i t i c l o w - p a s s circuits that are a l w a y s p r e s e n t in a s y s t e m is to " s l o w d o w n " t h e o p e r a t i o n of t h e s y s t e m : T o k e e p t h e signal distortion w i t h i n a c c e p t a b l e l i m i t s , o n e h a s to u s e a r e l a t i v e l y l o n g p u l s e w i d t h (for a g i v e n l o w - p a s s time constant). T h e o t h e r e x t r e m e c a s e — n a m e l y , w h e n r i s m u c h l a r g e r t h a n T—is i l l u s t r a t e d in F i g . D . 13(c). A s s h o w n , t h e output w a v e f o r m rises exponentially t o w a r d the level P. H o w e v e r , since x > T, the v a l u e r e a c h e d at t = T will b e m u c h smaller t h a n P. A t t = T the output w a v e f o r m starts its e x p o n e n t i a l decay t o w a r d zero. N o t e that in this c a s e t h e output w a v e form bears little r e s e m b l a n c e to the input pulse. A l s o n o t e that b e c a u s e x §> T t h e portion of t h e e x p o n e n t i a l c u r v e from t - 0 to t = T is a l m o s t linear. S i n c e t h e slope of this linear c u r v e is p r o p o r t i o n a l to t h e h e i g h t of t h e input p u l s e , w e see that the output waveform approximates the time integral of the input pulse. That is, a low-pass n e t w o r k with a large t i m e constant a p p r o x i m a t e s t h e operation of an integrator.
D.5.2 High-Pass Circuits Figure D . 14(a) shows the output of an S T C H P circuit (with unity high-frequency gain) excited b y the input pulse of Fig. D.12, assuming that x and T are comparable in value. A s shown, the step transition at the leading edge of the input pulse is faithfully reproduced at the output of the H P circuit. H o w e v e r , since the H P circuit blocks dc, the output waveform i m m e diately starts an exponential decay toward zero. This decay process is stopped at t = T, w h e n the negative step transition of the input occurs and the H P circuit faithfully reproduces it. T h u s at t - T the output w a v e f o r m exhibits an undershoot. T h e n it starts an exponential decay toward zero. Finally, n o t e that the area of the output w a v e f o r m a b o v e the zero axis will b e equal to that b e l o w the axis for a total average area of zero, consistent with the fact that H P cir cuits block dc. In m a n y applications an S T C high-pass circuit is u s e d to couple a pulse from one part of a system to another part. In such an application it is necessary to k e e p the distortion in the pulse shape as small as possible. This can be accomplished b y selecting the time constant T to be m u c h longer than the pulse width T. If this is indeed the case, the loss in amplitude during the pulse period T w i l l b e very small, as s h o w n in Fig. D . 14(b). Nevertheless, the output w a v e form still swings negatively, and the area u n d e r the negative portion will be equal to that u n d e r the positive portion.
' (c) FIGURE D . I 3 Pulse responses of three STC low-pass circuits.
C o n s i d e r t h e w a v e f o r m in Fig. D . 14(b). Since T I S m u c h larger than T, it follows that the portion of the e x p o n e n t i a l c u r v e from t = 0 to t = T w i l l b e almost linear and that its slope will b e equal to t h e slope of t h e exponential curve at t - 0, w h i c h is P/x. W e can u s e this value of
D-15
i
APPENDIX D
SINGLE-TIME-CONSTANT
CIRCUITS
PROBLEMS
<—r—>
T
T comparable to T
p
-<
7
1
>
T>
T),12"Find the rise and fall times of a 1 -fts pulse after it h a s passed through a low-pass R C circuit with a corner frequency of I'l Ml Iz.
T
1
Ans. 35 us t
t
0
D-16
T
1 (a)
i^"t
^
D.13 Consider the pulse response of a low-pass S T C circuit, as shown in Fig. D . 13(c). If T = 100T, find the ouiput voltage at ; •- T. Also, find the difference in the slope of the rising portion of the output waveibrm at / 0 and t - T (expressed as a percentage of the slope at t = 0). Ans.0.01P;l% D.14 T h e output of an amplifier stage is connected to the input of another stage via a capacitance C. If the first stage has an output resistance of 10 kQ, and the second stage has an input resistance of 4 0 k Q , find the mirrimum value of C such t h a t a 10-/is pulse exhibits less than 1% sag. Ans. 0.02 ,uK 0.15 A high-pass S T C circuit with a lime constant of 100 /is is excited by a pulse of l-V height and 100-us width. Calculate the value of the undershoot in the output waveform. Ans. 0.632 V
u l<—r—»-l F I G U R E D . 1 4 Pulse responses of three STC high-pass circuits.
t h e slope t o d e t e r m i n e t h e loss in a m p l i t u d e A P as
PROBLEMS
AP = -T x
(D.14)
T h e distortion effect of the h i g h - p a s s circuit on t h e i n p u t p u l s e is u s u a l l y specified in terms of the p e r - u n i t o r p e r c e n t a g e loss in p u l s e height. T h i s q u a n t i t y is t a k e n as a n indication of
D.1 Consider the circuit of Fig. D.3(a) and the equivalent shown in (d) and (e). There, the output, v - v + v , is the sum of outputs of a low-pass and a high-pass circuit, each with the time constant T = (C, + C )(R //R ). What is the con dition that makes the contribution of the low-pass circuit at zero frequency equal to the contribution of the high-pass cir cuit at infinite frequency? Show that this condition can be expressed as C Ri = C R . If this condition applies, sketch | V / V \ versus frequency for the case R - R . 0
2
the " s a g " in t h e o u t p u t p u l s e , P e r c e n t a g e sag =
x 100
(D. 15)
x
Thus
0
T P e r c e n t a g e sag = - x 100
(D.16)
2
i
01
Q2
2
2
t
}
2
D.2 Use the voltage divider rule to find the transfer function V (s)/Vj(s) of the circuit in Fig. D.3(a). Show that the transfer function can b e made independent of frequency if the condi tion Cji?i = C R applies. Under this condition the circuit is called a compensated attenuator. Find the transmission of the compensated attenuator in terms of R and R . a
Finally, n o t e that t h e m a g n i t u d e of the u n d e r s h o o t at t = Tis e q u a l to A P . T h e other e x t r e m e c a s e — n a m e l y , r < T—is illustrated in Fig. D . 14(c). In this case the exponential d e c a y is quite rapid, resulting in the output b e c o m i n g almost zero shortly b e y o n d the leading e d g e of the pulse. A t the trailing e d g e of the pulse the output swings negatively by an a m o u n t almost equal to the pulse height P. T h e n t h e w a v e f o r m decays rapidly to zero. A s seen from Fig. D . 14(c), the output w a v e f o r m bears n o r e s e m b l a n c e to t h e input pulse. It con sists o f t w o spikes: a positive o n e at the leading e d g e a n d a negative o n e at the trailing edge. N o t e that t h e output waveform is approximately equal to t h e t i m e derivative of the input pulse. That is, for x < T an S T C high-pass circuit approximates a differentiator.
H o w e v e r , the result
ing differentiator is not an ideal one; an ideal differentiator w o u l d p r o d u c e t w o impulses. Nevertheless, high-pass S T C circuits with short t i m e constants are e m p l o y e d in s o m e applica tions to p r o d u c e sharp pulses or spikes at t h e transitions of a n input waveform.
2
2
x
2
probe"—that is, a probe that attenuates the input signal by a factor of 10. Find the input impedance of the probe when connected to the oscilloscope, which is the impedance seen by v, in Fig. D.3(a). Show that this impedance is 10 times higher than that of the oscilloscope itself. This is the great advantage of the 10.T probe. D . 4 In the circuits of Figs. D.4 and D.5, let L = 10 mH, C = 0.01 uF, and R = 1 kQ.. At what frequency does a phase angle of 45° occur? * D . 5 Consider a voltage amplifier with an open-circuit voltage gain A = - 1 0 0 WV, R = 0, R, = 10 kQ, and an input capacitance C, (in parallel with R ) of 10 pF. The amplifier has a feedback capacitance (a capacitance con nected between output and input) C = I pF. The amplifier is fed with a voltage source V having a resistance R = 10 kQ,. Find the amplifier transfer function V (s)/V (s) and sketch its magnitude response versus frequency (dB vs frequency) on a log axis. vo
0
t
f
s
D** D.3 The circuit of Fig. D.3(a) is used as a compensated attenuator (see Problems D.1 and D.2) for an oscilloscope probe. The objective is to reduce the signal voltage applied to the input amplifier of the oscilloscope, with the signal attenu ation independent of frequency. The probe itself includes A , and Ci, while R and C model the oscilloscope input circuit. For an oscilloscope having an input resistance of 1 M£l and an input capacitance of 30 pF, design a compensated "10-to-l
s
a
s
1
2
2
D . 6 For the circuit in Fig. PD.6 assume the voltage ampli fier to be ideal. Derive the transfer function VfsyViis). What type of STC response is this? For C = 0.01 LLF and R = 100 kQ, find the corner frequency.
D-17
~J
APPENDIX D
SINGLE-TIME-CONSTANT CIRCUITS
10 ns? What is the actual rise time of a waveform whose dis played rise time is 49.5 ns?
R AA/V
D.I 1 A pulse of 10-ms width and 10-V amplitude is trans mitted through a system characterized as having an STC high-pass response with a corner frequency of 10 Hz. What undershoot would you expect? D.I 2 An RC differentiator having a time constant x is used to implement a short-pulse detector. When a long pulse with T > r i s fed to the circuit, the positive and negative peak out puts are of equal magnitude. At what pulse width does the negative output peak differ from the positive one by 10%? FIGURE PD.6
D.7 For the circuits of Figs. D.4(b) and D.5(b), find v (t) if v, is a 10-V step, R = 1 kQ, and L = 1 mH. 0
D.8 Consider the exponential response of an STC low-pass circuit to a 10-V step input. In terms of the time constant t , find the time taken for the output to reach 5 V, 9 V, 9.9 V, and 9.99 V. 0 . 9 The high-frequency response of an oscilloscope is spec ified to be like that of an STC LP circuit with a 100-MHz cor ner frequency. If this oscilloscope is used to display an ideal step waveform, what rise time (10% to 90%) would you expect to observe? D.I 0 An oscilloscope whose step response is like that of a low-pass STC circuit has a rise time of t seconds. If an input signal having a rise time of t seconds is displayed, the wave form seen will have a rise time t seconds, which can be 2 2 found using the empirical formula td = Jt s + t w. If ts = 35 ns, what is the 3-dB frequency of the oscilloscope? What is the observed rise time for a waveform rising in 100 ns, 35 ns, and s
w
D.I 3 A high-pass STC circuit with a time constant of 1 ms is excited by a pulse of 10-V height and 1-ms width. Calcu late the value of the undershoot in the output waveform. If an undershoot of 1 V or less is required, what is the time con stant necessary? D D . 1 4 A capacitor C is used to couple the output of an amplifier stage to the input of the next stage. If the first stage has an output resistance of 2 k£2 and the second stage has an input resistance of 3 kfl, find the value of C so that a 1-ms pulse exhibits less than 1% sag. What is the associated 3-dB frequency? DD.15 An RC differentiator is used to convert a step volt age change Vto a single pulse for a digital-logic application. The logic circuit that the differentiator drives distinguishes signals above V/2 as "high" and below V/2 as "low." What must the time constant of the circuit be to convert a step input into a pulse that will be interpreted as "high" for 10 tis?
s-Domain Analysis: Poles, Zeros, and Bode Plots In analyzing the frequency r e s p o n s e of an amplifier, m o s t of the w o r k involves finding the amplifier voltage gain as a function of the c o m p l e x frequency s. In this s - d o m a i n analysis, a capacitance C is r e p l a c e d b y an a d m i t t a n c e sC, or equivalently an i m p e d a n c e 1/sC, and an i n d u c t a n c e L is r e p l a c e d b y an i m p e d a n c e sL. T h e n , u s i n g usual circuit-analysis techniques, o n e derives the v o l t a g e transfer function T(s) = V (s)/V (s). 0
t
EXERCISE E.I
Find the voltage transfer function 7'(s) = V (s)/V u
t
(s) for the S T C n e t w o r k s h o w n in
d
D D . 1 6 Consider the circuit in Fig. D.7(a) with p. = - 1 0 0 , Cf= 100 pF, and the amplifier being ideal. Find the value of R so that the gain | V /V* | has a 3-dB frequency of 1 kHz. 0
J
R
o 1,
-o F I G U R E EE.1
, , Ans. 7(s) =
l/CR, 1
s-+
1/C{RJR ) 2
O n c e the transfer function T(s) is obtained, it can b e evaluated for p h y s i c a l f r e q u e n c i e s b y replacing s b y jco. T h e resulting transfer function T(jco) is in general a c o m p l e x quantity w h o s e m a g n i t u d e gives the m a g n i t u d e r e s p o n s e (or transmission) and w h o s e angle gives the p h a s e r e s p o n s e of t h e amplifier. In m a n y cases it will n o t b e n e c e s s a r y to substitute s = jco a n d evaluate T(jco); rather, t h e form of T(s) will r e v e a l m a n y useful facts about t h e circuit p e r f o r m a n c e . In general, for all
e-2
; _ :
APPENDIXE
S - D O M A I N ANALYSIS: POLES, ZEROS, A N D B O D E
PLOTS
E.3
the circuits dealt with in this b o o k , T(s) c a n b e e x p r e s s e d in t h e f o r m m
^, „ as T(s) = - 2 •
first-order n e t w o r k w e h a v e
m—\
+---+a
+ a„,_,s
m
BODE PLOTS
n
j
T(s)
n
s-!—
°-
n—l
x
j
y
x
0
(E.4)
S + CO, '0
In this case the dc gain is a /co , and co, is the corner or 3-dB frequency. N o t e that this transfer function has o n e zero at s = O n the other hand, the first-order high-pass transfer function h a s a zero at d c and c a n b e written as 0
s + b_s + ••• +b w h e r e t h e coefficients a a n d b are r e a l n u m b e r s , a n d t h e o r d e r m of t h e n u m e r a t o r is n
=
(E.l) 0
s m a l l e r t h a n or e q u a l to t h e o r d e r n of t h e d e n o m i n a t o r ; t h e latter is called t h e o r d e r of t h e n e t w o r k . F u r t h e r m o r e , for a s t a b l e c i r c u i t — t h a t i s , o n e t h a t d o e s n o t g e n e r a t e signals on its o w n — t h e d e n o m i n a t o r coefficients s h o u l d b e s u c h that the roots polynomial
all have negative
real parts.
of the
as
T(s)
x
T h e p r o b l e m of amplifier stability is studied in
(E.5)
s + co.'O
denominator
A t this point the reader is strongly urged to review the material o n S T C networks and their fre
C h a p t e r 8.
q u e n c y and p u l s e responses in A p p e n d i x D . Of specific interest are the plots of the m a g n i t u d e
r lj E.1
and p h a s e responses of the t w o special kinds of S T C networks. Such plots can be e m p l o y e d to
POLES AND ZEROS
generate the m a g n i t u d e and phase plots of a high-order transfer function, as explained below
A n alternate f o r m for e x p r e s s i n g T(s) is
' ) E.3 n
S
)
-
a
" ( s - P
1
H
S
m
where
multiplicative constant (the coefficient of s
are the roots of t h e n u m e r a t o r p o l y n o m i a l , and P , P ,..., x
polynomial. Z
h
(
- P J . . . ( s - P . )
2
K
2
)
in t h e n u m e r a t o r ) , Z , Z , . . . , Z x
2
BODE PLOTS
m
P„ are the roots of the d e n o m i n a t o r
Z , . . . , Z,„ are called t h e t r a n s f e r - f u n c t i o n z e r o s or t r a n s m i s s i o n zeros,
A s i m p l e t e c h n i q u e exists for obtaining a n a p p r o x i m a t e p l o t of t h e m a g n i t u d e a n d p h a s e of a transfer function g i v e n its p o l e s a n d zeros. T h e t e c h n i q u e is particularly useful in t h e case of r e a l p o l e s a n d z e r o s . T h e m e t h o d w a s d e v e l o p e d b y H . B o d e , a n d t h e resulting d i a g r a m s are called B o d e p l o t s .
2
and P , P , • . •, P are the t r a n s f e r - f u n c t i o n p o l e s or t h e n a t u r a l m o d e s of the n e t w o r k . A
A transfer function of t h e f o r m depicted in E q . (E.2) consists of a p r o d u c t of factors of
transfer function is c o m p l e t e l y specified in t e r m s of its p o l e s and zeros together with the
the form s + a, w h e r e s u c h a factor appears on top if it c o r r e s p o n d s to a z e r o and on the bot
x
2
n
t o m if it c o r r e s p o n d s to a p o l e . It follows that the m a g n i t u d e r e s p o n s e in decibels of the net
v a l u e of t h e multiplicative constant. T h e p o l e s and zeros c a n be either real or c o m p l e x n u m b e r s . H o w e v e r , since the a and b
w o r k c a n be o b t a i n e d b y s u m m i n g together terms of the form 2 0 1 o g
10
J
2 a
2
+ co , and the
_1
coefficients are r e a l n u m b e r s , t h e c o m p l e x p o l e s (or zeros) m u s t o c c u r in c o n j u g a t e pairs. T h a t is, if 5 + j3 is a zero, then 5 - j'3 also m u s t b e a zero. A z e r o that is p u r e i m a g i n a r y (±jC0z) c a u s e s t h e transfer function T(jco) to b e e x a c t l y zero at co = co . T h i s is b e c a u s e the z
2
2
n u m e r a t o r will h a v e t h e factors (s + jC0z)(s -jco-f) - (s + co ,), w h i c h for p h y s i c a l frequencies 2
b e c o m e s (-co
2
+ co ), and thus t h e transfer fraction will b e exactly zero at co = co . T h u s the z
p h a s e r e s p o n s e c a n b e obtained b y s u m m i n g terms of the form t a n ( f f l / a ) . In both c a s e s t h e t e r m s c o r r e s p o n d i n g to p o l e s are s u m m e d with negative signs. F o r c o n v e n i e n c e w e c a n extract the c o n s t a n t a a n d write the typical m a g n i t u d e t e r m in t h e f o r m 2 0 log Jl
O n a p l o t of decibels v e r s u s l o g frequency this t e r m gives rise t o t h e c u r v e a n d straight-line a s y m p t o t e s s h o w n i n F i g . E . l . H e r e t h e low-frequency a s y m p t o t e is a h o r i z o n t a l straight line
z
" t r a p " o n e p l a c e s at the input of a television set is a circuit that has a t r a n s m i s s i o n zero at the particular interfering frequency. R e a l zeros, on the other h a n d , d o n o t p r o d u c e transmission nulls. Finally, n o t e that for values of s m u c h greater than all the p o l e s and zeros, the transfer function in E q . ( E . l ) b e c o m e s T(s)
m
— a /s"~ . m
T h u s the transfer function has (n - m) zeros
at s = °°.
E.2
FIRST-ORDER FUNCTIONS
M a n y of t h e transfer functions e n c o u n t e r e d in this b o o k h a v e real p o l e s and zeros and c a n therefore b e written as the p r o d u c t of first-order transfer functions of the g e n e r a l f o r m
T( ) S
=
(E.3) s + co
0
w h e r e -co
0
is t h e location of the real p o l e . T h e quantity co , called the p o l e f r e q u e n c y , is 0
w
e q u a l to t h e i n v e r s e of the t i m e constant of this s i n g l e - t i m e - c o n s t a n t ( S T C ) n e t w o r k (see
co (log scale)
3dB •
A p p e n d i x D ) . T h e constants q and a d e t e r m i n e t h e t y p e of S T C n e t w o r k . Specifically, w e 0
x
F I G
studied in C h a p t e r 1 t w o types of S T C n e t w o r k s , l o w p a s s and h i g h p a s s . F o r t h e l o w - p a s s
2
+(co/a) .
J R
Î ! V ,^° ° « - e curve shown applies for the case of a zero For a pole, the high-frequency asymptote should be drawn with a -6-dB/octave slope. d eP l 0 t f
r
t y p i C a I m a
n i t u d e
t e m
T h
iP'il
E-3
APPENDIX E S - D O M A I N A N A L Y S I S : P O L E S , Z E R O S , A N D B O D E P L O T S E.3
at 0-dB level and the high-frequency asymptote is a straight line with a slope of 6 dB/octave or, equivalently, 2 0 dB/decade. The t w o asymptotes meet at the frequency co= \a\, which is called t h e c o r n e r frequency. A s indicated, the actual magnitude plot differs slightly from the value given b y the asymptotes; the m a x i m u m difference is 3 d B and occurs at the corner frequency. F o r a = 0 — t h a t is, a p o l e or a zero at s = 0 — t h e plot is s i m p l y a straight line of 6 d B / octave slope intersecting t h e 0-dB line at co = 1.
BODE PLOTS
Adding the four curves results in the asymptotic Bode diagram of the amplifier gain (curve 5). Note that since the two poles are widely separated, the gain will be very close to 1 0 (60 dB) over the frequency range 1 0 to 1 0 rad/s. At the two comer frequencies ( 1 0 and 1 0 rad/s) the gain will be approximately 3 dB below the maximum of 60 dB. At the three specific frequencies, the values of the gain as obtained from the Bode plot and from exact evaluation of the transfer function are as follows: 3
2
5
In s u m m a r y , to obtain the B o d e plot for the m a g n i t u d e of a transfer function, the a s y m p totic plot for each p o l e and zero is first d r a w n . T h e slope of t h e high-frequency a s y m p t o t e of t h e c u r v e c o r r e s p o n d i n g to a z e r o is + 2 0 d B / d e c a d e , w h i l e that for a p o l e is - 2 0 d B / d e c a d e . T h e various plots are then a d d e d together, a n d t h e overall c u r v e is shifted vertically by an a m o u n t d e t e r m i n e d b y t h e multiplicative constant of the transfer function.
2
03
Approximate Gain
Exact Gain
40 dB 60 dB 40 dB
39.96 dB 59.96 dB 39.96 dB
10 10 10
3
6
5
W e n e x t c o n s i d e r the B o d e p h a s e plot. F i g u r e E . 3 s h o w s a plot of the typical p h a s e t e r m t a n ( f » / a ) , a s s u m i n g that a is negative. A l s o s h o w n is an a s y m p t o t i c straight-line approxi m a t i o n of the arctan function. T h e a s y m p t o t i c plot consists of three straight lines. T h e first is horizontal at = 0 a n d e x t e n d s u p to co = 0.l\a\. T h e s e c o n d line h a s a slope of - 4 5 ° / d e c a d e a n d e x t e n d s f r o m co=0.1\a\ to co= 10\a\. T h e third line h a s a z e r o s l o p e a n d a level of cj> = -90°. T h e c o m p l e t e p h a s e r e s p o n s e can b e o b t a i n e d by s u m m i n g the a s y m p t o t i c B o d e plots of t h e p h a s e of all p o l e s a n d zeros. _1
\ n amplifier has the voltage transfer function 10s
T(s) z
(l+s/10 )(l+s/10°) I md the poles and zeros and sketch the magnitude of the gain versus frequency. Find approxi 3
6
mate values for the gain at co = 10, 1 0 , and 1 0 rad/s.
Solution
A
I lie zeros are as follows: one at s = 0 and one at s = °°. The poles are as follows: one at s = - 1 0 rad/s 2
5
and one at s = - 1 0 rad/s. Figure E.2 shows the asymptotic Bode plots of the different factors of the transfer function. ( urve 1, which is a straight line intersecting the co-axis at 1 rad/s and having a + 2 0 dB/decade slope, responds to the s term (that is, the zero at s = 0) in the numerator. T h e pole at s = - 1 0 results in ve 2, which consists of two asymptotes intersecting at &) = 1 0 . Similarly, the pole at s = - 1 0 epresented by curve 3, where the intersection of the asymptotes is at co= 10 . Finally, curve 4 2
2
c no r\ i i a
1 1
M
-7. /
i i
|
\a\
10|a|
AfJtu^^^N^
1
1
0
5
W
S C A L E
)
5
-45°
represents the multiplicative constant of value 10.
-90° 5.7° FIGURE E.3 Bode plot of the typical phase term t a n " ^ ) when a is negative. 1
Find the Bode plot for the phase of the transfer function of the amplifier considered in Example E . l . \ cu (rad/s) (log scale)
Solution T h e zero at s = 0 gives rise to a constant +90° phase function represented by curve 1 in Fig. E.4. T h e pole at s = - 1 0 gives rise to the phase function 2
i
FIGURE E.2 Bode plots for Example E.l.
0! = - t a n
-10)
—10
PROBLEMS E
_
6
, J
APPENDIX E
S-DOMAIN ANALYSIS: POLES, ZEROS, A N D BODE
(b) In this circuit, capacitor C is used to couple the signal source V, having a resistance R to a load R . For R = 10 kfi., design the circuit, specifying the values of R and C to only one significant digit to meet the following requirements: s
L
s
L
(i) The load resistance should be as small as possible. (ii) The output signal should be at least 70% of the input at high frequencies. (iii) The output should be at least 10% of the input at 10 Hz. E.3 Two STC RC circuits, each with a pole at 100 rad/s and a maximum gain of unity, are connected in cascade with an intervening unity-gain buffer that ensures that they func tion separately. Characterize the possible combinations (of low-pass and high-pass circuits) by providing (i) the rele vant transfer functions, (ii) the voltage gain at 10 rad/s, (iii) the voltage gain at 100 rad/s, and (iv) the voltage gain at 1000 rad/s. F I G U R E E.4 Phase plots for Example E.2. (the leading minus sign is due to the fact that this singularity is a pole). The asymptotic plot for this 5
function is given by curve 2 in Fig. E.4. Similarly, the pole ats = - 1 0 gives rise to the phase function ,
„
-1 CO
t a n
—^ 10
5
whose asymptotic plot is given by curve 3. The overall phase response (curve 4) is obtained by direct summation of the three plots. W e see that at 100 rad/s, the amplifier phase leads by 45° and 5
at 1 0 rad/s the phase lags by 45°.
E.4
AN IMPORTANT REMARK
E.4 Design the transfer function in Eq. (E.5) by specifying fl[ and co s o that the gain is 10 V/V at high frequencies and 1 V/V at 10 Hz. 0
E.5 An amplifier has a low-pass STC frequency response. The magnitude of the gain is 20 dB at dc and 0 dB at 100 kHz. What is the corner frequency?, At what frequency is the gain 19 dB? At what frequency is the phase - 6 ° ?
f ri?l). 0 (
T h e m a t e r i a l of F i g s . E . l a n d E . 2 a n d of t h e p r e c e d m g t w o e x a m p l e s ts
t h e n directly applicable.
PROBLEMS D*E.2 (a) Find E . l Find the transfer function T(s) = V (s)/V,(s) 0
of the
the
voltage
transfer
function
i
circuit in Fig. P E . l . Is this an STC network? If so, of what type? For C = C = 0.5 LiF and R = 100 kQ, find the location x
C
z
of the pole(s) and zero(s), and sketch Bode plots for the
+
magnitude response and the phase response. G —o
+
4)
0 F I G U R E PE.2 F I G U R E PE.1
T(s) ••
V ( s ) / V ( s ) , for the STC network shown in Fig. PE.2. 0
E-7
2
E . 7 An amplifier has a voltage transfer function T(s) = 1 0 ^ / ( i ' + 10)(s + 10 ). Convert this to the form convenient for constructing Bode plots [that is, place the denominator factors in the form (1 + s/a)]. Provide a Bode plot for the magnitude response, and use it to find approximate values for 3
3
4
5
the amplifier gain at 1, 10, 10 , 10 , 10 , and 10 rad/s. What would the actual gain be at 10 rad/s? At 10 rad/s? 3
E.8 Find the Bode phase plot of the transfer function of the amplifier considered in Problem E.7. Estimate the phase angle at 1, 10, 10 , 10 , 10 , and 10 rad/s. For comparison, calculate the actual phase at 1, 10, and 100 rad/s. 2
3
4
5
E.9 A transfer function has the following zeros and poles: one zero at ,s = 0 and one zero at s = <*>; one pole at s = - 1 0 0 and one pole at 5 = - 1 0 . The magnitude of the transfer function at ft) = 1 0 rad/s is 100. Find the transfer function T(s) and sketch a Bode plot for its magnitude. 6
4
E. 1 0 Sketch Bode plots for the magnitude and phase of the transfer function rpf
4
,
5
10 (l + 5 / 1 0 ) (l + s/10 X l + s/10 )
From your sketches, determine approximate values for the magnitude and phase at CO = 1 0 rad/s. What are the exact values determined from the transfer function? 6
E.l 1 A particular amplifier has a voltage transfer function T(s) = 1 0 s / ( l + s / 1 0 ) ( l + s / 1 0 0 ) ( l + 5 / 1 0 ) . Find the poles and zeros. Sketch the magnitude of the gain in dB versus frequency on a logarithmic scale. Estimate the gain at 10°, 10 , 10 , and 10 rad/s. 2
6
3
E.6 A transfer function has poles at (-5), (-7 + j l O ) , and (-20), and a zero at (-1 —720). Since this function represents an actual physical circuit, where must other poles and zeros be found?
6
F o r constructing B o d e plots, it is m o s t c o n v e n i e n t to e x p r e s s the transfer-function factors in !he
^
PLOTS
5
7
E. 1 2 A direct-coupled differential amplifier has a differential gain of 100 V/V with poles at 10 and 10 rad/s, and a commonmode gain of 10~ V/V with a zero at 1 0 rad/s and a pole at 10 rad/s. Sketch the Bode magnitude plots for the differential gain, the common-mode gain, and the CMRR. What is the CMRR at 10 rad/s? (Hint: Division of magnitudes corresponds to subtraction of logarithms.) 6
3
8
7
8
4
BIBLIOGRAPHY
J.L. Smith, Modern Operational Circuit Design, New York: WileyInterscience, 1971. J.V. Wait, L.P. Huelsman, and G.A. Korn, Introduction to Operational Amplifiers Theory and Applications, New York: McGraw-Hill, 1975. ANALOG CIRCUITS
Bibliography GENERAL TEXTBOOKS ON ELECTRONIC CIRCUITS E.F. Angelo Jr., Electronics: BJTs, FETs, and Microcircuits, New York: McGraw-Hill, 1969. S.B. Burns and P.R. Bond, Principles of Electronic Circuits, St. Paul: West, 1987. M.S. Ghausi, Electronic Devices and Circuits: Discrete and Integrated, New York: Holt, Rinehart and Winston, 1985. P.E. Gray and C.L. Searle, Electronic Principles, New York: Wiley, 1969. A.R. Hambley, Electronics, 2nd ed.. Upper Saddle River, NJ: PrenticeHall, 1999. W.H. Hayt and G.W. Neudeck, Electronic Circuit Analysis and Design, 2nd ed., Boston: Houghton Mifflin Go., 1984. CA. Holt, Electronic Circuits, New York: Wiley, 1978. M.N. Horenstein, Microelectronic Circuits and Devices, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1995. R.T. Howe and CG. Sodini, Microelectronics—An Integrated Approach, Englewood Cliffs, NJ: Prentice-Hall, 1997. R.C Jaeger and T.N. Blalock, Microelectronic Circuit Design, 2nd ed., New York: McGraw-Hill, 2004. N.R. Malik, Electronic Circuits: Analysis, Simulation, and Design, Englewood Cliffs, NJ: Prentice-Hall, 1995. J. Millman and A. Gräbel, Microelectronics, 2nd ed., New York: McGraw-Hill, 1987. D.A. Neamen, Electronic Circuit Analysis and Design, 2nd ed., New York: McGraw-Hill, 2001. M.H. Rashid, Microelectronic Circuits: Analysis and Design, Boston: PWS, 1999. D.L. Schilling and C. Belove, Electronic Circuits, 2nd ed., New York: McGraw-Hill, 1979. R.A. Spencer and M.S. Ghausi, Introduction to Electronic Circuit Design, Upper Saddle River, NJ: Pearson Education Inc. (PrenticeHall), 2003. CIRCUIT AND SYSTEM ANALYSIS L.S. Bobrow, Elementary Linear Circuit Analysis, 2nd ed., New York: Holt, Rinehart and Winston, 1987. A.M. Davis. Linear Circuit Analysis, Boston, MA: PWS Publishing Company, 1998. S.S. Haykin, Active Network Theory, Reading, MA: Addison-Wesley, 1970. F-1
W.H/Hayt, G.E. Kernmerly, and S.M. Durbin, Engineering Circuit Analysis, 6th ed., New York: McGraw-Hill, 2003. D. Irwin, Basic Engineering Circuit Analysis, 7th ed., New York: Wiley, 2001. B.P. Lathi, Linear Systems and Signals, New York: Oxford University Press, 1992. J.W. Nilsson and S. Riedel, Electronic Circuits, 6th ed., Revised Printing, Upper Saddle River, NJ: Prentice-Hall, 2001. ;
DEVICES AND IC FABRICATION R.S.C. Cobbold, Theory and Applications of Field Effect Transistors, New York: Wiley, 1969. I. Getreu. Modeling the Bipolar Transistor, Beaverton, OR: Teletronix, Inc., 1976. R.S. Muller and T.I. Kamins, Device Electronics for Integrated Circuits, 3rd ed., New York: Wiley, 2003. J.D. Plummer, M.D. Deal, and P.B. Griffin, Silicon VLSI Technology, Upper Saddle River, NJ: Prentice-Hall, 2000. D.L. Pulfrey and N.G. Tarr, Introduction to Micro-electronic Devices, Englewood Cliffs, NJ: Prentice-Hall, 1989. •C.L. Searle, A.R. Boothroyd, E.J. Angelo, Jr., P.E. Gray, and D.O. Pederson, Elementary Circuit Properties of Transistors, Vol. 3 of the SEEC Series, New York: Wiley, 1964. B.G. Streetman and S. Banerjee, Solid-State Electronic Devices, 5th ed., Upper Saddle River, NJ: Prentice-Hall, 2000. Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed., New York: Oxford University Press, 1999. OPERATIONAL AMPLIFIERS G.B. Clayton, Experimenting with Operational Amplifiers, London: Macmillan, 1975. G.B. Clayton, Operational Amplifiers, 2nd ed., London: NewnesButterworths, 1979. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd ed.. New York: McGraw-Hill, 2001. J.G. Graeme, G.E. Tobey, and L.P. Huelsman, Operational Amplifiers: Design and Applications, New York: McGraw-Hill, 1971. W. Jung, IC Op Amp Cookbook, Indianapolis: Howard Sams, 1974. E.J. Kennedy, Operational Amplifier Circuits: Theory and Applications, New York: Holt, Rinehart and Winston, 1988. J.K. Roberge, Operational Amplifiers: Theory and Practice, New York: Wiley, 1975.
P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design, 2nd ed., New York: Oxford University Press, 2002. K. Bult, Transistor-Level Analog IC Design. Notes for a short course or ganized by Mead, Ecole Polytechnique Federal De Lausanne, 2002. R.L. Geiyer, P.E. Allen, and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, New York: McGraw-Hill, 1990. P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis andDesign ofAnalog Integrated Circuits, 4th ed., New York: Wiley, 2001. A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley, 1984. R. Gregorian and G.C Temes, Analog MOS Integrated Circuits for Signal Processing, New York: Wiley, 1986. IEEE Journal of Solid-State Circuits, a monthly publication of the IEEE. D.A. Johns and K. Martin, Analog Integrated Circuit Design, New York: Wiley, 1997. K. Laker and W. Sansen, Design for Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1999. H.S. Lee, "Analog Design," Chapter 8 in BiCMOS Technology and Applications, A.R. Alvarez, editor, ,Boston: Kluwer Academic Publishers, 1989. B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001. J.K. Roberge, Operational Amplifiers: Theory and Practice, New York: Wiley, 1975. S. Rosenstark, Feedback Amplifier Principles, New York: Macmillan, 1986. A.S. Sedra and G.W. Roberts, "Current Conveyor Theory and Practice," Chapter 3 in Analogue IC Design: The Current-Mode Approach, C. Toomazon, F.J. Lidgey, and D.G. Haigh, editors, London: Peter Peregrinus, 1990. R. Severns, editor, MOSPOWER Applications Handbook, Santa Clara, CA: Siliconix, 1984. Texas Instruments, Inc., Power Transistor and TTL Integrated-Circuit Applications, New York: McGraw-Hill, 1977. S. Soelof, Applications of Analog Integrated Circuits, Englewood . Cliffs, NJ: Prentice-Hall, 1985. National Semiconductor Corporation, Audio/Radio Handbook, Santa Clara, CA: National Semiconductor Corporation, 1980. J.M. Steininger, "Understanding wideband MOS transistors," IEEE Circuits and Devices, Vol. 6, No. 3, pp. 26-31, May 1990. DIGITAL CIRCUITS A.R. Alverez, editor, BiCMOS Technology and Applications, 2nd ed., Boston: Kluwer, 1993. S.H.K Embabi, A. Bellaour, M.I. Elmasry, Digital BiCMOS Integrated Circuit Design, Boston: Kluwer, 1993. M.J. Elmasry, editor, Digital MOS Integrated Circuits, New York: IEEE Press, 1981. Also, Digital MOS Integrated Circuits II, 1992. D.A. Hodges and H.G. Jackson, Analysis and Design of Digital Inte grated Circuits, 2nd ed., New York: McGraw-Hill, 1988. IEEE Journal of Solid-State Circuits, a monthly publication of the
%0
IEEE. S.M. KangandY.Leblebici, CMOS Digital Integrated Circuits, 3rded. New York: McGraw-Hill, 2003. R. Littauer, Pulse Electronics, New York: McGraw-Hill, 1965. K. Martin, Digital Integrated Circuit Design. New York: Oxford University Press, 2000. J. Millman and H. Taub, Pulse, Digital, and Switching Waveforms New York: McGraw-Hill, 1965. Motorola, MECL Device Data, Phoenix, AZ: Motorola Semiconductor Products, Inc., 1989. Motorola, MECL System Design Handbook, Phoenix, AZ: Motorola Semiconductor Products, Inc., 1988. J.M. Rabaey, Digital Integrated Circuits, Englewood Cliffs. NJ: Prentice-Hall, 1996. Note: Also a 2nd ed., with A. Chandrakasan and B. Nikolic, appeared in 2003. L. Strauss, Wave Generation and Shaping, 2nd ed., New York: McGraw-Hill, 1970. H. Taub and D. Schilling, Digital Integrated Electronics, New York: McGraw-Hill, 1977. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Reading, MA: Addison-Wesley, 1985 and 1993. FILTERS AND TUNED AMPLIFIERS P.E. Allen and E. Sanchez-Sinencio, Switched-Capacitor Circuits, New York: Van Nostrand Reinhold, 1984. K.K. Clarke and D.T. Hess, Communication Circuits: Analysis and Design, Ch. 6, Reading, MA: Addison Wesley, 1971. G. Daryanani, Principles of Active Network Synthesis and Design, New York: Wiley, 1976. R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: Wiley-Interscience, 1986. C. Ouslis and A. Sedra, "Designing custom filters," IEEE Circuits and Devices, May 1995, pp. 29-37. S.K. Mitra and CF. Kurth, editors, Miniaturized and Integrated Filters, New York: Wiley-Interscience, 1989. R. Schaumann, M.S. Ghausi, and K.R. Laker, Design ofAnalog Filters, Englewood Cliffs, NJ: Prentice-Hall, 1990. R. Schaumann, M. Soderstand, and K. Laker, editors, Modern Active Filter Design, New York: IEEE Press, 1981. R. Schaumann and M.E. Van Valkenburg, Design of Analog Filters, New York: Oxford University Press, 2001. A.S. Sedra, "S witched-capacitor filter synthesis," in MOS VLSI Circuits for Telecommunications, Y. Tsividis and P. Antognetti, editors, Englewood Cliffs, NJ: Prentice-Hall, 1985. A.S. Sedra and P.O. Brackett, Filter Theory and Design: Active and Passive, Portland, OR: Matrix, 1978. M.E. Van Valkenburg, Analog Filter Design, New York: Holt, Rinehart and Winston, 1981. A.I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967. SPICE M.E. Herniter, Schematic Capture with Cadence PSpice, 2nd ed., NJ: Prentice-Hall, 2003. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE, 2nd ed., New York: McGraw-Hill, 1993. G.W. Roberts and A.S. Sedra, SPICE, New York: Oxford University Press, 1992 and 1997. J.A. Svoboda, PSpice for Linear Circuits, New York: Wiley, 2002. P.W. Tuinenga, SPICE: A Guide To Circuit Simulation & Analysis Using PSpice, 2nd ed., NJ: Prentice-Hall, 1992.
F
-2
S T A N D A R D R E S I S T A N C E V A L U E S A N D U N I T PREFIXES
r a n g e of 5 % resistors o n e finds resistances of 1.0, 1.1, 1.2, 1.3, 1 . 5 , . . . . In the s a m e r a n g e , o n e finds 1% resistors of k i l o h m values of 1 . 0 0 , 1 . 0 2 , 1.05, 1.07, 1.10, T a b l e G . 2 p r o v i d e s t h e S I unit prefixes u s e d in this b o o k a n d in all m o d e r n w o r k s in English.
TABLE G.2
Standard Resistance Values and Unit Prefixes
TABLE *Jr. 1
1 % Resistor Values (kß) 5% Resistor Values (kQ)
100-174
178-309
316-549
562-976
10 11
100 102
178
316 324
562
12
105
s
13
107
15
110
16
113
332
576 590 604
191 196
340 357
619 634
348
18
115
200 205
365
649
20
* 118
210
374
665
22
121
215
383
681
24
124
221
392
698
27
127
226
402
715
30
130
232
412
732
33
133
237
422
750
36
137
243
432
768
39
140
787
43 47
143
249 255
442 453
806
464
825
150 154
261 267 274
475 487
845
158
280
499
887
68
162
287
511
909
75 82
165
294
169 174
301
523 536
931 953
309
549
976
51 56 62
91
147
Symbol
Factor
f
x 10"
15
pico
P n
x 10"
12
x 10~
6
milli
M m
x 10"
3
kilo
k
x 10
micro
Standard Resistance Values
182 187
Name
femto nano
Discrete resistors are available only in standard values. T a b l e G . l p r o v i d e s the multipliers for t h e standard values of 5%-tolerance and 1%-tolerance resistors. T h u s , in the k i l o h m
866
SI Unit Prefixes
x 10"
3
mega
M
xlO
6
giga tera
G
xlO
9
T
peta
P
^
9
x 10
12
x 10
15
t
w
; i
G-2
H-2
ANSWERS T O SELECTED PROBLEMS
3.0 V ( p e a k - t o - p e a k ) of o p p o s i t e p h a s e , 6.0 V ( p e a k - t o - p e a k ) ; (b) 6 V / V ; (c) 5 6 V ( p e a k - t o - p e a k ) 19 8 V ( r m s ) 2.80 86 d B ; 5 0 0 H z ; 10 M H z
2.83 4 7 . 6 k H z ; 19.9 V / V ; 1.99 V / V
(b) 10 k H z ; (c) 64.4 k H z , about six times greater prefeired at l o w gains (d) I V peak
2.92 F o r e a c h , /
2.103 1.4 m V
3 d B
2.91 (a) f/(l
= / / 3
2.86 4 0 V / V
+ K), Kf/(1
+ ^ C ) ; 7? 2
2 . 1 0 7 4.54 m V
2.114 1 0 0 k H z ; 1.59 LIS
2
/-
f ; noninverting t
2.110 (a) 100 m V -
2 . 1 1 8 lOOpulses
1 k Q ; t f = 10 k Q ; C = 3.98 riF; 39.8 k H z
1=
(b) f/K,
/
2.99 (a) 31.8 k H z ; (b) 0.795 V ; (c) 0 to 2 0 0 k H z ;
± 1 0 m V ; add 5 - k Q resistor in series with t h e n e g a t i v e i n p u t t e r m i n a l .
2
+K);
1
(V2-l)
2.105 42.5 to 57.5 m V ; A d d a 5 - k Q resistor in series with the positive input terminal;
(b) 0.2 V ; (c) l O k Q , l O m V ; (d) 1 1 0 m V -(R /R{)/(\
2.89 (a)
2 . 1 1 9 V (s)/V (s) 0
=
i
2.121 1 . 5 9 k H z ; 10 V (peak-to-peak)
2
CHAPTER 3
Answers to Selected Problems
3.1 T h e diode can b e reversed biased and thus n o current w o u l d flow; or forward biased where current would f l o w (a) 0 A ; 1.5 V ; (b) 1.5 A ; 0 V 0 mA
3.2 (a) - 3 V ; 0.6 m A ;
3.5 100 m A ; 3 5 m A ; 100 m A ; 33.3 m A
3.10 (a) 4.5 V ; 0.225 m A ; (b) 2 V ; 0 A
CHAPTER 1 but preferably 1/4 W
1.2 (a) 0 . 9 W . 1 W ;
(c) 0.09 W , 1/8 W ; (f) 0.121 W , 1/8 W
1.4 17; 5 . 7 , 6 . 7 , 8.0, 8 . 6 , 1 0 , 1 3 . 3 , 1 4 . 3 , 1 7 . 1 , 2 0 , 2 3 . 3 , 2 8 , 3 0 , 4 0 , 4 6 . 7 , 5 0 , 6 0 , 7 0 (all in k Q )
1 7 2 9 4 V 2 2 2 l d 2 - 2 . 7 5 V t o 3.14 V, 2.11 k Q to 2.33 k Q
1.9 10.2 V ; s h u n t the 1 0 - k Q resistor a 1 5 7 - k Q
6
1.2 x 1 0 /
3.20 3.46 x 1 0
s
3.26 57.1 Q 6.9°CAV
- 1 5
3.39 0.73 V; 1.7 m A ; 0.7 V ; 2 m A (b) 0 A ; + 3 V ;
1 15 0 7 7 V and 6 15 k Q ; 0.1 m A 2
3
1 59 x 1 0 H z , 6.28 x 1 0 " s 1.24 10 k Q
1.17 1.88 pA; 5.64 V
7
7
1.19 (a) 10~ s, 1 0 H z , 6.28 x 1 0 ' H z ; (f) 10 rad/s,
1.21 (a) (1 - j l . 5 9 ) k Q ; (c) (71.72 - / 4 5 . 0 4 ) k Q
1.28 (a) 165 V ; (b) 2 4 V
1.34 0 1 0 1 , 1000, 1 1 0 0 1 , 1 1 1 0 0 1
1 2 2 (b) 0.1 V , 10 LLA, 10 k Q
1.30 0.5 V ; 1 V ; 0 V ; 1 V ; 1000 H z ; 10
s
1.32 4 k H z ; 4 H z
1.38 7 . 0 5 6 x 1 0 bits p e r s e c o n d
3.41 0.8 V
1 42 9 mV- 57 5 mV- 0 573 V
10.12 V ; 10.12 m A
(d) 5 5 5 7 V/V-
(e) 100 k Q , 100 Q , 3 6 3 V / V
1 6 6 s/(s + l/CR)
1.69 0.64 pF
2 0 dB- 0 d B - - 2 0 d B ; 9 9 0 0 H z 181 1 6 V 1 3 V (d) 5 2 8 ns'
V/V;
4
(b) 9 0 k Q , 3 x 1 0 A / A , 9 x 10 WAV; (c) 667 Q ; = 121 V/V
1.59 A v o l t a g e amplifier; R = 100 k Q , R = 100 s, A t
1.72 0.51/CR
1.77 \/(sC,R
0
1.73 13.3 p F ; 0.26 p F
+ 1); 16 k H z ; -G^RJIR^s
y
1 8 2 (a) 1.5V, I V ; (b) 2 . 0 6 V ; (c) - 3 . 5 V
Vg
(d) 0.73 A; (e) 1.35 A 3.104 14.14 V
+ R ))); 3
53 H z ; 16 k H z
1.84 (a) 0 . 4 V , 0 . 4 V ; (b) 8 m W ; (c) 1 . 1 2 m W ;
1.85 (a) 0.545 V , 5 V , 3 V , 0.455 V ; (b) 6; (c) 10.9 m W , 2.88 m W
1.88 2 5 m W , 5 m A
3.81 5 6 V
2 3 1 m A ; 4 4 8 m A ; (b) 1667 pF; 16.19 V ; 2 . 2 % ; 7 3 5 m A ; 1455 m A 2 2 2 m A ; (b) 833 ^ F ; 15.49 V ; 4 . 5 % ; 3 6 0 m A ; 7 0 4 m A
+ l/(C (R
2
3.70 8.83 V ; 19.13 m A ; 3 0 0 Q ; 9.14 V ; ± 0 . 0 1 V ; + 0 . 1 2 V ;
3.76 16.27 V; 4 8 . 7 % ; 0 . 1 3 ; 5.06 V ; 5.06 m A
3.78 15.57 V ; 9 4 . 7 % ; 9.4 V ; 9.4 m A
1.76 2 0 d B ; 3 7 d B ; 4 0 d B ; 3 7 d B ; 2
3.52 (a) + 4 9 %
3.56 (a) 0 V / V ; (b) 0.001 V / V ;
3.62 1 5 - m A supply; - 1 0 m V / m A , for a total output c h a n g e of - 5 0 m V
3.67 8.96 V ; 9.01 V ; 9.46 V
5 7 8 Q ; 8.83 V ; 9 0 m V / V ; - 2 7 . 3 m A / m A
1.53 (a) 3 0 0
3.46 (a) 0.53 m A ; 2.3 V ;
(c) 0.01 V / V ; (d) 0.1 V / V ; (e) 0.5 V / V ; (f) 0.6 V / V ; (g) 0.9 V / V ; (h) 0.99 V / V ; (i) 1 V / V ; 2.5 m V (peak).
1 4 0 11 V / V or 2 0 8 d B ; 2 2 A / A or 26.8 d B ; 2 4 2 WAV or 23.8 d B ; 120 m W ; 9 5 . 8 m W ; 2 0 . 2 % 1.48 0.83 V ; - 1 . 6 d B ; 79.2 d B ; 38.8 d B
60°C;8.7W;
3.48 (a) 0 . 3 6 m A ; 0 V ; (b) O A ; - 1 . 9 V
(b) + 2 2 % to - 1 8 % ; - 2 . 6 to +2.4 m V (n = 1); - 5 . 3 to +4.8 m V (n = 2)
3.65 - 3 0 Q ; - 1 2 0 Q
1.45 (a) 8.26 V / V or 18.3 d B ; (b) 2.5 V / V or 8 d B ; (c) 0.083 V / V or - 2 1 . 6 d B
3.29
3.37 0.687 V; 12.8 Q ; +28.1 m V ; - 2 9 . 5 m V ; + 3 4 . 2 m V
3.45 0.86 m A ; 0 V ; 0 A ; 3.6 V
(c) 0.53 m A ; 2.3 V ; (d) 0 A ; - 3 V
3.58 157 /uA; - 8 4 . 3 ° to - 5 . 7 °
5
1.36 (c) 1 1 ; 4.9 m V ; 2.4 m V
to - 3 3 % ;
3.36 R = 9 4 7 Q
3.18 3 4 5 m V ;
3.23 3.81 m A ; - 2 2 . 8 m V
3.27 (a) 6 7 8 m V ; (b) 647 m V ; (c) 8 1 4 m V ; (d) 6 5 6 m V ; (e) 6 6 2 m V
3.33 0.6638 V - 0 . 3 3 6 2 m A
1 11 S h u n t t h e 1-kQ resistor w i t h a 2 5 0 Q
L
3.15 2 9 . 6 7 V; 3.75 Q ; 0.75 A ;
3.16 r e d lights; neither lights; green lights
A ; 7.46 m A ; 2 7 3 . 2 m A ; 3.35 m A ; 91.65 LIA; 57.6 m V
resistor; add a s a l e s resistor of 2 0 0 Q ; s h u n t t h e 4 . 7 - k Q resistor with a 157 k Q and the 1 0 - k Q resistor with 9 0 k Q 1.13 S h u n t R with a 1.1-kQ resistor; current divider
3.9 (a) 0 V ; 0.5 m A ; (b) 1.67 V ; O A
3.13 3 V ; 1.5 V ; 3 0 m A ; 15 m A
2 6 . 8 3 V ; 30 V ; 3 Q ; 2 0 . 5 % ; 136 m A ; 1 A ; 2 7 V
1 1 (a) 10 m A ; (b) 10 k Q ; (c) 100 V ; (d) 0.1 A
(b) + 3 V ; 0 m A ; (c) + 3 V; 0.6 m A ; (d) - 3 V ;
3.8 5 0 k Q
3.77 16.27 V ; 9 7 . 4 % ;
3.83 (a) 166.7 pF; 15.4 V ; 7 . 1 % ;
3.85 (a) 83.3 ^ F ; 14.79 V ; 1 4 . 2 % ; 119 m A ;
3.87 (a) 2 3 . 6 V ; (b) 4 4 4 . 4 / / F ; (c) 32.7 V ; 4 9 V ;
3.98 0.51 V; 0.7 V ; 1.7 V ; 10.8 V; 0 V ; - 0 . 5 1 V; - 0 . 7 V; - 1 . 7 V ; - 1 0 . 8 V ; fairly hard; + 1 5
3
9
3
9
3
1 2
3
1 2
3.106 2.75 x 1 0 / c m ; 1.55 x 1 0 / c m ; 8.76 x 1 0 / c m ; 1.55 x 1 0 / c m ; 4.79 x 1 0 / c m
2
2
2
2
2
2
2
2
3.113 3 4 c m / s ; 12 c m / s ; 2 8 c m / s ; 10 c m / s ; 18 c m / s ; 6 c m / s ; 9 c m / s ; 4 c m / s 0.28 Lim; 4 5 . 6 x 1 0 "
1 5
C; 18.2 f F
3.116 16 x 1 0
- 1 5
3
3.114 1.27 V ; 0.57 pm; n
C
3.121 0.72 f A ; 0.684 V ; 2 x 1 0 ~ C; 8 0 0 p F
CHAPTER 4
CHAPTER 2
4.3 W IW = 2.5 4.4 238 Q ; 238 m V ; 50 4.5 2.38 ^ m 4.7 (a) 4.15 m A ; (b) 0.8 mA; 0.92 m A ; 9.9 m A p
2.2 1001 V / V 2.5 A - G R = 100,000 V/V 2.8 (a) - l O V A U O k Q ; (b) - 1 0 V / V , 10 k Q ; (c) - 1 0 V / V , 10 k Q ; (d) - 1 0 V / V 10 k Q 2.11 (a) - 1 V / V ; (b) - 1 0 V / V ; (c) - 0 . 1 V / V ; (d) - 1 0 0 V / V ; (e) - 1 0 V / V 2 1? , = 2 0 k Q R, = 1 0 0 k Q - 2.14 R, = 5 0 0 k Q , R, = 1 0 M Q ; 5 0 0 k Q 2.16 2 x % ; - 1 1 0 . 5 to 90.5 ? 18 0 V 5 V- - 4 9 V to - 5 1 V 2.20 (a) R = lttl,R = 100 k Q ; (b) - 9 0 . 8 V/V; (c) 8.9 k Q 2 21 ± 1 0 m V 2.23 R- '= R + R /(l + A) 2.26 9 0 9 V A ^ 2.27 A = (1 + R /RJ{k1 ) / ( 1 - x / 1 0 0 ) ; 2 x 10 V/V 2.29 100 Q - 1 0 0 k Q - - 1 0 0 Q 2.31 (a) R, R, R, R; (b) / , 27,47, 87; (c) -IR, -2IR, -AIR, -877? 2.33 (a) 0.53 k Q ;
R = 3kQ
(b) - 0 . 4 to +0.4 m A ; (c)*0 Q , 2 0 m A
7.6 V
m
n
m
4.11
3.5 V ; 5 0 0 Q ;
100 Q
4.12
3 V; 2 V; 5 V; 4 V
to 2 0 k Q ; (b) 5 0 Q to 5 k Q ; (c) 100 Q to 10 k Q
AAA
A Lira
4.16
0.7V
4 . 1 9 2 0 k Q ; 36 V ; 0.028 V "
4.17 1
100 Q to 10 k Q ;
(a)
200
Q
4.20 500 k Q ; 50 k Q ; 2 % ; 2 %
R
l
x
2.43 12 8 k Q
2
2
2.46 R = 1 0 0 k Q ; N o
2.36 v = 0
2.50 v = 0
add 0 5 k Q in series w i t h g r o u n d e d end of p o t 2.54
V
g
/
v
v - v /2; x
-1.5 V
2
2.37 R^ = 2 0 k Q ; R^ = 120 k Q ; R = 4 0 k Q
l O f o - w , ) ; v = 4 s i n ( 2 ^ x 10000 0
2.66 6 8 d B
2.68 (a) 1,0; (b) - 5 V t o + 5 V ;
H-l
v /v,=
\/x;+\to+™;
0
2.56 8.33 V / V ; Shunt R w i t h R {
2.62 v =v 0
2
(c) 1, 0 , - 3 0 t o + 3 0 V
- v ; R; 2R; 2R; R x
3
A
s h
= 36 k Q ;
2.64 R = R L
3
2.73 ( a ) - 0 . 1 4 t o + 0 . 1 4 V ; - 1 4 t o + 1 4 V
2.76 Rj_ = 100 k Q p o t plus 0.5 k Q fixed; R = 5 0 k Q ; R = 2 0 0 k Q ; R = 100 k Q 2
2.51
2.53 (a) 0.099 V ; 0.099 m A ; 0.099 m A ; (b) 10 V ; 10 m A ; 0 m A
2.59 - 1 0 . 7 1 4 t o + 1 0 . 7 1 4 V ; 1.07 V
1
- 1 V ; - 5 0 V ; - 0 . 0 2 V" ; 1.39mA/V
4.26 2 4 0 p A ; 5 2 4 p A ; 5 3 9 p A ; 5 8 8 p A
s
2
4.29 I V t o ' 1 . 6 9 V ; I V t o 3 . 7 V
All
4.35 (a) 9 . 7 5 k Q ; (b) 2 0 i t m ; 4 k Q
4.36 4 . 8 p m ; 3 0 . 4 k Q
4.44 (a) 2.51 V ; - 2 . 7 9 V ; (b) 7.56 V ; 5 V ; 2.44 V
4 . 3 1 (b)
- 3 V; +3 V; - 4 V; +4 V; -0.3%/°C
4.34/v = 5kQ; 0
4.37 8 p m ; 2 p m : 1 2 . 5 k Q
4.39 0 . 4 m A ;
4.46 (a) 7.5 pA; 1.5 V ; (b) 4.8 pA; 1.4 V ; (c) 1.5 V;
f
. = i / ( i + 1 / A ) ; 0.999, - 0 . 1 % ; 0.990, - 1 . 0 % ; 0.909, - 9 . 1 %
9 0 9 V/V- 11 1 V / V
4 . 2 2 82.13 pA; 2 . 7 % ; u s e L - 6 p i r n
2
2.77 (a) 3.0 V ( p e a k - t o - p e a k ) ,
7.5pA
4.48 (a) I V ; I V ; - 1 . 3 2 V ; (b) 0.2 V ; 1.8 V ; - 1 . 3 5 V
8.2 k Q ; 4 0 / i A t o 0 . 1 5 m A
4.58 1 m A ; 1 3 %
4.510.8V;25
4 . 5 9 1.59 V ; 2.37 V ; 2.37 m A
4.63 (a) - 3 V ; + 5 V ; 8 V ; (b) - 3 . 3 V; + 5 V ; + 8 . 3 V (b) 2 m A / V ; (c) - 7 . 2 V / V ; (d) 5 0 k Q ; - 6 . 7 V / V
4.57 3.4 V ; 1 1 0 / t A to 838 pA; 4.60 R
4 . 6 5 36 k Q ; 0.21 m A ; 2 V 4 . 7 3 2 0 pm; 1.7 V
D
= 11 k Q ; R = 7 k Q s
4 . 6 9 (a) 2 m A ; 2.8 V;
4 . 7 5 - 8 . 3 V / V ; 2.5 V ; - 1 0 . 8 V / V
4 . 7 6 N M O S : 0 . 4 2 m A / V , 160 k Q , 0.08 m A / V , 0.5 V ; P M O S : 0 . 2 4 5 m A / V , 2 4 0 k Q , 0 . 0 5 m A / V , 0.8 V 4.79 - 1 1 . 2 V / V
4 . 8 1 2 0 0 Q ; 3.57 V / V ; 100 Q ; 4 . 7 6 V / V
4 . 8 5 0.99 V / V ; 2 0 0 Q ; 0.83 V / V
4 . 9 1 5.1 G H z
APPENDIX H
H-3
ANSWERS TO SELECTED
ANSWERS TO SELECTED
PROBLEMS
4 9 3 2 7 GHz- 5 4 G H z 4 9 6 (a) - 1 5 . 2 4 V / V ; 33.1 k H z 4.99 - 1 0 V/V, 18.6 ßF 4.103 - 1 6 V / V ; C = 2 0 nF, C = 10ßF;C = 0.5ßF;47.7Hz 4 . 1 0 6 1.36 V ; 1.5 V ; 1.64 V 4.110 1 0 4 . 1 1 4 (b) - 1 2 5 V / V ; 8 0 k Q 4.115 0.59 m A , 5 m A ; 9 m A ; 9 m A 4.116 300 ßA; 416 ßA; 4 2 4 ttA; 4 8 0 /xA; 600 pA; 8 3 2 /iA; 848 txA; 960 ßA; C 1
s
C 2
300 , u A ;
4 1 6
M;
4 2 4
M ; 48° M
v
4.118+0.586
PROBLEMS
C is the second m o s t significant; f increases by a factor of 7, A r e m a i n s u n c h a n g e d 6.124 10 3 M Q - 14 8 Q1 V / V ; 0.985 V / V 6.128 80 pA; 8 M Q ; 0.9 V 6.132 1/(1 + (n + l ) / / 3 ) ; 9 6.133 0.5 k Q 6.135 4 1 V ' 6.137 2 / / A ; 0 . 2 % 6.141 (a) 5.76 k Q ; (b) 33 M Q , 0.15 pA 6.143 11 M Q 6.144 (a) 58.5 k Q ; (b) 200 M Q M2
H
M
2
CHAPTER-/
CHAPTER 5
7.8 1.19 V ; 1.06 m A / V ; 0.27 V ; 800 pA 7.10 - 1 . 5 V; + 0 . 5 V; e q u a l in b o t h cases; 0.05 V ; - 0 . 0 5 V ; 0.536 V 7.19 - 2 . 6 8 V ; 3.52 V; 3.52 V 7.20 - 2 . 6 8 3 V ; + 3 . 5 1 5 V 7.22 - 0 . 4 V 7.24 (a) V (I/2)R ; (b) -(I/2)R ,+(I/2)R ; (c) 4 V ; (d) 0 . 4 m A , 1 0 k Q 7.27 (a) 2 0 7 7 v V / V ; (b) V -0.0275A, 7.28 2.4 m A ; 3 . 6 m A ; 10.1 m V 7.29 I = 3.6 m A , I = 2.4 m A ; 10.1 m V 7.30 (a) 4.14 V ; (b) 3.15 V ; (c) 3.525 V ; (d) 3.755 V 7.32 I m A j l O k Q 7.34 (a) 0.4 m A , 10 m V ; (b) 1.40 m A , 0.60 m A ; (c) - 2 . 0 V +2.0 V ; (d) 4 0 V / V 7.37 4 0 V / V ; 50 k Q 7.38 30 V / V ; - 2 5 k Q 7.41 26.7 V / V ; 17.8 k Q ; 0.033 V / V ; 15 k Q 7.42 (a) 100 V / V ; (b) 2 0 0 V / V ; (c) 4 0 . 2 k Q ; (d) 0.1 V / V ; (e) 0 7.44 1.8 m A ; 360 V / V ; 1.8 sin cotV cc
5 1 active- saturation; active; saturation; i n v e r s e d active; active; cutoff; cutoff 5.2 (a) 7.7 x 10 A, 368; (b) 3 8 x 1 0 - A , 122; (c) 1.5 x 1 0 " A , 2 4 . 2 ; 1.008 m A ; 0.7 V ; 0.96 p C 5.4 5 3 . 3 ; 0.982 5.6 0.5; 0.667; 0 909- 0 9 5 2 ; 0 . 9 9 1 , 0.995; 0.999; 0.9995 5.8 0.907 m A ; 0.587 V 5.10 3 to 15 m A ; 3.05 to 15.05 m A ; 135 m W 5 12 - 0 7 1 8 V ; 4.06 V ; 0.03 m A 5.13 (a) 0.691 V , 1 m A , 1.01 m A ; (b) - 1 0 . 0 9 m A , 9.08 m A , - 1 . 0 1 m A 5 1 6 - 2 V- 0 82 mA- - 0 . 5 7 V 5.18 0.91 m A ; 9.09 m A ; 0.803 V ; 9.99 m A 5.20 (a) 1 m A ; (b) - 2 V ; (c) 1 mA- i V ; (d) 0.965 m A ; 0.35 V 5.22 4.3 V ; 2.1 m A 5.24 (a) - 0 . 7 V, 0 V, 0.756 V, 1.05 m A , 0.034 m A , 1 0 2 m A - ' (b) 0 7 V 0 V, - 0 . 7 7 V, 2.3 m A , 0.074 m A , 2.23 m A ; . (c) 3.7 V , 3 V , 2.62 V , 4.82 m A , 0.155 m A , 4 6 6 m A - (d) 2 3 V 3 V, 4.22 V , 4.89 m A , 0.158 m A , 4.73 m A 5.26 - 2 . 2 V ; 0.779; 3 . 5 3 ; 3.7 V ; 0 V ; - 0 . 7 V ; + 0 7 V '5 2 9 1 / 3 ; 1/2 5 30 0.74 V ; 0.54 V 5.32 3.35 pA 5.38 33.3 k Q ; 100 V ; 3.3 k Q 5.40 1.72 m A ; 6V-34V-20kQ 5 4 2 150; 125; 1.474 m A 5.45 40.2 m V 5.52 3 Q ; 110 m V ; 6 8 . 2 ; 0.11 5.54 - 3 6 0 V / V ; 0 7 V 2 m V 5.57 - 1 0 0 V / V 5.60 3 m A ; - 1 2 0 V / V ; - 0 . 6 6 V ; - 0 . 6 V ; 0.54 V ; 0.6 V 5.63 3 V ; 2.5 m A ; 25 uA- 3.2 V 5.65 1.8 k Q ; 2 5.67 (a) 1.8 m A , 1.5 m A , 3.3 m A ; (b) 1.8 m A , 0.3 m A ; 2.5 m A 1 7
1 7
5 69 (a) 1.3 V , 3.7 V ; (b) 0.3 V , 4.7 V ; (c) 0 V , +5 V 5.72 - 0 . 7 V ; + 4 . 7 V ; - 0 . 5 V ( - 1 V ; + 5 V ) ; + 2 6 V (1 9 V 2 6 V ) 5.74 0.3 V ; 15 pA; 0.8 m A ; 0.785 m A ; - 1 . 0 7 5 V ; 5 2 . 3 ; 0.98 5.79 (a) - 0 . 7 V , 1.8 V ; (b) 1.872 V , 1.955 m A ; (c) - 0 . 7 V , 0 V , 1.872 V ; (d) 1.9 V , - 0 . 2 0 9 V ; (e) 1.224 V , 1.924 V , - 0 . 2 4 6 V 5 82 1 0 8 k Q ; the transistor saturates. 5 . 1 1 2 1.25 V ; 2 0 m A / V ; 150 V / V 5.118 135; 41.8 Q ; 23 mA/V- 1 09 k Q ; - 0 . 7 6 V/V 5 . 1 2 3 9.3 k Q ; 2 8 . 6 k Q ; 1 4 3 V / V 5.124 1 m A ; 0.996 V/V; 0 63 V/V 5 1 4 6 0.7 V / V 5 . 1 4 7 ( a ) 1.73 m A , 68.5 m A / V , 14.5 Q , 1.46 k Q ; ( b ) 148.2 k Q , 0.93 V / V ; ( c ) 18.21 k Q , 0.64 V / V 5 . 1 5 0 1.25 G H z , 5.8 G H z , 2.47 p s , 0.95 p F 5 . 1 5 3 0.54 p F ; 2 0 m A / V ; 7.5 k Q ; 3 3 . 3 M Q 5 . 1 6 8 19 5 . 1 6 9 2.15 m A ; 4.62 m W ; 24 m W ; 14.3 m W 5 . 1 7 0 R = 11 k Q ; R = 2.2 k Q B
c
C
C
C
c
cl
cc
C2
7.45 R = 25 Q ; R = 10 k Q ; R > 5 0 k Q ; R^ = 5 M Q ; ± 1 2 V w o u l d d o , ± 1 5 V would be better. 7.46 2 % mis match, for e x a m p l e ± 1 % resistors 7.47 0.004 V / V 7.54 - 1 2 5 pV 7.55 V = V ((V /V ) (V /V ,)) 7.57 (a) 0 . 2 5 ; (b) 0.225 7.60 7 / 3 ; 2 7 / 3 ; 7 ? / / 3 ; 16.7 m V ; 17.3 m V ; 0.495 pA; 0.5 pA; 0.33 pA 7.98 R ; r e d u c e to 7.37 k Q ; 4 1 0 4 V / V ; r e d u c e 7? to 1.12 k Q 7.99 R = 7.37 k Q ; 4 1 0 4 V / V ; 7? = 1.11 k Q 7.100 173.1 x l O V / V 7.101 (a) 1 m A ; (b) 2.37 k Q , 128 Q ; (c) 2.81 x 1 0 V / V E
c
0
os
T
CE
Al
CE
A
c
5
4
5
4
3
4
CHAPTER 8 3
8.1 9.99 x 1 0 " ; 9 0 . 9 9 ; - 9 % 8.3 (b) 1110; (c) 20 d B ; (d) 1 0 V , 9 m V , l m V ; (e) - 2 . 4 4 % 8.12 A = A / ( 1 + A B); W = W /{\ + A / 3 ) ; 1 + A /3 8.14 100 k H z ; 10 H z 8.20 0.08; 12.34; 10.1 8.29 1 0 + 1 0 / ( 1 + j / 7 1 0 0 ) ; 1 0 + 1/(1 + j / 7 1 0 0 ) ; 1 M Q ; 14.1 k Q ; 10 Q ; 700 Q 8.30 (a) h = R R /(R + R ) Q, h = R /(R + R ) V / V , h = - R / ( R + R ) A / A , A = V(R + R ) 13; (b) h = 10 Q , h = 0.01 V / V , h = - 0.01 A / V , h = 0.99 x 10~ Z3 8.31 10 V/V; 9.9 Q 8.34 0.0 V; 0.7 V; 31.3 V/V; 0.1 V/V; 7.6 V/V; <»; 163 Q 8.35 (b) = 1 + (R /R ); (c) 1.2 k Q ; (d) 1.75 k Q , 628.1 Q ; (e) 23.8 V/V; (f) 154 k Q , 0.53 Q 8.37 7.52 m A / V ; 110.8 k Q ; 4 3 3 . 4 k Q 8.41 - 4 . 7 V / V ; 75 k Q 8.47 (a) shunt-series; (b) seriesseries; (c) shunt-shunt 8.48 - 5 . 6 6 V / V ; 142 k Q ; 5.63 k Q ; 142.9 k Q ; - 5 . 6 1 V / V ; 5.96 k Q 8.49 - 9 . 8 3 k Q ; 29.7 Q ; - 7 . 6 A / A 8.50 9.09 A / A ; 90.9 Q ; 110 k Q 8.53 3.13; 163 Q 8.61 1 0 rad/s; p= 0.002; 5 0 0 V / V 8.63 K< 0.008 8.65 9.9 V / V ; 1.01 M H z ; 10 M H z ; 101 8.66 (a) 5.5 x 1 0 Hz, B = 2.025 x 10~ ; (b) 330.6 V / V; (c) 165.3 V / V , 1/2; (d) 1.33 8.68 VCR; Q= 1/(2.1 - 7 Q ; 0 . 1 ; 0.686; K = 2.1 8.69 K>2; 17.3 M H z 8.70 1 M H z ; 90° 8.72 56.87°; 54.07°; 59.24°; 52.93° 8.74 159.2 ps; 39.3°; 20 dB 8.76 200 H z 8.77 1 0 H z ; 2000 8.78 1/107?C; 1/RC; 1/100RC/, 9.1/RC 8.79 10 H z ; 15.9 n F 8.80 58.8 p F ; 38.8 M H z Mf
M
M
4
Lf
7
L
M
M
- 3
n
l2
2
X
2
2i
2
l
2
22
1
2
u
1
l2
2
1
2
21
3
22
F
E
4
CHAPTER 6
4
6.4 12; 34 6.5 2.875 6.6 2 5 . 8 ; 1 m A ; 0.25 m A 6.8 0.5 m A ; 4 m A / V 6.10 0.4 m A / V ; 2 5 0 k Q ; 100 V / V ; 6 3 u m 6 13 16 7 G H z ; 2 3 . 9 G H z ; b e c a u s e the o v e r l a p c a p a c i t a n c e is n e g l e c t e d . 6.14 15 V / V ; 164.2 M H z ; 2 5 G H z 0 155 m A ; quadrupled to 0.62 m A ; 3.75 V / V ; 656.8 M H z 6.17 5.3 M H z ; 391 M H z 6.21 20 k Q ; 0.2 V ; 2 0 0 k Q - ' 5 fjA 6.24 80 pA; 0.3 V ; 0.8 V ; 3.2 11A 6.27 4: 2 5 , 5 0 , 2 0 0 , 4 0 0 pA; 3: 16.7, 4 0 , 133 pA; 1.53 V 6 2 9 (a) 10 u A to 10 m A ; 0.576 to 0.748 V 6.32 0.2 m A ; 1 0 % 6.35 (a) 2 m A , - 0 . 7 V , 5 V , 0.7 V, - 0 . 7 V , - 5 7 V- (b) 0.2 m A , - 0 . 7 V, 5 V, 0.7 V, 0.7 V , - 0 . 7 V 6.37 0.5 m A 6.40 (a) 2.07; (b) 7.02 6.41 (a) 10 rad/s; (b) 1 01 x 1 0 rad/s- 1 0 rad/s 6.42 5.67 x 1 0 rad/s 6.44 2.5 M H z ; 0.56 M H z 6.46 (a) -g R /(l + 5
7
6
m
F o r
=
0 : A
=
L
2
v
(b) R ^ ^ + Rya + gMiR^RL+R^ + ignfit/a+gJtM^ o=) ^ « - ^ /7'^: 4 5 3 5 k r a d / s G B W = 9.07 M r a d / s ; for R, = 100 Q : A = - 1 4 . 3 V / V , co = 6 2 4 . 3 krad/s, G B W = 8.93 M r a d / s ; for R = 250 Q- A = - 1 0 V / V , <% = 865.7 k r a d / s , G B W = 8.66 M r a d / s 6.48 4 0 . 6 V / V ; 243.8 ns; 3 1 0 0 n s ; 30 n s ; 47.2 k H z 6.53 (a) - 1 0 0 0 V / V , C = 1.001 n F , C = 1.001 p F ; (b) - 1 0 V / V , Q = 110 p F , C„ = 11 p F ; (c) - 1 V / V , C, = 20 p F , C = 20 p F ; (d) 1 V / V , C, = 0 p F , C = 0 p F ; (e) 10 V / V , C, = - 9 0 p F , C = 4 p F 6.59 0.905 V ; 1.4 V 6.65 (a) 0.5 m A ; (b) 100 k Q , 100 k Q , 5 0 k Q ; (c) 2.5 k Q , 2 0 m A / V ; (d) 2.5 k Q , 5 0 k Q , - 1 0 0 0 V / V 6.68 7.96 G H z ; 6 1 1 . 5 k H z ; 4 5 . 0 6 M H z ; 611 k H z ; 602.9 k H z ; 45.7 M H z 6.71 - 8 0 . 7 V / V ; 6.37 G H z ; 1.87 M H z ; 86.8 M H z ; 1.87 M H z 6.74 - 1 0 0 V / V ; 7.23 M H z ; 7 2 3 M H z 6.78 80 fF 6.83 932.6 Q ; 1.73 V 6.86 17.1 V/V; 557 M H z ; 3.79 M H z ; 3.79 M H z 6.90 50 k Q 6.93 0.97 A / A ; 2.63 M Q 6.98 v /v = r /{r + [1 + (g + g^r ]r } - l/g r 6.102 25 k Q ; 4 m A / V , 100 M Q ; - 2 x 1 0 V / V ; - 5 0 V / V 6.108 110 k Q ; - 1 0 0 V / V ; - 3 1 . 2 5 V / V ; 0.91 m A / V ; 0.45 V / V 6.116 (a) 2 m A ; (b) 8 m A / V , 1.6 m A / V , 10 k Q ; (c) 0.82 V / V , 103 Q ; (d) 0.75 V / V 6.120 0.964 V / V ; 5 4 4 M H z 6.122 (a) 2.51 M Q , - 3 9 4 3 V / V ; (b) 107.8 k H z , C d o m i n a t e s , 0
H
0
t
0
0
0
a
y
x
ol
ol
m2
5
o2
ol
m2
3
3
CHAPTER 9 9.21 36.3 pA 9.22 0.625 V ; for A, 7.3 m A / V , 134.3 Q , 6.85 k Q , 2 7 4 k Q ; for B , 21.9 m A / V , 44.7 Q , 2.28 k Q , 91.3 k Q 9.27 616 m V ; 535 m V ; 4.02 kQ. 9.29 4.75 pA; 1.94 k Q 9.31 56.5 k Q ; 9.353 pA 9.33 2 2 6 to 250; ± 5 % 9.36 6.37 k Q ; 2 7 0 pA 9.38 1.68 m A ; 50.4 m W 9.40 R a i s e 7?;, R to 4.63 k Q 9.43 0.96 m V 9.45 33.9 d B 9.48 3.10 M Q ; 9.38 m A / V 9.50 4.2 V t o - 3 . 6 V 9.52 2 1 m A 9.54 108 d B ; 61.9 Q ; 105.6 d B ; I V J < 4 V 9.56 11.4 M H z 9.58 6 3 7 k Q 9.60 159 k H z ; 15.9 M H z 9.62 six bits; 0.156 V ; s e v e n bits; seven bits; 0.117 V ; 0.059 V 9.65 7 / 1 6 ; 7 / 8 ; 7 / 4 ; 7 / 2 9.67 U s e o p a m p with R/2 input and 507? feedback to drive V ; 15 sine-wave a m p l i t u d e s , from 0.625 V p e a k to 9.375 V peak; an output of 10 V (peak-to-peak) corresponds to a digital input of (1000). 9.69 8.19 m s ; 4 . 0 9 6 m s ; 9.9 V ; n o , stays the s a m e ! 2
ref
CHAPTER 10
o2
L
10.1 1.5 V ; 1.5 V ; 1.5 V ; 0 V ; 3 V ; 1.5 V ; 1.5 V ; 0.35 V ; 0.35 to 0.45 V
10.4 (a) t = PLH
1.6 ns, t
m E
10.3 0.35 to 0.45 V ; 0.75 to 0.85 V ; 0 V ; 1.2 V ; 0.45 to = 0.8 ns; (b) C = 1 . 4 3 p F ; (c) C = 0.86 p F , C = 0.57 p F 0
t
H-5
iC.
APPENDIX H
1
10.6 0 . 4 3 6 ; 1.48 m W
ANSWERS T O SELECTED
PROBLEMS
ANSWERS T O SELECTED PROBLEMS
10.7 M a x i m u m o p e r a t i n g frequency is r e d u c e d b y a factor of (a) 0.66, (b) 0.44. DP
d e c r e a s e s b y a factor of 0.44 i n b o t h cases.
10.9 Effect of c h a n g e s i n d e v i c e d i m e n s i o n s is t o c h a n g e t h e
p e r f o r m a n c e parameters b y t h e factors: 0 . 8 1 , 1.11, 0.86, 0.77, 1 . 3 0 , 1 . 1 1 , 0.86, 1.60. 10.19 106 f F ; 68.5 p s
10.26 2 4
10.35 W i t h t h e p r o p e r sizing, t
A
B
=PD =
c
a n d n = n = 2n; n = n = 2(2n) = An. A
B
c
D
is o n e quarter t h e v a l u e o b t a i n e d with the smaller-size d e v i c e s ; t
PHL
in b o t h c a s e s .
10.33 p = p; p = p
10.14 9.1 m V ; 5 0 m V is the s a m e
PLH
10.38 (a) 0.69CR ;
(b) 0.5CR ,
D
+ 5 . 0 V ; 0.58 V ; 1.75 V ; 1.18 V
for a 2 7 . 5 % r e d u c t i o n
D
1 0 . 3 9 1.152; 1.76 V ; 3.25 V ; 2.70 V ;
10.40 2.4 f F ; 10.5 f F ; 63.5 p s ; 4 1 . 2 p s ; 52.4 p s ; 9.6 fF;-24.0 f F ; 72.5 p s ;
72.5ps;72.5ps
10.41 r - 2 ; A M
1.28V
183 pA; 111 p s
10.60 0.67 V ; 1.25 V
L m a x
10.43 1 . 3 3 ; 0 . 9 2 V
10.53 (a) 1 . 6 2 V ; 1 . 1 6 V ; 1 5 . 3 p A ; 3 5 1 . 6 p A ;
12.44 C = C = 1 n F ; R = R 4
6
l
4
= R = R = R = r = r = 159 k Q
2
3
5
6
l
/
"I
H-
2
8
1 2 . 4 8 (a) 7Y» = 0.451 x 1 0 ( s + 1 7 0 x 1 0 ) /
2
[(s + 0.729 x 1 0 ) ( s + 0.279 x 1 0 s + 1.05 x 1 0 ) ] ; (b) F o r L P section: C = 10 n F , R = R = 13 7 c » 4
2
4
8
x
F o r L P N section: C = 10 n F , R
1
R
=
= R = R = 9.76 k Q , R = 35.9 k Q , C
2
3
5
6
6 1
12.49, C=10nF;/?=15.9kQ;/v =/? =10kQ;/v =10kQ;/? = 390kQ;39V/V <
1
/
2
2
= 6.18 n F , C
k
= 3 82 n F '
6 2
12.51 ± 1 %
3
1 2 . 5 3 (a) F o r
only co , c h a n g e Q a n d r or R , or c h a n g e R a n d r or R ; R a n d R preferred; (b) F o r only Q c h a n g e only r z
3
or only R
3
2
3
3
2
12.55 R = 141.4 k Q ; R = 70.7 k Q 3
2
12.57 T(s) = -(16s/RQ/[s
4
2
co = A/RC; Q = 2; C e n t e r - f r e q u e n c y gain = 8 V / V
2
1 2 . 5 9 T(s) = s /[s
0
+ 16/(RQ ];
+ ( Q + C )s/R C C 2
High-pass; High-frequency gain = 1 V / V ; R = 141.4 k Q ; R = 70.7 k Q 3
2
+ 2s/RC 3
x
Bandpass-
+ 1
2
/R R C C ]; 4
3
X
2
12.60 For first-order section: Q = 3.18 n F ;
4
F o r o n e S a n d K section, the g r o u n d e d a n d floating capacitors are, respectively, C = 9 8 4 p F a n d C = 10.3 nF-
10.62 1.1 G H z
2
3
F o r t h e o t h e r S a n d K section, c o r r e s p o n d i n g capacitors are C = 2.57 n F a n d C = 3.93 n F , r e s p e c t i v e l y . 4
5
12.62 Sensitivities of co to R, L, C are 0, - \ , - I respectively, a n d of Q are 1, - 1 , | respectively. 0
CHAPTER 1 1 11.1 2 . 1 6 V ; 0 . 9 3 ; 1.86 large a s 2 1 m A (for R
on
(b) 1 0 k Q ; 7 2 1 p F
11.3 6
1 1 . 1 1 10.4 ps; 9.8 V ; 5.7 V ; - 0 . 1 V ; 21.5 m A ; T h e s o u r c e current c a n b e a s
= 2 0 0 Q ) , b u t is clearly limited b y k p of G ! t o a m u c h smaller v a l u e
11.14 9 7 . 2 %
1 1 . 1 8 16 bits
2
11.20 0.3 pm ; 0 . 3 9 p m x 0.78 pm
1 1 . 1 9 1024; 1024; 4 0 0 0 p F ; 2 2 5 p F ; 2 2 0 fF/bit; 2.8 times
11.2160%
11.22 4 ; 12; 2 8
11.30 1.589 mA/V; 11.36 pm; 34.1 pm; 1.56 n s (c) 1.46
11.27 3 2 M b i t s
11.36 2 6 2 1 4 4 ; 9; 1022
11.39 2.42 n s ; 2 2 ns, 3.16 V ; 1.9 n s
11.44 0.329 V W ; 8.94 V W ; 0.368 V W 11.49 7 c m
11.51 (W/L)
= 5pm/l
P
9 1 . 1 k Q ; f o r / v : 5 0 % ; 6.70 k Q ; 2 0 % ; 16.7 k Q ; 5 0 % ; R /R 2
1
50.7 p s ; 6 7 . 0 p s
1 1 . 5 6 (W/L)
= (W/L)
QNA
11.35 9; 1024; 4 6 0 8 ; 5 1 2 ; 5 6 4 1 ; 521
11.41 33.3 M H z ; high for 13 n s ; l o w for 17 n s
11.52 2.32 V ; 3 . 8 8 m A l
= 2(W/L) ;,
QM
(W/L)
Q
x
= 5.45
2
=
QPB
3
4
x
s = oo;ci =l/RC;Q
a
= li'Gamat
h
2
2
R=
29R;f
0
= 0.065/KC
13.15 20.3 V .
m
L
+
g
0
x
L
x
-LJi /R ,
2
R
6
2
x
V
2
m
1
13.36 R =R = x
A
2
B
9 0 ° , 0 . 7 0 0 V,
6
3
2
6
2
2
6
2
2
12.9 T(s) = 0.2225 ( s + 4 ) / [ ( s + l ) ( s + s + 0.89)]
2
12.11 T(s) = 0 . 5 / [ ( s + l ) ( s + s + l ) ] ; poles a t s = - l , - l + j ^ / 2 , 3 z e r o s at s = <*> 12.15 TV = 5 ; / = 10.55 k H z , a t - 1 0 8 ° , - 1 4 4 ° , - 1 8 0 ° , - 2 1 6 ° , - 2 5 2 ° ; 0
3
3
P
l
3
3
3
3
3
4
p = - 2 0 . 4 8 4 x 1 0 - J 6 3 . 0 4 3 x 1 0 (rad/s); T(s) = co /[(s + COQXS + 1.618to s + co )(s + 0.618ft) s + 3
3
5
5
2
2
0
12.19 R = 10 k Q ; / ? = 100 k Q ; C = 159 p F x
2
H i g h - f r e q u e n c y gain = - 1 0 0 V / V 6
2
1 2 . 2 5 T(s) = !0 /(s +5+1) 2
x
5
12.27 R = 4 . 5 9 k Q ; R = 10 k Q x
2
5
x
(b) 0.01 pF, (c) 1000 p F ; F o r R = 100 k Q and R 5
1
2
2
+ RCs); 2.68 k Q , 5.77 k Q , 10 k Q , 17.3 k Q ,
12.39 L j / Z ^ = 0.235; \T\ = Z ^ / ( L + LJ; \T\ = 1 12.43 R =R
col)];
12.33 L = 0.5 H ; C = 2 0 n F
1 2 . 3 7 Split R into t w o parts, leaving 2R i n its place and adding 2R
0
(b) 1000 p F , (c) 100 p F
x
12.30 T(s) = (s + 1.42 x 1 0 ) / ( s + 3 7 5 s + 1.42 x 1 0 )
2
0
k Q ; C = 0.159 pF; C = 1.59 n F ;
2
6
2
2
0
12.21 R = l k Q ; R =l
+ 1 0 s + 1 0 ) ; 7 0 7 rad/s; 1.16 V / V
12.35 V (s)/V;(s) = s / ( s + s/RC + l/LQ from the output to ground.
0
1 2 . 2 3 T(s) = (1 - RCs)/(l 3
1
=
R
2
12.40 F o r all resistors = 10 k Q ,
= R = 10 k Q , C is (a) 0.01 pF, 3
= R = R = 3979 Q ; R = 39.79 k Q ; C 3
5
2
= V (1 + R /R )-L_R /R ; R
x
2
X
6
4
6 1
= 6.4nF; C
62
= 3.6 n F
+
L
(b) R = 2 0 0 k Q ,
2
2
13.29 V = 6.8 V ; R =R = 37.5 k Q ; R = 4.1 k Q z
x
2
13.33 V = 6 . 8 V ; R = R
2
z
1
2
=R =R =R =
100 k Q ; i ? = 134.1 k Q ; / ? = 4 7 0 k Q ; 6.5 V ; 61.8 ps.
3
4
5
3
4
13.38 (a) 9 . 1 k Q ; (b) 1 3 . 3 V
1 3 . 4 1 V = 1.0996 V ; R = 4 0 0 Q ; T a b l e r o w s , for v , 0, 0.7 sin 6, error % are: 0
0.40 V, 3 2 . 8 ° , 0.379 V , 5 . 6 % ; 0.30 V , 2 4 . 6 ° , 0.291 V , 3 . 1 % ;
12.13 28.6 dB
= - 2 0 . 4 8 4 x 1 0 + J 6 3 . 0 4 3 x 1 0 (rad/s),
p = - 5 3 . 6 2 8 x 1 0 + ; 3 8 . 9 6 3 x 1 0 ( r a d / s ) , p = -Gh = - 6 6 . 2 8 8 x 1 0 r a d / s , p = - 5 3 . 6 2 8 x 1 0 - J 3 8 . 9 6 3 x 1 0 (rad/s), 2
X
0.50 V , 4 1 . 3 ° , 0.462 V , 8 . 3 % ;
6
+ 1618s + 1 0 ) ] , low-pass;
+ 1 0 ) ( s + 618s + 1 0 ) ( s + 1618s + 1 0 ) ] , high-pass
3
2
13.23 F r o m 2 . 0 1 6 1 2 M H z t o
0.55 V , 4 6 . 1 ° , 0.504 V , 9 . 1 % ;
1 2 . 5 0 . 5 0 9 r a d / s ; 3 r a d / s ; 5.90 2
+
L
+ (C L/R )}
0%;
0.010 VA7, - 8 9 . 4 ° , - 4 0 . 0 d B , 4 0 . 0 d B 3
x
3
7
0.65 V , 6 3 . 6 ° , 0.627 V , 3 . 7 % ;
1 5
x
3
2
- 100 k Q ; R = 5.0 k Q ; O u t p u t is a s y m m e t r i c triangle with half p e r i o d of 5 0 ps a n d ± 7 . 5 V p e a k s .
0.60 V, 5 2 . 4 ° , 0 . 5 5 4 V, 8.2%;
4
m
2
2
3
= C /C .
3
l/R C s ];
+ (C L/R )s
F o r circuit (c): LC C s
/? = 6.67kQ;/? = 5 0 k Q ; / v = 2 4 k Q , / v = 2 7 k Q .
0.100 V/V, - 8 4 . 3 ° , - 2 0 . 0 d B , 20.0 d B
C is (a) 0.1 pF,
R /R )
L
3
e a k )
13.28 (a) E i t h e r + 1 2 V o r - 1 2 V ; (b) Symmetrical square w a v e of f r e q u e n c y / a n d amplitude ± 1 2 V,
R
0.70 V ,
12.28 T(s) = s /(s
m
gR
x
= V (l+
0.196 V/V, - 7 8 . 7 ° , - 1 4 . 1 d B , 14.1 d B
12.3 1.000; 0 . 9 4 4 ; 0 . 0 1 0
5/i?c¥ +
( p e a k t
co= l/RC;
V = 0.0476 V.
TL
Z
12.8 T(s) = 1 0 / [ ( s + 1 0 ) ( s + 6 1 8 s + I0 )(s
0
-coRQ];
13.25 (a) V
13.31 V =3.6V,
dB
+ 6/i?Cs +
= C /C ;
a n d lags the input b y 65.4°. M a x i m u m shift of a v e r a g e is 0.1 V . dB, 0
6
-j(l/coRC2
2.01724MHz.
0.447 V/V, - 6 3 . 4 ° , - 6 . 9 9 d B , 6.99 d B
2
2
2
13.35 96ps
2
l
[(C + CJ/C^Lf ;
13.39 R = 2 1 . 3 k Q ; R = 10.7 k Q
37.3 k Q
3
2
gR
10 k Q ;
5
13.12 R = R = 6.5 k Q ; v = 2.08 V
L(jco) = (1 + R /R{)/[3
13.17 Ap%s) = -(R/R)/[l
2
= Q;co =
m
2
w i t h m a g n i t u d e zero at s = 0 ,
2
13.21 For circuits (a), (b), (d), characteristic equation is: Q Q L s
0.707 V/V, - 4 5 . 0 ° , - 3 . 0 1 d B , 3.01 d B
27.8dB
2
1
for o s c i l l a t i o n , , ^ / / ? ! = 2.
2
1/jLC
0
13.6 U s e R = R =
+ 3s/RC + l/R C ];
1 3 . 1 0 co = l.l6/CR.
2
(Ci + C )s + l/R
0.894 V/V, - 2 6 . 6 ° , - 0 . 9 7 d B , 0.97 d B
5
0
= \.
Q
2
= (s/RC)/[s
13.13 L(s) = (1 + i ? / / v ) ( s / / v O / [ s + s 3 / i ? C + l/R C ];
R
0°, 0
2
13.9 V (s)/V (s)
= R = 5 k Q ; R = 50 k Q
13.3 T o non-inverting input,
j
R
2
QP
J
X
V2
CHAPTER 1 2
T(s) = s /[(s
1
(C, + C )s + 1 //?£ + g = 0 ; C0Q — K Q + C )/C C L] ;
(W/L)
(c) AcOr /cc\ = -Acp/2Q.
0
> 1.0; U s e R = 10 k Q , R = 100 Q (say); co =
13.5 M i n i m u m gain is 2 0 d B ; p h a s e shift is 180°.
2
12.1 1 V A 7 ,
0
(a) - \ % \ , (b) - \ % ; (c) 0 % .
f
11.54 8 3 . 2 p s ;
= {W/L)
QPA
11.47 2 1 . 2
11.53 F o r R : 5 0 % ; 3 6 . 5 k Q ; 2 0 % ;
= 5.45; 2 0 % ; R /R
2
(b) dcb/dco at co = co is -2Q/co ;
0
2
11.32 ( b ) 2 ;
11.45 (a) - 1 . 3 7 5 V, - 1 . 2 6 5 V; (b) - 1 . 4 9 3 V , - 1 . 1 4 7 V pm; 6 . 5 m A
13.1 (a) co=co ,AK=l;
c o n n e c t L C t o g r o u n d a n d R t o output; A = 1 + R /R
11.29 2 p A
11.31 0.68 mAJV; 0.48 V ; 0.21 V ; 5 0 % ; 7.5 n s
11.34 9 ; 5 1 2 ; 18; 4 6 0 8 N M O S a n d 5 1 2 P M O S transistors
CHAPTER 13
11.13 (a) 1.39CR;
0.20 V , 16.4°, 0.197 V , 1.5%; 0.10 V ,
8.2°, 0 . 1 0 0 V,
0%;
0.00 V ,
0 ° , 0.0 V ,
0%.
13.42 ± 2 . 5 V 13.45 Table r o w s ; circuit v /V , 0.250, 0 . 4 5 1 , 0 . 2 5 9 , - 3 . 6 % 0
0.500, 0 . 9 0 5 , 0 . 5 1 7 , - 3 . 4 % 1.000,1.847,1.030,-2.9% 1.500, 2 . 8 8 6 , 1 . 5 3 5 , - 2 . 3 % 2.000, 4 . 1 9 7 , 2 . 0 3 5 , - 1 . 7 % 2 . 4 0 0 , 6.292, 2 . 4 1 3 , - 0 . 6 % 2.420,6.539,2.420, 0.0%
T
circuit Vj/V , T
ideal v /v , 0
T
a n d error as a % of ideal are:
H-y
.
APPENDIX H A N S W E R S T O S E L E C T E D P R O B L E M S
13.47 i ? = / ? = 1 0 k Q ( s a y ) ; 3 . 1 8 V 13.49 R = 1 M Q ; R = 1 M Q ; R = 4 5 k Q ; R = 1 M Q ; C = 0.16 /JF for a corner frequency of 1 H z . 13.53 U s e o p a m p circuit w i t h v c o n n e c t e d t o p o s i t i v e input, L E D b e t w e e n output and negative input and resistor R b e t w e e n negative input and ground; I = v /R. 13.54 i =C \dv/dt\; C - 2.65 /xF; 4fi2o = ' m 6 o ; 'miso = 3%6o; s as a linear frequency m e t e r for fixed input a m p l i t u d e ; w i t h C, h a s a d e p e n d e n c e on w a v e f o r m rate of c h a n g e ; 1.272 m A . 13.55 10 m V , 2 0 m V , 100 m V ; 5 0 p u l s e s , 100 p u l s e s , 2 0 0 p u l s e s 1
2
T
2
3
4
A
LED
2
j
A
M
A c t
CHAPTER 14 14.1 U p p e r limit ( s a m e i n all cases): 4.7 V , 5.4 V ; l o w e r limits: - 4 . 3 V , - 3 . 6 V ; - 2 . 1 5 V , - 1 . 4 5 V 14.4 152 Q ; 0.998 V / V ; 0.996 V / V ; 0.978 V / V ; 2 % 14.6 V I 14.9 5 V 14.11 4 V ; 1 2 . 8 % ; 11.1 Ml 14.13 5.0 V peak; ' 3.18 V p e a k ; 3.425 Q ; 4.83 Q ; 3.65 W ; 0.647 W 14.15 vl/R ; V V„/R ; V /V ; 1 0 0 % ; V ^ ; V /R ; V / 2 ; 50% 14.17 2.5 V 14.19 12.5 14.21 2 0 . 7 m A ; 7 8 8 m W ; 7.9°C; 37.6 m A 14.23 1.34 k Q ; 1.04 k Q 14.25 5 0 W ; 2.5 A 14.27 140°C; 0.57 V 14.29 100 W ; 0.4°C/W 14.31 0.85 Q 14.33 0 m A , 0 m A ; 2 0 pA, 22.5 LiA; - 2 0 p.A; - 2 2 . 5 pA 14.35 1.96 m A ; 38.4 pA; out of b a s e 1 a n d into b a s e 2 ; 3.4 pA; 211 k Q ; 0.94 V / V 14.37 0.033 m A ; 6 6 m A / V ; - 6 6 V / V ; 13.6 k Q 14.39 ^ = 3 0 0 kQ;\f? = 6 3 2 k Q ; 9.48 V ; - 1 0 . 6 5 V 14.41 13 Q ; 4 3 3 m V ; 0.33 /jA 14.43 R = 6 0 k Q ; R = 5 k Q ; 0.01 jiA 14.45 I =I -llpA;I = I -358/iA;I -I = 341 M ; 10.5 V 14.47 14 V ; 1.9 W ; 11 V 14.49 R =R = 4 0 Q ; R =R = 2.2 k Q 14.51 4 0 k Q ; 5 0 k Q 14.53 L = p,„(v - V,)/U ; 3 j i m ; 3 A ; 1 A7V CC
2
L
SS
L
0
ss
SS
L
ss
2
T
2
E1
3
GS
4
m
x
E3
m
E5
E6
2
sat
Numbers 2-input NAND (not AND) gates. See Two-input NAND (not AND) gates 2-input NOR (not OR) gates. See Two-input NOR (not OR) gates 2-integrator loop technologies. See Two-integrator loop technologies 2-port network parameters. See Two-port network parameters 2-stage CMOS op amps. See Two-stage CMOS op amps 3-dB bandwidth. 326-327 555 timer circuits. 1198-1203 741.op amp circuits, 893-899, 905-922, 942-946
APPENDIX B A 4
B.2 h
= 2.6 k Q ; h
B.3 y
= \/r + s{Cx+, C ); y
u
n
n
= 2.5 x 1 0 " ; h
2l
K
M
l2
5
= 100; h
22
= 2 x 1 0 " 13
= -sC^; y , = -sC^ + g , y 2
m
22
= l/r„ + sC^
APPENDIX C C . l Z =V /I t
oc
x
C.3 I V , 0.90 k Q ; 0 . 5 2 6 V
C.5 R
in
= (r + R )/(1 n
B
+
gr) m
K
APPENDIX D D.2 D.9
5
V (s)/V {s) = R /(R +R) D . 4 1 0 r a d / s D . 6 H P ; 1 0 r a d / s D . 7 v (t) = 10(1 - e ~ 3.5 n s D . l l - 4 . 6 7 V D . 1 3 - 6 . 3 2 V ; 9.5 m s D . 1 5 '14:4 jus 0
i
2
x
2
0
t
m
1 0
~ \ v {t) = l O e " ^ 0
APPENDIX E E. 1 V (syVi(s) = RC /(l + sR(C + C ) ) ; S T C with C = C IIC \ h i g h - p a s s ; zero at 0 H z ; p o l e at 1.59 H z E.5 10 k H z ; 5.1 k H z ; 1.05 k H z E . 1 0 0 d B , - 9 0 ° ; + 0 . 0 4 d B , - 9 5 . 0 ° 0
lS
x
2
e q
X
2
Absolute value circuits, 1211 Absoiption source theorems, C3-C5 Abstractions, 955 Ac amplifiers, 39 Ac circuits, 53-54 Ac grounds, 306 Ac voltage measurements, 1209-1210 Acceptors, 195-196 Access times, 1030 Active filters, 1084, 1112-1125. 1161-1162, 1177-1179, 1217-1219 Active loads, 582-588, 600-613, 727-740, 782-784 Active modes, 379-386 Active RC filters, 1084 ADCs (analog-to-digital converters), 12, 930-932 Address decoders, 1043-1045 Advanced digital circuits and memory, 1013-1082. See also Memory and advanced digital circuits Aids, digital circuit design, 955 Algorithms, filtering, 922 All pass, 1101, 1111-1120 circuits, 1118-1120 filters, 1101 functions, 1111-1112 All pole filters, 1090 Amplifiers. See also under individual topics ac amplifiers, 39 bandpass amplifiers. 40 bandpath amplifiers, 40 bipolar op amps, 758-766 BJT amplifiers and switches, 407^121 bridge amplifiers. 1265-1266 buffer amplifiers, 24 cascaded amplifiers, 25-27 cascode amplifiers, 613-629, 1146-1147 CB amplifiers, 474-^178, 600-613 CC amplifiers, 478-483 CC-CB amplifiers. 646-648 CC-CE amplifiers. 641-646 CD-CE amplifiers, 641-646 CD-CG amplifiers, 646-648 CD-CS amplifiers, 641-646 CE amplifiers, 461-475, 582-600 CG amplifiers, 311-315, 600-613 closed-loop amplifiers, 91-94 common drain (grounded drain) amplifiers, 315-318
CS amplifiers, 306-311, 326-336, 372-374, 582-600 current amplifiers, 28, 799-801 dc amplifiers, 39, 66, 572 differential amplifiers, 65-66, 81 fixed gain amplifiers, 1261-1265 instrumentation amplifiers, 85-89 inverted op amps, 68-77, 124-128 linear amplifiers, 274-275 LP amplifiers, 39 MOS amplifiers, 299-320, 370-372 multistage amplifiers, 749-767, 786-789 nonlinear amplifiers, 1205-1206 nonunilateral amplifiers, 301, 461 overviews and summaries, 13-31, 55-61 poles, 836-845, 869-870 power amplifiers, 14, 1249-1282 BJT amplifiers, 1249-1256, 1279-1280 IC amplifiers, 1261-1266, 1281-1282 MOSFET amplifiers, 1266-1270 overviews and summaries, 14 preamplifiers, 14, 797 series-series feedback amplifiers, 801-802, 811-818,865-866 series-shunt feedback amplifiers, 802-810, 863-865 shunt-series feedback amplifiers. 799-801, 818-831, 866-867 shunt-shunt feedback amplifiers, 802. 818-831, 866-867 single amplifier biquadratic active filters, 1125-1133, 1162 single difference amplifiers, 81-86 single-stage amplifiers, 299-320, 370-372, 460-485, 533-537, 545-686 source-follower amplifiers, 315-318 transconductance amplifiers, 28, 271, 802-804 transfer characteristics, 14-15 transmissions, 32 transresistance amplifiers, 28, 804 tuned amplifiers, 40. 1083-1164. See also Filters and tuned amplifiers two-stage CMOS op amps, 749-757. 872-883, 941 unilateral amplifiers, 301, 461 unity-gain amplifiers, 79-80, 315 voltage amplifiers, 14, 23-25, 28 Amplitude, 32, 1168-1169 nonlinear controls, 1168-1169 responses (magnitudes), 32 Analog and digital ICs (integrated circuits), 542-1008. See also under individual topics CMOS logic circuits, 949-1008 differential and multistage amplifiers, 687-791 feedback, 791-870 op amp and data-converter circuits. 871-948 overviews and summaries, 543 single stage IC amplifiers, 545-686 Analog signals, 10-13, 922-923 vs. digital signals, 10-13 sampling, 922-923 Analyses. See also under individual topics BJTs,415^tl9,457 circuit analyses, 53 forward characteristics, 154-155
graphical analyses, 415^119 rapid analyses, 155 i domain analyses, E1-E8 small signal operations, 457 AND logic functions, 145 Anodes, 141, 187 Answers (problems), selected, H1-H8 Antoniou inductance simulation circuits, 1112-1114 Architectures and types, memory, 1028-1031 1078-1079 Astable circuits, 1022, 1026-1027 Astable multivibrators, 1192-1196 Attenuation functions, 1084 Audio bands, 9 Augmentations, early effects, 457-458 Autotransformers, 1144-1145 Avalanches, 203, 260 effects, 203 weak, 260
B Backgates, 296 Bandpath amplifiers, 40 Bands. See also under individual topics audio bands, 9 bandwidth. See Bandwidth dead bands, 1236 digital bands, 10-11 frequency bands, 326-327 high-frequency bands, 326 low-frequency bands, 326 midbands, 326 narrow bands, 1149 Bandwidth. See also under individual topics 3-dB bandwidth, 326-327 CS amplifier frequency responses, 326-327 extensions, 795-796 full-power bandwidth, 97-98 functions, 1108-1109 GB products, 91-93 infinite bandwidth. 66 op-amp effects, 89-94, 134-135 overviews and summaries, 32-33 unity-gain bandwidth, 91, 488 Barkhausen criterion, 1167-1168 Barriers, 198 Bases. See also individual topics base-charging (diffusion) capacitances, 486 base-emitter junction capacitances, 486 BJTs, 379 CB amplifiers, 474^178 CBJs, 379 collector-base junction capacitances, 487 collector-to-base feedback resistors, 441^142 currents, 445^146 EBJs, 379 forward base-transit times, 486 input resistances, 445^-46 Basic circuits and devices, 2-542. See also under individual topics BJTs. 377-542 diodes, 139-234 electronics overviews, 5-62 MOSFETs, 235-377 IN-1
8SM-2
'
"
INDEX
Basic circuits and devices (Continued) op amps, 63-138 overviews and summaries, 3 Battery-plus-resistance models, 156-157. 166 Bias and biasing, 19-22. See also under individual topics bias circuits, 893-899 BJTs, 436-443 class AB output stage, 1244-1249 classical discrete circuit bias, 436^441 dc biasins, 19, 271 forward bias, 141-152, 204-208 diodes, 141 £>« junctions, 204-208 terminal junctions, 148-152 input bias, 102-105, 725-726, 899-901 currents, 102-105 differential amplifiers, 725-726 input state bias, 899-901 MOSFETs, 280-287, 367-368 overviews and summaries, 19-22, 436 pn junctions, 199-208 problems, 528-530 reference bias currents, 899 reverse bias, 141, 199-203 diodes, 141 pn junctions, 199-203 single-stage IC amplifiers, 562-571 V _ multipliers biasing, 1246-1249 Bibliographies, F1-F2 BiCMOS digital circuits, 628-629, 952, 1067-1076,1082, A9-A12 cascode, 628-629 dynamic operations, 1069-1070 inverters, 1067-1069 logic gates, 1070-1071 overviews and summaries, 952 SiGe BiCMOS processes, A11-A12 VLSIs, A9-A10 Bilinear transfer functions, 1098 Binary number systems, 11 Bipolar circuits, 951-952 ECL circuits, 951-952 TTL circuits, 951-952 Bipolar differential pairs, 723-726, 733-735 Bipolar mirrors, 650-651 Bipolar op amps, 758-766 Bipolar pairs, 725-726 Biquadratic (second order) filter functions, 1098-1106, 1160-1161 Biquads, 1120-1122 Bistable multivibrators, 1185-1192, 1223-1224 Bit lines, 1029 BJTs (bipolar junction transistors), 377-542 amplifiers and switches, 407-421, 521-524 CE circuits, 410-412 EOS points, 419 gain, 412-414 graphical analyses, 415-419 overviews and surnmaries, 407-410 problems, 521-524 switch operations, 419—421 transfer characteristics, 410^+12 bias and biasing, 436-443, 528-530 classical discrete circuit bias arrangements, 436^141 collector-to-base feedback resistors, 441-442 overviews and summaries, 436 problems, 528-530 cascode, 623-625 CE frequency responses, 538-540 current-voltage characteristics, 392-407, 518-519 CE characteristics, 401-407 circuit symbols and conventions, 392-397 overdrive factors, 403 overviews and summaries. 407 problems, 518-519 sustaining voltage, 406 transistor characteristics, 397—4-01 dc circuits, 421-436, 524-528 overviews and summaries, 421—436 -problems, 524-528 differential pairs, 704-720, 777-780 B
E
INDEX
digital logic inverters, 503-507, 540-541 current-mode logic, 506-507 overviews and summaries, 503-504 problems, 540-541 saturated vs. unsaturated digital circuits, 505-507 TTL, 505-506 VTCs, 504-505 high frequency models, 485—491 internal capacitances, 485-491, 537-538 base-charging (diffusion) capacitances, 486 base-emitter junction capacitances, 486 collector-base junction capacitances, 487 cutoff frequencies, 487—+90 forward base-transit times, 486 high-frequency hybrid-% models, 487 high-frequency responses, 492-497 low-frequency responses, 497-503 Miller effect, 496 Miller multiplier, 496 overviews and summaries, 485—486, 488-492 problems, 537—538 small-signal diffusion capacitances, 486 unity-gain bandwidth, 488 models, 443^60 overviews and summaries, 377-378, 516-517 power amplifiers, 1249-1256, 1279-1280 problems, 517-541 single-stage amplifiers, 460^-85, 533-537 bypass capacitors, 467 CB amplifiers, 474-478 CC amplifiers, 478^183 CE amplifiers, 461-475 characteristics, 461—+66 coupling capacitors, 468 current buffers, 477 emitter degeneration resistances, 474 eirritter followers, 478^183 nonunilateral amplifiers, 461 overviews and summaries, 460, 483—485 problems, 533-537 resistance reflection rules, 472 structures, 460-461 unilateral amplifiers, 461 small-signal operations, 443-460, 530-533 analyses, 457 base currents, 445-446 collector currents, 443^445 dc quantities, 448 early effect augmentations, 457—458 emitter currents, 446-447 equivalent circuits, 450—457 hybrid-/! models, 448-449 input resistance at bases, 445^446 input resistance at emitters, 446-441 overviews and summaries, 443, 458^459 problems, 530—533 signal separations, 448 T models, 449-450 transconductances, 443^445 voltage gain, 447 SPICE simulations, 507-516 examples, 512-516 Gummel-Poom models, 509-510 overviews and summaries, 507-509 parameters, 510-512 structures and operations, 378-392, 517-518 active modes, 379-386 bases. 379 CBJs, 379 collectors, 379 cutoff modes, 379 EBJs, 379 EM models, 387-390 emitters, 379 npn transistors, 392 overviews and summaries, 378-380 injunctions, 379 pnp transistors, 391-392 problems, 378-392, 517-518 reverse active (inverse active) modes, 379 saturation modes, 379, 390-392 transistor structures, 386-387
Bode plots, 36, 845-849, E3-E6 Body effects. 259, 296-297 models, 296-297 parameters, 259 Bonds, covalent. 191 Bound charges. 196 BP (bandpass). 40, 1085, 1149-1150 amplifiers. 40 BP-to-LP transformations. 1149-1150 filters, 1085 Break frequencies, 36 Breakdowns, 152-153, 167-187, 203-204, 259-260, 1255 MOSFETs, 259-260 regions, 152-153, 203-204 second breakdown limits, 1255 voltage, 152-153 zener diodes, 167-171, 187 Breakpoint methods, 1203-1205 Brick wall responses, 1085 Bridge amplifiers, 1265-1266 Bridge oscillators, 1171-1174, 1215-1217 Bridge rectifiers, 176-177, 1212-1213 BS (bandstop) filters, 1085 Buffers, 24,477,1213-1214 buffer amplifiers, 24 buffered precision peak detectors, 1213-1214 current buffers, 477 Built-in voltage, 198-199, 209 Butterworth filters, 1091-1098, 1159-1160 Bypass capacitors, 306, 467
c Capacitances. See also under individual topics base-charging (diffusion) capacitances, 206-208, 486 base-emitter junction capacitances, 486 collector-base junction capacitances, 487 depletion (junction) capacitances. 200-203, 206-208, 322 internal capacitances, 38, 320-325, 372, 485-491,537-538 overlap capacitances, 321 small-signal diffusion capacitances, 486 Capacitors. See also under individual topics bypass capacitors, 306, 467 clamped capacitors (dc restorers), 187-189 coupling capacitors, 38, 468 fabrication technology, A9 filter capacitors, 177-183 switched-capacitor filters, 1136-1141, 1162-1163 VLSIs, A9 Carriers, 197-209 carrier-depletion regions (space-charge regions), 197-199 concentrations, 208-209 intrinsic silicon, 208 n-type silicon, 208 retype silicon, 209 drift. 193 holes, 191 positively charged carriers, 191 Cascade amplifiers, 25-27, 1146-1147 CC-CB cascade amplifiers, 1146-1147 overviews and summaries, 25-27 Cascading dynamic logic gates, 995-996 Cascode amplifiers, 613-629, 1146-1147 Cascode MOS mirrors, 649-650 Cases, transistors, 1251-1254 Cathodes, 141 CB (common-base) amplifiers, 474-478, 600-613 CBJs (collector-base junctions), 379 CC (common-collector) amplifiers, 478^183, 641-648, 1146-1147 CC-CB amplifiers, 646-648 CC-CB cascade amplifiers, 1146-1147 CC-CE amplifiers, 641-646 overviews and summaries, 478-483 CD-CE amplifiers, 641-646 CD-CG amplifiers, 646-648 CD-CS amplifiers, 641-646 Center frequencies, 39, 1102
Center tapped secondary windings, 174 CEs (common.emitters), 401-412, 461-475, 538-540;582-600 amplifiers, 461-475, 582-600 BJTs, 410^112 characteristics, 401^107 frequency responses, 538-540 CG (common gate) amplifiers, 600-613 Channels, 238-258 channel-length modulations. 253 current flow channel creation, 238-239 MOSFETs, 238 n channels, 238 ,,. p channels, 256-258 Characteristics. See also under individual topics amplifier poles, 838 BJTs, 401-407 " CE characteristics, 401^107 CMOS logic circuits, 952-954 current-voltage characteristics. See Currentvoltage characteristics _ differential amplifiers, 720-727, 781-782 digital circuit design, 952-954 • digital logic inverters, 504-505 diodes, 140-141, 153-167, 223-227 forward characteristics, 153-167, 223-227 ideal op amps, 66 MOS amplifiers, 301-306 p channels, 256-258 parameters. See Parameters pseudo-NMOS logic circuits, 975-979 single-stage amplifiers, 301-306, 461-466 sinusoidal oscillators, 1168 terminal junctions, 147-153, 222-223 transfer characteristics. See Transfer characteristics two-port networks, B1-B6 voltage transfer characteristics, 504-505 VTCs, 41-42, 976-979. See also VTCs (voltage transfer characteristics) Charges, 191-199, 932-534. 992. 1091-1098, 1159-1160 bound, 196 charge redistribution converters, 932-934 charge sharing, 994-995 holes, positively charged carriers, 191 précharge phases, 992 space charge regions, 197-199 uncovered charges, 197 Chebyshev filters, 1091-1098, 1159-1160 Chips, ICs (integrated circuits), 5 Chokes, RFCs, 1146 Circuits (basic) and devices, 2-542. See also under individual topics bias and biasing. See Bias and biasing BJTs, 377-542 designs. See Designs, digital logic circuits diodes, 139-234 electronics overviews, 5-62 MOSFETs, 235-377 op amps, 63-138 overviews and summaries, 3 symbols and conventions, 392-397 Clamped capacitors (dc restorers), 187-189 Clamping and limiting circuits, 184-190, 1214 Class A output stage, 1231-1235, 1277-1278 Class AB output stage, 1241-1249, 1256-1261, 1270-1271, 1278-1281 Class B output stage, 1235-1241, 1278 Classical discrete-circuit bias arrangements, 436^141 Classical sensitivity functions, 1133-1134 Classifications, 1230-1231, D4-D6 output stages and power amplifiers, 1230-1231 STC (single-time constant) circuits, D4—D6 Clippers, 185 Clocked SR flip-flops, 1019-1021 Closed loops, 69-94, 794, 834 amplifiers, 91-94 gain, 69-71, 794 transfer functions, 834 Closure rates, 849 CMOS (complementary MOS) logic circuits, 949-1008
digital circuit design, 950-955, 1002-1003 abstraction and computer aids, 955 characteristics. 952-954 digital IC technologies, 950-952 DP products, 954 gate fan-ins and fan-outs, 954 logic circuit families, 950-952. See also Logic circuit families noise margins, 952-953 overviews, 950 power dissipations, 953-954 problems, 1002-1003 propagation delays, 953 silicon regions, 954 styles, 954-955 dynamic logic circuits, 991-998, 1008 cascading dynamic logic gates, 995-996 charge sharing, 994-995 domino CMOS logic, 996-998 evaluation phases, 992 leakage effects, 994 noise margins, 993-994 nonideal effects, 993-996 output voltage decay, 994 overviews and summaries, 991-992, 998 précharge phases, 992 problems, 1008 structures, 992-993 inverters. 336-346, 374-375, 955-953, 1003-1004 dynamic operations, 958-961 dynamic power dissipations, 962-963 overviews and summaries, 336-346, 374-375, 955 problems, 1003-1004 static operations. 956-958 structures, 955-956 logic-gate circuits, 963-973, 1004-1005 complex gates, 967-968 fan-in and fan-out effects. 973-974 NMOS pull-down transistors, 963-966 overviews and summaries, 963 PDNs, 973-974 PMOS pull-up transistors, 963-966 problems, 1004-1005 propagation delays, 973-974 PUNs, 963-966, 968-969 structures, 963-966 synthesis methods, 970 transistor sizing, 970-973 two-input NAND gates, 966-967 two-input NOR gates, 966 XOR functions, 969-970 monostable circuits, 1022-1026 MOSFET models, 998-1001 rc-well processes, A5-A7 op amps, 872-893, 941-942 folded cascade CMOS op amps, 883-893, 941-942 two-stage CMOS op amps, 872-883, 941 overviews and summaries, 949-950, 1002 problems, 1002-1008 pseudo-NMOS logic circuits, 974-982, 1005-1006 characteristics. 975-976 designs, 979-980 dynamic operations, 979 gate circuits, 980 inverters, 974-975 overviews and summaries, 974, 980-982 problems, 1005-1006 regions, 977-979 VTC derivations, 976-979 PTL circuits, 982-991, 1006-1007 CPL, 991 designs, 983-984 examples, 990-991 natural devices, 988 NMOS transistor switches, 984-988 overviews and summaries, 982-983, 991 problems, 1006-1007 transition fate switches, 988-989 SPICE simulations, 998-1001
IN-3
CMRR (common-mode rejection ratio) 81-82 700-704,715-716,732-733 Collectors. See also under individual topics BJTs, 379 ' CBJs, 379 CC amplifiers, 478-483 collector-base junction capacitances. 487 collector currents, 443-445, 904 collector-to-base feedback resistors, 441^142 dc collector currents, 904 Colpitts oscillators, 1179-1180 Column decoders, 1030 Combinational vs. sequential circuits, 1013-1014 Common modes. See also under individual topics CMRR, 81-82, 700-704, 715-716, 732-733 gain, 700-704, 715-716 half circuits, 716-717 input ranges, 726, 902 input resistances, 717-720 rejections, 65 signals, 67-68 voltage, 689-691 Comparators, 1189-1191 Compensation, 90-91, 849-855, 870 frequencies, 90-91, 849-855, 870 internally compensated op amps, 91 Complementary transformations, 1130 Complex gates, 967-968 Compound devices, 1257-1259 Computer aids, digital circuit design. 955 Concentration profiles, holes, 193 Conduction intervals, 180 Conjugate pairs, E2 Constants, 107-113, 157-166, 285-286 575-578, D1-D4 constant-current sources, 285-286 constant-voltage-drop models, 157-158, 166 open circuit constants, 575-578 time constants, 107, 113, 575-578, D1-D4 Conventions and symbols, 14, 22-23 248-'>49 392-397 Conversions, 727-728. 1236-1238 differential conversions, 727-728 power conversion efficiencies, 1236-1238 Converters, 12, 930-932. See also Data converter circuits ADCs, 12, 930-932 charge redistribution converters, 932-934 DACs, 12 dual slope converters, 930-932 parallel (flash) converters, 932 Corner frequencies, 36 Coupling capacitors, 38, 468 Covalent bonds, 191 CPL (complementary pass-transistor logic), 991 Crossover distortions, 1236, 1240 Crystal and LC (liquid crystal) oscillators, 1177-1185, 1222-1223 CS (common-source) amplifiers, 306-311, 326-336, 372-374, 582-600 CS (common-source) circuits, 271-272 Current amplifiers, 28, 799-831 current mixing-current sampling amplifiers, 799-801, 818-831, 866-867 current mixing-voltage sampling amplifiers, 802, 818-831, 866-867 overviews and summaries, 28, 799-801 Current-voltage characteristics, 205-206, 248-262, 360-362, 392-407, 518-519 Currents. See also under individual topics base currents, 445^146 collector currents, 443^145 current amplifiers. See Current amplifiers current buffers, 477 current dividers, 51-52 current mirrors. See Mirrors current-mode logic, 506-507 current-voltage characteristics. See Currentvoltage characteristics dc collector currents, 904 diffusion currents, 197 diodes, 140-141 drift currents, 198 emitter currents, 446-447 F
IN-4
INDEX
Currents (Continued) input bias currents, 102-105 input offset currents, 102-105 knee current, 167-168 offset currents, 725-726 output current limits. 94-95 reference bias currents, 899 wide swing current mirrors, 892-893 Cut-in voltage, 150 Cutoffs, 248, 379, 487-190 frequencies, 487—190 modes, 379 regions, 248 CVD (chemical vapor deposition), A7-A8 Cycle times, 1030 D DACs (digital-to-analog converters), 12, 925-929 Data converter circuits, 922-929, 946-947 ADCs, 929-934 analog signal sampling, 922-923 charge-redistribution converters. 932-934 DACs, 12, 925-929 digital signal processing, 922 dual-slope converters, 930-932 filtering algorithms, 922 LSBs, 925-926 MSBs, 925-926 parallel (flash) converters, 932 R-2R ladders, 926-928 S/H circuits, 923 signal quantization. 924 switches, 928-929 Dc (direct coupled) amplifiers, 39, 66, 315-318, 572 Dc analyses, 893-899 Dc bias and biasing, 19, 271 Dc circuits, 262-270. 362-366, 421^136, 524-528 BJTs, 421-436, 524-528 MOSFETs, 262-270, 362-366 Dc collector currents, 904 Dc imperfections, 98-105, 135-136 Dc offset voltage, output, 720-723 Dc quantities, 448 Dc restorers (clamped capacitors), 187-189 Dead bands, 1236 Decays, 994 Decoders, 1029-1030 column decoders, 1030 row decoders, 1029-1030 Degeneration, emitters, 474, 629-635 Degenerative (negative) feedback, 78, 795-798, 860-861 Delays, 45^18, 342-343, 953-954, 973-974 DP products, 342-343, 954 propagation delays. 45^18, 953, 973-974 Dependences, frequencies, 89-91 Depletions. See also under individual topics capacitances, 209 carrier depletion regions (space charge regions), 197-199 depletion (junction) capacitances, 200-203, 206-208, 322 depletion type MOSFETs, 346-351, 375 regions, 209 Depositions, CVDs, A7-A8 Derivations, VTCs, 976-979 Desensitivity, gain, 795 * Designs, digital logic circuits, 950-955, 1002-1003 abstractions and computer aids, 955 characteristics, 952-954 digital IC technologies, 950-952 DP products, 954 gate fan-ins and fan-outs, 954 .. logic-circuit families, 950-952. See also Logiccircuit families noise margins, 952-953 overviews and summaries, 950-955. 1002-1003 power dissipations, 953-954 problems, 1002-1003 propagation delays. 953 pseudo-NMOS logic circuits, 979-980 PTL circuits, 983-984 silicon regions, 954 styles, 954-955
Detectors, buffered precision peak, 1213-1214 Devices and basic circuits, 2-542. See also under individual topics BJTs, 377-542 diodes, 139-234 electronics overviews, 5-62 MOSFETs, 235-377 op amps, 63-138 overviews and summaries, 3 Differential and multistage amplifiers, 81, 687-790 BJT differential pairs, 704-720. 777-780 CMRR, 715-716 common-mode gain, 715-716 common-mode half circuits, 716-717 common-mode input resistances, 717-720 differential half circuits, 714-715 differential voltage gains, 713-714 input differential resistances, 711-713 large-signal operations, 707-709 operations, 704-709 overviews and summaries, 704 problems, 777-780 small-signal operations, 709-720 differential amplifiers, 720-749, 781-786 active loads, 727-740, 782-784 bipolar pairs, 723-726, 733-735 CMRR, 732-733 common mode gain, 732-733 conversions, 727-728 differential gains. 729-780 frequency responses, 740-749, 785-786 input bias, 725-726 input common-mode ranges. 726 input offset voltage, 720-735, 738-739 nonideal characteristics. 720-727, 781-782 offset currents, 725-726 output dc offset voltage, 720-723 problems, 781-786 large-signal transfer characteristics, 768-769 MOS differential pairs, 688-704, 775-776 CMRR, 700-704 common-mode gain, 700-704 common-mode voltage, 689-691 differential gain, 66, 697-700, 729-790 differential half circuits, 700 differential input signals, 692 differential input voltage, 691-693 differential output, 698 input common-mode range, 690 large-signal operations, 693-696 MOSFET effects, 699-700 overviews and summaries, 688-689 problems, 775-776 single ended outputs, 698 small-signal operations. 696-704, 776-777 multistage amplifiers, 749-767, 786-789 bipolar op amps. 758-766 differential in/differential out, 758 overviews and summaries, 749 problems, 786-789 two-stage CMOS op amps, 749-757 overviews and summaries, 81. 6S7-688, 773-775 SPICE simulations, 767-773 Differential gain, 66, 697-700, 729-790 Differential half circuits, 700, 714-715 Differential in/differential out, 758 Differential inputs, 691-693 Differential outputs, 698 Differential pairs, 704-720, 777-780 bipolar pairs, 723-725, 733-735 MOS pairs, 688-704, 775-776 Differential signals, 67-68 Differential voltage gains, 713-714 Differentiators, 105-113, 136-138 op amps, 105-113, 136-138 time-constants, 113 Diffusion, 192-197, 206-208, 486, A3 constants, 193 currents. 193. 208 densities, 208 diffusion capacitances, 206-208, 486 diffusion currents. 197 lengths, 205-206 mechanisms, 192-194
overviews and summaries, A3 small-signal diffusion capacitances, 486 Diffusivity, 193, 208 holes, 193 vs. mobility, 208 Digital and analog ICs (integrated circuits), 543-1008. See also under individual topics CMOS logic circuits, 949-1008 differential and multistage amplifiers, 687-791 feedback, 791-870 op amp and data converter circuits, 871-948 overviews and summaries, 543 single stage IC amplifiers, 545-686 Digital bands, 10-11 Digital logic circuits, 1013-1082 advanced, 1013-1082. See also Memory and advanced digital circuits designs. See Designs, digital logic circuits Digital logic inverters, 503-507, 540-541 BJTs, 503-507, 540-541 TTL (transistor-transistor logic), 505-506 Digital vs. analog signals, 10-13, 922 Diodes, 139-234 class AB output stage biasing, 1244-1246 forward characteristics, 153-167, 223-227 battery-plus-resistance models, 156-157, 166 constant voltage drop models, 157-158, 166 exponential models, 153-155 forward drop, 163-165 graphical analyses, 154-155 ideal diode models. 158-159. 166 overviews and summaries, 153, 165-166 piecewise linear models, 155-157. 166 problems, 223-227 rapid analyses, 155 small-signal models, 159-163, 166 voltage regulation, 163-165 ideal, 140-147, 218-221 anodes, 141 cathodes, 141 current-voltage characteristics, 140-141 diode logic gates, 144-147 forward bias and biasing, 141 problems, 218-221 rectifier circuits, 141-144 reverse bias and biasing, 141 junctions, terminal characteristics, 147-153, 222-223 breakdown regions, 152-153 forward bias and biasing, 148-152 overviews and summaries, 147-148 problems, 222-223 laser diodes, 211 limiting and clamping circuits, 184-190 clamped capacitors (dc restorers). 187-189 clippers, 185 double limiters, 185 hard limiters, 185 limiters, 184-187 overviews and summaries, 184 single limiters, 185 soft limiters, 185 voltage doublers, 187-190 operations, 190-209 overviews and summaries, 190 junctions, 196-209. See also injunctions semiconductors, 190-209. See also Semiconductors overviews and summaries, 139-140, 217-218 problems, 218-234 rectifier circuits, 141-144, 171-184 bridge circuits, 176-177 filter capacitors, 177-183 full-wave circuits, 174-176 half-wave circuits, 172-174 overviews and summaries, 141-144, 171-172 peak circuits, 177-183 superdiodes, 183-184 special types, 209-212 LEDs, 210-211 overviews and summaries, 209 photodiodes, 209-210 SBDs, 212 Schotty TTL diodes, 210 varactors, 209
SPICE simulations, 155, 174, 212-213 overviews and summaries, 212-213 vs. zener diode models, 167-169, 213 superdiodes, 183-184, 1207-1208 zener (breakdown) diodes, 167-171, 187 double anode diodes, 187 models, 167-169 overviews and summaries, 167, 171 shunt regulators, 168-169 TC/tempco, 170-171 Discrete circuits, 5, 436^141 Discrete time signals, 10 Dissipations, power, 46-48, 962-963, 1233-1234, 1250-1251 class A output stage, 1233-1234 dynamic power dissipations, 962-963 instantaneous power dissipations, 1233 overviews and summaries, 45-48, 953-954 static vs. dynamic power dissipations, 46 vs. temperature. 1250-1251 Distortions, 288, 797-798, 1236-1240 crossover distortions, 1236-1240 nonlinear distortions, 288, 797-798 reductions, 797-798 Dividers, 51-52 current, 52 voltage, 51-52 Dominant poles, 91 Domino CMOS (complementary MOS) logic, 996-998 Donors. 195 Doped semiconductors, 194-196 Double anode zener diodes, 187 Double limiters, 185 Doublers, voltage, 187-190 DP (delay power) products, 342-343, 954 Drains, 236, 284-289 drain-to-gate feedback resistors, 284-285 regions, 236 terminals, 288-289 DRAMs (dynamic RAMs), 1031, 1036-1038 Drift, 193-198, 208 carriers, 193 currents, 194, 198, 208 densities, 208 mechanisms, 192-194 velocities, 193-194 Drivers, 1030 Drop, 157-158, 163-166 constant voltage drop models, 157-158, 166 forward, 163-165 Dual slope ADCs, 930-932 Dynamic logic operations, 958-961. 979. 991-998, 1008,1069-1070 BiCMOS. 1069-1070 cascading gates, 995-996 circuits, 991-998, 1008 inverters. 958-961 pseudo-NMOS, 979 Dynamic power dissipations, 46, 962-963 Dynamic resistance, 168
E Early effect augmentations, 457^158 EBJs (emitter-base junctions), 379 ECL (emitter-coupled logic), 1052-1067. 1081-1082 EEPROMs (electrically erasable programmable ROMs), 1051 Einstein relationship, 194 Electrodes, gates, 236-237 Electronics overviews, 5-62 ac circuits, 53-54 amplifiers, 13-31, 55-61 ac amplifiers. 39 amplifier transmission, 32 bandpass amplifiers, 40 bandpath amplifiers, 40 bandwidth, 32-33 bias and biasing, 19-22 BJTs, 29-31 bode plots: 36 break frequencies, 36 buffer amplifiers, 24 cascaded amplifiers, 25-27
center frequencies, 39 circuit models, 23-31 corner frequencies, 36 coupling capacitors, 38 current amplifiers, 28 dc amplifiers, 39 dc bias points, 19 frequency responses, 31-40 grounds, 14 internal capacitances, 38 low-pass amplifiers, 39 magnitude (amplitude response), 32 nonlinear transfer characteristics, 19-22 open-circuit voltage gain, 24 operating points, 19 overviews and summaries, 13-23 phase responses, 32 power amplifiers, 14 power gain, 15-16 power supplies, 16-18 preamplifiers, 14 problems, 55-61 quiescent points, 19 saturation, 18-19 small-signal approximations, 20 STC networks, 33-38 symbols and conventions, 14, 22-23 transconductance amplifiers, 28 transfer characteristics, 14-15 transfer functions, 32 transresistance amplifiers, 28 tuned amplifiers, 40 unilateral models. 28-29 voltage amplifiers, 14, 23-25, 28 circuit analyses, 53 digital logic inverters, 40-49, 61-62 noise margins, 42-43 overviews and summaries, 40^11 PD switches, 44-45 power dissipations, 45^18 problems, 61-62 propagation delays, 45-48 PU switches, 44^15 static vs. dynamic power dissipations, 46 VLSIs. 45-48 VTCs, 41^12 discrete circuits, 5 dividers, 51-52 current, 52 voltage, 51-52 IC chips, 5 microelectronics, 5 microprocessors vs. microcomputers, 5 neflists, 49 Ohm's law, 51 overviews and summaries, 5-6, 50-51 problems. 51-62 resistors, 51 signals, 6-14. 54-55 ADCs, 12 analog vs. digital, 10-13 audio bands, 9 binary number systems. 11 DACs, 12 digital bands, 10-11 digital circuits, 12 digitized signals, 10 discrete-time signals. 10 Fourier series, 7-8 Fourier transform, 7-8 frequency spectrums, 7-10 fundamental frequencies, 8-9 LSBs, 12 MSBs, 12 overviews and summaries, 6-7 problems, 54-55 quantized signals, 10 sampling, 10 signal amplification, 13-14 signal processing, 6 transducers, 6 silicon chips. 5 SPICE simulations, 49-50 Thevenin equivalent circuits, 52 Electrons, free. 191
EM (Ebers-Moll) model, 387-390 Emitters. See also under individual topics base-emitter junction capacitances, 486 BJTs, 379, 410-412 CE amplifiers, 461-475, 582-600 CE circuits, 410^112 currents, 446-447 degeneration, 474, 629-635 EBJs, 379 ECL, 1052-1067, 1081-1082 followers, 478-483, 635-641, 1256-1257 inputs, 446^147, 1256-1257 resistances, 446-447, 474 EOS (edge-of-saturation) points, 419 Epitaxial layers, A7 Epitaxy, A7 EPROMs (erasable programmable ROMs) 1046-1051 Equilibrium, 198, 1185-1186 Equivalences, 450-457, 833-834,1130-1133, B5-B6 Evaluation phases, dynamic logic circuits, 992 Excess gate voltage, 239-240 Excess minority carriers, 205-206 Exclusive OR (XOR) logic functions, 969-970 Extensions, bandwidth, 795-796 Fabrication technology, A1-A14 BiCMOS processes, A9-A10 CVD, A3-A4 diffusion, A3 epitaxial layers, A3 epitaxy, A3 integrated devices, A7 ion implantation, A3-A4 lateral php transistors, A10-A11 layouts, A12-A14 metallization, A4 MOSFETs, A7-A8 B-well CMOS processes, A5-A7 overviews and summaries, Al oxidation, A2-A3 p-base resistors, A i l packaging, A4 photolithography, A4 pinched-base resistors, A l l pn junction diodes, A9 processes, A4-A12 resistors, A8-A9 SiGe BiCMOS processes, Al 1-A12 VSLIs, A1-A14 wafer preparation, A2 Families, logic circuit, 950-952. See also Logic circuit families Fan-ins and fan-outs. 954, 1061-1062 Fate switches. 988-989 Feedback, 791-870 amplifier poles, 836-845, 869-870 characteristics, 838 multiple poles, 843-845 overviews and summaries. 836 pole location, 837-838 problems, 836-845, 869-870 single pole responses, 838-843 collector-to-base feedback resistors, 441^142 drain-to-gate feedback resistors, 284-285 equivalent feedback loops, 1130-1133 feedback loops, 1126-1127, 1166-1167, 1185-1186 frequency compensation, 849-855, 870 implementations, 851-852 Miller compensations, 852-855 overviews and summaries, 849-850 pole splitting, 852-855 problems, 870 theories, 850-851 loop gain determinations, 831-834, 868-869 alternative approaches, 831-833 circuit equivalences, 833-834 loop transmission, 832 overviews and summaries, 831 problems, 868-869 negative (degenerative) feedback properties, 68-69, 795-798. 860-861 bandwidth extensions. 795-796
iN-6
INDEX
Feedback (Continued) gain desensitivity, 795 linearization, 797-798 noise reduction, 796-797 nonlinear distortion reduction, 797-798 overviews and summaries, 68-69, 795 power supply hums, 797 preamplifiers, 797 problems, 860-861 signal-to-noise ratios, 796-797 overviews and summaries, 68-69, 791-792, 859-860 positive (regenerative) feedback, 68-69, 792 positive feedback loops, 1166 problems, 860-870 series-series feedback (voltage mixing-current sampling) amplifiers, 801-802, 811-818, 865-866 overviews and summaries, 815-818 problems, 865-866 structures, 812-814 typologies, 801-802 series-shunt feedback amplifiers, 802-810, 863-865 overviews and summaries, 807-810 problems, 863-865 structures, 802-807 shunt-series feedback (current mixing-current sampling) amplifiers, 799-801, 818-831, 866-867 overviews and summaries, 818-819 problems, 866-867 structures, 823-829 typologies, 799-801 shunt-shunt feedback (current mixing-voltage sampling) amplifiers, 802, 818-831, 866-867 overviews, 818-819 problems, 866-867 structures, 819-823 typologies, 802 SPICE simulations, 855-859 stability, 834-836, 845-849, 869-870 alternative approaches, 847-849 bode plot studies, 845-849 closed-loop transfer functions, 834 closure rates, 849 feedback transfer functions, 834 gain margins, 845-847 Nyquist plots, 835-836 open-loop transfer functions, 834 oscillators, 835 phase margins, 845-847 problems, 869-870 transfer functions. 834-835 structures, 792-795, 860 closed-loop gain, 794 comparison circuits, 794 gain reduction factors (feedback amounts), 792-793 loop gain, 793 problems, 860 signal-flow diagrams, 792-793 typologies, 798-802, 830-831, 861-862 current amplifiers, 799-801 overviews and summaries, 798-799, 830-831 problems, 861-862 transconductance amplifiers, 802-804 transresistance amplifiers, 804 Filters and tuned amplifiers, 177-183, 922, 1083-1164 active RC filters, 1084 algorithms, filtering, 922 Butterworth filters, 1091-1098; 1159-1160 capacitors, 177-183 Chebyshev filters, 1091-1098, 1159-1160 fifth order Chebyshev filters, 1152-1154 filter transfer functions, 1088-1091,1159 all pole filters, 1090 filter orders, 1088 natural modes, 1088 overviews and summaries, 1088-1091 problems, 1159 transfer function poles, 1088 transfer function (transmission) zeros, 1088
INDEX
filter transmissions, types, and specifications, 1084-1088, 1159 attenuation functions, 1084 BP filters, 1085 brick wall responses, 1085 BS filters, 1085 filter specifications, 1085-1087 filter transmissions, 1084-1085 filter types, 1085 HP filters, 1085 passing signals, 1085 problems, 1159 first-order and second-order (biquadratic) filter functions, 1098-1106. 1160-1161 all-pass filters, 1101 bilinear transfer functions, 1098 center frequencies, 1102 first-order filters, 1098-1101 flat gain, 1102 notch frequencies, 1102 overviews and summaries, 1098 pole frequencies, 1102 pole Q (pole quality factors), 1102 problems, 1160-1161 second-order (biquadratic) filter functions, 1101-1106 inductorless filters, 1084 overviews and summaries, 1083-1084, 1158 passive LC filters, 1083-1084 problems, 1159-1163 second-order active filters, 1112-1125, 1161-1162 all-pass circuits, 1118-1120 Antoniou inductance-simulation circuits, 1112-1114 biquads, 1120-1122 circuit implementations, 1122-1123 filter types, 1114-1118 inductor replacements, 1112-1120 KHN biquads, 1122 op amp-RD resonators, 1114 overviews and summaries, 1125 problems, 1161-1162 Tow-Thomas biquads, 1123-1125 two-integrator loop technology, 1120-1125 second-order LCRs, 1108-1112 all-pass functions, 111 1-1112 ' bandwidth functions, 1108-1109 high-pass functions, 1108 low-pass functions, 1108 notch functions, 1110-1111 overviews and summaries, 1106 problems, 1161 resonator natural modes, 1106-1107 transmission zones, 1107-1108 sensitivity, 1133-1136, 1162 classical sensitivity functions, 1133-1134 overviews and summaries, 1135-1136 passive sensitivities, 1134-1135 problems, 1162 single-amplifier biquadratic active filters, 1125-1133, 1162 complementary transformations, 1130 equivalent feedback loops, 1130-1133 feedback loops, 1126-1127 input signal injections, 1128-1130 overviews and summaries, 1125-1126 problems, 1162 SPICE simulations, 1152-1158 switehed-capacitor filters, 1136—1141,1162-1163 overviews and summaries, 1136-1137 practical circuits, 1137-1141 problems, 1162-1163 tuned amplifiers, 1141-1152, 1163 autotransformers, 1144-1145 cascode amplifiers, 1146-1147 CC-CB cascade amplifiers, 1146-1147 inductor losses, 1143-1144 LP-to-BP transformations, 1149-1150 maximal flatness, 1148-1149 multiple tuned circuits, 1145-1146 narrow-band approximations, 1149 neutralizing effects, 1146
overviews and summaries, 1141-1143 problems, 1163 RFCs, 1146 stagger-tuning, 1148-1152 synchronous tuning, 1147-1148 transformers, 1144-1145 Finite open-loop gain, 89-94, 134-135 Finite output resistance saturation, 253-256 First-order and second-order (biquadratic) filter functions, 1098-1106, 1160-1161, E2-E3 Fixed-gain amplifiers, 1261-1265 Fixing, 280-284 Flash (parallel) converters, 932 Rat gain, 1102 Flatness, maximal. 1148-1149 Flip-flops and latches, 1014-1021, 1077-1078 Folded cascade CMOS op amps, 883-893, 941-942 Folded cascodes, 627-628 Followers, 78-79, 315-318, 478^183, 635-641, 1256-1257 emitter followers, 478^183, 635-641, 1256-1257 source followers, 315-318, 635-641 voltage followers, 79-80 Forward base-transit times, 486 Forward bias, 141, 148-152, 204-208 Forward characteristics, 153-167, 223-227 Forward current, 209 Forward drop, 163-165 Fournier series, 7-8 Fournier transform, 7-8 Free electrons, 191 Frequencies. See also under individual topics bands, 326-327 break frequencies, 36 CE frequency responses, 538-540 center frequencies, 39,1102 compensation, 90-91 corner frequencies, 36 cutoff frequencies, 487^190 dependences, 89-91 feedback frequency compensation, 849-855, 870 frequency selective networks, 1166 high frequencies, 487-497, 571-600 hybrid-% models, 487 responses, 492-497, 571-582, 588-600 integrator frequencies, 108 low frequencies, 497-503 notch frequencies, 1102 overviews and summaries, 31-40 pole frequencies. 1102 responses, 91-94. 325-336, 497-600, 740-749, 785-786 CS amplifiers, 326-336. 372-374 differential amplifiers. 740-749, 785-786 high frequencies, 571-582, 588-600 low frequencies, 497-503 overviews and summaries, 91-94 specfrums, 7-10 Full-power bandwidth, 97-98 Full-wave rectifiers, 174-176, 1210-1212
G GaAs (gallium arsenide) circuits. 952 Gain. See also under individual topics 741 op amp circuits, 917-922 BJT amplifiers, 412^114 common-mode gain, 700-704, 715-716 desensitivity, 795 differential gain, 66, 697-700, 713-714, 729-780 fixed-gain amplifiers, 1261-1265 flat gain, 1102 gain reduction factors (feedback amounts), 792-793 GB products, 91-93 high-frequency responses, 572-575 infinite open-loop gain, 66 loop gain, 69-71, 89-94, 134-135, 793-794, 831-834, 868-869 margins, 845-847 open-circuit voltage gain, 24 open-loop gain, 71-72, 89-94, 134-135
overviews and summaries, 14-15 power gain, 15-16 small-signal gain, 917-918 unity gain, 79-80, 91, 315, 488 amplifiers, 79-80,315 bandwidth, 91, 488 voltage gain, 447 Gates. See also under individual topics backgates, 296 BiCMOS gates, 1070-1071 capacitive effects, 321 cascading dynamic logic gates, 995-996 CG amplifiers, 600-613 CMOS logic-gate circuits, 963-973, 1004-1005 complex gates, 967-968 drain-to-gate feedback resistors, 284-285 ECL, 1053-1057. 1071-1076 electrodes, 236-237 excess gate voltage. 239-240 fan-ins and fari-outs, 954 gate-to-source overdrive voltage, 250-251 pseudo-NMOS logic circuits, 980 two-input NAND gates, 966-967 two-input NOR gates, 966 GB (gain bandwidth) products, 91-93 Generators, signals, 1165-1228. See also Signal generators and waveform shaping circuits Graphical analyses, 154-155, 415^-19 BJTs, 415^119 forward characteristics, diodes, 154-155 Grounds, 14, 69-70, 271-272, 306, 316-318 ac grounds, 306 circuit grounds, 14 grounded drain amplifiers, 315-318 grounded source circuits, 271-272 single grounds, 306 virtual grounds, 69-70 Gummel-Poom model, 509-510 ;
H H parameters, B4-B5 Half circuits, 700-717 common-mode half-circuits, 716-717 differential half circuits, 700, 714-715 Half-wave rectifiers, 172-174, 1207-1208 Hard limiters, 185 Hartley oscillators, 1179-1180 Heat sinks, 1251-1254 High frequencies, 320-326, 372. 485^197. 571-600 bands, 326 BJTs, 485^191 hybrid-% models. 487 models, 320-326, 372. 485^191 responses, 492-497, 571-582, 588-600 single-stage IC amplifiers, 571-582, 588-600 Holes, 191-205 concentration profiles, 193 injected holes, 204-205 positively charged carriers, 191 HP (high pass), 1085, 1108, D6-D18 circuits, D6-D18 filters, 1085 functions, 1108 Hums, power-supplies, 797 Hybrid-jr models, 296, 298, 448-449, 487
Impedances. 65-66, 105-107 input impedances, 65-66 inverted configurations, 105-107 output impedances, 65-66 Implantation, ions, A3-A4 Incremental resistances, 161-162, 168 Inductors, 1084. 1112-1120, 1143-1144 inductance simulation circuits, 1112-1114 inductorless filters, 1084 losses, 1143-1144 replacements, 1112-1120 Infinite bandwidth, 66 Infinite open-loop gain. 66 Injections, 204-205, 1128-1130 holes, 204-205 input signals, 1128-1130 Inputs. See also under individual topics bias and biasing. See also Bias and biasing currents, 102-105 differential amplifiers, 725-726 input state bias, 899-901 inverted input terminals, 65 offset currents, 102-105 offset voltage, 98, 720-735, 738-739 common-mode ranges, 726, 902 emitter followers, 1256-1257 impedances, 65-66 resistances, 72-75 bases, 445—146 common modes, 717-720 emitters, 446^147 signals, 691-693, 1128-1130 differential, 691-693 injections. 1128-1130 voltage. 691-693 Instantaneous operating points, 278 Instantaneous power dissipations, 1233 Instrumentation amplifiers, 85-89 Integrators. See also under individual topics frequencies, 108 inverted integrators, 105-112 Miller integrators, 107-112 op amp integrators, 105-113, 136-138 time constant integrators, 107 VLSI integrators, A2 Internal capacitances, 38, 320-325, 372 Internally compensated op amps (operational amplifiers), 91 Intervals, conduction, 180 Intrinsic silicon. 190-192, 208 Inverse active (reverse active) modes, 379 Inversion layers, 238 Inverters. See also under individual topics BiCMOS inverters, 1067-1069 BJT inverters. 503-507, 540-541 CMOS inverters, 336-346, 374-375, 955-953 1003-1004 digital logic inverters, 40-49, 61-62, 503-507, 540-541 input terminal inverters, 65 integrator inverters, 105-112 op-amp inverters, 68-77, 124-128 overviews and summaries, 105-107 Ion implantation, A3-A4 Ionization, thermal, 192
I ICs (integrated circuits), analog and digital, 543-1008. See also under individual topics chips, 4 CMOS logic circuits, 949-1008 differential and multistage amplifiers, 687-791 feedback, 791-870 op-amp and data-converter circuits, 871-948 overviews and summaries, 543 power amplifiers, 1261-1266, 1281-1282 single-stage IC amplifiers, 545-686 timers, 1198-1208 Ideal diodes, 140-147,158-159, 166, 218-221 Ideal op amps (operational amplifiers), 63-68, 123-124 IGFET (insulated gate FET). See MOSFETs (metal oxide semiconductor field effect transistors)
Junctions. See also under individual topics base emitter junction capacitances, 486 BJTs, 377-542. See also BJTs (bipolar junction transistors) built-in voltage, 209 capacitances, 322 CBJs, 379 collector base junction capacitances, 487 depletion (junction) capacitances, 200-203 206-208, 322 EBJs, 379 laws, 205 injunctions. See injunctions temperatures, 1229-1230, 1249 terminal characteristics. 147-153, 222-223
IN-7
K KHN (Kirwin-Huelsman-Newcomb) biquads 1 P 2 Knee current, 167-168
L Ladders, R-2R, 926-928 Large circuit-equivalent circuit models 251 Large signal operations, 94-98, 135 693-69fi 707-709, 768-769 differential transfer characteristics, 768-769 MOS differential pairs, 693-696 op amps, 94-98, 135 overviews and summaries, 707-709 Laser diodes, 211 Latches and flip-flops, 1014-1021, 1077-1078 Lateral pnp transistors, A10-A11 Layers, 238, A3 epitaxial, A3 inversion, 238 Layouts, A12-A14 LC (liquid crystal) and crystal oscillators, 1177-1185,1222-1223 LC (liquid crystal) filters, 1083-1084 LCRs (liquid crystal resonators), 1108-1112 Leakage effects, 994 LEDs (light emitting diodes), 210-211 Limits and limiters, 94-95, 184-190 1169-1180,1255 limiter circuits, 1169-1171 limiting and clamping circuits, 184-190 output currents, 94-95 second breakdown limits, 1255 self-limiting oscillators, 1180 Line regulations, 169 Linear amplifiers, 274-275 Linear macromodels, 115-119 Linear oscillators, 1120, 1166-1171 Linearization, 797-798 Loads, 154, 169, 273 lines, 154, 273 regulations, 169 resistors, 273 LOCOS (local oxidation), A7 Logic circuit families, 950-952. See also under individual topics BiCMOS circuits, 952 bipolar circuits, 951-952 ECL circuits, 951-952 TTL circuits, 951-952 CMOS circuits, 950-951 GaAs circuits, 952 NMOS circuits, 950-951 overviews and summaries, 950 pseudo-NMOS circuits, 950-951 Logic functions, 145, 969-970 AND, 145 NAND, 966-967 NOR, 966 OR, 145 XOR, 969-970 Logic gates. See Gates Loops and looping. See also under individual topics closed loops, 69-71, 91-94, 834 amplifiers, 91-94 gain, 69-71 transfer functions, 834 feedback loops, 1126-1133, 1166-1167 1185-1186 equivalents, 1130-1133 overviews and summaries, 1126-1127, 1166-1167, 1185-1186 positive, 1166 gain, 89-94, 134-135, 793, 831-834, 868-869 open loops, 71-74, 89-94, 134-135, 834 finite open-loop gain, 89-94, 134-135 gain, 71-72 infinite open-loop gain, 66 transfer functions, 834 transmissions, 832 two-integrator-loop technologies, 1120-1125 Losses, inductor, 1143-1144
IN-8
INDEX
Low frequencies, 326, 497-503 bands, 326 responses, 497-503 LP (low pass), 39. 1108, 1149-1150, D6-D8 amplifiers, 39 circuits, D6-D8 functions, 1108 LP-to-BP transformations, 1149-1150 LSBs (least significant bits), 12, 925-926
M Macromodels, 115-122 linear macromodels, 115-119 nonlinear macromodels, 119-122 Magnitude (amplitude response), 32 Main memory, 1028 Margins, noise, 42-43, 952-953, 993-994 Mask programmable ROMs, 1049 Maximal flatness, 1148-1149 Mean transit times, 207 Memory and advanced digital circuits, 1013-1082 BiCMOS circuits, 1067-1076, 1082 dynamic operations, 1069-1070 inverters, 1067-1069 logic gates, 1070-1071 overviews and summaries, 1067 problems, 1082 combinational vs. sequential circuits, 1013-1014 ECL, 1052-1067, 1081-1082 families, 1053 fan-outs, 1061-1062 gate circuits, 1053-1057,1071-1076 operation speeds, 1062-1063 overviews and summaries, 1052-1053, 1066-1067 power dissipation, 1062 problems, 1052-1067, 1081-1082 ringing, 1062 signal transmission, 1062-1063 thermal effects, 1062-1066 VTCs, 1057-1061 wired OR capabilities. 1066 latches and flip-flops, 1014-1021, 1077-1078 clocked SR flip-flops, 1019-1021 CMOS implementations, 1016-1021 latches, 1014-1016 overviews and summaries. 1014 problems, 1077-1078 SR flip-flops, 1016-1021 memory elements, 1188 multivibrator circuits, 1021-1028, 1078 astable circuits, 1022, 1026-1027 CMOS monostable circuits, 1022-1026 monostable multivibrators, 1021-1023 overviews and summaries, 1021 problems, 1078 quasi-stable multivibrators, 1021-1022 ring oscillators, 1027 overviews and summaries, 1013-1014, 1076-1077 problems, 1077-1082 RAMs, 1028, 1031-1038, 1079 DRAMs, 1031, 1036-1038 overviews and summaries, 1031 problems, 1079 S RAMs, 1031-1036 ROMs, 1028, 1046-1052,1080 EEPROMs, 1051 EPROMs, 1046-1051 mask programmable ROMs, 1049 MOS ROMs, 1047-1048 overviews and summaries, 1046-1047 problems, 1080 PROMs, 1046-1051 sense amplifier and address decoders, 1038-1046. 1080 column address decoder, 1045-1046 overviews and summaries, 1038 problems, 1080 row address decoders, 1043-1045 sense amplifiers, 1038-1043 SPICE simulations, 1071-1076
INDEX
types and architectures, 1028-1031, 1078-1079 bit lines, 1029 column decoders. 1030 digit lines, 1029 drivers, 1030 main memory, 1028 mass storage memory, 1028 memory access times, 1030 memory cells, 1029 memory chip organization, 1028-1030 memory chip timing, 1030 memory cycle times, 1030 memory elements, 1181 overviews and summaries, 1028 problems, 1078-1079 row decoders, 1029-1030 selection processes, 1029 word lines, 1029 Metallization, A4 Metastable states (unequal equinbrium), 1185-1186 Microcomputers vs. microprocessors, 5 Microelectronics, 5 Midbands, 326 Miller compensations, 852-855 Miller effects, 496, 581 Miller integrators, 107-112 Miller multipliers, 496, 581 Miller's theorem, 578-582, 589-590 Minority carriers, 209 Mirrors, 649-656, 892-893 bipolar mirrors, 650-651 cascode MOS"mirrors, 649-653 current mirrors, 563-565, 649-656 wide-swing current mirrors, 892-893 Wilson mirrors, 651-653 current mirrors, 651-652 MOS mirrors, 652-653 Mobility, 194, 208 Models. See also under individual topics battery-plus-resistance models, 156-157, 166 BJT models, 443-460 body effect models, 296-297 circuit models, 23-31 constant-voltage-drop models, 157-158, 166 EM models, 387-390 equivalent circuit models, 295-296 * exponential models, 153-155 Gummel-Poom models, 509-510 high-frequency models, 320-326, 372,485-491 hybrid-!!: models, 296-298, 448-449, 487 ideal-diode models, 158-159, 166 large circuit-equivalent circuit models, 251 linear models, 115-119, 155-157, 166 macromodels, 115-119 piecewise, 155-157,166 macromodels, 115-122 linear macromodels, 115-119 nonlinear macromodels, 119-122 MOSFET models, 287-299, 998-1001 nonlinear macromodels, 119-122 piecewise linear models, 155-157, 166 single pole models, 91 small-signal models, 159-163, 166 SPICE simulations. See SPICE (Simulation Program with Integrated Circuit Emphasis) simulations square law models, 351 T models, 295-296, 449^150 unilateral models, 28-29 zener diode models, 167-169, 213 Modulations, channel lengths, 253 Monostable CMOS (complementary MOS) circuits. 1022-1026 Monostable multivibrators, 1196-1198, 1225 MOS (metal oxide semiconductors). See also under individual topics cascode. 549-650 CMOS logic circuits. See CMOS (complementary MOS) logic circuits differential pairs, 688-704, 775-776 mirrors, 649-650 MOSFETs, 235-376. See also MOSFETs (metal oxide semiconductor field effect transistors) power transistors, 1266-1271, 1282-1283 ROMs, 1047-1048
MOSFETs (metal oxide semiconductor field effect transistors), 235-376 bias and biasing, 280-287, 367-368 constant-current sources, 285-286 degeneration resistance, 281 drain-to-gate feedback resistors, 284-285 negative feedback, 281 overviews and summaries, 287 problems, 367-368 source resistance connections, 281-284 V fixing, 281-284 V fixing. 280-281 class AB output staae. 1270-1271 CMOS digital logic inverters, 336-346, 374-375 circuit operations, 337-339 DP products, 342-343 dynamic operations, 342-345 overviews and summaries, 336-337, 346 problems, 374-375 propagation delays, 342 VTCs, 339-342 CS amplifier frequency responses, 326-336, 372-374 3-dB bandwidth, 326-327 bandwidth, 326-327 CMOS digital logic inverters, 336-337 frequency bands, 326-327 gain bandwidth products. 327 high-frequency bands, 326 high-frequency responses, 328-332 low-frequency bands, 326 low-frequency responses. 332-336 midbands, 326 overviews and summaries, 326. 336 problems, 372-374 current voltage characteristics. 24S-262, 360-362 body effect parameters, 259 breakdowns, 259-260 channel length modulations, 253 cutoff regions, 248 finite output resistance saturation, 253-256 gate-to-source overdrive voltage, 250-251 input protections, 259-260 large circuit-equivalent circuit models, 251 n channels, 248-249 overviews and summaries, 248, 260-262 p channels, 256-258 problems, 360-362 punch through, 260 saturation regions, 248 substrate body effects, 258-259 symbols and conventions, 248-249 temperature effects, 259 triode regions, 248 weak avalanches, 260 dc circuits, 262-270, 362-366 depletion type MOSFETs, 346-351, 375 modes, 346 overviews and summaries, 346-351 problems, 346-351, 375 fabrication technologies, Al 1-A12 internal capacitances, 320-325, 372 gate capacitive effects, 321 high-frequency models, 322-324, 372 junction capacitances, 322 overlap capacitances, 321 overviews and summaries, 320-321 problems, 320-325, 372 unity gain frequencies, 324-325 models, 287-299, 998-1001 operations, 236, 238-248, 360 channels, 238 CMOS logic circuits, 247-248. See also CMOS (complementary MOS) logic circuits current flow channel creation, 238-239 effective (overdrive) voltage, 240 enhancement mode operations, 240 enhancement types, 240 excess gate voltage, 239-240 inversion layers, 238 n channels, 238 NMOS transistors, 238-243, 247-248 overviews, 236 G
as
pinched-off channels, 242 PMOS transistors, 247-248 problems, 236, 238-248, 360 process transconductance parameters, 245 saturation regions, 242 ""'' subthreshold regions, 248 threshold voltage, 239 triode regions, 242 overviews and summaries, 235-236, 359-360 375-376 power amplifiers, 1266-1270 problems, 360-376 . single stage MOS amplifiers, 299-320, 370-372 ac grounds, 306 bypass capacitors, 306 cascode currents, 315 CG (grounded gate) amplifiers, 311-315 characteristics, 301-306 common-drain (grounded drain) amplifiers, 315-318 coupling capacitors, 306 CS amplifiers, 306-311 current followers, 315 feedback amounts, 311 nonunilaterai amplifiers, 301 overviews and summaries, 299, 318-320 problems, 370-372 single grounds, 306 source degenerations, 311 source follower amplifiers, 315-318 source resistances, 309-311 structures, 299-301 termination resistance, 315 transmission lines, 315 unilateral amplifiers, 301 unity-gain current amplifiers. 315 small-signal operations, 287-299, 368-370 backgates, 296 body effect models, 296-297 body transconductance, 296-297 conditions, 288 dc analyses-signal analyses separations, 290 ' dc bias points, 287 drain terminals, 288-289 \ hybrid-K models, 296, 298 nonlinear distortion, 288 overviews and summaries, 287, 297-299 problems, 368-370 small-signal equivalent-circuit models, 290-292 T equivalent circuit models, 295-296 transconductances, 288. 292-297 voltage gains, 289-290' SPICE simulations, 351-359 square law models, 351 structures, 236-238, 360 bodies, 236-237 drain regions, 236 gate electrodes, 236-237 overviews, 236-238 injunctions, 238 problems, 360 sources, 236 switches, 270-280, 366-367 CS circuits, 271-272 dc biasing, 271 grounded source circuits, 271-272 instantaneous operating points. 278 large signal operations, 271-273 linear amplifiers, 274-275 load lines, 273 load resistors, 273 overviews and summaries, 270-271 problems, 366-367 quiescent points, 274-275 switch operations, 274-275 transconductance amplifiers, 271 transfer characteristics, 271-279 VTCs, 272-273 VLSIs, A7-A8 MSBs (most significant bits), 12, 925-926 Multiple amplifier poles, 843-845 Multiple tuned circuits, 1145-1146 Multipliers, 496, 581, 1246-1249 Miller multipliers, 496, 581 V multipliers biasing, 1246-1249 BE
Multistage amplifiers, 749-789 bipolar op amps, 758-766 differential in/differential out, 758 overviews and summaries, 749 problems, 786-789 two-stage CMOS op amps, 749-757 Multivibrators, 1021-1029,1087,1185-1196 1223-1224 astable multivibrators, 1192-1196 bistable multivibrators, 1185-1192,1223-1224 monostable multivibrators, 1196-1198,1225 overviews and summaries, 1021-1028, 1078 problems, 1078 quasi-stable multivibrators, 1021-1022
N ^-channel MOSFETs, 238, 248-249 B-type doped semiconductors, 194-195 fi-type silicon, 208 n-well CMOS processes, A5-A7 NAND (not AND) gates, two-input, 966-967 Narrow band approximations, 1149 Natural devices, PTL circuits, 988 Natural modes, 1088, 1106-1107, E2 Negative (degenerative) feedback properties, 68-69, 795-798, 860-861 Netlists, 49 Networks, 963-969, 1166, C1-C5, E2 frequency selective networks, 1166 order of the network, E2 PDNs, 963-966, 968-969 PUNs, 963-966, 968-969 theorems, C1-C6. See also Theorems Norton's theorem, C1-C3 overviews and summaries, CI problems, C5-C6 source-absorption theorem, C3-C5 Thévenin's theorem, C1-C2 Neutralizing effects, tuned amplifiers, 1146 NMOS logic circuits, 238-248, 950-951, 963-966 overviews and summaries of, 950-951 pseudo-NMOS logic circuits. See Pseudo-NMOS logic circuits PTL circuits, 984-988 transistors, 238-248, 963-988 overviews and summaries, 238-243, 247-248 pull-down transistors, 963-966 transistor switches, 984-988 Noise, 42^13, 796-797, 952-953, 993-994 margins, 42-43, 952-953, 993-994 reductions, 796-797 signal-to-noise ratios, 796-797 Nonideal characteristics and effects, 720-727 781-782, 993-996 Noninverted characteristics, 77-79, 129-133 1188-1189 Nonlinear amplification methods, 1205-1206 Nonlinear amplitude controls, 1168-1169 Nonlinear distortions, 288, 797-798 Nonlinear macromodels, 119-122 Nonlinear transfer characteristics, 19-22 Nonlinear waveform-shaping circuits, 1203-1206, 1225-1227 Nonunilaterai amplifiers, 301, 461 NOR (not OR) gates, two-input, 966 Norton's theorem, C1-C3 Notch frequencies, 1102, 1110-1111 npn transistors, 392 Number systems, binary, 11 Nyquist plots, 835-836 Offsets, 98, 102-105, 720-739 currents, 725-726 input offset currents, 102-105 input offset voltage, 98, 720-735, 738-739 Ohmic contacts, 210 Ohm's law, 51 Op amp (operational amplifier) and data converter circuits, 871-947. See also Op amps (operational amplifiers) 741 circuits, 893-899, 905-922, 942-946 bias circuits, 893-895 dc analyses, 893-899
. ,
!
||\J-9
dc collector currents, 904 device parameters, 898 frequency responses, 917-922 gain, 917-922 input bias currents, 902 input common-mode ranges, 902 input offset voltage, 902 input stages, 895, 899-901 input state bias, 899-901 negative feedback loops, 901 offset currents, 902 output stage bias, 903-904 output stages, 896-897, 903-904 overviews and summaries, 893 problems, 893-899, 942-946 reference bias currents, 899 second stage bias, 902-903 second stages, 895-896, 902-903 short circuit protections, 895 slew rates, 917-922 small-signal analyses, 905-917 small-signal gain, 917-918 data converter circuits, 922-929 946-947 ADCs, 929-934 analog signal sampling, 922-923 charge-redistribution converters 932-934 DACs, 925-929 digital signal processing, 922 dual-slope converters, 930-932 filtering algorithms, 922 LSBs, 925-926 MSBs, 925-926 overviews and summaries, 922-925 parallel (flash) converters, 932 problems, 922-929. 946-947 R-2R ladders. 926-928 S/H circuits, 923 signal quantization, 924 switches, 928-929 folded cascade CMOS op amps, 883-893 941-942 circuits, 883-885 input common-mode range, 885-886, 890-893 output voltage swings, 885-886 overviews and summaries, 883 problems, 883-893, 941-942 rail-to-rail operations, 890-892 slew rates, 888-890 voltage gain, 886-888 wide-swing current mirrors, 892-893 overviews and summaries, 871-872, 940-941 problems, 941-947 SPICE simulations, 934-940 two-stage CMOS op amps, 872-883, 941 circuits, 872-873 frequency responses, 876-877 input common mode ranges, 873-874 output swing, 873-874 overviews and summaries, 872 problems, 941 slew rates, 879-883 voltage gain, 874-876 Op amps (operational amplifiers), 63-138 bandwidth effects, 89-94, 134-135 bipolar, 758-766 circuits (op amps and data converters), 871-947. See also Op amp (operational amplifier) and data converter circuits dc imperfections. 98-105, 135-136 input bias currents, 102-105 input offset currents, 102-105 input offset voltage, 98 offset voltage, 98-102 problems, 135-136 finite open loop gain effects, 89-94, 134-135 closed-loop amplifiers, 91-94 dominant poles, 91 frequency compensations, 90-91 frequency dependences, 89-91 frequency responses, 91-94 GB products, 91-93 internally-compensated op amps, 91 overviews and summaries, 89 problems, 134-135 single-pole models, 91 unity-gain bandwidth, 91
IN-10
INDEX
Op amps (operational amplifiers) (Continued) ideal, 63-68, 123-124 characteristics, 66 common-mode rejections, 65 common-mode signals, 67-68 dc amplifiers, 66 differential gain, 66 differential input single ended output amplifiers, 65-66 differential signals, 67-68 infinite bandwidth, 66 infinite open loop gain, 66 input impedances, 65-66 inverted input terminals, 65 output impedances, 65-66 problems, 123-124 integrators and differentiators, 105-113, 136-138 differentiators, 112-114 frequencies, 108 impedances, 105-107 inverted integrators, 105-112 Miller integrators, 107-112 overviews and summaries, 105 problems, 136-138 time constants, 107, 113 inverted configurations, 68-77, 124—128 closed-loop gain, 69-71 negative feedback, 68-69 open-loop gain, 71-72 overviews and summaries, 68-69 positive feedback, 68-69 problems, 124-128 resistances, input vs. output, 72-75 virtual grounds, 69-70 virtual short circuits, 69 weighted summer circuits, 75-77 large signal operations, 94-98, 135 full power bandwidth, 97-98 output current limits, 94-95 output voltage saturations, 94 overviews and summaries, 94 problems, 135 rated output voltage, 94 SRs, 95-97 noninverted configurations, 77-89, 129-133 characteristics, 78 closed-loop gain, 77-78 CMRR, 81-82 degenerative feedback, 78 difference amplifiers, 81-89, 131-133 differential amplifiers, 81 differential input resistance, 84-85 instrumentation amplifiers, 85-89 open-loop gain, 78-79 overviews and summaries, 77 problems, 129-133 single difference amplifiers, 81-86 unity gain amplifiers, 79-80 voltage followers, 79-80 op amp-RC oscillator circuits, 1171-1179, 1220-1222 op amp-RD resonators, 1114 overviews and summaries, 63-64, 122-123 problems, 123-138 SPICE simulations, 114-122 linear macromodels, 115-119 macromodels, 114-122 nonlinear macromodels, 119-122 overviews, 114-115 two-stage CMOS op amps, 749-757 Open circuits, 24,196-199, 575-578 Open loops, 71-72, 89-94,134-135; 834 gain, 71-72, 89-94,134-135 transfer functions, 834 Operations. See also under individual topics BiCMOS operations, 1069-1070 BJTs operations, 378-392, 443^160, 517-518, 530-533 class B output stage operations, 1236 diode operations, 190-209 inverter operations, 956-961 large-signal operations, 707-709 MOSFET operations, 236, 238-248, 360
INDEX
operating points, 154 pseudo-NMOS operations, 979 push pull operations, 1236 rail-to-rail operations, 890-892 single supply operations, 1240-1241 small-signal operations, 443-460, 530-533 Optoelectronics, 210 Optoisolators, 211 OR logic functions, 145 Order of the network, E2 Oscillators, 835 active filter tuned oscillators, 1177-1179, 1217-1219 Colpitts oscillators, 1179-1180 Hartley oscillators, 1179-1180 LC and crystal oscillators, 1177-1185, 1222-1223 linear oscillators, 1120,1166-1171 op amp-RC oscillator circuits, 1171-1179, 1220-1222 oscillation criterion, 1167-1168 phase shift oscillator, 1174-1175 quadrature oscillators, 1175-1177 ring oscillators, 1027 self-limiting oscillators, 1180 sinusoidal oscillators, 1120, 1166-1171 sustained oscillations, 1168 Wien-bridge oscillators, 1171-1174, 1215-1217 Output stages and power amplifiers, 1229-1283 class A output stage, 1231-1235,1277-1278 instantaneous-power dissipations, 1233 overviews and summaries, 1231 power conversion efficiencies, 1235 power dissipations, 1233-1234 problems, 1277-1278 signal waveforms, 1233 transfer characteristics, 1231-1233 class AB output stage, 1241-1249, 1256-1261, 1270-1271,1278-1281 circuit biasing, 1244-1249 circuit operations, 1242-1243 compound devices, 1257-1259 configuration variations, 1256-1261 diode biasing, 1244-1246 input emitter followers, 1256-1257 MOSFETs, 1270-1271 output resistance, 1243-1244 overviews and summaries, 1241-1242 problems, 1278-1281 short circuit protections, 1259-1260 thermal shutdowns, 1260 V multipliers biasing, 1246-1249 class B output stage, 1235-1241,1278 circuit operations, 1236 crossover distortions, 1236, 1240 dead bands, 1236 overviews and summaries, 1235-1236 power conversion efficiencies, 1236-1238 power dissipations, 1238-1240 problems, 1235-1241, 1278 push pull operations, 1236 single supply operations, 1240-1241 transfer characteristics, 1236 classifications, 1230-1231 dc offset voltage, 720-723 IC power amplifiers, 1261-1266,1281-1282 bridge amplifiers, 1265-1266 fixed gain amplifiers, 1261-1265 overviews and summaries, 1261 power op amps, 1265 problems, 1281-1282 junction temperatures, 1229-1230 MOS power transistors, 1266-1271, 1282-1283 overviews, 1266 problems, 1282-1283 overviews and summaries, 1229-1230, 1276-1277 power BJTs, 1249-1256, 1279-1280 heat sinks, 1251-1254 junction temperatures, 1249 overviews and summaries, 1249 power dissipations vs. temperatures, 1250-1251 BE
power transistor parameter values, 1255 problems, 1279-1280 second breakdown limits, 1255 SOAs, 1254-1255 thermal resistances, 1249-1250 transistor cases, 1251-1254 power MOSFETs, 1266-1270 vs. BJTs, 1269-1270 characteristics, 1268-1269 structures, 1266-1267 temperature effects, 1269 problems, 1277-1283 SPICE simulations, 1271-1276 THD, 1229-1230 voltage decays, 994 Overdrive factors, 250-251, 403 Overlap capacitances, 321 Overviews and summaries 741 op amp circuits, 893 amplifiers, 13-23 bias and biasing, 19-22, 436 BiCMOS digital circuits, 952, 1067 bistable multivibrators, 1185 BJT amplifiers and switches, 407^110 BJT differential pairs, 704 BJT structures and operations, 378-380 BJTs, 377-378 breakdown regions, 203-204 cascode amplifiers, 613-614 CC amplifiers, 478^-83 class A output stage, 1231 class AB output stage, 1241-1242 class B output stage, 1235-1236 CMOS digital logic inverters, 336-337, 346 current-mirror circuits, 649 current-voltage characteristics, 248, 260-262,407 data converter circuits, 871-872, 922-925, 940-941 differential and multistage amplifiers, 687-688, 773-775 digital logic inverters, 40-41, 503-504 diode operations, 190 diodes, 139-140, 217-218 dynamic logic circuits, 991-992, 998 ECL, 1052-1053, 1066-1067 electronics, 5-6, 50-51 fabrication technology, Al feedback, 791-792, 859-860 filter transfer functions, 1088-1091 filters and tuned amplifiers, 1083-1084, 1158 finite open-loop gain effects, 89 first-order and second-order (biquadratic) filter functions, 1098 folded cascade CMOS op amps, 883 forward-bias conditions, 204-206 forward characteristics, 153, 165-166 frequency compensation, 849-850 high-frequency responses, 571-572 integrators and differentiators, 105 internal capacitances, 320-321, 485^186 inverted op amps, 68-69 inverters, 955 large signal operations, 94 latches and flip-flops, 1014 limiting and clamping circuits, 184 logic-circuit families, 950 logic-gate circuits, 963 loop gain determinations, 831 memory and advanced digital circuits, 1013-1014, 1076-1077 monostable multivibrators, 1196-1198 MOS differential pairs, 688-689 MOS power transistors, 1266 multistage amplifiers, 749 negative (degenerative) feedback properties, 795 network theorems, CI nonlinear waveform shaping circuits, 1203 op amp-RC oscillator circuits, 1171 op amps, 63-64, 122-123, 871-872, 940-941 open circuit conditions, 196-197, 208-209 injunctions, 190 poles, 836 power amplifiers, 1261 power BJTs, 1249
precision rectifier circuits, 1206-1207 precision rectifiers, 1206-1214, 1227-1228 pseudo-NMOS logic circuits, 974, 980-982 PTL circuits, 982-983, 991 ^ RAM memory cells, 1031 rectifier circuits, 141-144, 171-172 reverse bias conditions, 199-200 ROMs, 1046-1047 .S domain analyses, E1-E2 second order active filters, 1125 second order LCRs, 1106 .'. semiconductors, 192 sensitivity, 1135-1136 series-series feedback amplifiers, 815-818 series-shunt feedback amplifiers, 807-810 shunt-series feedback amplifiers, 818-819 shunt-shunt feedback amplifiers, 818-819 signal generators and waveform shaping circuits, 1165-1166, 1219-1220 signals, 6-7 single-amplifier biquadratic active filters, 1125-1126 single-Mage amplifiers, 460, 483-485 single-stage IC amplifiers, 545-546, 665-666 single-stage MOS amplifiers, 299, 318-320 sinusoidal oscillators, 1166 small-signal operations, 443, 458-459 special type diodes, 209 square and triangular waveforms, 1192 standardized pulse generation, 1196 STC circuits, Dl switched capacitor filters, 1136-1137 switches, 270-271 terminal junction characteristics, 147-148 theorems, CI timers, 1198 toned amplifiers, 1141-1143 two-port network parameters, B1-B2 two-stage CMOS op amps, 872 VLSIs, Al zener (breakdown) diodes, 167, 171 Oxidation, A2-A3, A7
1 i-base resistors, A l l p-channels, 247-248, 256-258 i-type silicon, 209 p- vs. «-type doped semiconductors, 194-195 Packaging, fabrication technologies, A4 Pairs. See also under individual topics bipolar pairs, 725-726 conjugate pairs, E2 differential pairs, 688-720, 775-780 MOS differential pairs, 688-704, 775-776 transistors, 641-649 Panel tuned (tank) circuits, 1179-1180 Parallel (flash) converters, 932 Parameters. See also under individual topics body effect parameters, 259 power transistor parameters, 1255 process transconductance parameters, 245 two-port network parameters, B1-B7 y parameters, B2-B3 z parameters, B3-B4 Passing signals, 1085 Passive LC (liquid crystal) filters, 1083-1084 Passive sensitivities, 1134-1135 PD (pull down) switches, 44^-5 PDNs (pull down networks), 973-974 Peak detectors, 182,1213-1214 Peak rectifier circuits, 177-183 Phases, 32, 845-847, 992, 1174-1175 evaluations, 992 margins, 845-847 phase shift oscillators, 1174-1175 précharge phases, 992 responses, 32 Photocurrents, 210-211 Photolithography, A4 Photonics, 210 Piecewise linear models, 141, 155-157, 166 Pinched base resistors, A l l PIV (peak inverse voltage), 173-174
PMOS transistors (p channel enhancement type MOSFETs), 247-248, 963-966 injunctions, 196-209 BJTs, 379 breakdown regions, 203-204 avalanche effects, 203 overviews and summaries, 203-204 diodes, A9 fabrication technology, A9 VLSIs, A9 forward bias conditions, 204-208 current-voltage relationships, 205-206 diffusion capacitances, 206-208 junction capacitances, 206-208 overviews and summaries, 204-206 open circuit conditions, 196-199 barriers, 198 built-in voltage, 198-199 carrier depletion regions (space charge regions), 197-199 diffusion currents, 197 drift currents, 198 equilibrium, 198 overviews and summaries, 196-197, 208-209 uncovered charges, 197 overviews and summaries, 190 reverse-bias conditions, 199-203 depletion (junction) capacitances, 200-203 overviews and summaries, 199-200 semiconductors, 190-199 pnp transistors, 391-392, A10-A11 Points, 19, 162, 419 dc bias points, 19 EOS points, 419 operating points, 19 quiescent points, 19, 162 Poles. See also under individual topics all pole filters, 1090 amplifiers, 836-845, 869-870 dominant poles, 91 frequencies, 1102 overviews and summaries, E2 pole Q (pole quality factors), 1102 single pole models, 91 splitting, 852-855 transfer function poles, 1088 Positive (regenerative) feedback, 68-69, 792, 1166 Power. See also under individual topics dissipations, 45-48, 962-963, 1233-1251 class A output stage, 1233-1234 dynamic dissipations, 46 962-963 instantaneous power dissipations, 1233 overviews and summaries, 45-48, 953-954 power conversion efficiency, 1235-1238 static dissipations, 46 vs. temperature, 1250-1251 DP products, 342-343, 954 gain, 15-16 MOS power transistors, 1266-1271, 1282-1283 power amplifiers, 14, 1249-1282 BJT amplifiers, 1249-1256, 1279-1280 IC amplifiers, 1261-1266, 1281-1282 MOSFET amplifiers, 1266-1270 overviews and summaries, 14 power supplies, 16-18, 162, 797 hums, 797 overviews and summaries, 16-18, 162, 797 ripples, 162 power transformers, 171-172 Preamplifiers, 14, 797 Precharge phases, 992 Precision circuits, 183-184, 1214 clamping circuits, 1214 half-wave circuits, 183-184 Precision peak detectors, 1213-1214 Precision rectifiers, 1206-1214, 1227-1228 bridge rectifiers, 1212-1213 full-wave rectifiers, 1210-1212 half wave, 1207-1208 overviews and summaries, 1206-1214, 1227-1228 Prefixes, unit, G1-G2
'
. .!
IN-1 1
Primary windings, 171-172 Problems. See also under individual topics 741 op amp circuits, 893-899 942-946 amplifier poles, 836-845, 869-870 amplifiers, 55-61 answers (selected), H1-H8 bias and biasing, 528-530 BiCMOS digital circuits, 1082 bistable multivibrators, 1223-1224 BJT amplifiers and switches, 521-524 BJT differential pairs, 777-780 BJT structures and operations, 378-392 517-518 class A output stage, 1277-1278 class AB output stage, 1278-1281 class B output stage, 1235-1241, 1278 CMOS inverters, 374-375 CMOS logic circuits, 1002-1008 current voltage characteristics, 518-519 data converter circuits, 922-929, 946-947 dc imperfections, 135-136 differential amplifiers, 781-786 digital circuit design, 1002-1003 digital logic inverters, 61-62, 540-541 diodes, 218-234 dynamic logic circuits, 1008 ECL, 1052-1067, 1081-1082 electronics overviews, 51-62 feedback, 860-870 feedback structures, 860 filter transfer functions, 1159 filter transmissions, types, and specifications, 1159 filters and tuned amplifiers, 1159-1163 finite open loop gain effects, 134-135 first-order and second-order (biquadratic) filter functions, 1160-1161 folded cascade CMOS op amps, 883-893 941-942 forward characteristics, 223-227 frequency compensation, 870 idea op amps, 123-124 ideal diodes, 218-221 integrators and differentiators, 136-138 internal capacitances, 320-325, 372, 537-538 inverted op amps, 124-128 inverters, 1003-1004 large signal operations, 135 latches and flip-flops, 1077-1078 LC and crystal oscillators, 1222-1223 logic gate circuits, 1004-1005 loop gain determinations, 868-869 memory and advanced digital circuits, 1077-1082 monostable multivibrators, 1225 MOS differential pairs, 775-776 MOS power transistors, 1282-1283 multistage amplifiers, 786-789 negative (degenerative) feedback properties, 860-861 network theorems, C5-C6 nonlinear waveform shaping circuits, 1225-1227 op-amp and data-converter circuits, 941-947 op amp-RC oscillator circuits, 1220-1222 op amps, 123-138 overviews and summaries, 129-133 power amplifiers, 1281-1282 power BJTs, 1279-1280 • precision rectifier circuits, 1227-1228 pseudo-NMOS logic circuits, 1005-1006 PTL circuits, 1006-1007 RAM memory cells, 1079 ROMs, 1080 s domain analyses, E6-E7 second-order active filters, 1161-1162 second-order LCRs, 1161 sensitivity, 1162 series-shunt feedback amplifiers, 863-865 shunt-series feedback amplifiers, 866-867 shunt-shunt feedback amplifiers, 866-867 signal generators and waveform-shaping circuits, 1220-1228 signals, 54-55 single-amplifier biquadratic active filters, 1162 single-stage amplifiers, 533-537
IN-1 2
'
INDEX
INDEX
Problems (Continued) single-stage IC amplifiers, 666-687 single-stage MOS amplifiers, 370-372 sinusoidal oscillators, 1120 square and triangular waveforms, 1224-1225 STC circuits, D16-D17 switched capacitor filters, 1162-1163 switches, 366 367 terminal junction characteristics, 222-223 theorems, C5-C6 tuned amplifiers, 1163 two-port network parameters, B7 two-stage CMOS op amps, 941 Products, 91-93, 342-343 DP products, 342-343 GB products, 91-93 PROMs (programmable ROMs), 1046-1051 Propagation delays, 45^18, 953, 973-974 Pseudo-NMOS logic circuits, 950-951, 974-982, 1005-1006 PTL (pass transistor logic) circuits, 982-991, 1006-1007 PU (pull up) switches, 44^15 PU (pull up) transistors, 963-966 Pull down transistors, 963-966 Pulses, 1196-1198, D12-D16 responses, D12-D16 standardized generation, 1196-1198 Punch through, 260 PUNs (pull-up networks), 963-966, 968-969 Push pull operations, 1236
0 Quadrature oscillators, 1175-1177 Quantization, signals, 10, 924 Quasi-stable'multivibrators, 1021-1022 Quiescent points, 19,162, 274-275
R R-2R ladders, 926-928 Rail-to-rail operations, 890-892 RAM (random access) memory cells, 1028, 1031-1038, 1079 Rapid analyses, forward characteristics, 155 Rated output voltage, 94 Ratios, 81-82, 700-704,715-716,732-733,796-797 CMRR, 81-82, 700-704, 715-716, 732-733 signal-to-noise ratios, 796-797 RC-op amp oscillator circuits, 1171-1179, 1220-1222 RD-op amp resonators, 1114 Readings, reference, F1-F2 Recovery periods, 1198 Rectifiers, 141-144, 171-184, 1207-1228 bridge rectifiers, 1212-1213 full-wave rectifiers, 1210-1212 half-wave rectifiers, 1207-1208 overviews and summaries, 141-144, 171-184 precision rectifiers, 1206-1214, 1227-1228 superdiodes, 1207-1208 Reductions, 796-798 noises, 796-797 nonlinear distortions, 797-798 Reference bias currents, 899 Reference resources, F1-F2 Reflection resistance rule, 472 .. Regenerative (positive) feedback, 792 Regions. See also under individual topics. breakdown regions, 152-153, 203-204 carrier depletion regions (space charge regions), 197-199 cutoff regions, 248 ' depletion regions, 209 drain regions, 236 pseudo-NMOS logic circuits, 977-979 saturation regions, 242-248 silicon regions, 954 SOAs, 1254-1255 subthreshold regions, 248 triode regions, 242, 248 Regulators and regulations, 163-169 line regulations, 169 load regulations, 169 v
;
shunt regulators, 168-169 voltage regulations, 163-165 Resensitivity, 208 Resistances. See also under individual topics battery-plus-resistance models, 156-157, 166 emitter degeneration resistances, 474 incremental resistances, 161-162,168 input resistances, 72-75, 445^147, 717-720 bases, 445-446 common mode, 717-720 emitters, 446^47 vs. output resistances, 72-75 resistance reflection rule, 472 resistors. See Resistors standard values, G1-G2 thermal resistances, 1249-1250 Resistors. See also under individual topics fabrication technologies, A8-A9 feedback resistors, 284-285,441^142 collector-to-base resistors, 441^-42 drain-to-gate resistors, 284-285 load resistors, 273 overviews and summaries, 51 p-base resistors, Al 1 pinched base resistors, A l l resistances. See Resistances VLSIs, A8-A9 Resonators, 1106-1114 natural mode resonators, 1106-1107 op amp-RD resonators, 1114 second-order LCRs, 1108-1112 Responses, 492-503, 538-540, 571-600, 1085 brick wall responses, 1085 frequency responses, 492-503, 538-540, 571-600 CE frequency responses, 538-540 ' high-frequency responses, 492^-97, 571-582, 588-600 low-frequency responses, 497-503 Reverse active (inverse active) modes, 379 Reverse bias and biasing, 141, 199-203 diodes, 141 injunctions, 199-203 RFCs (radio frequency chokes), 1146 Ring oscillators, 1027 Ringing, 1062 Ripples and ripple voltage, 172 ROM (read only memory), 1028, 1046-1052, 1080 Row decoders, 1029-1030
s domain analyses, E1-E8 bode plots, E3-E6 conjugate pairs, E2 first-order functions, E2-E3 order of the network, E2 overviews and summaries, E1-E2 poles, E2 natural modes, E2 transfer function poles, E2 problems, E6-E7 stable circuits, E2 zeros, E2 transfer function zeros, E2 transmission zeros, E2 Sampling, 10, 922-923 analog signal sampling, 922-923 overviews and summaries, 10 Saturations, 94,149-152, 209, 248-256, 379-392, 505-507 current saturations, 149-152, 209 modes, 379, 390-392 output voltage saturations, 94 regions, 242-248 resistance saturations, 253-256 vs. unsaturated circuits, 505-507 SBDs (Schotty barrier diodes), 212 Scale current, 149 Schmidt triggers, 1188 Schotty TTL (Schotty transistor-transistor logic) diodes, 210 Second breakdown limits, 1255
Second order (biquadratic) filters, 1098-1106, 1112-1125, 1160-1162 Second order LCRs (liquid crystal resonators), 1108-1112 Second stage 741 op amp circuits, 895-896 Secondary windings, 171-172, 174 Self-limiting oscillators, 1180 Semiconductors, 190-196 covalent bonds, 191 diffusion and drift mechanisms, 192-194 doped, 194-196 free electrons, 191 holes, 191 intrinsic silicon, 190-192 overviews and summaries, 192 pn junctions, 190-199. See also junctions open circuits, 196-199 overviews and summaries, 190 recombination process, 191-192 Sensitivity, 1133-1136, 1162 Separations, signals, 448 Sequential vs. combinational circuits, 1013-1014 Series-series feedback amplifiers, 801-802, 811-818, 865-866 Series-shunt feedback amplifiers, 802-810, 863-865 S/H (sample-and-hold) circuits, 923 Shapers, sine wave, 1203 Sharing, charges, 994-995 Short circuits, 69, 616-895 741 op amp circuits, 895 transconductances, 616 virtual short circuits, 69 Shunt regulators, 168-169 Shunt-series feedback amplifiers, 799-801, 818-831,866-867 Shunt-shunt feedback amplifiers, 802, 818-831, 866-867 Shutdowns, thermal, 1260 SiGe BiCMOS processes, A15-A16 Signal generators and waveform shaping circuits, 1165-1228 astable multivibrators, 1192-1196 bistable multivibrators, 1185-1192, 1223-1224 comparators, 1189-1191 feedback loops, 1185-1186 memory elements, 1188 metastable states (unequal equilibrium), 1185-1186 noninverting transfer characteristics, 1188-1189 output level precision, 1191 overviews and summaries, 1185 problems, 1223-1224 Schmidt triggers, 1188 transfer characteristics, 1186-1187 trigger signals and triggering, 1185-1188 frequency selective networks, 1166 IC timers, 1198-1203 555 timer circuits, 1198-1203 overviews and summaries, 1198 LC and crystal oscillators, 1177-1185,1222-1223 Colpitts oscillators, 1179-1180 crystal oscillators, 1182-1184 Hartley oscillators, 1179-1180 LC tuned oscillators, 1177-1182 overviews and summaries, 1177 panel tuned (tank) circuits, 1179-1180 problems, 1222-1223 self-limiting oscillators, 1180 linear oscillators, 1120, 1166-1171 monostable multivibrators, 1196-1198, 1225 overviews and summaries, 1196-1198 problems, 1225 recovery periods, 1198 nonlinear waveform shaping circuits, 1203-1206, 1225-1227 breakpoint methods, 1203-1205 nonlinear amplification methods, 1205-1206 overviews and summaries, 1203 problems, 1225-1227 sine wave shapers, 1203 waveform shaping, 1203
op amp-RC oscillator circuits, 1171-1179, 1220-1222 active filter tuned oscillators, 1177-1179, 1217-1219 overviews and summaries, 1171 phase shift oscillators, 1174-1175 problems, 1220-1222 quadrature oscillators, 1175-1177 Wien-bridge oscillators, 1171-1174,1215-1217 overviews and summaries, 1165-1166,1219-1220 positive feedback'loops, 1166 precision rectifier circuits, 1206-1214,1227-1228 absolute value circuits, 1211 ac voltage measurements, 1209-1210 buffered precision peak detectors, 1213-1214 overviews-and summaries, 1206-1207 precision bridge rectifiers, 1212-1213 precision clamping circuits, 1214 precision full wave rectifiers, 1210-1212 problems, 1227-1228 superdiodes, 1207-1208 problems, 1220-1228 sinusoidal oscillators, 1120, 1166-1171 Barkhausen criterion, 1167-1168 characteristics, 1168 feedback loops, 1166-1167 hmiter circuits, 1169-1171 nonlinear amplitude controls, 1168-1169 oscillation criterion, 1167-1168 overviews, 1166 problems, 1120 sustained oscillations, 1168 SPICE simulations, 1214-1219 square and triangular waveforms, 1192-1196 1224-1225 astable multivibrators, 1192-1196 overviews and summaries, 1192 problems, 1224-1225 triangular waveforms, 1194-1196 standardized pulse generation, 1196-1198 monostable multivibrators, 1196-1198 • overviews and summaries, 1196 Signals. See also under individual topics amplification, 13-14amplifiers. See Amplifiers analog signals vs. digital signals, 10-13, 922 common mode signals, 67-68 differential signals, 67-68, 692 discrete time signals, 10 flow diagrams, 792-793 input signal injections, 1128-1130 overviews and summaries, 6-14, 54-55 passing signals, 1085 processes, 6 quantization, 924 quantized signals, 10 sampling, 922-923 separations, 448 signal-to-noise ratios, 796-797 small signals. See Small signal operations trigger signals and triggering, 1185-1188 waveforms, 1233 Silicon, 190-192, 208, 954 carrier concentrations, 208 intrinsic silicon, 190-192 regions, 954 Simulations, SPICE. See SPICE (Simulation Program with Integrated Circuit Emphasis) simulations Sine wave shapers, 1203 Single amplifier biquadratic active filters, 1125-1133, 1162 Single difference amplifiers, 81-86 Single end conversions, 727-728 Single end outputs, 698 Single grounds, 306 Single limiters, 185 Single pole models, 91, 838-843 Single stage IC (integrated circuit) amplifiers, 545-686 active loads, 582-588, 600-613 bias and biasing, 562-571 current mirror circuits, 563-565 current sources, 562-565, 569-570
current steering circuits, 565-567, 570-571 overviews and summaries, 562 BiCMOS amplifiers, 561-562 BJTs, 460-486, 533-537 cascode amplifiers, 613-629 BiCMOS cascode, 628-629 BJT cascode, 623-625 cascode transistors, 614 current sources, 625-627 folded cascodes, 627-628 MOS cascode, 614-622 overviews and summaries, 613-614 short circuit transconductances, 616 CB amplifiers, 600-613 CE amplifiers, 582-600 high frequency responses, 588-600 source (emitter) degeneration, 629-635 CG amplifiers, 600-613 CS amplifiers, 582-600 high frequency responses, 588-6Q0 source (emitter) degeneration, 629-635 current-mirror circuits, 649-656 bipolar mirrors, 650-651 cascode MOS mirrors, 649-650 overviews and summaries, 649 Widlar current sources, 653-656 Wilson current mirrors, 651-652 Wilson MOS mirrors, 652-653 designs, 546-547 emitter degeneration, 629-635 emitter followers, 635-641 high frequency responses, 571-582, 588-600 CB amplifiers, 610-613 CG amplifiers, 600-609 dc amplifiers, 572 gain functions, 572-575 Miller effect, 581 Miller's theorem, 578-582, 589-590 open circuit time constants, 575-578 overviews, 571-572 MOSFETs vs. BJTs, 547-571 overviews and summaries, 545-546, 665-666 problems, 666-687 source followers, 635-641 SPICE simulations, 656-665 transistor pairings, 641-649 CC-CB amplifiers, 646-648 CC-CE amplifiers, 641-646 CD-CE amplifiers, 641-646 CD-CG amplifiers, 646-648 CD-CS amplifiers, 641-646 overviews and summaries, 641 Single stage MOS amplifiers, 299-320, 370-372 Single supply operations, 1240-1241 Sinusoidal oscillators, 1120, 1166-1171 Sizing, transistors, 970-973 Small signal operations. See also under individual topics approximations, 161 BJTs, 443-460, 530-533, 709-720 conductances, 161 differential pairs, 696-704, 709-720, 776-777 diffusion capacitances, 207, 486 gain, 917-918 models, 159-163, 166 MOSFETs, 287-299, 368-370 overviews and summaries, 443, 458^159 resistances, 161-162 SOAs (safe operating areas), 1254-1255 Soft limiters, 185 Solar cells, 210 Source absorption theorem, C3-C5 Specialized topics, 1010-1283. See also under individual topics filters and tuned amplifiers, 1083-1165 memory and advanced digital circuits, 1013-1082 output stages and power amplifiers, 1229-1283 overviews and summaries, 1011 signal generators and waveform shaping circuits, 1165-1229 Spectrums, frequencies, 7-10 SPICE (Simulation Program with Integrated Circuit Emphasis) simulations. See-also under individual topics
IN-13
BJTs, 507-516 CMOS logic circuits, 998-1001 data converter circuits, 934-940 differential and multistage amplifiers, 767-773 diodes, 155, 174, 212-213 electronics overviews, 49-50 feedback, 855-859 filters and tuned amplifiers, 1152-1158 MOSFETs, 351-359 op amps, 114-122, 934-940 overviews and summaries, 49 signal generators and waveform shaping circuits, 1214-1219 single-stage IC amplifiers, 656-665 Splitting, poles, 852-855 Square and triangular waveforms, 1.192-1196, 1224-1225 Square law models, 351 SR flip-flops, 1016-1021 SRAMs (static RAMs), 1031-1036 SRs (slew rates), 95-97, 879-890, 917-922 741 op amp circuits, 917-922 folded cascade CMOS op amps, 888-890 overviews and summaries, 95-97 two-stage CMOS op amps, 879-883 Stability, 834-836, 845-849, 869-870, E2 feedback stability, 834-836, 845-849, 869-870 stable circuits, E2 Stagger tuning, 1148-1152 Standard resistance values, G1-G2 Standardized pulse generation, 1196-1198 Static operations, 46, 956-958 vs. dynamic operations, 46 inverters, 956-958 STC (single time constant) circuits, D1-D17 classifications, D4-D6 frequency responses, D6-D10 HP (high pass) circuits, D8-D10 LP (low pass) circuits, D6-D8 overviews and summaries, Dl problems, D16-D17 pulse responses, D12-D16 HP (high pass) circuits, D14-D16 LP (low pass) circuits, D13-D14 overviews and summaries, D12-D13 step responses, D10-D12 HP (high pass) circuits, Dl 1-D12 LP (low pass) circuits, D10-D11 overviews and summaries, D10 time constant evaluations, D1-D4 Step responses, D10-D12 Structures. See also under individual topics BJTs, 378-392, 460-461, 517-518 CMOS inverters, 955-956 dynamic logic circuits, 992-993 feedback, 792-795, 860 logic gate circuits, 963-966 MOS amplifiers, 299-301 MOSFETs, 236-238, 360, 1266-1267 series-series feedback amplifiers, 811-814 series-shunt feedback amplifiers, 802-807 shunt-series feedback amplifiers, 823-829 shunt-shunt feedback amplifiers, 819-823 single-stage amplifiers, 299-301,460-461 Styles, digital circuit design, 954-955 Substrate body effects, 258-259 Subthreshold regions, 248 Superdiodes, 183-184,1207-1208 Sustained oscillations, 1168 Sustaining voltage, 406 Swings, 885-886, 892-893 Switches, 1136-1141, 1162-1163. See also under individual topics BJT switches, 407^121 data converter circuits, 928-929 MOSFET switches, 270-280, 366-367 NMOS transistor switches, 984-988 operations, 419-421 PD switches, 44^15 PU switches, 44-45 switched capacitor filters, 1136-1141, 1162-1163 transition fate switches, 988-989 Symbols and conventions, 14, 22-23, 248-249, 392-397
IN-14
' . I
INDEX
Synchronous tuning, 1147-1148 Synthesis methods, 970
T T models, 295-296, 449^150 Tank (panel tuned) circuits, 1179-1180 Temperatures, 170-171, 1229-1230, 1249 junction temperatures, 1229-1230, 1249 tc/tempco, 170-171 Terminal characteristics, 65, 147-153. 222-223, . 288-289 drain terminals, 28S-289 inverted input terminals, 65 junctions, 147-153, 222-223 Theorems. C1-C6 Miller's theorem, 578-582, 589-590 Norton's theorem, C1-C3 overviews and summaries, CI problems, C5-C6 source absorption theorem, C3-C5 Thévenin's theorem, C1-C2 Thermal ionization, 192 Thermal resistances, 1249-1250 Thermal shutdown, 1260 Thermal voltage, 149 Thévenin equivalent circuits, 52 Thévenin's theorem, C1-C2 Thresholds, 184 Time constants, 107-113, 575-578, 1030, D1-D4 differentiators, 113 integrators, 107 memory access time constants, 1030 open circuit time constants, 575-578 time constant evaluations, D1-D4 Timers, 1198-1203 555 timers, 1198-1203 IC timers, 1198-1203 Tow-Thomas biquads, 1123-1125 Transconductance amplifiers, 28, 245, 271, 288-292, 443-445,616, 802-804 Transducers, 6 Transfer characteristics, 834—835. See also under individual topics amplifiers, 14-15, 410-112 bilinear characteristics, 1098 bistable multivibrators, 1186-1189 BJTs, 410^112 class A output stage, 1231-1233 class B output stage, 1236 closed loops, 834 filters, 1088-1091, 1159 large signals, 768-769 noninverting characteristics, 1188-1189 nonlinear characteristics, 19-22 open loops, 834 overviews and summaries, 834-835 switches, 271-279, 410-412 Transformations, 1130, 1149-1150 Transformers, 1144-1145 Transistors. See also under individual topics BJT transistors, 377-542 cascode transistors, 614 cases, 1251-1254 characteristics, 397-401 - ^ CPL transistors, 991 lateral pnp transistors, A14-A15 MOS power transistors, 1266-1271, 1282-1283 MOSFET transistors. See MOSFETs (metal oxide semiconductor field effect transistors) NMOS transistors, 238-243, 247-248, 963-966, 984-988 npn transistors, 392 pairs, 641-649 . PMOS transistors, 247-248, 963-966 pnp transistors, 391-392 power transistors, 1255 PTL circuits, 982-991, 1006-1007 sizing. 970-973 Transit times, 486 Transition fate switches, 988-989 ;
Transmissions. See also under individual topics amplifiers, 32 filters, 1084-1088, 1159 loops, 832 zeros, 1088. E2 zones, 1107-1108 Transresistance amplifiers, 28, 804 Triangular and square waveforms, 1192-1196, 1224-1225 Trigger signals and triggering, 1185-1188 overviews and summaries, 1185-1188 Schmidt triggers, 1188 Triode regions, 242-248 TTL (transistor-transistor logic) circuits, 210, 505-506, 951-952 Tuned amplifiers, 40, 1141-1152, 1163 autotransformers, 1.144-1145 cascode amplifiers, 1146-1147 CC-CB cascade amplifiers, 1146-1147 inductor losses, 1143-1144 LP-to-BP transformations, 1149-1150 maximal flatness, 1148-1149 multiple tuned circuits, 1145-1146 narrow band approximations, 1149 neutralizing effects, 1146 overviews and summaries, 1141-1143 problems. 1163 jRFCs, 1146 stagger tuning, 1148-1152 synchronous tuning, 1147-1148 transformers, 1144-1145 Tuned circuits, 1179-1180 Tuned oscillators, 1177-1182, 1217-1219 Two-input NAND (not AND) gates, 966-967 Two-input NOR (not OR) gates, 966 Two-integrator loop technologies, 1120-1125 Two-port network parameters, B1-B7 characteristics, B1-B6 equivalent circuit representations, B5-B6 h parameters, B4-B5 overviews and summaries, B1-B2 •y parameters, B2-B3 Z parameters, B3-B4 overviews and summaries, Bl problems, B7 Two-stage CMOS op amps, 749-757, 872-883, 941
U Uncovered charges, 197 Unequal equilibrium, 1185-1186 Unilateral amplifiers, 301, 461 Unilateral models, 28-29 Unit prefixes, G1-G2 Unity gain. 79-80, 91,315, 488 amplifiers, 79-80 bandwidth, 91,488 current amplifiers, 315 Unsaturated vs. saturated digital circuits, 505-507
V Varactors, 209 V multipliers biasing, 1246-1249 Velocities, drift, 193-194 V fixing, 281-284 V fixing, 280-281 Virtual grounds, 69-70 Virtual short circuits, 69 Voltage. See also under individual topics ac voltage, 1209-1210 breakdown, 152-153 built-in voltage, 198-199, 209 common-mode voltage, 689-691 constant-voltage drop models, 157-158, 166 current-voltage characteristics, 205-206, 248-262," 360-362 dc voltage, 720-723 decay, 994 differential voltage, 691-693, 713-714 diodes, 140-141 dividers, 51-52 BE
c
qs
doublers, 187-190 excess gate voltage, 239-240 followers, 79-80 offset voltage, 98, 720-735, 738-739 output voltage, 94, 885-886, 994 regulations, 163-165 ripple voltage, 180 sustaining voltage, 406 swings, 885-886 thermal voltage, 149 voltage gain, 447 VTCs. See VTCs (voltage transfer characteristics) VLSIs (very large scale integrated circuits) fabrication technologies, A1-A14 BiCMOS processes, A9-A10 capacitors, A9 CVD, A3-A4 diffusion, A3 epitaxial layers, A3 epitaxy, A3 integrated devices, A7 ion implantation, A3-A4 lateral pnp transistors, A10-A11 layouts, A12-A14 LOCOS, A7 metallization, A4 MOSFETs, A7-A8 n well CMOS processes, A5-A7 overviews and summaries, Al. A14 oxidation, A2-A3 p base resistors, A l l packaging, A4 photolithography, A4 pinched-base resistors, A l l pn junction diodes, A9 processes, A5-A12 resistors, A8-A9 SiGe BiCMOS processes, Al 1-A12 wafer preparation, A2 overviews and summaries, 45^18 VTCs (voltage transfer characteristics). See also under individual topics CMOS digital logic inverters, 339-342 derivations, 976-979 digital-logic inverters, 504—505 ECL, 1057-1061 \ overviews and summaries, 41-42 switches, 272-273 W Wafer preparation, A2 Waveforms, 1165-1228. See also Signal generators and waveform shaping circuits Weak avalanches, 260 Weighted summer circuits, 75-77 Wide swing current mirrors, 892-893 Widlar current sources, 653-656 Width of depletion regions, 209 Wien-bridge oscillators, 1171-1174, 1215-1217 Wilson mirrors, 651-653 Wilson current mirrors, 651-652 Wilson MOS mirrors, 652-653 Windings, 174 Wired OR capabilities, 1066 Word lines. 1029 XOR (exclusive OR) logic functions, 969-970
Y parameters, B2-B3
z Zparameters, B3-B4 Zener (breakdown) diodes, 167-171, 187, 213 Zeros, 1088, E2 Zones, transmission. 1107-1108
oniric us*,! oil.,, i^u ,r.^y ~upy tne~ sui t w a r e into any machine-readable form for back-up or archival purposes in support of your use of the software. The software may not be otherwise copied, networked, transmitted, electronically t o another machine,modified re-engineered, or reverse engineered. By opening this seal, you agree to abide by these terms. If you do not agree, return the book and the accompanying software with this seal unbroken for a full refund.