Microgrid Power Quality Enhancement Using a Three-Phase Four-Wire Grid-Interfacing Compensator.pdf

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005

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Microgrid Power Quality Enhancement Using a Three-Phase Four-Wire Grid-Interfacing Compensator Yunwei Li, Student Member, IEEE, D. Mahinda Vilathgamuwa, Senior Member, IEEE, and Poh Chiang Loh, Member, IEEE

Abstract—This paper presents a three-phase four-wire grid-interfacing power quality compensator for microgrid applications. The compensator is proposed for use with each individual distributed generation (DG) system in the microgrid and consists of two four-phase-leg inverters (a shunt and a series), optimally controlled to achieve an enhancement of both the quality of power within the microgrid and the quality of currents flowing between the microgrid and the utility system. During utility grid voltage unbalance, the four-phase-leg compensator can compensate for all the unwanted positive-, negative-, and zero-sequence voltage–current components found within the unbalanced utility. Specifically, the shunt four-leg inverter is controlled to ensure balanced voltages within the microgrid and to regulate power sharing among the parallel-connected DG systems. The series inverter is controlled complementarily to inject negative- and zero-sequence voltages in series to balance the line currents, while generating zero real and reactive power. During utility voltage sags, the series inverter can also be controlled using a newly proposed flux–charge current-limiting algorithm to limit the flow of large fault currents between the micro- and utility grids. The performance of the proposed compensator has been verified in simulations and experimentally using a laboratory prototype. Index Terms—Fault current limitation, four-phase-leg inverter, microgrid, power quality compensator, sequence voltages/currents.

I. I NTRODUCTION

M

ICROGRIDS can generally be viewed as a cluster of microgenerators connected to the mains utility grid, usually through some voltage-source-inverter (VSI)-based interfaces. Concerning the interfacing of a microgrid to the utility system, an important area of study is to investigate the impact of unbalanced utility grid voltages and utility voltage sags, which are two most common utility voltage quality problems, on the overall system performance. As a common practice, if the utility grid voltages are seriously unbalanced, a separation device, connected between the microgrid and the mains grid to provide isolation in the event of mains faults as in Fig. 1(a),

Paper IPCSD-05-064, presented at the 2004 Industry Applications Society Annual Meeting, Seattle, WA, October 3–7, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review October 15, 2004 and released for publication August 26, 2005. The authors are with the Center for Advanced Power Electronics, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). Digital Object Identifier 10.1109/TIA.2005.858262

will open and isolate the microgrid. However, when the utility voltages are not so seriously unbalanced, the separation device will remain closed, subjecting the microgrid to sustained unbalanced voltages at the point of common coupling (PCC), if no compensating action is taken. Such an unbalance in voltages can cause increased losses in motor loads and abnormal operation of sensitive equipment. An obvious solution is to balance the voltages within the microgrid using some voltage regulation techniques. However, large unbalanced currents can flow between the unbalanced utility grid and microgrid due to the very low line impedance interfacing both grids, if only the microgrid voltages are regulated [1]. This flow of large currents can overstress semiconductor devices within the interfacing inverters and the distribution lines, and is expected to worsen during utility voltage sags when the voltage differences between the utility grid and the microgrid increase. For low voltage distribution, where microgrids are usually constructed with a four-wire configuration to supply both single-phase and three-phase loads, the problem is further complicated by the flow of zero-sequence currents through the line and neutral conductors. To mitigate the above-mentioned complications, this paper proposes a grid-interfacing power quality compensator for three-phase four-wire microgrid applications. The proposed compensator is to be used with each individual distributed generator (DG), and it consists of two optimally controlled four-phase-leg inverters (a shunt and a series as in Fig. 1). Operating together, the two four-leg inverters can compensate for all the unwanted positive-, negative-, and zero-sequence voltages/currents within the system, enhancing both the quality of power within the microgrid and the quality of current flowing between the microgrid and the utility. During utility voltage sags, the compensator can also be controlled to limit the flow of large fault currents using a newly proposed flux–charge currentlimiting algorithm. The proposed system has been tested in simulations and experimentally using a laboratory hardware prototype. Lastly, to assist readers in identifying objectives of the paper, Table I, summarizing the compensator functionalities and control features, is included. II. T HREE -P HASE F OUR -W IRE G RID -I NTERFACING P OWER Q UALITY C OMPENSATOR Fig. 1 shows the general layout of the proposed grid-interfacing power quality compensator. The compensator consists

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Fig. 1. Proposed microgrid compensator. (a) Overall system structure. (b) Inverter topology. TABLE I POWER COMPENSATOR FEATURES AND CONTROL STRUCTURES

of two four-phase-leg inverters, namely inverter A (shunt) and inverter B (series). The main functions of inverter A are to maintain a set of balanced sensitive load voltages within the microgrid even under unbalanced load and grid voltage conditions, generate and dispatch power, share the power demand optimally with the other parallel-connected DG systems when the microgrid islands, and synchronize the microgrid with the utility system at the instant of connection. In addition, being connected directly to the microsource, inverter A must have sufficiently high power capacity with rated voltage and headroom for current higher than the rated value (in fault conditions) in order to continuously condition the routine energy supplied by the microsource (similar to most shunt inverter applications on power systems). On the contrary, the main functions of inverter B are to maintain a set of balanced line currents by introducing negative- and zero-sequence voltages to compensate for the grid voltage unbalance, and to limit the flow of large fault currents during utility voltage sags. This second control

task would require inverter B to carry relatively large current with a high compensating voltage appearing across it, implying that inverter B must have high power rating, too. It is commented that the operational principles of the compensator presented here are different from those of a unified power quality conditioner (UPQC), which is usually constructed using a shunt and a series three-phase-leg inverter. For a UPQC, the series three-leg inverter injects voltages to maintain a set of balanced distortion-free voltages at the load terminals, while the shunt three-leg inverter injects harmonic compensating currents into the alternating current (ac) system to shape the supply currents drawn by the UPQC-conditioned loads as balanced sinusoids. In addition, the UPQC is usually designed to function with zero real power flow through it during steady state to minimize the size of the direct current (dc) link energy storage capacitor [2]. These control objectives of a UPQC are obviously different from those of the proposed fourphase-leg compensator, where inverter A is used for voltage

LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR

Fig. 2. Control scheme for shunt inverter A. (a) Overall control structure. (b) Voltage control algorithm.

regulation and power control, and inverter B is used for line current balancing and fault current limiting, as described earlier. Therefore, for the proposed compensator, the development of an appropriate control algorithm is challenging since existing UPQC control algorithms are not directly applicable, and most references on four-phase-leg compensators in the literature are for either a shunt or a series four-leg inverter, but not for both used simultaneously. This control development is presented next in the remaining sections of the paper. III. C ONTROL OF S HUNT I NVERTER A A. Description of Control Algorithm As shown in Fig. 2(a), the control system of shunt inverter A contains a voltage–current regulation block, and external real and reactive power control blocks. The detailed design of the power control blocks has already been presented by Li et al. [3] and is therefore not duplicated here. Instead, this paper focuses more on the design of the voltage–current regulation block of shunt inverter A, after giving an introductory description of the power control blocks for the sake of completeness. In brief, the power blocks control real and reactive power flow, and facilitate power sharing between the paralleled DG systems when a utility fault occurs and the microgrid islands. This sharing of power is achieved with no physical communication link between the DG systems by introducing artificial “real power versus supply frequency” and “reactive power versus voltage magnitude” droop characteristics into the power loops. Outputs of the power controllers are the reference frequency ω, phase δ, and the positive-sequence voltage magnitude E. These

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variables are subsequently transformed to stationary α−β−0 frame quantities {Vα∗ , Vβ∗ , V0∗ }, used as reference voltages for the voltage–current regulation block. The external power blocks also incorporate synchronization algorithms for ensuring smooth and safe reconnection of the micro- and utility grids when the fault is cleared. Synchronization can be achieved by aligning the voltage phasors at the microgrid and utility ends of the separation device whose location is indicated in Fig. 1(a), and it can conveniently be implemented by adding two separate proportional and integral (PI) synchronization regulators to the external real and reactive power control algorithms [see Fig. 2(a)]. Inputs to these PI regulators are the magnitude ∆E and phase ∆δ errors of the two voltage phasors at both ends of the separation device, and their outputs are fed to the real and reactive power loops to make ∆E → 0 and ∆δ → 0, ensuring close tracking of the voltage phasors at both ends of the separation device. As mentioned earlier, details of these power control algorithms can be found in an earlier publication [3]. Fig. 2(b) shows the voltage–current regulation scheme for inverter A, which contains an inner filter inductor current control loop and an outer load voltage control loop. For the outer voltage loop, the theoretical analysis is first presented in the synchronous d−q−0 reference frames to assist in understanding the control principles. The developed voltage controllers are subsequently converted back to the stationary frame to allow for easier physical implementation. As illustrated in Fig. 2(b), the three-phase load voltages are first transformed from the stationary a−b−c frame to the stationary α−β−0 frame using the following quad transformation matrices [4] 2 Tαβ0 Uabcn (1) Uαβ0 = 3 Uαβ0 = [Uα Uβ U0 ]T (2) Uabcn = [Uan Ubn Ucn Un ]T   − 21 0 1 − 12 √ √   3 Tαβ0 =  0 − 23 0  2 1 1 1 √ √ √ − 2√3 2 2 2 2 2 2 2

(3) (4)

where Un is a placeholder quantity, usually chosen to be 0 [4]. The α−β−0 voltages are subsequently transformed to the forward-rotating positive-sequence synchronous frame (indicated with superscript “+”) and reverse-rotating negativesequence frame (indicated with superscript “−”) using the following transformation matrices: + = Ud+ Uq+ Udq0  cos(ωt) + =  − sin(ωt) Tdq0 0 − Udq0 = Ud− Uq−  cos(ωt) − Tdq0 =  − sin(ωt) 0

U0+

T

+ = Tdq0 Uαβ0  sin(ωt) 0 cos(ωt) 0  0 1 T − U0− = Tdq0 Uαβ0  − sin(ωt) 0 − cos(ωt) 0  . 0 1

(5) (6) (7) (8)

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+ − Note that the first two rows of Tαβ0 , Tdq0 , and Tdq0 resemble the commonly used three-phase “a−b−c to α−β to d−q” transformation. Equations (1)–(8) can therefore be viewed simply as an extension from the three-phase “a−b−c to α−β to d−q” transformation with only an independent zero-sequence row added. It would therefore be convenient to control the d−q voltages independently from the zero-sequence voltages, as indicated in Fig. 2(b) with the zero-sequence control path drawn external to the dotted box enclosing the d−q control paths. To achieve zero steady-state errors when controlling the positive- and negative-sequence d−q voltages, two PI controllers are used along the positive- and negative-sequence d−q control paths. Practically, the implementation of these d−q controllers can be computationally inefficient due to the numerous coordinate frame transformations needed [6]. A more efficient form of the voltage controllers can be derived by transforming both the positive- and negative-sequence PI controllers to the stationary α−β frame using either the state-space or frequencydomain technique [5], [6]. Performing this inverse transformation with kp+ = kp− = kp and ki+ = ki− = ki , the α−β frame voltage controllers can be expressed as

is 2kp + s22k+ω 2 0

0 is 2kp + s22k+ω 2

.

(9)

Effectively, these voltage ( P + resonant) controllers introduce an infinite gain at the positive (50 Hz) and negative (−50 Hz) fundamental frequencies to force the positive- and negative-sequence voltage errors to zero [see Fig. 3(a) for an example bode plot of (9) using a positive resonant frequency of 50 Hz], and can conveniently be implemented in the stationary α−β frame with minimum computational requirements [6]. The same P + resonant compensator with the resonant frequency set at 50 Hz can also be used for controlling the zerosequence voltage, again with zero steady-state error, as shown in Fig. 2(b). Note that for this work, the resonant frequency is set by inverter A “real power versus supply frequency” droop controller and not the utility grid frequency. A mechanism to track the grid frequency for determining resonant condition (or transformation phase for synchronous PI implementation) is therefore not required. The outputs of the individual voltage controllers when added together give the demanded reference currents Iα∗ , Iβ∗ , and I0∗ for the inner filter inductor current loop. This inner loop is implemented using only proportional controllers with peak current limiting in the stationary α−β−0 frame as any steadystate error in this loop would not affect the outer voltage loop accuracy substantially. The outputs of the current controllers are then transformed back to the a−b−c frame and sent to a four-phase-leg pulsewidth-modulation (PWM) modulator for switching shunt inverter A. B. Closed-Loop Transfer Functions As far as the dynamics of the outer voltage loop is concerned, the inner current loop is considered to be having fast dynamic response. The inner loop can therefore be represented as a

Fig. 3. Bode plots of P + resonant compensators using (a) (9) and (b) (15) with kP = 1, ki = 20, ω = 314 rad/s, and ωcut = 10 rad/s.

constant gain and the closed-loop transfer functions of inverter A control scheme can be derived in the α−β frame as V =

Cs3

2kp s2 + 2ki s + 2ω 2 kp V∗ + 2kp s2 + (ω 2 C + 2ki )s + 2ω 2 kp

(10)

and along the zero-sequence axis as V =

kp0 s2 + 2ki0 s + ω 2 kp0 V ∗. Cs3 + kp0 s2 + (ω 2 C + 2ki0 )s + ω 2 kp0 0

(11)

Both (10) and (11) are third-order transfer functions, whose transient and tracking performance can be improved by increasing the proportional gains {kp , kp0 } and resonant gains {ki , ki0 }, respectively, at the expense of stability. For this work, a tradeoff is obtained by choosing 2kp = kp0 = 0.1 and ki = ki0 = 100 (other system parameters are listed in Table II), which gives the same bode plot in Fig. 4 for both (10) and (11). This figure generally indicates good fundamental compensation and rapid high-frequency attenuation of the controller with an infinite


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TABLE II SYSTEM PARAMETERS

Fig. 4.

Bode plot of closed voltage loop of inverter A.

gain margin, 61.9◦ phase margin, 3.1-ms step response time, and 22.5% overshoot. IV. C ONTROL OF S ERIES I NVERTER B D URING U TILITY V OLTAGE U NBALANCE A. Description of Control Algorithm The circuit connection of series inverter B is shown in Fig. 1(a), where a four-leg inverter is again adopted for the control of zero-sequence component. The main function of the series inverter is to maintain a set of balanced line currents; i.e., to force the negative- and zero-sequence currents to zero in the three-phase four-wire system. Note that this inverter is not designed to control the positive-sequence currents, which are already (directly) regulated by shunt inverter A (in the power control loop). Fig. 5(a) shows the control scheme for series inverter B, where an inner voltage loop is shown embedded within an outer current loop. The outer current loop (also referred to as the reference voltage generator) functions to generate reference voltages for the inner voltage loop using the negative- and zero-sequence line currents as inputs. As seen, the measured

Fig. 5. Control scheme for series inverter B. (a) General representation. (b) Outer current loop in the negative synchronous frame. (c) Inner voltage loop.

line currents are first transformed to the negative synchronous d−q−0 reference frame using (1) and (7), and regulated with zero reference values using PI controllers for the negativesequence d−q currents and a resonant controller for the zerosequence component [see Fig. 5(b)]. (Note that the α−β resonant controllers described in Section III compensate for both positive- and negative-sequence components and therefore cannot be used here for solely compensating the negativesequence component. In addition, note the use of a nonideal resonant controller along the zero-sequence control path, which is particularly needed for this work due to experimental constraints described in the next subsection.) Before feeding into the PI controllers, the current signals should be filtered to remove positive-sequence currents, which appear as ac signals at twice the fundamental frequency, leaving only dc negative-sequence currents for compensation. This filtering is needed for enhancing the robustness of the control loop and is performed by averaging the d−q currents over half a fundamental cycle in the negative synchronous frame [8]. Quite obviously, a degradation associated with this “half fundamental

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cycle” filtering would be the overall poorer controller transient response. Also shown in Fig. 5(b) are measures taken to decouple the d- and q-control paths (indicated by dotted lines in the figure) to arrive at three decoupled d-, q-, and 0-axis control paths, which can be tuned independently. The outputs of this outer reference voltage generator, consisting only of negative- and zero-sequence components, are then transformed back to the α−β−0 frame and fed into the inner voltage control loop. The block representation of the inner voltage loop is shown in Fig. 5(c), where P + resonant controllers are used along the α−β−0 control paths. The use of P + resonant controllers in the inner control loop will force the filtered capacitor voltages VC of the series inverter to track the demanded negativeand zero-sequence reference voltages VC∗ with zero steadystate errors and eliminate any positive-sequence component since its reference value is kept at zero for the series inverter. The series inverter therefore injects only negative- and zerosequence voltages into the system to maintain a set of balanced line currents with no real and reactive power generation (or absorption) in the steady state. Note that an inner filter inductor current loop can be added to the voltage control loop to give a better dynamic response. However, due to the slow response of the outer reference voltage generation loop, a single inner voltage loop is considered sufficient, and this loop can reasonably be represented by a unity gain when designing the control scheme. B. Closed-Loop Transfer Functions As a common practice, the design of the proposed control algorithm for the series inverter begins with the inner voltage loop in the α−β−0 frame. Analyzing Fig. 5(c) with Kinv = 2/Vdc , the closed-loop transfer function of the inner voltage loop can be derived as in (12), shown at the bottom of the page, where RLine and LLine , which normally represent line resistance and inductance, are here lumped together with the series transformer winding parameters for convenience. When performing zero-sequence analysis, neutral line parameters are also lumped into RLine and LLine . To maintain stability, the Routh’s stability criteria of (13) and (14) must be met for the inner voltage loop 2ki L2Line > 0 RLine 2kp RLine + 2ki LLine + RLine + Lf Cf RLine ω 2 α

2 + L2f Cf RLine ω 2 2ki Lf Cf RLine − > 0. 2k L2Line Lf − Ri Line Lf −

(13)

(14)

To confirm the robustness of the inverter B control scheme, a typical distribution system where the line reactance is either the same or smaller than the line resistance [7] is considered. With the series transformer leakage impedance lumped together with the line impedance for simplicity, and even with an onerous condition of XLine = (2πf )LLine = 2RLine for this distribution system, the stability condition (13) becomes Lf − (2ki RLine /π 2 f 2 ) > 0, which can easily be met. Consequently, (14) can also be met since the α term in (14) is now minimized by having a relatively larger denominator than numerator (the numerator is usually small due to the presence of a microfarad capacitive term Cf ). Once the design of the inner voltage loop is completed, the next step is to design the outer reference voltage generator in the negative synchronous reference frame. In the negative synchronous d−q frame, positive-sequence currents, which appear as ac signals at twice the fundamental frequency, should be removed using “half fundamental cycle” filtering [8] to enhance the robustness of the control loop. Another consideration is to identify an alternative nonideal resonant controller [see Fig. 5(b)] for use along the zero-sequence control path, whose transfer function is expressed as [6]

kp0 +

2ki0 ωcut s s2 + 2ωcut s + ω 2

(15)

where ωcut represents the low-frequency cutoff. An example bode plot of (15) is given in Fig. 3(b), which obviously shows a wider resonant peak with a large finite gain, as compared to that of (9) given in Fig. 3(a). Equation (15) is therefore less sensitive to frequency fluctuation, and the steady-state error would be still kept relatively small. This nonideal controller should generally be used in cases with resonant frequency variations, and it is particularly applicable to the experimental series inverter implemented in Section VIII. In that prototype, the inverter neutral phase-leg is asynchronously switched by an external analog comparator and triangular signal generator due to the shortage of synchronized PWM channels on the dSPACE DS1103 controller card. This causes slight frequency variation in the neutral line current waveform, whose effect is nullified by the α−β−0 transformation matrix in (4) along the outer negative-sequence PI control path. However, along the 0-axis control path, its effect is not nullified, and, therefore, the nonideal P + resonant compensator with a wider resonant bandwidth is needed for reducing the system sensitivity level. Incorporating these fine-tuning schemes, the final closedloop transfer functions of the proposed control algorithm can

GVcl = kp LLine s3 + (2kp RLine + 2ki LLine )s2 + (2kp ω 2 LLine + 2ki RLine )s + 2kp ω 2 RLine Lf Cf LLine s5 + Lf Cf RLine s4 + (Lf + LLine + 2kp LLine + Lf Cf LLine ω 2 )s3 + (2kp RLine + 2ki LLine + RLine + Lf Cf RLine ω 2 )s2 + (2kp + 1)ω 2 LLine + ω 2 Lf + 2ki RLine s + (2kp + 1)ω 2 RLine

(12)


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Fig. 7. Flux–charge control scheme for series inverter B.

Fig. 6.

Open-loop Bode plot of zero-sequence control path.

be written as (16) in the negative d−q frame and (17) (shown at the bottom of the page) along the 0-axis GIcl =

kp s + ki . LLine s2 + (RLine + kp )s + ki

(16)

Using (16) and setting kp = 1.5 and ki = 80, the outer control loop gain margin, phase margin, and settling time are specified as infinity, 114◦ , and 0.2 s, respectively, with the long settling time inherently caused by the “half fundamental cycle” response time needed for outer loop filtering. For the 0-axis, setting kp0 = 16, ki0 = 200, and ωcut = 10 rad/s, and using the open-loop bode plot in Fig. 6 for the zero-sequence control path with the neutral line impedance included (see Table II for the neutral impedance parameters), the gain and phase margins are set to infinity and 89.7◦ , respectively. Together, these selected control parameters ensure the stability of series inverter B.

V. C ONTROL OF C OMPENSATOR D URING U TILITY V OLTAGE S AGS (F AULT C URRENT L IMITATION ) The control schemes, presented in the earlier two sections, regulate the compensator well during normal operating conditions, but not during utility voltage sags. Referring to Fig. 7, sag drops below its nominal value, and at the start of a sag, V shunt inverter A should now disable its external power control algorithms and set its voltage references ({Vα∗ , Vβ∗ } in Fig. 2) to some appropriate values according to the load sensitivity level. As an example, consider the (ideal) case where {Vα∗ , Vβ∗ } and, D , are kept hence, the shunt inverter terminal voltage phasor V constant at their nominal values with their phase-angles locked

GIcl

at the presag values to prevent the tripping of sensitive loads. D constant, however, gives rise to a large voltage Maintaining V sag ) across series inverter B and the distribution phasor (VD − V line, resulting in large fault currents flowing along the line. If these fault currents are allowed to flow through the line until clearance of the sag or opening of the electromechanical circuit breaker, there is a risk of damaging semiconductor devices in the inverters. A possible ride-through scheme for the above-mentioned complications would be to control series inverter B to act as a virtual current-limiting inductor L0 immediately after the sensing of a voltage sag. Sensing of voltage sag is indirectly done here by measuring the local three-phase line currents since in actual cases, the PCC can be located far away from the power compensator, and, therefore, its voltages are inaccessible to the compensator. Upon the instantaneous current value of a phase exceeding a specified threshold IT , inverter B is invoked to inject a large virtual inductance L0 in series with the line impedance {RLine , LLine } to limit the current flowing along the sag . By keeping V E ≈ V sag , smooth E ≈ V line, maintaining V recovery from a voltage sag can also be ensured by simply sag back to its nominal E , which will rise with V sensing V value. The fault current limiting action of inverter B can then be inhibited and the power algorithms of inverter A can be reenabled. One way of controlling inverter B as a virtual inductor is to use the flux-model control concept reported in [9] and [10]. In passing, it is commented that the predictive fluxmodel control presented in [9] and [10] is highly sensitive to system parameter variations, which is a common feature for most predictive schemes. An alternative robust flux–chargemodel control, with an outer flux-model and an inner chargemodel loop, is therefore proposed in this paper for controlling inverter B, as shown in Fig. 7. The control variable used for the outer flux model is the inverter filtered terminal flux, defined as Φ = VC dt, where VC is the filter capacitor voltage of the series inverter. This flux variable is compared against a

kp0 s2 + 2ωcut kp0 + ki0 s + ω 2 kp0 (17) = LLine s3 + 2ωcut LLine + RLine + kp0 s2 + ω 2 LLine + 2ωcut RLine + 2ωcut kp0 + 2ωcut ki0 )s + ω 2 (RLine + kp0

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Fig. 8. Bode plots of (a) closed charge loop and (b) open flux loop.

reference flux given by Φref = −L0 iLine , where iLine is the line current and the negative sign is to indicate that iLine is drawn flowing out of the series inverter in this paper. The flux error is then fed to the flux regulator, implemented using the P + resonant compensator given in (9). It can be shown through classical control analysis that this single flux model cannot damp out the resonant peak of the inductance–capacitance (LC) filter connected to the output of inverter B (analytical details are not shown here due to space limitation). To stabilize the system, an inner charge model is therefore added to force the filter capacitor charge, defined as Q = iC dt = Cf VC , where iC and Cf are the current through and capacitance of the filter capacitor, to track the reference charge output Qref of the flux regulator. Intuitively, the presented flux–charge model can be derived from the voltage–current control presented in Section III-A for shunt inverter A by integrating the voltage and current variables. The minor difference is that the capacitor current is to be integrated for the flux–charge model rather than the filter inductor current. Integrating the capacitor current would also

mean measuring the capacitor voltage. Therefore, the system was implemented by sensing the capacitor voltage, and Q can then be calculated directly from VC (noting that Q = iC dt = Cf VC ) without requiring additional current sensors. Although sharing common control principles, the flux–charge control does have an implementation advantage over voltage–current control. The additional integration in flux–charge control would allow its outer loop flux reference to be easily computed by multiplying L0 and iLine without differentiation (differentiation of iLine is needed for voltage–current control). The resulting flux reference is therefore more accurately calculated (without phase delay and noise amplification associated with differentiation), and the flux–charge-controlled series inverter would emulate virtual inductor L0 more closely. The calculated charge error is then fed to the charge regulator with a designed transfer function of kTd s/(1 + (Td s/N )). Note from this expression that a derivative term is found in its numerator. Intuitively, this derivative term neutralizes the effects of voltage and current integrations at the inputs of the flux–charge model, resulting in the proposed algorithm having the same regulation performance as the multiloop voltage–current feedback control. This similarity in performance is confirmed by plotting the closed-loop response of the charge model in Fig. 8(a) with kTd = 1000 and Td /N = 0.00002. As anticipated, the resulting bode plots have bandpass characteristics with a near-unity gain at the fundamental frequency, similar to those of an inner capacitor current loop (example bode plots of an inner capacitor current loop can be found in [11]). Lastly, to confirm the stability of the proposed flux–chargemodel control, its open-loop Bode plots are plotted in Fig. 8(b) with 2kp = 0.08 and 2ki = 160. The plotted figure clearly shows the system exhibiting good performance at the fundamental frequency with all high-frequency switching components effectively attenuated. (Closed-loop response of the flux–charge-model control is very similar to that of shunt inverter A in Fig. 4 and is therefore not explicitly shown.) VI. S IMULATION R ESULTS Simulation results using Matlab/Simulink are provided to verify the effectiveness of the proposed system. The system parameters used for simulation are given in Table II. These represent typical distribution system parameters as given in [7]. Fig. 9(a) shows the voltage profile used for simulation where the grid voltages are initially balanced. From t = 1.2 s onwards, negative sequence voltages of 0.1 per unit (p.u.) and zero-sequence voltages of 0.1 p.u. are added to the original balanced voltages. With the proposed grid-interfacing compensator added, Fig. 9(b) and (c) shows that the sensitive load voltages in the microgrid are kept well balanced even under unbalanced utility voltage conditions. This clearly verifies the performance of shunt inverter A in maintaining good power quality within the microgrid. Fig. 10(a) and (b) shows the extremely unbalanced line currents under grid voltage unbalance and without the functioning of series inverter B, which can cause system complications, as described in Section I. By operating series


Fig. 9. Simulated waveforms of (a) mains grid voltages, (b) a−b−c frame sensitive load voltages in the microgrid, and (c) α−β−0 frame sensitive load voltages in the microgrid.

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Fig. 11. Simulated filtered voltages generated by series inverter B. (a) a−b−c frame. (b) α−β−0 frame (zoomed-in view in the steady state).

Fig. 12. Simulated line currents with series inverter B. (a) a−b−c frame. (b) Negative d−q−0 frame. Fig. 10. Simulated line currents without series inverter B. (a) a−b−c frame. (b) Negative d−q−0 frame.

inverter B, these unbalanced line currents can be mitigated, as illustrated in Figs. 11 and 12. Fig. 11(a) shows the filtered voltages [VCan , VCbn , and VCcn ; see Fig. 1(a)] generated by series inverter B during the transient period of inverter B activation (from 1.15 to 1.5 s), while Fig. 11(b) shows the zoomedin view of the voltages in steady state (from 1.9 s onwards), which clearly show the presence of only negative- and zerosequence components. The performance of series inverter B is further verified by observing the line currents shown in Fig. 12(a) and (b), where the initial unbalanced line currents become balanced again after 0.2 s later. This 0.2-s time lapse is anticipated due to the “half fundamental cycle” averaging process used in inverter B outer control loop, as described in Section IV-B. Fig. 13(a)–(d) shows the power generated by the two inverters. As illustrated in these figures, shunt inverter A dispatches a constant real power of 300 W and a reactive power of 160 Var in steady state, while series inverter B constantly maintains zero real and reactive power output. The zero power output of series inverter B is expected since it injects only negative- and zerosequence voltages into a system where only positive-sequence line currents flow.

Fig. 13. Simulated waveforms of (a) real power supplied by shunt inverter A, (b) reactive power supplied by shunt inverter A, (c) real power supplied by series inverter B, and (d) reactive power supplied by series inverter B.

The current-limiting action of the compensator is also confirmed by simulating an unbalanced utility voltage sag (VGa = 32 ∠ − 44.7◦ , VGb = 66.4 ∠ − 170◦ , and VGc = 54.5 ∠ 38.6◦ )

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Fig. 14. Simulated waveforms of (a) mains grid voltages and (b) a−b−c frame sensitive load voltages in the microgrid.

Fig. 16. Simulated waveforms of (a) real power supplied by shunt inverter A, (b) reactive power supplied by shunt inverter A, (c) real power supplied by series inverter B, and (d) reactive power supplied by series inverter B.

real and reactive power absorbed by series inverter B. As confirmed in Fig. 16(c), series inverter B absorbs no real active power since it acts as a fictitious inductor during the sag period. VII. E XPERIMENTAL R ESULTS

Fig. 15. Simulated waveforms of (a) a−b−c frame voltages injected by series inverter B and (b) a−b−c frame line currents.

at t = 1.2 s in Fig. 14(a). From the load viewpoint, shunt inverter A should ideally maintain the microgrid voltages at their nominal values (power control algorithms of inverter A are disabled during the sag, as mentioned earlier). This ideal case, however, does not give the worst scenario for performance evaluation of the compensator since it would mean a step voltage disturbance only on the utility side of the compensator. An alternative case where the shunt inverter regulates its voltages at 90% of nominal is therefore assumed here to test the compensator performance when voltage steps are introduced on both its utility grid and microgrid sides while still drawing high line currents. Fig. 14(b) shows the corresponding simulated waveforms for inverter A, where, as anticipated, the microgrid voltages are maintained at 90% of their desired nominal values during the sag. With the proposed flux–charge algorithm implemented, the series inverter now acts like a large virtual inductor connected in series with the distribution feeder, limiting the line currents to a specified peak value of 6 A. The voltages across this inserted virtual inductor and the limited line currents are shown in Fig. 15(a) and (b), respectively. Lastly, Fig. 16(a) and (b) shows the increase in real and reactive power supplied by shunt inverter A during the sag, while Fig. 16(c) and (d) shows the

To verify the performance of the proposed compensator experimentally, a hardware prototype that has the same system parameters as in the simulation has been built in the laboratory (Table II). For the experimental system, a stiff programmable ac source connected to a resistance–inductance (RL) load is used to represent the utility grid and is connected to an emulated microgrid through a three-phase back-to-back silicon-controlled rectifier (SCR) isolation switch. The microgrid consists of the proposed compensator [a shunt four-leg insulated gate bipolar transistor (IGBT) inverter and a series four-leg IGBT inverter with an injection transformer] and a connected RL load. The compensator is controlled using a dSPACE DS1103 controller card with a relatively low sampling frequency fsa of 5 kHz used due to the long computational time needed for controlling two inverters simultaneously and the use of Simulink auto-code generation without optimization. (Note that the inverter PWM pulses are generated by embedded peripherals in the slave TMS320F240 processor mounted on the DS1103 card. The inverter switching frequency fsw can thus be set at 10 kHz even though the sampling frequency of the main DS1103 processor is only 5 kHz.) According to digital control theory, an immediate impact of using a lower sampling frequency would then be the poorer experimental response as compared to its simulated counterpart (this has been verified in simulation, but the simulated waveforms with distortions are not shown here due to space limitation). To ensure proper starting of the experimental system, the utility grid and the microgrid are powered up separately. After synchronizing the voltages at both ends of the SCR switch, the switch is closed to connect the micro- and utility grids, allowing the system to transit smoothly into the grid-connected mode of operation. Fig. 17(a)–(c) shows the utility voltages and


Fig. 17. Experimental waveforms of (a) mains grid voltages, (b) a−b−c frame sensitive load voltages in the microgrid, and (c) α−β−0 frame sensitive load voltages in the microgrid.

Fig. 18. Experimental filtered voltages generated by series inverter B. (a) a−b−c frame. (b) α−β−0 frame (zoomed-in view in the steady state).

microgrid load voltages, which are initially balanced. At t = 3.775 s, the utility voltages become unbalanced with 0.1-p.u. negative-sequence and 0.1-p.u. zero-sequence voltage components added. Despite this unbalance in utility voltages, the load voltages in the microgrid are kept balanced by controlling shunt inverter A. Similarly, to balance the currents flowing between the micro- and utility grids, series inverter B is operated with its injected negative- and zero-sequence voltages shown in Fig. 18(a) and (b). As compared to their simulated counterparts in Fig. 11, the experimental α−β waveforms in Fig. 18(b) are observed to be oscillatory, whereas the 0-axis waveform is (nearly) undistorted. As mentioned earlier, the relatively low experimental sampling frequency (fsa = 5 kHz = 0.5fsw ) used can cause oscillatory response in the system. Along the α−β control path for series inverter B (see Section IV-A), this oscillatory distortion is averaged out by the “half fundamental cycle” filter and is therefore not eliminated by the PI controllers. On the other hand, along the 0-axis control path where no filtering is performed, this distortion is directly compensated and therefore has lesser effect on the system.

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Fig. 19. Experimental line currents with series inverter B. (a) a−b−c frame. (b) Negative d−q−0 frame.

Fig. 20. Experimental waveforms of (a) real power supplied by shunt inverter A, (b) reactive power supplied by shunt inverter A, (c) real power supplied by series inverter B, and (d) reactive power supplied by series inverter B.

The effectiveness of series inverter B in balancing the line currents by suppressing negative- and zero-sequence current components is shown in Fig. 19(a) and (b). These experimental waveforms are less damped as compared to their simulated counterparts in Fig. 12, and the cause is identified in simulation to be the less accurate “half fundamental cycle” averaging associated with a low experimental sampling rate. Fig. 20(a)–(d) shows the real and reactive power supplied by the shunt and series inverters. These figures clearly show the shunt inverter supplying its specified dispatched power of 300 W and 160 var, and the series inverter injecting zero real and reactive power, as anticipated. The performance of the compensator during a voltage sag is also verified experimentally by programming the ac source to emulate a voltage sag (similar to that used for simulation) at t = 0.807 s, as shown in Fig. 21(a). Fig. 21(b) shows the microgrid load voltages kept constant at 90% of the nominal value during the transition from normal to sag condition, while Fig. 22(a) and (b) shows the voltages across and limited line currents through series inverter B, which now acts as a large

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Fig. 21. Experimental waveforms of (a) mains grid voltages and (b) a−b−c frame sensitive load voltages in the microgrid. Fig. 23. Experimental waveforms of (a) real power supplied by shunt inverter A, (b) reactive power supplied by shunt inverter A, (c) real power supplied by series inverter B, and (d) reactive power supplied by series inverter B.

balance the line currents, generating zero real and reactive power during compensation. During utility voltage sags, the series inverter can also be controlled to limit the flow of large fault currents using the proposed flux–charge control algorithm. The proposed system has been tested in simulations and experimentally using a laboratory prototype with satisfactory results obtained for confirming the effectiveness of the compensator. R EFERENCES Fig. 22. Experimental waveforms of (a) a−b−c frame voltages injected by series inverter B and (b) a−b−c frame line currents.

virtual inductor. These waveforms again exhibit some transient oscillations, which can be eliminated by setting fsa = fsw or 2fsw (commonly adopted for optimized digital implementation), as verified in the simulation. Lastly, the corresponding increase in real and reactive power supplied by shunt inverter A during the sag are shown in Fig. 23(a) and (b), while the real and reactive power absorbed by series inverter B are shown in Fig. 23(c) and (d). Fig. 23(c) again shows the zero real power flow to inverter B. VIII. C ONCLUSION This paper presents a three-phase four-wire grid-interfacing power quality compensator for compensating the two most common voltage quality problems, namely voltage unbalance and voltage sag, in a microgrid. During grid voltage unbalance, the proposed compensator, using a shunt and a series fourphase-leg inverter, can enhance both the quality of power within the microgrid and the quality of currents flowing between the microgrid and utility system. Functionally, the shunt four-leg inverter is controlled to maintain a set of balanced distortionfree voltages within the microgrid and to regulate power sharing among the parallel-connected distributed generation (DG) systems. To complement, the series four-leg inverter is controlled to inject negative- and zero-sequence voltages in series to

[1] M. Prodanovic and T. C. Green, “Control and filter design of three-phase inverters for high power quality grid connection,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 373–380, Jan. 2003. [2] A. Ghosh and G. Ledwich, Power Quality Enhancement Using Custom Power Devices. Boston, MA: Kluwer, 2002. [3] Y. W. Li, D. M. Vilathgamuwa, and P. C. Loh, “Design, analysis and realtime testing of controllers for multi-bus micro-grid system,” IEEE Trans. Power Electron., vol. 19, no. 5, pp. 1195–1204, Sep. 2004. [4] M. J. Ryan, R. W. De Doncker, and R. D. Lorenz, “Decoupled control of a four-leg inverter via a new 4 × 4 transformation matrix,” IEEE Trans. Power Electron., vol. 16, no. 5, pp. 694–701, Sep. 2001. [5] C. B. Jacobina, M. B. de R. Correa, T. M. Oliveiro, A. M. N. Lima, and E. R. C. da Silva, “Current control of unbalanced electrical systems,” IEEE Trans. Ind. Electron., vol. 48, no. 3, pp. 517–525, Jun. 2001. [6] D. N. Zmood, D. G. Holmes, and G. H. Bode, “Frequency-domain analysis of three-phase linear current regulators,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 601–610, Mar./Apr. 2001. [7] P. Heine, A. Lehtonen, and E. Lakervi, “Voltage sag analysis taken into account in distribution network design,” in Proc. IEEE Power Tech. Conf., Porto, Portugal, 2001. [8] H. Awad and J. Svensson, “Compensation of unbalanced voltage dips using vector-controlled static series compensator with LC-filter,” in Conf. Record IEEE Industry Applications Society (IAS) Annu. Meeting, Pittsburgh, PA, 2002, pp. 904–910. [9] H. Funato, T. Ishikawa, and K. Kamiyama, “Transient response of three phase variable inductance realized by variable active-passive reactance (VAPAR),” in Proc. IEEE Applied Power Electronics Conf. (APEC), Anaheim, CA, 2001, vol. 2, pp. 1281–1286. [10] H. Funato, K. Kamiyama, and A. Kawamura, “Transient performance of power circuit including virtual inductance realized by fully digital controlled variable active-passive reactance (VAPAR),” in Proc. IEEE Power Electronics Specialists Conf. (PESC), Galway, Ireland, 2000, vol. 3, pp. 1195–1200. [11] N. M. Abdel-Rahim and J. E. Quaicoe, “Analysis and design of a multiple feedback loop control strategy for single-phase voltage-source UPS inverters,” IEEE Trans. Power Electron., vol. 11, no. 4, pp. 532–541, Jul. 1996.


Yunwei Li (S’04) received the B.Eng. degree in electrical engineering from Tianjin University, Tianjin, China, in 2002. He is currently working toward the Ph.D. degree in the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. From February to July 2005, he was with the Institute of Energy Technology, Aalborg University, Aalborg, Denmark, as a Visiting Scholar. Mr. Li is a member of the IEEE Industry Applications Society (IAS).

D. Mahinda Vilathgamuwa (S’90–M’93–SM’99) received the B.Sc. and Ph.D. degrees in electrical engineering from the University of Moratuwa, Katubedda Moratuwa, Sri Lanka, and Cambridge University, Cambridge, U.K., in 1985 and 1993, respectively. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, in 1993, as a Lecturer, where he is now an Associate Professor. His research interests are power electronic converters, electrical drives, and power quality. He has published more than 80 research papers in refereed journals and conference proceedings. Dr. Vilathgamuwa is the Co-Chairman of The Power Electronics and Drives Systems Conference 2005 (PEDS05).

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Poh Chiang Loh (S’01–M’03) received the B.Eng. (Hons.) and M.Eng. degrees from the National University of Singapore, Singapore, in 1998 and 2000, respectively, and the Ph.D. degree from Monash University, Monash, Australia, in 2002, all in electrical engineering. During the summer of 2001, he was a Visiting Scholar at the Wisconsin Electric Machine and Power Electronics Consortium, University of Wisconsin, Madison, where he worked on the synchronized implementation of cascaded multilevel inverters and reduced common-mode carrier-based and hysteresis control strategies for multilevel inverters. From 2002 to 2003, he was a Project Engineer at the Defence Science and Technology Agency, Singapore, managing major defense infrastructure projects and exploring new technology for intelligent defense applications. Since 2003, he has been an Assistant Professor at Nanyang Technological University, Singapore.

Microgrid Power Quality Enhancement Using a Three-Phase Four-Wire Grid-Interfacing Compensator.pdf

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