SaberRD Electrical Lab Guide v1.7

Lab 1

1

Time Domain Analysis

Learning Objectives During this lab, you will perform a time domain analysis on an RLC filter to determine its transient response to a pulse input. After completing this lab, you should be able to: • Perform a time domain analysis • Turn simulation data into useful information by plotting waveforms and applying measurements to them

Lab Duration: 15 minutes

Time Domain Analysis Synopsys SaberRD Electrical Workshop

Lab 1-1

Lab

1

Instructions Task 1. 1.

Invoke SaberRD and Open the RLC Design Open SaberRD by selecting Start>Programs>Synopsys> SaberRD “version”>SaberRD

Note that SaberRD initially comes up with the “Start Page” that provides easy access to things like Recent Designs, Design Examples, Documentation, and Help resources.

2.

Click the SaberRD button

for access to the file menu. Choose:

Open > Open Design.

3.

Navigate to the install directory for the labs and go to the directory SaberRD_Training_Labs/Lab01. Open the file ex_rlc.ai_dsn.

The RLC schematic appears:

Task 2.

Lab 1-2

Run a Time-Domain Analysis

1.

Switch to the Simulate tab controls.

2.

If needed, change the simulation type to Transient

for access to the simulation


Lab 1

3.

Fill in the other fields with the following values:

End = 10m

# Run the simulation for 10ms

Step = 0.1u

# Set the initial time step to 0.1us

The quick simulation bar should now look like this:

4.

Hit the green “go” button.

Task 3.

View the waveforms for vin and vout

When the simulation completes, you’ll notice that the window where the Design Browser was on the left has now changed. You should now see a Results window in its place. You can toggle which one you’re viewing with the tabs along the bottom of this pane. Let’s plot the signals of interest, the stimulus, vin, and the output, vout. 1.

In the Results pane, if needed click the plus sign next to ex_rlc to expand all of the signals available for plotting.

2.

Double-click on the signal vout to plot its waveform.

3.

Double-click on the signal vin to plot its waveform.


Lab 1-3

Lab

1

This will place the two signals in separate graphs. You can combine them into the same graph for easier comparison. 4.

In the graph window you will notice the signal vin label to the right of the graph. Left-click on this signal and drag it down to the graph area for the vout signal. This should sumperimpose the two signals onto the same graph.

As can be seen, the filter is under-damped, and causes the output signal to overshoot the input signal. Since overshoot in a circuit can be a problem, use the Measure tool to find out how large the overshoot is.

Task 4.

Lab 1-4

Perform Measurement on vout

1.

Switch to the Analyze tab

2.

In the graph window, select the vout signal.

3.

Click on the apply measures button measurement tool.

to access the data analysis controls.

to bring up the


Lab 1

4.

In the measurement tool, left-click the button next to Measurement and select: Time Domain > Overshoot

from the drop down menu. 5.

Click Apply:

Question 1.

What is the overshoot measurement on the vout signal? ___________


Lab 1-5

Lab

1

Task 5.

Add a Probe to View Results on the Schematic

Often it is useful to be able to view results right on the schematic itself. SaberRD allows you to do this via “Probes.” You will add a probe to view the results on vout in this task. 1.

In the center/main window, toggle back to the schematic view using the tabs along the top of that area:

2.

Select the wire/net which is labeled vout. It should turn light green when selected.

3.

Keep your mouse overtop of the wire/net and right click for the contextsensitive pop-up menu and select “Probe”

4.

If you need to zoom in and out, you can do so via the zoom buttons within the View tab, the Zoom controls in the bottom right corner,

or you can hold down the Ctrl-key on the keyboard and use the mouse scroll wheel to zoom in and out.

This additional method of results analysis allows us to probe around a schematic and get a good feel for how a circuit is behaving. You can probe other wires/nets in the schematic simply by dragging the Probe arrow with your mouse and placing it on the desired wire/net.

Lab 1-6


Lab 1

Task 6.

Close out Lab #1

1.

Access the file menu from the SaberRD button and select Close > Close Design. It is not necessary to save the schematic.

2.

Leave SaberRD open.

Please let your instructor know when you have completed this lab.


Lab 1-7

Lab

1

Answers / Solutions Task 3.


Question 1.

Lab 1-8

overshoot = 0.262 V


Lab 2

2

Finding Parts and Creating Schematics

Learning Objectives During this lab, you will finish a schematic of a differential amplifier After completing this lab, you should be able to: • Find parts in the SaberRD parts library • Create schematics and wire components together • Parameterize components to match your design needs


Finding Parts and Creating Schematics Synopsys SaberRD Electrical Workshop

Lab 2-1

Lab

2

Background Finding the models you need in order to complete simulation is one of the key enablers to the vast benefits of simulation or virtual prototyping. One of SaberRD’s biggest advantages is its flexibility for using, creating, and providing models. The library of multi-domain behavioral models in SaberRD is one of the largest in the industry. In later labs, you will look at ways for reading-in existing models and intuitive ways to create models on your own. In this lab, you will concentrate on finding parts in the SaberRD model library. It is also important to note that models fall into two classifications: generic models and components. A generic model describes some behavior and must be parameterized by the user in order to meet the desired specification (e.g. a linear resistor requires the user to specify its resistance). A component represents the behavior of a specific part and has been characterized according to measurements or manufacturer’s data (e.g. a 2N2222 bipolar transistor). The SaberRD library has thousands of models in both classifications.

Lab 2-2


Lab 2


Open the Design and Add Parts Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab02. Open the file diffamp.ai_dsn.

An unfinished DiffAmp schematic appears:

You will be adding an op-amp, resistor, and ground in the area highlighted to complete the schematic.


Lab 2-3

Lab

2

3.

Lab 2-4

Display the SaberRD Parts Library by selecting the Parts tab in the bottom left corner of SaberRD.


Lab 2

4.

Add the required op-amp: a.

At the top of the Parts pane, select the Search tab.

b.

Select (click on) components.

c.

Fill in the search box with lm324 and hit Enter.

d.

Select from Available Parts: lm324_1 (lower in the list). Double-click on this entry to Place the Part into the schematic.


Lab 2-5

Lab

2

e.

5.

Lab 2-6

Left-click/hold on the part and drag it into place as shown in the zoomed-in picture below. SaberRD will complete the connections for you.

Next, let’s browse the library to find a resistor and wire it into the schematic: a.

Hit the Browse tab at the top next to the Search tab to go back to the browsing pane.

b.

Make sure “Generic Parts” is selected (ie the radio button is switched back to “Generic Parts.”)

c.

Expand the Category “Electronic.”

d.

Expand the sub-category “Passive Elements.”


Lab 2

e.

Scroll down to find the vertical Resistor (|)

f.

Doubleclick the Resistor (|) part to place on schematic.


Lab 2-7

Lab

2

6.

Lab 2-8

g.

Drag and drop it into place, approximately as shown below.

h.

Hover over the small box (port) that represents the + terminal of the op-amp (‘inp’) and when it highlights red, left-click once to start a wire connection.

i.

Drag to route the wire to the ‘p’ port (top port) of the resistor and click to complete the connection— SaberRD will automatically take care of the bend required to complete the route.

Finally let’s add the ground.

a.

Return to the search tab.

b.

Switch to “Generic Parts” tab, if needed, and search using the term, “ground.”

c.

Select the item labelled “Ground” and double-click to place it in the schematic.


Lab 2

Task 2.

d.

Drag and drop the ground symbol such that the top of the ground lines up and connects with the bottom of the resistor as shown below.

e.

Drag and drop the ground slightly lower in the schematic and SaberRD will automatically fill in the wire/net to maintain the connection.

Parameterize the Components and Save

Now that these parts are in place, we need to fill in the proper parameter values.

1.

Parameterize the op-amp.

a.


Select the op-amp. It will highlight green when selected.

Lab 2-9

Lab

2

Lab 2-10

b.

Notice that the Property Editor pane on the right will switch to displaying all of the properties of the lm324.

c.

Change the reference designator, or ref property to a value of u1.

d.

In the Attributes Editor pane below, change the visibility of the ref property to “value.” (This will display only the value of the property and not both the property name and value).


Lab 2

2.

Repeat this process to parameterize the resistor.

ref = r2

# Reference designator r2

visibility = value rnom = normal(10k,0.1)

#10k resistor, +/- 10%

visibiltiy = value

The finished schematic should look like the following:

3.

Save your completed schematic. You can either use the file menu from the SaberRD button or use the Save icon

Task 3. 1.

right next to it.

Close out Lab #2 Close the design from the SaberRD button:

Close > Close Design 2.

Leave SaberRD open.


Lab 2-11

Lab 3

Small-Signal Frequency Analysis

3

Learning Objectives During this lab, you will perform a small-signal frequency analysis on the RLC filter to determine its gain as a function of frequency. After completing this lab, you should be able to:

• Perform a small-signal frequency analysis • Perform frequency domain measurements on results • Enable looping to see the effect of sweeping a parameter.


Small Signal AC Analysis Synopsys SaberRD Electrical Workshop

Lab 3-1

Lab 3

Instructions For this lab we will be using an RLC filter as before.

Note that as the labs progress, some of the instructions will become abbreviated for instructions which have already been covered more explicitly in previous labs.

Task 1.

1.

Perform Small-signal Frequency Analysis



Open > Open Design.

2.

Navigate to the install directory for the labs and go to the directory SaberRD_Training_Labs/Lab03. Open the file ex_rlc.ai_dsn .

3.


4.

Change the simulation type to Small-Signal Frequency analysis.

5.

Set the frequency range over which the circuit is to be swept as indicated below:


Begin = 1

# Start frequency

End = 100k

# End frequency


6.

Lab 3-2

Click the green go button.

Small Signal AC Analysi Synopsys SaberRD Electrical Workshop

Lab 3

Task 2. 1.

Perform Measurement on vout When the simulation completes, the results window will display on the left side of SaberRD. If needed, expand the “ex_rlc” hierarchy. Double click on the vout signal to plot it.


Lab 3-3

Lab 3

Next you will make a measurement. Suppose you were interested in the bandwidth of the filter. A typical measurement of bandwidth for a lowpass filter such as this would be a -3dB measurement. This measurement indicates at what frequency the gain falls to -3dB (or where the output voltage falls to 0.707 of the input voltage).

2.

Switch to the Analyze tab controls.

3.

In the graph window, select the dB(vout) signal.

4.


5.

Left-click the button next to Measurement and select

to access the data analysis

to bring up the

Frequency Domain > Lowpass (3dB Point)

6.

Click Apply and then Close (or the x in the upper right corner of the measurement window) to close the measurement tool.

The measurement is applied in the waveform window. Question 1.

7.

Lab 3-4

What is the -3dB bandwidth? _________________

Close this graph window by left-clicking the x in the right corner of this pane:


Lab 3

Task 3.

Examine the Effect of Varying the Capacitor

For this filter design, it would be useful to know how the -3dB point changes with respect to the capacitance of c1. In this task, you will sweep the value of capacitance, simulate the response, and measure the -3dB point for each iteration.

1.


2.

From the simualtion controls, change the Looping control to


Parameter Sweep

3.

Toward the right you’ll see the box labaled “Param.” Click the ‘Browse’ button on the right side of the field that shows up with three dots:

4.

This will bring up a list of all the parameters available for sweeping. Expand ex_rlc and then c.c1 by clicking on the +. Click on “c” to select the value c for c.c1:

5.

Click OK.


Lab 3-5

Lab 3

6.

Fill in the details of the parameter sweep:

Start = 0.1u

# Start at 0.1uF

End = 1u

# End at 1uF

By = 0.1u

# increment in even steps of 0.1uF


7.

Click the green “go” button.

8.

When the results pane displays on the left, double-click on vout again to plot it. This time you should see a multi-membered waveform:

Now let’s see more specifically how the changing capacitance value affects the 3dB point for this design.

9.

Lab 3-6




Lab 3

10.

In the graph window, select the dB(vout) signal.

11.


12.


to bring up the

Frequency Domain > Lowpass (3dB Point)

13.

Click Apply and then Close.

This time you get a new graph showing the multiple values of the the -3dB point. Question 2.

How does increasing capacitance affect the -3dB point of this filter? _______________________________________________________

Task 4. 1.

Close out Lab #3 Close the design from the SaberRD button: Close > Close Design

2.

Leave SaberRD open.


Lab 3-7

Lab 3



Question 1.

Task 5.

Examine the Effect of Varying the Capacitor

Question 2.

Lab 3-8

The -3dB bandwidth is 1.47kHz.

Increasing the capacitance decreases the -3dB point of the filter.


Lab 4

4

Operating Point Analysis

Learning Objectives During this lab, you will gain some basic familiarity with an Operating Point analysis. After completing this lab, you should be able to: • Run an Operating Point analysis • Interpret an Operating Point report


Operating Point Analysis Synopsys SaberRD Electrical Workshop

Lab 4-1

Lab 4

Instructions Your goal is: •

Run an Operating Point analysis on a simple RLC circuit.

•

Make changes to the RLC circuit and see how that affects the operating point.

Task 1.

1.

Invoke SaberRD and Open the RLC Design



Open > Open Design.

2.

Navigate to the install directory for the labs and go to the directory SaberRD_Training_Labs/Lab04. Open the file ex_rlc.ai_dsn .

The RLC schematic appears:

This is a simple design but the Design Browser can be a very useful tool for navigating through design hierarchy and selecting and manipulating various parts of a design. The Design Browser is located on the left-hand side of the SaberRD window.

Lab 4-2


Lab 4

3.

Expand the ex_rlc design to list all of the components that comprise it.

This provides a means of viewing all of the contents of a design so it is good to become familiar with this feature.

Task 2.

Perform an Operating Point Analysis

One of the goals of SaberRD is to make it quick and easy to go from start to results. And, one of the more basic but important analyses to run is an Operating Point Analysis which provides an understanding of the steady state or dc response of a design.

1.


2.

Change the simulation type to Operating Point in the top-left corner of the Simulate ribbon.


We’ll stick with the default settings for the Operating Point analysis making the simulation run very straightforward.

3.



Lab 4-3

Lab 4

At this point, it is good to become familiar with the transcript window at the bottom of SaberRD. You might even want to expand the window so that you can see the progress of the underlying simulation steps. If there are warning or error messages during the simulation, this is also where they will be reported .

When the simulation completes, an Initial Point Report is displayed.

Note that all of the displayed values are zero. To find out if this is correct, look at the initial value of the voltage source that drives the filter. 4.

In the center/main window, toggle back to the schematic view using the tabs along the top of that area:

The schematic shows that the voltage source has an initial value of 0 and a pulse value of 1. This means that the source will supply zero volts at time = 0. So the results are correct. To get non-zero values for a DC analysis, you can change the initial value of the source. For example, you could change the initial value to 1V, and the pulse value to 0V. This way, you invert the previous waveform.

Lab 4-4


Lab 4

Task 3.

Change Input Voltage and Re-run Analysis

Let’s invert that pulse source such that its initial value is 1 to see how that affects our Operating Point analysis.

1.

Change the initial value of the voltage source as described below:

a.

Select the voltage source symbol in the schematic. It should highlight green.

b.

In the properties pane on the right of SaberRD, left click in the area to the right of the initial property. Change the value from 0 to 1.

c.

Left click in the area to the right of the pulse property. Change the value from 1 to 0.

The values of initial and pulse in the properties pane should now look like this:

You should also notice that the values being displayed next to the source in the schematic changed.

2.

Re-run the analysis by hitting the green “go” button again.

3.

Look at the results in the new Initial Point Report.


Lab 4-5

Lab 4

Question 1.

Task 4.

Lab 4-6

What is the new voltage on vout? _____________ Does this value make sense to you? Why or why not?

Close Out Lab #4

1.

Access the file menu from the SaberRD button and select Close > Close Design and when prompted, do NOT save the schematic.

2.

Leave SaberRD open.


Lab 4



Question 1.

vout = 0.9091 V

At its steady-state, the RLC circuit behaves as a simple resistor voltage divider with the voltage at vout calculated as:

‫= ݐݑ݋ݒ‬

‫ݎ‬2 1݇ߗ ∗ ‫= ݊݅ݒ‬ ∗ 1ܸ = 0.9091ܸ ‫ݎ‬1 + ‫ݎ‬2 100ߗ + 1݇ߗ


Lab 4-7

Lab 5

5

DC Sweep

Learning Objectives In this lab exercise, you will perform a DC Sweep Analysis on a Loudspeaker Design. After completing this lab, you should be able to: • Run a DC Sweep to see the effect of sweeping a parameter across a range. • Graph the dc transfer function of a design.


Operating Point with Looping Synopsys SaberRD Electrical Workshop

Lab 5-1

Lab

5

Background The goal of this exercise is to sweep the loudspeaker with a variable-amplitude input voltage, record the displacement of the speaker diaphragm, and plot this displacement as a function of the input voltage. In other words, this will generate a transfer function for the loudspeaker. This is a great example of SaberRD’s ability to handle multiple physical domains in a single simulation. In this example, we’ll have an electrical input and a mechanical output, with a voice coil to perform the work of converting the electrical energy into mechanical energy.

You will not need to know this for the lab, but just for your information, here are the straightforward equations underlying this model of a voice coil in a behavioral language (openMAST). Even without knowledge of this language, it is fairly evident how the physics equations represent the behavior: i(p->m) += i frc_N(pos1->pos2) += force i: v(p)-v(m) = r*i + d_by_dt(l*i) + v_bemf vel: vel = d_by_dt(posn)

Lab 5-2


Lab 5


Open the Loudspeaker Design and Perform Operating Point Analysis Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab05. Open the file ex_lspkr.ai_dsn.

The loudspeaker schematic will appear as shown:

3.

Perform an Operating Point Analysis. a.

Switch to the Simulate tab to the simulation controls.

b.

Change the simulation type to Operating Point

for access

in the top-left corner of the Simulate ribbon. c.



Lab 5-3

Lab

5

You should see an Initial Point Report with the following results:

Task 2.

Find the Transfer Function

1.

Switch back to the Simulate tab simulation controls.

2.

Change the simulation type to DC Sweep the top-left corner of the Simulate ribbon.

3.

Toward the right you’ll see the box labeled “Source” Click the

for access to the

in

‘browse’ button on the right side of the field:

Lab 5-4

4.

This will bring up a list of the sources available for sweeping. Expand the ex_lspkr entry. Select the entry v_pulse.vin:

5.

Click OK.


Lab 5

6.

Fill in the following values for the v_pulse.vin initial value:

Start = -30

# Start at -30V

End = 30

# End at 30V


7. 8.

Click the green “go” button on the quick simulation bar. When the results pane displays on the left double click on the signal diaphragm to display the result.

The resulting graph of the loudspeaker displacement gives you a good idea of the transfer function of this design. It looks like the position of the speaker diaphragm follows the input voltage fairly well, although there appears to be some non-linearity which could be investigated subsequently. Question 1.

Task 3. 1.

How does the voltage affect the position of the loudspeaker diaphragm?

Close out Lab #5 Close the design from the SaberRD button:


Lab 5-5

Lab

5

Close > Close Design

2.

Lab 5-6

Leave SaberRD open.


Lab 5



Question 1.


The larger the magnitude of the voltage, the farther the loud speaker diaphragm is from 0mm (the resting point).

Lab 5-7

Lab 6

pl

6

FFT

Learning Objectives In this lab exercise, you will perform a FFT analysis using the Waveform Calculator and examine the results. After completing this lab, you should be able to:

• Use FFT in the Waveform Calculator


FFT Synopsys SaberRD Electrical Workshop

Lab 6-1

Lab 6

Background This lab is designed to illustrate the difference between a Small-Signal AC analysis (which is run at an operating point, on a linearized system), and an FFT, which can be used to show non-linear effects in the frequency domain. In this lab exercise you will first perform a Small-signal AC analysis on the Loudspeaker portion of an Audio Test System. The next step is to run a Transient analysis and then a Fast Fourier Transform (FFT) analysis on the results from transient. You can then compare the FFT results to the Small-signal AC analysis. The observed difference could be assumed to be due to the nonlinearities in the system. The final step is a verification which requires removing the nonlinearities and then re-running the analysis.

Lab 6-2


Lab 6


Open the Loudspeaker Design Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab06. Open the file ex_lspkr.ai_dsn.

The loadspeaker schematic will appear as shown.

Task 2.

Add AC Parameters to the Source

The first analysis you will run will be a Small-Signal AC analysis. To run this analysis, the input source must be defined properly. You will do this in the following steps. 1.

Select the voltage source v_pulse.vin.


Lab 6-3

Lab 6

2.

Change the property ac_mag from 1 to 2.

You are setting the amplitude of the AC source to 2 since you are going to compare the results of this analysis to the FFT results. In FFT, the results are displayed as the sum of positive and negative frequency components. These components are equal for physical systems which means the FFT results are twice the expected single-sided values.

Task 3.

Run Small-Signal AC Analysis

Run a Small-Signal AC analysis to observe the loudspeaker’s behavior in the frequency domain. 1.


2.

Change the simulation type to Small-Signal Frequency analysis.


Lab 6-4


Lab 6

3.

Set the frequency range over which the circuit is to be swept as indicated below:

Begin = 1

# Start frequency

End = 1k

# End frequency

We are going to want to compare these results to the FFT results. Therefore, we need to make the results align and will need to change the number of points in the sweep range to 1024. You can do this with the advanced controls. 4.

You can do this by clicking on the “Advanced” controls tab in the Quick Simulation group:


Lab 6-5

Lab 6

5.

In the Advanced Simulation controls window, switch to the Small Signal AC tab if needed and modify the Number of Points field to 1024 as shown below:

6.

Click close on this window and then click the green go button.

7.

Plot the signal diaphragm.

Task 4.

Perform Time-Domain Analysis

You will next perform an FFT on time domain analysis results, and compare these results to the Small-Signal Frequency Response results you just generated. 1.

Change the simulation type to Transient analysis.

Lab 6-6


Lab 6

2.

Fill in the fields with the following values: End = 1

# Run for 1s

Step = 100n

# Initial step 100n

We will also need to change one accuracy setting in the Advanced Controls. We will be changing the Truncation Error. Truncation Error = 10u

3.

# Increase accuracy

You can do this by clicking on the “Advanced” controls tab in the Quick Simulation group:

4.

In the Advanced Simulation controls window, switch to the Transient if needed and modify the Truncation Error field to 10u as shown below:


Lab 6-7

Lab 6

Note:

You might be wondering why we need to change the truncation error. If all we were doing was looking at the waveforms for the transient analysis, this would not be necessary. Changes to the transient waveforms from this accuracy change would probably not be perceptible. However, we will soon be making an FFT transformation on this result. Keep in mind that this is numerical simulation. Reducing the truncation error will tighten up the accuracy of the transient simulation such that subsequent transformations such as FFT are better as well.

5.

Click Close on the Advanced Simulation controls tab and click the green go button.

6.

View the signals vin and diaphragm from the transient analysis plot file. Note that the input signal is a 4KV pulse, and the output shows a damped sinusoid.

Task 5.

Perform FFT Analysis

Next you will perform a Fourier transform on the signals you just observed. 1.

Switch to the Analyze tab Calculator.

2.

Click on the Waveform Calculator button

3.

Select the signal ‘diaphragm’ and use the middle mouse button to paste it into the Waveform Calculator. The Waveform Calculator should appear as shown below.

for access to the Waveform

Lab 6-8


Lab 6

4.

In the Waveform Calculator select Wave

, then FFT.

The form to perform a fast fourier transform should appear. 5.

Set Time Increment to log. The form should apprear as below.

6.

Click OK on the FFT form. The calculator should now show an fft transform on the diaphragm signal.

7.

Plot the results by clicking the ”Graph X” icon

8.

Observe the resulting waveform.

9.

Remove the transient versions of the vin and diaphragm signals that you plotted in Task 4. Left click to select them and then right click to delete.


Lab 6-9

Lab 6

Configure the X-axis to view from 10Hz to 1KHz. 10.

At the bottom of the graph, select the x-axis as it highlights red. The properties for the x-axis should now show on the Properties pane. Change the minimum and maximum values as shown below:

Note that it looks somewhat similar to the Small-Signal AC response you ran previously, but the waveform is much less ideal. This is due to the non-linear elements in the loudspeaker.

Lab 6-10


Lab 6

Task 6.

Linearize the System and Re-run Analysis

To verify that the differences in the frequency response curves are due to loudspeaker nonlinearities, you will now remove the nonlinearities from the loudspeaker and then re-run the FFT. The models for the spring and the wind drag include coefficients to represent non-linear behavior. We’ll set those to 0. 1.

Return to the schematic window for the loudspeaker design.

2.

Select the spring symbol (spring_nl.susp). Change the property k3 to 0.

3.

Select the wind drag symbol (windrag.air). Change the property w to 0.

4.

Re-run the transient analysis as you did earlier (keep the same settings).

Re-run the FFT analysis using the waveform calculator as you did earlier. 5.

Plot the signal diaphragm.

6.

Bring up the waveform calculator and delete the old entry by clicking on the

7.

button.

Select the signal ‘diaphragm’ and use the middle mouse button to paste it into the Waveform Calculator. The Waveform Calculator should appear as shown below.


Lab 6-11

Lab 6

8.

In the Waveform Calculator select Wave

, then FFT.

The form to perform a fast fourier transform should appear. 9.

Set Time Increment to log. The form should apprear as below.

10.

Click OK on the FFT form. The calculator should now show an fft transform on the diaphragm signal.

11.

Plot the results by clicking the ”Graph X” icon

12.

Observe the resulting waveform.

Lab 6-12


Lab 6

13.

Remove the transient version of the diaphragm signal: left click to select and then right click to delete.

14.

Compare the results of this FFT analysis to the original Small-Signal AC analysis. The waveforms should be nearly identical (you may need to adjust the default Y-Axes to show how well they match).

Task 7. 1.


2.

Leave SaberRD open.


Lab 6-13

Lab 7

Mixed-Signal Analysis

7

Learning Objectives In this lab exercise, you will run a simulation on a design with both analog and digital components. After completing this lab, you should be able to:

• Plot signals from both the analog and digital domain. • Describe the concept of hypermodels and why they are needed in a mixed-signal simulation environment.


Mixed Signal Analysis Synopsys SaberRD Electrical Workshop

Lab 7-1

Lab 7

Background

This exercise will use the above circuit to show how SaberRD can simulate a mixed-signal design. Digital parts include the 4-bit counter in the middle of the schematic and the inverter on the enable pin. Analog content makes up the rest of the circuit.

Lab 7-2


Lab 7


Run a Time domain Analysis Click the SaberRD button for access to the file menu and choose: Open > Open Design

2.

Navigate to the directory SaberRD_Training_Labs/Lab07. Open the file mm_lab.ai_dsn.

3.

Run a time domain (Transient) analysis with the following settings: End = 32u

# Run the simulation for 32us

Step = 1u

# Set the initial time step to 1u

As usual, the Results pane will appear on the left when the simulation completes. Notice that this time, it lists both analog and digital signals for plotting.


Lab 7-3

Lab 7

4.

Examine the digital signals

under mm_lab.

Note that some digital nodes have been created that are not a part of the original schematic, notably: d0_counter_q0 through d3_counter_q3. 5.

Examine the analog signals under mm_lab.

6.

Plot the analog signal d0.

7.

Plot the digital signal d0_counter_q0.

What you are seeing is that digital-to-analog hypermodels were inserted “underthe-hood” in SaberRD to separate the digital pins (d0-d3) and the analog resistors to which they connect. The nets on the digital side of these hypermodels were renamed to d0_counter_q0, d1_counter_q1, etc. The nets on the analog side of the hypermodels kept the original net names (d0-d3).

Lab 7-4


Lab 7

8.

Select and delete d0 from the graph, but keep signal d0_counter_q0.

9.

Plot the following signals: d1_counter_q1 d2_counter_q2 d3_counter_q3 clock sumx2 clock_counter_clkup

10.

Drag the signal sumx2 to on top of the clock signal.

Your Graph window should now look like this:

Note the step function shown by sumx2. Also note that when clock spends too much time in the “x region” (>15ns between 1.8V and 3.2V) clock_counter_clkup = x. We will not do so here, but you could further investigate and correct this design to eliminate this issue. 11.

Try zooming and measuring around in this window as you have learned previously to gain an understanding of the signal relationships.

Task 2. 1.


2.

Leave SaberRD open.


Lab 7-5

Lab 8

Design Optimization

8

Learning Objectives In this lab, you will use design optimization to design a bandpass filter After completing this lab, you should be able to: • Find the stochastic parameters from a design • Set up an optimization task in the WCA tool • Define a target characteristic from a digitized plot • Export the results of an optimization back to the simulator or schematic

• If you are using the SaberRD Student Edition for the training, skip this entire lab. Optimization is not enabled in the Student Edition.


Design Optimization Synopsys SaberRD Electrical Workshop

Lab 8-1

Lab 8

Background This lab will demonstrate how the SaberRD WCA tool can be applied to the synthesis of a band-pass filter. The L's and C's of a passive network (12 parameters in all) are optimized so its impedance matches a filter of passband [100Hz, 200Hz]. In particular, you will be shown how to extract the stochastic parameters from a design, how to set up an optimization task in the WCA tool, how to define a target characteristic from a digitized plot, and how to export the results of an optimization back to the simulator or schematic.

Lab 8-2


Lab 8


Open the bandpass filter & WCA tool Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab08. Open the file bandpass.ai_dsn.

3.

The following schematic should appear, which represents a bandpass filter:

The schematic "bandpass" shows the topology of the filter to optimize. The values of the capacitances and inductances are defined as distribution functions in the "Saber Include" symbol instance (e.g. uniform(0.1,0.01,0.5)). These stochastic definitions are typically used for Monte Carlo analyses. Let's assume we want to reuse the same range as the Monte Carlo distributions for our optimization task. 4.

Task 2.

In the Analyze tab, click the Worst-Case Analysis icon to open the WCA tool.

Extract the stochastic parameters

The WCA tool allows you to extract the parameters defined in the design with a stochastic distribution. This avoids duplicating the effort of defining parameter variability information in the WCA tool when this information is already defined in the design schematic.


Lab 8-3

Lab 8

1.

In the WCA tool, click on the icon that looks like a die

2.

Click the button Extract and the WCA tool will automatically identify the parameters which have tolerances associated.

The procedure takes around one minute to complete. A dozen parameters get identified. 3.

Click Append to add these parameters to the exisiting list of parameters (in this case, it was empty).

The parameter table is now populated with the parameters’ current values and domain information. You might want to expand the WCA tool window to ensure that you can see the whole list of parameters. The capacitances have a current value of 10uF and are defined over a continuous range between 1uF and 100uF. The inductances have a current value of 0.1H and are defined over a continuous range between 0.01H and 0.5H. Note that the table allows parameters to be fixed to their current values so they do not participate in a search (we will not use this feature in this lab). In this particular flat filter design, the stochastic parameters happen to be defined in a top-level "Saber Include" instance. But if you are dealing with a hierarchical design, nothing prevents you from defining your parameter distributions at any

Lab 8-4


Lab 8

level of the hierarchy (directly as model arguments or in a "Saber Include"). The extraction procedure will work as well.

Task 3.

Setup the optimization test

Now that we have defined the domain of the search, we need to define the objective of the optimization. The goal is to minimize the difference between the simulated Bode plot of the filter and a target one. The Bode plot of the impedance is obtained by running an ac analysis and plotting the voltage at node "out". 1.

Let's now define the simulation sequence. Add a dc analysis first by clicking the menu item "Analyses" and then "DC Operating Point".

2.

Retain the default settings of the DC analysis. Click OK.

3.

In the same manner, add a Small Signal AC analysis. Set the start frequency to 20. Set the end frequency to 500. Click OK.


Lab 8-5

Lab 8

The next step is to define the objective. The target waveform needs to be made available to the WCA tool from a plotfile. Assuming that the target characteristic is available as an image from vendor datasheets or a lab instrument, the Scanned Data Utility can be used to import the image, create digitized curves, and export the curves into a plotfile. A target characteristic defined in an ASCII file can also be loaded in the Scanned Data Utility and exported the same way into a plotfile. This step has been completed for you and a file named target.ai_pl included in the lab directory. Here is what this would look like in the Scanned Data Utility.

Let's now define a measure of waveform difference that references the waveform in the plotfile target.ai_pl.

Lab 8-6


Lab 8

4.

Click “New...” in the “Measures” menu.

5.

Set the name of the measure to " diff".

6.

Set the Waveform to “ out" by browsing the signal hierarchy. Click the down arrow to the right of the Waveform entry, select “Signals…”, expand “bandpass” and scroll down to select the signal “ out”. Click OK.


Lab 8-7

Lab 8

7.

Set Measurement to " Waveform Difference".

8.

Set Plotfile to "target.ai_pl" by using the file browser (select the down arrow to the right of the Waveform entry and select “Browse...”)

9.

Enter "mag" as the target waveform.

10.

Keep L1 as error function and Y as the Direction.

11.

Select "Magnitude" for the Y Transform option on the Optional tab.

12.

Click OK.

You may have noticed that a selection of error functions is available. For waveforms with a large dynamic range, the logarithmic error functions are preferred. Please refer to the WCA documentation for ampler information on the error functions. We set the Y transform option to "Magnitude" in order to compare the magnitude of the complex waveform produced by simulation to the real-valued target waveform. Now that we have defined a measure "diff", the next step is to define an objective seeking to minimize this measure. In other words, we want to produce simulation results that match the target waveform. Lab 8-8


Lab 8

13.

Right mouse click the measure " diff" and click the menu item Add Objective > Minimize

Allowed forms of objectives are: >

min(expr1)

>

max(expr1)

>

expr1 = expr2

>

expr1 > expr2

>

expr1 < expr2

where expr1 and expr2 are algebraic expressions of measures and/or parameter aliases. The last step before running the optimizer is to define the search algorithms. The search algorithms are evaluated sequentially. Each algorithm takes the best point found by the previous algorithm as starting point. The default algorithm sequence consists of the following list: 1. Variable Neighborhood Search 2. Downhill Simplex 3. Steepest Descent These are typically the most effective algorithms and the ones used in this lab. In order to increase the odds of finding the globally optimal solution, the sequence of algorithms can be evaluated multiple times. Design Optimization Synopsys SaberRD Electrical Workshop

Lab 8-9

Lab 8

14.

Lab 8-10

Set the number of iterations over the algorithm sequence is set by clicking the Algorithms button and the Loops... menu item.


Lab 8

The default number of loops is 1. 15.

Set the number of loops to 2 and click OK.


Lab 8-11

Lab 8

Before we start the search, let's take a look at the progress view (the graph in the bottom right corner). This view shows the values of measures or parameters for the different evaluations of the search. 16.

Select " diff" from the signal menu.

We are now ready to run the optimizer. 17.

Click the icon that looks like gears

to start the search.

The active algorithm becomes highlighted. The execution of the algorithm sequence will require thousands of evaluations and should take between 5 to 20 minutes depending on your computer performance. You can interrupt the execution at any time by clicking the Stop button, which will allow you to directly observe the results up to that point. You can re-click the Run button to start the next algorithm in the sequence. It will take several thousand iterations to find the optimal value but you can hit Stop when you are ready.

Lab 8-12


Lab 8

This process will find the optimal values for the L’s and C’s in the design to best match the bandpass filter response we targeted with the scanned-in waveform.

This might be a good time to grab a cup of coffee to let the optimizer complete all of the iterations. When the optimization completes, you should see values chosen to best match the desired bandpass which look similar to the following:


Lab 8-13

Lab 8

Task 4.

Use the results of optimization

So, how do we use this information? There are many things that we could do subsequently. We could re-run simulations with the new optimal values or create a new schematic with the optimal values and save that for printing or subsequent use. Suppose that we now wanted to check how well we did with our optimization. 1.

From the File > Export > Parameters...

menu item.. Choose New Schematic and click OK.

2.

Save the new schematic with a different name such as “ optimized_bandpass”

3.

You can close the optimizer now to be able to view the new schematic better.

Notice that the new optimized values are now annotated to the schematic. 4.

Lab 8-14

Run a Small-Signal Frequency analysis between 20 and 500 Hz.


Lab 8

5.

Plot the signal out and use the waveform calculator to take the absolute value of db(out) and re-plot that signal.


Lab 8-15

Lab 8

You should see a filter response that is a bandpass filter which approaches the scanned-in image to which we were optimizing.

There is additional optimization refinement that we could do to get our results to match the desired bandpass result even better. This is beyond the scope of this class. However, if you would like to do this on your own, the exercise is included as a tutorial in the WCA tool. In the WCA tool, simply click on the menu item Help > Tutorials > Filter Synthesis

to complete this refinement on your own.

Task 5. 1.


2.

Lab 8-16

Since this is the last lab of the day, close SaberRD.


Lab 9

Modeling: Hierarchical Models & Encryption

9

Learning Objectives In this lab exercise, you will create a hierarchical model and then encrypt it. After completing this lab, you should be able to: • Find parts using Parametric Search. • Automatically create a symbol from a hierarchical schematic. • Instantiate a custom created model. • Encrypt a model.



Lab 9-1

Lab 9

Background It is common in the design flow that you would want to make use of one design simulation as part of a higher level. This hierarchical approach to modeling is very straightforward to accomplish in SaberRD. Further, it is often common to want to share a model with a customer or partner, without exposing the Intellectual Property (IP) contained within. This is also straightforward to accomplish in SaberRD and the benefits of using simulation models as the supply chain communication mechanism can be tremendous. In this lab, we will also get to take advantage of SaberRD’s Parametric Search feature. Here is a summary of the steps that we will follow in the lab in order to create this hierarchical model:

Lab 9-2

1.

Create the sub-circuit that we wish to use as the model.

2.

Add hierarchical ports to the sub-circuit schematic that represent the pins of the device that we want to simulate.

3.

Use SaberRD’s automatic symbol creation feature to create a symbol from a schematic.

4.

Test the new model by instantiating it in a test circuit.

5.

Encrypt the model. a.

Cut-and-paste the text netlist for the sub-circuit into a new file.

b.

Run SaberRD’s encryption tool to automatically encrypt the model.

c.

Edit the symbol to refer to the encrypted text model rather than the hierarchical schematic.


Lab 9


Open the Sub-Circuit Open SaberRD by selecting Start>Programs>Synopsys> SaberRD “version”>SaberRD

2.

Click the SaberRD button for access to the file menu and choose: Open > Open Design.

3.

Navigate to the directory SaberRD_Training_Labs/Lab09. Open the file pwramp.ai_dsn.

The following schematic should appear, which represents our power amplifier, but with a missing component, a BJT.


Lab 9-3

Lab 9

In addition to the Parts Gallery search capability we’ve looked at previously, the parametric search capability can be a powerful tool for finding the parts in SaberRD’s library that you need. 4.

Switch to the Model tab

5.

Select the radio button for Components.

6.

Select the button marked “Parametric Search.”

7.

When the Parametric Search Wizard appears, select the category, BJT:

.

…and click “Next >”

Lab 9-4


Lab 9

8.

Select the tab for “Maximum Ratings,” change two of the search criteria from “>=” to “=” using the drop down arrow to the right as shown below, and fill in the following values Max Ic = 5

# Maximum collector current

Max Vce = 50

# Maximum collector-emitter voltage

…and click Finish.


Lab 9-5

Lab 9

Lab 9-6

9.

When the list of Parametric Search results gets displayed, scroll down and select the q2n718a

10.

Select “Place” and then “Close” the Parametric Search wizard.


Lab 9

11.

Task 2. 1.

Select and move the q2n718a into place such that the connections are automatically completed.

Add hierarchical ports to the sub-circuit In the Parts Search form, under the Model tab, in the top left corner of SaberRD, switch the radio button back to Generic Parts and type in the partial word “ hier” and click on the binocular icon to search:


Lab 9-7

Lab 9

This will help find all of the hierarchical ports in the library. Since the pins on this device are directionless or conserved, we want the analog pin.

Lab 9-8

2.

Select and hold the one labeled, “Hierarchical Analog” and drag-anddrop it on top of the circle for the vsrc net as shown:

3.

Repeat this process for the vload net in the upper right corner of the schematic.


Lab 9

4.

Task 3. 1.

Save your completed schematic.

Automatically create a symbol from schematic Right-click somewhere blank in the schematic canvas and from the context-sensitive menu that pops up choose: Create > Hierarchical Symbol


Lab 9-9

Lab 9

2.

The symbol editor will open and the Symbol Editor Assistant will display. In the Symbol Editor Assistant window, drag-and-drop the vload pin to the right side of the symbol:

3.

Click “Save” (use the default name, pwramp and file extension, ai_sym) then “Close”

4.

If needed, also close the SaberRD Symbol Editor Assistant window.

Task 4. 1.

Test the new model in a test circuit Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab09. Open the file test_pwramp.ai_dsn.

Be sure to open the one with test_ in the front of it.

Lab 9-10


Lab 9

The following schematic for testing our power amplifier should appear:

3.

To instantiate our new model, right-click somewhere blank in the schematic canvas, and from the context-sensitive menu choose: Get Part > By Symbol Name…

4.

When the form pops up, choose Browse.

5.

Select the symbol pwramp.ai_sym.

6.

Choose “Place” from the Get and Place Symbol By Name form:

…and then Close the Get and Place Symbol By Name form. 7.

Move the symbol into place and complete the connections.


Lab 9-11

Lab 9

8.

Run a Transient Analysis with the following settings: End = 50m

# End time 50ms

Step = 1u

# Set the initial time step to 1us

No Looping

9.

Plot the vsrc and vload signals on top of one another. You should see the following results:

Task 5.

Encrypt the model

If you are using the Student/Demo Edition of SaberRD, skip this Encryption part of the lab (Task 5 and Task 6). Encryption is not enabled in the non-commercial version of SaberRD.

5.1. 1.

Cut-and-paste the sub-circuit netlist

Open a Notepad (or other) text editor. Start Menu > Accessories > Notepad

2.

Navigate to the directory SaberRD_Training_Labs/Lab09. Open the file test_pwramp.sin.

You might need to change the file browser’s “Files of Type” to All Files to see test_pwramp.sin.

Lab 9-12


Lab 9

3.

If you’re using Notepad, turn on Word Wrap: Format > Word Wrap

4.

Resize (probably shrink) the window to make the text file readable.

5.

Highlight the text which contains the Intermediate Template pwramp:

6.

Copy this section of the netlist Edit > Copy

7.

Open a new File File > New

8.

Paste the Intermediate Template pwramp code.

9.

Save the file and give it the name pwramp.sin.

Be sure to change Notepad’s “Save as Type” box to “all files” such that this file does not end up with an extra “.txt” extension.


Lab 9-13

Lab 9

10.

Close Notepad.

5.2.

Run SaberRD’s Encryption Tool

Next, we will prepare the pwramp.sin file that we just created for encryption. In the process outlined below, you will add encryption instructions into the code and then the Encryption Tool will automatically encrypt your file for you. 1.

Back in SaberRD, switch to the “Model” tab and select SaberRD’s Encryption Tool in the bottom right of the Modeling Tools palette.

2.

In the Saber Encryption Tool, choose the menu: File > Open

And open the file that you just saved: pwramp.sin

Lab 9-14


Lab 9

3.

Select the green circle for “Encryption Start”

This will give you a new cursor in the form of an arrow that will insert the beginning of where you want encryption to start. 4.

Click when the arrow is just below the line that reads “ encrypted template pwramp vsrc:vsrc vload:vload ”

This will automatically insert two lines of directives for the Encryption Tool as shown below:


Lab 9-15

Lab 9

Lab 9-16

5.

Select the red circle for encryption end.

6.

Click when the arrow is at the very end of the file after the last brace.


Lab 9

7.

Select the Encrypt icon which looks like a lock.

8.

The Encryption Tool will ask you to backup your original source code. Save a backup of your original as pwramp.bak.

Your file is now encrypted and has been re-saved as pwramp.sin. It should now look like an encrypted file.

9.

Close the Saber Encryption Tool.

5.3. 1.

Modify the symbol to point to the encrypted model

In the test_pwramp schematic, right-click on top of the pwramp symbol and in the context-sensitive menu, select Symbol Editor.


Lab 9-17

Lab 9

2.

In the Properties pane on the right, select the schematic property:

3.

Just above that in the Properties pane, click on the red x to delete the schematic property.

4.

Click on the + sign next to that to add a new property.

5.

Fill in the form with the values “ primitive” and “ pwramp” as shown:

…and click “OK.” This will mean that the pwramp symbol will no longer use the schematic model, but rather will use the encrypted model that you created.

Lab 9-18


Lab 9

6.

In the Attributes pane in the lower right corner, change the visibility of this new property to just show the value:

7.

Next to the SaberRD button, click the Save Active icon to save the new symbol.

8.

Close the symbol schematic or simply go back to the test_pwramp schematic window using the tabs in the middle pane.

9.

Select the pwramp symbol and notice in the Properties pane that the symbol has been automatically updated such that the schematic property is no longer there but the primitive property is.

10.

Right click on the pwramp symbol and from the context-senstive menu select “View Model.”

11.

Notice that the model displays as encrypted and then close this model viewer.


Lab 9-19

Lab 9

Task 6.

Re-run the simulation and check results

1.

Re-run a transient simulation with the same settings as before (they should still be entered in the Quick Simulation bar).

2.

Plot the signals vsrc and vload on top of one another again and you should see the same results as when you used the schematic version of the model.

Task 7. 3.


4.

Lab 9-20

Leave SaberRD open.


Lab 10

10

Modeling: Import Spice Model

Learning Objectives In this lab exercise, you will import a Spice model and place it in a blank schematic. After completing this lab, you should be able to: • Import a Spice model for use in subsequent SaberRD simulations. • Compile a user library.


Modeling: Table Look Up (TLU) Synopsys SaberRD Electrical Workshop

Lab 10-1

Lab 10

Background In cases where you cannot find a model you need in the SaberRD parts library, there are still many options for getting what you need to complete your analysis. One place to look is on the web. Some manufacturers provide Saber models. Some provide Spice models. In this lab, we will walk through the process for how to take advantage of a Spice model in SaberRD.

Lab 10-2

Modeling: Table Look Up Synopsys SaberRD Electrical Workshop

Lab 10


Open the Design and Delete the Existing OpAmp Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab10. Open the file diffamp.ai_dsn.

3.

Select the lm324 part in the design. Right click for a context-sensitive menu and delete this part.

The schematic should now look like the following:

Task 2.

Import the Spice model

1.

Display the SaberRD Parts Library by selecting the Parts tab in the bottom left corner of SaberRD.

2.

Select the Browse tab.

Notice toward the top of the Parts Library the entry labeled, “ ai_User_Library.” This is a user-customizable entry for storing and using your own local models.


Lab 10-3

Lab 10

3.

Hover your mouse over “ ai_User_Library” and right-click:

4.

When the context-sensitive menu appears, choose Import Spice…

5.

Navigate to the directory: SaberRD_Training_Labs/Lab10. Open the file lm324_ns.mod

This is a Spice model provided by the manufacturer. 6.

If prompted about copying files to the library, select Yes.

This should bring up the Spice Wizard. SaberRD has started importing the model and even helps you automatically create a symbol for it. Since this is an OpAmp, let’s change the symbol type accordingly.

Lab 10-4


Lab 10

7.

In the Spice Wizard, toward the right side, select the drop-down menu next to Shape:

8.

Choose OpAmp from the drop-down menu.

Unfortunately, the pins do not show up in the correct locations for this model. Here is an excerpt from the source Spice model: *////////////////////////////////////////////////////////// *LM324 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM324_NS 1 2 99 50 28

9.

Select the yellow shaded boxes that get displayed as the pin ports and drag and drop them into the correct locations. Your symbol for the OpAmp should wind up looking like the following:

10.

Click Finish.

Notice that this part now shows up in your user library. Notice that the small symbol associated with the user library has turned red. This indicates that the


Lab 10-5

Lab 10

library has new information in it and needs “compiled” in order to be ready for usage. This is a simple step. 11.

Hover the mouse over the “ ai_User_Library” in the Parts pane again:

12.

Right-click to get the context-sensitive menu and choose Compile Library…

13.

When the Compile Library form appears, click OK.

14.

When the Library Compile Complete prompt appears, click Close.

Notice that the red indicator on the ai_User_Library has changed color to show that it is ready for use.

Lab 10-6


Lab 10

15.

Select the plus sign by the library to expand it and view your new part. Click and hold on the lm324_ns part and drag and drop it into place so that all of the pins get connected automatically.

This section of the schematic should now look like this:

Task 3.

Test the New Model If you are using the SaberRD Student Edition, skip Task 3. This model exceeds the node limits of the Student Edition.

1.

Run a transient simulation with the following settings: End = 10m


Step = 1u

# Set the initial time step to 1u

No Looping


Lab 10-7

Lab 10

2.

When the results pop up in the Results pane on the left, plot the signal out1.

You should see a response on out1 like the following:

You have successfully imported a Spice model for subsequent use in any of your SaberRD designs.

Task 4. 1.


2.

Lab 10-8

Leave SaberRD open.


Lab 11

11 Modeling: Table Look Up (TLU) Learning Objectives In this lab exercise, you will create a model using SaberRD’s Table Look Up (TLU) tool. After completing this lab, you should be able to: • Create a model from a data sheet. • Use the Waveform Calculator and other SaberRD features to validate its operation.



Lab 11-1

Lab 11

Background The data in the graph below was provided by Keystone Carbon Co. for their thermistor 060412-103.5-46-C. From this datasheet information, we were able to create a text file shown below the graph. The independent variable data (X axis) goes on the left (limited to 5 columns) and dependent variable data (Y axis) goes on the right (limited to one column). Our example has only one input (the thermal connection) so we have only one column of X axis data. We saved the file with the extension “.ai_dat”.

Lab 11-2


Lab 11


Open the Design and the TLU Tool Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab11. Open the file Thermistor_ex_TLU.ai_dsn.

3.


4.

Hover your mouse over each of the icons in the Modeling Tools palette and read through the tool tip that pops up with each such that you have a feel for each of the tools which is available in SaberRD.

5.

Left-click on the Table Look Up tool.

to access the Modeling Tools.

The Table Look Up (TLU) Modeling tool will appear.


Lab 11-3

Lab 11

Task 2. 1.

Create the TLU Model From the TLU Modeling tool, choose: File > New…

2.

As you recall from the Background section above, we have an ASCII data file with our table. So, when it prompts you to select a mode of data points input, select ASCII data file and click Ok.

3.

If you’re not already there, navigate to the directory SaberRD_Training_Labs/Lab11. Open the file keystone_060412_103_5_46_C.ai_dat.

Note that the data from our datafile is propagated into the TLU Modeling tool.

4.

In the TLU Modeling Tool, choose the menu: Properties > Interface Setup

Lab 11-4


Lab 11

This opens the Interface Setup window. The default connection type is Control. Control means that it is a numerical value that is non-conserved (vs. an electrical value, for example, which does follow conservation of energy). With our thermistor, we would like a temperature input and a resistance output. 5.

Click on the arrow to the right of the Type field in the Interface Setup windows to choose these options. Variable

Type

x

Thermal > temperature

y

Electrical > resistance

Your Interface Setup should now look like this:

6.

Click OK.

Note that the symbol and the axes on the model’s characteristic curve for the thermistor changes to reflect our new choice of connection types. Previously, it was somewhat meaningless data, now it reflects a temperature input and a resistance output. 7.

Save your new thermistor model by choosing the menu: File > Save

and name it keystone_thermistor. It is best to save the model in the same location as the datafile.


Lab 11-5

Lab 11

8.

In the TLU Modeling tool, left-click on the button place part place the part you just created into the thermistor test circuit.

9.

Close the TLU Modeling tool so that you can view the whole schematic.

10.

Move the new thermistor model into place in the middle of the schematic so that the connections get automatically completed.

11.

Change the ref value of the thermistor to keystone_thermistor1 :

12.

Save the schematic.

Task 3.

to

Simulate the Test Circuit

1.


2.

Run an Operating Point analysis:


Next, we will run a DC Parameter Sweep. Lab 11-6


Lab 11

3.

From the simualtion controls, change the simulation type to DC Sweep

4.

Toward the right you’ll see the box labeled “Source” Click the ‘Browse’ button on the right of the field:

5.

This will bring up a list of the sources available for sweeping. Expand the Thermistor_ex_TLU and select the t_dc.amb_temp entry.

6.

Click OK.

7.

Fill in the following values for the v_pulse.vin initial value:

Start = -40

# Start at -40C

End = 85

# End at 85C


Lab 11-7

Lab 11


Before hitting the “go” button, there is one more thing to note. In checking the validity of the model that we created, we will want to compare the output of the model with the data that we used to create it. We can do this by measuring the resistance on the output. This will be simple to find using the Waveform Calculator by dividing the output voltage by the output current. By default, and to improve simulation performance, SaberRD only saves waveforms for “across” variables such as voltage. We will need a “through” variable, that is, the current. This is easy to configure in the advanced settings for the DC Sweep.

Lab 11-8


Lab 11

8.

In the bottom right-corner of the Quick Simulation bar, left-click the icon

to display the Advanced Simulation controls.

9.

If needed, select the tab for DC Sweep

10.

Change the Signal List to All Signals which will leave the Advanced Simulation controls looking like the following:

Signal list options are explained in the table below.


Lab 11-9

Lab 11

Signal List Options

Description

Syntax

All Toplevel Signals

Includes all signals which are part of the top :*:* level design. The top level design corresponds to the highest level of the current schematic.

All Signals

Includes all signals at all levels of design hierarchy.

:...:*

Browse Design

Opens access to a design hierarchy browser to enable selecting desired circuit signals.

-NAChoose the desired signal(s) from the Design Hierarchy box (LHS) and add them to the Selected box (RHS)

11.

Click the “Close” button on the Advanced Simulation controls window.

12.

Click the green “go” button in the Quick Simulation bar.

Task 4. 1.

Compare Waveforms to Check Model When the results pane displays on the left, expand short.short_tlu.

Lab 11-10


Lab 11

2.

Double click on the signal i for short.short_tlu to plot the current.

3.

Double click on the signal vout_tlu to plot the voltage.

4.


5.

Click on the Waveform Calculator button

to display the

Waveform Calculator tool. Click the “Stack” select “Clear All” if needed.

button and


6.

Select the signal vout_tlu in the Graph window.

7.

Use the middle mouse button to paste the signal vout_tlu into the entry line/box in the Waveform Calculator as shown below.


Lab 11-11

Lab 11

Lab 11-12

8.

Next, select the signal i in the Graph window.

9.

Use the middle mouse button to paste i into the entry line/box in the Waveform Calculator as shown below.

10.

Divide these two signals by selecting the divide key on your keyboard or by left-clicking on the divide key in the calculator.

11.

Plot the resulting signal using the “Graph X” button on the Waveform Calculator and then close the Waveform Calculator.


Lab 11

You should now see a waveform for the transfer function of the thermistor model. Delete the vout_tlu and i waveforms by selecting them in the Graph window, right-clicking, and choosing “Delete”. You should be left with just the waveform for vout_tlu/i.

Question 1.


What does this graph of vout_tlu/i represent, i.e. what is the x-axis and what is the y-axis? _______________________________________________ _______________________________________________

Lab 11-13

Lab 11

Now let’s compare this to our original data. SaberRD can read in and plot many waveform formats, the most simple of which is just a table of ASCII text like our original input file. Let’s load this waveform and compare it to our model’s response.

12.

In the Analyze tab, click the button for Open Results.

13.

Open the file keystone_thermistor.txt

14.

Plot the signal Y2 and compare it to (vout_tlu/i). You might want to drag and drop this signal into the region of (vout_tlu/i) such that they are in the same graph.

You should see that they perfectly match. We can conclude that our model works as expected.

Task 5. 1.


2.

Lab 11-14

Leave SaberRD open.


Lab 11


Compare Waveforms to Check Model

Question 1.


This waveform represents the change in resistance vs. change in temperature (just like our original input data from the manufacturer).

Lab 11-15

Lab 12

Modeling: StateAMS

12

Learning Objectives In this lab exercise, you will create a model of a comparator using SaberRD’s StateAMS tool. After completing this lab, you should be able to: • Create a behavioral model with StateAMS.


Modeling: StateAMS Synopsys SaberRD Electrical Workshop

Lab 12-1

Lab 12

Background Saber has many flexible options for getting the models that you need. One of the most powerful options is the StateAMS tool. Don’t let the “State” in the name fool you, this tool can be used to create a model of a wide variety of devices. In this lab, you will complete a functional model of a comparator with hysteresis. The reason for creating this device lies in the difficulty of creating the design using discrete devices and the need to completely reformat the equations if the threshold or hysteresis values change in the preliminary stages of the design. Below is an example circuit and steps in calculating the resistor values for hysteresis. Additional resistors are needed to set the threshold and if the threshold voltage changes these resistor values must also change. From the Maxim website:

Lab 12-2


Lab 12


Lab 12-3

Lab 12


Open the Design and the StateAMS Tool Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab12 Open the file test_comp.ai_dsn.

Notice the empty space where your comparator will reside. 3.


4.

Left-click on the StateAMS tool.

to access the Modeling Tools.

The StateAMS tool opens. 5.

Lab 12-4

Choose Help > Tutorials menu. There are four very worthwhile tutorials available to teach how to model using the StateAMS tool. It would be good to revisit these at a later date.


Lab 12

Task 2.

Create the comparator model

Topology Editor The top left pane represents the topology editor. This area allows the user to add external connections to a model as one of three types: •

Branch terminals for conserved nets, including electrical, mechanical, hydraulic, magnetic, and more.

•

Input ports, which can assume continuous behavior for signal-flow inputs and state-based behavior for event-driven inputs.

•

Output ports, which can assume continuous behavior for signal-flow outputs and state-based behavior for event-driven outputs.

The comparator model will have 3 nodes. The 2 input nodes will be conserved analog and the output will be digital.


Lab 12-5

Lab 12

1.

Add branch terminal by selecting . Add the name inp to the Add Branch Terminal form, then click OK. Notice that the Nature is Electrical and the position is left. Both are correct.

The Topology Editor should now look as follows:

2.

Add another branch terminal

3.

Add output port with name out by selecting Output Port form as follows:

with name inm.

and filling in the Add

a. Name = out1 b. Type = State c. Unit = Digital Logic Note: for Type and Unit, select the drop down arror to the right to change.

Lab 12-6


Lab 12

You should now have the pins defined and the symbol in the Topology Editor should look as below.

Quantity Editor The top right pane represents the quantity editor. This area allows the user to define variables and quantities used in the model. A quantity can be one of the following types: •

Static Variables can either be constants, which do not change during a simulation, or internal parameters, which are evaluated as mathematical expressions when a simulation is initialized.

•

Continuous Variables are analog quantities that are evaluated at each simulation time step.

•

State Variables are event-driven quantities that change at discrete points during a simulation.

•

Functions are complex combinations of quantities that can be used in continuous variable equations, action statements, transition conditions, or transition time definitions.

You will now add 2 static variables (input parameters). These variables will be for the threshold and hysteresis parameters. 4.

Click on the


and select Static Variable…

Lab 12-7

Lab 12

5.

Fill in the following fields in the Add Static Variable form: a. Name = hysteresis b. Default = 1

6.

Repeat step 1 and create another Static Variable with Name = thresh and Default = 5.

Your model should now look as below.

State Diagram Editor The bottom pane represents the state diagram editor. This area is a canvas for defining state-dependent behavior of a model. A state diagram may consist of the following elements:

Lab 12-8

•

States are used to define the regions of a model’s behavior. Concurrent groups of states may exist on a single diagram, but an initial state must be defined for each group.

•

Transitions define when a model should enter or leave a state, depending on conditions met by model quantities.

•

Blocks allow a group of states to share transitions, thereby simplifying the state diagram. Modeling: StateAMS Synopsys SaberRD Electrical Workshop

Lab 12

•

Clocks can be used to define a periodic behavior that is not statedependent.

It’s now time to add 2 states (LO, HI) and the transitons. 7.

Select a initial state by clicking on . Drop it into the State Diagram Editor with a Left Mouse Button (LMB) click. Deselect with a Right Mouse Button (RMB) click.

8.

Add a second state by clicking on . Drop it into the State Diagram Editor with a LMB click. Deselect with the RMB.

9.

Double click on the initial state and name it LO.

10.

Double click on the second state and name it HI.

11.

Add transition from LO to HI by selecting the Add Transition icon . To start the transition, place your mouse over state LO and LMB click. To finish, place your mouse over HI and LMB click. Do not deselect (RMB)!

12.

Now add a transition from HI to LO by first LMB clicking on the HI state and then LMB clicking on the LO state. Now you can deselect with a RMB.


Lab 12-9

Lab 12

13.

Lab 12-10

Add transition condition for LO to HI by double clicking (LMB) on the “?” above the LO to HI transition. Add vin >= (thresh + 0.5*hysteresis) as shown below.


Lab 12

14.

Repeat for the HI to LO transition using the condition vin <= (thresh 0.5*hysteresis)

The model should now appear similar to below:

15.

Try to save the model as comp_hyst. Notice that an error message appears indicating that the quantity “vin” has not been defined.

You will now add a continuous variable vin. 16.

Click on the Add across variable icon Topology Editor.


on the left side of the

Lab 12-11

Lab 12

17.

Click on pin inp then pin inm. The Add Continuous Variable form will appear. Fill in the name vin. Click OK.

You will now define the input current to the comparator. 18.

Lab 12-12

Click on the Add thru variable icon

in the Topology Editor.


Lab 12

19.

Click on pin inp then pin inm. The Add Continuous Variable form will appear. Fill in the name iin. In the Analog Equations section select and then select ALL. Enter 0 in the Equation field (for all states). The form should appear as below.

20.

Click on OK


Lab 12-13

Lab 12

The last addition to this model is to set the state variable out1 to a logic 1 in the HI state and a logic 0 in the LO state.

Lab 12-14

21.

Double click on state LO and add out1=’0’ (include the single quotes) in the Entry Action field as shown below, then click OK. (Expand the window if needed to see OK.)

22.

Double click on state HI and add out1=’1’ in the Entry Action field. Then click OK. (Expand the window if needed to see OK.)

23.

Click the Save button

24.

The View HDL code button allows the user to view the model (in openMAST) that is automatically generated by StateAMS.


Lab 12

25.

Notice that you can also select to output your StateAMS model in VHDL-AMS. From the menu, select HDL > VHDL-AMS

You can now view the HDL code in VHDL-AMS with the button . 26.

Return the model to MAST mode with the menu HDL > MAST

27.

Press the View state diagram button Diagram Editor.

28.

Move the StateAMS window so that you can see the design schematic window.

29.

Place the model that you just finished in the schematic by pressing the place part button

to return to the State

in the StateAMS window.

30.

Close the StateAMS window.

31.

Move your new model into place such that the connections are automatically completed.

Task 3. 1.

Test Your Model Run a Transient simulation with the following settings:

End = 2

# Run the simulation for 2s

Step = 1u

# Set the initial time step to 1us


Lab 12-15

Lab 12

2.

Plot the waveforms in and out on one graph and and you should see the following response:

Now let’s analyze the response of our model. 3.


4.

In the graph window, select the out signal.

5.


6.

In the measurement tool, left-click the button next to Measurement and select:


to bring up the

General > Vertical Cursor


Click Apply.

Question 1.

Lab 12-16

At what time does the output signal change states? _______________________________________________


Lab 12

8.

In the graph window, select the in signal.

9.

In the measurement tool, left-click the button next to Measurement and select: General > At X


Fill in the X value from your answer above:

11.

Click Apply.


Lab 12-17

Lab 12

Question 2.

What is the value of input that causes the output to change and why? _______________________________________________ _______________________________________________

Note:

To answer the why part of this question, you may want to revisit the StateAMS model. Go back to the schematic and select the symbol for the comp_hyst part. In the properties window, you will see tool: StateAMS. Click in this line and select the button to bring up the StateAMS tool.

Note:

Notice what is defined as the transition condition from LO to HI…

Compare the effort that it took to create this model with simple transition equations in StateAMS vs. what it would have taken to create by assembling a macro model…

Task 4. 1.


2.

Lab 12-18

Leave SaberRD open.


Lab 12


Test Your Model

Question 1.

0.55

Question 2.

5.5V. This is due to the definition of the transition condition in our StateAMS model: vin >= (thresh + 0.5*hysteresis) and the default values of thresh (5) and hysteresis (1).


Lab 12-19

Lab 13

13

Modeling: Characterization

Learning Objectives During this lab, you create a diode model using the Diode Tool. After completing this lab, you should be able to: • Use the Scanned Data Tool • Create a diode model


Modeling: Characterization Synopsys SaberRD Electrical Workshop

Lab 13-1

Lab

13

Instructions It’s not always possible to find a fully characterized MAST model for the particular device you intend to use. The first option might be to use the Parametric Search Wizard to check if there are any substitute devices available. Another option could be finding a Spice model on the web and performing a translation, which was covered earlier. We’re going to detail one more option with this lab, which is creating a diode model by using data sheet information. The Diode Tool has a very straightforward characterization process. First, the dc characteristics are defined, then the capacitance, followed by the reverse recovery if needed.

Task 1. 1.

Invoke the Diode Tool To access the modeling tools select the Bring up the Diode Tool by first selecting the Model tab

2.

Bring up the Diode Tool by selecting the Diode icon

3.

Once in the Diode Tool, hover your mouse over the diode and two capacitors and note they are highlighted. Double click the resistor/diode to bring up the Diode I-V Characteristic form.

Task 2. 1.

Lab 13-2

I-V Curve Data

The idea is to be able to get the Data Sheet information associated with the I-V curve into the Diode Tool as quickly and efficiently as Modeling: Characterization Synopsys SaberRD Electrical Workshop

Lab 13

possible. To do this we are going to use the Scanned Data Utility. The Scanned Data Utility allows you to define the axis boundaries, then plot a curve inside those boundaries that overlies that of the data sheet. 2.

From Task 1, the Diode I-V Characteristic form should be displayed as shown below:

3.

In a Windows file browser, navigate to the directory SaberRD_Training_Labs/Lab13.

4.

Open the data sheet mur240-D.pdf (using Adobe Reader) . Page down until you can view Fig. 1 Typical Forward Voltage.


Lab 13-3

Lab

13

5.

In SaberRD, bring up the Scanned Data Utility by selecting the graph icon

6.

Lab 13-4

from the toolbar in the Diode I-V Characteristic form.

Notice in the top right hand corner of the Scanned Data Utility there is a Transparency slider. Drag the Transparency slider to the right to maximize the transparency and place the Scanned Data Utility (SDU) window over the Figure 1 on the data sheet. Enlarge the SDU window by dragging a corner. If the graph still doesn’t fit reduce the zoom to 75% in Adobe Reader. You should see something similar to below:


Lab 13

7.

You are now going to set the graph boundaries. Select the corners of the ‘box’ in your graph window and enclose the data sheet graph as shown below.

8.

Once the boundaries are defined, it’s time to define the axis. Select the Edit Axis icon in the SDU window and fill in the axis information. (You may need to reduce the transparency to see this icon) For the X-Axis, which is the diode forward voltage, set: Start = 0.3

# Start at 0.3V

End = 1.5

# End at 1.5V

Scale = linear the right

# use the drop down arrow to

For the Y-Axis, which is the diode forward current, set: Start = 0.1

# Start at 0.3A

End = 10

# End at 10A

Scale = log the right

# use the drop down arrow to

Then click OK.


Lab 13-5

Lab

13

The completed Axis Definition form for the mur2 shown below.

40 diode is

Now that the Scanned Data Utility has the axis information, it’s time to enter the curve data. 9.

Select the Create Curve icon in the SDU window and place the tip of the mouse over the data sheet I-V curve (use the 25°C curve) and use the LMB to place a point on the curve. Continue to place points on the curve and deselect (finish) by using the RMB.

Note:

Lab 13-6

If you would like to move any of the data points after the curve is finished, simply select the point and move. To extend the curve (ie, add more points), RMB click on the last data point and select Extend Curve.


Lab 13

10.

The curve @25°C is shown below.

11.

Decrease the transparency and enter 25 (for 25°C) in the temperature field “temp” of the I-V curve, in the top right portion of the Scanned Data Utility window.


Lab 13-7

Lab

13

12.

You should have something similar to below.

Note:

13.

Lab 13-8

The Diode Tool has the ability to create a model with temperature dependent I-V characteristices. If this is desired, you can enter the other I-V curves into the same graph window and make them uinque by specifying the temperature associated with each curve. We will not do this during this lab.

Save the scanned data. From the Scanned Data Utility select File > Save as… and save with the default name in the directory SaberRD_Training_Labs/Lab13.


Lab 13

14.

Select OK from Scanned Data Utility and the recently generated data will be loaded into the Diode I-V Characteristic. Notice that there are now 2 curves.

15.

Since the Vd data is in the range of 0.3 to 1.5 volts, set the range of the test sweep from 0.3 to 1.5 in 100 lin steps by bringing up the sweep range link at the bottom of the Diode I-V Characteristic. Click OK.

16.

You’re now ready to run the optimizer. Select the target icon bring up the Diode Forward I-V Optimizer.


to

Lab 13-9

Lab

13

17.

Set the Target Data Range to 0.3 and 1.5 and then select Run.

Move the Optimizer out of the way so you can observe the curves being matched in the I-V Characteristic window. Note:

Depending on the accuracy of your input data the two curves should nearly overlay one another, however the first opimization may not match well enough. If it does not meet your satisfaction, you can either run the Optimizer again or manually intervene, as described in the steps below.

Leave the Diode Forward I-V Optimizer window open, and move if needed to see the graph. 18.

Lab 13-10

Turn on the anchor objects with the Toggle Anchor Objects icon


Lab 13

19.

You are now going to increase the slope of rs to more closely match the data sheet curve by selecting the orange rs anchor object and moving it to another location to the left or right.

20.

When you are satisfied with the overlay check the box under Fixed to set rs in the Diode Forward I-V Optimizer to Fixed as shown below.


Lab 13-11

Lab

13

21.

Now the slopes of the curve should match the scanned data, however it may still be necessary to re-run the optimization. Do this now if needed. The final characterization should appear similar to below. Notice how closely the curves overlap.

22.

Close the Optimizer.

23.

Close the Diode I-V Characteristic.

24.

From within the Diode Tool, save the newly created model as SaberRD_Training_Labs/Lab13/mur240_dt.

Task 3.

Lab 13-12

Capacitance Data

1.

Return to the PDF window and page down to Fig. 7 Capacitance Curve.

2.

From the Diode Tool, double click the capacitor Cj to bring up the Junction Capacitance form.

3.

Bring up the Scanned Data Utility by selecting the graph icon

4.

Maximize the transparency and place the Scanned Data Utility over the Capacitance curve (Fig. 7) on the data sheet.

5.

Set the graph boundaries. Select the corners of the ‘box’ in your graph window and enclose the data sheet graph.

6.

Define the axis. Select the Edit Axis icon and fill in the axis information from Fig 7, including the start and end values. Name the X Axis Vr and the Y Axis Cj. Make sure that you enter the capacitance data in pf (i.e. 0 to 30p). Modeling: Characterization Synopsys SaberRD Electrical Workshop

Lab 13

7.

Select the Create Curve icon and use the LMB to place points on the curve. Continue to place points on the curve and deselect by using the RMB.

8.

Save the current scanned data. From the Scanned Data Utility select File > Save as… and save with the default name in SaberRD_Training_Labs/Lab13.

9.

Clicking on OK will load the curve data into the Junction Capacitance tool.

10.

Set the Reverse Voltage range in the Junction Capacitance tool from 0 to 30.


Lab 13-13

Lab

13

Lab 13-14

11.

Select the Optimizer icon to bring up the Diode Capacitance Optimizer and select Run. You should see something similar to below.

12.

Close the optimizer.

13.

Click on Apply in the Junction Capacitance tool.

14.

Close the Junction Capacitance tool.

15.

Save the diode.


Lab 13

Task 4. 1.

Reverse Recovery

From the Diode Tool, double click the capacitor Qrr. The Diode Reverse Recovery tool should appear as below.

A snapshot of the data sheet information related to reverse recovery is shown below.


Lab 13-15

Lab

13

2.

Fill in reverse recovery data in Diode Reverse Recovery tool. if0 (A) = 1 dirdt (A/s) = 50e6

3.

Click on Apply.

4.

Close the Diode Reverse Recovery tool.

5.

Save the diode.

There will be 3 files created.

6.

1.

mur240_dt.ai_sym is the symbol

2.

mur240_dt.ai_dp is the form data for the diode tool.

3.

mur240_dt.sin is the model code.

Open mur240_dt.sin using a text editor.

Notice that the characterized data has ben entered into the model structure as below. dp..model model=(rs=0.03438,isl=195.5n,nl=1.998, ish=1.988u,nh=2.634,cjo=26.17p,vj=0.6926,m=0.4789,fc=0.5, tt=50n,tm=10n,tsw=0,beta=0,betasw=0, trs1=0,trs2=0,xti=3,tnl1=0,tnl2=0, xtih=3,tnh1=0,tnh2=0,tnom=25,gamma=0)

The I-V curve data consists of rs, isl, nl, ish, and nh. The capacitance data consists of cjo, vj, and m The reverse recovery data consists of fc, tt, and tm

Lab 13-16


Lab 13

Task 5. 1.


2.

Leave SaberRD open.


Lab 13-17

Lab 14

14

Monte Carlo and Pareto Analysis

Learning Objectives In this lab exercise, you will perform a Monte Carlo analysis and examine the results using a Pareto Analysis. After completing this lab, you should be able to: • Use Monte Carlo and Pareto to analyze design robustness. • Describe the process for identifying the parameters to which a design is most sensitive.


Monte Carlo and Pareto Analysis Synopsys SaberRD Electrical Workshop

Lab 14-1

Lab

14

Background In this lab you will perform a Monte Carlo analysis. This analysis uses both component values and the tolerances associated with those values to simulate in a statistical environment. Because tolerance is now taken into account, the tolerances for a circuit’s components must be specified somewhere. For the RLC circuit, the tolerances are specified in a new SaberRD design, ex_rlc_mc.

Lab 14-2

Improve Design Robustness Synopsys SaberRD Electrical Workshop

Lab 14


Run a Nominal Time domain Analysis Click the SaberRD button for access to the file menu and choose: Open > Open Design.

2.

Navigate to the directory SaberRD_Training_Labs/Lab14. Open the file ex_rlc_mc.ai_dsn.

The RLC schematic will appear only this “_mc” version will now have tolerances specified:

Note that the component values are now specified using statistical distributions: uniform() and normal(). Note the syntax used here. The characteristics of the distributions are specified within parentheses using the following syntax: (nominal, tolerance). For example, each of the varying parts in the schematic has a tolerance of 0.1, that is, 10%. This is one commonly used method but SaberRD is flexible in how you specify tolerances. For detailed information, please consult the SaberRD documentation.


Lab 14-3

Lab

14

3.


4.

Change the simulation type to Transient

5.

Fill in the fields with the following values:


End = 5m


Step = 10n

# Set the initial time step to 10ns


Lab 14-4

6.


7.

When the simulation finishes, plot vout. This represents the nominal case for this design.


Lab 14

8.

Close this graph window by left-clicking the x in the right corner of this pane:

Task 2.

Run a Monte Carlo Analysis

1.

If needed, Switch to the Simulate tab simulation controls.

2.

From the simualtion controls, change the Looping control to Monte

for access to the

Carlo

If using SaberRD Student Edition for the training, fill in 10 runs instead of 100 in the step below. The Student Edition limits Monte Carlo runs to 10.

3.

For the number of runs, fill in 100. The quick simulation bar should now look like this:

4.


You are now running in a statistical environment. You can watch the simulation activity in the Simulator Transcript window. You should see runs 1-100 scroll by. You just did the following: •

Ran a nominal case transient analysis in Task 1 to make sure the design works.

•

Opened a Monte Carlo “loop” in which components will be randomly assigned new values within their specified tolerance bands. These random value changes will be made 100 times.


Lab 14-5

Lab

14

•

Each time the changes are made for a particular run, SaberRD will perform a transient analysis.

•

After the Monte Carlo analysis is complete, the plot file tr will be opened—you’ll notice a second tab called “ tr (100)” next to the nominal case “ tr” in the Results pane.

Other MC information: •

Runs is the number of times the analysis is to be executed.

•

For repeatable results, the random number generator’s Seed may be specified. This control can be accessed from the Quick Simulation advanced controls in the bottom right corner leave the default value for now.

Lab 14-6

. However, we’ll

•

For post-processing, MC creates a Parameter File which saves all of the parameter values used for each run. We’ll use this later to understand the results better. By default this gets named with mcpar in the name.

5.

Plot the signal vout again. Notice that you now have a spectrum of responses instead of just a nominal case:


Lab 14

Task 3.

Measure the Overshoot

1.


2.

In the graph window, select the vout signal.

3.


4.



to bring up the

Time Domain > Overshoot

5.

Click Apply.


Lab 14-7

Lab

14

Your graph should now look similar to this:

Over(ex_rlc_mc: vout) shows the overshoot fluctuations as a result of

component value changes (Overshoot as a function of MC runs). This is very useful data. It shows us what role component tolerances play in the overshoot of vout. The data may be more easily represented in histogram form, which you will do next. 6.

In the measurement tool, left-click the button next to Measurement and select Statistics > Histogram

Lab 14-8


Lab 14

7.

Use the drop-down menu next to the Signal box Signal to Over(ex_rlc_mc: vout)

8.

Click Apply.


to change the

Lab 14-9

Lab

14

9.

To make your graph more readable, you might want to remove the vout signal from the graph. To do so, select the signal vout in the

graph window. Right-click to get a context-sensitive menu and at the bottom you can click Delete to remove the vout signal from the graph. Your graph should now look similar to the following:

The histogram shows how often the MC results fell into a particular voltage range. The number of runs that fall into a particular voltage range is represented by count, on the y-axis; the ranges themselves are shown on the x-axis. Notice that the scatter plot of the Overshoot and the histogram correlate with each other in terms of the centering and the outliers—they are merely different views of the same data to help with interpretation.

Task 4.

Create a Pareto Analysis

We currently have a lot of data regarding our RLC filter design. How do we now interpret that data into something useful that we can take action on in order to improve the robustness of our design? What parameters have the biggest effect on the variability of the overshoot? What parameters have no effect on the variability of the overshoot? A Pareto Analysis can help us answer these questions by statistically sorting out the correlations between the parameter changes and the change in overshoot.

Lab 14-10


Lab 14

1.

In the measurement tool, left-click the button next to Measurement and select Statistics > Pareto

2.

Use the drop-down menu next to the Signal box Signal to Over(ex_rlc_mc: vout)

3.

As we discussed previously, an important part of this process is the parameter file which lists all of the individual parameter values for the various runs. SaberRD needs this file to build the Pareto analysis. You can locate the file using the browser button Parameter Plot File box. a.

b.

to change the

next to the

If needed, in the file browser, change the “Files of type” drop-down box to PL/AWD (*.ai_pl,*.p1.*,*.ai_awd). Navigate to the directory: SaberRD_Training_Labs/Lab14. Open the file ex_rlc_mc.mcpar.ai_awd.

c.

Click the drop-down menu for the “Parameter Names:” and choose Browse In Plotfile… Select c(c.c1), l(l.l1), rnom(r.r1) and rnom(r.r2). Hold down the Ctrl button to select multiple items:

Click “OK.”


Lab 14-11

Lab

14

Lab 14-12

d.

Use the drop-down menu to change to “R**2”

next to “Sorted by:”

e.

Change the three “Minimums” at the bottom of the Measurement form to all show 0.01 instead of 0.l. The filled out form should look like the following (your “Active graph” may have a different number):

f.

Click Apply and leave the Measurement tool up as we will use this form again shortly and this will spare us from re-entering everything. Move it out of the way if needed in order to see the graphs.


Lab 14

These plots are measures of how sensitive the overshoot of the output voltage is to the system components. This analysis yields some interesting information. For example, the Main Effect plot shows that the Overshoot is most sensitive to the resistance r1.

All of the parameter changes happened according to their tolerances. The Main Effect histogram shows the % change in performance per % change in parameter. The R**2 histogram shows the % total variation of the measure as a result of the given parameter. In other words, the R**2 histogram shows which are best able to rise above the others and make the Overshoot change despite all the parameters changing within their tolerance ranges. r.r1 seems to be able to effect the most change. Let’s examine the r1 effects more closely. 4.

Close the Pareto graph window (by left-clicking the x in the right corner of this pane)

but again, leave the Measurement tool open.


Lab 14-13

Lab

14

Task 5. 5.

Create a Scatter Plot for r1 Back in the Measurement form: a.

If it is not already listed, use the drop-down menu next to the Signal box

to change the Signal to

Over(ex_rlc_mc: vout)

b.

Click the drop-down menu for the “Parameter Names:” and choose Browse In Plotfile… Select only rnom(r.r1) this time:

Click “OK.”

Lab 14-14


Lab 14


c.

Uncheck the box next to Histogram Plots.

d.

Check the box next to Scatter Plots.

e.

Click Apply.

Lab 14-15

Lab

14

Your graph should look similar to the following:

This information is useful from a general design perspective as we’re trying to choose the right value for r.r1. Note the strong correlation between r.r1 and the overshoot. As r.r1 increases, the overshoot voltage decreases. The R**2 we looked at before predicted that the scatter points would be fairly tight around the best fit line. The Pareto Analysis is also useful from a robustness perspective. We know that a tighter tolerance on r.r1 will reduce the variability of the overshoot. Monte Carlo and Pareto Analysis play important roles in the design verification process. Having the ability to vary component parameters in a statistical environment is extremely useful to engineers, and makes for more robust designs. This section would be good to run through again after the training course. Many concepts were covered in a short period of time.

Task 6. 1.


Lab 14-16

2.

You can close the Measurement tool now as well.

3.

You can leave SaberRD open.


Lab 15

15

Worst Case Analysis (WCA)

Learning Objectives During this lab, you gain insight into non-monotonically increasing or decreasing functions and their relevance to Worst Case Analysis. After completing this lab, you should be able to: • Setup the Worst-Case Analysis Tool. • Perform a Worst Case Analysis. • Understand the difference between monotonic and nonmonotonic functions and their relevence with respct to WCA. • Plot a One-Dimensional Parameter Sweep. • Plot a Two-Dimensional Parameter Sweep.


Worst Case Analysis Synopsys SaberRD Electrical Workshop

• If you are using the SaberRD Student Edition for the training, skip this entire lab. WCA is not enabled in the Student Edition.

Lab 15-1

Lab 15

Overview Your goal is: •

Run an Worst Case Analysis on a simple resistor divider circuit using both a range and corner search methodology.

•

Compare the results and understand why they are different.

Task 1.

1.

Open the Resistor Divider Design and Invoke Saber Navigate to the directory SaberRD_Training_Labs/Lab15. Open the file resdiv_wca.ai_dsn.

The schematic appears as shown below:

This is a simple design that efficiently illustrates the difference in results obtained from WCA using corner and range search algorithms when encountering a non-monotonic function. Notice that the value of r1 = 3.7 ohms with a range of 3 to 4 ohms, while r2 = 3 ohms with a range of 1.5 to 4.5 ohms.

Task 2.

Setup the Worst-Case Analysis Tool

Before any analysis is undertaken we should first understand what information we will require. In this case, we are interested in determining what resistor values will provide the maximum power output to r2. In this case a DC Analysis is sufficient. Extraction of the power associated with resistor r2 is required for this analysis. 1.

Lab 15-2

Select the Analyze tab


Lab 15

1. Invoke the WCA Tool

2.

Extract the Stochastic Parameters.

Note:

a.

In this case, there are only two parameters. For more complex designs it may be necessary to perform a Sensitivity or Pareto Analysis prior to WCA in order to determine which parameters have influence on the measurment of interest.

Select the dice icon form.

to bring up the Extract Stocastic Parameters

Click on Extract. Parameters in the design that have tolerances will be identified and made available. In this case resistors r1 and r2. It’s also


Lab 15-3

Lab 15

possible to add parameters to the WCA Tool that do not have associated tolerances.

b. Since we are performing an initial WCA, you can select either Append or Replace. If you were adding more parameters to a WCA search and wanted to keep the ones aleady in the tool, an Append would be used. Notice that the parameter values and domains are automatically added. This eliminates manual entry errors which give erronous results.

Lab 15-4


Lab 15

3.

Define a Test. By default, a test by name test1 is provided by the Worst-Case Analysis tool. (If a test needed to be added, you could Click New)

a.

and select

To rename a test, either double-click the test name or right-click the test name, choose rename and enter the test name. For this example, rename test to MaxPwrRange as shown below.

Note:

To enable or disable a test in the test suite, either click the check box adjacent to the test name or right-click the test name and choose enabled.

Note:

All tests added to the test suite are enabled by default.

Note:

To copy a test specification to another test in the test suite, right-click the newly created empty test, choose Copy from and select the test whose specifications you want to copy.

Note:

To reorder the sequence of tests in a test suite, drag and drop the test name.

4.

Specify Simulation Analyses

The Worst-Case Analysis tool provides the ability to add simulation tasks in the definition of a test and the sequence in which they are executed supporting the following analysis.

DC Operating Point Transient Small-Signal AC


Lab 15-5

Lab 15

Note:

5.

c.

Lab 15-6

DC Transfer Alter - Alter commands can be inserted between analyses, allowing design configurations such as temperature or position of switches to be set for different analyses. This allows objectives tied to different design configurations to be optimized concurrently. Parameters being altered are not considered in the optimization search.

Click on and select DC Operating Point from the WorstCase Analysis tool. An options configuration dialog box appears.

Click OK to accept the analysis configuration details. Notice that the analysis has been entered below the Analysis tab.


Lab 15

6.

Specify Performance Measures The Worst-Case Analysis tool provides the ability to add performance measures in the test definition that consume the results of the analyses (signals) and produce measurement values used in the objectives. A measure is applied on a waveform expression which is an algebraic combination of signals. An example of valid waveform expression is: v(r.r1)*i(r.r2)+power(r.r3)

where v(v.r1), i(r.r2) and power(r.r3) are simulation

signals. a.

Click and select New from the Worst-Case Analysis tool. The New Measure dialog box appears:

b. Enter the measure Name = power_max. c. Set Analysis to dc if it isn’t already. d. Click on the to the right of Waveform and select Signals… e. Using the Signal Hierarchy browser expand resdiv_wca, navigate down to and expand r.r2 and scroll down and select power and click OK.


Lab 15-7

Lab 15

In SaberRD, typically you do not need to explicitly calculate the power dissipated in a component as it is built-in to the models.

Lab 15-8

f.

Choose a measurement function. In this case the default value of At X is correct.

g.

Click OK to add the performance measure to the test.


Lab 15

2. Click and select New from the Worst-Case Analysis tool. The New Objective dialog box appears a.

Set Objective to max(power_max).

b. Click OK to add the Objective to the test. c. Alternatively, you could have RMB clicked on the measure power_max and selected Add Objective… Maximize.

The Worst-Case Analysis tool provides the ability to add optimization objectives to a test to characterize the optimization goals and constraints of the input design. The Worst-Case Analysis tool supports the following objective function expressions:


min(expr1) max(expr1) expr1=expr2 expr1expr2

Lab 15-9

Lab 15

Where expr1 and expr2 are algebraic expressions of measures and parameter aliases. The mathematical functions allowed in an objective expression are: Function Description abs(x)

Absolute value of x

acos(x)

Arc-cosine of x.

asin(x)

Arc-sine of x.

atan(x)

Arc-tangent of x.

cos(x)

Cosine of x.

cosh(x)

Hyperbolic cosine of x.

exp(x)

Exponential, ex.

log(x)

Natural log of x.

log10(x) Log base 10 of x. max(x,y) Maximum of x and y.

min(x,y) Minimum of x and y. pow(x,y) x to the y power, xy. sign(x)

1 if x is positive, -1 if x is negative, 0 if x is zero.

sin(x)

Sine of x.

sinh(x)

Hyperbolic sine of x.

sqrt(x)

Square root of x.

tan(x)

Tangent of x.

tanh(x) Hyperbolic tangent of x. It is important to distinguish minimization and maximization directives from minimum and maximum functions. For example, the objective below is seeking to minimize the minimum between "a" and "b". min(min(a,b)) The first occurrence of "min" is the minimization directive that takes one argument; the second occurrence is the minimum function that takes two arguments. The objectives are assigned weights and are evaluated concurrently as part of a sum to minimize. The terms of this sum have a form that depends on the objective type:

Lab 15-10


Lab 15

7.

Uncheck the Downhill Simplex and Steepest Descent algorithms. We will only use the Variable Neighborhood Search algorithm.

To add an algorithm, you would click and choose an algorithm from the Worst-Case Analysis tool. However there is no need to add any more to this test.

Range search algorithms are looking for solutions within the continuous range of the parameters, including the corners. With the exception of the Steepest Descent algorithm that only works with continuous range parameters, the range algorithms are able to perform hybrid searches, allowing certain parameters to be defined over a discrete set while others are defined over a continuous range. While the domain of a range search is infinite, the range algorithms are able to exploit dichotomy and neighborhood properties like gradient to find solutions.


Lab 15-11

Lab 15

As multiple algorithms can be stacked and evaluated in sequence, there is merit in performing a corner search before a range search. The corner search is quicker and should already position many of the parameters to their optimal value. That is particularly the case for parameters defined over a tight range, with little interaction with other parameters and which influence over the performance characteristics is monotonic. The range search can then more efficiently focus on the parameters with non-monotonic and/or interactive influence. The user also has the ability to run the search algorithm sequence a number of times ("Number of Loops"). This increases the chance that the global solution be found. The Worst-Case Analysis tool supports the following search algorithms:

Task 3.

Exhaustive Corner Search Sensitivity Corner Method Variable Neighborhood Search (VNS) Simulated Annealing Greedy Randomized Adaptive Search Procedures (GRASP) Genetic Algorithm Random Search with Interval Shrinkage Steepest Descent Downhill Simplex

Execute the Test

Now that the Worst-Case Analysis tool is setup, it’s time to start the analysis. 1.

Press the gear icon

2.

Change what gets displayed in the graph window to the power by selecting the drop-down menu in the top-right corner:

3.

As the analysis progresses notice the values for rnom(r.r1) and rnom(r.r2) as they converge to a value. Stop the evaluations by pressing the solution.

Lab 15-12

to start.

button when satisfied you have reached a good


Lab 15

Question 1.

What is the final value of power_max? _____________

Question 2.

What are the values of r.r1 ______ and r.r2?_________ The final values of the parameters are listed in the “Current” column above the graph window.

Task 4.

Create a WCA Test Based on Sensitivity Corner

1. Click and select New from the Worst-Case Analysis tool. 2. To save time and effort we will now copy the setup from the first test into test2. a. Place the cursor over test2. b. RMB click to bring up a menu. c. Select Copy from > MaxPwrRange 3. Rename test2 to MaxPwrCorner 4. Click to add the Sensitivity Corner algorithm and click OK to accept the defaults. 5. Uncheck or delete all Algorithms other than our newly added Sensitivity Corner. 6. Uncheck the MaxPwrRange test. 7. Reset the parameters to the nominal values by clicking on 8. Run the WCA for test MaxPwrCorner by clicking the gear icon Question 3.

What is the final value of power_max? _____________

Question 4.

What are the values of r.r1 ______ and r.r2?_________

Question 5.

Among the two WCA tests we created MaxPwrRange and MaxPwrCorner, which algorithm found the maximum power and why?


Lab 15-13

Lab 15

Task 5.

Plot and Analyze the Signals

1. Plot power_max vs. rnom(r.r1) a. Bring up the One-Dimensional Parameter Sweep tool by clicking on

. The tool is shown below.

b. Select power_max by clicking on the pulldown arrow to the right of the field Expression. c. Select :resdiv_wca:r.r1:rnom if not already selected. Notice that the domain is already filled in, however it is editable. d. Plot power_max vs :resdiv_wca:r.r1:rnom by clicking on Plot.

Notice that the value of power_max decreases monotonically with the resistance of r1. 2. Plot power_max vs. :resdiv_wca:r.r2:rnom. Hint, use the drop down arrow next to : resdiv_wca:r.r1:rnom.

Lab 15-14


Lab 15

Notice that the value of power_max is a non-monotonic function with respect to the resistance of r2. While not all circuits exhibit this behavior, it is an important observation of the deficiency associated with any corner analysis. 3. Close the One-Dimensional Parameter Sweep Tool.


Lab 15-15

Lab 15

4. Plot power_max vs. rnom(r.r1) and rnom(r.r2) a. Bring up the Two-Dimensional Parameter Sweep tool by clicking on . b. Select power_max by clicking on the pulldown arrow to the right of the field Expression. c. Plot power_max vs :resdiv_wca:r.r1:rnom and :resdiv_wca:r.r2:rnom.

If necessary, expand the tool for a better view. 4.

Lab 15-16

Close

the Two Dimensional Parameter Sweep tool.


Lab 15

5.

Switch back to the Range search test by selecting that tab.

Let’s create a new schematic and re-run the DC analysis with the new values. 6.

From the File > Export > Parameters...

menu item.. Choose New Schematic and click OK.

7.

Save the new schematic with a different name such as “ wc_power”

8.

You can close the WCA tool now to be able to view the new schematic better.

Notice that the new worst-case values are now annotated to the schematic. 9.

Run an operating point analysis and notice the voltage between the under this condition of maximum power dissipation.


Lab 15-17

Lab 15

When you’re done, close the Worst-Case Analysis tool.

Task 6. 1.

Close Out Lab #15 Close the design from the SaberRD button: Close > Close Design

2.

Lab 15-18

Close SaberRD.


Lab 15

Answers / Solutions Question 1.

0.08333 Watts

Question 2.

r1 = 3.0 ohms

Question 3.

0.08 Watts

Question 4.

R1 = 3.0 ohmsr2 = 4.5 ohms

Question 5.

Variable Neighborhood. Range search overcomes the limitations of a corner search.


r2= 3.0 ohms

Lab 15-19

SaberRD Electrical Lab Guide v1.7

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