structural units of embedded processor.pdf

Objectives • Descr Describe ibe struc structur tural al units units of a process processor. or.

Proces Proc esso sorr an and d Memory Organization

• Explain Explain various various types types of memory memory devices devices and . • Expla Explain in conc concept ept of memo memory ry map. map.

Asst. Prof. Suree Pumrin, Ph.D. Semester 1/2553

•

e ec e appropr a e processor, m crocon ro er, or DSP.

• Organize Organize the chosen chosen process processor, or, memories, memories, and interfacing circuit. 1

2142492 Selected Topics in Automotive Engineering I

Topics


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Structural Units in a Processor (1)

• Struc Structur ture e unit units s of of proc process essor or •

emory oc s or set elements

e a a-s ruc ures an

aa

• Conc Concep eptt of of mem memor ory y map map • Device Device regist registers ers and and address addresses es of I/O devices devices • Direc Directt mem memory ory acce access ss •

2142492 Selected Topics in

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Structural Units in a Processor (2) 1) 2) 3) 4) 6)

Internal and external buses interconnect the processor internal units with system memories, I/O devices and all other s stem elements Address, data and control buses MDR (memory data register) holds the accessed byte or wor MAR (memory address register) holds the address Program Counter or Instruction Pointer and Stack Pointer

Figur e 2.1 Block Diagram of structural units at a processor . 2142492 Selected Topics in Automotive Engineering I

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Structural Units in a Processor (3) 7)

9)

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Structural Units in a Processor (4)

ARS (Application Register Set): Set of on-chip registers for use in the application program. subset storing static variables and status words of a routine. Changing windows helps in fast context-switching in a program. and Floating Points operations Unit). FLPU associates a FLP register set for operations. FLPU. 2142492 Selected Topics in


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12) Instruction, Data and Branch Target Caches and associated PFCU (Prefetch control unit) for pre, instructions, respectively. into number of processor-instructions called atomic o erations AOs , AOU finishes the AOs before an interrupt of the process occurs - Prevents problems arising out of incomplete processor-operations on the s are a a n e programs


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Processor Performance

Structural Units in a Processor (5) 14) Advanced Processing units – (i) MAC, bit reversal and shifter units, VLIW processing unit in a DSP, (ii) Units , superscalar processing to boost the processing s eeds much hi her than one instruction er clock cycle.


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in Embedded System (1) 1) 2) 3) 4) 5) 6) 7) 8)


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in Embedded System (2) 9) On-chip DMA controller 10) Interrupt System 11) Advanced Processing Units 12) Harvard or Princeton Architectures for memory organ za on 13) RISC or CISC or RISC core with CISC like

Instruction Cycle Time Processing Performance per sec per W Internal Bus Width Caches and multi-way caches On-chip RAM and ROM Interrupt System Requirement of Floating Point instructions Requirement of Bit Manipulations instruction needs 2142492 Selected Topics in

1) MIPS – Million Instructions Per Second – Operations Per Second rys one s – um er o mes a benchmark program called Dhrystone program can run per second.[1MIPS = 1757 Dhrystone/s

14) On-chip compiler 16) IO Mapped IO space like 80x86 or Memory ma ed IOs 11


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Real-Time Control of a Robot Motor needs signal at the rate of 50 to 100 ms onl . Pro ram size is also limited. Low MIPS performance suffices. Therefore Microcontroller 8051, 68HC11, 68HC12 are the best choice. [Refer Example 2.2 pp. 63 for details]

Processor Selection Examples:


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e wor

Voice Data Compression Voice signals are 64kbps. High MIPS erformance needed. On-chi memor does not suffice for the resulting data. Therefore an exem lar rocessor needed is 80x86 or a DSP . . -



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w c ng ys em

Transfer rates of 100 Mbps from a switch . MIPS needed. Exemplary processors . [Refer Example 2.4 pp. 64 for details]

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Real Time Video Processing

Software Concept

- Needs fast frame compression units MACs needed. - Multiprocessor system having TMS DSP SHARC Ti erSHARC ARM9 or PowerPC processors needed. [Refer . .


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Memory of a Computer System Von Neumann Architecture

Memory Selection Examples Harvard Architecture


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u oma c

as ng

ac ne

Data Acquisition System

ee s mass manu ac ur ng ere ore masked ROM, needs EEPROM for current machine status, RAM for variables and stack onl A Microcontroller on-chip 256 byte RAM,

Data acquired to be stored at the flash kB ROM or EPROM for program memory, 512 B RAM .

.

suffice [Refer Example 2.6a pp. 69 for eas 2142492 Selected Topics in Automotive Engineering I

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g a camera

Set-top Box System

1024 color camera images need 64 kB , , .

Large ROM as well as large RAM, 16kB

- Camera with 1 GB memory stick can record image and sound both for several minutes.

memory


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, , Stacks of Memory Se ment wise memor allocation in four segments; Code, Data, Stack and Extra , ,

Segments and Blocks


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eren a a ruc ures a Memor Blocks 1

Memory

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e

1) Stacks – Return addresses on the nested calls, Sets of LIFO (Last In First Out retrievable data, Saved Contexts of the tasks as the stacks

Figur e 2.2 (a) The segment types and pages in an exemplary program 2142492 Selected Topics in

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e

2) Arrays – One dimensional or multidimensional 3 Figur e 2.3 An example of different stack structures at the memor blocks.


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ueues – Sets of FIFO First In First Out) retrievable data; Circular Queue Queue (Example- a network stack)


Figur e 2.4 An array at .

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e

4) Table – - first column points to another memory 6) List: In a list element, a data structure of an item also points to the next item 7 Process Control Block Refer Cha ter 8]


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Memory Map Ma to show the ro ram and data allocation of the addresses to ROM, RAM, or

as

n

e sys em

gure . 33


ev ce

resses

or e

ap

our memory a oca on maps. 34


vs

emory

appe

Device control and status addresses and are not re-locatable in a program as e g ue c rcu ar ware o accesses these is fixed during the c rcu es gn.


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emory

appe

or e

In memory mapped I/O, for example, in 8051 microcontroller, the devices have the addresses for processor-accesses

In I/O mapped I/O (Ported I/O), for example, in 80x86 rocessor the devices have the addresses for processor-accesses that

and are accessed with same set of

accessed by distinct set of instructions e er xamp e . or a er a ne Device on pp. 87-88]


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,

rec emory ccess Controller

,

and devices

External Devices can directly write and read into the blocks of RAM using the DMA , of the processor


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The rocessor, memor and devices are interfaced (glued) together using a ro rammable circuit like GAL or FPGA. The circuit consists of the address decoders as er the memor and device addresses allocated and the needed latches multi lexers demulti lexers


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Exercise 1. What are the common structure units in most 2. What are the special structural units in processors for di ital camera s stems real-time video rocessin systems, speech compression systems, voice compression systems, and video games? 3. What do you mean by device registers and device address?


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structural units of embedded processor.pdf

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