Synopsys PrimeTime - Introduction to Static Timing Analysis Workshop

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PrimeTime: Introduction to Static Timing Analysis Workshop

Synopsys Customer Education Services © 2002 Synopsys, Inc. All Rights Reserved Welcome Synopsys 34000-000-S16

34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

First Things First 

Welcome and Introductions

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Materials you should have:

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Student Guide

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Lab Guide

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PrimeTime Quick Reference

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Synopsys Online Documentation (SOLD) CD

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Breaks

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Facilities

Welcome Synopsys 34000-000-S16

PrimeTime: Introduction to Static Timing Analysis

Workshop Goal

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Use UsePrimeTime PrimeTimeto toperform performStatic StaticTiming TimingAnalysis Analysis(STA) (STA) on onaa“Functional “FunctionalCore” Core”prior priorto toPlace Placeand andRoute Route (P&R). (P&R). Obtain Obtainthe theprerequisite prerequisiteknowledge knowledgeto toattend attendthe the “PrimeTime: “PrimeTime:Chip ChipLevel LevelSTA” STA”workshop. workshop.

A/D

DSP

CODEC

Processor_CORE MPEG USB

RAM

Functional Core

Core Clock

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

Design Assumptions: 1. STA is performed on the Functional core only; Block level STA has been done in DC. (See Flow Diagram) 2. No scan chains yet (Flow diagram in PT:Chip level STA workshop) 3. Functional Core routing parasitic RCs (detailed SPEF) and sub block WLMs are available from early design planning (Chip level floor plan) 4. No clock tree synthesis yet (Flow diagram in PT:Chip level STA workshop) 5. Blocks may be either synthesized netlist or QTMs (will be covered if class time permits) 6. Functional Core has Logical hierarchical partitions (blocks) 7. No I/O pads, no BSD, no clock generation logic yet (Definition of Functional Core) 8. Chip specification is available (in Constraints modules) 9. Multiple Synch/Asynch clocks (in Constraints modules) 10. Multicycle paths (in Constraints modules) 11. Hold Time analysis is performed using Worst case PVT (as opposed to Best case PVT) (in Constraints modules) 12. No case analysis (absence of scan chains); no functional modes (Flow diagram in PT:Chip level STA workshop -- although it may apply to Functional CORE but is not discussed in this PT: ISTA)

Workshop Target Audience

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Design or Verification engineers who perform STA at the “functional core” level

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Little or no formal experience with PrimeTime

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Little or no formal experience with Design Compiler

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Planning to take the “PrimeTime: Chip level STA” workshop

You are here

PrimeTime: ISTA PrimeTime: CHIP Level CHIP Synthesis (Design Compiler)



Design or Verification engineers who perform STA at the “functional core” level. In addition to block level STA, you will handle functional core integration. Little or no formal experience with Design Compiler. If you have taken “CHIP Synthesis” or have experience using Design Compiler, do not attend this workshop: Take “PrimeTime: Chip Level STA” If your expectation is to learn DC as you’re expanding your portfolio to include synthesis, you should take the CHIP Synthesis workshop next and then PrimeTime: Chip Level STA. “PT:Chip Level STA Workshop” focuses on final, full chip, post route STA in order to achieve Timing closure.

What is Functional Core on a CHIP?

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TOP CLOCK-GEN PLL JTAG/BSD Logic ASYNCH LOGIC



MID

FUNC_CORE Synthesized Block1(wlm)

Synthesized Block2

Synthesized Block3

RAM (Timing model)

Functional CORE constitutes “most” of the CHIP containing: 

Synthesized logic blocks (Gate level netlist) and Models (RAMs)

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Functional core constraints are derived from Chip-level constraints

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Functional core level parasitics are extracted 

Extraction is done after a CHIP level floorplan and global routing Welcome



Parasitics are supplied in SPEF (Standard Parasitic Extraction Format). At the full-chip level one must consider the following issues: Model clock generation circuitry Analyze latch-based versus flip-flop design styles Functional vs. Test modes (Case analysis) Analyze PVT corners These issues are addressed in the “PrimeTime: Chip level STA” workshop.

Functional Core Integration – Pre-Layout

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Fully synthesized Functional Core. Chip-Level floorplan and constraints.

Units 4-6

Functional core interblock RC parasitics extracted.

Write Top-Level constraints and exceptions Read required files

Design Compiler Resynthesis

Unit 3 Fix data

yes

Errors/ Warnings? no

Units 1,8

Generate STA Reports

Timing violations

Place&Route



After synthesis of all sub-blocks, perform Chip level floorplan, global routing and extract the parasitic RCs between blocks within the Functional core. QTMs (or Timing models) may be used for the blocks for which synthesized gate level netlist is not available. Day-1: Objective: Using the basic 5 step STA flow, constrain all the Register to Register (Internal) timing paths within the functional core Day-2: Objectives:Using the 5 step STA flow, constrain all the I/O (interface) timing paths within the functional core and apply the necessary single clock cycle timing exceptions

PT Compatibility with other Tools

Design Compiler

Physical Compiler

Mapped netlist (using WLM)

Placed netlist

PrimeTime STAMP PathMill

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CHIP Architect

Parasitics, SDF 3rd Party Layout



What Will Be Covered

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Performing basic 5 step Static Timing Analysis (STA) flow on a functional core prior to P&R using PrimeTime GUI and shell (Units 1-3)

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Applying required constraints and exceptions and checking for missing constraints and ignored exceptions (Units 4-6)

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Creating a Quick Timing Model (Unit 7)

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Analyzing in detail for timing, design rules and timing bottlenecks (Unit 8)



Workshop Prerequisites

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Understanding of digital IC design

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Familiarity with UNIX, X-Windows and Unix-based text editor



Agenda: Day One DAY 1

Unit

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Register to Register Paths

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Welcome

1

Introduction to Static Timing Analysis

2

Writing Basic Tcl Constructs in PT

3

Reading Data

4

Constraining Internal Reg-Reg Paths

Lab



Unit 1 Objective:

Is to introduce Static Timing Analysis in PrimeTime by: Defining the 2 steps performed by a Static Timing Analyzer; Understanding under the hood calculation of cell and net delays based on NLDM (Non-Linear Delay Model) and WLM (Wire Load Model); Listing 4 types of timing paths; Identifying the path with the WNS (worst negative slack) or longest delay using the report_timing command; Interpreting results of the report_delay_calculation command and for cell and net timing arcs and Finding specific topics in SOLD using key word search. Unit 2 Objective:

Is to find Tcl syntax errors using the Tcl Syntax checker, to fix these errors and to obtain command and variable syntax information. Unit 3 Objective:

Is to create a basic PT setup file, read all the required files for STA and resolve errors and warnings associated with reading the files. Unit 4 Objective:

Is to create a Tcl script, which fully constrains internal Register-to-Register paths by Applying clock constraints and design environmental attributes; Modeling multiple synchronous/asynchronous clocks, Modeling pre-layout non ideal clocks, Invoking appropriate report commands to verify the correctness of constraints and Invoking a report to verify the completeness of constraints.

Agenda: Day Two DAY 2

Unit

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I/O Paths and Exceptions

Lab

5

Constraining I/O Interface Paths

6

Specifying Timing Exceptions

7

Introduction to Timing Models (QTM)

8

Performing STA

9

Summary

10

Customer Support Welcome



Unit 5 Objective: Is to create a Tcl script which fully constrains the Input/Output interface paths by applying port constraints and environmental attributes, modeling I/O data paths between multiple synchronous and asynchronous clock domains, modeling pre-layout non ideal clock effects, Invoking appropriate report commands to verify the correctness of constraints, Invoking a report to ensure the completeness of constraints and Identifying the effect of constraints on the path reported by a timing report. Unit 6 Objective: Is to Efficiently constrain a design for non-single-clock cycle behavior by Defining Timing exceptions, Modeling multi cycle path, Modeling logically false paths, W riting efficient constraints to model the above and Identifying a ny ignored exceptions and remove them. Unit 7 Objective: Is to Create a Quick Timing model using a given specification for use in PT by Defining what QTM is, Writing a QTM script to create a QTM library cell for the given specification and Modifying the link_path to use the QTM just created. Unit 8 Objective: Is to Apply three techniques in a systematic approach to analyze timing and design rule violations by Listing the 3 techniques in the appropriate order, Obtaining summary reports of all constraint violations and determining the next course of action, Identifying timing bottleneck blocks for re-synthesis. Enabling generation of Divide and conquer Timing reports to investigate what types of timing paths are causing violations (group_path) and Generating timing reports for setup check, hold check and showing the fanout, capacitance and transition time along the path. Unit 9 Objective: Is to list ways to improve the runtime and memory when using the STA flow in PT and summarize the workshop. Unit 10 Objective: Is to introduce you to our Customer Support Services.

Test For Understanding

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 In this class, what are the 2 types of blocks which you assume are

contained within the floor-planned Functional Core? _____________________ _____________________  In this class, how are the net parasitics (RC values) within

Functional Core modeled prior to Place and Route? Nets within a block __________________________ Nets between blocks

__________________________

 After attending this class, you will be able to perform Static Timing Analysis on:

(Circle all that apply) a.

Block (Module) level design that is either a mapped netlist or a timing model

b.

Functional CORE level design containing synthesized gate le vel blocks

c.

Functional CORE level design with some blocks described as an RTL verilog/VHDL file

d.

CHIP level design that has been placed and routed (P&R) Welcome



Abbreviations and Acronyms Acronym Acronym

Meaning Meaning

Acronym Acronym

STA STA

PVT PVT

DC DC

WLM WLM

PT PT

WNS WNS

GUI GUI

SPEF SPEF

Tcl Tcl

DRC DRC

SOLD SOLD

NLDM NLDM

QTM QTM

--

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Appendix

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Icons used in this workshop Conventions used in this workshop The Synopsys “Physical Synthesis Hierarchical Design Flow”



Icons Used in This Workshop (1/2)

Lab Exercise

Recommendation

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Group Exercise

Acronyms

For further reference



Icons Used in This Workshop (2/2)

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Question

Remember

Checklist

Caution

Hint, Tip or Suggestion

Note



Conventions Used in this Workshop Convention

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Description

Courier

Indicates command syntax.

Courier italic

Indicates a user-defined value in Synopsys.

Courier bold

Indicates user input—text you type verbatim—in Synopsys syntax and examples. (User input that is not Synopsys syntax, such as a user name or password you enter in a GUI, is indicated by regular text font bold.)

[ ]

Denotes optional parameters, such as pin1 [pin2 ... pinN]

|

Indicates a choice among alternatives, such as low | medium | high (This example indicates that you can enter one of three possible values for an option: low, medium, or high.)

Control-c

Indicates a keyboard combination, such as holding down the Control key and pressing c.

\

Indicates a continuation of a command line.

/

Indicates levels of directory structure or design’s hierarchy.

Edit > Copy

Indicates a path to a menu command, such as opening the Edit menu and choosing Copy.



The Synopsys Physical Synthesis Flow START START RTLand and RTL Chip Chip Constraints Constraints

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Objectives Develop a realizable floorplan for the chip and realistic design budgets for blocks

Design Planning Design

Create a placed design which passes STA. Perform an initial detail route of chip

Implementation

Design Refinement and Chip Finishing

ECO the P&R until it meets required performance specs for tapeout

END END



RTL (R egister Transfer Level) The Synopsys Physical Synthesis hierarchical design flow was created by the Synopsys Design Flow Group to help promote and ease the adoption of Synopsys design tools, as well as to provide feedback and drive enhancements of product performance and usability. The Synopsys Design Flow Group engages in customer partnerships from RTL to tapeout to drive success for multi-million gate designs. The flow encourages top-level floorplanning, power planning and global routing early in the flow followed by successive refinement of data and design until timing closure (i.e. the Design Planning, Design Implementation, and Design Refinement phases).

An Overview of Design Planning START START

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RTL, chip constraints

RTL, RTL, Chip Chip constraints constraints

Obtain Obtaintarget targetRTL RTL and toggle coverage and toggle coverage

CoverMeter Vera MC,

Planning

ACS

Implementation

compile compiledatapath datapath

synthesis synthesiswith withscan scan

BSDC

Design

CA

CA

Power PowerPlanning Planning

CA

Initial Initial pin pin assignment assignment

FV

JTAG JTAGinsertion insertion Die DieInitialization Initialization

CA

CA

IO IOPad Pad Assignment Assignment

CA

Design

Power PowerAnalysis Analysis

RTL RTLverification verification

VCS

Design

PP

FR

Refinement and Chip Finishing

CA A

END END

Floor-planning, Floor-planning, hierarchy manipulation hierarchy manipulation reshaping reshaping

ILM

Top-level ILM Top-level global globalrouting routingand and congestion analysis congestion analysis Top-level Top-level ILM repeater insertion repeater insertion Top-level Top-levelroute route estimation estimation Initial Initialblock block timing budget timing budget

New in 2.2 Welcome PrimeTime: Introduction to Static Timing Analysis


VCS

VCS Verilog Simulator

CA

Chip Architect

PP

PrimePower

FR

Flex Route

BSDC

BSD Compiler, Boundary Scan Synthesis

FV

Formal Verification (FM Formality)

MC

Module Compiler

ACS

Automatic Chip Synthesis

ILM

Interface Logic Model

An Overview of Design Implementation

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A

Block BlockLevel Level physical synthesis physical synthesis

START START RTL, RTL, Chip Chip constraints constraints

Low Power Low Power Optimization Optimization One Pass Scan One Pass Scan Placement Placement

PC

Design

Block BlockLevel Level Detail Routing Detail Routing

FV

PT

Top TopLevel Level ILM physical physicalsynthesis synthesis

Design Implementation

Low Power FV Low Power Optimization Optimization One Pass Scan One Pass Scan Placement ATPG Placement

PC

Chip Finishing

END END

timing OK

FV

no

Block Block level levelIPO IPO

PC

Chip ChipIntegration Integration

ILM CTC, STAMP

FV no

ECO ECO Route Route

RCRCcorrelation correlation

Top TopLevel LevelCTS CTS

Full FullChip ChipSTA STA ILM Placement handoff Placement handoff

Detail Router

yes

and Design PT

Router

Block BlockLevel Level STA STAand and ILM ILMcreation creation

timing OK ?

CA

Refinement

Detail

Block BlockLevel Level RC RCExtraction Extraction

ILM Generation Generation

PC

CTC

Arcadia

ILM

PT

Planning

Block BlockLevel LevelCTS CTS

Top TopLevel Level Detail DetailRoute Route

Detail Router

yes

New in 2.2

Welcome PrimeTime: Introduction to Static Timing Analysis


CTS

Clock Tree Synthesis

ECO

Engineering Change Order

PC

Physical Compiler

CTC

ClockTree Compiler

ATPG

Automatic Test Pattern Generation

IPO

In-Place Optimization

An Overview of Design Refinement Arcadia

START START RTL, RTL, Chip Chip constraints constraints

Top TopLevel Level Extraction Extraction Full FullChip ChipSTA STA

PT

ILM

timing OK

Arcadia

Blocks/Top Blocks/Top RC RCExtraction Extraction

PT

ILM Generation ILM Generation

PT

Full FullChip ChipSTA STA

no

yes

Design

PP

Planning PT

Design

Capture Capture Block BlockLevel Level Constraints Constraints

PT-SI

Implementation PC

Block Blocklevel level IPO, IPO,hold holdfix fix

ILM Top Toplevel level IPO, hold fix IPO, hold fix

Design Refinement and Chip Finishing

PC

Detail Router

Block BlockLevel Level ECO ECORoute Route

Top TopLevel Level ECO ECORoute Route Detail Router

END END New in 2.2

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Detail Router

SLE

timing OK yes

Final FinalPower Power Analysis Analysis Crosstalk Crosstalk Analysis Analysis Crosstalk Crosstalk Repair Repair GDSII GDSIIMerge Merge

Calibre

DRC DRC

Calibre

LVS LVS

SLE

ILM

Chip ChipFinishing Finishing Welcome PrimeTime: Introduction to Static Timing Analysis


SLE

Synopsys Layout Editor

LVS

Layout vs. Schematic

DRC

Design Rule Checker

GDSII

Graphics Design Standard Format II

Synopsys PrimeTime - Introduction to Static Timing Analysis Workshop

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