1
CHAPTER 1: INTRODUCTION 1.1 FAST FOURIER TRANSFORM A Fast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete Fourier Fourier Trans Transfor form m (DFT) (DFT) and its its invers inverse. e. There There are many many distin distinct ct FFT algori algorithm thmss involving a wide range of mathematics, from simple complex-numer arithmetic to group theory and numer theory. The fast Fourier Transform is a highly efficient procedure for computing the DFT of a finite series and re!uires less numer of computations than that of direct evaluation of DFT. "t reduces the computations y ta#ing advantage of the fact that the calculation of the coefficients of the DFT can e carried out iteratively. Due to this, FFT computation techni!ue is used in digital spectral analysis, filter simulation, autocorrelation and pattern recognition. The FFT is ased on decomposition and rea#ing the transform into smaller transforms and comining them to get the total transform. FFT reduces the computation time re!uired to compute a discrete Fourier transform and improves the performance y a factor of $%% or more over ov er direct evaluation of the DFT. A DFT DFT deco decomp mpos oses es a se!u se!uen ence ce of valu values es into into comp compon onen ents ts of diff differ eren entt fre!uencies. This operation is useful in many fields ut computing it directly from the definition is often too slow to e practical. An FFT is a way to compute the same result more !uic#ly& computing a DFT of N of N points points in the ovious way, using the definition, ta#es '( ) arithmetical operations, while an FFT can compute the same result in only '( N log N ) operations. N log N The difference in speed can e sustantial, especially for long data sets where N where N may e in the thousands or millions*in practice, the computation time can e reduced y several several orders orders of magnitude magnitude in such cases, and the improvement improvement is roughly roughly proportiona proportionall to N to N +log ( N N ). ). This huge improvement made many DFT-ased DFT-ased algorithms practical. FFTs are of great importance importance to a wide variety of applicatio applications, ns, from digital digital signal processing and solving solving partial partial different differential ial e!uations to algorithms algorithms for !uic# multiplic multiplication ation of large large integers. The most well #nown FFT algorithms algorithms depend upon the factoriat factoriation ion of N of N , ut there are FFT with ' ( N log log N ) complexi complexity ty for all N , even for prime prime N . any FFT algorithms only depend on the fact that is an N an N th primitive root of unity, and thus can e appli applied ed to analo analogou gouss tran transf sfor orms ms over over any fini finite te fiel field, d, such such as num numer er-t -the heor oret etic ic transforms. The Fast Fourier Transform algorithm exploit the two asic properties of the twiddl twiddlee factor factor - the symmet symmetry ry proper property ty and period periodici icity ty proper property ty which which reduce reducess the numer of complex multiplications re!uired to perform DFT. FFT algori algorithm thmss are ased ased on the fundam fundament ental al princi principle ple of decomp decomposi osing ng the computation of discrete Fourier Transform of a se!uence of length into successively smaller discrete Fourier transforms. There are asically two classes of FFT algorithms. A) Decimation "n Time (D"T) algorithm /) Decimation "n Fre!uency (D"F) algorithm. "n decimation-in-time, the se!uence for which we need the DFT is successively divided into smaller se!uences and the DFTs of these suse!uences are comined in a certain pattern to otain the re!uired DFT of the entire se!uence. "n the decimation-in-
2
fre!uency approach, the fre!uency samples of the DFT are decomposed into smaller and smaller suse!uences in a similar manner. The numer of complex multiplication and addition operations re!uired y the simple forms oth the Discrete Fourier Transform (DFT) and "nverse Discrete Fourier Transform ("DFT) is of order N order N as there are N are N data points to calculate, each of which re!uires N re!uires N complex arithmetic operations. The discrete Fourier transform (DFT) is defined y the formula& − j Π nK N −$ N 0 X ( K ) = ∑ x(n) • e n =% 1here 2 is an integer ranging from % to N to N 3 3 $. The algorithmic complexity of DFT will '( N ) ) and hence is not a very efficient method. "f we can4t do any etter than this then the DFT will not e very useful for the ma5ority of practical D67 application. 8owever, there are a numer of different 4Fast Fourier Transform4 (FFT) algorithms that enale the calculation the Fourier transform of a signal much faster than a DFT. As the name suggests, FFTs are algorithms for !uic# calculation of discrete Fourier transform of a data vector. The FFT is a DFT algorithm which reduces the numer of computations needed for N for N points points from '( N N 2) 2 ) to '( N log N ) wher wheree log log is the the ase ase- - loga logari rith thm. m. "f the the func functi tion on to e tran transf sfor orme med d is not not harmonically related to the sampling fre!uency, fre!uenc y, the response of an FFT loo#s li#e a 9sinc function (sin x (sin x)) + x. + x. The :adix- D"T algorithm rearranges the DFT of the function x function xn into two parts& a sum over the even-numered indices n ; m m and a sum over the odd-numered indices n ; m m < $&
'ne 'ne can can fact factor or a comm common on mult multip ipli lier er out out of the the seco second nd sum sum in the the e!uation. "t is the two sums are the DFT of the even-indexed part x part xm and the DFT of odd-indexed part x part xm < $ of the function x function xn. Denote the DFT of the E ven-indexed ven-indexed inputs xm y E y E k and the DFT of the Odd-indexed inputs x inputs xm < $ y Ok and we otain&
8owever, these smaller DFTs have a length of N of N +, +, so we need compute only N only N + + outputs& than#s to the periodicity properties of the DFT, the outputs for + = # = from a DFT of length N length N + + are identical identical to the outputs outputs for %= # = +. That is, E is, E k < N < N + + ; E k and Ok < N + ?ik ik ++ N @ called called a twiddle twiddle factor factor which which N + ; Ok . The phase factor exp> 3 ? ?iexp> 3 ?ik oeys the relation& exp> 3 ?i ?i(k < N < N + + ) + N + N @ ; e 3 ?i ?ik + N + N @ ; 3 exp> 3 ?ik ?ik + N + N @, @, flippi flipping ng the sign sign of the Ok < N + terms. Thus, the whole DFT can e calculated as follows&
3
This result, result, expressing expressing the DFT of length length N recursively recursively in terms of two DFTs of sie N sie N +, +, is the core of the radix- D"T fast Fourier transform. The algorithm gains its speed y re-using the results of intermediate computations to compute multiple DFT outputs. ote that final outputs are otained y a <+3 comination of E of E k and Ok exp( 3 ?ik ?ik + N + N ), ), which is simply a sie- DFT0 when this is generalied to larger radices elow, the sie- DFT is replaced y a larger DFT (which itself can e evaluated with an FFT).
This This proces processs is an exampl examplee of the general general techni techni!ue !ue of divide divide and con!uer con!uerss algori algorithm thms. s. "n many many tradi traditio tional nal implem implement entati ations ons,, however however,, the explic explicit it recurs recursion ion is avoided, and instead one traverses the computational tree in readth-first fashion. Fig 1.1 Decimation In Time FFT "n the D"T algorithm, the twiddle multiplication is performed efore the utterfly stage whereas for the D"F algorithm, the twiddle multiplication comes after the /utterfly stage.
Fig 1.2 : Decimation In Freqenc! FFT The 4:adix 4 algorithms algorithms are useful if N if N is a regular power of ( N ; ; p). p). "f we assume that algorithmic complexity provides a direct measure of execution time and that the relevant logarithm ase is then as shown in tale $.$, ratio of execution times for the (DFT) vs. (:adix FFT) increases tremendously with increase in . The The term term 4FFT 4FFT44 is actu actual ally ly slig slight htly ly ami amigu guous ous,, ecau ecause se ther theree are are sever several al commonly used 4FFT4 algorithms. There are two different :adix algorithms, the socalled 4Decimation in Time4 (D"T) and 4Decimation in Fre!uency4 (D"F) algorithms. /oth of these rely on the recursive decomposition of an N an N point transform into ( N N +) +) point transforms.
4
umer of 7oints,
omplex ultiplications in Direct computations,
omplex ultiplication in FFT Algorithm, (+) log
6peed improvement Factor
B
$C
B
B.%
CB
$
E.
$C
EC
.%
$%B
%
$.
CB
B%GC
$G
$.
$
$CB
BB
C.C
Ta"#e 1.1: Com$ari%on o& E'ection Time%( DFT ) Ra*i' + 2 FFT 1.2 ,UTTERF- STRUCTURES FOR FFT /asically FFT algorithms are developed y means of divide and con!uer method, the is depending on the decomposition of an point DFT in to smaller DFTs. "f is factored as ; r $,r ,r ..r H where r $;r ;I;r H;r, then r H ;. where r is called as :adix of FFFt algorithm.
"f r; , then if is called as radix- FFT algorithm,. The asic DFT is of sie of . The point DFT is decimated into point DFT y two ways such as Decimation "n Time (D"T) and Decimation "n Fre!uency (D"F) algorithm. /oth the algorithm ta#e the advantage of periodicity and symmetry property of the twiddle factor. − j )Π nK N W nK = e N The radix- decimation-in-fre!uency FFT is an important algorithm otained y the divide and con!uers approach. The Fig. $. elow shows the first stage of the -point D"F algorithm.
Fig. 1.1: Fir%t Stage o& / $oint Decimation in Freqenc! A#gorit0m.
5
The decimation, however, causes shuffling in data. The entire process involves v ; log N stages of decimation, where each stage involves N + utterflies of the type shown in the Fig. $..
Fig. 1.: ,tter&#! Sc0eme.
8ere
− j )Π nk
W nk
=e
N
is the Twiddle factor.
onse!uently, the computation of -point DFT via this algorithm re!uires ( N +) log N complex multiplications. For illustrative purposes, the eight-point decimation-in fre!uency algorithm is shown in the Figure elow. 1e oserve, as previously stated, that the output se!uence occurs in it-reversed order with respect to the input. Furthermore, if we aandon the re!uirement that the computations occur in place, it is also possile to have oth the input and output in normal order. The point Decimation "n fre!uency algorithm is shown in Fig $.E.
Fig. 1.: / $oint Decimation in Freqenc! A#gorit0m
6
CHAPTER 2: HARD3ATE DESCRIPTION -AN4UA4E 2.1 INTRODUCTION 8ardware Description Hanguage (8DH) is a language that can descrie the ehavior and structure of electronic system, ut it is particularly suited as a language to descrie the structure and the ehavior of the digital electronic hardware design, such as A6"s and F7JAs as well as conventional circuits. 8DH can e used to descrie electronic hardware at many different levels of astraction such as Algorithm, :egister transfer level (:TH) and Jate level. Algorithm is un synthesiale, :TH is the input to the synthesis, and Jate Hevel is the input from the synthesis. "t is often reported that a large numer of A6" designs meet their specification first time, ut fail to wor# when plunged into a system. 8DH allows this issue to e addressed in two ways, a 8DH specification can e executed in order to achieve a high level of confidence in its correctness efore commencing design and may simulate one specification for a part in the wider system context(Kg&- 7rinted ircuited /oard 6imulation). This depends upon how accurately the specialiation handles aspects such as timing and initialiation. 2.2 AD5ANTA4ES OF HDA design methodology that uses 8DHs has several fundamental advantages over traditional Jate Hevel Design ethodology. The following are some of the advantages& 'ne can verify functionality early in the design process and immediately simulate • the design written as a 8DH description. Design simulation at this high level, efore implementation at the Jate Hevel allows testing architectural and designing decisions. F7JA synthesis provides logic synthesis and optimiation, so one can • automatically convert a L8DH description to gate level implementation in a given technology. 8DH descriptions provide technology independent documentation of a design and • its functionality. A 8DH description is more easily read and understood than a net-list or schematic description. 8DHs typically support a mixed level description where structural or net-list • constructs can e mixed with ehavioral or algorithmic descriptions. 1ith this mixed level capailities one can descrie system architectures at a high level or gate level implementation. 2.6 5HDL8DH is a hardware description language. "t descries the ehavior of an electronic circuit or system, from which the physical circuit or system can then e attained. L8DH stands for L86" 8ardware Description Hanguage. L86" is itself an areviation for Lery 8igh 6peed "ntegrated ircuits, an initiative funded y Mnited 6tates Department of Defense in the $G%s that led to creation of L8DH. "ts first version was L8DH N, later upgraded to the L8DH G. L8DH was the original and first hardware description language to e standardied y "nstitute of Klectrical and Klectronics Kngineers, through the "KKK $%NC standards. An additional standard, the "KKK $$CB, was later added to introduce a multi-valued logic system.
7
L8DH is intended for circuit synthesis as well as circuit simulation. 8owever, though L8DH is fully simulatale, not all constructs are synthesiale. The two main immediate applications of L8DH are in the field of 7rogrammale Hogic Devices and in the field of A6"s (Application 6pecific "ntegrated ircuits). 'nce the L8DH code has een written, it can e used either to implement the circuit in a programmale device or can e sumitted to a foundry for farication of an A6" chip. L8DH is a fairly general-purpose language, and it doesn4t re!uire a simulator on which to run the code. There are many L8DH compilers, which uild executale inaries. "t can read and write files on the host computer, so a L8DH program can e written that generates another L8DH program to e incorporated in the design eing developed. /ecause of this general-purpose nature, it is possile to use L8DH to write a test bench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. The #ey advantage of L8DH when used for systems design is that it allows the ehavior of the re!uired system to e descried (modeled) and verified (simulated) efore synthesis tools translate the design into real hardware (gates and wires). The L8DH statements are inherently concurrent and the statements placed in a 7:'K66, FMT"' or 7:'KDM:K are executed se!uentially. 2. EDA Too#% There are several KDA (Klectronic Design Automation) tool availale for circuit synthesis, implementation and simulation using L8DH. 6ome tools are offered as part of a vendors design suite such as Alteras Ouatus "" which allows the synthesis of L8DH code onto Alteras 7HD+F7JA chips, or Pilinxs "6K suite, for Pilinxs 7HD+F7JA chips. "6KQ WebPACK™ design software is the industryRs only F:KK, fully featured front-to ac# F7JA design solution for Hinux, 1indows P7, and 1indows Lista. "6K WebPACK is the ideal downloadale solution for F7JA and 7HD design offering 8DH synthesis and simulation, implementation, device fitting, and STAJ programming. "6K WebPACK delivers a complete, front-to-ac# design flow providing instant access to the "6K features and functionality at no cost. Pilinx has created a solution that allows convenient productivity y providing a design solution that is always up to date with error-free downloading and single file installation.
8
CHAPTER 6: DESI4N OF FFT 6.1 IMP-EMENTATION OF 178POINT FFT ,-OC9S The FFT computation is accomplished in three stages. The x(%) until x($E) variales are denoted as the input values for FFT computation and P(%) until P($E) are denoted as the outputs. The pipeline architecture of the $C point FFT is shown in Fig B.$ consisting of utterfly schemes in it. There are two operations to complete the computation in each stage.
Fig 6.1: Arc0itectre o& 17 $oint FFT. The upward arrow will execute addition operation while downward arrow will execute sutraction operation. The sutracted value is multiplied with twiddle factor value efore eing processed into the next stage. This operation is done concurrently and is #nown as utterfly process. The implementation of FFT flow graph in the L8DH re!uires three stages, final computation is done and the result is sent to the variale (%) to ($E). K!uation in each stage is used to construct scheduling diagram. For stage one, computation is accomplished in three cloc# cycles denoted as 6% to 6.The operation is much simpler compared with FFT. This is ecause FFT processed oth real and imaginary value. The result from FFT is represented in real and imaginary value ecause of the multiplication of twiddle factor. Twiddle factor is a constant defined y the numer of point used in this transform. This scheduling diagram is derived from the e!uations otain in FFT signal flow graph. The rest of the scheduling diagrams can e s#etched in the same way as shown in figure B.. Thus each stage re!uires a cloc# cycle and totally three cloc# cycles are needed. 6cheduling diagrams are a part of ehavioral modeling and 6ynthesis steps to translate the algorithmic description into :TH (register transfer level) in L8DH design.
9
6.2 DESI4N OF A 4ENERA- RADI82 FFT USIN4 5HDAs we move to higher-point FFTs, the structure for computing the FFT ecomes more complex and the need for an efficient complex multiplier to e incorporated within the utterfly structure arises. 8ence we propose an algorithm for an efficient complex multiplier that overcomes the complication of using complex numers throughout the process. A radix- FFT can e efficiently implemented using a utterfly processor which includes, esides the utterfly itself, an additional complex multiplier for the twiddle factors. A radix- utterfly processor consists of a complex adder, a complex sutraction, and a complex multiplier for the twiddle factors. The complex multiplication with the twiddle factor is often implemented with four real multiplications and add + sutract operations. Norma# Com$#e' O$eration: (P<5) (< 56) ; P < 56P < 5 - 6 ; P U 6 < 5 (6P < ) :eal 7art : ; P U 6 "maginary 7art " ; 6P < Msing the twiddle factor multiplier that has een developed, it is possile to design a utterfly processor for a radix- ooley-Tu#ey FFT. 8ence this asic structure of radix- FFT can e used as a uilding loc# to construct higher -point FFTs. This structure has een developed as an extension to provide for the computation of higher value index FFTs.
10
CHAPTER : 5HD- IMP-EMENTATION .1 DESI4N SOFT3ARE The implementations have een carried out using the software, Pilinx "6K G.i. The hardware language used is the Lery 8igh 6peed "ntegrated ircuit 8ardware Description Hanguage (L8DH). L8DH is a widely used language for register transfer level description of hardware. "t is used for design entry, compile and simulation of digital systems. .2 INTERFACE The architectural design consist of data inputs, control unit, cloc#s and the data output. The register may e of the array of four or eight variale in the type of real. The FFT implementation in L8DH consists of three states such as start, load and run.
.6 De%ign Smmar!
11
CHAPTER : RESU-TS
The simulation of this whole pro5ect has een done using the Pilinx "6K of version G.i. Pilinx "6K is a simulation tool for programming VLH6"W VA6"Ws, VF7JAWs, V7HDWs, and V6oWs. "t provides a comprehensive simulation and deug environment for complex A6" and F7JA designs. 6upport is provided for multiple languages including Lerilog, 6ystemLerilog, L8DH and 6ystem. .1 SIMU-ATION RESU-T O,TAINED
12
CHAPTER 7: CONC-USION AND FUTURE SCOPE 7.1. CONC-USION This pro5ect descries the efficient use of L8DH code for the implementation of radix ased FFT architecture and the wave form result of the various stages has een otained successfully. The accuracy in otained results has een increased with the help of efficient coding in L8DH. The accuracy in results depends upon the e!uations otained from the utterfly diagram and then on the correct drawing of scheduling diagrams ased on these e!uations. 7.2. FUTURE SCOPE The future scopes of this pro5ect are to implement the proposed FFT architecture using Field-7rogrammale Jate Arrays (F7JAs). The FFT (Fast Fourier Transform) processor plays a critical part in speed and power consumption of the 'rthogonal Fre!uency Division ultiplexing ('FD) communication system. Thus the FFT loc# can e implemented in 'FD.
13
CHAPTER ;: 5HD- CODE To$ rt# + %!nt0
entity synthXmain is port ( dataXio & in stdXlogicXvector($ downto %)0 finalXop & out stdXlogicXvector($ downto %) 0 cloc#Xmain,cloc#,enl,reset,init & in stdXlogic) 0 end synthXmain 0 architecture rtl of synthXmain is signal shft , waves & stdXlogicXvector( downto %) 0 component sutractor port ( a & in stdXlogicXvector ($ downto %) 0 & in stdXlogicXvector ($ downto %) 0 cloc# , rstXsu , suXen & in stdXlogic 0 aXsmaller , finXsu , numXero & out stdXlogic 0 eroXdetect & out stdXlogicXvector($ downto %) 0 su & out stdXlogicXvector ( downto %)0 change & out stdXlogic ) 0 end component 0 component swap port ( a & in stdXlogicXvector ($ downto %) 0 & in stdXlogicXvector ($ downto %) 0 cloc# & in stdXlogic 0 rstXswap , enXswap & in stdXlogic 0 finishXswap & out stdXlogic 0 d & out stdXlogicXvector ($ downto %) 0 largeXexp & out stdXlogicXvector (N downto %) 0 c & out stdXlogicXvector ( downto % ) ) 0 end component 0
component shift port ( suXcontrol & in stdXlogicXvector ( downto %) 0
14
cXin & in stdXlogicXvector ( downto %) 0 shiftXout & out stdXlogicXvector ($ downto %) 0 cloc# , shiftXen , rstXshift & in stdXlogic 0 finishXout & out stdXlogic ) 0 end component 0 component controlXmain port ( aXsmall , signXa , signX & in stdXlogic 0 signXout , addXsu , resetXall & out stdXlogic 0 enXsu , enXswap , enXshift , addpulse , normalise & out stdXlogic 0 finXsu , finXswap , finishXshift , addXfinish , endXall & in stdXlogic 0 cloc#Xmain , cloc# , reset , enl , eroXnum , change & in stdXlogic ) 0 end component 0 component summer port ( num$ , num & in stdXlogicXvector ($ downto %) 0 exp & in stdXlogicXvector (N downto %) 0 addpulseXin , addsu , rstXsum & in stdXlogic 0 addXfinish & out stdXlogic 0 sumout & out stdXlogicXvector ( downto %) ) 0 end component 0 component normalie port ( a , & in stdXlogicXvector ($ downto %) 0 num & in stdXlogicXvector ( downto %) 0 exp & in stdXlogicXvector (N downto %) 0 signit , addsu , cloc# , enXnorm , rstXnorm & in stdXlogic 0 eroXdetect & in stdXlogicXvector($ downto %) 0 exitXn & out stdXlogic 0 normalXsum & out stdXlogicXvector ($ downto %) ) 0 end component 0 component utXgen port ( addXincr , addXclear , stagedone & in stdXlogic 0 utXutterfly & out stdXlogicXvector( downto %) ) 0 end component 0 component stageXgen port ( addXstaged , addXclear & in stdXlogic 0 stXstage & out stdXlogicXvector($ downto %) ) 0 end component 0
15
component iodXstaged is port ( utXfly & in stdXlogicXvector( downto %) 0 stageXno & in stdXlogicXvector($ downto %) 0 addXincr , ioXmode & in stdXlogic 0 addXiod , addXstaged , addXfftd & out stdXlogic 0 utterflyXiod & out stdXlogicXvector( downto %) ) 0 end component 0 component aseindex port ( indXutterfly & in stdXlogicXvector( downto %) 0 indXstage & in stdXlogicXvector($ downto %) 0 addXfft & in stdXlogic 0 fftaddXrd & out stdXlogicXvector( downto %) 0 c% , c$ , c , c & in stdXlogic ) 0 end component 0 component ioaddXgen port ( ioXutterfly & in stdXlogicXvector( downto %) 0 addXiomode , addXip , addXop & in stdXlogic 0 aseXioadd & out stdXlogicXvector( downto %) ) 0 end component 0 component muxXadd port ( a , & in stdXlogicXvector( downto %) 0 sel & in stdXlogic 0 ! & out stdXlogicXvector( downto %) ) 0 end component 0 component ramXshift port ( dataXin & in stdXlogicXvector( downto %) 0 cloc#Xmain & in stdXlogic 0 dataXout & out stdXlogicXvector( downto %) ) 0 end component 0 component cycles port ( cloc#Xmain , preset , c%Xen , cyclesXclear & in stdXlogic 0 waves & out stdXlogicXvector( downto %) ) 0 end component 0
16
component counter port ( c & out stdXlogicXvector( downto %) 0 disale , cloc#Xmain , reset & in stdXlogic) 0 end component 0
component multXcloc# port ( cloc#Xmain , mult$Xc% , mult$Xiomode , multXclear & in stdXlogic 0 mult$Xaddincr & out stdXlogic ) 0 end component 0 component contXgen port ( conXstaged , conXiod , conXfftd , conXinit & in stdXlogic 0 conXip , conXop , conXiomode , conXfft & out stdXlogic 0 conXenw , conXenor , c%Xenale , conXpreset & out stdXlogic 0 conXclear , disale & out stdXlogic 0 c% , cloc#Xmain & in stdXlogic 0 enXrom , enXromgen , resetXcounter & out stdXlogic 0 conXcl#count & in stdXlogicXvector( downto %) ) 0 end component 0 component andXgates port ( wavesXand & in stdXlogicXvector( downto %) 0 cloc#Xmain , c%Xen & in stdXlogic 0 c%,c$,c,c & out stdXlogic 0 c%Xc$,cXc,c%Xc,c$Xc & out stdXlogic ) 0 end component 0 component rXloc# port ( data & in stdXlogicXvector($ downto %) 0 trigger & in stdXlogic 0 rXout & out stdXlogicXvector($ downto %) ) 0 end component 0 component lXloc# port ( dataXl & in stdXlogicXvector($ downto %) 0 triggerXl & in stdXlogic 0 lXout & out stdXlogicXvector($ downto %) ) 0 end component 0
17
component levelXedge port ( dataXedge & in stdXlogicXvector($ downto %) 0 triggerXedge & in stdXlogic 0 edgeXout & out stdXlogicXvector($ downto %) ) 0 end component 0 component mux port ( d% , d$ & in stdXlogicXvector($ downto %) 0 muxXout & out stdXlogicXvector($ downto %) 0 choose & in stdXlogic ) 0 end component 0 component negate port ( negXin & in stdXlogicXvector($ downto %) 0 negXen , cloc#Xmain & in stdXlogic 0 negXout & out stdXlogicXvector($ downto %) ) 0 end component 0 component multiply port( numXmux , numXrom & in stdXlogicXvector($ downto %) 0 cloc# & in stdXlogic 0 multXout & out stdXlogicXvector($ downto %) ) 0 end component 0 component divide port ( dataXin & in stdXlogicXvector($ downto %) 0 dataXout & out stdXlogicXvector($ downto %) ) 0 end component 0 component romaddXgen is port ( ioXrom,c%,c$,c,c & in stdXlogic 0 stageXrom & in stdXlogicXvector($ downto %) 0 utterflyXrom & in stdXlogicXvector( downto %) 0 romadd & out stdXlogicXvector( downto %) 0 romgenXen & in stdXlogic )0 end component 0 component regXdpram is port ( dataXfft , dataXio & in stdXlogicXvector ($ downto %)0
18
! & out stdXlogicXvector ($ downto %)0 cloc# , ioXmode & in stdXlogic0 we , re & in stdXlogic0 waddress& in stdXlogicXvector ( downto %)0 raddress& in stdXlogicXvector ( downto %))0 end component 0 component rom is port ( cloc# , enXrom & in stdXlogic 0 romadd & in stdXlogicXvector( downto %) 0 romXdata & out stdXlogicXvector($ downto %) ) 0 end component 0 '7'KT printXresult is 7':T( cloc# & " stdXlogic0 op & " stdXlogic0 finXres & 'MT stdXlogicXvector($ downto %)0 result & " stdXlogicXvector($ downto %))0 end component 0 egin result& printXresult port map (cloc#Xmain, op,finalXop,ramXdata )0 ut & utXgen port map (incr , clear , staged ,utterflyXiod) 0 stg & stageXgen port map (staged , clear , stage) 0 iodXstgd & iodXstaged port map(utterflyXiod,stage,incr,ioXmode,iod,staged,fftd,utterfly) 0 ase & aseindex port map (utterfly , stage , fftXen , fftaddXrd , c% , c$ , c , c) 0 ioadd & ioaddXgen port map (utterfly , ioXmode , ip , op , ioXadd) 0 ramXshift$ & ramXshift port map (fftaddXrd , cloc#Xmain , shift$) 0 ramXshift & ramXshift port map (shift$ , cloc#Xmain , shft) 0 ramXshift & ramXshift port map (shft , cloc#Xmain , shift) 0 ramXshiftB & ramXshift port map (shift , cloc#Xmain ,shiftB) 0 ramXshiftE & ramXshift port map (shiftB , cloc#Xmain , shiftE) 0 --ramXshiftC & ramXshift port map (shiftE , cloc#Xmain , shiftC) 0 multx$ & muxXadd port map (shiftE , ioXadd , ioXmode , ramXwr) 0 multx & muxXadd port map (fftaddXrd , ioXadd , ioXmode , ramXrd) 0 cyc & cycles port map (cloc#Xmain , preset , c%Xen , cycXclear , waves) 0 gates & andXgates port map(waves,cloc#Xmain,c%Xen,c%,c$,c,c,c%Xc$,cXc,c%Xc,c$Xc) 0 cnt & counter port map (cl#Xcount , disale , cloc#Xmain , resetXcount) 0 muxXcloc# & multXcloc# port map (cloc#Xmain , c% , ioXmode , clear , incr) 0 control & contXgen port map (staged , iod , fftd , init , ip , op , ioXmode , fftXen ,
19
enw , enor , c%Xen , preset , clear , disale , c% , cloc#Xmain ,romXen,romgenXen,resetXcount,cl#Xcount) 0 regXram & regXdpram port map (outXdata,dataXio,ramXdata,cloc#Xmain,ioXmode,enw,enor,ramXwr,ramXrd) 0 f$ & rXloc# port map (ramXdata , c% , d) 0 f & lXloc# port map (ramXdata , c$ , d) 0 f & rXloc# port map (ramXdata , c , dB) 0 fB & rXloc# port map (ramXdata , c , dE) 0 fE & rXloc# port map (d , c$Xc , dG) 0 fC & lXloc# port map (d , c%Xc , d$%) 0 fN & lXloc# port map (d$ , c , d$) 0 f & lXloc# port map (d$ , c$ , d$B) 0 fG & rXloc# port map (d$N , cloc#Xmain , d$) 0 f$% & rXloc# port map (dataXrom , cloc#Xmain , romXff) 0 mux$ & mux port map (d , d , dC , cXc) 0 mux & mux port map (dB , dE , dN , c$Xc) 0 mux & mux port map (d$ , d$B , d$E , c$Xc) 0 neg$ & negate port map (d$% , c%Xc$ ,cloc#Xmain , d$$) 0 neg & negate port map (d$E , c%Xc$ ,cloc#Xmain , d$C) 0 mult$ & multiply port map (dC , romXff , cloc#Xmain , d) 0 div & divide port map (d$ , d$G) 0 f$$ & levelXedge port map (d$G,cloc#Xmain,outXdata) 0 romXadd$ & romaddXgen port map (ioXmode,c%,c$,c,c,stage,utterfly,romXadd,romgenXen) 0 rom$ & rom port map (cloc# ,romXen,romXadd,dataXrom) 0 $$ & sutractor port map ( d$C , dN , cloc# , rst , ensu , aXsmall , finsu , numero , erodetect , su , change) 0 & swap port map ( a;Yd$C , ;YdN , cloc#;Ycloc# , rstXswap;Yrst , enXswap;Yenswap , finishXswap;Yfinswap , d;YswapXnum , largeXexp;Yexp , c;YswapXnum$ ) 0 B & shift port map (suXcontrol;Ysu , cXin;YswapXnum$ , shiftXout;YshiftXout , cloc#;Ycloc# , shiftXen;Yenshift, rstXshift;Yrst , finishXout;Yfinshift ) 0 E & controlXmain port map ( aXsmall , d$C($) , dN($) , signit , addsu , rst , ensu , enswap , enshift , addpulse , normalise , finsu , finswap , finshift ,finishXsum , endXall , cloc#Xmain , cloc# , reset , enl , numero , change ) 0 C & summer port map ( shiftXout , swapXnum , exp , addpulse , addsu , rst , finishXsum , sumXout ) 0 N & normalie port map (d$C , dN , sumXout , exp , signit , addsu , cloc# , normalise , rst , erodetect , endXall , d$N) 0
20
a$ & sutractor port map ( dG , d$$ , cloc# , rst , ensu , aXsmall , finsu , numero , erodetect , sua , changea) 0 a & swap port map (dG ,d$$ ,cloc# ,rst ,enswap , finswap ,swapXnum , exp , swapXnum$ )0 aB & shift port map (sua ,swapXnum$ ,shiftXouta ,cloc# , enshift , rst , finshift ) 0 aE & controlXmain port map ( aXsmall , dG($) , d$$($) , signit , addsu , rst , ensu , enswap , enshift , addpulse , normalise , finsu , finswap , finshift ,finishXsum , endXall , cloc#Xmain , cloc# , reset , enl , numero , changea ) 0 aC & summer port map ( shiftXouta , swapXnum , exp , addpulse , addsu , rst , finishXsum , sumXout ) 0 aN & normalie port map (dG , d$$ , sumXout , exp , signit , addsu , cloc# , normalise , rst , erodetect , endXall , d$) 0 end rtl 0 Te%t"enc0 &i#e + %!nt0
KT"T t "6 KD t0 A:8"TKTM:K testenchXarch 'F t "6 F"HK :K6MHT6& TKPT '7K 1:"TKX'DK "6 Zresults.txtZ0 '7'KT synthXmain 7':T ( dataXio & "n stdXlogicXvector ($ DownTo %)0 finalXop & 'ut stdXlogicXvector ($ DownTo %)0 cloc#Xmain & "n stdXlogic0 cloc# & "n stdXlogic0 enl & "n stdXlogic0 reset & "n stdXlogic0 init & "n stdXlogic )0 KD '7'KT0 6"JAH dataXio & stdXlogicXvector ($ DownTo %) &; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z0
21
6"JAH finalXop & stdXlogicXvector ($ DownTo %) &; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z0 6"JAH cloc#Xmain & stdXlogic &; 4%40 6"JAH cloc# & stdXlogic &; 4%40 6"JAH enl & stdXlogic &; 4%40 6"JAH reset & stdXlogic &; 4%40 6"JAH init & stdXlogic &; 4%40 constant 7K:"'DXcloc# & time &; %% ns0 constant DMTXHKXcloc# & real &; %.E0 constant 'FF6KTXcloc# & time &; $%% ns0 constant 7K:"'DXcloc#Xmain & time &; %% ns0 constant DMTXHKXcloc#Xmain & real &; %.E0 constant 'FF6KTXcloc#Xmain & time &; % ns0 /KJ" MMT & synthXmain 7':T A7 ( dataXio ;Y dataXio, finalXop ;Y finalXop, cloc#Xmain ;Y cloc#Xmain, cloc# ;Y cloc#, enl ;Y enl, reset ;Y reset, init ;Y init )0 process variale i & integer &; % 0 egin for i in $ to $%%% loop cloc# =; 4$4 0 wait for E ns 0 cloc# =; 4%4 0 wait for E ns 0 end loop 0 end process 0 process variale 5 & integer &; % 0 egin for 5 in $ to $%%% loop cloc#Xmain =; 4$4 0 wait for %% ns 0 cloc#Xmain =; 4%4 0 wait for %% ns 0
22
end loop 0 end process 0 process file vectorXfile & text open readXmode is ZJ&[PilinxGi[pro5ects[pro5XfftX""[romXram.vhdZ 0 variale l , l & line 0 variale ! , p & integer &; % 0 variale count & integer 0 variale tXa , tX & stdXlogicXvector ($ downto %) 0 variale space & character 0 egin while not endfile(vectorXfile) loop --for count in $ to $C loop ! &; $ 0 readline(vectorXfile , l) 0 for p in $ to loop -- data from :A read(l , tX(!)) 0 ! &; ! - $ 0 end loop 0 ! &; $ 0 dataXio =; tX($ downto %) 0 wait for B%% ns 0 end loop 0 wait for ms 0 --wait for CE% ns 0 end process0 -- process to reset process egin reset =; 4$4 0 enl =; 4$4 0 wait for $% ns 0 reset =; 4%4 0 wait 0 end process 0 process egin init =; 4$4 0 wait for $E ns 0 init =; 4%4 0
23
wait 0 end process 0
KD testenchXarch0
24
%>a$.=0* -- 61A 6 1A7 7 M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity swap is port ( a & in stdXlogicXvector ($ downto %) 0 & in stdXlogicXvector ($ downto %) 0 cloc# & in stdXlogic 0 rstXswap , enXswap & in stdXlogic 0 finishXswap & out stdXlogic 0 d & out stdXlogicXvector ($ downto %) 0 largeXexp & out stdXlogicXvector (N downto %) 0 c & out stdXlogicXvector ( downto % ) ) 0 end swap 0 architecture rtl of swap is egin process (a , , cloc# , rstXswap , enXswap) variale x , y & stdXlogicXvector (N downto %) 0 variale p , ! & stdXlogicXvector ( downto %) 0 egin if(rstXswap ; 4$4 ) then c =; 4%4 \ a( downto %) \ Z%%%%%%%%%Z 0 finishXswap =; 4%4 0 elsif(rstXswap ; 4%4) then if(enXswap ; 4$4) then x &; a (% downto ) 0 y &; (% downto ) 0 p &; a ( downto %) 0 ! &; ( downto %) 0 if (cloc# ; 4$4) then if (x = y) then c =; 4$4 \ a ( downto %) \ Z%%%%%%%%%Z 0 -- 4$4 for chec#ing d =; 4$4 \ ( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit one largeXexp =; (% downto ) 0 finishXswap =; 4$4 0 elsif (y = x) then c =; 4$4 \ ( downto %) \ Z%%%%%%%%%Z 0 d =; 4$4 \ a ( downto %) \ Z%%%%%%%%Z Z%%%%%%% %Z 0 -- 4$4 for implicit $. largeXexp =; a (% downto ) 0
25
finishXswap =; 4$4 0 elsif ( (x;y) and (p = !)) then c =; 4$4 \ a ( downto %) \ Z%%%%%%%%%Z 0 -- 4$4 for chec#ing d =; 4$4 \ ( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit one largeXexp =; (% downto ) 0 finishXswap =; 4$4 0 else c =; 4$4 \ ( downto %) \ Z%%%%%%%%%Z 0 d =; 4$4 \ a ( downto %) \ Z%%%%%%%%Z Z%%%%%%% %Z 0 -- 4$4 for implicit $. largeXexp =; a (% downto ) 0 finishXswap =; 4$4 0 end if 0 end if 0 end if 0 end if 0 end process0 end rtl0
26
%mmer.=0* -- 6MK: lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity summer is port ( num$ , num & in stdXlogicXvector ($ downto %) 0 exp & in stdXlogicXvector (N downto %) 0 addpulseXin , addsu , rstXsum & in stdXlogic 0 addXfinish & out stdXlogic 0 sumout & out stdXlogicXvector ( downto %) ) 0 end summer 0 architecture rtl of summer is egin process (num$ , num , addpulseXin , rstXsum) variale tempXnum$ , tempXsum , tempXnum , tempXsum , res & stdXlogicXvector ( downto %)0 variale tempXexp & stdXlogicXvector (N downto %) 0 egin if (rstXsum ; 4%4) then if (addpulseXin ; 4$4) then tempXnum$ &; 4%4 \ num$ ($ downto %) 0 --% to find whether normalisation is re!uired. tempXnum &; 4%4 \ num ($ downto %) 0 --if re!uired 6/ will e $ after addition if (addsu ; 4$4) then tempXsum &; tempXnum$ < tempXnum 0 sumout =; tempXsum 0 addXfinish =; 4$4 0 else tempXsum &; tempXnum - tempXnum$ 0 --res &; tempXsum < tempXnum$ 0 sumout =; tempXsum 0 addXfinish =; 4$4 0 end if 0 end if 0 elsif (rstXsum ; 4$4) then addXfinish =; 4%40 end if 0 end process 0
27
end rtl 0
28
%"tractor.=0* -- 6M/T:AT': M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity sutractor is port ( a & in stdXlogicXvector ($ downto %) 0 & in stdXlogicXvector ($ downto %) 0 cloc# , rstXsu , suXen & in stdXlogic 0 aXsmaller , finXsu , numXero & out stdXlogic 0 eroXdetect & out stdXlogicXvector($ downto %) 0 su & out stdXlogicXvector ( downto %) 0 change & out stdXlogic ) 0 end sutractor 0 architecture rtl of sutractor is egin process (a , , cloc# , rstXsu , suXen) variale temp ,c , d & stdXlogicXvector (N downto %) 0 variale e , f & stdXlogicXvector ( downto %) 0 egin if (rstXsu ; 4%4) then c &; a (% downto ) 0 d &; (% downto ) 0 e &; a ( downto %) 0 f &; ( downto %) 0 if(suXen ; 4$4) then if (cloc# ; 4$4) then if ((c;%)) then eroXdetect =; Z%$Z 0 numXero =; 4$4 0 elsif ((d;%)) then eroXdetect =; Z$%Z 0 numXero =; 4$4 0 elsif (c = d ) then temp &; d - c 0 aXsmaller =; 4$4 0 su =; 4$4 \ temp (N downto %) 0 finXsu =; 4$4 0
29
eroXdetect =; Z%%Z 0 numXero =; 4%4 0 elsif (d = c) then temp &; c - d 0 aXsmaller =; 4%4 0 su =; 4$4 \ temp (N downto %) 0 finXsu =; 4$4 0 eroXdetect =; Z%%Z 0 numXero =; 4%4 0 elsif((c;d) and e = f) then aXsmaller =; 4$4 0 temp&; c-d 0 su =; 4$4 \ temp (N downto %) 0 finXsu =; 4$4 0 eroXdetect =; Z%%Z 0 numXero =; 4%4 0 elsif ((c;d) and e Y f) then aXsmaller =; 4%4 0 temp &; c-d 0 su =; 4$4 \ temp (N downto %) 0 eroXdetect =; Z%%Z 0 numXero =; 4%4 0 finXsu =; 4$4 0 elsif ((c;d) and (e ; f)) then temp &; c-d 0 aXsmaller =; 4%4 0 su =; 4$4 \ Z%%%%%%%%Z 0 finXsu =; 4$4 0 eroXdetect =; Z%%Z 0 numXero =; 4%4 0
end if 0 end if 0 end if 0 elsif(rstXsu ; 4$4) then finXsu =; 4%4 0 su =; Z%%%%%%%%%Z 0 numXero =; 4%4 0 eroXdetect =; Z%%Z 0
30
end if 0 end process 0 process(a , ) -- process to identify when a new numer comes egin change =; transport 4$4 after $ ns 0 change =; transport 4%4 after E ns 0 end process 0 end rtl 0 %tage.=0* -- 6TAJK M/K: JKK:AT':. lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity stageXgen is port ( addXstaged , addXclear & in stdXlogic 0 stXstage & out stdXlogicXvector($ downto %) ) 0 end stageXgen 0 architecture rtl of stageXgen is egin process(addXstaged , addXclear) variale sXcount & stdXlogicXvector($ downto %) 0 egin if (addXclear ; 4$4) then stXstage =; Z%%Z 0 sXcount &; Z%%Z 0 elsif(addXstaged4event and addXstaged; 4$4 ) then stXstage =; sXcount < $ 0 sXcount &; sXcount < $ 0 end if 0 end process 0 end rtl 0
31
%0i&t2.=0* -- 68"FT M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXarith.all 0 use ieee.stdXlogicXunsigned.all 0
entity shift is port ( suXcontrol & in stdXlogicXvector ( downto %) 0 cXin & in stdXlogicXvector ( downto %) 0 shiftXout & out stdXlogicXvector ($ downto %) 0 cloc# , shiftXen , rstXshift & in stdXlogic 0 finishXout & out stdXlogic ) 0 end shift 0 architecture rtl of shift is egin process(cloc#) variale suXtemp & stdXlogicXvector(N downto %) 0 variale temp , tempB & stdXlogicXvector($ downto %) 0 variale temp , t & stdXlogic 0 egin if(rstXshift;4%4) then if(shiftXen ; 4$4) then if(temp ; 4$4) then if(suXcontrol() ; 4$4) then suXtemp &; suXcontrol (N downto %) 0 temp &; 4$4 \ cXin ($ downto $) 0 --4$4 for implicit one temp &; 4%4 0 end if 0 end if 0 end if 0 end if 0 if(rstXshift;4%4) then if(shiftXen ; 4$4) then if(t ; 4$4) then if (suXcontrol() ; 4$4) then if (convXinteger(suXtemp(N downto %)) ; %) then shiftXout =; temp 0 finishXout =; 4$4 0 t &; 4%4 0 elsif ( cloc# ; 4$4) then temp &; 4%4 \ temp ($ downto $) 0 suXtemp &; suXtemp - Z%%%%%%%$Z 0
32
end if 0 end if 0 end if 0 end if 0 elsif(rstXshift;4$4) then temp &; 4$4 0 finishXout =; 4%4 0 t &; 4$4 0 end if 0 end process 0 end rtl 0
33
roma**
entity romaddXgen is port ( ioXrom,c%,c$,c,c & in stdXlogic 0 stageXrom & in stdXlogicXvector($ downto %) 0 utterflyXrom & in stdXlogicXvector( downto %) 0 romadd & out stdXlogicXvector( downto %) 0 romgenXen & in stdXlogic )0 end romaddXgen 0 architecture rtl of romaddXgen is egin process(ioXrom,c%,c$,c,c,stageXrom,utterflyXrom) egin if(romgenXen ; 4$4) then if(ioXrom ; 4%4) then case stageXrom is when Z%%Z ;Y if(c%;4$4 or c;4$4) then romadd =; Z%%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z%%$Z 0 end if 0 when Z%$Z ;Y if(utterflyXrom;% or utterflyXrom;$) then if(c%;4$4 or c;4$4) then romadd =; Z%%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z%%$Z 0 end if 0 elsif(utterflyXrom; or utterflyXrom;) then if(c%;4$4 or c;4$4) then romadd =; Z$%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z$%$Z 0 end if 0 end if 0
34
when Z$%Z ;Y if(utterflyXrom;%) then if(c%;4$4 or c;4$4) then romadd =; Z%%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z%%$Z 0 end if 0 elsif(utterflyXrom;$) then if(c%;4$4 or c;4$4) then romadd =; Z$%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z$%$Z 0 end if 0 elsif(utterflyXrom;) then if(c%;4$4 or c;4$4) then romadd =; Z%$%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z%$$Z 0 end if 0 elsif (utterflyXrom;) then if(c%;4$4 or c;4$4) then romadd =; Z$$%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z$$$Z 0 end if 0 end if 0 when others ;Y romadd =; Z%%%Z 0 end case 0 end if 0 end if 0 end process 0 end rtl 0
35
rom.=0* -- :' T' 6T':K 6"K AD '6"K LAHMK6 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity rom is port ( cloc# , enXrom & in stdXlogic 0 romadd & in stdXlogicXvector( downto %) 0 romXdata & out stdXlogicXvector($ downto %) ) 0 end rom 0 architecture rtl of rom is egin process(cloc#,enXrom) egin if(enXrom ; 4$4) then if(cloc# ; 4$4) then case romadd is when Z%%%Z ;Y romXdata =; Z%%$$$$$$$%%%%%%%%%%%%%%%%%%%%%%%Z 0 when Z%%$Z ;Y romXdata =; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0 when Z%$%Z ;Y romXdata =; Z%%$$$$$$%%$
%%%%%$%%$%%%%%%$Z 0 when Z%$$Z ;Y romXdata =; Z%%$$$$$$%%$
%%%%%$%%$%%%%%%$Z 0 when Z$%%Z ;Y romXdata =; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0 when Z$%$Z ;Y romXdata =; Z%%$$$$$$$%%%%%%%%%%%%%%%%%%%%%%%Z 0 when Z$$%Z ;Y romXdata =; Z$%$$$$$$%%$
%%%%%$%%$%%%%%%$Z 0 when Z$$$Z ;Y romXdata =; Z%%$$$$$$%%$
%%%%%$%%$%%%%%%$Z 0 when others ;Y romXdata =; Z%$%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0 end case 0 end if 0 end if 0 end process 0 end rtl 0
36
r"#oc?.=0* -- KJAT"LK KDJK T:"JJK:KD FH"7 FH'76 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity rXloc# is port ( data & in stdXlogicXvector($ downto %) 0 trigger & in stdXlogic 0 rXout & out stdXlogicXvector($ downto %) ) 0 end rXloc# 0 architecture rtl of rXloc# is egin process(data , trigger) egin if (trigger;4%4 and trigger4event) then rXout =; data($ downto %) 0 end if 0 end process 0 end rtl 0
37
ram<%0i&t.=0* -- 7A:AHHK " 7A:AHHKH 'MT 68"FTK: " T8K ADD:K66 JKK:AT"' M"T. -- :KOM":KD /KAM6K FFT "6 '7MTKD ' DATA AD 1:"TTK /A2 "T' T8K 6AK -- H'AT"' AFTK: E HK6. 6' T8K :KAD ADD:K66 "6 68"FTKD T8:'MJ8 E HK6 -- AD J"LK A6 1:"TK ADD:K66. lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity ramXshift is port ( dataXin & in stdXlogicXvector( downto %) 0 cloc#Xmain & in stdXlogic 0 dataXout & out stdXlogicXvector( downto %) ) 0 end ramXshift 0 architecture rtl of ramXshift is egin process(cloc#Xmain , dataXin) egin if (cloc#Xmain4event and cloc#Xmain ; 4%4) then dataXout =; dataXin( downto %) 0 end if 0 end process 0 end rtl 0
38
ram.=0* -- /ehavioral description of dual-port 6:A with & -- Active 8igh write enale (1K) -- Active 8igh read enale (:K) -- :ising cloc# edge (loc#) lirary ieee0 use ieee.stdXlogicX$$CB.all0 use "KKK.stdXlogicXarith.all0 use "KKK.stdXlogicXunsigned.all0 use wor#.utterXli.all 0 entity regXdpram is port ( dataXfft , dataXio & in stdXlogicXvector ($ downto %)0 ! & out stdXlogicXvector ($ downto %)0 cloc# , ioXmode & in stdXlogic0 we , re & in stdXlogic0 waddress& in stdXlogicXvector ( downto %)0 raddress& in stdXlogicXvector ( downto %))0 end regXdpram0 architecture ehav of regXdpram is type K is array (% to $E) of stdXlogicXvector($ downto %)0 signal ramTmp & K0
egin -- 1rite Functional 6ection process (cloc#,waddress,we) egin if (cloc#;4%4) then if (we ; 4$4) then if (ioXmode ; 4%4) then ramTmp (convXinteger (waddress)) =; dataXfft 0 elsif (ioXmode ; 4$4) then ramTmp (convXinteger (waddress)) =; dataXio 0 end if 0 end if 0 end if 0 end process 0 -- :ead Functional 6ection process (cloc#,raddress,re) egin if (cloc#;4$4) then if (re ; 4$4) then ! =; ramTmp(convXinteger (raddress)) 0 end if0
39
end if0 end process0 end ehav0
$rint.=0* -- M6KD T' 7:"T T8K :K6MHT6 " A KAT F':AT. 'T 6T8K6"6A/HK. -- M6KD 'H F': 6"MHAT"' 7M:7'6K. lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use std.textio.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXtextio.all 0 use ieee.stdXlogicXunsigned.all 0 use "KKK.mathXreal.all0 use "KKK.stdXlogicXarith.all0 use wor#.txtXutil.all0
entity printXresult is port (cloc#,op & in stdXlogic 0 finXres & 'MT stdXlogicXvector($ downto %)0 result & in stdXlogicXvector($ downto %))0 end printXresult 0 architecture rtl of printXresult is file vectorwXfile & text open writeXmode is ZJ&[PilinxGi[pro5ects[pro5XfftX""[result.txtZ 0 egin process(op,cloc#) variale l , l & line 0 variale ! , p & integer &; % 0 variale count & integer &; $ 0 egin if (op ; 4$4) then if (count = $N) then if(cloc#;4%4 and cloc#4event) then ! &; $ 0 count &; count < $ 0 for p in $ to loop -- data from :A --write(l , result(p)) 0 ! &; ! - $ 0 end loop 0 ! &; $ 0 --writeline(vectorwXfile , l) 0 end if 0 end if 0
40
end if 0 end process 0 end rtl 0
41
ot
entity printXresult is 7':T( cloc# & " stdXlogic0 op & " stdXlogic0 finXres & 'MT stdXlogicXvector($ downto %)0 result & " stdXlogicXvector($ downto %))0 end printXresult 0 architecture rtl of printXresult is egin process(op,cloc#) variale count & integer &; $ 0 egin if (op ; 4$4) then if (count = $N) then if(cloc#;4%4 and cloc#4event) then finXres =; result 0 count &; count < $ 0 end if 0 end if 0 end if 0 end process 0 end rtl 0
42
norma#i@e.=0* lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXarith.all 0 use std.textio.all 0 use ieee.stdXlogicXtextio.all 0 use ieee.stdXlogicXunsigned.all 0
entity normalie is port ( a , & in stdXlogicXvector ($ downto %) 0 num & in stdXlogicXvector ( downto %) 0 exp & in stdXlogicXvector (N downto %) 0 signit , addsu , cloc# , enXnorm , rstXnorm & in stdXlogic 0 eroXdetect & in stdXlogicXvector($ downto %) 0 exitXn & out stdXlogic 0 normalXsum & out stdXlogicXvector ($ downto %) ) 0 end normalie 0 architecture rtl of normalie is egin process (cloc#) variale numXtemp & stdXlogicXvector ($ downto %) 0 variale tempXexp & stdXlogicXvector (N downto %) 0 variale t , t & stdXlogic &; 4$4 0 egin if (rstXnorm ; 4%4) then if (enXnorm ; 4$4) then if (t ; 4$4) then numXtemp &; num($ downto %) 0 tempXexp &; exp (N downto %) 0 t &; 4%40 end if 0 if (t ; 4$4) then if (eroXdetect ; %) then if (addsu ; 4%4) then if (numXtemp ; %) then normalXsum =; numXtemp($ downto %) 0 exitXn =; 4$4 0 t &; 4%4 0 elsif (numXtemp($) ; 4$4 and cloc# ; 4$4) then normalXsum =; signit \ tempXexp(N downto %) \ numXtemp(% downto ) 0--chec#]] exitXn =; 4$4 0
43
t &; 4%4 0 elsif (cloc# ; 4$4) then numXtemp &; numXtemp(% downto %) \ 4%4 0 tempXexp &; tempXexp - Z%%%%%%%$Z 0 end if 0 elsif (addsu ; 4$4 and num() ; 4$4 and cloc# ; 4$4) then tempXexp &; tempXexp < Z%%%%%%%$Z 0 normalXsum =; signit \ tempXexp(N downto %) \ numXtemp($ downto G) 0 exitXn =; 4$4 0 t &; 4%4 0 elsif (cloc# ; 4$4) then normalXsum =; signit \ tempXexp(N downto %) \ numXtemp(% downto ) 0 exitXn =; 4$4 0 t &; 4%4 0 end if0 elsif (eroXdetect ; $) then normalXsum =; 0 exitXn =; 4$4 0 t &; 4%4 0 elsif (eroXdetect ; ) then normalXsum =; a 0 exitXn =; 4$4 0 t &; 4%4 0 end if 0 end if 0 end if 0 elsif (rstXnorm ; 4$4) then exitXn =; 4%4 0 t &; 4$4 0 t &; 4$4 0 end if 0 end process 0 end rtl 0
44
negate.=0* --KJAT"' M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity negate is port ( negXin & in stdXlogicXvector($ downto %) 0 negXen , cloc#Xmain & in stdXlogic 0 negXout & out stdXlogicXvector($ downto %) ) 0 end negate 0 architecture rtl of negate is egin process(negXin , negXen , cloc#Xmain) variale negXtemp & stdXlogicXvector($ downto %) 0 egin negXtemp &; negXin($ downto %) 0 if (cloc#Xmain ; 4$4) then if (negXen ; 4$4) then if(negXin($) ; 4%4) then negXtemp &; 4$4 \ negXtemp (% downto %) 0 else negXtemp &; 4%4 \ negXtemp (% downto %) 0 end if 0 negXout =; negXtemp 0 else negXout =; negXin($ downto %) 0 end if 0 end if 0 end process 0 end rtl 0
45
m'<"t.=0* -- MHT"7HKPK: " T8K /MTTK:FH 7:'K66"J M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity mux is port ( d% , d$ & in stdXlogicXvector($ downto %) 0 muxXout & out stdXlogicXvector($ downto %) 0 choose & in stdXlogic ) 0 end mux 0 architecture rtl of mux is egin process(d% , d$ , choose) egin if (choose ; 4%4) then muxXout =; d%($ downto %) 0 elsif (choose ; 4$4) then muxXout =; d$($ downto %) 0 end if 0 end process 0 end rtl 0
46
m'
entity muxXadd is port ( a , & in stdXlogicXvector( downto %) 0 sel & in stdXlogic 0 ! & out stdXlogicXvector( downto %) ) 0 end muxXadd 0 architecture rtl of muxXadd is egin process (a , , sel) egin if(sel ; 4%4) then ! =; a( downto %) after ns 0 elsif(sel ; 4$4) then ! =; ( downto %) after ns 0 end if 0 end process 0 end rtl 0
47
m#ti$#!.=0* -- MHT"7H M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity multiply is port( numXmux , numXrom & in stdXlogicXvector($ downto %) 0 cloc# & in stdXlogic 0 multXout & out stdXlogicXvector($ downto %) ) 0 end multiply 0 architecture rtl of multiply is egin process(numXmux , numXrom , cloc#) variale signXmult , t & stdXlogic &; 4%4 0 variale temp$ , temp & stdXlogicXvector( downto %) 0 variale expXmux , expXrom & stdXlogicXvector(N downto %) 0 variale mantXtemp & stdXlogicXvector(BE downto %) 0 variale expXmult , muxXtemp , romXtemp & stdXlogicXvector( downto %) 0 variale resXtemp & stdXlogicXvector($ downto %) 0 egin temp$ &; 4$4 \ numXmux( downto $) 0 -- 4$4 for implicit 4$4. temp &; 4$4 \ numXrom( downto $) 0 if (numXmux($) ; 4$4 and numXrom($) ; 4$4 and cloc# ; 4$4) then -- sign of results signXmult &; 4%4 0 elsif (numXmux($) ; 4%4 and numXrom($) ; 4%4 and cloc# ; 4$4) then signXmult &; 4%4 0 elsif(cloc# ; 4$4) then signXmult &; 4$4 0 end if 0 if (numXmux ; % and cloc# ; 4$4) then -- ie, the numer is ero. t &; 4$4 0 elsif (numXrom ; % and cloc# ; 4$4) then t &; 4$4 0 elsif (cloc# ; 4$4) then t &; 4%4 0 end if 0 if (t ; 4%4 and cloc# ; 4$4) then -- separation of mantissa and exponent expXmux &; numXmux (% downto ) 0
48
expXrom &; numXrom (% downto ) 0 muxXtemp &; 4%4 \ expXmux(N downto %) 0 romXtemp &; 4%4 \ expXrom(N downto %) 0 expXmult &; muxXtemp < romXtemp 0 expXmult &; expXmult - $N 0 mantXtemp &; temp$ ^ temp 0 if(mantXtemp(BE) ; 4$4) then -- normalisation. expXmult &; expXmult < $ 0 resXtemp &; signXmult \ expXmult(N downto %) \ mantXtemp(BB downto ) 0 multXout =; resXtemp($ downto %) 0 elsif(mantXtemp(BE) ; 4%4) then resXtemp &; signXmult \ expXmult(N downto %) \ mantXtemp(B downto $) 0 multXout =; resXtemp($ downto %) 0 end if 0 elsif (t ; 4$4 and cloc# ; 4$4) then -- numer ero multXout =; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0 t &; 4%4 0 end if 0 end process 0 end rtl 0
49
m#t.=0* -- MHT"7HKPK: T' 8''6K /KT1KK H'2 AD % lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity multXcloc# is port ( cloc#Xmain , mult$Xc% , mult$Xiomode , multXclear & in stdXlogic 0 mult$Xaddincr & out stdXlogic ) 0 end multXcloc# 0 architecture rtl of multXcloc# is egin process(cloc#Xmain , mult$Xc% , mult$Xiomode , multXclear) variale temp$ & stdXlogic 0 variale temp & stdXlogic 0 egin if(mult$Xiomode ; 4%4) then -- ie, fft computation mode temp &; mult$Xc% 0 elsif(mult$Xiomode ; 4$4) then -- ie, io mode temp$ &; cloc#Xmain 0 end if 0 if (mult$Xiomode ; 4$4) then mult$Xaddincr =; temp$ 0 elsif(mult$Xiomode ; 4%4) then mult$Xaddincr =; temp 0 end if 0 end process 0 end rtl 0
50
#"#oc?.=0* -- 7'6"T"LK HKLKH T:"JJK:KD FH"7 FH'76 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity lXloc# is port ( dataXl & in stdXlogicXvector($ downto %) 0 triggerXl & in stdXlogic 0 lXout & out stdXlogicXvector($ downto %) ) 0 end lXloc# 0 architecture rtl of lXloc# is egin process(dataXl , triggerXl) egin if (triggerXl;4$4) then lXout =; dataXl 0 end if 0 end process 0 end rtl 0
51
io*<%tage*.=0* -- T8"6 F"HK 'MT7MT6 T8K Z"' D'KZ AD Z6TAJK D'KZ AD ZFFT D'KZ 6"JAH6 AT T8K -- '::KT T"K. "T AH6' :KK"LK6 T8K 'MT7MT 'F T8K /MTTK:FH JKK:AT': -- AD 'MT7MT6 "T M8AJKD. lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity iodXstaged is port ( utXfly & in stdXlogicXvector( downto %) 0 stageXno & in stdXlogicXvector($ downto %) 0 addXincr , ioXmode & in stdXlogic 0 addXiod , addXstaged , addXfftd & out stdXlogic 0 utterflyXiod & out stdXlogicXvector( downto %) ) 0 end iodXstaged 0 architecture rtl of iodXstaged is egin process(utXfly,addXincr,ioXmode) egin if(utXfly ; $E and ioXmode ; 4$4 and addXincr;4%4) then addXiod =; 4$4 0 -- io done signal utterflyXiod =; utXfly 0 elsif(utXfly ; B and ioXmode ; 4%4 and addXincr;4$4) then utterflyXiod =; utXfly 0 addXiod =; 4%4 0 addXstaged =; 4$4 0 -- stage done signal else utterflyXiod =; utXfly 0 addXstaged =; 4%4 0 end if 0 end process 0 process(stageXno) egin if (stageXno;) then addXfftd =; 4$4 0 -- fft done signal end if 0 end process 0 end rtl0
52
ioa**.=0* -- "' ADD:K66 JKK:AT': lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity ioaddXgen is port ( ioXutterfly & in stdXlogicXvector( downto %) 0 addXiomode , addXip , addXop & in stdXlogic 0 aseXioadd & out stdXlogicXvector( downto %) ) 0 end ioaddXgen 0 architecture rtl of ioaddXgen is egin process(ioXutterfly , addXiomode , addXip , addXop) variale outXdata & stdXlogicXvector( downto %) 0 egin if(addXiomode ; 4$4) then if (addXip ; 4$4) then outXdata &; ioXutterfly( downto %) 0 elsif(addXop ; 4$4) then if(ioXutterfly() ; 4%4) then -- ie, real part outXdata &; 4%4 \ ioXutterfly(%) \ ioXutterfly($) \ ioXutterfly() 0 elsif(ioXutterfly();4$4) then -- ie, complex part outXdata &; 4$4 \ ioXutterfly(%) \ ioXutterfly($) \ ioXutterfly() 0 end if 0 end if 0 end if 0 aseXioadd =; outXdata( downto %) 0 end process 0 end rtl 0
53
*i=i*e.=0* -- D"L"DK / T1' M"T. T8"6 F"HK 8'1KLK: 7A66KD T8K DATA M8AJKD -- /KAM6K D"L"6"' "6 :KOM":KD 'H "F 6AH"J "6 M6KD T' AL'"D 'LK:FH'1. -- ' 6AH"J 1A6 M6KD " T8"6 7:'SKT, 6' T8AT :K6MHT6 'F ATHA/ AT8KD 1"T8 'M:6 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity divide is port ( dataXin & in stdXlogicXvector($ downto %) 0 dataXout & out stdXlogicXvector($ downto %) ) 0 end divide 0 architecture rtl of divide is egin process(dataXin) variale divideXexp & stdXlogicXvector(N downto %) 0 variale divideXmant & stdXlogicXvector($ downto %) 0 egin if (dataXin ; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z) then dataXout =; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0 elsif (dataXin ; Z$%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z) then dataXout =; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0 else divideXexp &; dataXin(% downto ) 0 divideXmant &; dataXin ($ downto %) 0 divideXexp &; divideXexp - Z%%%%%%%$Z 0 --dataXout =; divideXmant($) \ divideXexp(N downto %) \ divideXmant( downto %) 0 dataXout =; dataXin($ downto %) 0 -- pass data unchanged end if 0 end process 0 end rtl 0
54
*&&.=0* -- 7'6"T"LK KDJK T:"JJK:KD FH"7FH'76 7 HAKD /KF':K T8K D"L"DK / T1' M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity levelXedge is port ( dataXedge & in stdXlogicXvector($ downto %) 0 triggerXedge & in stdXlogic 0 edgeXout & out stdXlogicXvector($ downto %) ) 0 end levelXedge 0 architecture rtl of levelXedge is egin process(dataXedge , triggerXedge) egin if (triggerXedge;4$4 and triggerXedge4event) then edgeXout =; dataXedge($ downto %) 0 end if 0 end process 0 end rtl 0
55
c!c#e%<"t.=0* --1ALKF': JKK:AT': -- T8K B /"T6 'F ZDATAX'MTZ A:K Z% $ Z lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use wor#.utterXli.all 0
entity cycles is port ( cloc#Xmain , preset , c%Xen , cyclesXclear & in stdXlogic 0 waves & out stdXlogicXvector( downto %) ) 0 end cycles 0 architecture rtl of cycles is --type stateXvalues is (st% , st$ , st , st) 0 --signal presXstate$ , nextXstate$ & stateXvalues 0 shared variale dataXout & stdXlogicXvector( downto %) 0 egin process (cloc#Xmain , preset , c%Xen,cyclesXclear) variale t & stdXlogic 0 egin if (c%Xen ; 4$4) then if (preset ; 4$4 and t;4$4)then presXstate$ =; st% 0 t &; 4%4 0 elsif (cloc#Xmain4event and cloc#Xmain; 4%4) then presXstate$ =; nextXstate$ 0 end if 0 end if 0 if(cyclesXclear ; 4$4) then t &; 4$4 0 end if 0 end process 0 process(presXstate$ , c%Xen , cloc#Xmain) variale tempXcloc# & stdXlogic 0 egin case presXstate$ is when st% ;Y dataXout &; Z$%%%Z 0 nextXstate$ =; st$ 0 when st$ ;Y dataXout &; Z%$%%Z 0 nextXstate$ =; st 0
56
when st ;Y dataXout &; Z%%$%Z 0 nextXstate$ =; st 0 when st ;Y dataXout &; Z%%%$Z 0 nextXstate$ =; st% 0 when others ;Y nextXstate$ =; st% 0 end case 0 waves =; dataXout 0 end process 0 end rtl 0 conter.=0* -- T8"6 F"HK 'MT6 T8K M/K: 'F HK6 AFTK: FFT '7MTAT"' "6 KA/HKD. -- T8"6 "6 :KOM":KD /KAM6K 1:"T"J "T' T8K :A /KJ"6 'H AFTK: E HK6 (DM:"J $) lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity counter is port ( c & out stdXlogicXvector( downto %) 0 disale , cloc#Xmain , reset & in stdXlogic) 0 end counter 0 architecture rtl of counter is egin process (reset , cloc#Xmain , disale) variale temp & stdXlogicXvector( downto %) 0 egin if (disale =; 4%4) then if(reset ; 4$4) then c =; Z%%%Z 0 temp &; Z%%%Z 0 elsif(cloc#Xmain ; 4$4 and cloc#Xmain4event) then c =; (temp < $) 0
57
temp &; temp < $ 0 end if 0 end if 0 end process 0 end rtl 0
58
contro##er.=0* -- 'T:'H M"T 'F T8K 7:'K66': lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity contXgen is port ( conXstaged , conXiod , conXfftd , conXinit & in stdXlogic 0 conXip , conXop , conXiomode , conXfft & out stdXlogic 0 conXenw , conXenor , c%Xenale , conXpreset & out stdXlogic 0 conXclear , disale & out stdXlogic 0 c% , cloc#Xmain & in stdXlogic 0 enXrom , enXromgen , resetXcounter & out stdXlogic 0 conXcl#count & in stdXlogicXvector( downto %) ) 0 end contXgen 0 architecture rtl of contXgen is type state is (rst$,rst,rst,rstB,rstE,rstC,rstN) 0 signal currentXstate , nextXstate & state 0 shared variale counter , temp & stdXlogicXvector($ downto %) &; Z%%Z 0 egin process (currentXstate ,conXstaged , conXiod , conXfftd , conXcl#count , c%) egin case currentXstate is when rst$ ;Y conXiomode =; 4$4 0 -- set mode to io. conXip =; 4$4 0 -- input mode conXclear =; 4$4 0 -- clear all loc#s conXenw =; 4$4 0 -- enale write to :A conXenor =; 4%4 0 -- disale read c%Xenale =; 4%4 0 -- disale cycles unit disale =; 4$4 0 -- disale counter nextXstate =; rst 0 when rst ;Y conXclear =; 4%4 0 -- ring clear signal ac# to ero nextXstate =;rst 0 when rst ;Y if(conXiod ; 4$4) then conXpreset =; 4$4 0 -- reset cycles resetXcounter =; 4$4 0 -- reset counter
59
c%Xenale =; 4$4 0 -- enale cycles conXiomode =; 4%4 0 -- set io mode to 4%4 conXfft =; 4$4 0 -- fft mode enXrom =; 4$4 0 -- enale :' enXromgen =; 4$4 0 -- enale :' address generator conXclear =; 4$4 0 -- clear all loc#s conXenw =; 4%4 0 -- disale write to :A conXenor =; 4$4 0 -- enale read from :' disale =; 4%4 0 -- enale counter unit. nextXstate =; rstB 0 else nextXstate =; rst 0 end if 0 when rstB ;Y conXpreset =; 4%4 0 -- reset for cycles resetXcounter =; 4%4 0 -- reset for counter conXclear =; 4%4 0 -- clear all signals if (conXcl#count ; E) then -- chec# whether B or not conXenw =; 4$4 0 -- enale write to :' disale =; 4$4 0 -- disale counter resetXcounter =; 4$4 0 -- reset counter nextXstate =; rstE 0 else nextXstate =; rstB 0 end if 0 when rstE ;Y if (conXfftd ; 4$4) then disale =; 4%4 0 -- enale counter resetXcounter =; 4%4 0 conXclear =; 4$4 0 -- clear utterfly generator conXfft =; 4%4 0 -- disale fft address generator if (conXcl#count ; B) then disale =; 4$40 conXenw =; 4%4 0 conXiomode =; 4$4 0 conXop =; 4$4 0 conXip =; 4%4 0 nextXstate =; rstC 0 else nextXstate =; rstE 0 end if 0 else nextXstate =; rstE 0
60
end if 0 when rstC ;Y conXclear =; 4%4 0 nextXstate =; rstN 0 when rstN ;Y if(conXiod ; 4$4) then conXclear =; 4$4 0 conXpreset =; 4$4 0 conXenor =; 4%40 else nextXstate =; rstN 0 end if 0
when others ;Y nextXstate =; rst$ 0 end case 0 end process 0 process(cloc#Xmain , conXinit) egin if(conXinit ; 4$4) then currentXstate =; rst$ 0 elsif (cloc#Xmain4event and cloc#Xmain ; 4%4) then currentXstate =; nextXstate 0 end if 0 end process 0 end rtl 0
61
"tter<#i".=0* -- T8"6 F"HK DKHA:K6 T8K 6"JAH6 M6KD " T8K 7:'K66': lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use ieee.stdXlogicXunsigned.all 0
pac#age utterXli is signal ramXdata,d,d,dB,dE,dC,dN,d,dG,d$%,d$$,d$,d$,d$B,d$E,d$C,d$N,d$,d$G,outXdata & stdXlogicXvector($ downto %) &; (others ;Y 4%4) 0 signal dataXrom , romXff & stdXlogicXvector($ downto %) 0 signal cloc#Xmain , reset , enl , cloc# & stdXlogic &; 4%4 0 signal c% , c$ , c , c , c%Xc$ , cXc , c%Xc , c$Xc & stdXlogic 0 signal c%Xand,c$Xand,cXand,cXand,c%Xc$and,cXcand,c%Xcand,c$Xcand & stdXlogic 0 signal resetXcount & stdXlogic 0 type state is (reset$ , reset , reset , resetB , resetE , resetC , resetN) 0 signal finalXsum & stdXlogicXvector ($ downto %) &; (others ;Y 4%4) 0 signal shift , finishXsum , signit , normalise , endXall , aXsmall , addsu ,sumXout , shiftXdone , done , numXrec , setit , addpulse & stdXlogic &; 4%4 0 signal shiftXouta , swapXnum & stdXlogicXvector ( $ downto % ) &; (others ;Y 4%4) 0 signal swapXnum$ , sumXout & stdXlogicXvector ( downto %) &; (others ;Y 4%4) 0 signal su & stdXlogicXvector ( downto %) &; (others ;Y 4%4) 0 signal sua & stdXlogicXvector ( downto %) &; (others ;Y 4%4) 0 signal exp & stdXlogicXvector (N downto %) &; (others ;Y 4%4) 0 signal rst , enswap , ensu , enshift , finsu , finswap , finshift , numero & stdXlogic &; 4%4 0 signal erodetect & stdXlogicXvector($ downto %) 0 signal changea & stdXlogic 0 signal finalXsum & stdXlogicXvector ($ downto %) &; (others ;Y 4%4) 0 signal shift , finishXsum , signit , normalise , endXall , aXsmall , addsu,sumXout , shiftXdone , done , numXrec , setit , addpulse , cloc# & stdXlogic &; 4%4 0 signal shiftXout , swapXnum & stdXlogicXvector ( $ downto % ) &; (others ;Y 4%4) 0 signal swapXnum$ , sumXout & stdXlogicXvector ( downto %) &; (others ;Y 4%4) 0 signal su & stdXlogicXvector ( downto %) &; (others ;Y 4%4) 0 signal su & stdXlogicXvector ( downto %) &; (others ;Y 4%4) 0 signal exp& stdXlogicXvector (N downto %) &; (others ;Y 4%4) 0 signal rst , enswap , ensu , enshift , finsu , finswap , finshift , numero , cloc#Xmain , reset , enl & stdXlogic &; 4%4 0 signal erodetect & stdXlogicXvector($ downto %) 0 signal change & stdXlogic 0
62
signal incr , clear , ioXmode , staged , iod & stdXlogic 0 signal utterfly,fftaddXrd,shift$,shift,shiftB,shiftE,shiftC,ramXwr,ramXrd,ioXadd & stdXlogicXvector( downto %) &; (others ;Y 4%4) 0 signal fftd , fftXen , ip , op , init & stdXlogic 0 signal stage & stdXlogicXvector($ downto %) 0 --signal cloc#Xmain,c%,c$,c,c,c%Xc$,cXc,c%Xc,c$Xc & stdXlogic 0 signal preset,disale,c%Xen,romXen,romgenXen & stdXlogic 0 signal cl#Xcount & stdXlogicXvector( downto %) 0 signal enw , enor & stdXlogic 0 signal dataXio & stdXlogicXvector($ downto %) &; (others ;Y 4%4) 0 signal romXadd & stdXlogicXvector( downto %) 0 type stateXvalues is (st% , st$ , st , st) 0 signal presXstate$ , nextXstate$ & stateXvalues 0 signal utterflyXiod & stdXlogicXvector( downto %) 0 signal cycXclear & stdXlogic 0 signal addXrd , addXwr & stdXlogicXvector( d ownto %) 0 end utterXli 0
63
"t.=0* -- /MTTK:FH JKK:AT': lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0
entity utXgen is port ( addXincr , addXclear , stagedone & in stdXlogic 0 utXutterfly & out stdXlogicXvector( downto %) ) 0 end utXgen 0 architecture rtl of utXgen is egin process(addXclear , addXincr , stagedone) variale cnt & integer 0 variale count & stdXlogicXvector( downto %) 0 egin if(addXclear ; 4$4 or stagedone ; 4$4) then count &; Z%%%%Z 0 utXutterfly =; Z%%%%Z 0 elsif (addXincr4event and addXincr ; 4$4) then utXutterfly =; (count < $) 0 count &; count < $ 0 end if 0 end process 0 end rtl 0
64
"a%ein*e'.=0* --/A6K "DKP JKK:AT': lirary ieee0 use ieee.stdXlogicX$$CB.all0 use wor#.utterXli.all 0
entity aseindex is port( indXutterfly& in stdXlogicXvector( downto %)0 indXstage& in stdXlogicXvector($ downto %)0 addXfft& in stdXlogic0 fftaddXrd& out stdXlogicXvector( downto %)0 c%,c$,c,c& in stdXlogic)0 end aseindex0 architecture rtl of aseindex is egin process(indXutterfly,indXstage,addXfft,c%,c$,c,c) variale outXsig & stdXlogicXvector( downto %)0 egin if (addXfft;4$4) then if(c;4$4) then -- address for 4x4. 6ince this is the real part, case indXstage is -- .6./ is 4%4. when Z%%Z ;Y outXsig &; Z%%Z \ indXutterfly($ downto %)0 when Z%$Z ;Y outXsig &; 4%4 \ indXutterfly($) \ 4%4 \ indXutterfly(%)0 -- when Z$%Z ;Y outXsig &; 4%4 \ 4$4 \ 4$4 \ indXutterfly()0 when Z$%Z ;Y outXsig &; 4%4 \ indXutterfly($ downto %) \ 4%40 when others ;Y outXsig &; Z%%%%Z0 end case0 elsif(c%;4$4) then -- address for 4y4. case indXstage is when Z%%Z ;Y outXsig &; Z%$Z \ indXutterfly($ downto %)0 when Z%$Z ;Y outXsig &; 4%4 \ indXutterfly($) \ 4$4 \ indXutterfly(%)0 when Z$%Z ;Y outXsig &; 4%4 \ indXutterfly($ downto %) \ 4$40 when others ;Y outXsig &; Z%%%%Z0 end case0 elsif(c$;4$4) then -- addresss for 44 case indXstage is when Z%%Z ;Y outXsig &; Z$$Z \ indXutterfly($ downto %)0 when Z%$Z ;Y outXsig &; 4$4 \ indXutterfly($) \ 4$4 \ indXutterfly(%)0 when Z$%Z ;Y outXsig &; 4$4 \ indXutterfly($ downto %) \ 4$40 when others ;Y outXsig &; Z%%%%Z0 end case0
65
elsif(c;4$4) then -- address for 4P4 case indXstage is when Z%%Z ;Y outXsig &; Z$%Z \ indXutterfly($ downto %)0 when Z%$Z ;Y outXsig &; 4$4 \ indXutterfly($) \ 4%4 \ indXutterfly(%)0 when Z$%Z ;Y outXsig &; 4$4 \ indXutterfly($ downto %) \ 4%40 when others ;Y outXsig &; Z%%%%Z0 --else --outXsig &; Z____Z0 end case0 end if0 end if0 fftaddXrd =; outXsig ( downto %) 0 end process0 end rtl0
an*
lirary ieee0 use ieee.stdXlogicX$$CB.all0 use "KKK.stdXlogicXarith.all0 use "KKK.stdXlogicXunsigned.all0 use wor#.utterXli.all 0 entity andXgates is port ( wavesXand & in stdXlogicXvector( downto %) 0 cloc#Xmain , c%Xen & in stdXlogic 0 c%,c$,c,c & out stdXlogic 0 c%Xc$,cXc,c%Xc,c$Xc & out stdXlogic ) 0 end andXgates 0 architecture rtl of andXgates is egin process(cloc#Xmain,wavesXand) egin if (c%Xen ; 4$4 and cloc#Xmain;4$4) then c% =; wavesXand() 0 c$ =; wavesXand() 0 c =; wavesXand($) 0 c =; wavesXand(%) 0 c%Xc$ =; wavesXand() or wavesXand() 0
