21)What is diference between reeze deposit and orce?
$deposit(variable, value); This system task sets a Verilog Verilog register or net to the specifed value. variable is the register or net to be changed; value is the new value or the register or net. The value remains until there is a subse!uent driver transaction or another $deposit task or the same register or net. This system task operates identically to the "odel#im orce deposit command. The orce command has has ree%e, drive, and and deposit options. &hen none o these is specifed, then ree%e is assumed or unresolved signals and drive is assumed or resolved signals. This is designed to provide compatibility with orce fles. 'ut i you preer ree%e as the deault or both resolved and unresolved signals. Verilog interview uestions 22)Will case iner priority register i yes how give an example?
yes case can iner priority register depending on coding style reg r; *riority encoded mu+, always (a or b or c or select-) begin r c; case (select-) -/b001 r a; -/b021 r b; endcase end
Verilog interview uestions 23)Casexz diferencewhich is preerablewhy? 34#56 1 #pecial version o the case statement which uses a 6 logic value to represent don/tcare bits. 34#57 1 #pecial version o the case statement which uses 6 or 7 logic values to represent don/tcare bits. 34#56 should be used or case statements with wildcard don8t cares, otherwise use o 34#5 is re!uired; 34#57 should never be used. This is because1 9on8t cares are not allowed in the :case: statement. Thereore case+ or case% are re!uired. 3ase+ will automatically match any + or % with anything in the case statement. 3ase% will only match %8s +8s re!uire an absolute match. Verilog interview uestions 2!)"iven the ollowing #erilog code what val$e o %a% is displayed? always (clk) begin a 0; a 2; $display(a); end This is a tricky one< Verilog scheduling semantics basically imply a ourlevel deep !ueue or the current simulation time1 21 4ctive 5vents (blocking statements) -1 =nactive 5vents (>0 delays, etc) ?1 @on'locking 4ssign Apdates (nonblocking statements) B1 "onitor 5vents ($display, $monitor, etc). #ince the :a 0: is an active event, it is scheduled into the 2st :!ueue:. The :a 2: is a nonblocking event, so it/s placed into the ?rd
!ueue. Cinally, the display statement is placed into the Bth !ueue. Dnly events in the active !ueue are completed this sim cycle, so the :a 0: happens, and then the display shows a 0. = we were to look at the value o a in the ne+t sim cycle, it would show 2. 2&) What is the diference between the ollowing two lines o #erilog code? >E a b; a >E b;
>E a b; &ait fve time units beore doing the action or :a b;:. a >E b; The value o b is calculated and stored in an internal temp register,4ter fve time units, assign this stored value to a. 2')What is the diference between( c oo ? a ( b* and i +oo) c a* else c b*
The F merges answers i the condition is :+:, so or instance i oo 2/b+, a /b20, and b /b22, you/d get c /b2+. Dn the other hand, i treats 7s or 6s as C4G#5, so you/d always get c b. 2,)What are -ntertial and .ransport /elays ?? 20)What does timescale 1 ns 1 ps signiy in a verilog code?
/timescale directive is a compiler directive.=t is used to measure simulation time or delay time. Asage 1 Htimescale reerenceItimeIunit 1 #pecifes the unit o measurement or times and delays. timeIprecision1 specifes the precision to which the delays are rounded oJ. 2) What is the diference between and ?
output o :: can be 2, 0 or 7. output o :: can only be 0 or 2. &hen you are comparing - nos using :: and i oneboth the numbers have one or more bits as :+: then the output would be :7: . 'ut i use :: outpout would be 0 or 2. e.g 4 ?/b2+0 ' ?/b20+ 4 ' will give 7 as output. 4 ' will give 0 as output. :: is used or comparison o only 2/s and 0/s .=t can/t compare 7s. = any bit o the input is 7 output will be 7 :: is used or comparison o 7 also. 34)5ow to generate sine wav $sing verilog coding style?
41 The easiest and eKcient way to generate sine wave is using 3DL9=3 4lgorithm. 31) What is the diference between wire and reg?
@et types1 (wire,tri)*hysical connection between structural elements. Value assigned by a continuous assignment or a gate output. Legister type1 (reg, integer, time, real, real time) represents abstract data storage element. 4ssigned values only within an always statement or an initial statement. The main diJerence between wire and reg is wire cannot hold (store) the value when there no connection between a and b like aMb, i there is no connection in a and b, wire loose value. 'ut reg can hold the value even i there in no connection. 9eault values1wire is 6,reg is +. 32 )5ow do yo$ implement the bi6directional ports in #erilog 5/7?
module bidirec (oe, clk, inp, outp, bidir); *ort 9eclaration input oe; input clk; input NO10P inp; output NO10P outp; inout NO10P bidir; reg NO10P a; reg NO10P b; assign bidir oe F a 1 Q/b6 ; assign outp b; 4lways 3onstruct always (posedge clk) begin
b bidir; a inp; end endmodule
3!)what is verilog case +1) ?
wire N?10P +; always (...) begin case (2/b2) +N0P1 #D"5TR=@S2; +N2P1 #D"5TR=@S-; +N-P1 #D"5TR=@S?; +N?P1 #D"5TR=@SB; endcase end The case statement walks down the list o cases and e+ecutes the frst one that matches. #o here, i the lowest 2bit o + is bit -, then something? is the statement that will get e+ecuted (or selected by the logic). 3&) Why is it that %i +28b41 9 28b14):::% doesn8t r$n the tr$e case?
This is a popular coding error. ou used the bit wise 4@9 operator (U) where you meant to use the logical 4@9 operator (UU). 3')What are /iferent types o #erilog ;im$lators ?
There are mainly two types o simulators available. 5vent 9riven 3ycle 'ased 5ventbased #imulator1 This 9igital Gogic #imulation method sacrifces perormance or rich unctionality1 every active signal is calculated or every device it propagates through during a clock cycle. Cull 5ventbased simulators support B-Q states; simulation o 'ehavioral R9G, LTG R9G, gate, and transistor representations; ull timing calculations or all devices; and the ull R9G standard. 5ventbased simulators are like a #wiss 4rmy knie with many diJerent eatures but none are particularly ast. 3ycle 'ased #imulator1 This is a 9igital Gogic #imulation method that eliminates unnecessary
calculations to achieve huge perormance gains in veriying 'oolean logic1 2.) Lesults are only e+amined at the end o every clock cycle; and -.) The digital logic is the only part o the design simulated (no timing calculations). 'y limiting the calculations, 3ycle based #i mulators can provide huge increases in perormance over conventional 5ventbased simulators. 3ycle based simulators are more like a high speed electric carving knie in comparison because they ocus on a subset o the biggest problem1 logic verifcation. 3ycle based simulators are almost invariably used along with #tatic Timing verifer to compensate or the lost timing inormation coverage. 3,)What is Constrained6
=ntroduction 4s 4#=3 and systemonchip (#o3) designs continue to increase in si%e and comple+ity, there is an e!ual or greater increase in the si%e o the verifcation eJort re!uired to achieve unctional coverage goals. This has created a trend in LTG verifcation techni!ues to employ constrainedrandom verifcation, which shits the emphasis rom handauthored tests to utili%ation o compute resources. &ith the corresponding emergence o aster, more comple+ bus standards to handle the massive volume o data traKc there has also been a renewed signifcance or verifcation =* to speed the time taken to develop advanced testbench environments that include randomi%ation o bus traKc. 9irectedTest "ethodology 'uilding a directed verifcation environment with a comprehensive set o directed tests is e+tremely timeconsuming and diKcult. #ince directed tests only cover conditions that have been anticipated by the verifcation team, they do a poor ob o covering corner cases. This can lead to costly respins or, worse still, missed market windows. Traditionally verifcation =* works in a directedtest environment by acting on specifc testbench commands such as read, write or burst to generate transactions or whichever protocol is being tested. This directed traKc is used to veriy that an interace behaves as e+pected in response to valid transactions and error conditions. The drawback is that, in this directed methodology, the task o writing the command code and checking the responses across the ull breadth o a protocol is an overwhelming task. The verifcation team re!uently runs out o time beore a mandated tapeout date, leading to poorly tested interaces. Rowever, the bigger issue is that directed tests only test or predicted behavior and it is typically the unoreseen that trips up design teams and leads to e+tremely costly bugs ound in silicon. 3onstrainedLandom Verifcation "ethodology
The advent o constrainedrandom verifcation gives verifcation engineers an eJective method to achieve coverage goals aster and al so help fnd cornercase problems. =t shits the emphasis rom writing an enormous number o directed tests to writing a smaller set o constrainedrandom scenarios that let the compute resources do the work. 3overage goals are achieved not by the sheer weight o manual labor re!uired to handwrite directed tests but by the number o processors that can be utili%ed to run random seeds. This signifcantly reduces the time re!uired to achieve the coverage goals. #coreboards are used to veriy that data has successully reached its destination, while monitors snoop the interaces to provide coverage inormation. @ew or revised constraints ocus verifcation on the uncovered parts o the design under test. 4s verifcation progresses, the simulation tool identifes the best seeds, which are then retained as regression tests to create a set o scenarios, constraints, and seeds that provide high coverage o the design.
