1 1. VGA VGA (HD (HD-15 -15)) Mon Monit itor or Port Port 2 2. 9-p 9-piin (D (DB-9) -9) 3 3. Pow Poweer Con Conne necctor tor 4 4. A1 Expa Expans nsio ion n Por Portt 5 5. A2 Expa Expans nsio ion n Por Portt 6 6. B1 Expa Expans nsio ion n Por Portt 7 7. PS/2 Port 8 8. Seve Seven n Seg Segme ment nt Disp Displa lays ys 9 9. Sw Switches (8 (8) 10 10. Butt Button onss (4) 1 11. LEDs (8 (8) 2 12. Power LED 3 13. 13. Spa Spart rtan an 3 FPG FPGA A Cor Coree 4 14. Progra Program m LED (Lit (Lit when when the the FPGA FPGA is is progra programme mmed) d) 5 15. JTAG JTAG Port Port (used (used to prog program ram the the FPGA FPGA))
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Programming Programming Xilinx Board (Spartan 3) Tutorial Using ISE 8.1i Tutorial prepared by Oluwayomi Adamo Introduction This tutorial shows you how to program Spartan 3 FPGA board using Xilinx ISE 8.1i. As an example, a half half adder circuit will be implemented implemented on the Spartan 3 board. The tutorial begins begins by showing you how to create create a new project and how to describe the the digital circuit circuit in VHDL. VHDL. After the circuit’s functionality has been verified, it is then downloaded to the Spartan 3 board for implementation. implementation. You are encouraged to try try out the examples before embarking on any exercise. exercise. Creating a new Project and Source
Start the Xilinx ISE 8.1i project navigator navigator by double clicking clicking the Xilinx ISE 8.1i icon on your desktop.
Xili nx ISE 8.1i.lnk
Click on File and select New Project
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Select a project location and type the name you would like to call your project “HalfAdder ”:
Click Next
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Select the device family, device, package, and speed grade as shown below:
Click Next Click New Source
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Select VHDL Module in the New Source Wizard window:
Click Next
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Specify the inputs and outputs of your design ( HalfAdder ). This is used to generate a template for your VHDL code.
Click Next
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Click Finish if you are satisfied your specifications shown in the summary page
Click Next
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Click Next Verify the information on the Project Summary window:
Click Finish.
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Double-click on “HalfAdder-Behavioral(HalfAdder.vhd)” tab in the “Sources” pane. Include an “ enable” input in your entity and it should be 1 bit wide. Complete the architectural part of your VHDL code.
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Specify the pins you would like the inputs and outputs to be connected to. Double-click on “ Assign Package Pins” in the “ Process” pane in the left of the window.
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Note: You may be asked to save your VHDL code. Your design will be checked for syntax error. If you have any error, make sure you fix them before proceeding.
Click Yes.
Click Yes. The Pace editor is loaded.
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You can select “ Package View” tab at the bottom of the right pane. The package view gives a better view of the physical FPGA package).
Type in the desired pin names for each signal in the “ Design Object List” at the left in the “Loc” column
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Click File and Save. Click File and Exit. Note: The following dialog may appear when saving the file:
Click on “ Don’t show this dialog again ”. Click Ok. View the UCF file by double-clicking “Edit Constraints (Text)” in the project Navigator window. 13
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Programming the Board In the Project Navigator window, double-click on “HalfAdder-Behavioral (HalfAdder)” tab in the “ Sources” pane.
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Right-click on “Generate Programming File” in the “ Processes” pane. Select “Properties”.
In the Process Properties windows, Select “ Startup Options” tab. Change “FPGA Start-UP Clock ” to “ JTAG Clock ” 16
Click Apply. Click Ok . In the “Processes” window, click on the + sign by “ Generate programming file”. Double-click on “ Configure Device (iMPACT)”. This opens the iMPACT tool and a wizard for creating a new configuration.
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Click Finish. “Assign New Configuration File” window opens. Select the name of your select the “.bit” file (HalfAdder.bit).
Click Open.
click Bypass.
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You will now be at the main iMPACT window:
Right-click on the FPGA (“xc3s200”). select “Program”.
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Make sure that “ Verify” is not checked.
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Click Apply. Click Ok . The FPGA is now being programmed as shown:
