2-16 Bit Microprocessor 8086

16-bit Microprocessor 8086

Microprocessor and Programming

2. 16-bit Microprocessor: 8086 24 Marks Syllabus: 2.1 8086 Microprocessor, Salient features, Pin descriptions, Architecture of 8086 - Functional Block diagram, Register organization, Concepts of pipelining, Memory segmentation, Physical memory addresses generation. 2.2 Operating Modes of 8086 8284 Clock Generator, 8288 Bus Controller, 74LS245 Bi-directional Buffer, 74LS373 Octal Latch, Minimum Mode operation and its timing diagram, Maximum Mode operation and its timing diagram

Features of 8086 microprocessor:

1) 40 pin dual inline package 2) Operating clock frequencies: 5 MHz, 8 MHz, 10 MHz 3) 20 address lines therefore addressing capacity is 1MB memory 4) 16 bit microprocessor, it can perform operations on 16 bit data at a time 5) Two operating modes: Minimum mode (single processor mode), Maximum mode (multiprocessor mode) 6) More powerful instruction set 7) Provides 256 software interrupts 8) 6 byte instruction queue for pipelining 9) Memory segmentation implemented, segment size 64 KB 10) Multiprogramming support 11) Can generate 8 bit and 16 bit I/O addresses so it can access max. 64K I/O devices 12) String manipulation instructions are available 13) Supports 24 addressing modes

Pin description of 8086: AD0 – AD15: These are multiplexed address/data lines. During T1 of bus cycle, these lines carry

lower order 16 bit address. During remaining T-states theses lines are used as data lines. l ines.

A16/S3, A17/S4, A18/S5, A19/S6 : These are multiplexed address/status lines. During T1 of bus cycle,

these lines carry upper 4 bit address. During remaining T-states theses lines carry status information. S3 and S4 indicate which segment register is presently being used. S5 gives the status of interrupt enable flag bit. The S6 status line is always LOW.

Computer Department, Jamia Polytechnic, Akkalkuwa

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-----------------------------------------------------------------------S4 S3 Segment Register being used -----------------------------------------------------------------------0 0 ES – Extra Extra Segment 0 1 SS – Stack Stack Segment 1 0 CS – Code Code Segment or None 1 1 DS – Data Data Segment ̅ ̅ signal is used to indicate the transfer of data over higher  /S7 (Bus High Enable/S7): The 

order data lines (D0 – D15). D15). It can be used to drive chip select signals of odd memory bank. ̅ During T1 this line is used as  signal and during rest of the bus cycle it acts as S7. S7 is

not used.

̅ (Read): This is active LOW signal. It indicates that the processor is performing a memory or I/O 

read operation.

READY: This is an active high signal. When this signal is made LOW, microprocessor adds wait

states in its bus cycle. When slow responding device is ready to transfer or accept data, it makes this signal HIGH.

INTR (Interrupt Request): It is an active HIGH signal. Microprocessor accepts interrupt requests

through this pin. The interrupts can be masked by resetting interrupt enable flag bit in flag register.

̅ : If this signal is LOW then execution will continue, otherwise processor remains in idle state. 

This signal is examined by WAIT instruction. NMI (Non-Maskable Interrupt): It is active HIGH signal and used to send a non-maskable interrupt to

microprocessor. NMI has higher priority than INTR. Interrupt flag has no effect on NMI.

RESET: This is an active HIGH signal and used reset the 8086 and bring it microprocessor to a

predefined state. To reset 8086, this signal must remain HIGH for at least four clock cycles. After reset, 8086 starts execution by fetching first instruction from memory location FFFF0h.


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Fig. Pin diagram of 8086 microprocessor

RESET: This is an active HIGH signal and used reset the 8086 and bring it microprocessor to a

predefined state. To reset 8086, this signal must remain HIGH for at least four clock cycles. After reset, 8086 starts execution by fetching first instruction from memory location FFFF0h.

(Clock Input): Through this pin CLK is applied to 8086. It provides basic timing for processor CLK (Clock operations and bus control activities. The clock signal is asymmetric square wave with 33% duty cycle. The range of frequency for different 8086 versions is from 5 MHz to 10 MHz.


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Vcc: +5V power supply.

GND: Ground reference for internal circuit.

̅ : This signal is used to operate the 8086 in either minimum mode (MN/ ̅=1) or in maximum MN/

mode (MN/̅=0).

Following signals are available when 8086 operates in minimum mode.

̅ : When this signal is LOW, it indicates that the microprocessor is performing an I/O operation M/

and when it is HIGH, it indicates that the microprocessor is performing a memory read/write operation. This line becomes active during T4 of previous bus cycle and remains active till T4 of current bus cycle. ̅  (Interrupt Acknowledge): In response to interrupt request (INTR) signal, microprocessor

generates this signal indicating it has accepted the interrupt request. This signal is generated twice. Second ̅ indicates that microprocessor needs interrupt number which can be from 00H to FFH.

ALE (Address Latch Enable): This signal indicates that valid address is present on multiplexed

address/data lines. It is connected to latch enable input of address latches.

 (Data Transmit/Receive): This signal indicates the direction of data flow through transceivers. DT/

When microprocessor transmits data, this signal is HIGH. When microprocessor receives/reads data, this signal is LOW.

̅  (Data Enable): This signal indicates that valid data is available on address/data lines. It is used to

enable transceivers to separate the data from multiplexed address/data bus. It is active from middle of T2 to middle of T4.

HOLD and HLDA: When Hold signal goes HIGH, it indicates to the processor that another bus

master is requesting to use the buses. In response to this signal, 8086 issues the HLDA (Hold Acknowledge) signal. When HOLD goes LOW, the HLDA signal becomes inactive.


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Following signals are available when 8086 operates in maximum mode.

̅ ,  ̅ ,  ̅ (Status lines): These are status lines which indicate the type of operation carried out by 

8086. These signals become active during T4 of previous bus cycle and remain active during T1 and T2 of current bus cycle. Following table shows status of these lines during different operations:

̅ 

̅ 

̅

Operation ------------------------------------------------------------------------------------0 0 0 Interrupt Acknowledge 0 0 1 I/O Read 0 1 0 I/O Write 0 1 1 Halt 1 0 0 Code Access 1 0 1 Memory Read 1 1 0 Memory Write 1 1 1 Passive ̅ : This is active LOW signal. When it is active, it indicates that other bus masters cannot gain 

system buses. This signal is activated by LOCK prefix instruction and remains active till the completion of instruction. While executing critical instructions, the LOCK prefix can be used.

QS1, QS0 (Queue Status): Theses lines give the status of code prefetch queue. Instructions are fetched

by Bus Interface Unit (BIU) in advance and stored in a 6 byte prefetch queue. Instruction decoder reads instructions from queue and decodes them. When at least 2 bytes of queue are emptied, 8086 performs instruction fetch operation. Following table shows the queue status indicated by QS1 and QS0: QS1 QS0 Meaning -----------------------------------------------------------------------------------0 0 No operation 0

1

First byte of opcode from the queue

1

0

Empty queue

1

1

Subsequent byte from queue

̅/ ̅ ̅ , ̅/ (Request/Grant): In maximum mode, other bus masters send request to use system

buses with the help of these lines. Processor completes current bus cycle and release system ̅ /̅ has higher priority than  ̅ /̅. The sequence of buses for other bus masters. , 

operations is as follows:


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1) A pulse one clock wide from other bus master is sent to 8086 requesting to use system buses. 2) During T4 of current bus cycle or T1 of next bus cycle, a pulse one clock wide is generated by 8086 indicating microprocessor microprocessor has allowed the bus master to use system buses. 3)

Other bus master gains access of bus. When the bus master to release the bus it sends a pulse one clock wide to 8086. This indicates that 8086 can regain the control of bus and proceed with its operation.

Architecture Architecture of 8086: Block diagram:

The complete architecture of 8086 can be divided into two parts: 1) Bus Interface Unit (BIU) 2) Execution Unit (EU) BIU: BIU sends out addresses, fetches instructions from memory, reads/writes data from/to IO ports

and memory. It contains the circuit for physical address calculation and a 6 byte instruction queue. Instructions are fetched from memory and stored in this queue.


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It has segment registers which contain the base addresses of logical segments in memory. To access a particular segment, the contents of segment register are shifted to left by 4 bit position and a 16 bit offset value is added to the shifted contents. Thus a 20 bit physical address is generated. Instruction pointer holds the address of next instruction to be fetched from memory. memory. EU: The EU tells BIU from where to fetch instructions or data. It decodes instructions and executes

them. EU contains control circuit which controls the internal operation of 8086. Instruction decoder translates the instruction into a series of actions in order to execute the instruction. The EU has a 16 bit ALU which can add, subtract, multiply, divide, AND, OR, XOR, increment, decrement, complement, shift and rotate binary numbers. It contains flag register which has nine flags. Flags reflect the result of some operations.

X

X

X

X

O

D

I

T

S

Z

X

AC

X

P

X

C

Figure: Flag Register of 8086 C: Carry Flag

When an operation generates carry/borrow, this flag is set. P: Parity Flag

If lower byte of result contains even number of 1s then parity flag is set. AC: Auxiliary Carry Flag

If carry is generated from bit D3 to bit D4 then this flag is set. It is used in BCD operations. Z: Zero Flag

If result of an operation is zero, this flag is set to reflect the status of result. S: Sign Flag

This flag is set according accor ding to the most significant bit (MSB) of the r esult. If MSB=1, then this flag is set indicating the sign of result is negative. T: Trap Flag

If this flag is set, the processor enters in single step execution mode. I: Interrupt Enable Flag

If this flag is set, maskable interrupts (i.e. interrupts on INTR pin of 8086) are recognized by microprocessor, otherwise they are ignored. D: Direction Flag

This is used by string manipulation instructions. If this bit is reset, the string is processed from lowest address to highest address i.e. auto increment mode.


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O: Overflow Flag

This flag is set if overflow occurs i.e. i.e . the result of a signed operation cannot be stored in destination.

Out of these flags, 6 flags are condition flags: O, S, Z, AC, P, C and 3 flags are machine control flags: D, I, T.

General purpose registers: EU has 4 general purpose registers: AX, BX, CX and DX. These can be

used as 8 bit registers as AH, AL, BH, BL, CH, CL, DH, DL. AX is used as 16 bit accumulator while AL can be used as 8 bit accumulator for 8 bit operations. There are two pointer registers: SP (Stack Pointer) and BP (Base Pointer). There are two index registers: SI (Source Index) and DI (Destination Index).

Pipelining:

Fetching next instruction while the current instruction executes is called pipelining. In a non-pipelined processor, the instruction is fetched, decoded and executed. Unless one instruction is completely executed, next instruction is not fetched. In a pipelined processor, the operations instruction fetch (IF), Instruction decode (ID) and execute(E), are performed in parallel i.e. while one instruction is being decode, at the same time microprocessor can fetch the next instruction, thus speeding up execution. Figure below shows execution of 3 instructions I1, I2, I3 in a non-pipelined processor and in a pipelined processor:

IF

ID

E

IF

ID

E

IF

ID

E

I1

I1

I1

I2

I2

I2

I3

I3

I3

1

2

3

4

5

6

7

8

9

Clock cycles

Fig.(a) Execution of 3 instructions on a non-pipelined processor


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I1

IF

ID

I2

I3

I1

I2

I3

I1

I2

I3

3

4

5

E

1

2

Clock cycles Fig.(b) Execution of 3 instructions on a pipelined processor

From the above two figures it is clear that pipeline processors take less time to execute same number of instructions as compared to non-pipelined processors. In the above example, to execute 3, instructions non-pipelined processor takes 9 clock cycles while pipelined processor takes only 5 clock cycles. In 8086, pipelining is implemented by dividing the processor into 2 functional units: Bus Interface Unit (BIU) and Execution Unit (EU). Bus Interface Unit fetches next instructions and stores them in prefetch queue while current instruction is executed by Execution Execution Unit.

Memory Segmentation:

The memory in 8086 based systems is organized as segmented memory. The physical memory is divided into a number of logical segments. Maximum size of each segment can be 64KB. The segments are accessed with the help of segment segment registers. The 16 bit content of segment register points to starting location of a particular segment. To address a location within a segment, an offset address is needed. The offset is 16 bit long therefore the size of segment is 216=64KB. 8086 can address 1MB of memory. Segment size is 64KB, therefore, 1MB/64 KB=16 i.e. the whole physical memory can be divided into 16 segments of 64 KB each. There are only 4 segment registers, therefore at a time we can access only 4 segments. The segments can be overlapped.


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Benefits of segmentation segmentation :

1) Segmentation allows memory capacity to be 1 MB. 2) It allows placing of code, data and stack portions of same program into different segments. It helps protection of code and data. 3) Segmentation allows multiprogramming. 4) Allows data sharing between two or more programs. 5) Segmentation makes it possible to create relocatable programs. 6) It allows creating multi-user and time-shared systems.

Address generation:

In order to access any memory location, 8086 microprocessor generates 20 bit address. Memory of 8086 based systems is divided into segments. To access a location in a particular segment, 8086 uses segment register. The content of segment register is shifted to left by 4 bit position. An offset value is added to this shifted content and the result is placed on address bus.

Fig. Physical address generation For example, if contents of CS=2000H and IP=1234H then in order to fetch instruction from memory: i) Shift contents of CS by 4 bit position: 2000  20000 ii) Add offset value (contents of IP) to this: this : 20000 1234 21234H


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iii) 21234H will be placed on address bus.

8284 Clock generator:

The 8284 generates 1) Clock (CLK) signal for 8086 microprocessor 2) READY signal for 8086 microprocessor 3) RESET signal for 8086 microprocessor CLK (Clock (Clock output):

This is system clock for microprocessor with 33% duty cycle. The frequency of this signal is 1/3 the frequency of crystal connected at X1, X2 or at EFI. OSC:

The frequency available at this output is same as crystal frequency or frequency input given at EFI. PCLK :

The frequency at this pin is half of the frequency fr equency available at CLK pin. F/̅:

If crystal is used to generate CLK signal then this pin is grounded. If EFI is used to generate CLK signal then this pin is made HIGH.

Fig. Pin diagram of 8284


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CSYNC:

This is synchronization signal and generally grounded. It all ows multiple 8284s to be synchronized to provide clocks that are in phase. ̅  ̅ Ready Synchronization Select (  ) is an active LOW input which defines the synchronization

mode of the READY logic. ̅ ̅ ,  , RDY1, RDY2:  ̅ Address Enable (  ) is an active LOW signal serves to qualify its respective bus Ready Signal ̅ ̅ (RDY1 or RDY2).  validates RDY1 while  validates RDY2. The two AEN signal

inputs are useful in system configurations which permit the processor to access two multi-master system busses. In non-multi-master configurations, the AEN signal inputs are tied true (LOW). ̅ : 

When this signal goes low, 8284 generates RESET signal for 8086.

Above figure shows interfacing of 8284 with 8086 microprocessor.

8288 Bus Controller :

In maximum mode, 8288 is used to generate different control signals. These signals are used to interface memory and I/O devices with 8086 microprocessor. Functions of 8288 :

1) To generate ALE signal for address latch 74LS373 or 8282. Computer Department, Jamia Polytechnic, Akkalkuwa

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 and DEN signals for data bus transceiver 74LS245 or 8286. 2) To generate DT/ 

3) To generate read/write signals for memory and I/O devices. 4) To generate ̅ signal for interrupt controller 8259.

̅ ,  ̅ ,  ̅ : These are status signals received from 8086. 8288 decodes these signals and generates 

different control signals. These control signals are generated in T2 of current bus cycle. ̅  ̅  ̅ 

Signal generated Description ------------------------------------------------------------------------------------------̅  0 0 0 Interrupt Acknowledge ̅  0 0 1 Read input port ̅  0 1 0 & ̅ Write to output port 0 1 1 Halt ̅ 1 0 0 Instruction fetch  ̅ 1 0 1 Read memory  ̅ ̅ 1 1 0 &  Write to memory  1 1 1 -Passive CEN: When it is HIGH, all commands are enabled. ̅ : When it is LOW, all commands are enabled. 

IOB: This signal is grounded in PC.  : When this signal is HIGH, microprocessor will transmit data. If this signal is LOW, DT/

microprocessor will receive data. DEN: This is used to enable data bus transceivers. ALE: This signal is used to enable latches in T1 of bus cycle. ̅  : This signal is generated in response of INTR signal. This is used to acknowledge interrupt

controller. ̅ MCE/ : When IOB=0, this functions as Master Cascade Enable indicating interrupt

controller is connected in cascade mode. When IOB=1, this pin acts as Peripheral Data Enable. Interfacing diagram of 8288 with 8086:


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Minimum mode of 8086 :

When MN/̅ is connected to logic 1(+5V), the 8086 operates in minimum mode. In this mode all control signals are generated by microprocessor. There is a single processor in minimum mode system. The other components in this mode are address latches (74LS373 or 8282), data transceivers (74LS245 or 8286), clock generator (8284), memory and I/O devices. Chip select logic is required for selecting memory or I/O devices. Address latches are used to separate address from multiplexed address/data signals. ALE signal is used to enable latches. Transceivers are used to separate data from multiplexed address/data lines. These are ̅ . controlled by two signals –  & DT/ 

Fig. below shows minimum mode 8086 system.


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Timing diagram - Read cycle of 8086 in minimum mode:

The Read cycle begins with generation of ALE and M/ ̅ signals in T1. During falling edge of ALE, ̅ the address is latched in address latches. Depending on the type of data access  and A0 may be

HIGH or LOW. During T1 to T4 M/ ̅ is HIGH for memory operations and it is LOW for IO ̅ is activated. operations. During T2, address is removed from the multiplexed address/data bus and  ̅ goes LOW, the multiplexed address/data bus is reserved for data transfer to 8086.  ̅ After  goes  remains LOW during whole read cycle. LOW during T2 and becomes HIGH in T4. DT/ 

Timing diagram - Write cycle of 8086 in minimum mode:

Write cycle begins with generation of ALE signal and placing the address on address bus. At the same time, M/̅ is activated to indicate memory or IO related operation. In T2, address is removed from the ̅ multiplexed address/data bus and data is placed on it. This data is available till the mid of T4. The   is pulled HIGH during T1 and remains up to T4.  ̅ becomes active at the beginning of T2. DT/  is ̅ . activated with 


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Maximum mode of 8086:

When MN/̅ is connected to ground, the 8086 operates in maximum mode. Instead of generating ̅ ,  ̅ ,  ̅ . Bus controller is used to generate control control signals, 8086 outputs status signals 

signal. There can be more than one processor in the system. The components in this mode are, address latches (74LS373 or 8282), data transceivers (74LS245 or 8286), clock generator (8284), bus controller (8288), memory and I/O devices. ̅ ,  ̅ ,  ̅ and CLK. It generates output signals ALE, DEN, DT/  , The bus controller has input lines  ̅ ̅ ̅ ̅ ̅ ,  ,  , ̅,  and  . It also generates ̅ signal. ̅ and ̅ are  ̅ ̅ used to read/write data from/to I/O devices.  and  are used as Memory Read Command ̅ and Memory Write Command signals. ̅ and  are advanced control signals which are ̅ ̅ activated one clock pulse earlier than  and  signals.

Fig. below shows maximum mode 8086 system. (Refer next page)


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Timing diagram of Read cycle in Maximum mode:

̅ ,  ̅ ,  ̅ signals are ̅ During T1, 8086 generates AD0-AD15, A16/S3-A19/S6,  /S7 signals. 

activated during T4 of previous cycle. These signals are connected to 8288. Depending upon these


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̅ ̅ ,  signals, 8288 generates ALE, DEN, DT/  / signals. ALE is generated during T1, also  becomes active during T1. Other signals are activated during T2. if READY goes LOW during DT/

T2 and T3, Tw will be added between T3 and T4.

Timing diagram of Write cycle in Maximum mode: ̅ ,  ̅ ,  ̅ signals are ̅ During T1, 8086 generates AD0-AD15, A16/S3-A19/S6,  /S7 signals. 

activated during T4 of previous cycle. These signals are connected to 8288. Using status signals, 8288 ̅ , ̅/ generates different control signals on behalf of 8086. ALE, DEN, DT/  control signals ̅  become active. In T2, DEN, ̅/ are generated by 8288. In T1, ALE and DT/  signals are

activated. If Ready signal goes LOW during T2 and T3, wait state Tw will be added after T3.

74LS245 Bi-directional Buffer:

To increase the driving capability of data bus, bi-directional buffer is used. Fig. below shows the logic diagram of the bi-directional buffer 74LS245. It is also called as octal bus transceiver. It consists of 16 non-inverting buffers, 8 for each direction with tri state output. The direction of data flow is controlled by DIR pin. When DIR is HIGH, data flows from A bus to B bus. When it is LOW, data flows from B to A. the active LOW enable signal and the DIR signals are ANDed to activate the bus lines.


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74LS373 Octal Latch

The IC 74LS373 is a octal latch with three state outputs. It is a 20 pin IC has eight input data lines (D0-D7) and eight output lines (O0-O7). The OE pin is used for Output enable and LE pin for Latch enable. And the rest two pins VCC for power supply and GND for Ground. The IC 74LS373 has eight D flip flops through which the input is given to the each pins of the IC. The Flip flops ’ data changes when the Latch enable (LE) is in High state. When the Latch Enable pin is pulled low, the data will be. The Output Enable pin also plays an important role in the working of this 74LS373 IC. When the (OE) pin is low input data will appear in the output. But when the OE is high the output will be in a high impedance state. This IC operates with maximum of 5 V and widely used in many kinds of electronic appliances.


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Write the difference between 8085 and 8086.

Differentiate between minimum mode and maximum mode of 8086 microprocessor (Eight points).


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2-16 Bit Microprocessor 8086

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