Morgan Kaufmann Publishers
May 14, 2014
The Computer Revolution
Progress in computer technology
Computer Abstractions and Technology
Underpinned by Moore’s Law
§ 1 .1 I n t r o d u c t i o n
Makes novel applications feasible
Computers in automobiles
Cell phones
Human genome project
World Wide Web
Search Engines
Computers are pervasive Chapter 1 — Computer Abstractions and Technology — 2
Classes of Computers
Desktop computers
General purpose, variety of software Subject to cost/performance tradeoff
Server computers
The Processor Market
Network based High capacity, performance, reliability Range from small servers to building sized
Embedded computers
Hidden as components of systems Stringent power/performance/cost constraints Chapter 1 — Computer Abstractions and Technology — 3
What You Will Learn
How programs are translated into the machine language
And how the hardware executes them
The hardware/software interface
What determines program performance
Chapter 1 — Computer Abstractions and Technology — 4
Understanding Understand ing Performance
Determine number of machine instructions executed per operation
Processor and memory system
Determines number of operations executed
Programming language, compiler, architecture
And how it can be improved
How hardware designers improve performance
Algorithm
Determine how fast instructions are executed
I/O system (including OS)
Determines how fast I/O operations are executed
What is parallel processing Chapter 1 — Computer Abstractions and Technology — 5
Chapter 1 — Computer Abstractions and Technology
Chapter 1 — Computer Abstractions and Technology — 6
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Morgan Kaufmann Publishers
May 14, 2014
Below Your Program
Application software
Written in high-level language
System software
Compiler: translates HLL code to machine code
§ 1 .2 B e l o w Y o u r P r o g r a m
Levels of Program Code
Operating System: service code
Handling input/output
Managing memory and storage
Scheduling tasks & sharing resources
High-level language
Assembly language
Hardware
Textual representation of instructions
Hardware representation
Level of abstraction closer to problem domain Provides for productivity and portability
Processor, memory, I/O controllers
Binary digits (bits) Encoded instructions and data
Chapter 1 — Computer Abstractions and Technology — 7
Components of a Computer
Same components for all kinds of computer
Desktop, server, embedded
§ 1 . 3 U n d e r t h e C o v e r s
Chapter 1 — Computer Abstractions and Technology — 8
Anatomy of a Computer Output device
Input/output includes
User-interface devices
Storage devices
Network adapters
Network cable
Display, keyboard, mouse Hard disk, CD/DVD, flash Input device
For communicating with other computers
Chapter 1 — Computer Abstractions and Technology — 9
Anatomy of a Mouse
Optical mouse
Basic image processor
Chapter 1 — Computer Abstractions and Technology — 10
Through the Looking Glass
LED illuminates desktop Small low-res camera
Input device
LCD screen: picture elements (pixels)
Mirrors content of frame buffer memory
Looks for x, y movement
Buttons & wheel
Supersedes roller-ball mechanical mouse
Chapter 1 — Computer Abstractions and Technology — 11
Chapter 1 — Computer Abstractions and Technology
Chapter 1 — Computer Abstractions and Technology — 12
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Morgan Kaufmann Publishers
Opening the Box
May 14, 2014
Inside the Processor (CPU)
Datapath: performs operations on data
Control: sequences datapath, memory, ...
Cache memory
Small fast SRAM memory for immediate access to data
Chapter 1 — Computer Abstractions and Technology — 13
Inside the Processor
Chapter 1 — Computer Abstractions and Technology — 14
Abstractions
AMD Barcelona: 4 processor cores
Abstraction helps us deal with complexity
Instruction set architecture (ISA)
The hardware/software interface
Application binary interface
Hide lower-level detail
The ISA plus system software interface
Implementation
The details underlying and interface
Chapter 1 — Computer Abstractions and Technology — 15
A Safe Place for Data
Volatile main memory
Networks
Communication and resource sharing
Local area network (LAN): Ethernet
Loses instructions and data when power off
Non-volatile secondary memory
Magnetic disk Flash memory
Optical disk (CDROM, DVD)
Chapter 1 — Computer Abstractions and Technology — 16
Chapter 1 — Computer Abstractions and Technology — 17
Chapter 1 — Computer Abstractions and Technology
Within a building
Wide area network (WAN: the Internet
Wireless network: WiFi, Bluetooth
Chapter 1 — Computer Abstractions and Technology — 18
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Morgan Kaufmann Publishers
May 14, 2014
Technology Trends
Defining Performance
Electronics technology continues to evolve
Increased capacity and performance
Which airplane has the best performance? Boeing 777
Boeing 777
Boeing 747
Boeing 747
BAC/Sud Concorde
BAC/Sud Concorde
Douglas DC-8-50
Douglas DC8-50
DRAM capacity
Reduced cost
0
1 00
2 00
3 00
4 00
0
5 00
Technology
1951
Vacuum tube
Relative performance/cost 1
1965
Transistor
1975
Integrated circuit (IC)
1995
Very large scale IC (VLSI)
2005
Ultra large scale IC
35 900 2,400,000
Boeing 777
Boeing 777
Boeing 747
Boeing 747
BAC/Sud Concorde
BAC/Sud Concorde
Douglas DC-8-50
Douglas DC8-50 0
500
6,200,000,000
Response Time and Throughput Response time
Execution timeY Execution timeX n
Example: time taken to run a program
Replacing the processor with a faster version? Adding more processors?
We’ll focus on response time f or now…
10s on A, 15s on B Execution TimeB / Execution Time A = 15s / 10s = 1.5 So A is 1.5 times faster than B
Chapter 1 — Computer Abstractions and Technology — 21
Measuring Execution Time
Elapsed time
Determines system performance Time spent processing a given job
CPU Clocking Operation of digital hardware governed by a constant-rate clock
Processing, I/O, OS overhead, idle time
CPU time
Chapter 1 — Computer Abstractions and Technology — 22
Total response time, including all aspects
Discounts I/O time, other jobs’ shares
Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance
Clock period Clock (cycles) Data transfer and computation Update state
Clock period: duration of a clock cycle
Chapter 1 — Computer Abstractions and Technology
e.g., 250ps = 0.25ns = 250×10 –12s
Clock frequency (rate): cycles per second
Chapter 1 — Computer Abstractions and Technology — 23
Passengers x mph
Performance X Performance Y
e.g., tasks/transactions/… per hour
How are response time and throughput affected by
1 00 00 0 2 0 00 00 3 00 00 0 4 00 00 0
Define Performance = 1/Execution Time “X is n time faster than Y”
Total work done per unit time
0
Relative Performance
Throughput
1500
Chapter 1 — Computer Abstractions and Technology — 20
How long it takes to do a t ask
1000
Cruising Speed (mph)
Chapter 1 — Computer Abstractions and Technology — 19
2000 4000 6000 8000 10000 Cruising Range (miles)
Passenger Capacity
Year
§ 1 .4 P e r f o r m a n c e
e.g., 4.0GHz = 4000MHz = 4.0 ×109Hz Chapter 1 — Computer Abstractions and Technology — 24
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Morgan Kaufmann Publishers
May 14, 2014
CPU Time
CPU Time Example
CPU Time CPU Clock Cycles Clock Cycle Time
Computer A: 2GHz clock, 10s CPU time
Designing Computer B
CPU Clock Cycles Clock Rate
Reducing number of clock cycles
Increasing clock rate
Aim for 6s CPU time Can do faster clock, but causes 1.2 × clock cycles
How fast must Computer B clock be?
Performance improved by
Clock CyclesB 1.2 Clock Cycles A CPU TimeB 6s
Clock RateB
Clock Cycles A CPU Time A Clock Rate A
Hardware designer must often trade off clock rate against cycle count
10s 2GHz 20 109 Clock RateB
1.2 20 109 24 109 4GHz 6s 6s
Chapter 1 — Computer Abstractions and Technology — 25
Chapter 1 — Computer Abstractions and Technology — 26
Instruction Count and CPI
CPI Example
Clock Cycles Instruction Count Cyclesper Instruction
CPU Time Instruction Count CPI Clock Cycle Time
Clock Rate
CPU Time Instruction Count CPI Cycle Time A A A A is faster… I 2.0 250ps I 500ps
Instruction Count for a program
Instruction Count CPI
Determined by program, ISA and compiler
CPU Time Instruction Count CPI Cycle Time B B B I 1.2 500ps I 600ps
Average cycles per instruction
Determined by CPU hardware
If different instructions have different CPI
Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same ISA Which is faster, and by how much?
CPU Time B I 600ps 1.2 CPU Time I 500ps A
Average CPI affected by instruction mix Chapter 1 — Computer Abstractions and Technology — 27
CPI in More Detail
n
Chapter 1 — Computer Abstractions and Technology — 28
CPI Example
If different instruction classes take different numbers of cycles Clock Cycles
Alternative compiled code sequences using instructions in classes A, B, C
(CPIi Instruction Counti )
i1
CPI
Weighted average CPI Clock Cycles Instruction Count
…by this much
Instruction Counti CPIi Instruction Count i1 n
Chapter 1 — Computer Abstractions and Technology
A
B
CPI for class
1
2
3
IC in sequence 1
2
1
2
IC in sequence 2
4
1
1
Sequence 1: IC = 5
Relative frequency
Chapter 1 — Computer Abstractions and Technology — 29
Class
Clock Cycles = 2×1 + 1×2 + 2×3 = 10
Sequence 2: IC = 6
Avg. CPI = 10/5 = 2.0
C
Clock Cycles = 4×1 + 1×2 + 1×3 =9 Avg. CPI = 9/6 = 1.5
Chapter 1 — Computer Abstractions and Technology — 30
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Performance Summary
CPU Time
May 14, 2014
Power Trends
Instructions Clock cycles Seconds Program Instruction Clock cycle
Performance depends on
Algorithm: affects IC, possibly CPI
Programming language: affects IC, CPI
Compiler: affects IC, CPI
Instruction set architecture: affects IC, CPI, Tc
Reducing Power
In CMOS IC technology Power Capacitive load Voltage2 Frequency ×30
Chapter 1 — Computer Abstractions and Technology — 31
§ 1 . 5 T h e P o w e r W a l l
5V → 1V
×1000
Chapter 1 — Computer Abstractions and Technology — 32
Uniprocessor Performance
Suppose a new CPU has
85% of capacitive load of old CPU
15% voltage and 15% frequency reduction
Pnew Cold 0.85 (Vold 0.85)2 Fold 0.85 0.854 0.52 2 Pold Cold Vold Fold
The power wall
We can’t reduce voltage further
We can’t remove more heat Constrained by power, instruction-level parallelism, memory latency
How else can we improve performance? Chapter 1 — Computer Abstractions and Technology — 33
Multiprocessors
Chapter 1 — Computer Abstractions and Technology — 34
Manufacturing ICs
Multicore microprocessors
More than one processor per chip
Requires explicitly parallel programming
Compare with instruction level parallelism
Hardware executes multiple instructions at once
Hidden from the programmer
§ 1 . 6 T h e S e a C h a n g e : T h e S w i t c h t o M u l t i p r o c e s s o r s
§ 1 .7 R e a l S t u f f : T h e A M D O p t e r o n X 4
Hard to do
Programming for performance Load balancing
Optimizing communication and synchronization
Chapter 1 — Computer Abstractions and Technology — 35
Chapter 1 — Computer Abstractions and Technology
Yield: proportion of working dies per wafer Chapter 1 — Computer Abstractions and Technology — 36
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Morgan Kaufmann Publishers
May 14, 2014
AMD Opteron X2 Wafer
Integrated Circuit Cost Cost per die
Cost per wafer Dies per wafer Yield
Dies per wafer Wafer area Die area Yield
Nonlinear relation to area and defect rate
1 (1 (Defects per area Die area/2))2
X2: 300mm wafer, 117 chips, 90nm technology X4: 45nm technology
Wafer cost and area are fixed
Defect rate determined by m anufacturing process
Die area determined by architecture and circuit design
Chapter 1 — Computer Abstractions and Technology — 37
SPEC CPU Benchmark
Supposedly typical of actual workload
Standard Performance Evaluation Corp (SPEC)
CINT2006 for Opteron X4 2356
Programs used to measure performance
Develops benchmarks for CPU, I/O, Web, …
SPEC CPU2006
Elapsed time to execute a selection of programs
Negligible I/O, so focuses on CPU performance
Normalize relative to reference machine Summarize as geometric mean of performance ratios
Chapter 1 — Computer Abstractions and Technology — 38
CINT2006 (integer) and CFP2006 (floating-point)
Name
Description
IC×109
CPI
Tc (ns)
Exec time
Ref time
perl
Interpreted string processing
2,118
0.75
0.40
637
9,777
15.3
bzip2
Block-sorting compression
2,389
0.85
0.40
817
9,650
11.8
gcc
GNU C Compiler
1,050
1.72
0.47
24
8,050
11.1
mcf
Combinatorial optimization
336
10.00
0.40
1,345
9,120
6.8
go
Go game (AI)
1,658
1.09
0.40
721
10,490
14.6
hmmer
Search gene sequence
2,783
0.80
0.40
890
9,330
10.5
sjeng
Chess game (AI)
2,176
0.96
0.48
37
12,100
14.5
libquantum
Quantum computer simulation
1,623
1.61
0.40
1,047
20,720
h264avc
Video compression
3,102
0.80
0.40
993
22,130
22.3
omnetpp
Discrete event simulation
587
2.94
0.40
690
6,250
9.1
astar
Games/path finding
1,082
1.79
0.40
773
7,020
9.1
xalancbmk
XML parsing
1,058
2.70
0.40
1,143
6,900
Geometric mean
SPECratio
19.8
6.0 11.7
n
n
Execution time ratio
i
High cache miss rates
i1
Chapter 1 — Computer Abstractions and Technology — 39
SPEC Power Benchmark
Power consumption of server at different workload levels
Performance: ssj_ops/sec Power: Watts (Joules/sec)
Overall ssj_opsper Watt ssj_opsi power i i0 i0 10
10
Chapter 1 — Computer Abstractions and Technology — 40
SPECpower_ssj2008 for X4 Target Load %
295
90%
211,282
286
80%
185,803
275
70%
163,427
265
60%
140,160
256
50%
118,324
246
40%
920,35
233
30%
70,500
222
20%
47,126
206
10%
23,066
180
0%
0
141
1,283,590
2,605
∑ssj_ops/ ∑power
Chapter 1 — Computer Abstractions and Technology
Average Power (Watts)
231,867
Overall sum
Chapter 1 — Computer Abstractions and Technology — 41
Performance (ssj_ops/sec)
100%
493
Chapter 1 — Computer Abstractions and Technology — 42
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Morgan Kaufmann Publishers
May 14, 2014
Pitfall: Amdahl’s Law
Improving an aspect of a computer and expecting a proportional improvement in overall performance Timproved
Taffected Tunaffected improvement factor
§ 1 . 8 F a l l a c i e s a n d P i t f a l l s
Example: multiply accounts for 80s/100s
Fallacy: Low Power at Idle
20
20
Can’t be done!
At 100% load: 295W
At 50% load: 246W (83%)
At 10% load: 180W (61%)
Google data center
n
How much improvement in multiply performance to get 5× overall? 80
Look back at X4 power benchmark
Corollary: make the common case fast
Mostly operates at 10% – 50% load At 100% load less than 1% of the time
Consider designing processors to make power proportional to load
Chapter 1 — Computer Abstractions and Technology — 43
Pitfall: MIPS as a Performance Metric
MIPS: Millions of Instructions Per Second
Concluding Remarks
Doesn’t account for
Differences in ISAs between computers
Differences in complexity between instructions
MIPS
Chapter 1 — Computer Abstractions and Technology — 44
Cost/performance is improving
Hierarchical layers of abstraction
Instruction count Execution time 106
Instruction count Clock rate 6 Instruction count CPI 106 CPI 10 Clock rate
CPI varies between programs on a given CPU
In both hardware and software
Instruction set architecture
Due to underlying technology development
The hardware/software interface
Execution time: the best performance measure Power is a limiting factor
Use parallelism to improve performance
Chapter 1 — Computer Abstractions and Technology — 45
Instruction Set Architecture
MIPS instruction set
MIPS is a RISC Computer
“simple” instructions
§ 1 . 9 C o n c l u d i n g R e m a r k s
Chapter 1 — Computer Abstractions and Technology — 46
MIPS
add r2, r0, r1 sub r3, r2, r1 sw MyLoc, r3
Load/store are done only with load/store instructions. Other operations are only done using registers.
Intel Instruction set (80x86)
More of a CISC instruction set
More complex/powerful(?) instructions
Most instructions can get things from memory. Chapter 1 — Computer Abstractions and Technology — 47
Chapter 1 — Computer Abstractions and Technology
Chapter 1 — Computer Abstractions and Technology — 48
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Morgan Kaufmann Publishers
May 14, 2014
Intel
mov r2, r0
Add r2, r1
Mov myLoc, r2
Sub myLoc, r1
Chapter 1 — Computer Abstractions and Technology — 49
Chapter 1 — Computer Abstractions and Technology
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