Ec2203-Unit IV Memory Devices Digital Electronics

EC2203-DE|G.Karthikeyan, EC2203-DE|G.Karthikey an, AP|ECE, SKPEC SKP EC

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EC2203-DIGITAL ELECTRONICS

UNIT IV - MEMORY DEVICES PART-I G.Karthikeyan M.E., AP | ECE, SKP Engineering College, Tiruvannamalai – 606611, Tamilnadu, India


CONTENTS •

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Introduction Classification of Memory ROM •

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RAM •

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Read Cycle Write Cycle

Memory Decoding •

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Static RAM Dynamic RAM RAM Organization DRAM organization

Memory Cycles and Timing Waveforms •

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PROM EPROM EEPROM ROM Origination

Coincident Decoding

Memory Expansion •

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Expanding Word Size Expanding memory Capacity

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CONTENTS •

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Introduction Classification of Memory ROM •

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RAM •

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Read Cycle Write Cycle

Memory Decoding •

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Static RAM Dynamic RAM RAM Organization DRAM organization

Memory Cycles and Timing Waveforms •

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PROM EPROM EEPROM ROM Origination

Coincident Decoding


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Expanding Word Size Expanding memory Capacity

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Introduction Name

Meaning/Operation

Memory Memory Location

It is made up of registers Each register in the memory is is one storage location. It is also called as memory location

Address Capacity

Used to identify the memory location The total no. of bits that a memory can store is its capacity (Most of the types of capacity is specified in terms of bytes. 1 byte=8bits)

Registers

Consists of storage elements {Flip flop or Capacitors =Semiconductor memories Magnetic domain = Magnetic storage}

Cell Write Read

It is a storage element The process of storing a data in to a memory The process of retrieving the data from the memory

EC2203-DE|G.Karthikeyan, AP|ECE, SKPEC

Read & Write operation

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Block diagram of memory unit

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How a communication is takes place between memory and its environment 1.

Data lines Provides the information stored in the memory

2. Address selection lines Specify the particular word

3. Control Lines Direction of transfer

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Classification of memory CLASSIFICATION OF SEMICONDUCTOR MEMORIES NON VOLATILE READ ONLY READ/WRITE MEMORY (ROM) MEMORY (NVRAM) MaskEPROM Programmable ROM Programmable EEPROM ROM Flash

VOLATILE READ/WRITE MEMORY (PWM)

RANDOM ACCESS

NON RANDOM ACCESS

SRAM

FIFO

DRAM

LIFO Shift Registers


ROM (Read only Memory) 1. PROM 2. EPROM 3. EEPROM 4. ROM ORGANIZATION

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ROM CELL

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PROM (Programmable Read Only Memory)


Four Byte PROM •

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Diode: Initially all 0 Proper current pulse: to blow the fuse Fuse material: Nichrome & Polycrystalline Current range to blow fuse: 20 to 50mA Time: 5 to 20µs Also called as “burning of PROM”

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EPROM (Erasable Programmable Read Only Memory) •

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Uses MOS circuitry Store 1s & 0s Programmed by user Erasing the date: by using Ultraviolet light through its quartz window Time: 20minutes Erasing: Entire information lost


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EEPROM (Electrically Erasable Programmable Read Only Memory)

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Very Similar to EPROM The insulating layer: very thin (i.e) <200Ao Voltage: 20 to 25 V for programming or erasing Selective information can be erased Time: 10ms

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ROM Organization •

Simple Four Byte Diode ROM

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1

A

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5

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ROM ORGANIZATION (CONTD…) •

Contents of ROM Address in binary

00 01 10

Binary Data

D0 1 0 0

D1 0 1 1

D2 1 0 0

D3 0 1 0

D4 0 0 0

D5 1 0 1

D6 0 0 1

D7 1 1 0

Data in Hexa decimal

A5 51 46


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ROM ORGANIZATION (CONTD…)


RAM (Random Access Memory) Static RAM (SRAM)

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Static RAM Cell

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Read Operation Write operation 

Bipolar RAM Cell MOSFET RAM Cell 

Dynamic RAM (DRAM)

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Dynamic RAM Cell

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COMPARISON BETWEEN SRAM AND DRAM

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STATIC RAM CELL •

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Read Operation Write Operation

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BIPOLAR RAM CELL

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MOSFET RAM CELL

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Dynamic RAM (DRAM) •

Dynamic Ram Cell

Storage Capacitor

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COMPARISON BETWEEN SRAM AND DRAM Sl.No 1

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Static RAM

Dynamic RAM

Static RAM contains less memory Dynamic RAM contains more memory cells per area. cells as compared to static RAM per unit area It has less access time hence Its access time is greater than static faster memories RAMs

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Static RAM consists of flip-flops. Dynamic RAM stores the data as a Each flip-flop stores one bit charge on the capacitor. It consists of MOSFET and the capacitor for each cell.

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Refreshing required.

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Cost is more

circuitry

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not Refreshing circuitry is required to maintain the charge on the capacitors after every few milliseconds. Extra hardware is required to control refreshing. This makes system design complicated. Cost is less


RAM Organization •

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RAM organization: in the form of Array Each cell: capable of storing one bit information Memory chip: 8191 bit Line decoder 64 rows 128 columns i.e 64x128=8192 memory cells •

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13 address lines •

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6 for rows ( 0 to 5 ) 7 for columns ( 0 to 6 )

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DRAM Organization •

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Two dimensional It is a 16 M-bit DRAM. Configured as 2M x 8 Cells organized 4Kx4K array 4096 cells addressed by 12 address bits It can store 512x8, i.e 512 bytes 21 address lines •

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9 for column ( 0 to 8) 12 for row ( 9 to 20)

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DRAM ORGANIZATION (CONTD…) •

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Configured as 2Mx4 Row & Column address lines multiplexed: To reduce number of pins So, less address pins than SRAM chip 11 address lines: to select one of 2048 lines for output 211=2048


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Memory Cycles and Timing Waveforms

Read Cycle 1. tRC 2. tAA 3. tOH 4. tLZ 5. tACS 6. tHZ 7. tOE 8. tDF 9. tPU 10. tPD •

ADDRESS DATA CS OE SYPPLY CURRENT


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Memory Cycles and Timing Waveforms

Write Cycle 1. tWC 2. tAW 3. tWR 4. tAS 5. tCW 6. tWP 7. tDW 8. tDH •


Memory Decoding •

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Decoder operation 16 words of 8 bits each A memory with 16 words needs 4 address lines So, 4 x16 decoder is used If memory enable = 0 •

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If memory enable = 1 •

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No memory word is select One of the 16 word is selected

Read/write determines the operation Write operation: •

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Data transferred in to eight memory cells If a memory cell is not selected, that is disabled and the previous value remain unchanged

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Coincident Decoding •

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k input 2k output 2k and gates are needed with k input to each gate So, 2 decoders used to reduce the no. of inputs So k/2 inputs to each decoder instead of k inputs Instead of 10 x 1024 we use 5 x 32 decoders

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Illustrate The Concept of 16 X 8 Bit ROM Arrange With Diagram


Explain the Basic Structure of 256 X 4 Static RAM, with neat diagram

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2 methods 1. Expanding word size 2. Expanding memory capacity 3. Limitations for memory expansion 4. Example Problems

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Expanding Word Size

By connecting 2 or more ICs together Data bus: In Series Address bus: In parallel Chip select: common to Both memory ICs Word size is limited: by Data bus width

Design 1 K X 8 RAM using two 1 K X4 ICs


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Expanding Memory Capacity

By connecting 2 or more ICs in parallel i.e. The address & data bus connected in parallel Chip select: separate to each cell(generated by address decoder) Capacity is limited: by address bus width

Design 16 K X 8 RAM using four 4 K X 8 ICs


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Limitations for memory Expansion

Memory devices: Processors accessed using Address, data & Control bus But Each Processor has limited no. of address lines & data lines Eg:Suppose a processor has 24 address lines & 16 data lines, we can expand memory word size up to 16 Memory capacity up to 224 = 16Mbytes


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How one can make 64x8 ROM using four 32x4 ROMs? Draw such a circuit and explain •

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64x8 ROM = Four 32x4 ROM Two pair ICs Data bus: In series Address bus: In parallel In two pair: The data, address & control bus: In parallel To address 32 memory locations: 5 address lines(A0 to A4) needed The additional line: used to select the particular pair(A5)


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Given the 32x8 ROM chip with enable input, show the external connection necessary to construct a 128x8 ROM with four chips and a decoder

Ec2203-Unit IV Memory Devices Digital Electronics

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