LAPORAN RESMI PRAKTIKUM VHDL

LAPORAN RESMI PRAKTIKUM

VHDL

Disusun Oleh :

FAHRIZAL F UMARILA 08530107

LABORATORIUM ELEKTRONIKA FAKULTAS TEKNIK UNIVERSITAS MUHAMMADIYAH MALANG 2011

LEMBAR PERSETUJUAN Telah diperiksa dan disetujui Isi laporan ini

LAPORAN PRAKTIKUM VHDL

FAKULTAS TEKNIK LABORATORIUM ELEKTRONIKA UNIVERSITAS MUHAMMADIYAH MALANG

Disusun oleh Nama Nim Kelompok Tgl praktikum

: Fahrizal Febrifta Umarila : 08530107 : : 15 Oktober 2011

Malang, Desember 2011 Mengetahui, Kepala Laboratorium Elektronika

Menyetujui, Koordinator Asisten Praktikum

Ir. Nur Alif M, M.T

Dwi Ari Cahyanto

2

KATA PENGANTAR Assalamualaikum. Wr. Wb Puji syukur ke hadirat Allah Swt yang telah memberikan segala rahmat, nikmat dan hidayahnya. Sehingga saya bisa menyelesaikan tugas dalam pembuatan laporan praktikum kali ini. Sesuai dengan peraturan yang telah diberikan kepada seluruh praktikan yang mengikuti praktikum VHDL ada tahun ini. Bahwa semua laporan yang telah selesai di ACC harus dijadikan satu dan disusun dalam bentuk sudah dijilid. Dan oleh karena itu maka laporan ini dibuat. Kesemua data yang terkait dengan praktikum yang materinya saya ikuti dapat didapatkan di blog saya di www.elektronika2008.blogspot.com juga pada www.sribd.com semoga saja semua ini nantinya dapat membantu praktikan lainnya untuk memahami dengan baik, juga bagi saya agar dengan pengetahuan yang sudah ada ini semakin berkembang dan bertambah. Saya ingin mengucapkan terima kasih kepada orang – orang yang berada di sekitar saya yang sudah membantu banyak sekali dalam penyelesaian laporan ini. Ucapan terima kasih saya berikan kepada : 1. Istri saya tercinta, Eki Mahbubati Nazwa, yang sudah memberikan support yang luar biasanya dalam mengerjakan laporan ini. 2. Anak saya yang berada dalam kandungan, yang terus memberikan saya semangat walaupun tanpa berkata – kata. 3. Orang tua, yang sudah melahirkan saya. 4. Teman – teman satu jurusan yang sudah banyak membantu dalam memberikan data yang benar – benar kompeten dan benar. Dalam penulisan laporan ini, saya yakin tidak semuanya akan benar – benar sempurna 100 %. Maka saya mohon maaf atas segala kesalahan yang sudah ada dalam penulisan ini baik disengaja ataupun tidak. Untuk kritik dan saran saya terima secara langsung, atau bisa lewat email di [email protected] Akhir kata saya ucapkan terima kasih sebanyak – banyaknya dan Wassalamualaikum. Wr. Wb

Salam Hormat Penyusun

Fahrizal F Umarila 08530107 3

DAFTAR ISI

..................................................................................................... ............................................... 2 LEMBAR PERSETUJUAN ...................................................... KATA PENGANTAR ........................................................ .............................................................................................................. ........................................................ 3 DAFTAR ISI .............................................................................................................................. 4 DAFTAR GAMBAR .......................................................... ................................................................................................................ ........................................................ 9

........................................................................................................... ............................................................... ......... 10 DAFTAR TABEL .....................................................

............................................................................................................ ..................................................... 11 11 LEMBAR ASISTENSI....................................................... BAB I ........................................................................................................................................ 12

1.1

Pengertian Pengertian VHDL ................................................ ....................................................... 12

1.2

Struktur Program Program VHDL ........................................................ ............................................................................................ .................................... 12

1.2.1

Entity Declaration Declaration ................................................................................................ 13

1.2.2

Architecture Architecture Body.............................................................................. .................. 15

1.3

Proses Pemrograman Pemrograman VHDL .................................................. .................................... 15

1.4

Makalah VHDL ................................................................................................. ......................................... ................................................................. ......... 17

LEMBAR ASISTENSI....................................................... ............................................................................................................ ..................................................... 25 25 BAB II ....................................................................................................................................... 26

2.1

TUJUAN ................................................................................................... .................. 26 26

2.2

DASAR TEORI ................................................... ....................................................... 26

2.2.1

Compiler Warp ....................................................... ............................................. 26

2.2.2

Simulator Nova ............................................................................................. ....... 29 29

2.3

PERCOBAAN PERCOBAAN ........................................................................ ................ ............................................................................................ .................................... 30

2.4

TUGAS .......................................................................... ............................................. 32

2.4.1

Tugas Rangkaian 3 Kombinasi Logika Dasar ..................................................... 33

2.4.1.1

Gambar Rangkaian Logika........................................................................... 33

2.4.1.2

Listing Program........................................................ ............................................................................................ .................................... 33

2.4.1.3

Tabel Kebenaran ................................... ....................................................... 33

2.4.1.4

Simulasi NOVA ............................ ...................................................... ............................................................... ......... 34

2.4.1.5

Report File ....................................................... .................................................................................................... ............................................. 34 4

2.5

Analisa Hasil Percobaan Percobaan ......................................................... .................................... 40

2.6

Kesimpulan Kesimpulan Percobaan Percobaan .................................................. ............................................. 42 42

LEMBAR ASISTENSI....................................................... ............................................................................................................ ..................................................... 43 43 BAB III ..................................................................................................................................... 44

3.1

TUJUAN ................................................................................................... .................. 44 44

3.2

DASAR TEORI ................................................... ....................................................... 44

3.2.1

Rangkaian Rangkaian Combinational Combinational .............................. ..................................................... 44

3.2.2

Multiplexer Multiplexer ........................ ........................................................ .................................................................................. .......................... 45 45

3.2.3

Dekoder .......................................................... ..................................................... 46

3.3


3.4

TUGAS .......................................................................... ............................................. 47

3.4.1

Tugas Multiplexer 4 Masukan ................................................... .......................... 48

3.4.1.1


3.4.1.2

Listing Program........................................................ ............................................................................................ .................................... 48

3.4.1.3

Tabel Kebenaran ................................... ....................................................... 49

3.4.1.4

Simulasi NOVA ............................ ...................................................... ............................................................... ......... 49

3.4.1.5

Report File ....................................................... .................................................................................................... ............................................. 50

3.4.2

Tugas Demultiplexer Demultiplexer Keluaran Keluaran 4 ......................................................... ......................................................................... ................ 56 56

3.4.2.1


3.4.2.2

Listing Program........................................................ ............................................................................................ .................................... 56

3.4.2.3

Tabel Kebenaran ................................... ....................................................... 57

3.4.2.4

Simulasi NOVA ............................ ...................................................... ............................................................... ......... 57

3.4.2.5

Report File ....................................................... .................................................................................................... ............................................. 58

3.4.3

Tugas Rangkaian Decoder 3 Ke 8 ................................... .................................... 64

3.4.3.1


3.4.3.2

Listing Program........................................................ ............................................................................................ .................................... 64

3.4.3.3

Tabel Kebenaran ................................... ....................................................... 66

3.4.3.4

Simulasi NOVA ............................ ...................................................... ............................................................... ......... 66

3.4.3.5

Report File ....................................................... .................................................................................................... ............................................. 67

3.5

Analisa Percobaan Percobaan................................................ ....................................................... 73

3.6

Kesimpulan Kesimpulan Percobaan Percobaan .................................................. ............................................. 75 75

5

............................................................................................................ ..................................................... 76 76 LEMBAR ASISTENSI....................................................... ........................................................................................................... ............................................................... ......... 77 PERCOBAAN IV ..................................................... 4.1

TUJUAN ................................................................................................... .................. 77 77

4.2

DASAR TEORI ................................................... ....................................................... 77

4.3


4.3.1

Program 1 : ................................................................................ ........................ .................................................................................. .......................... 79

4.3.2

Program 2 : ................................................................................ ........................ .................................................................................. .......................... 80

4.3.3

Program 3 : ................................................................................ ........................ .................................................................................. .......................... 80

4.4

TUGAS .......................................................................... ............................................. 81

4.4.1

4.5

Tugas Membuat Rangkaian Rangkaian Sequensial Sequensial ...................................................... ............................................................... ......... 82 82

4.4.1.1


4.4.1.2

Listing Program........................................................ ............................................................................................ .................................... 82

4.4.1.3

Tabel Kebenaran ................................... ....................................................... 83

4.4.1.4

Simulasi NOVA ............................ ...................................................... ............................................................... ......... 83

4.4.1.5

Report File ....................................................... .................................................................................................... ............................................. 83

Analisa Percobaan Percobaan................................................ ....................................................... 89

LEMBAR ASISTENSI....................................................... ............................................................................................................ ..................................................... 93 93 PERCOBAAN V ....................................................... ............................................................................................................. ............................................................... ......... 94

5.1

TUJUAN ................................................................................................... .................. 94 94

5.2

DASAR TEORI ................................................... ....................................................... 94

5.2.1

DESKRIPSI DESKRIPSI STRUKTURAL ................................ ............................................. 94

5.2.2

DESKRIPSI DESKRIPSI BEHAVIORAL .................................................... .............................................................................. .......................... 95

5.2.3

DESKRIPSI DESKRIPSI DATA FLOW........................................................................ ......... 96

5.3


5.3.1

Program 1 (Structural) (Structural) : ............................................................. .......................... 96

5.3.2

Program 2 (Behavioral) (Behavioral) : ................................ ..................................................... 97

5.3.3

Program 3 (Data Flow) : ...................................................................................... 98

5.4

TUGAS .......................................................................... ............................................. 98

5.4.1

Tugas Membuat Rangkaian Up / Down Counter ................................................ 99

5.4.1.1


5.4.1.2

Listing Program........................................................ ............................................................................................ .................................... 99 6

5.4.1.3

Tabel Kebenaran ..................................................... ......................................................................................... .................................... 99

5.4.1.4

Simulasi NOVA ............................ ...................................................... ............................................................. ....... 100

5.4.1.5

Report file........................................................ ................................................................................................... ........................................... 100

5.4.2

5.4.2.1

Gambar Rangkaian Logika......................................................................... 106 106

5.4.2.2

Listing Program........................................................ .......................................................................................... .................................. 106

5.4.2.3

Tabel Kebenaran ..................................................... ....................................................................................... .................................. 107

5.4.2.4

Simulasi NOVA ............................ ...................................................... ............................................................. ....... 107

5.4.2.5

Report file........................................................ ................................................................................................... ........................................... 107

5.4.3

Tugas Rangkaian Up / Down Demultiplexer ............................................. ....... 113

5.4.3.1


5.4.3.2

Listing Program........................................................ .......................................................................................... .................................. 113

5.4.3.3

Tabel Kebenaran ..................................................... ....................................................................................... .................................. 114

5.4.3.4

Simulasi NOVA ............................ ...................................................... ............................................................. ....... 114

5.4.3.5

Report File ....................................................... .................................................................................................. ........................................... 115

5.4.4

5.5

Tugas Rangkaian Up / Down Register .............................................................. 106 106

Tugas Rangkaian Rangkaian Decoder............................................... .................................. 121

5.4.4.1


5.4.4.2

Listing Program........................................................ .......................................................................................... .................................. 121

5.4.4.3

Tabel Kebenaran ..................................................... ....................................................................................... .................................. 122

5.4.4.4

Simulasi NOVA ............................ ...................................................... ............................................................. ....... 122

5.4.4.5

Report File ....................................................... .................................................................................................. ........................................... 122

Analisa Hasil Percobaan Percobaan ................................................ ........................................... 128 128

5.5.1

Analisa Register...................................................... ................................................................................................. ........................................... 128

5.5.2

Analisa Counter ............................................................... .................................. 130 130

5.5.3

Analisa Encoder...................................................... ................................................................................................. ........................................... 131

5.6

Kesimpulan Kesimpulan Percobaan Percobaan .................................................. ........................................... 132 132

PERCOBAAN PERCOBAAN VI ....................................................... ............................................................................................................. ............................................................. ....... 133 133 6.1

Tujuan ..................................................................................... .................................. 133 133

6.2

Simulasi FSM dengan menggunakan STATECAD .................................................. 133

6.3

Percobaan Percobaan ....................................................................... ........................................... 136

6.4

Tugas.................................................. ....................................................... ....................................................................... ................ 136

7

PERCOBAAN PERCOBAAN VII V II ............................................................... ................................................... 137 137 7.1

Tujuan ..................................................................................... .................................. 137 137

7.2

Dasar Teori ............................................................................. ..................... .......................................................................................... .................................. 137

7.3

Percobaan Percobaan ....................................................................... ........................................... 138

7.4

Tugas.................................................. ....................................................... ....................................................................... ................ 139

8

DAFTAR GAMBAR

Gambar 1-1. Hasil Simulasi Simulasi Nova Tabel 1 ................................................................................ 16 Gambar 2-1. Window Galaxy Dan Project ...................................................... ................................................................................ .......................... 26 Gambar 2-2. Window New Project ........................................................................................... 27 Gambar 2-3. Window VHDL Editor ....................................................................... .................. 27 Gambar 2-4. Window Directory VHDL ................................................ .................................... 28 Gambar 2-5. Window Project VHDL .................................................... ........................................................................................ .................................... 28 Gambar 2-6. Window Device VHDL .................................................... ........................................................................................ .................................... 29 Gambar 2-7. Compiling VHDL .................................................... ................................................................................................. ............................................. 29 Gambar 2-8. Simulasi Nova N ova .................................................................. .................................... 30 Gambar 2-9. Gerbang Logika ....................................................... .................................................................................................... ............................................. 30 Gambar 2-10. Rangkaian Kombinasi Logika Logika ............................................................................ 31 Gambar 2-11. Rangkaian Kombinasi 3 Logika Dasar ...................................................... ............................................................... ......... 33 Gambar 2-12. Hasil Simulasi Nova 3 Logika Dasar ............................................... .................. 34 Gambar 3-1. Rangkaian Rangkaian Kombinasi ................................................................................. ......... 44 Gambar 3-2. Rangkaian Rangkaian Multiplexer Multiplexer ......................................................................................... 45 Gambar 3-3. Rangkaian Multiplexer 4 Masukan ...................................................................... 48 Gambar 3-4. Hasil Simulasi Simulasi Nova Untuk Multiplexer 4 Masukan .......................................... 49 Gambar 3-5. Rangkaian Rangkaian Demultiplexer Demultiplexer 4 Keluaran ................................................ .................. 56 Gambar 3-6. Hasil Simulasi Simulasi Nova Demultiplexer 4 Keluaran .................................................. 57 57 Gambar 3-7. Rangkaian Logika Decoder 3 Ke 8 ............................................................... ..... ................................................................. ....... 64 Gambar 3-8. Hasil Simulasi Simulasi Nova Decoder 3 Ke 8 ................................................... ................ 66 Gambar 4-1. Rangkaian Rangkaian Sequencial Sequencial dengan Enable ................................................ .................. 77 Gambar 4-2. Rangkaian Sequensial dengan Clock .. .......................................................... ................................................................. ....... 78 Gambar 4-3. Rangkaian Rangkaian Sequensial Sequensial dengan Reset dan Rising Edge......................................... 78 78 Gambar 4-4. Rangkaian Rangkaian Sekuensial....................................................... Sekuensial........................................................................................... .................................... 82 Gambar 4-5. Hasil Simulasi Simulasi Nova Rangkaian Sekuensial ............................................... ......... 83 Gambar 5-1. Rangkaian Up / Down Counter ............................................................................ 99 Gambar 5-2. Hasil Simulasi Simulasi Nova Untuk Up/Down Counter ................................................. 100 Gambar 5-3. Rangkaian Rangkaian Up / Down Register .................................................. ........................ 106 Gambar 5-4. Hasil Simulasi Simulasi Nova Untuk Up / Down Register ............................................... 107 107 Gambar 5-5. Rangkaian Rangkaian Logika Up / Down Demultiplexer .................................................... 113 113 Gambar 5-6. Hasil Simulasi Simulasi Nova Rangkaian Up / Down Demultiplexer .............................. 114 Gambar 5-7. Rangkaian Rangkaian Up / Down Encoder ................................................. ........................ 121 Gambar 5-8. Hasil Simulasi Simulasi Nova Rangkaian Up / Down Encoder ........................................ 122 Gambar 6-1. State Diagram Simulasi Traffic Light ......................................................... ....... 133 Gambar 7-1. ALL-11 .................................................. ...................................................... ............................................................. ....... 137 Gambar 7-2. Window WPLD1.EXE ................................................................................ ....... 138

9

DAFTAR TABEL Tabel 1-1. Tabel Kebenaran dari rangkaian rangkaian kombinasi kombinasi AND dan OR ...................................... 15 15 Tabel 2-1. Tabel Kebenaran Kebenaran Gerbang OR ....................................................... ................................................................................. .......................... 33 Tabel 3-1. Tabel Kebenaran Multiplexer 4 Masukan....................................................... ................................................................ ......... 49 Tabel 3-2. Tabel Kebenaran Kebenaran Demultiplexer 4 Keluaran............................................................ 57 Tabel 3-3. Tabel Kebenaran Decoder 3 Ke 8 ............................................................................ .................................................. .......................... 66 Tabel 4-1. Tabel Kebenaran Sekuensial Sekuensial .................................................................................... 83 Tabel 5-1. Tabel Kebenaran Kebenaran Up / Down Counter...................................................... ...................................................................... ................ 99 Tabel 5-2. Tabel Kebenaran Kebenaran Rangkaian Up / Down Register ................................................. 107 Tabel 5-3. Tabel Kebenaran Kebenaran Rangkaian Up / Down Demultiplexer ....................................... 114 Tabel 5-4. Tabel Kebenaran Kebenaran Rangkaian Up / Down Encoder Encoder ................................................. 122

10


LEMBAR ASISTENSI VHDL Judul percobaan

: PENGANTAR VHDL

Nama Praktikan

: Fahrizal Febrifta Umarila

NIM

: 08530107

Tanggal Pelaksanaan

: 15 Oktober 2011

Asisten Pembimbing

: Dwi Ari Cahyanto

Tanda Tangan

:

Instruktur

:

Tanda Tangan

:

Tanggal

:

Tanggal

:

Disetujui Kord. Praktikum : Dwi Ari Cahyanto Tanda Tangan

:

Tanggal

:

11

1 BAB I

PENGANTAR VHDL

1.1

Pengertian VHDL

Vhdl (VHSIC Hardware Description Language) merupakan bahasa tingkat tinggi yang dapat digunakan untuk memrogram suatu IC digital yang didalamnya terdiri dari gate-gate gate-gate yang jumlahnya ratusan gate. Seperti bahasa pemrograman lain, VHDL juga memiliki memiliki aturan penulisan sintak sistematika yang digunakan. digunakan. Dengan kata lain VHDL merupakan bahasa yang dipakai untuk menuliskan logika sebuah perancangan system elektronika yang logikanya akan diisikan pada device yang programmable untuk mengatur logika dari perancangan elektronika yang dibuat. Jenis-jenis programmable device yang bias digunakan dengan dengan VHDL adalah: < 500 gate PLD (Programable Logic Device) > 500 dan > 5.000 gate CPLD (Comlpex Programable Logic Device) > 500 dan > 10.000 gate FPGA (Fast Programable Gate Array) > 10.000 dan > 20.000 ASIC (Aplication Spesific Integrated Circuit) Seluruh jenis device di atas pada dasarnya adalah gate-gate kosong yang siap disambungkan dengan berbagai logika perancangan elektronika tanpa terikat pada keterbatasan fungsi maupun jumlah pin yang dibutuhkan untuk perancangan seperti halnya jenis IC TTL dan CMOS. Namun pada praktikum ini akan lebih banyak menggunakan jenis IC PLD (Programable Logic Device) seperti PAL, PALCE dan GAL. Secara garis besar langkah pemrograman device dengan VHDL adalah :  Tentukan Desain yang akan di program yang dilanjutkan dengan membuat algoritma dan table kebenaran dari desain.  Buat desain dengan bahasa VHDL dan kompilasi program dengan Warp.  Lakukan Simulasi untuk menguji kebenaran logika desain dengan Simulator Nova.  Isikan program hasil kompilasi dan simulasi ke dalam device dengan ALL-11.    

1.2

Struktur Program VHDL

Struktur program VHDL pada dasarnya hampir sama dengan program bahasa tinggi yang lain. Pemrograman VHDL dengan Warp harus menggunakan kaidah pemrograman yang sudah ditetapkan vendor yang bersangkutan, namun umumnya mengacu pada standart IEEE. Pada bagian awal program akan dijelaskan terlebih dahulu identitas bagi port input dan output yang disebut dengan bagian Entity. Kemudian pada bagian berikutnya diberikan statemen logika dari alur program yang dibuat dalam sebuah bagian yang disebut Architecture Body.

12

Secara umum struktur program VHDL dapat digambarkan sebagai berikut :

Interface (Entity Delcaration)

Body (Architecture) Sequential, Combinational Processes

1.2.1

Entity Declaration

Entity secara umum dapat dideklarasikan dengan mpdel berikut :

Entity NAME_OF_ENTITY Is Port (signal_names (signal_names : mode type; type; signal_names : mode type); type); End [NAME_OF_ENTITY]; Mode berupa: IN untuk menerangkan identitas port masukan, OUT untuk menerangkan identitas port keluaran, BUFFER untuk menerangkan identitas port tersebut berupa Buffer, dan INOUT untuk menerangkan identitas port tersebut bias menjadi masukan sekaligus keluaran. Type berupa: i. BIT - berupa bilangan 0 dan 1. ii. BIT_VECTOR - berupa vector dari nilai bit (BIT_VECTOR 0 TO 7) iii. Std_Logic – banyak digunakan digunakan untuk jenis rangkaian sequensial. sequensial. iv. Std_Ulogic – Digunakan untuk jenis rangkaian rangkaian sequensial. sequensial. v. Std_Logic_Vector – Jika ada Vektor Berikut ini adalah contoh dari berbagai model pendeklarasian bagian Entity dari program VHDL : Contoh 1 (Rangkaian Combinational) :

Library ieee ; Use ieee.Std_Logic_1164.all; Entity Combinational Is Port ( A, B, C : In BIT; D : Out BIT ); End Combinational; Contoh 2 (Rangkaian Combinational) :

Library ieee ; Use ieee.Std_Logic_1164.all; 13

Entity Combinational Is Port ( A : In Bit_Vector ( 0 to 2 ); D : Out BIT ); End Combinational; Pendeklarasian port pada Entity untuk rangkaian kombinasional type-nya type-nya biasanya berupa Bit atau Bit_Vector Contoh 3 (D Flip-Flop) :

Library ieee ; Use ieee.Std_Logic_1164.all; Entity D_FF Is Port ( D, CLK : In Std_Logic; Q, Q_Bar : Out Std_Logic ); End D_FF; Contoh 4 (Multiplexer4) :

Library ieee ; Use ieee.Std_Logic_1164.all; Entity Mux_4 Is Port (A: In Std_Logic_Vector (3 Downto 0); Sel : In Std_logic_Vector(0 to 1); OUT : Out Std_Logic); End Mux_4; Pendeklarasian port pada Entity untuk rangkaian kombinasional, multiplexer atau sequensial type-nya type-nya biasanya berupa Std_Logic atau Std_Logic_Vector Contoh 5 (Full_Adder) :

Library ieee ; Use ieee.Std_Logic_1164.all; Entity Full_Adder Is Port ( A0, B0, Ci C0, S0 End Full_Adder;

: In Std_Ulogic; : Out Std_Ulogic );

Pendeklarasian port pada Entity untuk rangkaian Half Adder dan Full Adder type-nya type-nya berupa Std_Ulogic atau Std_Ulogic_Vector

14

1.2.2

Architecture Body

Architecture Body merupakan inti dari program VHDL, dengan format sebagai berikut:

Architecture Architecture_Name Of NAME_OF_ENTITY Is Begin --------- Statement End Architecture_Name; Contoh 2 :

Architecture behav1 of AND_ent Is Begin Process(x, y) Begin -- compare to truth table If ((x='1') And (y='1')) Then F <= '1'; Else F <= '0'; End If; End Process; End behav1; 1.3

Proses Pemrograman VHDL

Berikut ini akan diberikan gambaran proses pembuatan program rangkaian kombinasi dari gerbang logika sederhana : (…………………Combinational Gate………………) F =((A AND B ) OR C)

Tabel 1-1. Tabel Kebenaran dari rangkaian kombinasi AND dan OR A 0 1 0 1 0 1 0 1

B 0 0 1 1 0 0 1 1

C 0 0 0 0 1 1 1 1

A AND B 0 0 0 1 0 0 0 1

Program VHDL dari rangkaian di atas :

Entity Combinational Is Port ( A, B, C, : In BIT; 15

F 0 0 0 1 1 1 1 1

Y : Out BIT ); End Combinational; Architecture Contoh1 Of Combinational Is Begin F <= ((A AND B) OR C); End Contoh1; Simulasi Nova :

Gambar 1-1. Hasil Simulasi Nova Tabel 1

16

1.4

Makalah VHDL

Tulis Tangan Halaman 1

17

Makalah VHDL Tulis Tangan Halaman 2

18


19


20


21


22


23


24



: KOMPILER WARP DAN SIMULATOR NOVA

Nama Praktikan


NIM

: 08530107

Tanggal Pelaksanaan

: 15 Oktober 2011

Asisten Pembimbing

: Dwi Ari Cahyanto

Tanda Tangan

:

Instruktur

:

Tanda Tangan

:

Tanggal

:

Tanggal

:


:

Tanggal

:

25

2 BAB II KOMPILER WARP DAN SIMULATOR NOVA

2.1

TUJUAN

Peserta praktikum dapat menggunakan compiler Warp untuk mengkompilasi program dan dapat menggunakan Nova sebagai fasilitas simulasi program. 2.2

DASAR TEORI 2.2.1

Compiler Warp

Proses kompilasi adalah proses pengecekan sistematika penulisan program, statement dan kebenaran penulisan sintak-sintak yang digunakan pada program. Langkah penggunaan Compiler WARP : 1. Awali dengan Start. Kemudian Program dan pilih Warp R4, seterusnya Galaxy. 2. Pada Window PC terlihat buka muncul jendela Galaxy dan sebuah jendela Project Compiler. 3. Buat jendela Project baru dengan meng-klik project pada jendela galaxy dan pilih new project. Lalu buat nama folder untuk project baru tersebut. 4. Mulailah program VHDL dengan mengklik bagian new pada jendela Compiler dan buatlah program dengan struktur program yang sudah ada.

Gambar 2-1. Window Galaxy Dan Project

26

Gambar 2-2. Window New Project

Gambar 2-3. Window VHDL Editor

 

Setelah selesai rancangan disimpan dengan Save dan filenya diberi nama yang secara otomatis berekstensi .VHD. Agar file dikenali project maka klik Files kemudian Add pada jendela Galaxy. Klik file yang dirancang kemudian dipindah dari kolom kiri ke kana n dan Ok.

27

Gambar 2-4. Window Directory VHDL  

Klik Set top pada project Compiler agar file yang akan dikompilasi dikenali Compiler dan akan ditampilkan pada pojok kiri bawah jendela project Compiler. Setting Device sesuai kebutuhan dan spesifikasi program yang dirancang dengan mengklik Device pada Syntetis option.

Gambar 2-5. Window Project VHDL

28

Gambar 2-6. Window Device VHDL 



Lakukan proses Compilasi dengan mengklik Smart pada kolom Compile. Jika Compilasi sukses maka akan keluar kata Compilation Successful pada bagian kiri bawah jendela Compiling VHDL yang keluar secara otomatis. Jika proses Compilasi sukses maka secara otomatis file rancangan sudah berekstensi .JED dan siap untuk dilakukan simulasi.

Gambar 2-7. Compiling VHDL

2.2.2

Simulator Nova

Proses simulasi dilakukan untuk membuktikan kebenaran logika program yang sudah dibuat pada program rancangan dengan memasukkan nilai inputan berdasarkan table kebenaran yang keluarannya dibandingkan dengan keluaran pada table kebenaran. Langkah simulasi dengan NOVA : Proses simulasi diawali dengan mengklik Tools pada jendela Galaxy dan pilih NOVA. Kemudian  ambil file rancangan yang sudah berekstensi .JED pada jendela Nova melalui File kemudian Open. Maka akan terlihat lajur-lajur sinyal masukan dan keluaran sesuai rancangan.

29

Gambar 2-8. Simulasi Nova 



2.3

Aturlah kondisi masukan dengan menggeser mouse pada lajur sinyal masukan hingga warnanya merah dan pilih Edit pada jendela NOVA. Kemudian tentukan apakah kondisi sinyal Clock, High atau Low. Proses simulasi kondisi keluaran dilakukan dengan mengklik lajur sinyal keluaran hingga merah. Kemudian klik Simulate kemudian Execute, maka dengan sendirinya akan keluar sinyal keluaran. Yang menjadi pertanyaan, apakah kondisi sinyal keluaran keluaran sesuai atau tidak dengan table kebenaran dari rancangan. Jika tidak, maka terjadi kesalahan pada bagian program yang sudah kita buat.

PERCOBAAN

Untuk mempraktekkan penggunaan compiler Warp dan simulator Nova di atas cobalah beberapa program berikut :

Program 1 :

Gambar 2-9. Gerbang Logika

Entity Combinational Is Port ( A, B, C : In BIT; D : Out BIT ); End Combinational; Architecture Contoh1 Of Combinational Is Begin D <= (A AND B) OR C; End Contoh1;

30

Program 2 :

Gambar 2-10. Rangkaian Kombinasi Logika

Library ieee; Use ieee.std_logic_1164.all; Entity Buzzer Is Port ( Door, Ignition, SBelt : In Std_Logic; Warning : Out Std_Logic ); End Buzzer; Architecture Lengkap Of Buzzer Is Begin Warning <= <= (NOT (NOT Door Door AND Ignition) OR (NOT SBelt AND Ignition); End Lengkap;

Program 3 : Library ieee; Use ieee.std_logic_1164.all; Entity OR_ent is Port ( x, y : In Std_Logic; F : Out Std_Logic); End OR_ent; Architecture behav1 of OR_ent Is Begin Process(x, y) Begin -- compare to truth table If ((x='0') OR (y='0')) Then F <= '0'; Else F <= '1'; End If; 31

End Process; End behav1; ------------------------------- atau -------------------------Architecture behav2 of OR_ent Is Begin F <= x OR y; End behav2; 2.4

TUGAS

1. Buatlah program yang terdiri dari gerbang-gerbang terimplementasi dalam suatu aplikasi elektronika !

32

logika

dasar

yang

2.4.1

Tugas Rangkaian 3 Kombinasi Logika Dasar

2.4.1.1 Gambar Rangkaian Logika

Gambar 2-11. Rangkaian Kombinasi 3 Logika Dasar

2.4.1.2 Listing Program Library ieee; use ieee.std_logic_1164.all; Entity buzzer is port (Door, ignition, sbelt:in std_logic; warning :out std_logic); end buzzer; Architecture lengkap of buzzer is begin Warning<=(NOT door AND ignition)Or(NOT sbelt AND ignition); End lengkap;

2.4.1.3 Tabel Kebenaran Tabel 2-1. Tabel Kebenaran Gerbang OR INPUT A B 0 0 0 1 1 0 1 1

OUTPUT Y 0 1 1 1

33

2.4.1.4 Simulasi NOVA

Gambar 2-12. Hasil Simulasi Nova 3 Logika Dasar

2.4.1.5 Report File | | | | | | | _________________ -| |-| |-| |-| CYPRESS |-| |-| |-| ||_______________| |____________ ___| | | | | | | |

Warp VHDL Synthesis Compiler: Version 4 IR x77 Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1997 Cypress Semiconductor Semiconducto r

====================================================================== Compiling: 2.3.1.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 2.3.1.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sat Nov 19 21:07:16 2011 Library Linking Library Linking

VHDL parser

'work' => directory 'lc22v10' 'C:\warp\lib\common\work\cypress.vif'. 'ieee' => directory 'C:\warp\lib\ieee\work' 'C:\warp\lib\ieee\work\stdlogic.vif'.

C:\warp\bin\vhdlfe.exe: C:\warp\bin\vh dlfe.exe:

No errors.

C:\warp\bin\tovif.exe C:\warp\bin\to vif.exe V4 IR x77: Sat Nov 19 21:07:17 2011

High-level synthesis

Linking 'C:\warp\lib\common\work\cypress.vif'.

34

Linking 'C:\warp\lib\ieee\work\stdlogic.vif'. C:\warp\bin\tovif.exe: C:\warp\bin\to vif.exe:

No errors.

C:\warp\bin\topld.exe C:\warp\bin\to pld.exe V4 IR x77: Sat Nov 19 21:07:17 2011

Synthesis and optimization

Linking 'C:\warp\lib\common\work\cypress.vif'. Linking 'C:\warp\lib\ieee\work\stdlogic.vif'. ---------------------------------------------------------Detecting unused logic. --------------------------------------------------------------------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------Created 4 PLD nodes. C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.

--------------------------------------------------------------------------PLD Optimizer Software: DSGNOPT.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN HEADER INFORMATION Input File(s): Device : Package : ReportFile :

(21:07:18)

2.3.1.pla C22V10 PALCE22V10-5JC PALCE22V10-5 JC 2.3.1.rpt

Program Controls: None.

35

Signal Requests: GROUP DT-OPT ALL Completed Successfully -----------------------------------------------------------------------PLD Optimizer Software: x77 OPTIMIZATION OPTIONS

DSGNOPT.EXE

01/MAR/97

[v4.00 ] 4 IR

(21:07:18)

Messages: Information: Optimizing logic using best output polarity for signals: warning

Summary: Error Count = 0

Warning Count = 0

Completed Successfully -----------------------------------------------------------------------PLD Optimizer Software: x77 LOGIC MINIMIZATION

MINOPT.EXE

19/JUL/96

[v3.22A] 4 IR

()

Messages: Summary: Error Count = 0

Warning Count = 0

Completed Successfully -----------------------------------------------------------------------PLD Optimizer Software: x77 OPTIMIZATION OPTIONS

DSGNOPT.EXE

01/MAR/97

[v4.00 ] 4 IR

(21:07:18)

Messages: Information: Optimizing Banked Preset/Reset requirements. Summary: Error Count = 0

Warning Count = 0

Completed Successfully ------------------------------------------------------------------------

36

PLD Compiler Software: x77 DESIGN EQUATIONS

PLA2JED.EXE

01/MAR/97

[v4.00 ] 4 IR

(21:07:19)

warning = ignition * /sbelt + /door * ignition Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(21:07:19)

Messages: None. Summary: Error Count = 0

Warning Count = 0

Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN SIGNAL PLACEMENT

(21:07:19)

Messages: Information: Checking for duplicate NODE logic. None. Device: C22V10 Package: PALCE22V10-5JC i g n u u i s n n d t b u u o i e V s s o o l N C e e r n t C C d d | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | |

37

unused_| 5 25|_unused unused_| 6 24|_unused unused_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_unused unused_|11 19|_unused | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u w u n n N C n a n u u D u r u s s s n s e e e i e d d d n d g


Warning Count = 0

Completed Successfully ------------------------------------------------------------------------PLD Compiler Software: x77 RESOURCE ALLOCATION

PLA2JED.EXE

01/MAR/97

[v4.00 ] 4 IR

(21:07:19)

Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 2 | 11 | | Clock/Inputs Clock/Inputs | 1 | 1 | | I/O Macrocells | 1 | 10 | ______________________________________ 4 / 22 = 18 Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | warning | 2 | 8 | | 15 | Unused | 0 | 10 | | 16 | Unused | 0 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 |

38

%

| 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | Unused | 0 | 12 | | 22 | Unused | 0 | 10 | | 23 | Unused | 0 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 2 / 121 = 1

%

Completed Successfully ------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 JEDEC ASSEMBLE

(21:07:19)

Messages: Information: Output file '2.3.1.jed' created. Summary: Error Count = 0

Warning Count = 0

Completed Successfully at 21:07:19

39

2.5

Analisa Hasil Percobaan

40

41

2.6

Kesimpulan Percobaan

42



: RANGKAIAN KOMBINASIONAL MULTIPLEXER DAN DEKODER

Nama Praktikan


NIM

: 08530107

Tanggal Pelaksanaan

: 15 Oktober 2011

Asisten Pembimbing

: Dwi Ari Cahyanto

Tanda Tangan

:

Instruktur

:

Tanda Tangan

:

Tanggal

:

Tanggal

:


:

Tanggal

:

43

3 BAB III RANGKAIAN KOMBINASIONAL, MULTIPLEXER DAN DEKODER 3.1

TUJUAN

Peserta praktikum dapat memahami model-model rangkaian kombinasional dan multiplexer yang dapat dirancang dengan bahasa VHDL dan memahami statementstatement yang digunakan. 3.2

DASAR TEORI 3.2.1

Rangkaian Combinational

Rangkaian Combinational adalah rangkaian logika yang terdiri dari kombinasi gerbang-gerbang logika sederhana seperti AND, OR, NAND, NOR, X-OR dan X-NOR. Contoh : Rangkaian kombinasional

Gambar 3-1. Rangkaian Kombinasi

Entity Combinational1 Is Port ( A, B, C, D : In BIT; OUTPUT : Out BIT ); End Combinational1; Architecture Contoh Of Combinational1 Is Begin OUTPUT <= (A AND B) OR (NOT (C XOR D); End Contoh;

44

3.2.2

Multiplexer

Gambar 3-2. Rangkaian Multiplexer

Contoh (2 Mux2) : Menggabungkan 2 Multiplexer 2 masukan

Entity Dbl_Mux2 Is Port ( A, B : In Bit_Vector (0 To 1); Sel : In Bit; OUTPUT : Out Bit_Vector (1 To 2 )); End Dbl_Mux2; Architecture Combinational2 Of C Is Begin Mux2_A : Process ( A, Sel ) Begin If Sel = „0‟ THEN OUTPUT (1) <= A (0); Else OUTPUT(1) <= A (1); End If; End Process Mux2_A; Mux2_B : Process ( B, Sel ) Begin If Sel = „0‟ THEN OUTPUT (2) <= B (0); Else OUTPUT(2) <= B (1); End If; End Process Mux2_B; End Combinational2;

45

3.2.3

Dekoder

Contoh (Dekoder 2 ke 4) :

Program 3 (Behavioral) : Library ieee; Use ieee.std_logic_1164.all; Entity DECODER is Port ( I : In std_logic_vector (1 downto 0); O: Out std_logic_vector (3 downto 0)); End DECODER; Architecture behv Of DECODER Is Begin -- process statement Process (I) Begin -- use case statement Case I Is When "00" => O <= "0001"; When "01" => O <= "0010"; When "10" => O <= "0100"; When "11" => O <= "1000"; When Others => O <= "XXXX"; End Case; End Process; End behv;

3.3

PERCOBAAN

Program 1 : Full Adder Library ieee ; Use ieee.std_logic_1164.all; Entity Full_Adder Is Port ( A0, A1, Ci : in Std_Ulogic; C0, S0 : Out Std_Ulogic); End Full_Adder; Architecture behv of Full_Adder is Begin S0 <= A0 XOR B0 XOR Ci; C0 <= (A0 AND B0) OR ((A0 XOR B0) AND Ci); End behv;

46

Program 1 : Encoder Library ieee ; Use ieee.std_logic_1164.all; Entity Full_Adder Is Port ( A0, A1, Ci : in Std_Ulogic; C0, S0 : Out Std_Ulogic); End Full_Adder; Architecture behv of Full_Adder is Begin S0 <= A0 XOR B0 XOR Ci; C0 <= (A0 AND B0) OR ((A0 XOR B0) AND Ci); End behv;

3.4

TUGAS 1. Buatlah program program untuk rangkaian rangkaian kombinasional yang terdiri terdiri dari minimal 3 jenis gerbang logika dasar yang diaplikasikan pada sebuah desain aplikasi elektronika ! 2. Buatlah program untuk Multiplexer 4 masukan ! 3. Buatlah program untuk Demultiplexer 4 keluaran ! 4. Buatlah program untuk Dekoder 3 ke 8 !

47

3.4.1

Tugas Multiplexer 4 Masukan 3.4.1.1 Gambar Rangkaian Logika

Gambar 3-3. Rangkaian Multiplexer 4 Masukan

3.4.1.2 Listing Program Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity multiplexer4_1 is port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; sel : in std_logic_vector(1 downto 0); bitout : out std_logic ); end multiplexer4_1; architecture behavioral of multiplexer4_1 is begin process(i0,i1,i2,i3,sel) begin case sel is when "00" => bitout <= i0; when "01" => bitout <= i1; when "10" => bitout <= i2; when others => bitout <= i3; end case; end process; end behavioral;

48

3.4.1.3 Tabel Kebenaran

Tabel 3-1. Tabel Kebenaran Multiplexer 4 Masukan


Gambar 3-4. Hasil Hasil Simulasi Nova Untuk Multiplexer 4 Masukan

49



====================================================================== Compiling: 3.1.1.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 3.1.1.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:05:42 2011 Library Linking Library Linking

VHDL parser



No errors.

C:\warp\bin\tovif.exe C:\warp\bin\to vif.exe V4 IR x77: Sun Nov 27 18:05:42 2011


Linking 'C:\warp\lib\common\work\cypress.vif'. Linking 'C:\warp\lib\ieee\work\stdlogic.vif'. C:\warp\bin\tovif.exe: C:\warp\bin\to vif.exe:

No errors.

C:\warp\bin\topld.exe C:\warp\bin\to pld.exe V4 IR x77: Sun Nov 27 18:05:42 2011


Linking 'C:\warp\lib\common\work\cypress.vif'. Linking 'C:\warp\lib\ieee\work\stdlogic.vif'. ---------------------------------------------------------Detecting unused logic. ----------------------------------------------------------

50

-----------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------Created 7 PLD nodes. C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:05:42)


Program Controls: None. Signal Requests: GROUP DT-OPT ALL Completed Successfully --------------------------------------------------------------------------PLD Optimizer Software: DSGNOPT.EXE 01/MAR/97 [v4.00 ] 4 IR x77 OPTIMIZATION OPTIONS

(18:05:42)

Messages: Information: Optimizing logic using best output polarity for signals: bitout

51


Warning Count = 0

Completed Successfully --------------------------------------------------------------------------PLD Optimizer Software: MINOPT.EXE 19/JUL/96 [v3.22A] 4 IR x77 LOGIC MINIMIZATION

()


Warning Count = 0

Completed Successfully --------------------------------------------------------------------------PLD Optimizer Software: DSGNOPT.EXE 01/MAR/97 [v4.00 ] 4 IR x77 OPTIMIZATION OPTIONS

(18:05:42)


Warning Count = 0

Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN EQUATIONS bitout = i0 + i2 + i1 + i3

* * * *

(18:05:42)

/sel_1 * /sel_0 sel_1 * /sel_0 /sel_1 * sel_0 sel_1 * sel_0

Completed Successfully

52

--------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(18:05:42)


Warning Count = 0


(18:05:42)

Messages: Information: Checking for duplicate NODE logic. None. Device: C22V10 Package: PALCE22V10-5JC u u s s n n e e u u l l V s s i _ _ N C e e 3 1 0 C C d d | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | | i2_| 5 25|_unused i1_| 6 24|_unused i0_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_unused unused_|11 19|_unused | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u b u n n N C n i n u u D u t u

53

s e d

s e d

s e d

o u t

s e d


Warning Count = 0

Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 RESOURCE ALLOCATION

(18:05:42)

Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 5 | 11 | | Clock/Inputs Clock/Inputs | 1 | 1 | | I/O Macrocells | 1 | 10 | ______________________________________ 7 / 22 = 31

%

Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | bitout | 4 | 8 | | 15 | Unused | 0 | 10 | | 16 | Unused | 0 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | Unused | 0 | 12 | | 22 | Unused | 0 | 10 | | 23 | Unused | 0 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 4 / 121 = 3

%

Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77

54

JEDEC ASSEMBLE

(18:05:42)


Warning Count = 0


55

3.4.2

Tugas Demultiplexer Keluaran 4 3.4.2.1 Gambar Rangkaian Logika

Gambar 3-5. Rangkaian Demultiplexer 4 Keluaran

3.4.2.2 Listing Program Library IEEE; USE IEEE.std_logic_1164.all; entity demux1_4 is port ( out0 : out std_logic; --output bit out1 : out std_logic; --output bit out2 : out std_logic; --output bit out3 : out std_logic; --output bit sel : in std_logic_vector(1 std_logic_vector(1 downto 0); bitin : in std_logic --input bit ); end demux1_4; architecture behavioral of demux1_4 is begin process(bitin,sel) begin case sel is when "00" => out0 <= bitin; out1 <='0'; out2 <='0'; out3 <='0'; when "01" => out1 <= bitin; out0 <='0'; out2 <='0'; out3 <='0';

56

when "10" => out2 <= bitin; out0 <='0'; out1 <='0'; out3 <='0'; when others => out3 <= bitin; out0 <='0'; out1 <='0';out2 <='0'; end case; end process; end behavioral;

3.4.2.3 Tabel Kebenaran Tabel 3-2. Tabel Kebenaran Demultiplexer 4 Keluaran


Gambar 3-6. Hasil Simulasi Nova Demultiplexer 4 Keluaran

57

3.4.2.5 Report File

| | | | | | | _________________ -| |-| |-| |-| CYPRESS |-| |-| |-| ||_______________| |____________ ___| | | | | | | |


====================================================================== Compiling: 3.1.2.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 3.1.2.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:09:40 2011 Library Linking Library Linking

VHDL parser



No errors.




No errors.




58

-----------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------Created 7 PLD nodes. C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:09:40)



(18:09:40)

Messages: Information: Selected logic optimization OFF for signals:

59

out3 out2 out1 out0


Warning Count = 0


()


Warning Count = 0


(18:09:40)


Warning Count = 0

Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN EQUATIONS

(18:09:40)

out0 = /sel_1 * /sel_0 * bitin out1 = /sel_1 * sel_0 * bitin out2 = sel_1 * /sel_0 * bitin

60

out3 = sel_1 * sel_0 * bitin Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(18:09:40)


Warning Count = 0


(18:09:40)

Messages: Information: Checking for duplicate NODE logic. None. Device: C22V10 Package: PALCE22V10-5JC s s b e e i o o l l t V u u _ _ i N C t t 1 0 n C C 2 0 | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | | unused_| 5 25|_unused unused_| 6 24|_unused unused_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_unused unused_|11 19|_unused | | | 12 13 14 15 16 17 18 |

61

________________________ | | | | | | | u u G N u o o n n N C n u u u u D u t t s s s 3 1 e e e d d d


Warning Count = 0


(18:09:40)


%

Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | out3 | 1 | 8 | | 15 | out1 | 1 | 10 | | 16 | Unused | 0 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | Unused | 0 | 12 | | 22 | out0 | 1 | 10 | | 23 | out2 | 1 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 4 / 121 = 3 Completed Successfully

62

%

--------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 JEDEC ASSEMBLE

(18:09:40)


Warning Count = 0


63

3.4.3

Tugas Rangkaian Decoder 3 Ke 8


Gambar 3-7. Rangkaian Logika Decoder 3 Ke 8

3.4.3.2 Listing Program -This is the AND gate Library Ieee; use ieee.std_logic_1164.all; entity andGate is port( A,B,C:IN std_logic; F : out std_logic); END andgate; Architecture Architecture func of andgate is begin F<=A AND B AND C; END func; --*=================================== -This is the NOT gate Library ieee; use ieee.std_logic_1164.all; entity notGate is port( inport : in std_logic; outport : out std_logic); end notgate; --

64

architecture architecture func of notgate is begin outport <= not inport; end func; --*=================*================== -Now we write the definition for the 3-to-8 decoder library ieee; use ieee.std_logic_1164.all; -entity decoder_3to8 is port(A0, A1, A2: in std_logic; D0, D1, D2, D3, D4, D5, D6, D7: OUT STD_logic); end decoder_3to8; -architecture func of decoder_3to8 is component andgate --import and gate entity port(A, B, C: in std_logic; F: out std_logic); end component; component notgate --import not gate entity port( inport : in std_logic; outport: out std_logic); end component; signal invA0, invA1, invA2 : std_logic; begin --notice that there are as many cocurrent statements --here as there are gates in the physical circuit shown --on teahlab.com. teahlab.com. GI1: notgate port map(A0, InvA0); GI2: notgate port map(A1, InvA1); GI3: notgate port map(A2, invA2); --the outputs GA1: andgate port map(invA0, invA1, invA2, D0); GA2: andgate port map( A0, invA1, invA2, D1); GA3: andgate port map(invA0, A1, invA2, D2); GA4: andgate port map( A0, A1, invA2, D3); GA5: andgate port map(invA0, invA1, A2, D4); GA6: andgate port map( A0, invA1, A2, D5); GA7: andgate port map(invA0, A1, A2, D6); GA8: andgate port map( A0, A1, A2, D7); end func; -----------------------------------------------END -----------------------------------------------END

65

3.4.3.3 Tabel Kebenaran Tabel 3-3. Tabel Kebenaran Decoder 3 Ke 8


Gambar 3-8. Hasil Simulasi Nova Decoder 3 Ke 8

66



====================================================================== Compiling: 3.1.3.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 3.1.3.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:13:47 2011 Library Linking Library Linking Library Library

VHDL parser

'work' => directory 'lc22v10' 'C:\warp\lib\common\work\cypress.vif'. 'ieee' => directory 'C:\warp\lib\ieee\work' 'C:\warp\lib\ieee\work\stdlogic.vif'. 'ieee' => directory 'C:\warp\lib\ieee\work' 'ieee' => directory 'C:\warp\lib\ieee\work'


No errors.




No errors.



Linking 'C:\warp\lib\common\work\cypress.vif'. Linking 'C:\warp\lib\ieee\work\stdlogic.vif'. Linking 'C:\warp\lib\lc22v10\stdlogic\c22v10.vif'. ---------------------------------------------------------Detecting unused logic.

67

--------------------------------------------------------------------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 3 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------Created 14 PLD nodes. C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:13:48)



(18:13:48)

Messages: Information: Selected logic optimization OFF for signals: d7 d6 d5 d4 d3 d2 d1 d0

68


Warning Count = 0


()


Warning Count = 0


(18:13:48)


Warning Count = 0


(18:13:48)

d0 = /a0 * /a1 * /a2 d1 = a0 * /a1 * /a2 d2 = /a0 * a1 * /a2

69

d3 = a0 * a1 * /a2 d4 = /a0 * /a1 * a2 d5 = a0 * /a1 * a2 d6 = /a0 * a1 * a2 d7 = a0 * a1 * a2 Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(18:13:48)


Warning Count = 0


(18:13:48)

Messages: Information: Checking for duplicate NODE logic. None. Device: C22V10 Package: PALCE22V10-5JC V a a a N C d d 0 1 2 C C 6 4 | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | |

70

unused_| 5 25|_d2 unused_| 6 24|_d0 unused_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_d1 unused_|11 19|_d3 | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u d d n n N C n 7 5 u u D u s s s e e e d d d


Warning Count = 0


(18:13:48)

Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 2 | 11 | | Clock/Inputs Clock/Inputs | 1 | 1 | | I/O Macrocells | 8 | 10 | ______________________________________ 11 / 22 = 50 Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | d7 | 1 | 8 | | 15 | d5 | 1 | 10 | | 16 | d3 | 1 | 12 | | 17 | d1 | 1 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | d0 | 1 | 14 |

71

%

| 21 | d2 | 1 | 12 | | 22 | d4 | 1 | 10 | | 23 | d6 | 1 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 8 / 121 = 6

%

Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 JEDEC ASSEMBLE

(18:13:48)


Warning Count = 0


72

3.5

Analisa Percobaan

73

74

3.6


75



: RANGKAIAN SEQUENCIAL

Nama Praktikan


NIM

: 08530107

Tanggal Pelaksanaan

: 15 Oktober 2011

Asisten Pembimbing

: Dwi Ari Cahyanto

Tanda Tangan

:

Instruktur

:

Tanda Tangan

:

Tanggal

:

Tanggal

:


:

Tanggal

:

76

4 PERCOBAAN IV RANGKAIAN SEQUENSIAL 4.1

TUJUAN

Peserta praktikum dapat memahami model-model rangkaian sequensial yang dapat dirancang dengan bahasa VHDL dan memahami statement-statement yang digunakan. 4.2

DASAR TEORI

Rangkaian sequensial merupakan rangkaian digital dengan jalur feedback yang operasinya operasinya merupakan fungsi dari 2 keadaan yaitu kondisi sebelum dan input saat i tu, yang terdiri dari elemen Enable, Clock, Reset, Preset, Sinkron dan Asinkron. Rangkaian sequensial pada dasarnya berupa terdiri S-R Flip-flop, D Flip-flop, J-K Flip-flop maupun T Flip-flop yang nantinya akan digunakan untuk merangkai Counter Contoh 1 : Menggunakan Enable

Gambar 4-1. Rangkaian Sequencial dengan Enable

Library ieee ; Use ieee.std_logic_1164.all; Entity D_latch is Port ( data_in: in std_logic; enable: in std_logic; data_out: out std_logic); End D_latch; Architecture behv of D_latch is Begin -- compare this to D flipflop Process(data_in, enable) Begin If (enable='1') then -- no clock signal here data_out <= data_in; End If; End Process; End behv;

77

Contoh 2 : Menggunakan Clock

Gambar 4-2. Rangkaian Sequensial dengan Clock

Library ieee ; Use ieee.std_logic_1164.all; Use work.all; Entity dff is Port ( data_in: in std_logic; clock: in std_logic; data_out: out std_logic); End dff; Architecture behv of dff is Begin Process(data_in, clock) Begin -- clock rising edge If (clock='1' and clock'event) then data_out <= data_in; End if; End Process; End behv; Contoh 3 : Menggunakan Reset dan Rising_Edge Clock

Gambar 4-3. Rangkaian Sequensial dengan Reset dan Rising Edge

Library ieee; Use ieee.std_logic_1164.all; Entity JK_FF is Port ( clock: in std_logic; J, K: in std_logic; reset: in std_logic; Q, Qbar: out std_logic); End JK_FF; 78

Architecture behv of JK_FF is -- define the useful signals here signal state: std_logic; signal input: std_logic_vector(1 downto 0); Begin -- combine inputs into vector input <= J & K; P: Process(clock, reset) is Begin If (reset='1') then state <= '0'; Elsif (rising_edge(clock)) then -- compare to the truth table Case (input) is When "11" => state <= not state; When "10" => state <= '1'; When "01" => state <= '0'; When others => null; End Case; End If; End Process; -- concurrent statements Q <= state; Qbar <= not state; End behv;

4.3

PERCOBAAN 4.3.1

Program 1 :

Library ieee; Use ieee.Std_Logic_1164.all; Entity Sequensial1 Is Port ( CLK, D : In Std_Logic; Q : Out Std_Logic ); End Sequensial1; Architecture Contoh1 Of Sequential1 Is Begin Process ( D, CLK ) 79

Begin If CLK = „1‟ AND CLK ‟Event THEN Q <= D; End If; End Process; End Contoh1;

4.3.2

Program 2 :

Library ieee; Use ieee.Std_Logic_1164.all; Entity Sequensial2 Is Port ( CLK, D1, D2 : In Std_Logic; Q, Q_Bar : Out Std_Logic_Vector (1 To 2) ); End Sequensial2; Architecture Contoh Of Sequential2 Is Begin FF_A : Process ( D1, CLK ) Begin If CLK = „1‟ AND CLK ‟Event THEN Q (1) <= D1; Q_Bar (1) <= NOT D1; End If; End Process FF_A; FF_B : Process ( D2, CLK ) Begin If CLK = „0‟ AND CLK ‟Event THEN Q (2) <= D2; Q_Bar (2) <= NOT D2; End If; End Process FF_B; End Contoh; 4.3.3

Program 3 :

Library ieee ; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity counter is generic(n: natural :=2); Port ( clock: In std_logic; clear: In std_logic; count: In std_logic; Q: Out std_logic_vector (n-1 downto 0)); 80

End counter; Architecture behv of counter is signal Pre_Q: std_logic_vector(n-1 downto 0); Begin -- behavior describe the counter Process(clock, count, clear) Begin If clear = '1' Then Pre_Q <= Pre_Q - Pre_Q; Elsif (clock='1' and clock'event) then If count = '1' Then Pre_Q <= Pre_Q + 1; End If; End If; End Process; -- concurrent assignment statement Q <= Pre_Q; End behv; 4.4

TUGAS 1. Buatlah program berupa rangkaian sequensial yang dikombinasi dengan gerbang logika dasar !

81

4.4.1

Tugas Membuat Rangkaian Sequensial 4.4.1.1 Gambar Rangkaian Logika

Gambar 4-4. Rangkaian Sekuensial

4.4.1.2 Listing Program Library ieee; Use ieee.std_logic_1164.all; Entity D_LATCH is port (Data_in:In std_Logic; enable: in std_logic; data_out: out std_logic); End D_LATCH; architecture BEHV of D_latch is begin --compare this to D FLIPFLOP Process(data_in,enable) begin if (enable='1') then --no clock signal here data_out<=data_in; End if; End process; end behv;

82

4.4.1.3 Tabel Kebenaran

Tabel 4-1. Tabel Kebenaran Sekuensial


Gambar 4-5. Hasil Simulasi Nova Rangkaian Sekuensial



====================================================================== Compiling: 4.1.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 4.1.vhd

83

====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:17:04 2011 Library Linking Library Linking

VHDL parser



No errors.




No errors.



Linking 'C:\warp\lib\common\work\cypress.vif'. Linking 'C:\warp\lib\ieee\work\stdlogic.vif'. ---------------------------------------------------------Detecting unused logic. --------------------------------------------------------------------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------Created 3 PLD nodes.

84

C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:17:04)

4.1.pla C22V10 PALCE22V10-5JC PALCE22V10-5 JC 4.1.rpt


(18:17:04)

Messages: Information: Optimizing logic using best output polarity for signals: data_out


Warning Count = 0


()


Warning Count = 0


85

--------------------------------------------------------------------------PLD Optimizer Software: DSGNOPT.EXE 01/MAR/97 [v4.00 ] 4 IR x77 OPTIMIZATION OPTIONS

(18:17:05)


Warning Count = 0

Completed Successfully -----------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN EQUATIONS

(18:17:05)

data_out = /enable * data_out + data_in * enable Completed Successfully -----------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(18:17:05)


Warning Count = 0

Completed Successfully -----------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN SIGNAL PLACEMENT

(18:17:05)

Messages: Information: Checking for duplicate NODE logic. None. Device:

C22V10

86

Package: PALCE22V10-5JC d u a e u u n t n n n u a a u u s _ b V s s e i l N C e e d n e C C d d | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | | unused_| 5 25|_unused unused_| 6 24|_unused unused_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_unused unused_|11 19|_unused | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u d u n n N C n a n u u D u t u s s s a s e e e _ e d d d o d u t


Warning Count = 0


(18:17:05)

Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 1 | 11 | | Clock/Inputs Clock/Inputs | 1 | 1 | | I/O Macrocells | 1 | 10 |

87

______________________________________ 3 / 22 = 13

%

Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | data_out | 2 | 8 | | 15 | Unused | 0 | 10 | | 16 | Unused | 0 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | Unused | 0 | 12 | | 22 | Unused | 0 | 10 | | 23 | Unused | 0 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 2 / 121 = 1

%

Completed Successfully -----------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 JEDEC ASSEMBLE

(18:17:05)

Messages: Information: Output file '4.1.jed' created. Summary: Error Count = 0

Warning Count = 0


88

4.5

Analisa Percobaan

89

90

91

92



: MODEL DEKLARASI ARCHITECTURE BODY

Nama Praktikan


NIM

: 08530107

Tanggal Pelaksanaan

: 15 Oktober 2011

Asisten Pembimbing

: Dwi Ari Cahyanto

Tanda Tangan

:

Instruktur

:

Tanda Tangan

:

Tanggal

:

Tanggal

:


:

Tanggal

:

93

5 PERCOBAAN V MODEL DEKLARASI ARCHITECTURE BODY 5.1

TUJUAN

Peserta praktikum dapat memahami model-model pendeklarasian Architecture Body yang digunakan pada VHDL. 5.2

DASAR TEORI 5.2.1

DESKRIPSI STRUKTURAL

Deskripsi model struktural merupakan model dari gerbang-gerbang spesifik yang terinterkoneksi dalam sebuah struktur. Contoh (Buzzer) :

Architecture structural Of Buzzer Is -- Declarations Component AND2 Port (In1, In2 : In Std_Logic; Out1 : Out Std_Logic); End Component ; Component OR2 Port (In1, In2 : In Std_Logic; Out1 : Out Std_Logic); End Component ; Component NOT1 Port (In1 : In Std_Logic; Out1 : Out Std_Logic); End Component ; -- Declaration of signals used to interconnect gates Signal Door_NOT, SBelt_NOT, B1, B2 : Std_Logic; Begin -- Component instantiations statements U0 : NOT1 Port Map (Door, Door_NOT); U1 : NOT1 Port Map (SBelt , SBelt_NOT); U2 : AND2 Port Map (Ignition, Door_NOT, B1); U3 : AND2 Port Map (Ignition, SBelt_NOT, B2); U4 : OR2 Port Map (B1, B2, Warning); End structural;

94

5.2.2

DESKRIPSI BEHAVIORAL

Model deskripsi behavioral adalah deskripsi Architecture yang menjelaskan tingkah laku fungsional rangkaian terhadap terhadap berbagai berbagai kondisi sinyal masukan system. Ciri dari model ini adalah pada penggunaan statement Process. Contoh 1 (Rangkaian Multiplexer 2 inputan) :

Entity Behavioral1 Is Port ( D0, D1, Sel : In Bit; Output : Out Bit ); End Behavioral1; Architecture Mux_2 Of Behavioral1 Is Begin Process ( D0, D1, Sel ) Begin If Sel = „0‟ THEN Output <= D1; Else Output <= D0 ; End If; End Process ; End Mux_2; Contoh 2 (Rangkaian D_FF Asynkronous Clear) :

Entity Behavioral2 Is Port ( CLK, D, CLEAR : In Std_Logic; Q : Out Std_Logic ); End Behavioral2; Architecture D_FF_Clear Of Behavioral2 Is Begin D_FF : Process ( CLK, CLK , CLEAR ) Begin If (CLEAR = „1‟ ) THEN Q <= „0‟ ; Elseif Q <= D ; End If; End Process ; End D_FF_Clear;

95

5.2.3

DESKRIPSI DATA FLOW

Model deskripsi Architecture ini merupakan model dimana fungsi dari rangkaian dijelaskan dengan mendefenisikan aliran data dari suatu input, register ke register lain atau output. Contoh 1 (By conditional signal assignments) :

Entity Mux_4_1 Is Port ( A, B, C, D : In Std_Logic; Sel : In Std_Logic_Vector (1 Downto 0); Z : Out Std_Logic ); End Mux_4_1; Architecture Data_Flow1 Of M ux_4_1 Is Begin Z <= A When Sel = “00” Else B When Sel = “01” Else C When Sel Sel = “10” Else D; End Data_Flow1; Contoh 2 (By selected signal assignments) :

Entity Mux_4_1 Is Port ( A, B, C, D : In Std_Logic; Sel : In Std_Logic_Vector (1 Downto 0); Z : Out Std_Logic ); End Mux_4_1; Architecture Data_Flow2 Of M ux_4_1 Is Begin With Sel Select Z <= A When “00” ; B When “01” ; C When “10” ; D; End Data_Flow2; 5.3

PERCOBAAN 5.3.1

Program 1 (Structural) :

Library ieee; Use ieee.std_logic_1164.all; Use work.all; Entity comb_ckt is Port ( Input1: In std_logic; Input2: In std_logic; Input3: In std_logic; Output: Out std_logic); End comb_ckt; 96

-- top level circuit

Architecture struct of comb_ckt is component AND_GATE is -- as entity of AND_GATE Port ( A: In std_logic; B: In std_logic; F1: Out std_logic ); End component; component OR_GATE is -- as entity of OR_GATE Port ( X: In In std_logic; Y: In std_logic; F2: Out std_logic); End component; signal wire: std_logic; -- signal just like wire Begin -- use sign "=>" to clarify the pin mapping Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire); Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output); End struct; 5.3.2

Program 2 (Behavioral) :

Library ieee; Use ieee.std_logic_1164.all; Entity Mux is Port ( I3, I2, I1, I0 : In std_logic_vector(2 downto 0); S : In std_logic_vector(1 downto 0); O : Out std_logic_vector(2 downto 0)); End Mux; Architecture behv1 of Mux is Begin Process(I3,I2,I1,I0,S) Begin -- use case statement Case S is When "00" => O <= I0; When "01" => O <= I1; When "10" => O <= I2; When "11" => O <= I3; When others => O <= "ZZZ"; End Case; End Process; End behv1;

97

5.3.3

Program 3 (Data Flow) :

Library ieee; Use ieee.std_logic_1164.all; Entity DECODER is Port ( I : In std_logic_vector (1 downto 0); O: Out std_logic_vector (3 downto 0)); End DECODER; Architecture Data_Flow Of DECODER Is Begin -- use When..Else statement O <= "0001" When I = "00" Else "0010" When I = "01" Else "0100" When I = "10" Else "1000" When I = "11" Else "XXXX"; End Data_Flow; 5.4

TUGAS

Buatlah program untuk Up/Down Counter, Register, Demultiplexer dan Encoder dengan deskripsi Arsitektur Arsitektur yang anda sukai !

98

5.4.1

Tugas Membuat Rangkaian Up / Down Counter


Gambar 5-1. Rangkaian Up / Down Counter

5.4.1.2 Listing Program

library ieee; use ieee.std_logic_1164.all; entity counter is port(a,b: in bit_vector(3 downto 0); q : out std_logic_vector(3 std_logic_ve ctor(3 downto 0)); end; architecture rtl of counter is begin q<=to_stdlogicvector(a and b); end;

5.4.1.3 Tabel Kebenaran Tabel 5-1. Tabel Kebenaran Up / Down Counter

99


Gambar 5-2. Hasil Simulasi Nova Untuk Up/Down Counter

5.4.1.5 Report file | | | | | | | _________________ -| |-| |-| |-| CYPRESS |-| |-| |-| ||_______________| |____________ ___| | | | | | | |


====================================================================== Compiling: 5.2.vhd

100

Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 5.2.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:22:11 2011 Library Linking Library Linking

VHDL parser



No errors.




No errors.




-----------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10.

101

---------------------------------------------------------Created 12 PLD nodes. C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:22:12)



(18:22:12)

Messages: Information: Selected logic optimization OFF for signals: q_0 q_1 q_2 q_3


Warning Count = 0


()


Warning Count = 0

102


(18:22:12)


Warning Count = 0


(18:22:12)

q_3 = a_3 * b_3 q_2 = a_2 * b_2 q_1 = a_1 * b_1 q_0 = a_0 * b_0 Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(18:22:12)


Warning Count = 0

103


(18:22:12)

Messages: Information: Checking for duplicate NODE logic. None.

Device: C22V10 Package: PALCE22V10-5JC b a b V q q _ _ _ N C _ _ 1 0 0 C C 1 3 | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | | a_1_| 5 25|_unused b_2_| 6 24|_unused a_2_| 7 23|_unused NC_| 8 22|_NC b_3_| 9 21|_unused a_3_|10 20|_unused unused_|11 19|_unused | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u q q n n N C n _ _ u u D u 0 2 s s s e e e d d d


Warning Count = 0

Completed Successfully ---------------------------------------------------------------------------

104

PLD Compiler Software: x77 RESOURCE ALLOCATION

PLA2JED.EXE

01/MAR/97

[v4.00 ] 4 IR

(18:22:12)


%

Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | q_0 | 1 | 8 | | 15 | q_2 | 1 | 10 | | 16 | Unused | 0 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | Unused | 0 | 12 | | 22 | q_3 | 1 | 10 | | 23 | q_1 | 1 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 4 / 121 = 3

%


(18:22:12)


Warning Count = 0


105

5.4.2

Tugas Rangkaian Up / Down Register 5.4.2.1 Gambar Rangkaian Logika

Gambar 5-3. Rangkaian Up / Down Register

5.4.2.2 Listing Program library ieee; use ieee.std_logic_1164.all; entity my_reg is port( a,b: in std_logic; io: inout std_logic; q: out std_logic); end; architecture rtl of my_reg is begin q<=a and io; io<='1' when a='1' and b='0' else 'Z'; end;

106

5.4.2.3 Tabel Kebenaran Tabel 5-2. Tabel Kebenaran Rangkaian Up / Down Register


Gambar 5-4. Hasil Simulasi Nova Untuk Up / Down Register

5.4.2.5 Report file | | | | | | | _________________ -| |-| |-| |-| CYPRESS |-| |-| |-| ||_______________| |____________ ___| | | | | | | |


107

====================================================================== Compiling: 5.4.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 5.4.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:26:40 2011 Library Linking Library Linking

VHDL parser



No errors.




No errors.



Linking 'C:\warp\lib\common\work\cypress.vif'. Linking 'C:\warp\lib\ieee\work\stdlogic.vif'. ---------------------------------------------------------Detecting unused logic. --------------------------------------------------------------------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10.

108

---------------------------------------------------------Created 7 PLD nodes. C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:26:41)



(18:26:41)

Messages: Information: Process virtual 'io_FB' ... expanded. Information: Process virtual 'ioE' ... expanded. Information: Selected logic optimization OFF for signals: q io io.OE


Warning Count = 0


()

Messages:

109


Warning Count = 0


(18:26:41)


Warning Count = 0

Completed Successfully PLD Compiler Software: x77 DESIGN EQUATIONS

PLA2JED.EXE

01/MAR/97

[v4.00 ] 4 IR

(18:26:41)

q = a * io io = VCC io.OE = a * /b Completed Successfully ------------------------------------------------------------------------PLD Compiler Software: x77 DESIGN RULE CHECK

PLA2JED.EXE

01/MAR/97

(18:26:41)


Warning Count = 0

110

[v4.00 ] 4 IR

Completed Successfully -------------------------------------------------------------------------

PLD Compiler Software: x77 DESIGN SIGNAL PLACEMENT

PLA2JED.EXE

01/MAR/97

(18:26:41)

Messages: Information: Checking for duplicate NODE logic. None. Device: C22V10 Package: PALCE22V10-5JC u u n n u u s V s e N C i e d a b C C o d | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | | unused_| 5 25|_unused unused_| 6 24|_unused unused_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_unused unused_|11 19|_unused | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u q u n n N C n n u u D u u s s s s e e e e d d d d


Warning Count = 0


111

[v4.00 ] 4 IR

--------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 RESOURCE ALLOCATION

(18:26:41)


%

Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | q | 1 | 8 | | 15 | Unused | 0 | 10 | | 16 | Unused | 0 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | Unused | 0 | 12 | | 22 | Unused | 0 | 10 | | 23 | io | 1 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 2 / 121 = 1

%


(18:26:41)


Warning Count = 0


112

5.4.3

Tugas Rangkaian Up / Down Demultiplexer 5.4.3.1 Gambar Rangkaian Logika

Gambar 5-5. Rangkaian Logika Up / Down Demultiplexer

5.4.3.2 Listing Program Library ieee; use ieee.std_logic_1164.all; entity demux6 is port( A : in std_logic; sel : in std_logic_vector(2 std_logic_vecto r(2 downto 0); q,r,s,u,v,w: out std_logic); end; architecture rtl of demux6 is begin process(A,SEL) BEGIN CASE SEL Is when "001" =>q<=A; when "010" =>r<=A; when "011" =>s<=A; when "101" =>u<=A;

113

when "110" =>v<=A; when others =>w<=A; END CASE; END PROCESS; END;

5.4.3.3 Tabel Kebenaran Tabel 5-3. Tabel Kebenaran Rangkaian Up / Down Demultiplexer


Gambar 5-6. Hasil Simulasi Nova Rangkaian Up / Down Demultiplexer

114


Warp VHDL Synthesis Compiler: Version 4 IR x77 Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1997 Cypress Semiconductor

====================================================================== Compiling: 5.1.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 5.1.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:19:49 2011 Library Linking Library Linking

VHDL parser



No errors.




No errors.



Linking 'C:\warp\lib\common\work\cypress.vif'. Linking 'C:\warp\lib\ieee\work\stdlogic.vif'.

115

---------------------------------------------------------Detecting unused logic. --------------------------------------------------------------------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------Created 10 PLD nodes. C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:19:49)



(18:19:49)

Messages: Information: Optimizing logic using best output polarity for signals:

116

w v u s r q


Warning Count = 0


()


Warning Count = 0


(18:19:50)


Warning Count = 0


(18:19:50)

s = a * /sel_2 * sel_1 * sel_0 + /sel_0 * s + /sel_1 * s + sel_2 * s r = a * /sel_2 * sel_1 * /sel_0

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+ sel_0 * r + /sel_1 * r + sel_2 * r q = a * /sel_2 * /sel_1 * sel_0 + /sel_0 * q + sel_1 * q + sel_2 * q w = + + + +

a * sel_2 * sel_1 * sel_0 /sel_2 * sel_0 * w a * /sel_1 * /sel_0 sel_1 * /sel_0 * w /sel_1 * sel_0 * w

v = a * sel_2 * sel_1 * /sel_0 + sel_0 * v + /sel_1 * v + /sel_2 * v u = a * sel_2 * /sel_1 * sel_0 + /sel_0 * u + sel_1 * u + /sel_2 * u Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(18:19:50)


Warning Count = 0


(18:19:50)

118

Messages: Information: Checking for duplicate NODE logic. None. Device: C22V10 Package: PALCE22V10-5JC s s s e e e l l l V _ _ _ N C 2 1 0 C C v s | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | | a_| 5 25|_q unused_| 6 24|_unused unused_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_unused unused_|11 19|_r | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u w u n n N C n u u D u s s s e e e d d d


Warning Count = 0


(18:19:50)

Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 3 | 11 | | Clock/Inputs Clock/Inputs | 1 | 1 |

119

| I/O Macrocells | 6 | 10 | ______________________________________ 10 / 22 = 45

%

Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | w | 5 | 8 | | 15 | u | 4 | 10 | | 16 | r | 4 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | q | 4 | 12 | | 22 | s | 4 | 10 | | 23 | v | 4 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 25 / 121 = 20

%


(18:19:50)


Warning Count = 0


120

5.4.4

Tugas Rangkaian Decoder 5.4.4.1 Gambar Rangkaian Logika

Gambar 5-7. Rangkaian Up / Down Encoder

5.4.4.2 Listing Program Entity case_encoder is port(a: in integer range 0 to 30; q: out integer range 0 to 6); end; architecture rtl of case_encoder is begin p1:process(a) begin case a is when 0 => q<=3; when 1 to 17 => q<=2; when 23 downto 18 => q<=6; when others => q<=0; end case; end process; end;

121

5.4.4.3 Tabel Kebenaran Tabel 5-4. Tabel Kebenaran Rangkaian Up / Down Encoder


Gambar 5-8. Hasil Simulasi Nova Rangkaian Up / Down Encoder



122

====================================================================== Compiling: 5.3.vhd Options: -q -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V10-5JC -pPALCE22V10- 5JC 5.3.vhd ====================================================================== C:\warp\bin\vhdlfe.exe C:\warp\bin\vh dlfe.exe V4 IR x77: Sun Nov 27 18:24:44 2011

VHDL parser

Library 'work' => directory 'lc22v10' Linking 'C:\warp\lib\common\work\cypress.vif'. C:\warp\bin\vhdlfe.exe: C:\warp\bin\vh dlfe.exe:

No errors.



Linking 'C:\warp\lib\common\work\cypress.vif'. C:\warp\bin\tovif.exe: C:\warp\bin\to vif.exe:

No errors.



Linking 'C:\warp\lib\common\work\cypress.vif'. ---------------------------------------------------------Detecting unused logic. ----------------------------------------------------------

-----------------------------------------------------Alias Detection ----------------------------------------------------------------------------------------------------------Aliased 0 equations, 0 wires. --------------------------------------------------------------------------------------------------------------Circuit simplification ------------------------------------------------------------------------------------------------------------------Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------Created 8 PLD nodes.

123

C:\warp\bin\topld.exe: C:\warp\bin\to pld.exe:

No errors.


(18:24:45)



(18:24:45)

Messages: Information: Optimizing logic using best output polarity for signals: q_IBV_2 q_IBV_1 Information: Selected logic optimization OFF for signals: q_IBV_0


Warning Count = 0


()

Messages: Summary:

124

Error Count = 0

Warning Count = 0


(18:24:45)


Warning Count = 0


(18:24:45)

q_IBV_0 = /a_IBV_1 * /a_IBV_2 * /a_IBV_3 * /a_IBV_4 * /a_IBV_0 /q_IBV_1 = a_IBV_3 * a_IBV_4 q_IBV_2 = a_IBV_2 * /a_IBV_3 * a_IBV_4 + a_IBV_1 * /a_IBV_3 * a_IBV_4 Completed Successfully --------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 01/MAR/97 [v4.00 ] 4 IR x77 DESIGN RULE CHECK

(18:24:45)


Warning Count = 0


125

PLD Compiler Software: x77 DESIGN SIGNAL PLACEMENT

PLA2JED.EXE

01/MAR/97

[v4.00 ] 4 IR

(18:24:45)

Messages: Information: Checking for duplicate NODE logic. None. Device: C22V10 Package: PALCE22V10-5JC a a a q _ _ _ _ u I I I I n B B B B u V V V V V s _ _ _ N C _ e 3 4 0 C C 1 d | | | | | | | ________________________ | 4 3 2 1 28 27 26 | | | a_IBV_2_| 5 25|_unused a_IBV_1_| 6 24|_unused unused_| 7 23|_unused NC_| 8 22|_NC unused_| 9 21|_unused unused_|10 20|_unused unused_|11 19|_unused | | | 12 13 14 15 16 17 18 | ________________________ | | | | | | | u u G N u q q n n N C n _ _ u u D u I I s s s B B e e e V V d d d _ _ 2 0


Warning Count = 0

Completed Successfully ---------------------------------------------------------------------------

126

PLD Compiler Software: x77 RESOURCE ALLOCATION

PLA2JED.EXE

01/MAR/97

[v4.00 ] 4 IR

(18:24:45)


%

Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | q_IBV_2 | 2 | 8 | | 15 | q_IBV_0 | 1 | 10 | | 16 | Unused | 0 | 12 | | 17 | Unused | 0 | 14 | | 18 | Unused | 0 | 16 | | 19 | Unused | 0 | 16 | | 20 | Unused | 0 | 14 | | 21 | Unused | 0 | 12 | | 22 | Unused | 0 | 10 | | 23 | q_IBV_1 | 1 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 4 / 121 = 3

%


(18:24:45)


Warning Count = 0


127

5.5

Analisa Hasil Percobaan 5.5.1

Analisa Register

128

129

5.5.2

Analisa Counter

130

5.5.3

Analisa Encoder

131

5.6


132

6 PERCOBAAN VI FINITE STATE MACHINE (FSM) 6.1

Tujuan

Memahami cara kerja dan bentuk FSM sebagai metode pembantu perencangan dan pembentukan program VHDL 6.2

Simulasi FSM dengan menggunakan STATECAD

Finite Stete Machine merupakan suatu metode pembantu dalam perencangan VHDL. Ciri utama dari metode ini adalah terbagi atas statestate, dimana satu dengan state yang lain memiliki hubungan yang tidak dapat dipisahkan. Dalam perancangan menggunakan software WARP dibuat dengan menuliskan program dan disimulasikan dengan menggunakan NOVA. Dengan perkembangn teknologi, kita dapat dengan mudah membuat suatu FSM dengan hanya menggambarkan state diagramnya (seperti blok diagram). Kemudian disimulasikan dan dapat dihasilkan listing program dengan format *.vhd. adapun aplikasinya sebagai contoh : State diagram Simulasi Traffic Light :

Gambar 6-1. State Diagram Simulasi Traffic Light

133

Dari state ini kemudian dicompile dan disimulasikan dengan utility yang ada. Selain itu dapat juga dihasilkan listing dalam format *.vhd yang merupakan format standart dalam pemrograman VHDL, untuk selanjutnya file yang dihasilkan dapat decompile menggunakancompiler WARP dan disimulasikan di NOVA. Berikut ini adalah listing yang dihasilkan : ---------

This code is to be used for evaluation purposes only C:\SC501E\AMD1.vhd VHDL code created created by Visual Software Solution's StateCAD 5.01 Fri Dec 19 10:54:52 2003 2003 This VHDL code (for use with Synopsys) was was generated using: enumerated state assignment with structured code format. Minimization is enabled, implied else is enabled, and outputs outputs are speed optimized. optimized.

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY synopsys; USE synopsys.attributes.all; ENTITY SHELL_AMD1 IS PORT (A00,A01,A1,A02,A2,A03,A3,B,B0,B1,B2,B3,RESET: IN std_logic; VAR00,VAR01,VAR02,VAR03 : OUT std_logic); SIGNAL BP_VAR00,BP_VAR01,BP_VAR02,BP_VAR03: std_logic; END; ARCHITECTURE BEHAVIOR OF SHELL_AMD1 IS SIGNAL BP_VAR0 : std_logic_vector (3 DOWNTO 0); SIGNAL VAR0 : std_logic_vector (3 DOWNTO 0); BEGIN PROCESS (A00,A01,A1,A02,A03,BP_VAR00,BP_VAR01,BP_VAR02,BP_VAR03,BP_VAR0) BEGIN BP_VAR0 <= ( (( std_logic_vector'(A03, A02, A01, A00)) AND ( std_logic_vector'( A1, A1, A1, A1)) ) OR (( std_logic_vector'(BP_VAR03, BP_VAR02, BP_VAR01, BP_VAR00)) AND ( std_logic_vector'( NOT A1, NOT A1, NOT A1, NOT A1)) )); BP_VAR00 <= BP_VAR0(0); BP_VAR01 <= BP_VAR0(1); 134

BP_VAR02 <= BP_VAR0(2); BP_VAR03 <= BP_VAR0(3); END PROCESS; PROCESS (BP_VAR00,BP_VAR01,BP_VAR02,BP_VAR0 ( BP_VAR00,BP_VAR01,BP_VAR02,BP_VAR03,VAR0) 3,VAR0) BEGIN VAR0 <= (( std_logic_vector'(BP_VAR03, BP_VAR02, BP_VAR01, BP_VAR00))); VAR00 <= VAR0(0); VAR01 <= VAR0(1); VAR02 <= VAR0(2); VAR03 <= VAR0(3); END PROCESS; END BEHAVIOR; LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY synopsys; USE synopsys.attributes.all; ENTITY AMD1 IS PORT (A0 : IN std_logic_vector (3 DOWNTO 0); VAR0 : OUT std_logic_vector (3 DOWNTO 0); A1,A2,A3,B,B0,B1,B2,B3,RESET: IN std_logic); END; ARCHITECTURE BEHAVIOR OF AMD1 IS COMPONENT SHELL_AMD1 PORT (A00,A01,A1,A02,A2,A03,A3,B,B0,B1,B2,B3,RESET: IN std_logic; VAR00,VAR01,VAR02,VAR03 : OUT std_logic); END COMPONENT; BEGIN SHELL1_AMD1 : SHELL_AMD1 PORT MAP (A00=>A0(0),A01=>A0(1),A1=>A1,A02=>A0(2), A2=>A2,A03=>A0(3),A3=>A3,B=>B,B0=>B0,B1=>B1,B2=>B2,B3=>B3,RESE T=>RESET,VAR00 =>VAR0(0),VAR01=>VAR0(1),VAR02=>VAR0(2),VAR03=>VAR0(3)); END BEHAVIOR;

135

6.3

Percobaan

Percobaan dilakukan dengan mengisikan salah state diagram yang sudah dirancang sebelumnya sesuai prosedur yang telah disebutkan sebelumnya.

6.4

Tugas

Buatlah sebuah diagram dari rangkaian Up/down Counter, Register, Demultiplexer dan Encoder

136

7 PERCOBAAN VII PEMROGRAMAN IC PLDs DENGAN ALL-11 7.1

Tujuan

Peserta praktikum dapat melakukan proses pengisian sebuah program desain elektronika tertentu ke dalam IC PLDs dengan menggunakan ALL-11. 7.2

Dasar Teori

Proses perancangan yang dilakukan pada percobaan sebelumnya pada dasarnya adalah agar dapat diimplementasikan ke dalam wujud sebuah hardware yang dikendalikan oleh sebuah IC PLDs. Pada percobaan ini akan dilakukan pengisian IC PLDs dengan sebuah program yang mengandung logika rancangan tertentu.

Gambar 7-1. ALL-11 Langkah pengisian IC (PLDs) dengan ALL-11 : o Buka program ALL-11 kemudian Wacess. o Pilih Device untuk memilih jenis IC yang akan diisikan ( berupa jenis produk dan jenis PLDs dan OK .

137

Gambar 7-2. Window WPLD1.EXE

o

o o o o o o o

7.3

Secara otomatis, maka akan keluar jendela WPLD1.EXE sebagai jendela yang berisikan fungsi-fungsi berupa Read, Blank, Program, Verify, Erase dan Security. Cek kondisi IC dengan Read yang berarti mengecek kondisi IC baik apa bukan. Pilih File untuk mengambil file desain berekstensi .JED yang sudah dibuat sebelumnya. Cek apakah IC masih kosong apa sudah terisi program dengan mengklik Blank. Jika IC dalam keadaan berisi program, maka klik Erase untuk menghapus program yang sudah ada sebelumnya. Kalau sudah kosong, maka IC siap untuk diisikan program berupa file .JED yang sudah di load sebelumnya dengan mengklik Program. Cek keberadaan program dengan mengklik Verify, yaitu untuk melihat apakah konfigurasi program sudah benar. Jika program sudah dianggap benar dan sudah diujikan ke alat sesungguhnya, maka program pada IC dapat dikunci dengan Security.

Percobaan

Percobaan dilakukan dengan mengisikan salah satu atau beberapa program yang sudah dirancang sebelumnya sesuai prosedur yang telah disebutkan sebelumnya.

138

7.4

Tugas Buatlah sebuah rancangan program yang dapat diimplementasikan ke dalam bentuk hardware !

139

LAPORAN RESMI PRAKTIKUM VHDL

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