ECE - 10ESL38 Dept. of Electronics and Communications Communications Engg. CITY ENGINEERING COLLEGE BANGALORE – 62.
Manual Prepared by: Mr. Vishvakiran RC, Asst. Prof., CEC
Logic Design Lab
2013
10ESL38
TABLE OF CONTENTS
Experiments
Page No.
IC Pin Configurations
2
1.
Boolean Expression realization using Logic gates
4
2.
Half/Full Adder and Subtractor
7
3.
a. Parallel Adder/ Subtractor
10
b. BCD to Excess-3 and Vice-versa
14
4.
Binary to Gray Conversion and vice versa
16
5.
MUX/DEMUX for arithmetic circuits
21
6.
Comparators
27
7.
Decoder Chip for LED Display
31
8.
Priority Encoder
33
9.
Flip-Flop verification
35
10. Counters
38
11. Shift Registers
50
12. Ring Counter/ Johnson Counter
55
13. Sequence Generator
57
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Logic Design Lab Syllabus – 10ESL38
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Possible Viva Questions
60
3 Sem, E&C Dept.
1
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Logic Design Lab
2013
10ESL38
TABLE OF CONTENTS
Experiments
Page No.
IC Pin Configurations
2
1.
Boolean Expression realization using Logic gates
4
2.
Half/Full Adder and Subtractor
7
3.
a. Parallel Adder/ Subtractor
10
b. BCD to Excess-3 and Vice-versa
14
4.
Binary to Gray Conversion and vice versa
16
5.
MUX/DEMUX for arithmetic circuits
21
6.
Comparators
27
7.
Decoder Chip for LED Display
31
8.
Priority Encoder
33
9.
Flip-Flop verification
35
10. Counters
38
11. Shift Registers
50
12. Ring Counter/ Johnson Counter
55
13. Sequence Generator
57
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Logic Design Lab Syllabus – 10ESL38
59
Possible Viva Questions
60
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Logic Design Lab
2013
10ESL38
IC Pin configurations Inverter (NOT Gate) - 7404LS
2-Input AND Gate - 7408LS
2-Input OR Gate - 7432LS
2-Input NAND Gate - 7400LS
2-Input NOR Gate - 7402LS
2-Input EX-OR Gate - 7486LS
3-Input NAND Gate - 7410LS
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4-bit Binary Full Adder74LS83
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Dual 4-Input NAND Gate - 7420LS
Dual 4-input Multiplexer74153
4-Bit Magnitude Comparator - 7485
Decoders/Demultiplexer 74139
Shift Register - 7495
Synchronous Up/Down Counter – 74192
Decimal scalar - 7490
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DualJKFlip-flop – 7476
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2013
10ESL38
Experiment No. 1
BOOLEAN EXPRESSION REALIZATION USING LOGIC GATES Aim: – To Simplify and Realize Boolean expressions using logic gates/Universal gates.
Components Required: -
IC 7408 (AND), IC 7404 (NOT), IC 7432 (OR),IC 7400 (NAND), IC 7402 (NOR),IC 7486 (EX-OR)
Procedure –
1. Verify that the gates are working. 2. Construct a truth table for the given problem. 3. Draw a Karnaugh Map corresponding to the given truth table. 4. Simplify the given Boolean expression manually using the Karnaugh Map.
A: Implementation Using Logic Gates
5. Realize the simplified expression using logic gates. 6. Connect VCC and ground as shown in the pin diagram. 7. Make connections as per the logic gate diagram. 8. Apply the different combinations of input according to the truth tables. 9. Check the output readings for the given circuits; check them against the truth tables. 10. Verify that the results are correct.
B. Implementation Using Universal Gates
11. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic. 12. Implement the simplified Boolean expressions using only NAND gates, and then using only NOR gates. 13. Connect the circuits according to the circuit diagrams, apply inputs according to the truth table and verify the results.
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10ESL38
Given Problem:
Truth Table:
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C D Y 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1
Switching Expression:
∑
π Karnaugh Map Simplification: K-Map for POS
K-Map for SOP CD
CD AB
00
01
11
AB
10
00 01
1
1
1
11
1
1
1
10
00
01
11
10
00
0
0
0
0
01
0
11
0
10
0
B 0
0
0
BC BD
C+D
Simplified Boolean Expression:
SOP form Y=f(A,B,C,D)=BC+BD POS form Y=f(A,B,C,D)=B(C+D)
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Expression Realization using Basic Gates: C
1
3
7408
1
2
B
3
7432 6
7408
D
Y=BC+BD
2
4 5
1
B C D
7432
Y=B(C+D)
3
7408
1
2
3
2
Realization using only NAND gates:
C
Realization using only NOR gates:
1
2
7400
3
B 9
2
8
B
7400 4
1
5 7402
3
4
Y=B(C+D)
6
Y=BC+BD
10 7400
D
7402
C D
6
5
8 7402
10
9
Realization using only NOR gates: C
2 7402
1
11 7402
3
13
12 5
B
5 7402
7402'
4
6
2
8
3
7402
10
7402'
6
10
Y=BC+BD
9
1
7402'
D
8
4
9
Realization using only NAND gates: 11
B
7400 1
C
7400
3
9 7400
2
rd
1 7400'
3
Y=B(C+D)
2
8
10
4
D
12
13
7400
6
5
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Experiment No. 2
HALF/FULL ADDER AND HALF/FULL SUBTRACTOR Aim: – To realize half/full adder and half/full subtractor using Logic gates
Components Required: -
IC 7408, IC 7432, IC 7486, IC 7404, etc.
Procedure: -
1. Verify that the gates are working. 2. Make the connections as per the circuit diagram for the half adder circuit, on the trainer kit. 3. Switch on the VCC power supply and apply the various combinations of the inputs according to the respective truth tables. 4. Note down the output readings for the half adder circuit for the corresponding combination of inputs. 5. Verify that the outputs are according to the expected results. 6. Repeat the procedure for the full adder circuit, the half subtractor and full subtractor circuits. 7. Verify that the sum/difference and carry/borrow bits are according to the expected values.
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A. Half Adder using Logic Gates: Half Adder Using Basic Gates
1
A B
7486
3
2 1 7408
3
A
B
S
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
2
B. Full Adder Using Logic Gates
Full Adder Using Basic Gates A
B
Cn-1
S
C
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
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C. Half Subtractor Using Logic Gates Half Subtractor Using Basic Gates
A
B
D
Bo
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
D. Full Subtractor Using Logic Gates
Full Subtractor Using Basic Gates
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A
B
Cn-1
D
B
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
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Experiment No. 3
PARALLEL ADDER AND SUBTRACTOR USING 7483 Aim: – i. To realize Parallel Adder and Subtractor Circuits using IC 7483 ii. BCD to Excess-3 Code conversion and Vice Versa using IC7483
Components Required: -
IC 7483, IC 7486, etc.
Procedure: -
1. Connect one set of inputs from A1 to A4 pins and the other set from B1 to B4, on the IC 7483. 2.Connect the pins from S1 to S4 to output terminals. 3. Short S,C0 to XOR gate 1 input and other input take from C4 and obtain the Output Carry Cout (Output Borrow Bout). 4. In order to Perform Addition take S=0. 5. In order to implement the IC 7483 as a subtractor, Take S=1, Apply the B input through XOR gates (essentially taking complement of B). 6. Apply the inputs to the adder/ subtractor circuits as shown in the truth tables. 7. Check the outputs and note them down in the table for the corresponding inputs. 8. Verify that the outputs match with the expected results. IC 7483 Pin Diagram
7483
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10ESL38
A. IC 7483 as a Parallel Adder
Circuit Diagram: Output Carry
VCC 5
A4
14
A3
Input Data A
Cout
S4
10
2
3
16
6
4
9
S3
Data Output
S2 S1
2 4
7486
B3
Input Data B
3
15
6
7486
7486' 2
8
A1
1
C4
3
A2
B4
1
1
7483
5 9
7486
B2
8
7
10 12
7486
B1
11
11
13
12
13
GND
C0
S=0
4-BIT Parallel Adder Using 7483 where S=0
Truth Table:Input Data A
Input Data B
Addition
A4
A3
A2
A1
B4
B3
B2
B1
Cout
S4
S3
S2
S1
1
0
0
0
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
1
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B. IC 7483 as a Parallel Subtractor Output Carry
VCC
Circuit Diagram: 5
A4
14
A3
Input Data A
1
1
Bout
S4 15
10
S3
2
3
16
6
4
Data Output
S2
6
1
S1
9
2 4
7486
B3
Input Data B
3
2
8
A1
7486
7486'
3
A2
B4
C4
7483
5 9
7486
B2
8
7
10 12
7486
B1
11
11
13
12
13
GND
C0
S=1
4-BIT Parallel Subtractor Using 7483 Where S=1
Truth Table: Subtraction Input Data A
Input Data B
A4
A3
A2
A1
B4
B3
B2
B1
Bout
S4
S3
S2
S1
1
0
0
0
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
0
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
0
1
Note: Bout = 1 for A
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Bout = 0 for A>B;
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Example 4bit adder operation using 7483 if control input S=0,addition can be performed Ex:If ↓C0=0 A4 A3 A2 A1=1100
B4 B3 B2 B1=0011
then Sum,S4 S3 S2 S1 =1111 and C0C4 = Cout. 4 bit subtraction operation using 7483 for A>B here S=1 A4 A3 A2 A1= 1001 B4 B3 B2 B1= 1101 (2's complement) of +3=0011 The end around carry is disregarded 1 0110 C0 C4 = Bout = 0
Difference, S4 S3 S2 S1 = 0110 2's complement method of subtraction can be performed,if S=1(i.e. C0=1). Consider the above Example A 4 A3 A 1001 and B 4 B3 B2 B1= 0011 _2 A_1=_ 1‟s Complement of B4 B3 B2 B1is B4 B3 B2 B1= 1100
.
A _ A2_ A1= 4 A3_
1001
B4 B3 B2 B1=
1100→(1's complement) of +3 = 0011 +1 ←C0=1(S&C0 shorted)
The end around carry is disregarded 1 0110 C0 C4 = Bout = 0
2‟s Complement of B input = -B
+6
4 bit subtraction operation using 7483 for A
A _ A2_ A1= 4 A3_ B4 B3 B2 B1=
1110 0000→(1's complement) of +15=1111
2‟s Complement of B input = -B
0 1111 →(2's complement) of +1=0001 The end around carry is disregarded C0 C4 = Bout = 1 -1
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C. BCD To Excess-3 And Vice-Versa Conversion Using 7483 Chip I.
BCD TO EXCESS-3 CONVERTER
Note: S = 0 and B3,B2,B1,B0 = 0011 vary the BCD input at A3,A2,A1,A0. VCC
Circuit Diagram: A3 A2
X
NC
E3
8 A0
15 10
E2
2
E1
6
1
Input Data B
C4
14 3
A1
Input Data A
7486
B3 = 0
5 1
3
16
6
4
E0
9
Data Output
2 4
7486
B2 = 0
7483
5 9
7486
B1 = 1
8
7
10 12
7486
B0 = 1
11
11
13
12
13
GND
C0
S=0
BCD to XCS3 using 7483
Truth Table :
Consider Constant Value for B3B2B1B0 = 0011 and S=0 BCD Inputs
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Excess – 3 Outputs
A3
A2
A1
A0
E3
E2
E1
E0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
X
X
X
X
1
0
1
1
X
X
X
X
1
1
0
0
X
X
X
X
1
1
0
1
X
X
X
X
1
1
1
0
X
X
X
X
1
1
1
1
X
X
X
X
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EXCESS-3 to BCD CONVERTER
Note: S=1 andB3,B2,B1,B0 = 0011 vary the Excess-3 input at A3(E3),A2(E2),A1(E1),A0(E0) .
Circuit Diagram:
VCC 5
A3
1 14
A2
X NC
A1
Input Data A
D
8 15
A0
7486
B3 = 0
10
C
2
B
6
1
Input Data B
C4
3
3
16
6
4
A
9
Data Output
2 4
7486
B2 = 0
7483
5 9
7486
B1 = 1
8
7
10 12
7486
B0 = 1
11
11
13
12
13
C0
S=1
GND
XCS3 to BCD using 7483
Truth Table :
Consider Constant Value for B3B2B1B0 = 0011 and S=1 Excess-3 Inputs
rd
BCD Outputs
E3
E2
E1
E0
A
B
C
D
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
0
1
1
0
1
1
1
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
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Experiment No. 4
BINARY TO GRAY CONVERTER AND VICE VERSA Aim: – To realize:. i. Binary to Gray Converter using logic gates. ii. Gray to Binary Converter using logic gates.
Components Required: -
IC 7486, etc.
Procedure: -
1.Verify that the gates are working properly. 2. Write the proper truth table for the given Binary to Gra y converter. 3.
Draw Karnaugh maps for each bit of output. Simplify the Karnaugh maps to get simplified Boolean Expressions.
4. Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray converter. 5. Apply the Binary inputs at B 3-B0 pins, according to the truth table. 6. Check the outputs at the G 3-G0 pins and note them down in the table for the corresponding inputs. 7. Verify that the outputs match with the expected results. 8. Repeat the procedure to design, test and verify the working of a Grey to Binary Converter.
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A. Binary to Gray Converter.
Truth Table: Binary Input
Gray Code Output
B3
B2
B1
B0
G3
G2
G1
G0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
Karnaugh Maps:
For G3:
For G2:
G3 = B3 rd
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For G1:
For G0:
Circuit:
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B. Gray to Binary Converter
Truth Table Gray Code Input
Binary Output
G3
G2
G1
G0
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
1
0
0
1
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
Karnaugh Maps:
For B3:
For B2:
B3 = G3 rd
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For B1:
For B0:
Circuit:
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Experiment No. 5
MUX/DEMUX FOR ARITHMETIC CIRCUITS Aim: – To study IC 74153 and 74139 and to implement arithmetic circuits with them.
Components Required: -
IC 74153, IC 74139, IC 7404, IC 7400, IC 7420,etc.
Procedure – A. For MUX IC 74153 1.The Pin [16] is connected to + Vcc and Pin [8] is connected to ground. 2. The inputs are applied either to ‘A’ input or ‘B’ input. 3.If MUX ‘A’ has to be initialized, E A is made low and if MUX ‘B’ has to be
initialized, EB is made low. 4. Based on the selection lines one of the inputs will be selected at the
output, and thus the truth table is verified. 5.In case of half adder using MUX, apply constant inputs at (I 0a, I1a, I2a,
I3a)and(I0b, I1b, I2b and I3b) as shown. 6.The corresponding values of select input lines, A and B (S 1 and S0) are
changed as per table and the output is taken at Z a as sum and Zb as carry. 7.In this case, the inputs A and B are varied. Making E a and Eb zero
andthe output is taken at Z a, and Zb. 8.In case of Half Subtractor, connections are made according to the circuit,
Inputs are applied at A and B as shown, and outputs are taken at Z a (Difference) and Z b (Borrow). Verify outputs. 9.In full adder using MUX, the inputs are applied at C n-1, A n and Bn
according to the truth table. The corresponding outputs are taken at S n (pin Za) and Cn (pin Zb) and are verified according to the truth table. 10. In full subtractor using MUX, the inputs are applied at C n-1, A n and Bn
according to the truth table. The corresponding outputs are taken at pin Za(Difference) and pin Z b(Borrow) and are verified according to the truth table.
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Half Adder Using 74153
Half Subtractor using 74153
Truth Table:
Inputs
Half Adder Outputs
A
B
Sum
Carry
Diff
Borrow
0
0
0
0
0
0
0
1
1
0
1
1
1
0
1
0
1
0
1
1
0
1
0
0
Full Adder Using 74153
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Half Subtractor Outputs
3 Sem, E&C Dept.
Full Subtractor using 74153
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Truth Tables for Full Adder/Subtractor using 74153 Inputs
Full Adder Outputs
A
B
Cin/Bin
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Full Subtractor Outputs
S
Cout
D
Bout
0
0
0
0
1
0
1
1
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
Procedure – B. For DEMUX IC 74139 1. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground. 2. The inputs are applied either to ‘A’ input or ‘B’ input. 3. If DEMUX ‘A’ has to be initialized, E A is made low and if DE MUX ‘B’ 4. 5.
6.
7.
8.
rd
has to be initialized, E B is made low. Based on the selection lines one of the inputs will be selected at the set of outputs, and thus the truth table is verified. In case of half adder using DEMUX,Ea is set to 0, the corresponding values of select input lines, A and B (S 1a and S0a) are changed as per table and the output is taken at Sum and Carry. Verify outputs. In case of Half Subtractor, connections are made according to the circuit, Inputs are applied at A and B as shown, and outputs are taken at Differenceand Borrow. Verify outputs. In full adder using DEMUX, the inputs are applied at C n-1, A n and Bn according to the truth table. The corresponding outputs are taken at Sum and Carry, and are verified according to the truth table. In full subtractor using DEMUX, the inputs are applied at C n-1, A n and Bn according to the truth table. The corresponding outputs are taken at Difference and Borrow as shown, and are verified according to the truth table.
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Half Adder Using 74139
Half Subtractor Using 74139
Truth Tables: Inputs
rd
Half Adder Outputs
Half Subtractor Outputs
A
B
Sum
Carry
Diff
Borrow
0
0
0
0
0
0
0
1
1
0
1
1
1
0
1
0
1
0
1
1
0
1
0
0
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Full Adder Using 74139
Full Subtractor Using 74139
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Truth Tables: Inputs
rd
Full Adder Outputs
A
B
Cin/Bin
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
3 Sem, E&C Dept.
Full Subtractor Outputs
S
Cout
D
Bout
0
0
0
0
1
0
1
1
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
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Experiment No. 6
ONE/TWO BITCOMPARATOR AND IC 7485 Aim: – To verify the truth tables for one bit and two bit comparators after constructing them with basic logic gates, and to study the working of IC 7485. Components Required: -
IC 7404, IC 7408, IC 7486, IC 7432, IC 7485, etc.
Procedure – A. Comparators Using Logic Gates: 1.Verify the working of the logic gates. 2.Make the connections as per the respective circuit diagrams. 3.Switch on Vcc. 4.Apply the inputs as per the truth tables. 5.Check the outputs and verify that they are according to the truth tables.
B. Study of IC 7485: 1.Write the truth table for an4-bit comparator. 2. Connect pin 16 to V cc and pin 8 to GND for the ICs. 3.Apply the two inputs as shown; making sure that the MSB and LSB is correctl y
connected. 4. Outputs are recorded at pin 2 (AB), pin 3 (A=B) pins and a re
verified as being according to the truth table.
A. One-Bit Comparator: Circuit :
Truth Table: 1bit Comparator Inputs
Outputs
A
B
A>B
A=B
A
0
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
B. Two-Bit Comparator: rd
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Truth Table : 2bit Comparator A1 A0 B1 B0
A>B
A=B
A
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
1
1
0
0
1
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
0
1
1
1
1
0
1
0
Karnaugh Maps: For A>B:
For A
For A=B
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Circuit:
C. 4-Bit comparator using IC 7485 Pin Diagram:
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Truth Table: 4bit Comparator Input A
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Input B
Output
A3
A2
A1
A0
B3
B2
B1
B0
A>B
A
A=B
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
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Experiment No. 7
DECODER CHIP FOR LED DISPLAY Aim: – Tostudy the use of a Decoder Chip (IC 7447) to drive a LED Display.
Components required: -
IC 7447, 7-segment LED Display, etc.
Procedure: -
1. Test and verify that all the segments of the LED Display are working. 2. Make the circuit connections as shown in the circuit diagram. 3. Connect Pin 16 to Vcc and Pin 8 to GND. 4. Connect the input pinsof the 7-segment LED Display to the respective pins (A3-A0) of the 7447 BCD to 7-Segment decoder driver chip. 5. Give the different BCD inputs according to the truth table, and observe the Decimal outputs displayed on the 7-segment LCD Display. 6. Verify that the outputs match the expected results in the truth tables.
IC 7447 Pin Diagram
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Circuit Diagram:
Output Table: BCD inputs D C B A 0 0 0 0
segment outputs a b c d e f g 1 1 1 1 1 1 0
0
0
0
1
0 1 1 0 0 0 0
0
0
1
0
1 1 0 1 1 0 1
0
0
1
1
1 1 1 1 0 0 1
0
1
0
0
0 1 1 0 0 1 1
0
1
0
1
1 0 1 1 0 1 1
0
1
1
0
0 0 1 1 1 1 1
0
1
1
1
1 1 1 0 0 0 0
1
0
0
0
1 1 1 1 1 1 1
1
0
0
1
1 1 1 0 0 1 1
display
7-segment LED Display Schematic
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Experiment No. 8
PRIORITY ENCODER Aim: – Tostudy the use of a 10-line-to-4-Line Priority Encoder Chip (IC 74147).
Components Required: -
IC 74147, etc.
Procedure: -
1. Make the connections as shown in the circuit diagram. 2. Connect Pin 16 of the IC to Vcc and Pin 8 to GND. 3. Connect the pins designated Inputs 1 through 9, to the input switches of the trainer kit. 4. Connect the Output pins designated A, B, C, D to the LED indicators of the trainer kit. 5. Provide the inputs to the encoder chip as shown in the truth table. 6. Observe the outputs on the LED indicators, and note down the results for the respective inputs. 7. Verify that the outputs are as shown in the truth table.
IC 74147 Pin Diagram
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Truth Table:
1 1 0 X X X X X X X X
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2 1 1 0 X X X X X X X
3 Sem, E&C Dept.
3 1 1 1 0 X X X X X X
Decimal Input 4 5 6 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 X 0 1 X X 0 X X X X X X X X X
7 1 1 1 1 1 1 1 0 X X
8 1 1 1 1 1 1 1 1 0 X
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9 1 1 1 1 1 1 1 1 1 0
BCD Output D C B A 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0
Decimal Value 0 1 2 3 4 5 6 7 8 9
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Experiment No. 9
STUDY OF FLIP-FLOPS Aim: – To study and verify the truth tables for J-K Master Slave Flip Flop, T-type and DType Flip-Flops.
IC 7410, IC 7400, etc.
Components Required: -
Procedure: -
1. Make the connections as shown in the respective circuit diagrams. 2. Apply inputs as shown in the respective truth tables, for each of the flip-flop circuits. 3. Check the outputs of the circuits; verify that they match that of the respective truth tables.
A. J-K Master-Slave Flip-Flop Circuit:
Truth Table :
rd
Preset
Clear
J
K
Clock
0
1
X
X
X
1
0
Set
1
0
X
X
X
0
1
Reset
1
1
0
0
1
1
0
1
0
1
Reset
1
1
1
0
1
0
Set
1
1
1
1
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Status
No Change
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B. T-Type Flip-Flop
Circuit:
Truth Table :
rd
Preset
Clear
T
1
1
0
1
1
1
3 Sem, E&C Dept.
Clock
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C. D-Type Flip-Flop
Circuit:
Truth Table:
rd
Preset
Clear
D
1
1
0
0
1
1
1
1
1
0
3 Sem, E&C Dept.
Clock
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Experiment No. 10
STUDY OF COUNTERS Aim: – Realization of 3-bit counters as a sequential circuit and Mod-N counter Design (7476, 7490, 74192, 74193)
Components Required: -
IC 7476, IC 7490, IC 74192, IC 74193, IC 7400, IC 7408, IC 7416, IC 7432, etc.
Procedure: A. Counter Circuits using IC 7476
1. Make the connections as shown in the respective circuit diagrams. 2. Clock inputs are applied one by one at the clock I/P, and the outputs are observed at QA, QB and QC pins of the 7476 ICs. 3. Verify that the circuit outputs match those indicated by the truth tables. B. Study of Counters IC 74192, IC 74193
1. Connections are made as shown in the respective ci rcuit diagrams, except for the connection from the output of the NAND gate to the load input. 2. The data (0011) = 3 is made available at the t he data input pins designated A, B, C and D respectively. 3. The Load pin is made LOW so that the data 0011 appears at Q D, QC, QB and QA respectively. 4. Now, the output of the the NAND gate is connected to the Load input input pin. 5. Clock pulses are applied to the “Count Up” pin, and truth table is veri fied for that condition. 6. Next, the data (1100) =12 (for 12 to 5 counter) is applied at A, B, C and D and the same procedure as explained above, is performed. 7. IC 74192 and IC 74193 have the same pin configurations. 74192 can be configured to count between 0 and 9 in either direction. Starting value can be any number between 0 and 9.
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A. 3-bit Asynchronous Up Counter
Circuit Diagram:
Timing Diagram:
Truth Table:
rd
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
0
0
0
9
0
0
1
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B. 3-bit Asynchronous Down Counter
Circuit Diagram:
Timing Diagram:
Truth Table:
rd
Clock
QC
QB
QA
0
1
1
1
1
1
1
0
2
1
0
1
3
1
0
0
4
0
1
1
5
0
1
0
6
0
0
1
7
0
0
0
8
1
1
1
9
1
1
0
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C. Mod-5 Asynchronous Counter
Circuit:
Timing Diagram:
Truth Table:
rd
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
0
0
0
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D. Mod-3 Asynchronous Counter
Circuit:
Timing Diagram:
Truth Table:
rd
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
0
0
4
0
0
1
5
0
1
0
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E. 3-bit Synchronous Counter Circuit:
Timing Diagram:
Truth Table:
rd
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
0
0
0
9
0
0
1
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F. 4-bit Ripple Counter
Circuit:
Truth Table:
rd
CLK
QD
QC
QB
QA
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
15
1
1
1
1
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G. Mod-10 Ripple Counter
Circuit:
Truth Table
rd
CLK
QD
QC
QB
QA
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
0
0
0
0
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H. Decade Counter (using IC 7490)
Circuit:
Truth Table:
rd
Clock
QD
QC
QB
QA
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
0
0
0
0
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I. Mod-8 Counter (Using IC 7490)
Circuit:
Truth Table:
rd
Clock
QD
QC
QB
QA
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
0
0
0
0
9
0
0
0
1
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J. Presettable counter using IC 74192/IC 74193 to count up from 3 to 8
Circuit:
Truth Table:
rd
Clock
QD
QC
QB
QA
Decimal
0
0
0
1
1
3
1
0
1
0
0
4
2
0
1
0
1
5
3
0
1
1
0
6
4
0
1
1
1
7
5
1
0
0
0
8
6
0
0
1
1
3
7
0
1
0
0
4
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K. Presettable counter using IC 74192/74193 to count down from 5 to 12
Circuit:
Implementation of 4-Input OR gate:
Truth Table:
rd
Clock
QD
QC
QB
QA
Decimal
0
0
1
0
1
5
1
0
1
1
0
6
2
0
1
1
1
7
3
1
0
0
0
8
4
1
0
0
1
9
5
1
0
1
0
10
6
1
0
1
1
11
7
1
1
0
0
12
8
0
1
0
1
5
9
0
1
1
0
6
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Experiment No. 11
STUDY OF SHIFT REGISTERS Aim: – To study IC 74S95, and the realization of Shift left, Shift right, SIPO, SISO, PISO, PIPO operations using the same. Components Required: -
IC 7495, etc.
Procedure: A. Serial In-Parallel Out (Left Shift):
1. Make the connections as shown in the respective c ircuit diagram. 2. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to HIGH, and connect clock input to Pin 8 (Clk 2). 3. Apply the first data at pin 5 (D) and apply one clock pulse. We observe that this data appears at pin 10 (Q D). 4. Now, apply the second data at D. Apply a clock pulse. We now observe that the earlier data is shifted from QD to QC, and the new data appears at Q D. 5. Repeat the earlier step to enter data, until all bits are entered one by one. 6. At the end of the 4 th clock pulse, we notice that all 4 bits are available at the parallel output pins QA (MSB), QB, QC, QD (LSB). 7. Enter more bits to see there is a left shifting of bits with each succeeding clock pulse. B. Serial In-Parallel Out (Right Shift):
1. Make the connections as shown in the respective ci rcuit diagram. 2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to LOW, and connect clock input to Pin 9 (Clk 1). 3. Apply the first data at pin 1 (SD1) and apply one clock pulse. We observe that this data appears at pin 13 (Q A). 4. Now, apply the second data at SD1. Apply a clock pulse. We now observe that the earlier data is shifted from QA to QB, and the new data appears at Q A. 5. Repeat the earlier step to enter data, until all bits are entered one by one. 6. At the end of the 4 th clock pulse, we notice that all 4 bits are available at the parallel output pins QA through QD. 7. Enter more bits to see there is a right shifting of bits with each succeeding clock pulse. rd
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C. Serial In-Serial Out Mode:
1. Connections are made as shown in the SISO circuit diagram. 2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set
to LOW, and connect clock input to Clk 1(Pin 9). 3. The 4 bits are applied at the Serial Input pin (Pin 1), one by one, with a clock pulse in between each pair of inputs to load the bits into the IC. 4. At the end of the 4 th clock pulse, the first data bit, „d0‟ appears at the output pin QD. 5. Apply another clock pulse, to get the second data bit „d1‟ at Q D. Applying yet another clock pulse gets the third data bit „d2‟ at Q D, and so on. 6. Thus we see the IC 7495 operating in SISO mode, with serially applied inputs appearing as serial outputs.
D. Parallel In-Serial Out Mode:
1. Connections are made as shown in the PISO circuit diagram. 2. Now apply the 4-bit data at the parallel input pins A, B, C, D (pins 2 through 5). 3. Keeping the mode control M on HIGH, apply one clock pulse. The data applied at the parallel input pins A, B, C, D will appear at the parallel output pins Q A, QB, QC, QDrespectively. 4. Now set the Mode Control M to LOW, and apply clock pulses one by one. Observe the data coming out in a serial mode at QD. 5. We observe now that the IC operates in PISO mode with parallel inputs being transferred to the output side serially.
E. Parallel In-Parallel Out Mode:
1. Connections are made as shown in the PIPO mode circuit diagram. 2. Set Mode Control M to HIGH to enable Parallel transfer. 3. Apply the 4 data bits as input to pins A, B, C, D. 4. Apply one clock pulse at Clk 2 (Pin 8). 5. Note that the 4 bit data at parallel inputs A, B, C, D appears at the parallel output pins Q A, QB, QC, QDrespectively.
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IC 7495 Pin Diagram:
A. SIPO Mode (Left Shift) Circuit:
Truth Table:
Clock
Serial I/P
QA
QB
QC
QD
1
1
X
X
X
1
2
0
X
X
1
0
3
1
X
1
0
1
4
1
1
0
1
1
1
B. SIPO MODE (Right Shift) Circuit:
Truth Table:
Clock
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Serial I/P
QA
QB
QC
QD
1
1
1
X
X
X
2
0
0
1
X
X
3
1
1
0
1
X
4
1
1
1
0
1
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Logic Design Lab
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10ESL38
C. SISO Mode
Circuit:
Truth Table:
Clock
Serial I/P
QA QB QC
QD
1
d0=0
0
X
X
X
2
d1=1
1
0
X
X
3
d2=1
1
1
0
X
4
d3=1
1
1
1
0=d0
5
X
X
1
1
1=d1
6
X
X
X
1
1=d2
7
X
X
X
X
1=d3
D. PISO Mode
Circuit:
Truth Table:
Mode
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Clk
Parallel I/P
Parallel O/P
A
B
C
D QA QB QC QD
1
1
1
1
0
1
1
0
1
1
0
2
X
X X X
X
1
0
1
0
3
X
X X X
X
X
1
0
0
4
X
X X X
X
X
X
1
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Logic Design Lab
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10ESL38
E. PIPO Mode
Circuit:
Truth Table:
Clk
Parallel I/P
Parallel O/P
A B C D QA QB QC QD 1
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1
0
1
1
1
0
1
1
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Logic Design Lab
2013
10ESL38
Experiment No. 12
RING COUNTER /JOHNSON COUNTER Aim: – To design and study the operation of a ring counter and a Johnson Counter.
Components Required: -
IC 7495, IC 7404, etc.
Procedure: -
1. Make the connections as shown in the respective circuit diagram for the Ring Counter. 2. Apply an initial input (1000) at the A, B, C, D pins respectively. 3. Keep Select Mode = HIGH (1) and apply one clock pulse. 4. Next, Select Mode = LOW (0) to switch to serial mode and apply clock pulses. 5. Observe the output after each clock pulse, record t he observations and verify that they match the expected outputs from the truth table. 6. Repeat the same procedure as above for the Johnson Counter circuit and verify its operation.
A. Ring Counter
Circuit:
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Truth Table:
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Mode
Clock
QA QB QC QD
1
1
1
0
0
0
0
2
0
1
0
0
0
3
0
0
1
0
0
4
0
0
0
1
0
5
1
0
0
0
0
6
0
1
0
0
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Logic Design Lab
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10ESL38
B. Johnson Counter
Circuit:
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Truth Table:
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Mode
Clock
QA QB QC QD
1
1
1
0
0
0
0
2
1
1
0
0
0
3
1
1
1
0
0
4
1
1
1
1
0
5
0
1
1
1
0
6
0
0
1
1
0
7
0
0
0
1
0
8
0
0
0
0
0
9
1
0
0
0
0
10
1
1
0
0
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Logic Design Lab
2013
10ESL38
Experiment No. 13
SEQUENCE GENERATOR Aim: – To design and study the operation of a Sequence Generator.
Components Required: -
IC 7495, IC 7486, etc.
Theory: -
In order to generate a sequence of length „S‟, it is necessary to use at least „N‟ number of Flip-flops, in order to satisfy the condition . The given sequence length S = 15 Therefore, N = 4 Note: There is no guarantee that the given sequence c an be generated by 4 flip-flops. If the sequence is not realizable by 4 flip-flops, we need to use 5 flip-flops, and so on.
Procedure:-
1. Truth table is constructed for the given sequence, and Karnaugh maps are dr awn in order to obtain a simplified Boolean expression for the circuit. 2. Connections are made as shown in the circuit dia gram. 3. Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9). 4. Clock pulses are applied at CLK 1 and the output values are noted, and checked against the expected values from the truth table. 5. The functioning of the circuit as a sequence generator is verified.
Circuit:
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Logic Design Lab
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10ESL38
Truth Table:
Map Value
Karnaugh Map:
O/p Clock QA QB QC QD D
15
1
1
1
1
1
0
7
2
0
1
1
1
0
3
3
0
0
1
1
0
1
4
0
0
0
1
1
8
5
1
0
0
0
0
4
6
0
1
0
0
0
2
7
0
0
1
0
1
9
8
1
0
0
1
1
12
9
1
1
0
0
0
6
10
0
1
1
0
1
11
11
1
0
1
1
0
5
12
0
1
0
1
1
10
13
1
0
1
0
1
13
14
1
1
0
1
1
14
15
1
1
1
0
1
1
1
1
1
1 1
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Logic Design Lab
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10ESL38
Syllabus
LOGIC DESIGN LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code : 10ESL38
IA Marks : 25
Hrs/ Week : 03
Exam Hours : 03
Total Hrs.:
Exam Marks : 50
NOTE: Use discrete components to test and verify the logic gates. LabView can be used for designing the gates along with the above. 1. Simplification, realization of Boolean expressions using logic gates/Universal gates. 2. Realization of Half/Full adder and Half/Full Subtractors using logic gates. 3. (i)Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versausing 7483 chip. 4. Realization of Binary to Gray code conversion and vice versa 5. MUX/DEMUX – use of 74153, 74139 for arithmetic circuits and code converter. 6. Realization of One/Two bit comparator and study of 7485 magnitude comparator. 7. Use of Decoder chip to drive LED display. 8. Use of IC 74147 as Priority encoder. 9. Truth table verification of Flip-Flops: (i)
JK Master slave
(ii)
T type
(iii)
D type.
10. Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476, 7490, 74192,74193). 11. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95. 12. Wiring and testing Ring counter/Johnson counter. 13. Wiring and testing of Sequence generator.
http://www.scribd.com/doc/62491691/Logic-Design-Lab-Manual-10ESL38-3rd-sem-2011
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