Operational Amplif iers Av
vo vi
3.5 In circuit shown in fig. P3.5.4, the input voltage v i is
?
0.2 V. The output voltage vo is
400 k
50 k 40 k
vi
vi
vo
150 k
10 k 25 k
vo
R
Fig. P3.5.4
Fig. P3.5.1
(A) 10
(B) 10
(A) 6 V
(B) 6 V
(C) 11
(D) 11
(C) 8 V
(D) 8 V
Av
vo vi
Forr th Fo the e cir ircu cuiit shown in fi fig g. P3.5 .5.5 .5 gain is
?
Av
400 k
vo
vi
10 10.. The value of R R
is 100 k
40 k
vi
100 k
vo
60 k
100 k
vi
vo
Fig. P3.5.2
(A) 10
(B) 10
(C) 13.46
(D) 13.46
The
input
to th the e
circuit
in
fig.
Fig. P3.5.5
P3.5.3
vi 2sin t mV. The current io is
(B) 450 k
(C) 4.5 M
(D)) 6 M (D
Forr th Fo the e op op-a -amp mp ci circ rcui uitt sh show own n in fi fig. g. P3 P3.5 .5.6 .6 th the e
10 k
vi
is
(A) 600 k
voltage gain Av
1 k io
vo
vi is
R
vo
R
R
4 k
R
R
R vi vo
Fig. P3.5.3
(A) 2sin t A
(B) 7sin t A
(C) 5sin t A
(D) 0
Fig. P3.5.6
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183
Operational Amplifiers
(A) 8
3.5
(B) 8
(C) 10
20
20 k
+0.5 V
(D) 10
40 k -1 V vo
60 k
For the op-amp shown in fig. P3.5.7 open loop
+2 V
differential gain is Aod 10 3. The output voltage v o for vi 2 V is
Fig. P3.5.10 100 k
vi
100 k
(A) 2.67 V
(B) 2.67 V
(C) 6.67 V
(D) 6.67 V
vo
In the circuit of fig. P3.5.11 the voltage vi1 is (1 2 sin
t) mV
and v i2
10 mV.
The output voltage
vo is
Fig. P3.5.7
20 k
(A) 1.996
(B) 1.998
(C) 2.004
(D) 2.006
20 k 2 k
vi1
1 k vo
vi2
The op-amp of fig. P3.5.8 has a very poor open-loop
1 k
voltage gain of 45 but is otherwise ideal. The closed-loop gain of amplifier is
Fig. P3.5.11
(A) 0.4(1 sin
t) mV (C) 0.4(1 2 sin t) mV
100 k 2 k vo
(B) 0 .4(1 sin
t)
(D) 0.4(1 2 sin
t)
mV
For the circuit in fig. P3.5.12 the output voltage is
vi
vo 2.5 V in response to input voltage vi 5 V. The
Fig. P3.5.8
finite open-loop differential gain of the op-amp is
(A) 20
(B) 4.5
(C) 4
(D) 5
vi
500 k vo
1 k
For the circuit shown in fig. P3.5.9 the input voltage Fig. P3.5.12
vi is 1.5 V. The current io is (A) 5 10 4
10 k
vi
mV
(C) 2
6 k 8 k io
(B) 250.5
10 4
(D) 501
vo ?
vo
100 k 5 k 100 k vo
20 k
Fig. P3.5.9
+18 V 40 k
(A) 1.5 mA
(B) 1.5 mA
(C) 0.75 mA
(D) 0.75 mA
+15 V
Fig. P3.5.13
In the circuit of fig. P3.5.10 the output voltage vo is
(A) 34 V
(B) 17 V
(C) 32 V
(D) 32 V
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3.5
Operational Amplifiers
vo ?
184
For the circuit shown in fig. P3.5.18 the true relation is
100 k 20 k vo
60 k +10 V
vo1
10 k 20 k
1 k
+15 V
R
30 k R vi
Fig. P3.5.14
vo2
(A) 5.5 V
(B) 4.58 V
(C) 5.5 V
(D) 4.58 V
Av
vo vi
Fig. P3.5.18
? R
R
(A) vo1
vo2
(C) vo
2 vo2
(B) vo1
vo2
(D) 2 vo1
vo2
R
vo ?
R vo
R
10 10 k
vi vo
+6 V 48 k
Fig. P3.5.15
(A) 5
(B) 5
(C) 6
(D) 6
5 k
6 k
Fig. P3.5.19
Statement for Q.16–17:
(A)
4 V 3
(B)
(C)
2 V 3
(D)
The circuit is as shown in fig. P3.5.16–17.
vo
50 k
2 V 3 4 V 3
vo ?
1 k
vi
3 k
Fig. P3.5.16–17
(B) 1
(C)
(D) 50
vo
12 V
The ideal closed-loop voltage gain is (A) 1
4 k
2 k R
1 k
If open-loop gain is Aod 999, then closed-loop gain
Fig. P3.5.20
is (A) 0.999
(B) 0.999
(A) 12 V
(B) 12 V
(C) 1.001
(D) 1.001
(C) 18 V
(D) 18 V
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185
Operational Amplifiers
vo ?
Avd
3.5
8 k
vo ( v1
v2 )
?
4 k v1
vo 0.1 mA
+
2 k
2 V
6 k 2 k 4 k
vo
Fig. P3.5.21 -
(A) 30V
(B) 18V
(C) 18V
(D) 28V v2
vo ? 10 k
Fig. 3.5.25
vo 0.1 mA
(A) 8
(B) 6
(C) 6
(D) 8
20 k
vo ?
5 V
Fig. P3.5.22
vo
(A) 4 V
(B) 4 V
(C) 5 V
(D) 5 V
io ?
1 3 k
2 k 3 k 4 k
3 k
io 12 V
2
6 V
2m A 6 k
Fig. 3.5.26 Fig. P3.5.23
(A) 12 mA
(B) 8.5 mA
(C) 6 mA
(D) 7.5 mA
(A) 6 V
(B) 6 V
(C) 10 V
(D) 10 V
Av
vo ?
vo vi
? 2 k vi
6 k
1 k vo
vo
3 k
2.5 V 8 k
6 k
1 k
4 k
Fig. P3.5.27
Fig. P3.5.24
(A) 7.5 V
(B) 7.5 V
(A) 15.8
(B) 10
(C) 8 V
(D) 8 V
(C) 17.4
(D) 8
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3.5
Operational Amplifiers
For the circuit shown in fig. P3.5.28 the input
186
io ?
resistance is
6 k
io
2 k
vo
6 A 2 k 4 k i s
Fig. S3.5.31 2 k 10 k
Fig. P3.5.28
(A) 18 A
(B) 18 A
(C) 36 A
(D) 36 A
Statement for Q.32–33:
(A) 38 k
(B) 17 k
(C) 25 k
(D) 47 k
Consider the circuit shown below
In the circuit of fig. P3.5.29 the op-amp slew rate is SR 0.5 V s . If the amplitude of input signal is 0.02
vi
3 k
D1
6 k
D2
2 k
V, then the maximum frequency that may be used is
vo
240 k vi
10 k
Fig. P3.5.32–33 vo
If vi 2 V, then output vo is
Fig. P3.5.29
(A) 4 V
(B) 4 V
(C) 3 V
(D) 3 V
If vi 2 V, then output vo is (A) 0.55 106 rad/s
(B) 0.55 rad/s
(C) 1.1 106 rad/s
(D) 1.1 rad/s
(A) 6 V
(B) 6 V
(C) 3 V
(D) 3 V
vo( t) ? In the circuit of fig. P3.5.30 the input offset voltage and input offset current are V io 4 mV and I io 150 8 mF
nA. The total output offset voltage is 500 k
vi
5u(t) mA
250
vo
50
1 k
5 k vo
Fig. P3.5.34
(A) e
5 k
Fig. P3.5.30
(A) 479 mV
(B) 234 mV
(C) 168 mV
(D) 116 mV
(C) e
t 10
u( t) V
(B) e
t 1 .6
u( t) V
(D) e
t 10
u( t) V
t 1 .6
u( t) V
The circuit shown in fig. P3.5.35 is at steady state before the switch opens at t 0. The voltage vC ( t) for t 0 is
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187
Operational Amplifiers
3.5
v ss
t=0
10 k X R
20 k
v s vo
20 k 20 k + vC
4 F
5 V
Fig. P3.5.38
-
Fig. P3.5.35
(A) v s vss
(B)
v s vss
v s v ss
(D)
v s v ss
(C) (A) 10 (C) 5
5 e12 .5t V
5 e
(B) 5
5 e12 .5t V
t 12 .5
V
(D) 10
5 e
t 12 .5
If the input to the ideal comparator shown in fig.
V
P3.5.39 is a sinusoidal signal of 8 V (peak to peak) without any DC component, then the output of the The LED in the circuit of fig. P3.5.36 will be on if vi
comparator has a duty cycle of
is Input
10 k +10 V
Output
470 10 k
V ref = 2 V
vi
Fig. P3.5.39 Fig. P3.5.36
(A) 10 V
(B)
(C) 5 V
(D)
10 V 5 V
(A)
1 2
(B)
1 3
(C)
1 6
(D)
1 12
In the op-amp circuit given in fig. P3.5.40 the load In the circuit of fig. P3.5.37 the CMRR of the op-amp is 60 dB. The magnitude of the vo is
current i L is R1
2 V
R1 v s
100 k R
R 1 k
R
R
R2
vo
1 k
I L
R2 R L
100 k
Fig. P3.5.40 Fig. P3.5.37
(A) 1 mV
(B) 100 mV
(C) 200 mV
(D) 2 mV
The analog multiplier X of fig. P.3.5.38 has the characteristics v p v1 v2 . The output of this circuit is
(A)
v s R2
(B)
v s R2
(C)
v s R L
(D)
v s R L
1
In the circuit of fig. P3.5.41 output voltage is vo
V for a certain set of , R, an C. The vo will be 2 V if
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3.5
Operational Amplifiers
R1
(A)
R1
(C)
vo
vi = sin t V
188
1 F 2 1 2 6
(B) 2 F
F
(D) 2 6
F
R C
In the circuit shown in fig. P3.5.45 the op-amp is ideal. If F 60, then the total current supplied by the
Fig. P3.5.41
15 V source is
(A) is doubled
(B)
is halved
(C) R is doubled
(D) None of the above
+15 V
47 k
In the filter circuit of fig. P3.5.42. the 3 dB cutoff frequency is 50 nF
6 k vo
3 k
vo
V z = 5
V
100
vi
Fig. P3.5.42
Fig. P3.5.45
(A) 10 kHz
(B) 1.59 kHz
(C) 354 Hz
(D) 689 Hz
(A) 123.1 mA
(B) 98.3 mA
(C) 49.4 mA
(D) 168 mA
The phase shift oscillator of fig. P3.5.43 operate at f 80 kHz. The value of resistance R F is
In the circuit in fig. P3.5.46 both transistor Q1 and Q2 are identical. The output voltage at T 300 K is
R F
100 pF
100 pF
100 pF
R R1 vo
R
R2
v1
v2
R
333 k
Fig. P3.5.43
(A) 148 k
(B) 236 k
20 k
(C) 438 k
(D) 814 k
20 k
The value of C required for sinusoidal oscillation of
vo
333 k
frequency 1 kHz in the circuit of fig. P3.5.44 is 2.1 k
1 k
Fig. P3.5.46
v2 R1 v1 R2
(A) 2 log 10 C 1 k
1 k
Fig. P3.5.44
v2 R1 v1 R2
(C) 2.303 log 10
C
v2 R1 v1 R2
(B) log 10
v2 R1 v1 R2
(D) 4.605 log 10
In the op-amp series regulator circuit of fig. P8.3.47 V z 6.2 V, V BE 0.7 V and 60. The output voltage vo is www.nodia.co.in
189
Operational Amplifiers
vo
+36 V
3.5
Gain of second stage Av2
1 k
Av1 Av2 30,
Total gain Av
150 25
6
vo 30 0.2
6
V
30 k
(B) Let v x be the node voltage v x R 10 k
(B) 24.8 V
(C) 29.8 V
(D) None of the above
vx
0
vo
0
vo
2 100 vx R
0
v x
100
vx R
R vi , 100
2 100 10 R 100 2 R 100 1000 , R 450 k vo vi
(A) 35.8 V
100
0 vi 100
Fig. P3.5.47
vx
(A)
R
0
vi R
0
v1 R
*******
0,
R
v1 vi R
v1
R
Solutions
R
v2
R
R vi vo
(A) This is inverting amplifier R 400 Av F 10 R1 40
Fig. S3.5.6
(A) The noninverting terminal is at ground level. Thus inverting terminal is also at virtual ground. There will not be any current in 60 k. 400 10 Av 40 (B) vo
10 (2 sin 1
t)
v1 0 v1 v2 v1 0, 3v1 R R R v2 v1 v2 v2 vo 0 R R R
3vi vi 3vi 3vi vo
mV 20sin t mV
(A) i1
10 k
vi
i2 io
ii
i L
3vi
8
100 k
100 k
vi
vo
vo vi
v2
vi v1 100 k
i1
1 k
v2 ,
v1
i1
vo
4 k
Fig. S3.5.7 Fig. S3.5.3
i L
vo 4k
5 sin t A
2 sin t i1 ii 1k io
i2
v1 vo , i1 100 k
i2
2 sin t A
iL i1 5 sin t 2 sin t 7sin t A (A) Gain of first stage Av1
50 10
5
, v1
2 v1 vo vi , vo v 2vo v1 o vo Aod Aod vo vi
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1
1 2 Aod
vo vi v1
Aodv1 vi vo
2 (1 2 10 3)
1996 .
3.5
Operational Amplifiers
(B) A closed loop gain ACL
2k 8k 2k
ACL
Aod 1 Aod
4.5
. 15 0.25
(C) i1
vo vi
0.2
45 1 ( 45)(0.2)
mA, i1
6k
i2
i L
vo
5 k
(A) v
vi
, v vi
(B) v
vi
, v vo
10 ki2 2.5
V, i2 io
iL
vo
vo vi
,
2 60
999 1 999
0.999
Av 1. Lower op-amp circuit is inverting amplifier R having gain Av 1. Therefore vo1 vo2 . R
2.67 V
(B) Output of first op-amp vo1
vo ) vo
same. The upper op-amp circuit is buffer having gain
(B) This is summing amplifier
10(1 2 sin t)
1
(B) At second stage input to both op-amp circuit is
2.5 io , io 0.75 mA 5k
0.5 1 80 20 40
Aod ( vi
Aod 999 vo Aod vi 1 Aod
Fig. S3.5.9
vo
let v1 be the node voltage of T network v v v1 0 v1 2 v 2 vi R R v1 v v1 v v 1 o 0 3v1 v vo , R R R vo 5 6vi vi vo vi
8 k io
i1
0.25m
vi v
6 k
vi
vo
(A) v
i2
10 k
190
(A) v
20 vi1 2
mV
6 6 48 6
2 V, 3
vo 1
10 v 10
4 V 3
(A) Applying KVL to loop,
The second stage is summing amplifier
10 (1 2 sin t) 10 mV 1 1 0.4(1 sin t) mV (B) v
vi , vo 500 1
18 40 20 40
vo
R 1 k
17
v
v 30
1
3 4
6
vo v 1
v
10 60
v
3ki1 2 ki1 i1 2 .4 mA , io i1 2.4 i2 i1 2.4 mA vo i2 (1k) 2.4 V vo va io ( 4k) 2.4 (2.4)(4) 12 V
12
15 20
0
11
(A) v1
12
100 20
i2
Fig. S3.5.20
V
100 k v 34 V vo 1 100 k (C)
io
2 k
Aod vi 501
15 20 20 40
4 k
i1
12 V
(2.5)(501) A od (5), Aod 2505 . (A) v
va
3 k
vo 20
11 (1 5) 5.5 V 12
vo 3
8 2,
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vo ( 4) 48
12( 8) , v 48
vo 30 V
2
V, v
v
mA
191
Operational Amplifiers
5 V v
(A) v
v
,
10 k
vo 1 , 5 vo 1 ,
v
v 0,
(D) v
12 4k
v s
v , 2 ki s 4 ki1 2 kis 10 ki2
i2
i s i1
v s
i 2 kis 10 k is s 2
v
0.1 mA
vo 4 V
i1
vo
3 mA
3.5
i s 2 i1
2 kis 10 k( is i1 ),
, v s
v s i s
i1
i s 2
17k Rin
3 k i2
i1
4 k
R F 240 k 24 R1 10 k The maximum output voltage vom 24 0.02 0.48 SR 0.5 / 1.1 10 6 rad/s (C) Closed loop gain
io
12 V
2 mA
i L
vo
6 k
i2
3 2 5
i2 io
(5) (3) 15 V 15 , 5 io , io 7.5 mA
iL
(B)v
(A) The offset due to V io is vo
mA, vo
1
6
2.5 V v
(C) v1
v1 v1
,
vo ( 4) 8
, v2
4
2.5
i
6 3k
2
v2 0
v2 v2
(A) 6
vo
,
6k 6( 6 k) 3k
io
6
vo 3k
18 A.
(B) If v i 0, then v o 0, D1 blocks and D 2 conducts Av
10
vo (1) vo v (2) , v i 1 3 4 2 1 v v 2 vi vo v v , o o 8 , vi 4 3 3 (D) v
io 6
V
vo(1) 21
6k 3k
2
Av
3k 2k
15 . ,
(2)(2) 4
vo
V
( 2)(15 . )3 V
(A) Voltage follower vo v v (0 )
5m(250 ||1000 ) 1 8m(1000 250) 10 s (A) vc (0 )
(B) Since op-amp is ideal
vo
(D) If vi 0, then vo 0, D2 blocks and D1 conduct
V, current through 6 V source
mA, vo 2m( 3k 2 k)
500 4m 404 mV 5
Due to I io, vo
Current through 2 k resistor v v2 v v 1 2 i 1 2k 2k ( v v2 ) vo i( 6 k 2 k 4 k) 1 (12 k) 2k vo 6 Avd v1 v2 (C) v2
R 1 1 V io R1
RF I io (500 k)(150n) 75 mV Total offset voltage vo 404 75 479 mV
vo 7.5 V
v
V, v ( ) 0
5 V vc (0 ) 5
V
For t 0 the equivalent circuit is shown in fig. S3.5.35 20 k i1
+ 10 V
4 k i s
4 F
vC
–
i s
2 k
i2
10 k
Fig. S3.5.28
V
0.48
vom
Fig. S3.5.23
A
Fig. S3.5.35
20 k 4 0.08 vc
10 (5 10) e
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s t 0 .08
10 5 e12 .5t
V for t 0
3.5
Operational Amplifiers
(C) v When v
(10)(10 k) 10 k 10 k
Thus when and R is changed, the transfer function
5 V
5 V, output will be positive and LED will
is unchanged. be
3 k , R2 6 k , C 50 nF vi v v vi v v i o 0 i o R2 1 R1 R2 R2 R1 || sC 1 sR1 C (B) Let R1
on. Hence (C) is correct.
(2)
(B) v
v
1 V,
v (2)
R 2 R
V CM 2 1 CMRR 100 1 CMRR 60 dB 10 3 , vo 1 10 3
V CM
v
R 2 R
(C) v
1,
vo
1 V, vd 0
R F
100
mV
vi R2 R1
vo vi
Let output of analog multiplier be v p . v v s p v s vp , v p vss vo R R v v s vss vo , vo s v ss
output is negative. V
2 V 2
t
5 6
6
v R L
5 6 6 2
v vo R1
v vo R2
v R2
2 v
R v s 2 2 v R L
0
v
v s
R 1 2 1 s( R1 || R2 ) C R1
i L
1 2 (2 k)50n
159 .
( 80 k)(2 6 )(100 )
29
R F
8.12 k
( 8.12 k)(29) 236 k
2 v1
oscillation
v s vo
R2
, v
vo
R 2 2 v R L
R1
v R R
kHz
(A) This is Wien-bridge oscillator. The ratio R2 2.1k 2.1 is greater than 2. So there will be R1 1k
1 3
0
v , R L
jRC 1 jRC
H ( j) 1
1
R2 v R L
R L v s , R2
1 2 ( R1 || R2 ) C
R
R F R
i L
v s R2
, H ( j)
Frequency 1 ( R 2 C) 2 1 ( RC) 2
C
C
Fig. S3.5.44
(D) This is a all pass circuit vo vi
sR1 R2 C vo
1 2 ( 3k ||6 k)50n
Fig. S3.5.39
v s v R1
R1
(B) The oscillation frequency is 1 1 80 k f 2 6 RC 2 6 R(100 )
4 V
(A)
vo vi
f 3dB
R2 R1 sR1 R2 C 1 R1 R1 R2
(B) When v i 2 V, output is positive. When v i 2 V,
R2 R (1 sR1 C) 1 vo 1
vi
0 v ,
T Duty cycle ON T
192
1
C
1 F 2
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1 2 RC
1 10 3
1 2 (1k C )
193
Operational Amplifiers
(C) v
5 V v v E
,
The input current to the op-amp is zero.
iZ iC i Z F iE 15 5 60 5 49.4 47 k 61 100 i15V
(B) vo vo1 vo1
333 ( vo1 20
vo2 )
i i vBE1 V t ln c1 , vo2 vBE 2 V t ln c 2 i s i s i i vo2 V t ln c1 V t ln c 2 ic 2 ic1 v1 , R1
vo1
v R vo2 V t ln 2 1 , R2 v1
ic 2
333 ( vo1 20
v2 R2
ic1
vo
mA
vo2 )
V t 0.0259 V
v R 333 (00259 . ) ln 2 1 20 v1 R2
v R v R 0.4329 ln 2 1 0.4329(2 .3026 ) log10 2 1 v1 R2 v1 R2 v R log 10 2 1 v1 R2 (B) v vo
v ,
v Z
10 vo 10 30
4 vz 6.2 4 24.8
vo 4
V
************
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3.5
