Fundamentals of VLSI Lab viva and interview questions with answers for freshers.
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Fundamentals of VLSI Lab viva and interview questions with answers for freshers.Full description
short doc on vlsi questions. Good for a last minute review. Not my work..Full description
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======================================== VLSI VIVA QUESTIONS by Irfan Sir ========================================
Chp 1: MOSFET-OPERATIONS
1. What are the typical values of threshold voltage for Depletion, Enhancement NMOS & PMOS? 2. What are the differences between NMOS & PMOS? 3. When does channel punch through occur? 4. Is pinch off and punch through the same? If not then what is the difference? 5. Draw and show the energy band changes in channel region? 6. What is the meaning of surface inversion and strong surface inversion? 7. What are the different parasitic effects present in the MOSFET? 8. What is the significance of Fermi level and intrinsic Fermi level? 9. What is work function and Electron affinity? 10. Which voltage is more: flat band or threshold? 11. What are the different factors influencing the threshold voltage? 12. What is the difference between MOSFET & BJT? 13. When we have BJT, why do we need MOSFET in digital circuits for switching? 14. What is the difference between BJT saturation and MOS saturation? 15. If Drain region is heavily doped and source is lightly doped, then what will be the change in the operation of MOSFET? 16. What is the significance of junction capacitance; overlap capacitance? 17. How can mobility variation cause threshold voltage variation? 18. What is substrate biasing or body effect coefficient? What is the importance of this factor in designing? 19. In operation, do we apply any substrate biasing? 20. Can we fabricate PMOS with N type Gate and substrate? 21. Which transistor performance is better: PMOS or NMOS? 22. Mobility of holes is less than mobility of electrons. How does it
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matter in MOSFET designing or operation? 23. Which transistor enters in early saturation: Enhancement PMOS, Depletion PMOS? 24. If VDS =VGS – VTH, VGS>VTH then MOS is in linear or saturation? 25. What is the use of channel length modulation? What does it exactly mean? 26. Which MOSFET is preferred: small channel length or large channel length? 27. MOSFET is current controlled or voltage controlled? 28. Which voltage controls the channel Resistance? 29. What is channel Resistance & ON Resistance? What are the formulae to calculate them? 30. What is the relation for threshold voltage of Depletion MOSFET? 31. When channel is pinch off in saturation how does the current flow in MOSFET?
Chp 2: MOS – INVERTER
1. Compare the different loads in MOS inverter? 2. If we have PMOS driver and NMOS load then how does it work? 3. Can u connect PMOS depletion pull up? How does it work? 4. What is the significance of i) Aspect Ratio, ii) Inverter Ratio, iii) β iv) Threshold Voltage of inverter? 5. Which parameter is important in MOS circuit designing i) Power Dissipation, ii) Noise Margin 6. What is the relation between aspect ratios of pull up and pull down if we require equal rise and fall time? 7. What are the suitable aspect ratios for NMOS, CMOS – NAND, NOR Inverter? 8. How will you increase noise margin? 9. What is figure of Merit? 10. Is the rise time, fall time of NAND- NOR Gate same or different? 11. As the switching speed increases, CMOS power dissipation increases, then what is the advantage of CMOS circuits? 12. What is the difference between Power Consumption & Power Dissipation?
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13. What will be the effect of transistor sizing on device operation (Current, Voltage, etc.)? 14. What is Reference Inverter? What is the use of it? 15. What will be the effect of i) Symmetrical Inverter, ii) Identical Transistors in circuit operation? 16. What is the difference between Saturated load and Linear load MOS Inverter? 17. How do you scale Reference Inverter? 18. What are the steps / parameters for designing of Inverter? 19. Which Gate is faster NAND or NOR? 20. How do we decide the different region of operation of transistor related to voltages, e.g. for VOH why is the driver in cutoff ? 21. When one inverter is driving the other inverter, what is the impact on sizing of transistors?
Chp 3: MOS –LAYOUT FABRICATION
1. What is the meaning of MASK? 2. What are the different types of Isolation? 3. Which method of crystal Growth is advantageous and why? 4. What is the importance of diffusion profile? 5. What is metallization? 6. What are the different types of contacts? Which one is better? 7. Compare Ohmic Contact with rectifying contact? 8. What is the importance of photolithography? 9. Name the softwares used in IC Fabrication? 10. What are the different types of lithography? 11. What is channel stop and Guard Rings in CMOS Fabrication? 12. What is the main advantage of twin-tub process? 13. What is the advantage of epitaxial growth over diffusion? 14. When are butting and buried contacts used? 15. How many MASK are required for fabrication of NMOS and CMOS?
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16. What is the significance of stick diagrams? 17. What is the need of design Rules? 18. What are the rules for depletion transistor, Butting contact and buried contact? 19. What is the significance of demarcation line? 20. What is the difference between micron rules and lambda based design Rule? 21. What is the minimum feature size? How it is decided? 22. What is the difference in area of Gate of NAND and NOR Gate? 23. What are the physical limitations of design Rule? 24. How we can increase integration density? 25. What is the maximum number of Metal levels used in fabrication for interconnection? 26. What is planner technology and what does monolithic, Hybrid IC mean? 27. What is the difference between CMOS & NMOS design rules? 28. What are the rules for Nwell or Pwell? 29. Name the different EDA tools used for VLSI Design? 30. What does the micron technology or nanotechnology means? 31. How to draw the optimum layout? 32. How we calculate the area of GATE and area of Transistor? 33. What is the impact of scaling on the area of layout? 34. Which scaling is preferable? 35. What are the limitations of Scaling? 36. If capacitance is scaled then what will be impact on VTH? 37. Draw the stick Diagram for Half Adder using EX-OR Gate. Use minimum number of transistors. 38. What is the advantage of Pass transistor logic? 39. What is CPL? 40. Compare Transmission Gate with Pass transistor Logic? 41. How will you Fabricate 4:1 MUX? 42. What are the advantages of double Metal Process rules? 43. What is the use of VIA?
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44. What is latchup? How is CMOS protected from latchup? 45. How do we show substrate contact in fabrication cross sectional view? 46. Draw the stick diagram of 2:1 MUX using pass transistor logic? 47. Why PMOS gives strong 1 and NMOS gives strong '0'? 48. What are the different ways of adding impurities? 49. What is the use of VHDL in VLSI design? 50. What are the different testing methods? 51. What is controllability and observability? 52. What are the Basics of VLSI? 53. What is gate area? What is the significance of this area? 54. What are the CAD tools used in VLSI Design?
Chp 4: SCALING
1. What is the importance of scaling? 2. What are the types of scaling? Why are they called so? 3. When does the short channel effect take place? 4. When does the narrow channel effect take place? 5. Which type of scaling is preferred and why? 6. What are the limitations on scaling? How can we overcome them?
