DESIGN OF SEQUENCE DETECTOR
Ex No: Date: AIM:
Designing, synthesising and implementing a sequence detector for the given sequence using verilog and VHDL. The given sequence is “11010”. HARDWARE REQUIRED: Spartan 3E. SOFTWARE REQUIRED: Xilinx 13.1 ISE. ALGORITHM: Step 1: Start the program. Step 2: Declare the input, clk, reset. Step 3: Declare the output as y. Step 4: Draw the state diagram whose initial state is reset. Step 5: If the input matches with a given sequence the present state transits to the next state. Step 6: If the input does not match with a given sequence the state will be in present state or move to the reset state as per the condition given. Step 7: The output is always remains “0” until the whole sequence is received. Step 8: When the sequence is fully received the output changes from “0” to “1”. THEORY: A sequence detector is the one which detects the next state when the reset value is given. The transition takes place from the present state to the next state when the value is given or else the present state will be the same state. It can be described using state diagrams. Each state is used to represent the present state or the next state. The five bit sequence 11010 can be detected using this state diagram if reset is given then it goes to the next state s1and attains the value 1or else it stays in the same state s0. STATE DIAGRAM:
STATE TABLE:
PRESENT STATE
NEXT STATE
OUTPUT (Y)
X=0
X=1
X=0
X=1
S0
S0
S1
0
0
S1
S0
S2
0
0
S2
S3
S2
0
0
S3
S0
S4
0
0
S4
S5
S0
1
0
S5
S0
S1
0
0
PROGRAM:
a)Verilog codemodule me1(x,clk,rst,y); input x,clk,rst; output y; reg[2:0]state; reg y; always @ (posedge clk) begin if(rst==1)begin state<=3'b000; y<=0; end else begin case (state) 3'b000:begin if (x) begin state<=3'b001; y<=0; end else begin state<=3'b000; y<=0; end end 3'b001:begin if (x) begin state<=3'b010; y<=0; end
else begin state<=3'b000; y<=0; end end 3'b010:begin if (x) begin state<=3'b010; y<=0; end else begin state<=3'b011; y<=0; end end 3'b011:begin if (x) begin state<=3'b100; y<=0; end else begin state<=3'b000; y<=0; end end 3'b100:begin if (x) begin state<=3'b000; y<=0;
end else begin state<=3'b101; y<=1; end end 3'b101:begin if (x) begin state<=3'b001; y<=0; end else begin state<=3'b000; y<=0; end end endcase end end endmodule
b) VHDL code:-
Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_unsigned.ALL; Entity fsm is Port ( x,clk,reset : in STD_LOGIC; z : out STD_LOGIC); end fsm; Architecture Behavioral of fsm is type state_type is (s0,s1,s2,s3,s4,s5); signal state,nextstate: state_type; signal count: std_logic_vector(2 downto 0); begin jump_process:process(state,x) begin case state is when s0=> if x='1' then nextstate<=s1;z<='0'; else nextstate<=s0;z<='0'; end if; when s1=> if x='1' then nextstate<=s2;z<='0'; else nextstate<=s0;z<='0'; end if; when s2=> if x='1' then nextstate<=s2;z<='0'; else nextstate<=s3;z<='0';end if; when s3=> if x='1' then nextstate<=s4;z<='0'; else nextstate<=s0;z<='0';end if; when s4=> if x='1' then nextstate<=s2;z<='0'; else nextstate<=s5; z<='1';end if; when s5=> if x='1' then nextstate<=s1;z<='0'; else nextstate<=s0; z<='0';end if; end case; end process; seq_process :process(clk,reset) begin if reset='1' then state<=s0; elseif(rising_edge(clk)) then state<=nextstate; end if; end if; end process; end Behavioral;
TEST BENCH FOR VHDL PROGRAM: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY try IS END try; ARCHITECTURE behavior OF try IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fsm PORT( x : IN std_logic; clk : IN std_logic; reset : IN std_logic; z : OUT std_logic ); END COMPONENT; --Inputs signal x : std_logic := '0'; signal clk : std_logic := '0'; signal reset : std_logic := '0'; --Outputs signal z : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fsm PORT MAP ( x => x, clk => clk, reset => reset, z => z ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; reset <= '1', '0' after 10 ns;
x <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 50 ns,'0' after 60 ns; -- Stimulus process --stim_proc: process --begin -- hold reset state for 100 ns. -- wait for 100 ns; -- wait for clk_period*10; -- insert stimulus here -- wait; --end process; END; UCF FILE: # Plan Ahead Generated physical constraints NET "clk" LOC = P178; NET "reset" LOC = P106; NET "x" LOC = P107; DEVICE UTILIZATION SUMMARY: Selected Device: 3s250epq208-4 Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of IOs Number of bonded IOBs Number of GCLKs
: 3 out of 2448 0% : 3 out of 4896 0% : 5 out of 4896 0% :4 : 4 out of 158 2% : 1 out of 24 4%
TIMING SUMMARY: Speed Grade: -4 Minimum period: 2.225ns (Maximum Frequency: 449.438MHz) Minimum input arrival time before clock: 2.992ns Maximum output required time after clock: 5.749ns Maximum combinational path delay: 6.280ns
OUTPUT WAVEFORM: Verilog:
VHDL:
RESULT: Thus a sequence detector for the sequence “11010” is detected, simulated and implemented using verilog and VHDL.
