K. S. SCHOOL OF ENGINEERING & MANAGEMENT # 15, Mallasandra, Off Kanakapura Road, Bangalore-560062, Bangalore-560062, Karnataka, India.
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
HDL Lab Manual Sub Code: 10ECL48 Sem : IV Prepared By Mr. Manu D. K., Asst. Professor
Mrs. Shalini Shravan, Asst. Professor Mr. Ravikiran B. A., Asst. Professor Ms. Devika N., Asst. Professor
CONTENTS
PART A:
PROGR PROGRAM AM M I NG (using (using VH DL and Veri Veri log)
1. Write HDL code to realize all the logic gates ................................................................. ....................................................................................... ...................... 1 2. Write a HDL program for the following combinational designs ..................................................... ..........................................................3 a. 2 to 4 decoder ................................................................. ................................................................................................. .................................................................. .................................. 3 b. 8 to 3 (encoder without priority & with priority) ................................................................. ......................................................................... ........ ..5 c. 8 to 1 multiplexer ................................................................. .................................................................................................. ........................................................... .......................... 9 d. 4 bit binary to gray converter .............................................................. .............................................................................................. .......................................... .......... 11 e. De-multiplexer, comparator
............................................................... ............................................................................................... ...................................... ...... 1 4
3. Write a HDL code to describe the functions of a Full Adder Using 3 modeling st yles................. a. Full Adder Data Flow Description
....18
.................................................................. ................................................................................................ .............................. 18
b.
Full Adder Behavioral Description ............................................................... ............................................................................................... ................................ 19
c.
Full Adder Structural Description ................................................................. ................................................................................................. ................................ 21
4. Write
a
model
for
32
bit
ALU
using
the
schematic
diagram
shown below A (31:0) B (31:0) ............................................................... ............................................................................................... .......................................... .......... 24
ALU should use combinational logic to calculate an output based on the four-bit op-code input.
ALU should pass the result to the out bus when enable line in high, and tri -state the out bus when the enable line is low.
ALU should decode the 4 bit op-code according to the given in example below:
OPCODE
ALU OPERATION OPERATION
1.
A+B
2.
A – A – B B
3.
A Complement
4.
A AND B
5.
A OR B
6.
A NAND B
7.
A XOR B
OPCODE ALU OPERATION ENABLE
a. SR Flip Flop .................................................................. .................................................................................................. ................................................................ ................................ 26 b. JK Flip Flop .................................................................. .................................................................................................. ................................................................ ................................ 2 8 c. D Flip Flop .............................................................. ............................................................................................... ................................................................. ..................................... ..... 30 d. T Flip Flop .............................................................. ............................................................................................... ................................................................. ..................................... ..... 6. Design
4
bit
binary,
BCD
counters
(Synchronous
reset
and
Asynchronous
32
reset)
and “any sequence” counters .............................................................. ............................................................................................... ............................................ ........... .....34 a. Binary Synchronous Reset 4bit Counter ............................................................. ....................................................................................... .......................... 34 b. Binary Asynchronous Reset 4bit Counter ................................................................................. ..................................................................................... .... 35 c. BCD Synchronous Reset 4bit Counter ............................................................... ......................................................................................... .......................... 37 d. BCD Asynchronous Reset 4bit Counter ............................................................. ....................................................................................... .......................... 39 e. Binary Any Sequence up down 4bit Counter Counter ............................................................... ............................................................................... ................ 41
PART B:
I NT ERF ACI NG (at leas leastt four of the fol lowin g must must be cove covered red usin usin g VH DL /Veri /Veri log) 1.
Write HDL code to control speed, direction of DC and Stepper motor ......................................... ....43 a. Stepper Motor ............................................................... .................................................................................................. ................................................................ ............................. 43 b. DC Motor ................................................................. ................................................................................................. ................................................................. ..................................... .... 46
2.
Write HDL code to control external lights using relays. ................................................................. ..................................................................... .... 50
3.
Write
a
HDL
code
to
generate
different
waveforms
(Sine,
Square,
Triangle,
Ramp etc.,). Using DAC, change the frequency and amplitude ................................................... ........................................................52 a. Sine Wave ................................................................. ................................................................................................. .................................................................. .................................... .. 52 b. Square Wave ................................................................. ................................................................................................. ................................................................ ................................ 56 c. Triangle Wave .............................................................. ............................................................................................... ................................................................. ................................ 58 d. Positive Ramp .............................................................. ............................................................................................... ................................................................. ................................ 60
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EXPERIMENT EXPERIMENT 1 ALL LOGIC GATES
not_op and_op nand_op
a_in inputs
ALL LOGIC GATES
outputs
or_op nor_op xor_op xnor_op
b_in Figure 1: Block Diagram of All Logic Gates
not_op a_in b_in
and_op
nand_op
or_op nor_op xor_op xnor_op
Logic Diagram Diagram of All Gates
Inputs a_in b_in
Outputs not_op and_op (a_in) 1 0
nand_op
or_op
nor_op
xor_op
xnor_op
1
0
1
0
1
0
0
0
1
1
0
1
1
0
1
0
1
0
0
0
1
1
0
1
0
1
1
0
1
0
1
0
0
1
Truth Table 1: All Logic Gates VHDL File Name: AlllogicGates.vhd
-- All Logic Gates - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;;
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entity AllLogicGates is port ( a_in : in STD_LOGIC; b_in : in STD_LOGIC; not_op : out STD_LOGIC; and_op : out STD_LOGIC; nand_op : out STD_LOGIC; or_op : out STD_LOGIC; nor_op : out STD_LOGIC; xor_op : out STD_LOGIC; xnor_op : out STD_LOGIC); end AllLogicGates; architecture DataFlow of AllLogicGates is begin not_op <= not a_in; and_op <= a_in and b_in; b_in; nand_op <= a_in nand b_in; or_op <= a_in or b_in; nor_op <= a_in nor b_in; xor_op <= a_in xor b_in; b_in; xnor_op <= a_in xnor b_in; end DataFlow;
Verilog File Name: AlllogicGates.v
// All Logic Gates module AllLogicGates( a_in, b_in, not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op ); input a_in, b_in; output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op; wire a_in, b_in; reg not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op; always @ (a_in, b_in) begin not_op = ~(a_in); and_op = a_in & b_in; b_in; nand_op = ~(a_in & b_in); or_op = a_in | b_in; nor_op = ~(a_in | b_in); xor_op = a_in ^ b_in; b_in; xnor_op = ~(a_in ^ b_in); end endmodule
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EXPERIMENT EXPERIMENT 2 COMBINATORIAL COMBINATORIAL DESIGNS A. 2-to-4 Decoder
d_in
2 inputs
Decoder 2 to 4
4
d_op
outputs en Figure 2: Block Diagram of Decoder 2 to 4
Inputs
Outputs
en
d_in(1)
d_in(0)
d_op(3)
d_op(2)
d_op(1)
d_op(0)
1
X
X
Z
Z
Z
Z
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
Truth Table 2 : 2-to-4 Decoder VHDL File Name: decoder2to4.vhd
-- decoder2to4 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity decoder2to4 is Port ( d_in : in i n STD_LOGIC_VECTOR (1 downto 0); en : in STD_LOGIC; d_op : out STD_LOGIC_VECTOR (3 downto 0)); end decoder2to4; architecture Behavioral of decoder2to4 is begin process(en,d_in) begin if(en/='0')then -- Active Low Enabled d_op<="ZZZZ"; else case d_in is
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when "00" => d_op <= "0001"; when "01" => d_op <= "0010"; when "10" => d_op <= "0100"; when "11" => d_op <= "1000"; when others => d_op <= "ZZZZ"; end case; end if; end process; end Behavioral; Verilog File Name: decoder2to4.v
// decoder2to4 module decoder2to4( d_in, en, d_op ); input [1:0] d_in; input en; output [3:0] d_op; wire en; wire [1:0] d_in; reg [3:0] d_op; always @ (en, d_in) begin if(en) // Active Low Enabled d_op = 4'bZZZZ; else begin case (d_in) 2'b00 : d_op = 4'b0001; 2'b01 : d_op = 4'b0010; 2'b10 : d_op = 4'b0100; 2'b11 : d_op = 4'b1000; default : d_op = 4'bZZZZ; endcase end end endmodule
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B. 8-to-3 Encoder (Without Priority)
a_in
8 Encoder Without Priority
inputs
3
y_op
outputs
en Figure 3: Block Diagram of Encoder Without Priority Inputs
Outputs
en
a_in(7)
a_in(6)
a_in(5)
a_in(4)
a_in(3)
a_in(2)
a_in(1)
a_in(0)
y_op (2)
y_op (1)
y_op (0)
1
X
X
X
X
X
X
X
X
Z
Z
Z
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
1
1
Truth Table 3: Encoder Without Priority VHDL File Name: encd_wo_prior.vhd
-- encoder without priority - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity encd_wo_prior is Port ( en : in STD_LOGIC; a_in : in STD_LOGIC_VECTOR (7 downto 0);
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y_op : out STD_LOGIC_VECTOR (2 downto 0)); end encd_wo_prior; architecture Behavioral of encd_wo_prior is begin process (en,a_in) begin if(en /= '0') then -- Active Acti ve Low Enabled y_op <= "ZZZ"; else case a_in is when "00000001" => y_op <= "000"; when "00000010" => y_op <= "001"; when "00000100" => y_op <= "010"; when "00001000" => y_op <= "011"; when "00010000" => y_op <= "100"; when "00100000" => y_op <= "101"; when "01000000" => y_op <= "110"; when "10000000" => y_op <= "111"; when others => y_op <= "ZZZ"; end case; end if; end process; end Behavioral;
Verilog File Name: encd_wo_prior.v
// encoder without priority module encd_wo_prior( en, a_in, y_op ); input en; input [7:0] a_in; output [2:0] y_op; wire en; wire [7:0] a_in; reg [2:0] y_op; always @ (a_in, en) begin if(en) //Active Low Enabled y_op = 3'bZZZ; else begin case (a_in) 8'b00000001 : y_op = 3'b000; 8'b00000010 : y_op = 3'b001; 8'b00000100 : y_op = 3'b010; 8'b00001000 : y_op = 3'b011;
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8'b00010000 : y_op = 3'b100; 8'b00100000 : y_op = 3'b101; 8'b01000000 : y_op = 3'b110; 8'b10000000 : y_op = 3'b111; default : y_op = 3'bZZZ; endcase end end endmodule
8-to-3 Encoder (With Priority)
a_in
8 3
Encoder With Priority
inputs
y_op
outputs
en Figure 4: Block Diagram of Encoder With Priority
Inputs
Outputs a_in(2)
a_in(1 )
a_in (0)
y_op (2)
y_op (1)
y_o p (0)
X
X
X
X
Z
Z
Z
X
X
X
X
X
1
1
1
X
X
X
X
X
X
1
1
0
0
1
X
X
X
X
X
1
0
1
0
0
0
1
X
X
X
X
1
0
0
0
0
0
0
0
1
X
X
X
0
1
1
0
0
0
0
0
0
1
X
X
0
1
0
0
0
0
0
0
0
0
1
X
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
en
a_in(7 )
a_in(6 )
a_in(5 )
a_in(4 )
a_in(3 )
1
X
X
X
X
0
1
X
X
0
0
1
0
0
0
Truth Table 4: Encoder With Priority
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VHDL File Name: encd_w_prior.vhd
-- encd_w_prior - Dataflow library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity encd_w_prior is Port ( en : in STD_LOGIC; a_in : in STD_LOGIC_VECTOR (7 downto 0); y_op : out STD_LOGIC_VECTOR (2 downto 0)); end encd_w_prior; architecture Dataflow of encd_w_prior is begin y_op <=
"ZZZ" when en = '1' else -- Active Low Enabled "111" when a_in(7)='1' else "110" when a_in(6)='1' else "101" when a_in(5)='1' else "100" when a_in(4)='1' else "011" when a_in(3)='1' else "010" when a_in(2)='1' else "001" when a_in(1)='1' else "000" when a_in(0)='1' else "ZZZ";
end Dataflow;
Verilog File Name: encd_w_prior.v
// encoder with priority module encd_w_prior( en, a_in, y_op ); input en; input [7:0] a_in; output [2:0] y_op; wire en; wire [7:0] a_in; reg [2:0] y_op; always @ (a_in, en) begin if (en == 1'b1) // Active Low Enabled y_op = 3'bZZZ; else begin if(a_in[7] == 1'b1) y_op = 3'b111; else if(a_in[6] == 1'b1) y_op = 3'b110; else if(a_in[5] == 1'b1) y_op = 3'b101;
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else if(a_in[4] == 1'b1) y_op = 3'b100; else if(a_in[3] == 1'b1) y_op = 3'b011; else if(a_in[2] == 1'b1) y_op = 3'b010; else if(a_in[1] == 1'b1) y_op = 3'b001; else if(a_in[0] == 1'b1) y_op = 3'b000; else y_op = 3'bZZZ; end end endmodule
C. Multiplexer 8 to 1
8
i_in
inputs
y_out
Multiplexer 8 to 1 output
en 3
sel
Figure 5: Block Diagram of Multiplexer 8 to 1 Inputs
Output
en
sel (2)
sel (1)
sel (0)
i_in (7)
i_in (6)
i_in (5)
i_in (4)
i_in (3)
i_in (2)
i_in (1)
i_in (0)
y_out
1
X
X
X
X
X
X
X
X
X
X
X
Z
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
1
Truth Table 5: Mux 8 to 1
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HDL Laboratory (10ECL48)
VHDL File Name: mux8to1.vhd
--mux8to1 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity mux8to1 is Port ( en : in STD_LOGIC; sel : in STD_LOGIC_VECTOR STD_LOGIC_VECTOR (2 downto 0); i_in : in STD_LOGIC_VECTOR (7 downto 0); y_out : out STD_LOGIC); end mux8to1; architecture Behavioral of mux8to1 is begin process(en,sel,i_in) begin if( en /= '0') then -- Active Low Enabled y_out <= 'Z'; else case sel is when "000" => y_out <= i_in(0); when "001" => y_out <= i_in(1); when "010" => y_out <= i_in(2); when "011" => y_out <= i_in(3); when "100" => y_out <= i_in(4); when "101" => y_out <= i_in(5); when "110" => y_out <= i_in(6); when "111" => y_out <= i_in(7); when others => y_out <= 'Z'; end case; end if; end process; end Behavioral;
Verilog File Name: mux8to1.v
// Multiplexer 8 to 1 module mux8to1(en,i_in,sel,y_out); input en; input [2:0] sel; input [7:0] i_in; output y_out; wire en; wire [7:0] i_in; wire [2:0] sel;
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reg y_out; always@(en,sel,i_in) begin if(en != 0) // Active Low Enabled y_out = 1'bZ; else begin case(sel) 3'b000: y_out = i_in[0]; 3'b001: y_out = i_in[1]; 3'b010: y_out = i_in[2]; 3'b011: y_out = i_in[3]; 3'b100: y_out = i_in[4]; 3'b101: y_out = i_in[5]; 3'b110: y_out = i_in[6]; 3'b111: y_out = i_in[7]; default: y_out = 1'bZ; endcase end end endmodule D. 4-Bit Binary to Gray Converter
b_in
inputs 4
Binary to Gray Converter
4
g_op
outputs
Figure 6: Block Diagram of Binary to Gray Converter b_in(0) b_in(1) b_in(2) b_in(3)
g_op(0) g_op(1) g_op(2) g_op(3)
Logic Diagram of 4bits Binary Binary to Gray Converter
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HDL Laboratory (10ECL48)
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Boolean Expressions g_op(3) = b_in(3) g_op(2) = b_in(3) ⨁ b_in(2) g_op(1) = b_in(2) ⨁ b_in(1) g_op(0) = b_in(1) ⨁ b_in(0) Inputs Decimal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Outputs
Binary
Gray
b_in(3) 0
b_in(2) 0
b_in(1) 0
b_in(0) 0
g_op(3) 0
g_op(2) 0
g_op(1) 0
g_op(0) 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
Truth Table 6: Binary to Gray
HDL Laboratory (10ECL48)
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VHDL File Name: bin_to_gray_4bit.vhd
-- Binary to Gray 4 bit converter - Dataflow library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity bin_to_gray_4bit is Port ( b_in : in i n STD_LOGIC_VECTOR (3 downto 0); g_op : out STD_LOGIC_VECTOR (3 downto 0)); end bin_to_gray_4bit; architecture Dataflow of bin_to_gray_4bit is begin g_op(3) <= b_in(3); g_op(2) <= b_in(3) xor b_in(2); g_op(1) <= b_in(2) xor b_in(1); g_op(0) <= b_in(1) xor b_in(0); end Dataflow;
Verilog File Name: bin_to_gray_4bit.v
// Binary to Gray 4bit Converter module bin_to_gray_4bit( b_in, g_op ); input [3:0] b_in; output [3:0] g_op; wire [3:0] b_in; reg [3:0] g_op; always @ (b_in) begin g_op[3] = b_in[3]; g_op[2] = b_in[3] ^ b_in[2]; g_op[1] = b_in[2] ^ b_in[1]; g_op[0] = b_in[1] ^ b_in[0]; end endmodule
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Demultiplexer 1 to 4
en inputs 2
sel
4
Demultiplexer 1 to 4
y_out
outputs
a_in
Figure 7: Block Diagram of Demultiplexer 1 to 4
Inputs
Outputs
en 1 0
sel (1) X 0
sel (0) X 0
a_in X 1
y_out (3) Z 0
y_out (2) Z 0
y_out (1) Z 0
y_out (0) Z 1
0 0 0
0 1 1
1 0 1
1 1 1
0 0 1
0 1 0
1 0 0
0 0 0
Truth Table 7: Demux 1 to 4 VHDL File Name: demux1to4.vhd
-- Demux1to4 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1to4 is Port ( en
: in STD_LOGIC; sel : in STD_LOGIC_VECTOR(1 STD_LOGIC_VECTOR(1 downto 0); a_in : in STD_LOGIC; y_out : out STD_LOGIC_VECTOR (3 downto 0));
end demux1to4; architecture Behavioral of demux1to4 is begin process(en,sel,a_in) begin if(en /= '0') then -- Active Acti ve Low Enabled y_out <= "ZZZZ"; else y_out <= "0000"; case sel is when "00" => y_out(0) <= a_in;
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HDL Laboratory (10ECL48)
when "01" => y_out(1) <= a_in; when "10" => y_out(2) <= a_in; when "11" => y_out(3) <= a_in; when others => y_out <= "ZZZZ"; end case; end if; end process; end Behavioral; Verilog File Name: demux1to4.v
// Demultiplexer 1 to 4 module demux1to4(en,sel,a_in,y_out); input en; input [1:0] sel; input a_in; output [3:0] y_out; wire en; wire [1:0] sel; wire a_in; reg [3:0] y_out; always@(en,sel,a_in) begin if(en != 0) // Active Low Enabled y_out = 4'bZZZZ; else begin y_out = 4'b0000; case(sel) 2'b00 : y_out[0] = a_in; 2'b01 : y_out[1] = a_in; 2'b10 : y_out[2] = a_in; 2'b11 : y_out[3] = a_in; default : y_out = 4'bZZZZ; 4 'bZZZZ; endcase end end endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
F.
KSSEM, Bangalore
4-Bit Comparator a_in
b_in
4
g_op outputs
Comparator 4bit
inputs 4
L_op e_op
Figure 8: Block Diagram of Comparator 4bit
Outputs
Inputs
a_in > b_in a_in = b_in a_in < b_in
a_in
b_in
g_op
e_op
L_op
----
----
Z
Z
Z
1100 0011
1
0
0
0110 0110
0
1
0
1000 1110
0
0
1
Truth Table 8: Comparator 4Bits VHDL File Name: comparator4bit.vhd
--Comparator4bit - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity comparator4bit is Port ( a_in : in STD_LOGIC_VECTOR STD_LOGIC_VECTOR (3 downto 0); b_in : in STD_LOGIC_VECTOR STD_LOGIC_VECTOR (3 downto downto 0); g_op : out STD_LOGIC; e_op : out STD_LOGIC; L_op : out STD_LOGIC); end comparator4bit; architecture Behavioral of comparator4bit is begin process(a_in,b_in) begin if( a_in > b_in) then g_op <= '1'; e_op <= '0'; L_op <= '0'; elsif(a_in = b_in) then g_op <= '0';
HDL Laboratory (10ECL48)
4 t Sem
e_op <= '1'; L_op <= '0'; elsif(a_in < b_in) then g_op <= '0'; e_op <= '0'; L_op <= '1'; else g_op <= 'Z'; e_op <= 'Z'; L_op <= 'Z'; end if; end process; end Behavioral; Verilog File Name: comparator4bit.v
// Comparator 4bit module comparator4bit( a_in,b_in,g_op,L_op,e_op); a_in,b_in,g_op,L_op,e_op); input [3:0] a_in,b_in; output g_op,L_op,e_op; g_op,L_op,e_op; wire [3:0] a_in,b_in; reg g_op,L_op,e_op; g_op,L_op,e_op; always@(a_in,b_in) if( a_in > b_in) begin g_op = 1; L_op = 0; e_op = 0; end else if( a_in < b_in) begin g_op = 0; L_op = 1; e_op = 0; end else if( a_in == b_in) begin g_op = 0; L_op = 0; e_op = 1; end else begin g_op = 1'bZ; L_op = 1'bZ; e_op = 1'bZ; end endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
EXPERIMENT EXPERIMENT 3 FULL ADDER
a_in b_in
sum Full Adder
inputs
outputs
c_in
carry
Figure 9: Block Diagram of Full Adder
a_in b_in
S1 x1
sum
x2
a2 S3 o1
a1 S2 c_in
Logic Diagram of Full Adder
Inputs
Outputs
a_in b_in c_in sum carry
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Truth Table 9: Full Adder
carry
HDL Laboratory (10ECL48)
4 t Sem
A. Full Adder Data Flow Description VHDL File Name: FullAdder_DF.vhd
-- FullAdder_DF - Data_Flow library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity FullAdder_DF is Port ( a_in, b_in, c_in : in STD_LOGIC; sum, carry : out STD_LOGIC); end FullAdder_DF; architecture Data_Flow of FullAdder_DF is begin sum <= a_in xor b_in xor c_in; carry <= (a_in and b_in) or (b_in and c_in) or (a_in and c_in); end Data_Flow;
Verilog File Name: FullAdder_DF.v
// FullAdder - Data Flow Model module FullAdder_DF( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry; assign sum = a_in ^ b_in ^ c_in; assign carry = (a_in & b_in) | (b_in & c_in) | (c_in & a_in); endmodule
B. Full Adder Behavioral Description VHDL File Name: FullAdder_Behav.vhd
-- Full Adder - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity FullAdder_Behav is Port ( a_in, b_in, c_in : in STD_LOGIC; sum, carry : out STD_LOGIC);
KSSEM, Bangalore
HDL Laboratory (10ECL48)
4 t Sem
end FullAdder_Behav; architecture Behavioral of FullAdder_Behav is begin process ( a_in, b_in, c_in) begin if(a_in='0' and b_in='0' and c_in = '0') then sum <= '0';carry <= '0'; elsif (( a_in='0' and b_in='0' and c_in = '1') or (a_in='0' and b_in='1' and c_in = '0') or (a_in='1' and b_in='0' and c_in = '0')) then sum <= '1';carry <= '0'; elsif (( a_in='0' and b_in='1' and c_in = '1') or (a_in='1' and b_in='0' and c_in = '1') or (a_in='1' and b_in='1' and c_in = '0')) then sum <= '0';carry <= '1'; elsif(a_in='1' and b_in='1' and c_in = '1') then sum <= '1';carry <= '1'; end if; end process; end Behavioral;
Verilog File Name: FullAdder_Behav.v
//FullAdder - Behavioral Model module FullAdder_Behav( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry; wire a_in, b_in, c_in; reg sum, carry; always @ ( a_in, b_in, c_in) begin if(a_in==0 & b_in==0 & c_in==0) begin sum = 0; carry = 0; end else if (( a_in==0 & b_in==0 & c_in == 1) | (a_in==0 & b_in==1 & c_in == 0) | (a_in==1 & b_in==0 & c_in == 0)) begin sum = 1; carry = 0; end
KSSEM, Bangalore
HDL Laboratory (10ECL48)
4 t Sem
else if (( a_in==0 & b_in==1 & c_in == 1) | (a_in==1 & b_in==0 & c_in == 1) | (a_in==1 & b_in==1 & c_in == 0)) begin sum = 0; carry = 1; end else if(a_in==1 & b_in==1 & c_in == 1) begin sum = 1; carry = 1; end end endmodule
C. Full Adder Structural Structural Description VHDL File Name: full_adder_struct.vhd
-- Full Adder - Structural library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity full_adder is port ( a_in, b_in, c_in : in STD_LOGIC; sum,carry : out STD_LOGIC); end full_adder; architecture structural of full_adder is component xor2_1 port( a, b : in STD_LOGIC; STD_LOGIC; y : out STD_LOGIC); end component; component and2_1 port( a, b : in STD_LOGIC; STD_LOGIC; y : out STD_LOGIC); end component; component or2_1 port( a, b : in STD_LOGIC; STD_LOGIC; y : out STD_LOGIC); end component; signal s1,s2,s3: STD_LOGIC; begin x1: xor2_1 port map (a_in, b_in, s1); a1: and2_1 port map (a_in, b_in, s2);
KSSEM, Bangalore
HDL Laboratory (10ECL48)
4 t Sem
x2: xor2_1 port map (s1, c_in, sum); a2: and2_1 port map (s1, c_in, s3); o1: or2_1 or2_1 port map (s2, s3, carry); end structural; VHDL File Name: xor2_1.vhd
-- xor2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity xor2_1 is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC); end xor2_1; architecture data_flow of xor2_1 is begin y <= a xor b; end data_flow; VHDL File Name: and2_1.vhd
-- and2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity and2_1 is port ( a, b : in STD_LOGIC; STD_LOGIC; y : out STD_LOGIC); end and2_1; architecture data_flow of and2_1 is begin y <= a and b; end data_flow; VHDL File Name: or2_1.vhd
-- or2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;;
KSSEM, Bangalore
HDL Laboratory (10ECL48)
4 t Sem
entity or2_1 is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC); end or2_1; architecture data_flow of or2_1 is begin y <= a or b; end data_flow; Verilog File Name: full_adder_struct.v
//Full Adder - Structural module full_adder( a_in, b_in, c_in, sum, carry carr y ); input a_in, b_in, c_in; output sum, carry; wire s1,s2,s3; //syntax: gate_operator lable (ouput, input, input); xor x1 (s1, a_in, b_in); and a1 (s2, a_in, b_in); xor x2 (sum, s1, c_in); and a2 (s3, s1, c_in); or o1 (carry, s2, s3); endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
EXPERIMENT EXPERIMENT 4 32 - BIT ALU en 32
a_in
inputs
y_op
outputs
32
b_in
32
ALU 32bits
4
opc
Figure 10: Block Diagram of ALU 32bits
Inputs
Outputs Actions
en
opc
a_in
b_in
y_op
0
XXX X
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ZZZZZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZ
1
0001
1
0010
1
0011
1
0100
1
0101
1
0110
1
0111
011000000000000001111111111111 11 011000000000000001111111111111 11 011000000000000001111111111111 11 011000000000000001111111111111 11 011000000000000001111111111111 11 011000000000000001111111111111 11 011000000000000001111111111111 11
0100000000000000011111111001100 1 0100000000000000011111111001100 1 0100000000000000011111111001100 1 0100000000000000011111111001100 1 0100000000000000011111111001100 1 0100000000000000011111111001100 1 0100000000000000011111111001100 1
101000000000000011111111100110 00 001000000000000000000000011001 10 100111111111111110000000000000 00 010000000000000001111111100110 01 011000000000000001111111111111 11 101111111111111110000000011001 10 001000000000000000000000011001 10
Truth Table 10: ALU 32bits VHDL File Name: alu32bit.vhd
--ALU32bit – Behavioral Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu32bit is Port ( en : in BIT; opc : in STD_LOGIC_VECTOR (3 downto 0); a_in, b_in : in STD_LOGIC_VECTOR (31 downto 0); y_op : out STD_LOGIC_VECTOR (31 downto 0)); end alu32bit; architecture Behavioral of alu32bit is
No Change a_in + b_in a_in - b_in not a_in a_in and b_in a_in or b_in a_in nand b_in
a_in xor b_in
HDL Laboratory (10ECL48)
4 t Sem
KSSEM, Bangalore
begin process(en, a_in, b_in, opc) begin if (en = '1') then -- Active High Enabled case opc is when "0001" => y_op <= a_in + b_in; when "0010" => y_op <= a_in - b_in; when "0011" => y_op <= not a_in; when "0100" => y_op <= a_in and b_in; when "0101" => y_op <= a_in or b_in; when "0110" => y_op <= a_in nand b_in; when "0111" => y_op <= a_in xor x or b_in; when others => null; end case; else y_op <= < = "ZZZZZZZZZZZZZZZZZZZZZZZZ "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; ZZZZZZZZ"; end if; end process; end behavioral; Verilog File Name: alu32bit.v
// ALU 32bit module alu32bit( en, opc, a_in, b_in, y_op ); input en; input [3:0] opc; input [31:0] a_in, b_in; output [31:0] y_op; wire en; wire [3:0] opc; wire [31:0] a_in, b_in; reg [31:0] y_op; always @ ( en, opc, a_in, b_in) if (en == 1) // Active High Enabled case (opc) 4'b0001 : y_op = a_in + b_in; 4'b0010 : y_op = a_in - b_in; b _in; 4'b0011 : y_op = ~ a_in; 4'b0100 : y_op = a_in & b_in; 4'b0101 : y_op = a_in | b_in; 4'b0110 : y_op = ~ (a_in & b_in); 4'b0111 : y_op = a_in ^ b_in; default null; endcase else y_op = 32'bZ; endmodule
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
EXPERIMENT EXPERIMENT 5 FLIP FLOPS A. SR Flip Flop s q
r outputs
SR Flip Flop
inputs
qb rst
clk Figure 11: Block Diagram of SR Flip Flop
Inputs rst clk s
1 0 0 0 0
↑ ↑ ↑ ↑ ↑
Outputs r
q qb
Action
X X
q
qb
No Change
0
0
q
qb
No Change
0
1
0
1
Reset
1
0
1
0
Set
1
1
-
-
Illegal
Truth Table 11: S R Flip Flop VHDL File Name: sr_ff.vhd
-- S R Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity sr_ff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end sr_ff; architecture Behavioral of sr_ff is signal temp : std_logic := '0'; begin
HDL Laboratory (10ECL48)
4 t Sem
process(clk,rst) begin if(rst = '1') then temp <= '0'; elsif (clk'event and clk = '1') then if(s = '0' and r ='0') then temp <= temp; elsif(s = '0' and r ='1') then temp <= '0'; elsif(s = '1' and r ='0') then temp <= '1'; elsif(s = '1' and r ='1') then temp <= 'X'; end if; end if; end process; q <= temp; qb <= not temp; end Behavioral;
Verilog File Name: sr_ff.v
//Async SR Flip Flop module sr_ff( sr , clk , reset , q ,qb ); input [1:0] sr; input clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or posedge reset) if (reset) begin q = 1'b0; qb = ~q; end else begin case (sr) 2'd0 : q = q; 2'd1 : q = 1'b0; 2'd2 : q = 1'b1; 2'd3 : q = 1'bX; endcase qb = ~q; end endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
B. J K Flip Flop j q
k JK Flip Flop
inputs
outputs qb
rst
clk Figure 12: Block Diagram of JK Flip Flop
Inputs rst clk j 1 ↑ X
0 0 0 0
↑ ↑ ↑ ↑
k q X q
Outputs qb Action qb No Change
0
0
q
qb
No Change
0
1
0
1
Reset
1
0
1
0
Set
1
1
q'
q'
Toggle
Truth Table 12: J K Flip Flop VHDL File Name: jk_ff.vhd
--JK Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity jk_ff is Port ( j,k,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end jk_ff; architecture Behavioral of jk_ff is signal temp : std_logic := '0'; begin process(clk,rst) begin if(rst = '1') then temp <= '0'; elsif(clk'event and clk = '1') then if(j = '0' and k ='0') then temp <= temp; elsif(j = '0' and k ='1') then temp <= '0'; elsif(j = '1' and k ='0') then
4 t Sem
HDL Laboratory (10ECL48)
temp <= '1'; elsif(j = '1' and k ='1') then temp <= not temp; end if; end if; end process; q <= temp; qb <= not temp; end Behavioral;
Verilog File Name: jk_ff.v
//Async JK Flip Flop module jk_ff( jk , clk , reset , q ,qb ); input [1:0] jk; input clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or posedge reset) if (reset) begin q = 1'b0; qb = ~q; end else begin case (jk) 2'd0 : q = q; 2'd1 : q = 1'b0; 2'd2 : q = 1'b1; 2'd3 : q = ~q; endcase qb = ~q; end endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
C. D Flip Flop
d
q D Flip Flop
inputs
outputs qb
rst
clk Figure 13: Block Diagram of D Flip Flop
Inputs
Outputs
rst clk d
1 0 0
↑ ↑ ↑
q qb
Action
X
q
qb
No Change
0
0
1
Reset
1
1
0
Set
Truth Table 13: D Flip Flop VHDL File Name: d_ff.vhd
-- D Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity d_ff is Port ( d,clk,rst : in STD_LOGIC; q,qb : out STD_LOGIC); end d_ff; architecture Behavioral of d_ff is signal temp : std_logic := '0'; begin process(clk,rst) begin if(rst = '1') then temp <= '0'; elsif(clk'event and clk = '1') then temp <= d; end if; end process; q <= temp; qb <= not temp; end Behavioral;
HDL Laboratory (10ECL48)
4 t Sem
Verilog File Name: d_ff.v
//Async D Flip Flop module d_ff( d , clk , reset , q ,qb ); input d, clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or posedge reset) if (reset) begin q = 1'b0; qb=~q; end else begin q = d; qb=~q; end endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
D. T Flip Flop t
q inputs
outputs
T Flip Flop
qb rst
clk Figure 14: Block Diagram of T Flip Flop
Inputs
Outputs
rst clk t
1 0 0
↑ ↑ ↑
q
qb
Action
X
q
qb
No Change
0
q
qb
No Change
1
q'
q'
Toggle
Truth Table 14: T Flip Flop VHDL File Name: t_ff.vhd
--T Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity t_ff is Port ( t,clk,rst : in STD_LOGIC; q,qb : out STD_LOGIC); end t_ff; architecture Behavioral of t_ff is signal temp : std_logic := '0'; begin process(clk,rst) begin if(rst = '1') then temp <= '0'; elsif(clk'event and clk = '1' and t = '1') then temp <= not temp; end if; end process; q <= temp; qb <= not temp; end Behavioral;
HDL Laboratory (10ECL48)
4 t Sem
Verilog File Name: t_ff.v
//Async T Flip Flop module t_ff( t, clk, reset, q, qb ); input t, clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or posedge reset) if (reset) begin q = 1'b0; qb=~q; end else if (t) begin q = ~q; qb = ~q; end endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
EXPERIMENT 6 4- BIT COUNTERS A. Binary Synchronous Reset 4-bit Counter
Binary Synchronous Reset 4bit Counter
rst inputs
4
bin_out
outputs
clk Figure 15: Block Diagram of Binary Synchronous Reset Reset 4bit Counter
VHDL File Name: bin_counter_sync_4bit.vhd
-- Binary Synchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity bin_counter_sync_4bit is Port ( clk,rst : in STD_LOGIC; bin_out : out STD_LOGIC_VECTOR STD_LOGIC_VECTOR (3 downto downto 0)); end bin_counter_sync_4bit; architecture Behavioral of bin_counter_sync_4bit is signal temp: std_logic_vector(3 downto 0); begin process(clk) begin if ( clk'event and clk='1') then if(rst = '1') then temp <= "0000"; else temp <= temp+'1'; end if; end if; end process; bin_out <= temp ; end Behavioral;
Verilog File Name: bin_counter_sync_4bit.v
// Binary synchronous reset 4bit counter module bin_sync_4bit ( rst, clk, count); input rst,clk;
HDL Laboratory (10ECL48)
4 t Sem
KSSEM, Bangalore
output [3:0] count; reg [3:0] count; initial begin count = 4'b0000; end always @(posedge clk) if(rst) count = 4'b0000; else count = count + 4'b0001; endmodule
B. Binary Asynchronous Reset 4-bit Counter
Binary Asynchronous Reset 4bit Counter
rst inputs
4
bin_out
outputs
clk Figure 16: Block Diagram of Binary Asynchronous Reset 4bit Counter
VHDL File Name: bin_counter_async_4bit.vhd
--Binary Asynchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity bin_counter_async_4bit is Port ( clk,rst : in STD_LOGIC; bin_out : out STD_LOGIC_VECTOR STD_LOGIC_VECTOR (3 downto downto 0)); end bin_counter_async_4bit; architecture Behavioral of bin_counter_async_4bit is signal temp: std_logic_vector(3 downto 0); begin process(clk,rst) begin if(rst = '1') then
HDL Laboratory (10ECL48)
4 t Sem
temp <= "0000"; elsif ( clk'event and clk='1') then temp <= temp+'1'; end if; end process; bin_out <= temp ; end Behavioral;
Verilog File Name: bin_counter_async_4bit.v
// Binary asynchronous reset 4bit counter module bin_async_4bit ( rst, clk, count); input rst,clk; output [3:0] count; reg [3:0] count; initial begin count = 4'b0000; end always @(posedge clk or posedge rst) if(rst) count = 4'b0000; else count = count + 4'b0001; endmodule
KSSEM, Bangalore
4 t Sem
HDL Laboratory (10ECL48)
KSSEM, Bangalore
C. BCD Synchronous Reset 4-bit Counter
BCD Synchronous Reset 4bit Counter
rst inputs
4
bcd_out
outputs
clk Figure 17: Block Diagram of BCD Synchronous Reset 4bit Counter
VHDL File Name: bcd_counter_sync_4bit.vhd
--BCD Synchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity bcd_counter_sync is Port ( clk,rst : in STD_LOGIC; bcd_out : out STD_LOGIC_VECTOR STD_LOGIC_VECTOR (3 downto downto 0)); end bcd_counter_sync; architecture Behavioral of bcd_counter_sync is signal temp: std_logic_vector(3 downto 0); begin process(clk) begin if ( clk'event and clk='1') then if(rst = '1' or temp = "1001") then temp <= "0000"; else temp <= temp+'1'; end if; end if; end process; bcd_out <= temp ; end Behavioral;
HDL Laboratory (10ECL48)
4 t Sem
Verilog File Name: bcd_counter_sync_4bit.v
// BCD synchronous reset 4bit counter module bcd_sync ( rst, clk, count); input rst,clk; output [3:0] count; reg [3:0] count; initial begin count = 4'd0; end always @(posedge clk) if(rst) count = 4'd0; else if(count < 4'd9 ) count = count + 4'd1; else count = 4'd0; endmodule
KSSEM, Bangalore
HDL Laboratory (10ECL48)
4 t Sem
KSSEM, Bangalore
D. BCD Asynchronous Reset 4-bit Counter
BCD Asynchronous Reset 4bit Counter
rst inputs
4
bcd_out
outputs
clk Figure 18: Block Diagram of BCD Asynchronous Reset 4bit Counter
VHDL File Name: bcd_counter_async_4bit.vhd
-- BCD asynchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd_counter_async is Port ( clk,rst : in STD_LOGIC; bcd_out : out STD_LOGIC_VECTOR STD_LOGIC_VECTOR (3 downto downto 0)); end bcd_counter_async; architecture Behavioral of bcd_counter_async is signal temp: std_logic_vector(3 downto 0):= "0000"; begin process(clk,rst) begin if(rst = '1' or temp = "1010") then temp <= "0000"; elsif ( clk'event and clk='1') then temp <= temp+'1'; end if; end process; bcd_out <= temp ; end Behavioral;
HDL Laboratory (10ECL48)
4 t Sem
Verilog File Name: bcd_counter_async_4bit.v
// BCD asynchronous reset 4bit counter module bcd_async ( rst, clk, count); input rst,clk; output [3:0] count; reg [3:0] count; initial begin count = 4'd0; end always @(posedge clk or posedge rst) if(rst) count = 4'd0; else if(count < 4'd9 ) count = count + 4'd1; else count = 4'd0; endmodule
KSSEM, Bangalore
HDL Laboratory (10ECL48)
E.
4 t Sem
KSSEM, Bangalore
Binary Any-Sequence Any-Sequence Up-Down Up-Down 4-bit Counter Counter
d_in load
4 Binary Any Sequence 4bit Counter
updown inputs
4
bin_out
outputs
rst clk Figure 19: Block Diagram of Binary Any Sequence 4bit Counter
VHDL File Name: bin_counter_any_seq_4bit.vhd
-- Binary Any Sequence up down 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL IEEE.STD_LOGIC_UNSIGNED.ALL;; entity bin_counter_any_seq is Port ( clk,rst,load,updown : in STD_LOGIC; d_in :in STD_LOGIC_VECTOR( 3 downto 0); bin_out : out STD_LOGIC_VECTOR STD_LOGIC_VECTOR (3 downto downto 0)); end bin_counter_any_seq; architecture Behavioral of bin_counter_any_seq is signal temp: std_logic_vector(3 downto 0):= "0000"; begin process(clk, rst) begin if(rst = '1') then temp <= "0000"; elsif(load = '1') then temp <= d_in; elsif ( clk'event and clk='1' and load = '0') then if ( updown = '1') then temp <= temp+'1'; else temp <= temp-'1'; end if; end if; end process; bin_out <= temp ; end Behavioral;
HDL Laboratory (10ECL48)
4 t Sem
Verilog File Name: bin_counter_any_seq_4bit.v
// Binary Any Sequence Up Down Counter module any_seq_bin ( rst,load, clk,din,updown, count); input rst,clk,updown,load; input [3:0] din; output [3:0] count; reg [3:0] count; always @(posedge clk) if(rst) count = 4'b0000; else if(load) count = din; else if (updown) count = count + 4'b0001; else count = count - 4'b0001; endmodule
KSSEM, Bangalore
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
PART B EXPERIMENT 1 STEPPER MOTOR AND DC MOTOR 1.(a) Write a VHDL code to control speed, direction of Stepper motor.
Figure 1 : Interfacing Diagram of CPLD Board and Stepper Motor Interfacing Card
Figure 2: Block Diagram of Stepper Motor
Dept of ECE
Page|43
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
Procedure:
1. Make the connection between FRC9 of the FPGA board to the Stepper motor connector of the VTU card2. 2. Make the connection between FRC7 of the FPGA board to the Keyboard connector of the VTU card2. 3. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 4. Connect the downloading cable and power supply to the FPGA board. 5. Then open the Xilinx IMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 6. Make the reset switch on (active low). 7. Press the HEX keys and analyze the speed changes. VHDL CODING :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity STEPPERnew is Port ( dout : out std_logic_vector(3 downto 0); clk,reset: in std_logic; row:in std_logic_vector(1 downto 0); dir:in std_logic); end STEPPERnew; architecture Behavioral of STEPPERnew is signal clk_div : std_logic_vector(25 downto 0); signal clk_int: std_logic; signal shift_reg : std_logic_vector(3 downto 0); begin process(clk) begin if rising_edge (clk) then Dept of ECE
Page|44
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
clk_div <= clk_div + '1'; end if; end process; clk_int<=clk_div(21) when row="00"else clk_div(19) when row="01"else clk_div(17) when row="10"else clk_div(15) ; process(reset,clk_int,dir) begin if reset='0' then shift_reg <= "1001"; elsif rising_edge(clk_int) then if dir='0' then shift_reg <= shift_reg(0) & shift_reg(3 downto 1 ); else shift_reg<=shift_reg(2 downto 0) & shift_reg(3); end if; end if; end process; dout <= shift_reg; end Behavioral; --------------------------------------------------------------------------------------------------------------------UCF file(User constraint File) NET "clk" LOC = "p52" ; NET "dir" LOC = "p76" ; NET "dout<0>" LOC = "p141" ; NET "dout<1>" LOC = "p2" ; NET "dout<2>" LOC = "p4" ; NET "dout<3>" LOC = "p5" ; NET "reset" LOC = "p74" ; NET "row<0>" LOC = "p77" ; NET "row<1>" LOC = "p79" ;
Dept of ECE
Page|45
4th Sem
HDL Laboratory(10ECL48)
KSSEM,Bangalore
1. (b) Write a VHDL code to control speed, direction of DC motor.
Figure 3 : Interfacing Diagram of CPLD Board and DC Motor Interfacing Card
Figure 4: Block Diagram of DC Motor
Procedure:
1. Make the connection between FRC9 of the FPGA board to the DC motor connector of the VTU card2. 2. Make the connection between FRC7 of the FPGA board to the Keyboard connector of the VTU card2. 3. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 4. Connect the downloading cable and power supply to the FPGA board. 5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 6. Make the reset switch on (active low). 7. Press the HEX keys and analyze the speed changes. VHDL CODING :
Dept of ECE
Page|46
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
Library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; Library UNISIM; use UNISIM.vcomponents.all; entity dcmotor is generic(bits : integer := 8 ); -- number of bits b its used for duty cycle. -- Also determines pwm period. port ( CLK: in STD_LOGIC; -- 4 MHz clock RESET,DIR: in STD_LOGIC; -- dircntr pwm : out std_logic_VECTOR(1 DOWNTO 0); rly: out std_logic; ROW: in STD_LOGIC_VECTOR(0 to 3) ); -- this are the row lines end dcmotor; architecture dcmotor1 of dcmotor is signal counter : std_logic_vector(bits - 1 downto 0):="11111110"; signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide register signal DCLK,DDCLK,datain,tick: STD_LOGIC; -- this has the divided clock. signal duty_cycle: integer range 0 to 255; signal ROW1 : STD_LOGIC_VECTOR(0 to 3); -- this are the row lines begin -- select the appropriate lines for setting frequency CLK_DIV: process (CLK, DIV_REG) -- clock divider begin if (CLK'event and CLK='1') then DIV_REG <= DIV_REG + 1; end if; end process; DDCLK<=DIV_REG(12); ------------------------------------------------------ END OF CLOCK DIVIDER ---------------------------------------------------------------------------------------------tick <= row(0) and row(1) and row(2) and row(3); Dept of ECE
Page|47
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
process(tick) begin if falling_edge(tick) then case row is when "1110" => duty_cycle <= 255 ; --motor speed 1 when "1101" => duty_cycle <= 200 ; --motor speed 2 when "1011" => duty_cycle <= 150 ; --motor speed 3 when "0111" => duty_cycle <= 100 ; --motor speed 4 when others => duty_cycle <= 100; end case; end if; end process; process(DDCLK, reset) begin if reset = '0' then counter <= (others => '0'); PWM<="01"; elsif (DDCLK'event and DDCLK = '1') then counter <= counter + 1; if counter >= duty_cycle then pwm(1) <= '0'; else pwm(1) <= '1'; end if; end if; end process; rly<=DIR --motor direction control end dcmotor1; ---------------------------------------------------------------------------------------------------------------------
Dept of ECE
Page|48
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
UCF file(User constraint File) NET "CLK" LOC = "p52" ;
NET 泥IR49 LOC = 菟7649; NET "pwm<0>" LOC = "p4" ; NET "pwm<1>" LOC = "p141" ; NET "RESET" LOC = "p74" ; NET "rly" LOC = "p44" ; NET "ROW<0>" LOC = "p69" ; NET "ROW<1>" LOC = "p63" ; NET "ROW<2>" LOC = "p59" ; NET "ROW<3>" LOC = "p57" ;
Dept of ECE
Page|49
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
EXPERIMENT 2 EXTERNAL LIGHT 2. Write a VHDL code to control external lights using relays.
Figure 5: Interfacing Diagram of CPLD Board an d Relay Interface Card
Procedure: 1. Make the connection between FRC9 of the FPGA board to the External light connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board. 4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data.
Dept of ECE
Page|50
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
VHDL CODING :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity extlight is Port ( cntrl1,cntrl2 : in std_logic; light : out std_logic); end extlight; architecture Behavioral of extlight is begin light<= cntrl1 OR cntrl2 ; end Behavioral; --------------------------------------------------------------------------------------------------------------------UCF file(User constraint) NET "cntrl1" LOC = "P74"; NET "cntrl2" LOC = "P76"; NET "light" LOC = "P5";
Dept of ECE
Page|51
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
EXPERIMENT 3 SIGNAL GENERATION USING DAC 3.(a) Write a VHDL code to generate Sine waveforms using DAC .
.
Figure 6: Interfacing Diagram of CPLD Board an d Dac Interface Card
Figure 7: Block Diagram of Sine/Traingular/Square/Ramp Wave Generator using DAC
Procedure:
Dept of ECE
Page|52
4th Sem
HDL Laboratory(10ECL48)
KSSEM,Bangalore
1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board. 4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data. VHDL CODING :
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sine is port ( clk : in std_logic; rst : in std_logic; dac_out : out std_logic_vector(0 to 7)); end sine;
architecture behavioral of sine is signal c1:std_logic_vector(7 downto 0); signal i :integer range 0 to 179; type sine is array (0 to 179) of integer range 0 to 255; constant VALUE:SINE:=(128,132,136,141,154,150,154,158,163,167,171,175,180,184,188, 192,195,199,203,206,210,213,216,220,223,226,228,231,234,236, 238,241,243,244,246,247,248,249,250,251,252,253,254,255,255, 255,255,255,254,254,253,252,251,249,246,244,243,241,238,236, 234,231,228,226,223,220,216,213,210,206,203,199,195,192,188, 184,180,175,171,167,163,158,154,150,145,141,136,132,128,
Dept of ECE
Page|53
4th Sem
HDL Laboratory(10ECL48)
KSSEM,Bangalore
123,119,114,110,105,101,97,92,88,84,80,75,71,67,64,60,56,52, 49,45,42,39,35,32,29,27,24,21,19,17,14,12,11,9,7,6,4,3,2,1,1,0,0,0,0, 0,0,0,0,1,1,2,3,4,6,7,9,11,12,14,17,19,21,24,27,29,32,35,39,42,45,49, 52,56,60,64,67,71,75,80,84,88,92,97,101,105,110,114,119,123,128); begin process(clk,rst) begin if(rst='1') then c1<=(others=>'0'); elsif(clk'event and clk='1') then c1<=c1+1; end if; end process; process(c1(3)) begin if(c1(3)'event and c1(3)='1')then
dac_out<=conv_std_logic_vector(value(i),8); i<=i+1; if(i=179) then i<=0; end if; end if; end process; end behavioral; ---------------------------------------------------------------------------------------------------------------------
Dept of ECE
Page|54
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
UCF file(User constraint File) NET "clk" LOC = "p52" ; NET "dac_out<0>" LOC = "p21" ; NET "dac_out<1>" LOC = "p18" ; NET "dac_out<2>" LOC = "p17" ; NET "dac_out<3>" LOC = "p15" ; NET "dac_out<4>" LOC = "p14" ; NET "dac_out<5>" LOC = "p13" ; NET "dac_out<6>" LOC = "p12" ; NET "dac_out<7>" LOC = "p1" ; NET "rst" LOC = "p74" ;
Dept of ECE
Page|55
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
3.(b) Write a VHDL code to generate Square waveforms using DAC . Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board. 4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data. VHDL CODING
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity square_wave is Port ( clk : in std_logic; rst : in std_logic; dac_out : out std_logic_vector(0 to 7)); end square_wave; architecture Behavioral of square_wave is signal temp : std_logic_vector(3 downto 0); signal counter : std_logic_vector(0 to 7); signal en :std_logic; begin process(clk) begin if rising_edge(clk) then temp <= temp + '1' ; end if; end process; Dept of ECE
Page|56
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
process(temp(3)) begin if rst='1' then counter <= "00000000"; elsif rising_edge(temp(3)) then if counter<255 and en='0' then counter <= counter + 1 ; en<='0'; dac_out <="00000000"; elsif counter=0 then en<='0'; else en<='1'; counter <= counter-1; dac_out <="11111111"; end if; end if; end process; end Behavioral; --------------------------------------------------------------------------------------------------------------------UCF file(User constraint File) NET "clk" LOC = "p52" ; NET "dac_out<0>" LOC = "p21" ; NET "dac_out<1>" LOC = "p18" ; NET "dac_out<2>" LOC = "p17" ; NET "dac_out<3>" LOC = "p15" ; NET "dac_out<4>" LOC = "p14" ; NET "dac_out<5>" LOC = "p13" ; NET "dac_out<6>" LOC = "p12" ; NET "dac_out<7>" LOC = "p1" ; NET "rst" LOC = "p74" ;
Dept of ECE
Page|57
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
3.(c) Write a VHDL code to generate Traingular waveforms using DAC Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board. 4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data. VHDL CODING :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity triangular_wave is Port ( clk : in std_logic; rst : in std_logic; dac_out : out std_logic_vector(0 to 7)); end triangular_wave ; architecture Behavioral of triangular_wave is signal counter : std_logic_vector(0 to 8); signal temp : std_logic_vector(3 downto 0); signal en :std_logic; begin process(clk) begin if rising_edge(clk) then temp <= temp + '1' ; end if; end process; Dept of ECE
Page|58
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
process(temp(3)) begin if rst='1' then counter <= "000000000"; elsif rising_edge(temp(3)) then counter <= counter + 1 ; if counter(0)='1' then dac_out <=counter(1 to 8); else dac_out <=not(counter(1 to 8)); end if; end if; end process; end Behavioral; --------------------------------------------------------------------------------------------------------------UCF File(User constraint File) NET "clk" LOC = "p52" ; NET "dac_out<0>" LOC = "p21" ; NET "dac_out<1>" LOC = "p18" ; NET "dac_out<2>" LOC = "p17" ; NET "dac_out<3>" LOC = "p15" ; NET "dac_out<4>" LOC = "p14" ; NET "dac_out<5>" LOC = "p13" ; NET "dac_out<6>" LOC = "p12" ; NET "dac_out<7>" LOC = "p1" ; NET "rst" LOC = "p74" ;
Dept of ECE
Page|59
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
3.(d) Write a VHDL code to generate Ramp waveforms using DAC . Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board. 4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data.
VHDL CODING
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ramp_wave is Port ( clk : in std_logic; rst : in std_logic; dac_out : out std_logic_vector(0 to 7)); end ramp_wave; architecture Behavioral of ramp_wave is signal temp : std_logic_vector(3 downto 0); signal counter : std_logic_vector(0 to 7); signal en :std_logic; begin process(clk) begin if rising_edge(clk) then temp <= temp + '1' ; end if; Dept of ECE
Page|60
HDL Laboratory(10ECL48)
4th Sem
KSSEM,Bangalore
end process; process(temp(3)) begin if rst='1' then counter <= "00000000"; elsif rising_edge(temp(3)) then counter <= counter + 08 ; end if; end process; dac_out <=counter; end Behavioral; --------------------------------------------------------------------------------------------------------------------UCF file(User constraint File) NET "clk" LOC = "p52" ; NET "dac_out<0>" LOC = "p21" ; NET "dac_out<1>" LOC = "p18" ; NET "dac_out<2>" LOC = "p17" ; NET "dac_out<3>" LOC = "p15" ; NET "dac_out<4>" LOC = "p14" ; NET "dac_out<5>" LOC = "p13" ; NET "dac_out<6>" LOC = "p12" ; NET "dac_out<7>" LOC = "p1" ; NET "rst" LOC = "p74" ;
Dept of ECE
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