Verilog Hdl Lab Quiz

1

B.E 4/4 – I Semester EC 432

VERILOG HDL LAB

List Of Experiments Prescribed By Osmania University Write the Code (using VERILOG), Simulate and Synthesize 1. Basic Logic Gates. 2. Realization of a four variable function. 3. Arithmetic Units (Adders, Subtractors). 4. 8 - bit parallel adder using 4 - bit tasks and functions. 5. Multiplexers, Demultiplexers. 6. Encoders, Decoders, Priority encoder. 7. Four – bit Digital Comparator. 8. Arithmetic Logic Unit with 8 instructions. 9. Waveform generators 10. Flip – Flops. 11. Registers / Counters. 12. Sequence detector using Mealy and Moore type state machines.

All the programs should be simulated using test benches.

2

Mini Project: i)

8 bit CPU

ii)

Generation of different waveforms using DAC.

iii)

RTL code for Booths algorithm for signed binary number multiplication.

iv)

Development of HDL code to control speed, direction of DC/Stepper motor.

v)

Development of HDL code for MAC unit and realization of FIR filter.

3

VERILOG HDL LAB CONTENTS S.No.

Name Of The Experiment

PageNo.

1

Basic Logic Gates

14

2

Realization of four variable functions

18

3

Arithmetic Units(Adders & Subtractors)

20

4

N-BIT parallel adder

26

5

Multiplexers & Demultiplexers

28

6

Encoders, Decoders & Priority encoders

33

7

4-Bit Comparators

39

8

ALU Modeling

43

9

Waveform Generators

48

*10

Latches

51

11

Flip-Flops

53

12

Shift Registers and Counters

57

*13

Parity Generator

63

14

Finite State Machine

65

*Extra Experiments beyond the syllabus

4

Verilog Theory: Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description language is a language used to describe a digital system: for example, a microprocessor or a memory or a simple flip-flop. This just means that, by using a HDL, one can describe any digital hardware at any level. Verilog HDL is case sensitive Design Styles: The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standard gates. With the increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new practices it would be impossible to handle the new complexity. Bottom-Up Design: The desired design-style of all designers is the top-down one. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure topdown design. Due to this fact most designs are a mix of both methods, implementing some key elements of both design styles.

5 Verilog Design Flow: Specification High Level Design Micro Design/Low level design RTL Coding Simulation Synthesis Place & Route Post Silicon Validation Simulation: It is the process of verifying the functional characteristics of models at any level of abstraction. We use simulators to simulate the Hardware models, to test if the RTL code meets the functional requirements of the specification. To achieve this we need to write a test bench, which generates clk, reset and the required test vectors. A sample test bench for a counter is shown below. Normally we spend 60-70% of time in design verification. Synthesis: It is the process in which synthesis tools like design compiler take RTL in Verilog or VHDL, target technology, and constrains as input and maps the RTL to target technology primitives. Synthesis tool, after mapping the RTL to gates, also do the minimal amount of timing analysis to see if the mapped design is meeting the timing requirements. (Important thing to note is, synthesis tools are not aware of wire delays, they only know of gate delays). After the synthesis there are a couple of things that are normally done before passing the netlist to backend (Place and Route). Place and Route: The gate level netlist from the synthesis tool is taken and imported into place and route tool in Verilog netlist format. All the gates and flip-flops are placed; clock tree synthesis and reset is routed. After this each block is routed. The PAR tool output is a GDS file, used by foundry for fabricating the ASIC. Backend team normally

6 dumps out SPEF (standard parasitic exchange format) /RSPF (reduced parasitic exchange format)/DSPF (detailed parasitic exchange format) from layout tools like ASTRO to the frontend team, who then use the read_parasitic command in tools like Prime Time to write out SDF (standard delay format) for gate level simulation purposes. Module: In Verilog, we call our "black boxes" module. This is a reserved word within the program used to refer to things with inputs, outputs, and internal logic workings. •

wire data type is used for connecting two points.

•

reg data type is used for storing values

Here we have only two types of ports, input and output. In real life, we can have bi-directional ports as well. Verilog allows us to define bi-directional ports as "inout." Operators: Nearly all operators are exactly the same as their counterparts in the C programming language. Control Statements: If-else statements check a condition to decide whether or not to execute a portion of code. If a condition is satisfied, the code is executed. Else, it runs this other portion of code. One could use any operator in the condition checking, as in the case of C language. If needed we can have nested if else statements; statements without else are also ok, but they have their own problem, when modeling combinational logic, in case they result in a Latch (this is not always true). Case statements are used where we have one variable which needs to be checked for multiple values. like an address decoder, where the input is an address and it needs to be checked for all the values that it can take. Instead of using multiple

7 nested if-else statements, one for each value we're looking for, we use a single case statement: this is similar to switch statements in languages like C++.

A while statement executes the code within it repeatedly if the condition it is assigned to check returns true. While loops are not normally used for models in real life, but they are used in test benches. As with other statement blocks, they are delimited by begin and end. For loops in Verilog are almost exactly like for loops in C or C++. The only difference is that the ++ and -- operators are not supported in Verilog. Repeat is similar to the for loop. Instead of explicitly specifying a variable and incrementing it when we declare the for loop, we tell the program how many times to run through the code, and no variables are incremented. •

While, if-else, case (switch) statements are the same as in C language.

•

If-else and case statements require all the cases to be covered for combinational logic.

•

For-loop is the same as in C, but no ++ and -- operators.

•

Repeat is the same as the for-loop but without the incrementing variable.

•

Combinational elements can be modeled using assign and always statements.

•

Sequential elements can be modeled using only always statement.

•

There is a third block, which is used in test benches only: it is called Initial statement.

•

An initial block, as the name suggests, is executed only once when simulation starts. This is useful in writing test benches. If we have multiple initial blocks, then all of them are executed at the beginning of simulation.

•

always: As the name suggests, an always block executes always, unlike initial blocks which execute only once (at the beginning of simulation). A second difference is that an always block should have a sensitive list or a delay associated with it.

8 •

The sensitive list is the one which tells the always block when to execute the block of code. The @ symbol after reserved word ' always', indicates that the block will be triggered "at" the condition in parenthesis after symbol @.

•

One important note about always block: it cannot drive wire data type, but can drive reg and integer data types.

•

An assign statement is used for modeling only combinational logic and it is executed continuously. So the assign statement is called 'continuous assignment statement' as there is no sensitive list.

Tasks and Functions: When repeating the same old things again and again, Verilog, like any other programming language, provides means to address repeated used code, these are called Tasks and Functions. Functions and tasks have the same syntax; one difference is that tasks can have delays, whereas functions can not have any delay. This means that function can be used for modeling combinational logic. A second difference is that functions can return a value, whereas tasks cannot. Module Instantiation •

Modules are the building blocks of Verilog designs

•

You create the design hierarchy by instantiating modules in other modules.

•

You instance a module when you use that module in another, higher-level module

•

Ports: Ports allow communication between a module and its environment.

•

All but the top-level modules in a hierarchy have ports.

•

Ports can be associated by order or by name.

•

Registers: store the last value assigned to them until another assignment statement changes their value.

•

registers represent data storage constructs.

•

we can create regs arrays called memories.

•

register data types are used as variables in procedural blocks.

9 •

register data type is required if a signal is assigned a value within a procedural block

•

Procedural blocks begin with keyword initial and always.

Gate level primitives: •

Verilog has built in primitives like gates, transmission gates, and switches. These are rarely used in design (RTL Coding), but are used in post synthesis step for modeling the ASIC/FPGA cells; these cells are then used for gate level simulation, or what is called as SDF simulation. Also the output netlist format from the synthesis tool, which is imported into the place and route tool, is also in Verilog gate level primitives. Ex: and , or etc:

•

There are six different switch primitives (transistor models) used in Verilog, nmos, pmos and cmos and the corresponding three resistive versions rnmos, rpmos and rcmos. The cmos types of switches have two gates and so have two control signals.

•

Transmission gates tran and rtran are permanently on and do not have a control line. Tran can be used to interface two wires with separate drives, and rtran can be used to weaken signals. Resistive devices reduce the signal strength which appears on the output by one level. All the switches only pass signals from source to drain; incorrect wiring of the devices will result in high impedance outputs.

Delays: In real circuits, logic gates have delays associated with them. Verilog provides the mechanism to associate delays with gates •

Rise, Fall and Turn-off delays.

•

Minimal, Typical, and Maximum delays.

•

In Verilog delays can be introduced with #'num' as in the examples below, where # is a special character to introduce delay, and 'num' is the number of ticks simulator should delay current statement execution

10 •

The rise delay is associated with a gate output transition to 1 from another value (0, x, z).

•

The fall delay is associated with a gate output transition to 0 from another value (1, x, z).

•

The Turn-off delay is associated with a gate output transition to z from another value (0, 1, x).

•

The min value is the minimum delay value that the gate is expected to have.

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The typ value is the typical delay value that the gate is expected to have.

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The max value is the maximum delay value that the gate is expected to have.

User Defined Primitives (UDP): Verilog has built-in primitives like gates, transmission gates, and switches. This is a rather small number of primitives; if we need more complex primitives, then Verilog provides UDP, or simply User Defined Primitives. Using UDP we can model. •

Combinational Logic

•

Sequential Logic

UDP begins with reserve word primitive and ends with endprimitive. Ports/terminals of primitive should follow. This is similar to what we do for module definition. UDPs should be defined outside module and endmodule. UDP port rules: •

An UDP can contain only one output and up to 10 inputs.

•

Output port should be the first port followed by one or more input ports.

•

All UDP ports are scalar, i.e. Vector ports are not allowed.

•

UDPs cannot have bidirectional ports.

•

The output terminal of a sequential UDP requires an additional declaration as type reg.

•

It is illegal to declare a reg for the output terminal of a combinational UDP.

•

Functionality of primitive (both combinational and sequential) is described inside a table, and it ends with reserved word 'endtable'. For sequential UDP, we can use initial to assign an initial value to output.

11 Note: An UDP cannot use 'z' in the input table table: It is used for describing the function of UDP. Verilog reserved word table marks the start of table and reserved word endtable marks the end of table. Each line inside a table is one condition; when an input changes, the input condition is matched and the output is evaluated to reflect the new change in input. initial: This statement is used for initialization of sequential UDPs. This statement begins with the keyword 'initial'. The statement that follows must be an assignment statement that assigns a single bit literal value to the output terminal reg. •

Concatenations: are expressed using the brace characters { & }, with commas separating the expressions within. o

Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the results has 24 bits

•

Unsized constant numbers are not allowed in concatenations.

Abstraction Levels: •

Behavioral Models: Higher level of modeling where behavior of logic is modeled.

•

RTL Models : Logic is modeled at register level

•

Structural Models: Logic is modeled at both register level and gate level.

Procedural Blocks: Verilog behavioral code is inside procedure blocks, but there is an exception: some behavioral code also exist outside procedure blocks. •

initial: initial blocks execute only once at time zero (start execution at time zero).

•

always: always blocks loop to execute over and over again; in other words, as the name suggests, it executes always.

Procedural Assignment Statements: •

Procedural assignment statements assign values to reg, integer, real, or time variables and cannot assign values to nets (wire data types)

12 Procedural Group Statements: If a procedure block contains more than one statement, those statements must be enclosed within •

Sequential begin - end block

•

Parallel fork - join block

When using begin-end, we can give name to that group. This is called named blocks begin - end •

Group several statements together.

•

Cause the statements to be evaluated sequentially (one at a time)

•

Any timing within the sequential groups is relative to the previous statement.

•

Delays in the sequence accumulate (each delay is added to the previous delay)

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Block finishes after the last statement in the block fork - join

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Group several statements together.

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Cause the statements to be evaluated in parallel (all at the same time).

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Timing within parallel group is absolute to the beginning of the group.

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Block finishes after the last statement completes (Statement with highest delay, it can be the first statement in the block).

Blocking and Nonblocking Assignment Statements: •

Blocking assignments are executed in the order they are coded, hence they are sequential. Since they block the execution of next statement, till the current statement is executed, they are called blocking assignments. Assignment are made with "=" symbol. Example a = b;

•

Nonblocking assignments are executed in parallel. Since the execution of next statement is not blocked due to execution of current statement, they are called

13 nonblocking statement. Assignments are made with "<=" symbol. Example a <= b; assign and deassign: •

The assign and deassign procedural assignment statements allow continuous assignments to be placed onto registers for controlled periods of time. The assign procedural statement overrides procedural assignments to a register. The deassign procedural statement ends a continuous assignment to a register.

force and release: •

Another form of procedural continuous assignment is provided by the force and release procedural statements. These statements have a similar effect on the assign-deassign pair, but a force can be applied to nets as well as to registers. One can use force and release while doing gate level simulation to work around reset connectivity problems. Also can be used insert single and double bit errors on data read from memory.

casex and casez: •

Special versions of the case statement allow the x ad z logic values to be used as "don't care":

Looping statements: •

Appear inside procedural blocks only; Verilog has four looping statements like any other programming language.

•

The forever loop executes continually, the loop never ends. Normally we use forever statements in initial blocks.

•

The repeat loop executes < statement > a fixed < number > of times

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The while loop executes as long as an < expression > evaluates as true. This is the same as in any other programming language.

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The for loop is the same as the for loop used in any other programming language.

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Continuous assignment statements drive nets (wire data type). They represent structural connections.

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1. Basic Logic Gates

AIM: a) Write verilog code for two input logic gates b) Verify the code using test bench PROGRAMME: module gate2(a,b,x); input a,b; output x; // 2- input Logic gates 1.

and(x,a,b);

2.

or(x,a,b);

3.

not(x,a);

4.

nand(x,a,b);

5.

nor(x,a,b);

6.

xor(x,a,b);

7.

and a1(x,m,n);

// only one input for NOT

// Instance name a1 is specified even though optional // for logic gates

8.

and(x,a,b,c);

// 3-Input AND gate

9.

xor(x,a,b,c,d);

// 4- Input XOR gate

endmodule

15 OUTPUT WAVEFORM: 1. and gate

Fig. 1

2. or gate

Fig. 2

3. not gate

Fig. 3

4. nand gate

Fig. 4

16

5. nor gate

Fig. 5

6. xor gate

Fig. 6

7. and gate using instance

Fig.7

17 8. 3_input and gate

Fig. 8

9. 4_input xor gate

Fig. 9

VIVA – VOCE QUESTIONS: 1. What is a Simulator? 2. What are the different levels of abstractions in the Verilog? 3. What are the differences between ‘C’ language and ‘Verilog’? 4. What is the basic component in Verilog programme? 5. What is the difference between wire and reg data types? 6. What is the difference between wire and reg? 7. What is the difference between blocking and non-blocking assignments? 8. What is the difference between bit wise, unary and logical operators?

18

2. Realization of Four Variable Functions

AIM: a) Realize Four Variable functions b) Verify the code using test bench i) f(a,b,c,d) = Σ 0, 1, 3, 5, 7, 11, 15 ii) f(a,b,c,d) = Σ 0, 1, 2, 3, 4, 8, 10, 12, 15 iii) f(a,b,c,d) = Σ 0, 2, 8, 9, 11, 12, 13, 14 iv) f(w,x,y,z) = π 0, 1, 3, 5, 7, 11, 15 v) f(w,x,y,z) = π 0, 1, 2, 3, 4, 8, 10, 12, 15 vi) f(w,x,y,z) = π 0, 2, 8, 9, 11, 12, 13, 14

Minimize the above expressions using Boolean algebra and write the data flow model.

19 VIVA – VOCE QUESTIONS: 1. What are the different logic minimization techniques and name them? 2. What is the difference between Minterm and Maxterm? 3. What is the difference between POS and SOP? 4. In logic minimization, which method is preferred if the number of variables are more than 5? 5. How many Boolean equations are possible with ‘n’ variables? 6. Which one preferred-casex or casez? 7. What is the difference between task and function? 8. What is the difference between casex, casez and case statements?

20

3. Arithmetic Units (Adders & Subtractors) AIM: Write verilog code for halfadder, fulladder, 4-bit parallel adder and full subtractor. a) Verify the code using test bench PROGRAMME: Half Adder: module halfadder(sum,carryout,in0,in1); input ino,in1; output sum,carryout; 1.

xor x1(s,a,b); and a1(c,a,b);

2.

assign sum = a ^ b; assign carryout = (a & b) | (b & c) | (c & a);

endmodule OUTPUT WAVEFORM:

Fig. 10

Full – Adder:

21 module fulladder (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; reg s, Cout; 1.

assign s = x ^ y ^ Cin;

//concurrent dataflow

assign Cout = (x & y) | (x & Cin) | (y & Cin); 2.

always @(x or y or Cin)

// Sequential

{Cout, s} = x + y + Cin; 3.

xor (z4, x, y);

// Using Primitives

xor (s, z4, Cin);

// wire z1,z2,z3,z4 ; connecting

wires and (z1, x, y); and (z2, x, Cin); and (z3, y, Cin); or (Cout, z1, z2, z3); 4.

xor (s, x, y, Cin);

//3-input xor

and (z1, x, y), (z2, x, Cin),(z3, y, Cin);

//multiple instantiations

or (Cout, z1, z2, z3); endmodule OUTPUT WAVEFORM:

Fig. 11

4-bit Full Adder:

22 module adder4bit (carryin, X, Y, S, carryout); input carryin; input [3:0] X, Y; output [3:0] S; output carryout; wire [3:1] C; // Structural Model for 4-bit Full Adder fulladder stage0 (carryin, X[0], Y[0], S[0], C[1]); fulladder stage1 (C[1], X[1], Y[1], S[1], C[2]); fulladder stage2 (C[2], X[2], Y[2], S[2], C[3]); fulladder stage3 (C[3], X[3], Y[3], S[3], carryout); endmodule OUTPUT WAVEFORM:

Fig. 12

N-Bit Adder: module addern (carryin, X, Y, S, carryout); parameter n=32; input carryin; input [n-1:0] X, Y; output [n-1:0] S; output carryout; reg [n-1:0] S; reg carryout; reg [n:0] C; integer k; 1.

always @(X or Y or carryin)

23 begin C[0] = carryin; for (k = 0; k <= n-1; k = k+1) begin S[k] = X[k] ^ Y[k] ^ C[k]; C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]); end carryout = C[n]; end 2.

always @(X or Y or carryin) S = X + Y + carryin;

3.

always @(X or Y or carryin)

// output carryout,

overflow; begin

// reg carryout, overflow; Sum = {1'b0,X} + {1'b0,Y} + carryin;

// reg [n:0] Sum;

S = Sum[n-1:0]; carryout = Sum[n]; overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1]; end endmodule Carry Look Ahead adder: module CLA_4b(sum,c_4,a,b,c_0); input [3:0]a,b; input c_0; output [3:0]sum; output c_4; wire p0,p1,p2,p3,g0,g1,g2,g3; wire c1,c2,c3,c4; assign

24 p0=a[0]^b[0], p1=a[1]^b[1], p2=a[2]^b[2], p3=a[3]^b[3], g0=a[0]&b[0], g1=a[1]&b[1], g2=a[2]&b[2], g3=a[3]&b[3]; assign c1=g0|(p0&c_0), c2=g1|(p1&g0)|(p1&p0&c_0), c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&c_0), c4=g3|(p3&g2)|(p3&p2&p1&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&c_0); assign sum[0]=p0^c_0, sum[1]=p1^c1, sum[2]=p2^c2, sum[3]=p3^c3, c_4=c4; endmodule OUTPUT WAVEFORM:

Fig. 13

Full Subtractor:

25 module fullsub(x1,x2,x3,d,b); input x1,x2,x3; output d,b; assign d= x1^x2^x3; assign b=(~x1)&((x1^x3)|(x2&x3)); endmodule OUTPUT WAVEFORM:

Fig. 14

VIVA – VOCE QUESTIONS: 1. What is module instantiation? 2. What are the different ways of association of ports in module instantiation? 3. Which is the fastest Adder? 4. What are the applications of Adders and Subtractors? 5. Which level of abstraction is suitable for combinational circuits? 6. What is the data type supports for the assignment of data in data flow modeling? 7. What is the difference between $display and $monitor and $write and $strobe? 8. What is the difference between code-compiled simulator and normal simulator?

26

4. N-Bit Parallel Adder

AIM: a) Write the verilog code for N – Bit Parallel Adder b) Verify the code using test bench PROGRAMME: N-Bit Adder: module addern (carryin, X, Y, S, carryout); parameter n=32; input carryin; input [n-1:0] X, Y; output [n-1:0] S; output carryout; reg [n-1:0] S; reg carryout; reg [n:0] C; integer k; 1.

always @(X or Y or carryin) begin C[0] = carryin; for (k = 0; k <= n-1; k = k+1) begin S[k] = X[k] ^ Y[k] ^ C[k]; C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]); end carryout = C[n]; end

2.

always @(X or Y or carryin) S = X + Y + carryin;

27 3.

always @(X or Y or carryin)

// output carryout,

overflow; begin

// reg carryout, overflow; Sum = {1'b0,X} + {1'b0,Y} + carryin;

// reg [n:0] Sum;

S = Sum[n-1:0]; carryout = Sum[n]; overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1]; end endmodule OUTPUT WAVEFORM:

Fig. 15

VIVA – VOCE QUESTIONS: 1. What are the differences between tasks and function declarations? 2. How many values can be returned using functions? 3. How many values can be returned using tasks? 4. Are the tasks and functions synthesizable? 5. Can you call a task in a function? 6. What is the difference between “= =” and “= = =”? 7. What is the difference between inter statement and intra statement delay? 8. What is delta simulation time?

28

5. Multiplexers & Demultiplexers

AIM: a) Write the verilog code for Multiplexers & Demultiplexers b) Verify the code using test bench PROGRAMME: Mux 2x1: module mux2to1 (w0, w1, s, f); input w0, w1, s; output f; reg f; 1.

assign f = s ? w1 : w0;

2.

always @(w0 or w1 or s) f = s ? w1 : w0;

3.

always @(w0 or w1 or s) if (s==0) f = w0; else f = w1;

endmodule OUTPUT WAVEFORM:

Fig. 16

29 Mux 4x1: module mux4to1 (w0, w1, w2, w3, S, f); input w0, w1, w2, w3; input [1:0] S; output f; 1.

assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);

2.

always @(w0 or w1 or w2 or w3 or S) if (S == 2'b00)

// (S == 1)

f = w0; else if (S == 2'b01)

// (S == 2)

f = w1; else if (S == 2'b10)

// (S == 3)

f = w2; else if (S == 2'b11)

// (S == 4)

f = w3; 3.

always @(W or S) case (S) 0: f = W[0]; 1: f = W[1]; 2: f = W[2]; 3: f = W[3]; endcase

endmodule OUTPUT WAVEFORM:

Fig. 17

30 Mux 16x1: module mux16to1 (W, S16, f);

// Structural Modeling

input [0:15] W; input [3:0] S16; output f; wire [0:3] M; mux4to1 Mux1 (W[0:3], S16[1:0], M[0]); mux4to1 Mux2 (W[4:7], S16[1:0], M[1]); mux4to1 Mux3 (W[8:11], S16[1:0], M[2]); mux4to1 Mux4 (W[12:15], S16[1:0], M[3]); mux4to1 Mux5 (M[0:3], S16[3:2], f); endmodule OUTPUT WAVEFORM:

Fig. 18

DEMULTIPLEXERS 1x4 Demux: module demux1x4(y,s,i); input i; input [1:0]s; output [3:0]y; wire w0,w1; not(w0,s0); not(w1,s0); and(y[0],i,w0,w1); and(y[1],i,w1,s0); and(y[2],i,s1,w0); and(y[3],i,s1,s0); endmodule

31

1x8 Demux: module demux18(i,s,f); input i; input[2:0] s; output[7:0] f; 1.

always @(s) begin case (s) 3'b000: f[0]=i; 3'b001: f[1]=i; 3'b010: f[2]=i; 3'b011: f[3]=i; 3'b100: f[4]=i; 3'b101: f[5]=i; 3'b110: f[6]=i; 3'b111: f[7]=i; endcase end

2.

wire[2:0] sb; assign sb[0]=~s[0]; assign sb[1]=~s[1]; assign sb[2]=~s[2]; assign f[0]=i&sb[2]&sb[1]&sb[0]; assign f[1]=i&sb[2]&sb[1]&s[0]; assign f[2]=i&sb[2]&s[1]&sb[0]; assign f[3]=i&sb[2]&s[1]&s[0]; assign f[4]=i&s[2]&sb[1]&sb[0]; assign f[5]=i&s[2]&sb[1]&s[0]; assign f[6]=i&s[2]&s[1]&sb[0]; assign f[7]=i&s[2]&s[1]&s[0];

endmodule

32 OUTPUT WAVEFORM:

Fig. 19

VIVA – VOCE QUESTIONS: 1. How many 2 x 1 multiplexers are required in implementing a n x 1 multiplexer where ‘n’ is multiple of 2? 2. What are the applications of multiplexers and demultiplexers? 3. How many select lines are required for n x 1 multiplexer? 4. What is other name of behavioral level of abstraction? 5. Why the multiplexer can be called as a Universal element? 6. What is difference between Verilog full case and parallel case? 7. How blocking and non blocking statements get executed? 8. What is sensitivity list?

33

6. Encoders, Decoders & Priority Encoder

AIM: a) Write the verilog code for encoders, priority encoders & decoders b) Verify the code using test bench PROGRAMME: 4 to2 Encoder: Module encoder4to2(W,Y,En); input En; input [3:0]W; output [1:0]Y; if (En == 0) Y = 2'b00; else case (W) 0: Y = 2'b00; 1: Y = 2'b01; 2: Y = 2'b10; 3: Y = 2'b11; endcase endmodule OUTPUT WAVEFORM:

Fig. 20

34 DECODERS 2 to 4 Decoder: module dec2to4 (W, Y, En); input [1:0]W;

// Address lines

input En;

// Enable

output [0:3]Y; reg [0:3]Y; 1.

always @(W or En) case ({En, W}) 3'b100: Y = 4'b1000; 3'b101: Y = 4'b0100; 3'b110: Y = 4'b0010; 3'b111: Y = 4'b0001; default: Y = 4'b0000; endcase

2.

if (En == 0) Y = 4'b0000; else case (W) 0: Y = 4'b1000; 1: Y = 4'b0100; 2: Y = 4'b0010; 3: Y = 4'b0001; endcase

3.

always @(W or En) for (k = 0; k <= 3; k = k+1) if ((W == k) && (En == 1)) Y[k] = 1; else Y[k] = 0;

4.

not n1(r1,W[1]); not n2(r2,W[0]);

35 and a1(Y[1],r1,r2); and a2(Y[2],r1,W[0]); and a3(Y[3],r2,W[1]); and a4(Y[4],W[1],W[0]); endmodule OUTPUT WAVEFORM:

Fig. 21

4 to 16 Decoder: module dec4to16(W, Y, En); input [3:0] W; input En; output [0:15] Y; wire [0:3] M; 1.

integer k; always @(W or En) for (k = 0; k <= 3; k = k+1) if (W == k) Y[k] = En;

2.

dec2to4 Dec1 (W[3:2], M[0:3], En); dec2to4 Dec2 (W[1:0], Y[0:3], M[0]); dec2to4 Dec3 (W[1:0], Y[4:7], M[1]); dec2to4 Dec4 (W[1:0], Y[8:11], M[2]); dec2to4 Dec5 (W[1:0], Y[12:15], M[3]);

endmodule

36 OUTPUT WAVEFORM:

Fig. 22

PRIORITY ENCODER 3-bit Priority Encoder: module priority (W, Y, z); input [3:0] W; output [1:0] Y; output z; reg [1:0] Y; reg z; 1.

always @(W) begin z = 1; casex(W) 4'b1xxx: Y = 3; 4'b01xx: Y = 2; 4'b001x: Y = 1; 4'b0001: Y = 0; default: begin z = 0; Y = 2'bx; end endcase end

37 2.

Y = 2'bx; z = 0; for (k = 0; k < 4; k = k+1) if(W[k]) begin Y = k; z = 1; end end

endmodule OUTPUT WAVEFORM:

Fig. 23

8-bit Priority Encoder: module priority_8(q,q3,d); input [7:0]d; output q3; output [2:0]q; reg [2:0]q; reg q3; always@(d) begin q3=1; if(d[7]) q=3'b111; if(d[6]) q=3'b110; if(d[5]) q=3'b101; if(d[4]) q=3'b100; if(d[3]) q=3'b011;

38 if(d[2]) q=3'b010; if(d[1]) q=3'b001; if(d[0]) q=3'b000; else begin q3=0; q=3'b000; end end endmodule OUTPUT WAVEFORM:

Fig. 24

VIVA – VOCE QUESTIONS: 1. What is an Encoder and Decoder? 2. What are the applications of Encoder and Decoder? 3. How a priority encoder is different from normal encoder? 4. Why the decoder is widely used than demultiplexer? 5. Design a 3 x 8 line decoder using a 2 x 4 line decoder? 6. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why? 7. What are the difference between Verilog and VHDL? 8. What are system tasks?

39

7. 4-Bit Comparator

AIM: a) Write the verilog code for 4-bit comparator b) Verify the code using test bench PROGRAMME: 4-bit Comparator with Equal, Lesser & Greater than functions: module compare (A, B, AeqB, AgtB, AltB); input [4:0] A, B; output AeqB, AgtB, AltB; reg AeqB, AgtB, AltB; always @(A or B) begin AeqB = 0; AgtB = 0; AltB = 0; if(A == B) AeqB = 1; else if (A > B) AgtB = 1; else AltB = 1; end endmodule

40 OUTPUT WAVEFORM:

Fig. 25

2-bit Magnitude Comparator: module magcomp(a0,a1,b0,b1,f0,f1,f2); input a0,a1,b0,b1; output f0,f1,f2; wire x,y,u,v,p,q,r,j,k,c,f,g; not(x,a0); not(y,a1); not(u,b0); not(v,b1); and(p,x,y,b0); and(q,x,b0); and(r,b0,b1,y); or(f0,p,q,r); and(j,a1,b1); and(k,y,v); or(f1,j,k); and(c,a1,u,v); and(f,a0,u); and(g,v,x,y); or(f2,c,f,g); endmodule

//Gate level model

41 4-bit magnitude comparator using functions: module mc(a,b,l,g,e); input [3:0]a,b; output [3:0]l,g,e; reg [3:0]l,g,e; always @(a or b) begin l=less(a,b); g=great(a,b); e=equal(a,b); end function [3:0]less; input [3:0]a,b; if(ab) begin great=a; $display(“a>b”); end else great=0; endfunction

42 function [3:0]equal; input [3:0]a,b; if(a==b) begin equal=a; $display(“a==b”); end else equal=0; endfunction endmodule

VIVA – VOCE QUESTIONS: 1. Write verilog code for 4 – bit comparator in gate level model? 2. What are the differences between gate level and data flow models? 3. Explain gate delays using comparator? 4. What are the differences between data flow model and behavioral model? 5. What are the enhancements in Verilog 2001? 6. What is PLI? Why is it used? 7. What are inertial and transport delays? 8. If you miss sensitivity list what happens?

43

8. ALU Modeling

AIM: a) Write the verilog code for ALU with 16 Operations b) Verify the code using test bench PROGRAMME: module alu_8(out,in1,in2,s); input [8:0]in1,in2; input [3:0]s; output [8:0]out; reg [8:0]out; //,flag; always@(s) begin case(s) 4'b0000:

out=in1+in2;

//8-bit addition

4'b0001:

out=in1-in2;

//8-bit subtraction

4'b0010:

out=in1*in2;

//8-bit multiplication

4'b0011:

out=in1/in2;

//8-bit division

4'b0100:

out=in1%in2;

//8-bit modulo division

4'b0101:

out=in1&&in2;

//8-bit logical and

4'b0110:

out=in1||in2;

//8-bit logical or

4'b0111:

out=!in1;

//8-bit logical negation

44 4'b1000:

out=~in1;

//8-bit bitwise negation

4'b1001:

out=in1&in2;

//8-bit bitwise and

4'b1010:

out=in1|in2;

//8-bit bitwise or

4'b1011:

out=in1^in2;

//8-bit bitwise xor

4'b1100:

out=in1<<1;

//left shift

4'b1101:

out=in1>>1;

//right shift

4'b1110:

out=in1+1;

//increment

4'b1111:

out=in1-1;

//decrement

endcase end endmodule OUTPUT WAVEFORM:

Fig. 26

ALU with 8 Operations:

45 module alu(s, A, B, F); input [2:0] s; input [3:0] A, B; output [3:0] F; reg [3:0] F; always @(s or A or B) case (s) 0: F = 4'b0000; 1: F = B - A; 2: F = A - B; 3: F = A + B; 4: F = A ^ B; 5: F = A | B; 6: F = A & B; 7: F = 4'b1111; endcase endmodule ALU using Functions: module alu(a,b,out,s); input [7:0]a,b; input [2:0]s; output [15:0]out; reg [15:0]out; always @(s) begin case(s) 3’b000:out=add(a,b); 3’b001:out=sub(a,b); 3’b010:out=mul(a,b); 3’b011:out=and1(a,b); 3’b100:out=or1(a,b); 3’b101:out=xor1(a,b);

46 3’b110:out=rshift(a,b); 3’b111:out=lshift(a,b); endcase end function [15:0]add; input [7:0]a,b; add=a+b; endfunction function [15:0]sub; input [7:0]a,b; sub=a-b; endfunction function [15:0]mul; input [7:0]a,b; mul=a*b; endfunction function [15:0]and1; input [7:0]a,b; and1=a&b; endfunction function [15:0]or1; input [7:0]a,b; or1=a|b; endfunction function [15:0]xor1; input [7:0]a,b; xor1=a^b; endfunction

47 function [15:0]lshift; input [7:0]a,b; lshift=a<>b; endfunction endmodule VIVA – VOCE QUESTIONS: 1. What are the differences between tasks and functions? 2. Write a program for ALU using tasks and functions? 3. What are various delays in behavioral model? 4. What are various delays in data flow model? 5. What is the use of ‘generate’ statement? Give its syntax? 6. What is the significance Timescale directive? 7. What is difference between freeze deposit and force? 8. Write a verilog code to swap contents of two registers with and without a temporary register?

9. Waveform Generators

48 AIM: a) Write the verilog code for Waveform Generators b) Verify the code using test bench PROGRAMME: module square(clk); inout clk; reg clk; always @(posedge clk) begin repeat(10) #10 clk=~clk; end endmodule

module square; parameter TON=5,TOFF=5; reg clk; initial clk=1'b0; always begin #TOFF clk=1'b0; #TON clk=1'b1; end endmodule

49 OUTPUT WAVEFORM:

Fig. 27

module trianglewave(out); output out; voltage out; parameter real period=10 from [0:inf],ampl=1; integer slope; real offset; analog begin @(timer(0,period)) begin slope=1; offset=$realtime; discontuinity(1); end @(time(period/2,period)) begin slope=-1; offset=$realtime;

50 discontuinity(1); end v(out)
Fig. 28

VIVA – VOCE QUESTIONS: 1. Write verilog program to generate square wave of duty cycle with 66.6 %? 2. Write a program to explain pin – pin delay? 3. Write a verilog program to generate rectangular wave? 4. What are timing constraints? 5. What are the differences between ‘always’ and ‘initial’ statements? 6. How to generate sine wave using verilog coding style?

51

10. Latches

AIM: a) Write the verilog code for D Latch, SR Latch b) Verify the code using test bench PROGRAMME: D Latch: module D_latch(D, Clk, Q); input D, Clk; output Q; reg Q; always @(D or Clk) if (Clk) Q = D; endmodule OUTPUT WAVEFORM:

Fig. 29

SR latch: module SRlatch(q,q_bar,s,r); input s,r; output q,q_bar; nor(q_bar,r,q); nor(q,s,q_bar); endmodule

52 OUTPUT WAVEFORM:

Fig. 30

VIVA – VOCE QUESTIONS: 1. What are user defined primitives and gate primitives? 2. What are the differences between latch and flip flop? 3. What you mean by inferring latches? 4. How to avoid latches in your design? 5. Why latches are not preferred in synthesized design? 6. What is general structure of Verilog code you follow? 7. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?

53

11. Flip-Flops

AIM: a) Write the verilog code for SR Flip-Flop, D Flip-Flop, JK Flip-Flop b) Verify the code using test bench PROGRAMME: SR Flip Flop: module srff(q,s,r,clr,clk); input s,r,clk,clr; output q; reg q; initial q=1'b 0; always@(r or s or clk or clr) begin if(clk==1 && clr==0) begin if(s==0 && r==0) q=q; else if((s==0 && r==1) || (s==1 && r==0)) q=s; else if(s==1 && r==1) $display("Undefined operation performed"); else q=q; end end endmodule

54 OUTPUT WAVEFORM:

Fig. 31

D Flip Flop: module flipflop(D, Clock, Resetn, Q); input D, Clock, Resetn; output Q; reg Q; 1.

always @(posedge Clock) Q = D;

2.

always @(negedge Resetn or posedge Clock) if (!Resetn) Q <= 0; else Q <= D;

endmodule OUTPUT WAVEFORM:

Fig. 32

JK Flip Flop: module jkff(q,qb,j,k,clr,clk); input j,k,clk,clr; output q,qb; reg q,qb;

55 initial q=1'b 0; always @(j or j or posedge clk or posedge clr) begin if(clr==0) q=1’b0; else begin if(j==0 && k==0) q=q; else if((j==0 && k==1) q=1’b0; else if (j==1 && k==0)) q=1’b1; else if(j==1 && k==1) q=~q; qb=~qb; end end endmodule OUTPUT WAVEFORM:

Fig. 33

56 D Flip-Flop using 2x1 mux; module muxdff(D0, D1, Sel, Clock, Q); input D0, D1, Sel, Clock; output Q; reg Q; always @(posedge Clock) if (!Sel) Q <= D0; else Q <= D1; endmodule OUTPUT WAVEFORM:

Fig. 34

VIVA – VOCE QUESTIONS: 1. Write a verilog program for D – flip flop in gate level model? 2. What are the differences between edge triggered flip flop and level triggered flip flop? 3. Explain synthesis of T – flip flop? 4. What is Synthesis? 5. Write a Verilog code for synchronous and asynchronous reset?

57

12. Shift Registers and Counters

AIM: a) Write the verilog code for 4-bit shift register & counters b) Verify the code using test bench PROGRAMME: SHIFT REGISTER 4-bit Shift Register: module shift4(R, L, w, Clock, Q); input [3:0] R; input L, w, Clock; output [3:0] Q; reg [3:0] Q; always @(posedge Clock) if (L) Q <= R; else begin Q[0] <= Q[1]; Q[1] <= Q[2]; Q[2] <= Q[3]; Q[3] <= w; end endmodule OUTPUT WAVEFORM:

Fig. 35

58 8-bit Shift Register: module shift_reg(out,in,load,clk); output [7:0]out; input [7:0]in; input clk; input load; reg [7:0]out; wire [7:0]in; always@(posedge clk) begin if(load) begin out<=in; end else begin out[0]<=out[7]; out[1]<=out[0]; out[2]<=out[1]; out[3]<=out[2]; out[4]<=out[3]; out[5]<=out[4]; out[6]<=out[5]; out[7]<=out[6]; end end endmodule

59 OUTPUT WAVEFORM:

Fig. 36

Generic N-bit Shift Register: module shiftn(R, L, w, Clock, Q); parameter n = 16; input [n-1:0] R; input L, w, Clock; output [n-1:0] Q; reg [n-1:0] Q; integer k; always @(posedge Clock) if (L) Q <= R; else begin for (k=0; k
60

COUNTER Up Counter: module upcount(R, Resetn, Clock, E, L, Q); input [3:0] R; input Resetn, Clock, E, L; output [3:0] Q; reg [3:0] Q; always @(negedge Resetn or posedge Clock) if (!Resetn) Q <= 0; else if (L) Q <= R; else if (E) Q <= Q + 1; endmodule OUTPUT WAVEFORM:

Fig.37

Up-Down Counter: module updowncount(R, Clock, L, E, up_down, Q); parameter n=8; input [n-1:0] R; input Clock, L, E, up_down;

61 output [n-1:0] Q; reg [n-1:0] Q; integer direction; always @(posedge Clock) begin if (up_down) direction = 1; else direction = -1; if (L) Q <= R; else if (E) Q <= Q + direction; end endmodule OUTPUT WAVEFORM:

Fig.38

BCD Counter: module BCDcount(Clock, Clear, E, BCD1, BCD0); input Clock, Clear, E; output [3:0] BCD1, BCD0; reg [3:0] BCD1, BCD0; always @(posedge Clock)

62 begin if (Clear) begin BCD1 <= 0; BCD0 <= 0; end else if (E) if (BCD0 == 4'b1001) begin BCD0 <= 0; if (BCD1 == 4'b1001) BCD1 <= 0; else BCD1 <= BCD1 + 1; end else BCD0 <= BCD0 + 1; end endmodule VIVA – VOCE QUESTIONS: 1. Why constructs are not supported in synthesis? 2. What is gate level net list? 3. Write verilog program for counter using instantiation? 4. Explain delay with respect to counters? 5. What is universal shift register? 6. What are the differences between synchronous and asynchronous counters? 7. What are the components that are needed to construct decade counter?

63

13. Parity Generator

AIM: a) Write the verilog code for Parity Generator b) Verify the code using test bench PROGRAMME: Parity Generator: module parity_9bit(d,even,odd); input[0:8]d; output even,odd; xor xe0(e0,d[0],d[1]), xe1(e1,d[2],d[3]), xe2(e2,d[4],d[5]), xe3(e3,d[6],d[7]), xf0(f0,e0,e1), xf1(f1,e2,e3), xh0(h0,f0,f1), xeven(even,d[8],h0); not xodd(odd,even); endmodule OUTPUT WAVEFORM:

Fig.39

64 Gray to Binary Converter: module GTB(out,in); input [3:0]in; output [3:0]out; assign out[3]=in[3]; xor(out[2],out[3],in[2]); xor(out[1],out[2],in[1]); xor(out[0],out[1],in[0]); endmodule VIVA – VOCE QUESTIONS: 1. What is gate level net list? 2. What is the purpose of ‘parameter’ in verilog? 3. Give the syntax of case statement? 4. Will case always infer priority register? If yes how? Give an example. 5. How do you implement the bi-directional ports in Verilog HDL? 6. What are Different types of Verilog simulators available?

65

14. Finite State Machine

AIM: a) Write the verilog code for FSM using Moore & Mealy models b) Verify the code using test bench PROGRAMME: Moore Machine: module moore (Clock, w, Resetn, z); input Clock, w, Resetn; output z; reg [1:0] y, Y; parameter A = 2'b00, B = 2'b01, C = 2'b10; always @(w or y) begin case (y) A: if (w == 0) Y = A; else Y = B; B: if (w == 0) Y = A; else Y = C; C: if (w == 0) Y = A; else Y = C; default:

Y = 2'bxx;

endcase end always @(posedge Clock or negedge Resetn) begin if (Resetn == 0) y <= A; else y <= Y; end assign z = (y == C); endmodule

66 OUTPUT WAVEFORM:

Fig.40

Finite State Machine Using Moore machine: module moore_fsm (a,clock,z); input a,clock; output z; reg z; parameter st0=0,st1=1,st2=2,st3=3; reg[1:0] moore_state; initial moore_state=st0; always @(negedge clock) begin case (moore_state) st0: begin z=0; if(a) moore_state =st1; end st1: begin z=0; if(a) moore_state=st1;

67 else moore_state=st2; end st2 : begin z=0; if (a) moore_state =st3; else moore_state =st0; end st3: begin if (a) begin moore_state =st0; z=1; end else begin moore_state =st2; z=0; end end endcase end endmodule OUTPUT WAVEFORM:

68 Fig.41

Mealy Machine: module mealy (Clock, w, Resetn, z); input Clock, w, Resetn ; output z ; reg z; reg y, Y; parameter A = 0, B = 1; always @(w or y) case (y) A: if (w == 0) begin Y = A; z = 0; end else begin Y = B; z = 0; end B: if (w == 0) begin Y = A; z = 0; end else begin Y = B; z = 1; end endcase

69

always @(posedge Clock or negedge Resetn) if (Resetn == 0) y <= A; else y <= Y; endmodule OUTPUT WAVEFORM:

Fig.42

VIVA – VOCE QUESTIONS: 1. What is Mealy machine? 2. What is Moore machine? 3. What are the differences between Mealy and Moore machine? 4. What is state diagram? 5. Draw state diagram for module counter? 6. Generate synthesis report for Mealy machine? 7. How to write FSM is verilog?