Layout Design Rule

VLSI Design and Layout Layout Practice Lect5 – Stick Diagram & Scalable Design Rules

2012/8/13

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IC Layout Concept and Examples   

I. II. III.

Stick Diagram Design Rules Layout Verification

















A. Basic Concept Concept 

1. Based on the view point of IC layout, the stick diagram can help us understand the circuit function fun ction and its geometrical location relative to other oth er circuit blocks. VDD



Legend: contact metal 2 metal 1

■ in

















A. Basic Concept Concept 



2. Although the stick diagram is an abstract presentation of real layout, it can use graphical symbols or legend to allocate the circuit to 2diomensional plane and reach the aim same as the physical layout does. 3. The stick diagram is similar to a backbone of the real layout but without the real size and

















B. Notations of the stick diagram

















Stick Diagram 



 

Intermediate representation  between the transistor level and the mask (layout) level. Gives topological information  (identifies different layers and their relationship) Assumes that wires have no width. It is possible  to translate stick diagram automatically to layout layou t with correct design rules.



















Stick Diagram 

1. When the same material (on the same layer) touch or cross, they are connected and belong to the same electrical node.

















Stick Diagram



3. When a metal line needs to be connected to one

















Stick Diagram 

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4. Manhattan geometrical rule: When we use only vertical and horizontal lines In orthogonal to describe circuitry. Boston geometrical rule: The stick diagram also allows curves to describe circuitry.

















Conclusion 

1. Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and layout.. layout

















CMOS Inverter Stick Diagrams 

Basic layout



















CMOS Inverter Stick Diagrams



















CMOS Transmission Gate



















CMOS Stick Diagrams



















CMOS Stick Diagrams



















< Exercise 1 >



















































































































































































































Terminology & Definition  

Max. area of the specific region. Bonding Pad Area, max. = 100um x 100um

















Conventional Layer Definition Layer

Color

Well (p,n)

Yellow

Active Area Area (n+,p+) (n+,p+)

Green

Select (p+,n+)

Green

Polysilicon

Red

Metal1

Blue

Metal2

Magenta

Representation

















SCMOS Design Rules Intra- Layer Layer Design Rules Same Potential

0 or 6

Well

Different Potential

2

9 Polysilicon 2

10 3 Contact or Via Hole

3 2 Select

3

Metal1

Active 2 2

3

Metal2

4

















SCMOS Design Rules 2 4

Via 1

1 5

Metal to Active Contact

1

Metal to Poly Contact 3

2 2

2

















SCMOS Design Rules 2 Select 3 2 1 3

3

2

5



















SCMOS Design Rules

















MOSIS Layout Design Rules 



MOSIS design rules (SCMOS rules) are available at http://www.mosis.org. 3 basic design rules: Wire width

















III. Layout Verification A. Definition  DRC – Design Rule Check 

















Layout Verification  

B. DRC(Design Rule Check) => To check the min. line width and

















Layout Verification 

D. LVS(Layout versus Schematic) => To verify the consistency between Schematic and Layout. For example to check the amount of



















Layout Verification



















Layout Verification



















Concluding Remarks





































Design Rules



















































































































































































































Contact Cut Metal connects to polySi/diffusion by contact cut. Contact area: 2 2 Metal and polySi or diffusion must overlap this contact area by so that the two desired conductors encompass the contact area despite any mis-alignment between conducting layers and the contact hole

















Contact Cut Contact cut – any gate: 2

apart

Why? No contact to any part of the gate.

4 2

















Contact Cut Contact cut – contact cut: 2 apart Why? To prevent holes from merging. merging .

















Rules for CMOS layout Similar to those for NMOS except No 1. Depletion implant 2. Buried contact Additional rules 1. Definition of n-well area

















Rules for CMOS layout To ensure the separation of the PMOS and NMOS devices, n-well supporting PMOS is 6 away from the active area of NMOS transistor transist or..

Why?



















Rules for CMOS layout 2 N-well must completely

















Rules for CMOS layout 2 The threshold implant

















Rules for CMOS layout The p+ diffusion mask defines the areas to receive a p+ diffusion.

2

















Rules for CMOS layout A p+ diffusion is required to effect the ground connection to the substrate. Thus mask also defines this substrate region. It surrounds the conducting material of this contact by

















Rules for CMOS layout Total contact area = 2 4

Layout Design Rule

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