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1. Consider the circuit shown in Figure 1. Reduce the portion of the circuit to the left of terminals a–b to (a) a Thévenin equivalent and (b) a Norton equivalent. Find the current through R=16, and comment on whether resistance matching is accomplished for maximum power transfer. 2. Consider the circuit of Figure 2, including a dependent source. Obtain the Thévenin equivalent at terminals a–b. 3. By means of nodal analysis, find the current delivered by the 10-V source and the voltage across the 10-resistance in the circuit shown in Figure-3 4. For the network shown in Figure 4, find the current delivered by the 10-V source and the voltage across the 3-resistor by means of mesh-current analysis. 5. Determine the voltage across the 20-resistor in the following circuit of Figure-5 with the application of superposition. 6. Use delta–wye transformation for network reduction and determine the current through the 12-ohm resistor in the circuit of Figure-6 7. Determine the Thévenin and Norton equivalent circuits as viewed by the load resistance Rin the network of Figure-7 (i) Find the value of R if the power dissipated by Ris to be a maximum. (ii) Obtain the value of the power in part (b). 8. Reduce the circuit of Figure-8 to a Thévenin and a Norton equivalent circuit. 9. Find the Thévenin and Norton equivalent circuitsfor configuration of Figure-9 as viewed from terminals a–b.
the
10. Obtain the Thévenin and Norton equivalent circuits for the portion of the circuit to the left of terminals a–b in Figure 10, and find the current in the 200-ohm resistance. 11. In the circuit given in Figure 11, determine the currentIthrough the 2-ohm resistor by (a) the nodalvoltage method, and (b) meshcurrent analysis.
12. Find the voltage across the 8-A current source in the circuit of Figure 12 with the use of nodal analysis & Determine the current in the 0.5-resistor of the circuit by mesh analysis.
Figure.1
Figure.2
Figure.3
Figure.4
Figure.5
Figure.6
Figure.7
Figure.8
Figure.9
Figure.10
Figure.11
Figure.12
I!08
1. In an electrical network to neglect a current source the current source is: a) b) c) d)
Open Circuited. Short Circuited. Replaced by a capacitor. Replaced by an Inductor.
2. Which of the following theorem is applicable for both linear and nonlinear circuits? a) b) c) d)
Superposition theorem. Thevenin's theorem. Norton's theorem. none of these.
3. In an electrical network to neglect a voltage source the voltage source is: a) b) c) d)
Open Circuited. Short Circuited. Replaced by a capacitor. Replaced by an Inductor.
4. In figure, the total power consumed is a) b) c) d)
10 12 16 20
W W W W
5. What is maximum power transfer condition? a) b) c) d)
Rs = R L Rs < R L Rs > R L None of the above.
6. In Thevenin’s Theorem which term to be determined? a) b) c) d)
Vth, Isc Vth,Rth Rth, Isc None of the above
7. In Norton’s Theorem which term to be determined? a) b) c) d)
Vth, Isc Vth,Rth Rth, Isc None of the above
8. In Thevenin’s equivalent circuit Rth is Parallel connection with Vth? a) b) c) d)
True False May be None of the above
9. In Norton’s equivalent circuit Rth is Parallel connection with Isc ? a) b) c) d)
True False May be None of the above
10. Star network is also known as a) b) c) d)
T-network X- network Y-network Z-network
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1. Obtain the truth table for the logic block shown in Figure
2. For the NOR and inverter realizations shown in Figure, find the truth table, the type of gate realized, and the expression for the logic output,in each case.
3. Draw the logic diagram for the following Boolean expressions (without any simplification).
4.
5.
6. Draw the logic diagram of an SR latch using only NAND gates, and obtain the truth table for that implementation. 7. J and K are the external inputs to the JKFF shown in Figure. Note that gates 1 and 2 are enabled only when the clock pulse is high. Consider the four cases of operation and explain what happens.
8. Draw a block diagram for a 2-to-4 decoder. Obtain the truth table, and develop a logic diagram. 9. Show a block diagram of a 4-bit, parallel-input shift-right register and briefly explain its operation. 10. What is the basic difference between the weighted resistor and the R–2R ladder D/A converters? I!08 1.
Convert hexadecimal value 16 to decimal.
A.
2210
B.
1610
C.
1010
D.
2010
2. Convert the following decimal number to 8-bit binary. 187 A.
10111011 2
B.
11011101 2
C.
10111101 2
D.
10111100 2
3.The output of an AND gate with three inputs, A, B, and C, is HIGH hen ________. A.
A = 1, B = 1, C = 0
B.
A = 0, B = 0, C = 0
C.
A = 1, B = 1, C = 1
D.
A = 1, B = 0, C = 1
4. The output of an exclusive-NOR gate is HIGH if ________. A.
the inputs are equal
B.
one input is HIGH, and the other input is LOW
C.
the inputs are unequal
D.
none of the above
5.Determine the values of A, B, C, and D that make the sum term
equal to zero.
A.
A = 1, B = 0, C = 0, D = 0
B.
A = 1, B = 0, C = 1, D = 0
C.
A = 0, B = 1, C = 0, D = 0
D.
A = 1, B = 0, C = 1, D = 1
6.Which of the following expressions is in the sum-of-products (SOP) form? A.
(A +
B.
(A )B (CD )
C.
AB (CD )
D.
AB + CD
7. How is a
B )(C + D )
J-K flip-flop
A.
J =
0,
K =
0
B.
J =
1,
K =
0
C.
J =
0,
K =
1
D.
J =
1,
K =
1
made to toggle?
8.A positive edge-triggered D flip-flop will store a 1 when ________. A.
the D input is HIGH and the clock transitions from HIGH to LOW
B.
the D input is HIGH and the clock transitions from LOW to HIGH
C.
the D input is HIGH and the clock is LOW
D.
the D input is HIGH and the clock is HIGH
9.If both inputs of an goes high?
S-R flip-flop
are LOW, what will happen when the clock
A.
No change will occur in the output.
B.
An invalid state will exist.
C.
The output will toggle.
D.
The output will reset.
10. Implementation of the Boolean expression ________. A.
three AND gates, one OR gate
B.
three AND gates, one NOT gate, one OR gate
C.
three AND gates, one NOT gate, three OR gates
D.
three AND gates, three OR gates
results in
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