Best PWBA Design Practices for Optimal EMC, SI, and PI
Jim Herrmann, Principal Engineer AppliedLogix, LLC. Fairport, NY
[email protected]
Presentation Outline Background and history The high speed design challenge Digital signaling fundamentals PWB stack-up and construction – key details Power distribution network (PDN) design approach HyperLynx LineSim & BoardSim: ad hoc intro following talk – if any interest…
1 hour time limit - topic coverage is very brief / “snapshots”, references provided for further investigation **Let’s keep the discussion informal - questions are welcomed and encouraged at any time** 2
Brief Bio 25 years of digital electronics design engineering – always a hands-on practitioner… On-site Field Service Engineer, Kodak (1981 – 1983) Design Engineer (Jr…Sr…Team Leader) Kodak (1984-1995) Hardware Design Manager, Xerox Corp. (1995-1998) Engineering VP, InSciTek Microsystems / Allworx (1998 – 2006) Founder / Managing Partner, AppliedLogix LLC, (2006 – present)
Career-long pursuit of a lean yet robust digital electronics design methodology – still evolving today maximizing the product’s performance versus price ratio Zero defects mindset: quantitative design approach Cannot overlook or “outsource” DFM and DFT Methodology yields predictable / repeatable results and dev schedules
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The High Speed Design Challenge Nicely summarized by Dr. Howard Johnson… “Signal Integrity is not just a ‘nice to know’ subject. It is essential to the proper operation of every high-speed digital product. Without due consideration of the basic signal integrity issues typical high-speed products will fail to operate on the bench and, worse yet, become flaky or unreliable in the field…Maintain a healthy interest in properly balancing your signal integrity, EMC, and manufacturing cost objectives. Get some formal training, constantly keep on the lookout for new tools, and tear apart lots of other people's products to see what the competition is doing. The payoff is easy to understand: better system-level performance, a more reliable product, and an overall reduction is cost”.
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PWBA Design 2010 Moore’s Law has delivered very high performance IC’s with subnanosecond switching times Power delivery – lower DC voltages w/ higher transient currents Output buffers – faster slew rates, lower output impedance
…The PWB physical interconnects are not transparent to the digital signaling… Modern PWBA design methodology – careful analysis and specification of the PWBA physical interconnects combined with “SI aware” component selection and circuit design PWB stack-up, construction, and trace routing Power Distribution Network (PDN) Off-board IO Connectors
Optimal EMC achieved when signal and power integrity addressed in a comprehensive manner
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My “Early Wake Up Call” 1984 – Very first electrical design role on the Kodak 12 MByte floppy disk drive w/ embedded SCSI controller (huh?) SMT was a brand new technology, enabling higher parts density Challenging mixed-signal design with significant digital processing and analog circuits (2) Z80 microprocessors, (4) gate arrays High gain analog read channel; track-following servo control
A split ground plane was implemented for analog / digital isolation First prototype K12 PWBA Passed “smoke-test” and bench-top POST When PWBA mounted onto the disk drive: R/W Channel FAILURE Severe coupling of board emissions into the read/write head
Weeks to determine SRAM signal traces routed over the split GND plane were the source of the interference
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No Free Lunch Design complexity continues to ramp up SOCs and DSPs are larger and faster FPGA performance and gate counts have reached “ASIC proportions” Virtually all modern IC devices produce signaling that has surpassed the high speed effects threshold Hign speed digital design has acquired the complexity of analog and more
Growing number of “low complexity” embedded designs failing EMC Must plan for sufficient development time, budget, and engineering resources to adequately address and manage high speed issues
High Speed Timeline
Low Speed Timeline
Architecture
Architecture
Detailed Design
Detailed Design
PWB Layout
PWB Layout
Prototype Verification
Prototype Verif.
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Defining “High Speed” Digital Signal Edge Rates are the determining factor Higher clock frequencies mandate faster edge rates, thereby inferring high speed signaling issues Simply operating high speed ICs at a lower clock frequency does not eliminate the high speed signal integrity issues
Think signal bandwidth not clock frequency… Digital Signal Bandwidth – the relationship between signal rise time (10% to 90% in nsec), and its bandwidth (in GHz) Empirical approximation: BW ~ 0.35 / rise time Example: rise time = 0.35nsec, then signal bandwidth ~1 GHz.
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No Safe Haven
OSCILLOSCOPE Design file: 6-LAYER STACKUP.FFS Designer: Jim Herrmann HyperLynx V8.0 Comment: Fast / Strong Corner
Recent peer review of very simple “low speed” board schematic. Example net:
6.000
[U7.1 [U2.1 [U7.1 [U2.1
(at (at (at (at
5.000
4.000
V ol t ag e - V -
Single SN74LVC1G14 D-flip-flop driving 4” of trace and a single load. Zout = 12 ohms Output rise = 500ps BW = 700 MHz
V V V V
3.000
2.000
1.000
0.00 DesignFile:6-layerstackup.ffs HyperLynxLineSimV8.0
U7.1
LVC1G14_DBV Y
-1.000
TL2
52.8 ohms 686.222 ps 4.000 in Stackup
U2.1
-2.000
-3.000 0.00 LVC1G14_DBV A
4.000
8.000
12.000 Time (ns)
16.000
Date: Monday Mar. 29, 2010 Time: 19:59:33 Cursor 1, Voltage = 5.507V, Time = 2.923ns Cursor 2, Voltage = 1.783V, Time = 4.575ns Delta Voltage = 3.725V, Delta Time = 1.652ns Show Latest Waveform = YES, Show Previous Waveform = YES
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pin)] pin)] pin)] pin)]
Digital Signaling Fundamentals CMOS output structure - the die I/O pad buffer Modeled as a voltage source (Vs ) and series resistance (Zs) Series terminator (Zst) (optional) acts to increase the source impedance Incident wave amplitude: voltage divider across the lumped source impedance and the line characteristic impedance (Z0)
Vi = Vs (Z0 / (Z0 + Zs+Zst) Any impedance discontinuity along the line generates a reflection Load Impedance Special Cases Open circuit: Rc = 1 Short circuit: Rc = -1 Load = Line: Rc = 0
Reflection Coefficient Rc = (ZL - Z0) / (ZL + Z0) Vi Zs + ZST
Z0
Vr = Vi(Rc) ZL
VS
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Digital Signaling Fundamentals PWB Trace characteristic impedance (Z0) A function of dielectric constant, trace width, trace thickness, and trace height above the return plane(s)
PWB Trace - propagation velocity a function of dielectric constant (Er)
v = c / (Er)1/2 Microstrip (surface) layers: prop delay ~150 psec/inch Magnetic field propagating thru: FR4 below, solder mask, then air above
Internal stripline layers: prop delay ~165 psec/inch Magnetic field propagating thru: FR4 above and below
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High frequency signal return paths Kirchhoff’s Current Law: Sum of the currents entering and leaving a node is zero Low frequency (sine wave < 10 MHz) return: path of least resistance High frequency return: path of least inductance The smallest physical loop area always provides lowest inductance Return current density in ref plane falls off with the square of the distance The approx current density at D is proportional to 1 / (1 + (D / H)2)
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Signal Return Path – Signal Layer Change Three general cases: 1. 2.
3.
The (2) trace layers straddle the same reference plane The (2) trace layers reference different planes, both planes at same potential, e.g. GND The (2) trace layers reference different planes, planes at different DC potential
Implications to PWB stack up and trace routing rules Case 2- apply a GND shorting via grid across entire (x,y) PWB surface
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Signal Return Path – Signal Layer Change Case 3.) The (2) trace layers reference different planes each at a different DC potential. The return current encounters the plane capacitance impedance thereby inducing a voltage drop across this impedance. This impedance drops over time as the current spreads out and traverses a larger capacitive area. This return path impedance (Z) can be estimated as: Z ~ 5 ohm x [plane separation (inches) / time (nsec)] Simple stack-up shown not suitable for commuting very fast edge rate signaling (<< 1 nsec). Deploy thin core PWR//GND construction to minimize the impedance and correspondingly the voltage drop.
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Return Path – Common Design Issue Signal trace routing directly over a split (or other discontinuity) in its reference plane Closely spaced adjacent Vias – anti-pad induced slots Often creates mutual inductive crosstalk (noise margin) Case when many adjacent bus lines cross together
Can increase radiated EMI and lower radiated immunity threshold Degrades rising and falling edge rates (timing margin)
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Return Path – Another Common Mistake Signal return often overlooked / compromised in “homebrew” board-to-board IO connector pin assignment. “Low speed” designs - Limit the ratio of signal pins to shared return pins - Mutual inductance coupling – crosstalk! High speed designs – controlled impedance connector with continuous GND reference recommended. Best practice – ensure that the signal trace reference plane is the same on both boards.
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Pre-layout Phase SI Analysis HyperLynx LineSim can be used for: Stack-up definition Evaluate IO drive strengths and slew rates IBIS Models – I/V characteristics over PVT Component family selections Termination requirements
Determine Bus Topologies, e.g., pt to pt, star, daisy-chain,… Clock Distribution Common Clock topology – clock tree skew management Ensure monotonic clock edges
AC Timing – guesstimate trace lengths and develop initial timeof-flight estimates based on LineSim results Develop max and min trace length budgets to meet setup and hold time requirements
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Clock Distribution Topology Issue Example of a simple, yet prevalent signaling problem: clock edge monotonicity. Customer experiencing design reliability problems – issue easily caught with Hyperlynx simulation (show BoardSim tool in operation) Root cause: very poor clock routing topology, output drive strength, and termination choice With some SI experience, would never consider such a topology (with or w/o simulation tool) Design File: PPC_CLK_original.ffs HyperLynx LineSim V8.0 U5.U4
EP2C20F484C7_p... ppc_clk
TL10
TL9
69.9 ohms 363.405 ps 2.200 in PPC_CLK
69.9 ohms 476.016 ps 2.882 in PPC_CLK
U9.F2
MT48H32M16LFCJ CLK
U8.F2
TL8
69.9 ohms 101.217 ps 0.613 in PPC_CLK
TL11
69.9 ohms 20.954 ps 0.127 in PPC_CLK
U1.A10
Apollo7pm SYSCLK
MT48H32M16LFCJ CLK
U7.F2
TL7
69.9 ohms 101.217 ps 0.613 in PPC_CLK
MT48H32M16LFCJ CLK
TL6
TL5
R25
69.9 ohms 63.401 ps 0.384 in PPC_CLK
62.0 ohms 3.563 ps 0.024 in PPC_CLK
220.0 ohms
1P8V 1.8V
TL4
TL1
62.0 ohms 5.672 ps 0.038 in PPC_CLK
69.9 ohms 34.856 ps 0.211 in PPC_CLK
U6.F2
MT48H32M16LFCJ CLK
TL3
TL2
R24
58.7 ohms 15.114 ps 0.092 in PPC_CLK
62.0 ohms 3.881 ps 0.026 in PPC_CLK
220.0 ohms
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Controlled Impedance PWB Stack-up Specify dielectric thicknesses and trace widths to achieve the same characteristic impedance on all signal layers (50 to 60 ohms is typical target range). All signal layers ~54 ohms here 5 mil trace width on external layers 4 mil trace width on internal layers
Each signal layer has an adjacent plane return layer. Spacing between signal layers (8 mils) is much larger than signal layer to its reference (reduce sig-sig coupling) Always Tradeoffs – Here PWR//GND pairs in middle – giving up some PDN performance (more inductance), but gain routing flexibility – all signals reference only GND and no splits to contend with. 19
Improper Controlled Impedance Stack-up Example from a peer design review provided for a company building relatively high performance embedded systems Their stack-up has several issues They had adopted rather elaborate “standard practice” routing rules (trace to trace separation, including layer-to-layer) to manage crosstalk problems in previous designs (undoubtedly with this same stack-up)
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PDN Design Significant PDN characterization and design optimization work published by Sun Microsystems staff since the 1990’s Larry Smith (now with Altera), Ray Anderson (now with Xilinx) Istvan Novak (still at Sun) http://www.electrical-integrity.com/
Other notable research and papers (try DesignCon archives) IBM - Bruce Archambeault Teraspeed Consulting Group – Steve Weir, Scott McMorrow
Step-by-step PDN “cookbook” process very well defined by Eric Bogatin See the second addition of his book “Signal Integrity – Simplified”, or visit his website www.bethesignal.com Altera’s FPGA PDN design spreadsheet tool – follows Eric’s methodology Spreadsheet tool (newest release now requires Quartus user license) Altera application note AN-574 Printed Circuit Board Power Delivery Network Design Methodology http://www.altera.com/technology/signal/power-distribution-network/sglpdn.html?GSA_pos=2&WT.oss_r=1&WT.oss=pdn%20tool 21
Power Distribution Network (PDN) Overarching Design Principle – Careful attention to MINIMIZE the inductance of the interconnects thereby reducing the voltage rail collapse noise voltage: V = Ldi/dt Lumped equivalent circuit model of a typical PWBA PDN:
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The PDN Design Process 1. 2.
Identify the highest current devices on the PWBA Determine their max actual operating current Estimate the max load step transient current for each
3. 4.
5. 6.
Focus on the largest transient current device first Calculate the required PDN target impedance Ztarget = (Vnominal)(%AC ripple/100) / MaxTransientCurrent Estimate the IC package cutoff frequency Using the PDN spreadheet tools (1-D, lumped models) experiment with the type and quantity of capacitors required to achieve the target impedance across the frequency range Adjust the location (within stackup), dielectric thickness, and number of PWR // GND plane pairs to meet Ztarget over frequency range
7.
Repeat process for next IC (now w/ planes locked down)
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PDN - Decoupling Capacitor Array Decoupling Capacitors – Selection and Mounting MLCC package size and mounting inductance are the dominant factors. Recommend 0402 package with side-attach vias with minimum trace attach as the baseline high frequency decoupling capacitor footprint
Minimize distance Minimize distance
0.006” 0.006”
High freq caps
Bulk decoupling caps
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Via-in-Pad Process Option Enhances Cap Mounting Via Non-conductive Fill-and-plate (“via-in-pad”) Can reduce the mounting inductance of SMT components (w/ ~15% bare board cost adder) Unique capability to mount 0402 caps directly to the non-component side vias of 1 mm BGA Center the 0.0098” vias within the 0402 SMT pads. 0.014”
0402 MLCC
0.026”
0.020” 0.010”
Bulk Decoupling Cap
Center of 0.0098 via hole to pad inner edge = 0.010” min.
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PDN Decoupling Capacitor Selection Decoupling Capacitor Selection Strategies Impedance versus frequency plots shown for (1) each 1.0 uF, 0.1uF, and 0.01 uF – all same package “Big-V” single value array vs. Multi-value array Aside: avoid high-Q, NPO/COG capacitors – some ESR provides dissipative effect – damps plane resonance
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Decoupling Capacitor Selection Strategies Generic example of multi-value capacitor approach Several different capacitor values (and package sizes) all applied in as needed quantities, goal of carefully “sculpting” the impedance profile 9 different values, 23 total caps shown here
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Example: Stratix2 FBGA-1152 1.2V Core Voltage Big-V approach deployed: required (58) 0402 1.0 uF X5R capacitors Via-in-pad utilized with the 1 mm BGA 16-layer PWB with 2-mil PWR//GND dielectric spacing Ztarget = 6.8 mohms, out to 50 MHz FPGA has both on package and on-die decoupling
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The PWB Layout Process Do not “toss responsibility over the fence” to the PWB layout service bureau. The design team must specify and manage: Define Detailed Routing Constraints Define Component placement Define the PWB stack-up Define the Via Pad-stack
Work closely with the layout service bureau and the PWB fabricator– “trust, but verify”…
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PWB Via Pad-stack Considerations Via pad-stack definition - Know the IPC guidelines and design to your chosen DFM limits (i.e.,Class2 or Class 3) Drill diameter Aspect ratio: board thickness to drill diameter
Pad diameter Anti-pad diameter Careful attention to the anti-pad diameter – keep as small as possible - effects plane DC drop and spreading inductance below BGAs. Do not let service bureau choose arbitrarily.
Consider eliminating via thermal relief (except for through-hole components)
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IPC Pad-stack Guidelines – As reported in Printed Circuit Design & Manufacture, Sept 2007. Gil White, DDI Global
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PWB Stack-up Best Practice Attributes Controlled impedance for all signal traces Every signal layer has an adjacent plane reference layer If (2) signal layers are adjacent (dual-stripline), then provide additional separation between the signal layers ensure orthogonal routing is deployed
PWR // GND pairs – thin dielectric spacing, move towards the surface layer with highest transient current IC(s) if absolute minimum inductance needed Split power planes – very often required, must avoid trace crossing Tie all GND planes together with x,y via grid –– commuting signal return current between GND layers Know the PWB fabrication process (see IPC specs) and PWB fabricator’s manufacturing capabilities. A few of the best: DDI Global Merix Endicott Interconnect TTM Technologies
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Post – Route Analysis Perform after initial layout and before committing to board fabrication HyperLynx Boardsim based analysis Confirm that the signal integrity, AC timing, and crosstalk goals have all been met. Batch mode analysis capabilities can accelerate the verification process by assessing and reporting Signal time-of-flights Overshoot levels and non-monotonic behavior Crosstalk levels
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Functional Problems – Not Always a SI or PI Issue 1.
Simple behavioral level logic/functional failure Corner cases / boundary conditions HW/SW interaction Silicon device errata
2.
Metastability All asynchronous inputs to synchronous logic must be routed through 1 or more synchronizing latches before that signal is utilized. Latches must eliminate any setup or hold time violations to succeeding logic.
3.
Worst Case AC Timing analysis – neglected or incomplete Time of flight (TOF) ignored or incorrect Lack of analysis over full PVT Impact of SI effects not included
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Summary Modern PWBA design – the challenges are well documented Significant information and resources are readily available SI & PI Simulation Tools Textbooks White papers / App Notes Consultants / Formal Training Classes
Read up, then develop and apply your own best practices methodology Strive to enhance your technical understanding and design process with each iteration Join the SI-LIST email reflector for a daily dose of the state of the art http://www.freelists.org/webpage/si-list
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References Text Books Eric Bogatin, Signal Integrity - Simplified, ISBN: 0-13-066946-6. Howard Johnson, Martin Graham, High-Speed Signal Propagation – Advanced Black Magic, ISBN: 013-084408-X. Howard Johnson, Martin Graham, High-Speed Digital Design - A Handbook of Black Magic, ISBN: 013-395724-1. Istvan Novak, Jason Miller, Frequency-Domain Characterization of Power Distribution Networks, ISBN: 978-1-59693-200-5. S. Hall, G. Hall, J. McCall, High Speed System Design – A Handbook of Interconnect Theory and Practices, ISBN: 0-471-36090-2. S. Hall, H. Heck, Advanced Signal Integrity for High-Speed Digital Designs, ISBN: 0-471-36090-2.
Websites www.signalintegrity.com www.bethesignal.com www.electrical-integrity.com www.teraspeed.com www.ipblox.com http://www.altera.com/technology/signal/sgl-index.html www.mentor.com/products/pcb-system-design www.pcb.ddiglobal.com/Technology/index.cfm 36
