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INTRODUCTION
Since their inception in the late 1950s, planar transistors have acted as the basic building block of microprocessors. The scaling of planar transistors requires the scaling of gate oxides and source/drain junctions. However, as these transistor elements become harder to scale, so does the transistor gate length. The scaling of planar transistors is getting more difficult due to the worsening electrostatics and short-channel performance with reducing gate-length dimension. In a multigate device, the channel is surrounded by several gates on multiple surfaces, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance. Non-planar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics. A new transistor architecture that can significantly improve the electrostatics and short-channel performance is the tri-gate transistor, as shown in Figure 1. This transistor, which can be fabricated either on the SOI substrate or standard bulk-silicon substrate, has a gate electrode on the top and two gate electrodes on the sides of the silicon body.
Figure 1. Tri-Gate Transistor.
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HISTORY OF TRANSISTORS
A transistor is a semiconductor device used to amplify and switch electronic signals and power. It is composed of a semiconductor material with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current flowing through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits. The transistor is the fundamental building block of modern electronic devices, and is ubiquitous in modern electronic systems. Following its development in the early 1950s the transistor revolutionized the field of electronics, and paved the way for smaller and cheaper radios, calculators, and computers, among other things. The thermionic triode, a vacuum tube invented in 1907, propelled the electronics age forward, enabling amplified radio technology and long-distance telephony. The triode, however, was a fragile device that consumed a lot of power. Physicist Julius Edgar Lilienfeld filed a patent for a field-effect transistor (FET) in Canada in 1925, which was intended to be a solid-state replacement for the triode. Lilienfeld also filed identical patents in the United States in 1926 and 1928. However, Lilienfeld did not publish any research articles about his devices nor did his patents cite any specific examples of a working prototype. Since the production of high-quality semiconductor materials was still decades away, Lilienfeld's solid-state amplifier ideas would not have found practical use in the 1920s and 1930s, even if such a device were built. In 1934, German inventor Oskar Heil patented a similar device. From November 17, 1947 to December 23, 1947, John Bardeen and Walter Brattain at AT&T's Bell Labs in the United States, performed experiments and observed that when two gold point contacts were applied to a crystal of germanium, a signal was produced with the output power greater than the input. Solid State Physics Group leader William Shockley saw the potential in this, and over the next few months worked to greatly expand the knowledge of semiconductors. The term transistor was coined by John R. Pierce as a portmanteau of the term "transfer resistor". According to Lillian Hoddeson and Vicki Daitch, authors of a recent biography of John Bardeen, Shockley had proposed that Bell Labs' first patent for a transistor should be based on the fieldeffect and that he be named as the inventor. Having unearthed Lilienfeld‟s patents that went into obscurity years earlier, lawyers at Bell Labs advised against Shockley's proposal since the idea of a field-effect transistor which used an electric field as a “grid” was not new. Instead, what Bardeen, Brattain, and Shockley invented in 1947 was the first bipolar point-contact transistor. In acknowledgement of this accomplishment, Shockley, Bardeen, and Brattain were jointly awarded the 1956 Nobel Prize in Physics "for their researches on semiconductors and their discovery of the transistor effect." In 1948, the point-contact transistor was independently invented by German physicists Herbert v Babu Banarasi Das Northern India Institute of Technology, Lucknow
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Mataré and Heinrich Welker while working at the Compagnie des Freins et Signaux, a Westinghouse subsidiary located in Paris. Mataré had previous experience in developing crystal rectifiers from silicon and germanium in the German radar effort during World War II. Using this knowledge, he began researching the phenomenon of "interference" in 1947. By witnessing currents flowing through point-contacts, similar to what Bardeen and Brattain had accomplished earlier in December 1947, Mataré by June 1948, was able to produce consistent results by using samples of germanium produced by Welker. Realizing that Bell Labs' scientists had already invented the transistor before them, the company rushed to get its "transistron" into production for amplified use in France's telephone network. The first silicon transistor was produced by Texas Instruments in 1954. This was the work of Gordon Teal, an expert in growing crystals of high purity, who had previously worked at Bell Labs. The first MOS transistor actually built was by Kahng and Atalla at Bell Labs in 1960.
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MOSFET Scaling and Moore’s Law In 1965, Gordon Moore published his famous paper describing the evolution of the transistor density in integrated circuits. He predicted that the number of transistors per chip would quadruple every three years. This prediction became known as Moore’s law and has been remarkably followed by the semiconductor industry for the last forty years (Figure1.1).Since the early 1990‟s semiconductor companies and academia have teamed up to predict more precisely the future of the industry. This initiative gave birth to the International Technology Roadmap for Semiconductors (ITRS) organization. Every year, the ITRS issues are port that serves as a benchmark for the semiconductor industry. These reports describe the type of technology, design tools, equipment and metrology tools that have to be developed in order to keep pace with the exponential progress of semiconductor devices predicted by Moore‟s law. Figure 1.1 shows the evolution of the number of transistors per chip predicted by the ITRS 2005 for DRAMs and high-performance microprocessors. The semiconductor industry‟s workhorse technology is silicon CMOS, and the building block of CMOS is the MOS transistor, or MOSFET(MOS fieldeffect transistor). In order to keep up with the frantic pace imposed by Moore‟s law, the linear dimensions of transistors have reduced by half every three years. The sub-micron dimension barrier was overcome in the early 1980‟s, and in 2010 semiconductor manufacturers will produce transistors with a 20nm gate length on a regular basis. Since the first integrated circuit transistors were fabricated on “bulk” silicon wafers. At the end of the 1990‟s, however, it became apparent that significant performance improvement could be gained by switching to a new type of substrate, called SOI (Silicon-On-Insulator) in which transistors are made in a thin silicon layer sitting on top of a silicon dioxide layer. SOI technology brings about improvements in both circuit speed and power consumption. In the early 2000‟s major semiconductor companies, including IBM, AMD and Free scale, began manufacturing microprocessors using SOI substrates on an industrial scale. SOI devices offer the advantage of reduced parasitic capacitances and enhanced current drive.
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Gate Geometry and Electrostatic Integrity Short-channel effects arise when control of the channel region by the gate is affected by electric field lines from source and drain. These field lines is illustrated graphically in Figure 1.2. In a bulk device (Fig. 1.2.A), the electric field lines propagate through the depletion regions associated with the junctions. Their influence on the channel can be reduced by increasing the doping concentration in the channel region. In very small devices, unfortunately, the doping concentration becomes too high (1019cm-3) for proper device operation. In a fully depleted SOI (FDSOI) device, most of the field lines propagate trough the buried oxide (BOX) before reaching the channel region (Fig. 1.2.B). Short channel effects in FDSOI devices may be better or worse than in bulk MOSFETs, depending on the silicon film thickness, buried oxide thickness, and doping concentrations. Short-channel effects can be reduced in FDSOI MOSFETs by using a thin buried oxide and an underlying ground plane. In that case, most of the electric field lines from the source and drain terminate on the buried ground plane instead of the channel region (Figure 1.2.C). This approach, however, has the inconvenience of increased junction capacitance and body effect. A much more efficient device configuration is obtained by using the doublegate transistor structure. This device structure was first proposed by Sekigawa and Hayashi in 1984 and was shown to reduce threshold voltage roll-off in short-cannel devices. In a doublegate device, both gates are connected together. The electric field lines from source and drain underneath the device terminate on the bottom gate electrode and cannot, therefore, reach the channel region (Fig. 1.2.D). Only the field lines that propagate through the silicon film itself can encroach on the channel region and degrade short-channel characteristics. This encroachment can be reduced by reducing the silicon film thickness. ((fiigur od fdsoi))
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MULTIGATE DEVICES A multigate device or multiple gate field-effect transistor(MuGFET) refers to a MOSFET which incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor or MIGFET. Multigate transistors are one of several strategies being developed by CMOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's Law which states that the number of transistors on a chip will double about every two years. Intel has kept that pace for over 40 years, providing more functions on a chip at significantly lower cost per function. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-k/metal gate materials. In a multigate device, the channel is surrounded by several gates on multiple surfaces, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance. Non-planar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics.
MULTIGATE SOI MOSFETs : The first SOI transistor dates back to 1964. These were partially depleted devices fabricated on silicon-sapphire (SOS) substrates. SOS technology was successfully used for numerous military and civilian applications and is still being used to realize commercial HF circuits in fully depleted CMOS. Once the first SOI substrates (the insulator is now silicon dioxide) were available for experimental MOS device fabrication, partially depleted technology the natural choice derived from SOS experience. Partially depleted CMOS continues to be used nowadays and several commercial IC manufacturers have SOI products and product lines such as microprocessors and memory chips. Variations on the partially depleted SOI MOSFET theme include devices where the gate is connected to the floating body. These devices, which have been called „„voltage-controlled bipolar-MOS device‟‟, „„hybrid bipolar-MOS device‟‟, „„gatecontrolled lateral BJT‟‟, „„multiple-threshold CMOS‟‟, „„dynamic threshold MOS‟‟, or „„variable-threshold MOS‟‟ have ideal subthreshold characteristics, reduced body effect, improved current drive, and superior HF characteristics. They are mostly used for very lowvoltage (0.5 V) applications. Figure 1.6 shows the “Family Tree” of SOI MOSFETs and shows the evolution from partially depleted, single-gate devices to multi-gate, fully depleted structures. Partially depleted silicon ix Babu Banarasi Das Northern India Institute of Technology, Lucknow
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MOSFETs are the successors of earlier SOS (Silicon-On-Sapphire) devices. PDSOI MOSFETs were first used for niche applications such as radiation-hardened or high-temperature electronics. At the turn of the century PDSOI technology became main stream as major semiconductor manufacturers started to use it to fabricate high-performance microprocessors. The low-voltage performance of PDSOI devices can be enhanced by creating a contact between the gate electrode and the floating body of the device. Such a contact improves the sub threshold slope, body factor and current drive, but limits the device operation to sub-1V supply voltages. Fully depleted SOI devices have a better electrostatic coupling between the gate and the channel. This results in a better linearity, sub threshold slope, body coefficient and current drive. FDSOI technology is used in a number of applications ranging from low-voltage, low-power to RF integrated circuits.
DELTA/FinFET structure
Gate-all-around (GAA) MOSFET
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SOI MOSFET family tree
The triple-gate MOSFET is a thin-film, narrow silicon island with a gate on three of its sides. xi Babu Banarasi Das Northern India Institute of Technology, Lucknow
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Implementations include the quantum-wire SOI MOSFET and the tri-gate MOSFET. Improved versions feature either a field-induced, pseudo-fourth gate such as the P-gate device and the Xgate device. The structure that theoretically offers the best possible control of the channel region by the gate is the surrounding-gate MOSFET. Such a device is usually fabricated using a pillarlike silicon island with a vertical-channel. Such devices include the CYNTHIA device (circularsection device, Fig. 5) and the pillar surrounding-gate MOSFET (square-section device).
Triple-gate SOI MOSFET
CYNTHIA/surrounding-gate MOSFET structure
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Current drive of multiple-gate SOI MOSFETs The current drive of multiple-gate SOI MOSFETs is essentially proportional to the total gate width. For instance, the current drive of a double-gate device is double that of a single-gate transistor with same gate length and width. In triple-gate and vertical double-gate structures all individual devices need to have the same thickness and width. As a result the current drive is fixed to a single, discrete value, for a given gate length. To drive larger currents multi-fingered devices need to be used. The current drive of a multi-fingered MOSFET is then equal to the current of an individual device multiplied by the number of fingers (also sometimes referred to as „„fins‟‟ or „„legs‟‟). Considering a pitch P for the fingers, the current per unit device width is given by: ID = ID0 (W + 2tsi)/P where ID0 is the current of a unit-width, planar, single gate device, and where W is the width of each individual finger, tsi is the silicon film thickness, and P is the finger pitch (Fig. 6). The FinFET device achieves high current drive through the use of a relatively thick silicon thickness. In that device there is no current flow at the top of the silicon island, such that ID = ID0 (2tsi/P). In triple gate devices (where tsi= W) the finger pitch needs to be smaller than 3W to obtain a larger current drive than in a single-gate, planar device occupying the same silicon real estate.
Cross-section of a multi-fingered triple-gate MOSFET (left) and SEM picture of the fingers (right)
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SHORT CHANNEL EFFECT: It is possible to predict how small the silicon film thickness should be in multiple-gate devices to avoid short-channel effects (or, at least, to maintain a decent sub threshold swing). Sub threshold swing degradation and other short-channel effects are caused by the encroachment of electric field line from the drain on the channel region, thereby competing for the available depletion charge, and reducing the threshold voltage.
Definition of coordinate system in a multiple-gate device. Gate-induced fields are in the x- and z-directions. Drain penetration field is in the y-direction.
Fig. 7 shows how the gates and the drain compete for the depletion charge. Gate control is exerted in the yand z-directions and competes with the variation of electric field in the xdirection due to the drain voltage. The one-dimensional analysis of a fully depleted device yields a parabolic potential distribution in the silicon film in the y (vertical) direction.
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Triple- gate structures It is quite clear from the above considerations, than the surrounding-gate structure offers the best possible characteristics in terms of current drive and short channel effects control. All surrounding-gate devices reported in the literature have a vertical-channel and have a non-planar nature, and the source and drain are situated at different depths in the silicon film (Fig. 5). It is, however, possible to design and fabricate quasi-surrounding- gate MOSFETs using a process similar to that used to fabricate triple-gate SOI MOSFETs. Such devices are called either P-gate [39,40] or X-gate [41] MOSFETs (Fig. 9). These devices are basically triple gate devices with an extension of the gate electrode below the active silicon island, which increases current drive and improves short-channel effects. The gate extension can readily be formed by slightly over etching the buried oxide (BOX) during the silicon island patterning step. The gate extension forms a virtual, field induced gate electrode underneath the device that can block drain electric field lines from encroaching on the channel region at the bottom of the active silicon. Instead the lines terminate on the gate extensions. This gate structure is very effective at reducing shortchannel effects. Such devices can be called 3þ (triple-plus)-gate devices because their characteristics lie between those of triple- and quadruple-gate devices. Fig. 10 presents the equipotential line distribution in (A) a triple-gate, (B) a quadruple-gate, and (C) Pi-gate device. The gate length silicon film thickness and width are 30, 50, and 50 nm respectively. The gate voltage and substrate (back gate) voltages are 0V, while the drain voltage is 1 V. Encroachment of electric field from drain on the channel region can be seen in the triple-gate device, but not in the Pi-gate and quadruple-gate devices. These contour plots illustrate the effectiveness of the field-induced, pseudo back gate created by the gate extension. Fig. 11 compares the sub threshold swing of transistors with 2–4 gates with that of a P-gate device. Increasing the number of gates improves the sub threshold swing because the control of the channel region by the gate(s) becomes more effective and because multiple gates offer more shielding plates protecting the channel region from the electric field lines from the drain. It should be noted that the performances of the P-gate structure are very close to those of a 4-gate device.
P-gate (Pi-gate) and X-gate (Omega-gate) MOSFET cross-sections
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Contour plot of potential in a triple-gate device (A), a quadruple-gate device (B) an a Pi-gate device (C).
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TRI-GATE TRANSISTORS Tri-gate or 3-D are the terms used by Intel Corporation to describe their non-planar transistor architecture planned for use in future microprocessors. These transistors employ a single gate stacked on top of two vertical gates allowing for essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than current transistors. This allows up to 37% higher speed, and a power consumption at under 50% of the previous type of transistors used by Intel. Intel explains, "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)." The world‟s first demonstration of a 22nm microprocessor --code-named Ivy Bridge --that will be the first high-volume chip to use 3-D Tri-Gate transistors. Further to increase the drive strength for increased performance, multiple fins are used. Figure 2.a shows such a design with just a single fin while that of figure 2.b and figure 2.c show designs with two and three fins respectively.
Figure 2.a Design with a single Fin
Figure 2.b Design with a two Fins
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Figure 2.c Design with a three Fins.
PERFORMANCE TEST RESULTS The performance tests were done by Intel with other planar devices of different technologies and the test results are obtained for Gate voltage versus Channel current shown in figure 3 (fig 3.a and fig 3.b) and Operating Voltage versus Transistor Gate Delay shown in figure4 (fig4.afig4.d).
Figure 3.a Comparison of Planar and Tri-Gate
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Figure 3.b comparison of Planar and Tri-Gate with and without reduced threshold voltage
Transistor Gate Delay :
Fig.4.a Operating voltage Vs Gate delay
Fig. 4.b operating voltage Vs Gate delay
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Fig. 4.c operating voltage Vs Gate delay
Fig. 4.d operating voltage Vs Gate delay
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CONCLUSION As transistors get smaller, parasitic leakage currents and power dissipation become significant issues. By integrating the novel three-dimensional design of the tri-gate transistor with advanced semiconductor technology such as strain engineering and high-k/metal gate stack, Intel has developed an innovative approach toward addressing the current leakage problem while continuing to improve device performance. Because tri-gate transistors greatly improve performance and energy efficiency, they enable to extend the scaling of silicon transistors. Intel expects that the tri-gate transistors could become the basic building block for microprocessors in future technology nodes. The technology can be integrated into an economical, high-volume manufacturing process, leading to high-performance and low-power products.
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Reference 1)http://www.intel.com/technology/mooreslaw 2)http://en.wikipedia.org/wiki/Multigate_device 3)http://www.intel.com(*pdf) files downloaded: a)Trigate_press_briefing_0606 b) Intel_Transistor_Backgrounder c) 22nm-Details_Presentation d)22nm-Announcement_Presentation 4) Vaidhyanadhan Subramanian- Multiple gate field effect transistior for future CMOS technologies- http:// www.tr.ieitejournals.org 5) Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew Metz, Willy Rachmady, Marko Radosavljevic, Uday Shah, Nancy Zelick and Robert Chau- Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering- Components Research, Technology and Manufacturing Group, Intel Corporation, Mail Stop RA3-252, 5200 NE Elam Young Parkway, Hillsboro 97124, USA Email :
[email protected].
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