A Course on
Design of of Digital Digital VLSI VLSI Systems Systems & Circuits
By Pragnan Chakravorty . .
,
,
M.Tech (IIT Kharagpur), (IIT Kharagpur), MIEEE Member IEEE(USA) Member IEEE(USA) :‐ Communication. Soc, Microwave Theory and Theory and Techniques Techniques Soc, IEEE Standards IEEE Standards Soc.
INTRODUCTION TO INTEGRATED CIRCUITS
How is a VLSI Circuit Different? Unlike conventional electronic circuits, Transistors in a VLSI/ Integrated Circuits are , , concatenated so as to reduce the lengths of interconnects. The interconnects are made as the final layer of fabrication known as metallization layer. Metallizations are now no w do done ne us usin in ol si sili liccon. Th The e ab abil ilit it to man anii ul ula ate th the e ar area ea vol olum ume e occ ccu u ie ied db the carved transistors and the interconnects between them renders a tremendous scope sc ope of devi device ce miniatur miniaturiz izat ation ion /scali /scaling ng and a ver very y lar large ge scale integr integrat ation ion over a small space.
SSI, MSI, LSI,VLSI,ULSI:
There has been a tremendous rise in the number of devices integrated into a sing (conventionally 10mm x 10mm area chip) in the past few decades as a result the s device integration integration has been categ categorize orized d as follows: Device Integration Table: S.No
Category
Year
Number of ev ces
1
Small Scale Integration (SSI)
1964
05 ‐to‐ 20
2
Medium Scale Integration (MSI)
1967
20 ‐to‐ 200
3
Large Scale Integration (LSI)
1972
200 ‐to‐ 2000
4
Very Large Scale Integration (VLSI)
1978
2000 ‐to‐ 20000
5
Ultra Large Scale Integration (ULSI)
1989
20000 ‐to‐ ?
Moor’s Law:
In 1965, a Caltech Professor, Gordon Moore observed that plotting the number of tran logari loga rithm thmic ic sca scale. le. At the tim time, e, he fo foun und d tr tran ansis sisto torr co coun untt do doub ublin ling g ev every ery 18 mo mont nt observation has been called Moore’s Law and has become a self ‐fulfilling prophecy Moor’s graph compared with actuality
t n u o C r o t s i s n a r T
Advantages of High of High Scale Integration/Device Miniaturization:
The mo most im im ortant me messa e her here e is is th that th the lo lo ic co com le lex xit er chi ha (and still is) increasing exponentially. The monolithic integration of a large nu of functions on a single chip usually provides: Less area/volume and therefore, compactness Less power consumption Less testing requirements at system level
,
‐
Higher speed, due to significantly reduced interconnection length Significant cost savings due to batch processing
Less sser er fab abri rica cati tion on Le
erro er rorr /H /Hii he herr iel ield d du due e to ba batc tch h roc oces essi sin n
VLSI Design Flow
A VLSI system is a multi domain system where designs need to be carried ou e av ora eve s to p ys y s ca ayout eve s. t n eac oma n t e es gn categorized into certain levels of abstraction and then the designs need to certain hierar hierarchically chically categoriz categorized ed steps.
Domains of Design: of Design: Domains are different distinct categories over which any engineering system spans. There can be three such major domains stated below Behavioral domain: Which describes the behavior of of the the system for example transmitting behavior of of a a transmitter system. Structural domain: Which describes the structure of of the the system for example and how are the various amplifiers ,oscillators, filters etc are structured in the transmitter system.
Geometrical layout domain. Describe the physical layout or placement of diff components or devices in a system for example the placement and connection
Generalized Design Flow
The Y Chart The Y‐chart (first introduced by D. Gajski) shown in Fig. illustrates a design flo most og c c ps, us us ng resemble the letter Y.
es gn ac act v t es on on t ree
erent ax axes
oma ns
Levels of Abstraction of Abstraction Domains can further be hierarchically divided into different levels of of design design a st stra ract ct on on.. as asss ca y, t ese ave nc u e t e o ow ng for digital chips: Architectural or functional level
Circuit level
description domains and levels of abstraction is elegantly shown by
‐ In th this is di diag agrram am,, th the e th thrree rad adia iall line li ness rep eprres esen entt th the e be beha havi vior oral al,, struc st ructur tural, al, and ph phys ysica icall dom domains ains.. The annular regions between conce co ncentr ntric ic cir circle cless sho show w dif diffe fere rent nt levels of abstraction.
Design Hierarchy
The levels of abstraction are generic divisions which can map designs of one d nto an anot er. oma n sp spec c v s ons o t e eve s o a stract ons ar ar hier hi erar arch chic ical al di divi visi sio ons ns.. Th The e hi hier erar arcchi hiccal de desi sign gn ap appr proa oach ch red educ uces es th the e complexity by dividing the large system into several sub‐modules
Concepts of Regularity, of Regularity, Modularity and Locality
Though the design complexity reduces down with hierarchical sub‐modules su mo u e t emse ves must ave some consonance an ntegr ty w t eac so as to furth the er simpl pliify the desig ign n process and make th the em effec ecttiv consonance between the sub‐modules are brought in by the following concept
Regularity: Regularity is the division of the hierarchy into a set of similar bu blockss (mod block (modules/ ules/sub sub‐modu dule les) s).. Reg egul ula ari rity ty can exi xisst at al alll le lev vel elss of th the e
gate level, a finite library of fixed‐height, variable‐length logic gates can be use
Modularity: Mo Modu dula lari rity ty stat ates es th tha at mo modu dule les/ s/su sub b‐modules have well functions and interfaces. If modules/sub‐modules are “well‐formed,” the inter with other modules/sub‐modules can be well characterized.
Locality: Locality is the localized composition of components with in a modul modu mo dule le so that they they do no nott in inte terrac actt wi with th ot othe herr mo modu dules les//su sub b‐modules. The internals of a module/sub‐modules are unimportant to other modules/sub‐mo
VLSI Design Styles/Methods
The VLSI design styles or methods depend upon the target IC platform or sta De endin u on the the IC standa darrds th the de desi n st st le var and ha have la lattform s limitations and flexibility or advantages and disadvantages.
Complex Programmable Logic Device(CPLD)
CPLD is a single device with multiple simple progr programma ammable ble logic devices(SPL devices(SPL as rogramma e rray og c or ener c rray og c . s an based on sum of products (SOP) architecture with a programmable AND array fixed OR array PLA/GLA CKT View
PLA/GLA Block Diagram
CPLD Block Diagram
Field Programmable Gate Array (FPGA) Design
A typical field programmable gate array (FPGA) chip consists of I/O buffers, an , programming of the interconnects is implemented by programming of RAM whose output terminals are connected to the gates of MOS pass transistors. G and detailed detailed blocks blocks of an FPGA are shown shown below. below.
The LUT is a g ta memory that stores the truth table of the Boolean
Configurable Logic Block (CLB): A simple CLB (model XC2000 from XILINX) is above where it consists of four signal input terminals (A, B, C, D), a clock , , , The LUT is a digital memory that stores the truth table of the Boolean function generate any function of up to four variables or any two functions of three vari
Gate Array/ Sea of Gates of Gates Design
While the design implementation of the FPGA chip is done with user program that of the gate array is done with metal mask design and processing. Gate implementation requires a two‐step manufacturing process: The first phase, w based on generic (standard) masks, results in an array of uncommitted transist each GA chip. These uncommitted chips can be stored for later customization, is completed by defining the metal interconnects between the transistors array
Standard Cell Based Design
In this design style, all of the commonly used logic cells are developed, characte and an d sto store red d in in a st stan anda darrd cell cell lib librrar . A t ic ical al li libr brar ar ma co cont ntai ain n a few hu hund nd including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D ‐latche flip‐flops. It is almost a full custom design but for the predesigned cells which be customiz customized. ed.
Full Custom Design
In full custom design the customization starts at transistor level itself. The
General Purpose IC & ASSP System Design
S stem level di it ital desi ns ns are often racticall done b ro ra rammin purpose ICs. These general purpose ICs are programmed using high level lang and an d ar are e di difffer eren entt from th the e ASI SICs Cs de desc scrrib ibed ed so far ar.. Th Thes ese e IC ICss in incl clud ude e micr mi crop opro roces cesso sorrs mi micr croc ocon ontr trol oller lers, s, MI MIPS PS , RIS RISC C an and d SI SISC SC pr proc ocess essor ors. s. Ap Appl pl Spec Sp ecif ific ic Sys yste tem m Pr Proc ocess essor ors(A s(ASS SSP Ps) ar are e al also so a ki kind nd of de dedic dicat ated ed ge gene nerral proces esssors such as DSP processors which are programmed usin ing g hi hig g languages.
DESIGN & FABRICATION ASPECTS of Standard Cell Standard Cell Based Based Design Design Style
Basic Steps of Fabrication of Fabrication Process Each processing step requires that certain areas are Consequently, the integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In genera , a ayer must e patterne e ore t e next laye la yerr of ma mate teri rial al is ap appl plie ied d on ch chip ip.. Th The e pr proc oces esss used to transfer a pattern to a layer on the chip is called lithography/Photolithography lithography/Photolithography.. Since each layer has its own distinct patterning requirements, the th e li lith thog ogrrap aphi hicc se sequ quen ence ce mu must st be re repe peat ated ed fo forr every layer, using a different mask Figure at the right shows simplified process sequence for fabrication of the n‐well CMOS inte integr grat ated ed circ circui uitt with with a sing single le poly polysi sili lico con n lay layer, er, showing only major fabrication steps.
Lithographic Steps of Patterning of Patterning
Set of Masks of Masks for Patterning
The The cros crosss‐section view is of an inverter
In a CMOS circuit circuit fabr fabrica icatio tion, n, the hypot ypothe heti tica call set set of six six mask masks: s: n‐ well well,, poly polysil silic icon on,, n+ diffu diffusio sion, n, p+ dif diffusi fusion on,, cont ontacts acts,, and met metal. al. Masks s ecif where the
Different Development Stages in CMOS Fabrication
Fab of &
Fabrication of N of N Well
2D & 3D Representations of NMOS & PMOS in CMOS Process
Layout Design Rules
The physical mask layout of any circuit to be manufactured using a particular p must mu st co conf nfor orm m to a set set of eo eome metr tric ic co cons nstr trai aint ntss or or rul rules es wh whic ich h ar are ene enerral layout design rules. These rules usually specify the minimum allowable line w for physical objects on‐chip such as metal and polysilicon interconnects or dif areas, minimum feature dimensions, and minimum allowable separations be two such features. The main objective of design rules is to achieve a high o yield and reliability while using the smallest possible silicon area, for any circui manufactured with a particular process. The design rules are usually described in two ways :
minimum allowable feature separations, are stated in terms of absolute dime in micrometers, or,
•Lambda Lambda rules: rules: Th Thes ese e ru rule less sp spec ecif ify y th the e la lay you outt cons nsttrai ain nts in ter erm ms of parameter (which is generally half the channel length and equal to the thickn ol sil silicon la er er and, thus, allow li lin near, ro ortional scalin of all eo
Basic Lambda Design Rules
c
agram
As layout is time‐consuming, designers need fast ways to plan cells and es area before committing to a full layout. Stick diagrams are easy to draw becaus . corresponding stick diagram even though the diagram is not to scale. As an ex stick stic k diagrams diagrams of an inverter inverter and 3 I/P NAND ga gate te are shown below below
MOSIS Design Rule (Sample Set) Rule number R1 R3 R4 R5
R7
R9 R10 R11 R13 R14 R15
R17 R18
Description Minimum active area width n mum ac ve area spac ng Minimum poly width Minimum poly spacing Minimum gate extension of of poly poly over active n mum po y‐ac ve e ge spac ng (poly outside active area) Minimum poly‐active edge spacing (poly inside active area) n mum me a w Minimum metal spacing Poly contact size Minimum poly contact spacing n mum po y con ac o po y e ge spac ng Minimum poly contact to metal edge spacing Minimum poly contact to active edge spacing Active contact size n mum ac ve con ac spac ng (on the same active region) Minimum active contact to active edge spacing Minimum active contact to metal edge spacing
L‐Rule 3L 2L 2L 2L
3L
3L 2L 2L 1L 3L 2L
1L 1L
Illust Illu strrat atio ion n of so some me of the typical MOSIS layout design rules listed above
NMOS & PMOS Transistors as Switches( Binary Logic Generators)
NMOS Transistor
PMOS Transistor
‐
semiconductor adjacent to the gate called the source and drain. They are phy equivalent and for now we will regard them as interchangeable. The body is ty grounded. A PMOS transistor is just the opposite, consisting of p ‐type sour drai dr ain n reg egio ions ns wi with th an n‐ty type pe bo body dy.. In a CM CMOS OS tec echn hnol olog ogy y wi with th bo both th fl transistors, the substrate is either n‐type or p‐type. The other flavor of tran must be built in a special well in which dopant atoms have been added to for
Transistor in OFF state Considering NMOS transistor, the body is generally grounded so the p–n junct the source and drain to body are reverse‐biased. If the gate is also ground current flows through the reverse‐biased junctions. Hence, we say the transi OFF. Just the opposite happens with PMOS transistors.
Transistor in ON state When the gate voltage is raised, it creates an electric field that starts to attra electrons to the underside of the Si–SiO2 interface. If the voltage is raised en the electrons outnumber the holes and a thin region under the gate calle channel is inverted to act as an n‐type semiconductor. Hence, a conducting p electron carriers is formed from source to drain and current can flow. We s transistor is ON. Similarly in case of PMOS the conditions are reversed
Layout Examples: CMOS Inverter
NOR2 GATE
Circuit Diagram
NAND2 GATE
Layout Diagram
Full Adder
Circuit Diagram
Layout Diagram
Calculation of Capacitances of Capacitances & Resistances
Capacitanc Capaci tances es and resi resista stances nces are the most vital factor factorss governing governing the perf perfor or . speed of operation which can be determined through delay calculations. Resis and capacitances in an IC form ‘RC’ pairs and cause various delays in the signa Resist Resi stances ances and and ca acit acitances ances in ICs can can be cate cate oriz orized ed into two two:: Intrinsic RCs: Those resistances and capacitances which occur inside the transis Extrinsic RCs: The resistances and capacitances which occur outside the trans i.e. those which are contributed from the interconnects. Resistance & Capacitance Calculation through RC Delay Model
Effective resistance in transistors: A unit NMOS transistor is defined to have effective resistance R. The size of the transistor is arbitrary but conventionally refers to a transistor with minimum . ., . , width of the NMOS transistor in a minimum‐sized inverter in a standard cell l An NMOS transistor of k times unit width has resistance R/k because it del
Effective capacitance in transistors: Eac ach h tr tran ansi sist stor or al also so has gate an and d di diff ffus usio ion n ca capa paci cita tanc nce. e. We de defi fine ne C to be th capa ca paci cita tanc nce e of a un unit it tr tran ansi sissto torr of ei eith ther er fl flav avor or.. A tr tran ansi sist stor or of k ti time mess un unit it wi widt dt capac ance . us on capac ance epen s on e s ze o e source ra n reg on the approx approxim imati ation onss we ass assum ume e th the e co cont ntac acte ted d sou sourc rce e or dr drai ain n of a un unit it tr trans ansist istor or have ha ve ca capa paci cita tanc nce e of ab abou outt C. Wi Wide derr tr tran ansi sist stor orss ha have ve pr prop opor orti tion onal ally ly gr grea eatter di capacitance. Increasing channel length increases gate capacitance proportionally but not affect diff ffu usi sion on capac acit ita ance ce.. Alth thou oug gh capac aciitanc nce es ha hav ve a nonl nlin ine ear dependence, we use a single average value. We roughly estimate C for a minimum l transistor to be 1 fF/micron of width. In a 65 nm process with a unit transistor bein , . .
Generalized Generalized model for MOSFET capacitances: capacitances: The capacitances associated with a MOSFET are shown in Fig as lumped elements bet the th e de devi vice ce te term rmin inal als. s. Ba Base sed d on th thei eirr ph phys ysic ical al or orig igin ins, s, th the e de devi vice ce ca capa paci cita tanc nces es c ass e n o wo ma or groups: ox e‐re a e capac ances an an capacitances. The gate‐oxide‐related capacitances are Cgd (gate‐to‐drain capacitance (gate‐to‐source capacitance), and Cgb (gate ‐to‐substrate capacitance). Notice that in re the gate‐to‐channel capacitance is distributed and voltage dependent. Consequently, the th e oxi xide de‐re rela late ted d ca capa paci cita tanc nces es de desc scri ribe bed d he herre ch chan ange ge wi with th th the e bi bias as co cond ndit itio ions ns transistor.
Effective resistance in interconnects: The resistance of a metal or polysilicon line also have a profound influence on the propagation delay over that line. The resistance of a line depends on the type of materi po ys con, a um num, go , ... , e mens ons o e ne an na y, e num locations of the contacts on that line. Consider the interconnection line shown in Fig. Th resistance in the indicated current direction can be found as
Where repr re prese esent ntss the cha charract acter eris istic tic re resis sistiv tivity ity of the in inte terc rcon onnec nectt ma mate teria rial, l, an represents the sheet resistivity of the line, in (ohm/square). For a typical polysilicon lay sheet resistivity is between 20‐40 ohm/square, whereas the sheet resistivity of silicide i
Effective capacitance in interconnects: A set of simple formulas developed by Yuan and Trick in the early 1980’s can be u estimate the capacitance of the interconnect structures in which fringing fields complic e ec ve capac ance ca cu a on. e o ow ow ng wo cases are cons ere or wo ranges of line width (w).
Power Dissipation
Static CMOS gates are very power ‐efficient because they dissipate nearly zero power wh For much of the history of CMOS design, power was a secondary consideration behind and area for many chips. As transistor counts and clock frequencies have increased, . some definitions. The instantaneous power P(t) drawn from the power supply is proporti the supply current i DD(t) and the supply voltage VDD
The energy consumed over some time interval T is the integral of the of the instantaneous powe
Static Power Dissipation
. , = ' ,' nMOS transistor is OFF and the pMOS transistor is ON. The output voltage is VDD o '1.'When the input = '1,' the associated nMOS transistor is ON and the pMOS transistor The output voltage is 0 volts (GND). Note that one of the transistors is always OFF when t is in either of these logic states. Ideally, no current flows through the OFF transistor power dissipation is zero when the circuit is quiescent, i.e., when no transistors are sw Zero quiescent power dissipation is a principle advantage of CMOS over competing tra tech techno nolo lo ies. ies. How Howev ever er seco second ndar ar eff effects ects incl includ udin in sub sub thr thresho eshold ld con condu duct ctio ion n tunn tunnel el leakage lead to small amounts of static current flowing through the OFF transistor. Assum leakage current is constant so instantaneous and average power are the same, the static dissipation is the evaluation product of total leakage current and the supply voltage.
Dynamic Power Dissipation Dissipation
Combinational & Sequential Logic Design
What is VHDL?
VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym . used to model a digital system at many levels of abstraction ranging from the algorit level to the gate level. The complexity of the digital system being modeled could vary that of a simple gate to a complete digital electronic system, or anything in between digital system can also be described hierarchically. Timing can also be explicitly model the same description. The VHD VHDLL lan langu guag age e ca can n be re rega gard rded ed as an in inte tegr grat ated ed am amalg algam amat ation ion of the fo follo llo
sequential language + sequential concurrent language + net‐list language + timing specifications + waveform generation language => VHDL
Therefo There fore re,, th the e lan langua guage ge ha hass co cons nstru tructs cts th that at ena enabl ble e yo you u to ex expr press ess the co conc ncur urre re sequential behavior of a digital system with or without timing. It also allows you to m the system as an interconnection of components. Test waveforms can also be gener
Use of VHDL in digital logic design VHDL is used to describe a model for a digital hardware device. This model specif external view of the device and one or more internal views. The internal view of the spec es e unc ona y or s ruc ure, w e e ex erna v ew spec es e n er a device devi ce thr through ough which it com commun munica icates tes with the othe otherr mod models els in its environm environment ent.. The drawn dra wn below shows the hardware hardware device and the corresponding corresponding software software model.
Entity is an abstraction level of the hardware device in cosideration. The device to model mapping is strictly a one to many. That is, a hardware device may have many models. For example, a device modeled at a higher level of abstraction may not have a c one of its inputs, since the clock may not have been used in the description. Also th transfer at the interface may be treated in terms of say, integer values, instead of values. In VHDL, each device model is treated as a distinct representation of a unique
Basic Terminologies The digital system can be as simple as a logic gate or as complex as a complete ele
in another entity Y, becomes a component for the entity Y. Therefore, a component is entity, depending on the level at which you are trying to model. To describe an entity, VHDL provides five different types of primary constructs, called un ts. ts. ey are 1. Entity declaration 2. Architecture bod 3. Configuration declaration 4. Package declaration 5. Package body
An entity is modeled using an entity declaration and at least one architecture body. The declaration describes the external view of the entity, for example, the input and outpu names. The architecture body contains the internal description of the entity, for examp set of interconnected components that represents the structure of the entity, or as a concurrent or sequential statements that represents the behavior of the entity. Each s repr re prese esent ntat atio ion n can be spe specif cifie ied d in a di diff ffer eren entt ar arch chit itect ectur ure e bod body y or mi mix xed wit withi hin n
. binding of one architecture body from the many architecture bodies that may be asso with wi th th the e en enti tity ty.. It may al also so sp spec ecif ify y th the e bi bind ndin ings gs of com ompo pone nen nts use sed d in th the e architecture body to other entities. An entity may have any number of configurations. A package declaration encapsulates a set of related declarations such as type declar subtype declarations, and subprogram declarations that can be shared across two o declaration.
Once an entity has been modeled, it needs to be validated by a VHDL system. A typica system consists of an analyzer and a simulator. The analyzer reads in one or more desig contained in a single file and compiles them into a design library after validating the an per orm ng so some s a c se seman c c ec ec s. e es gn rary s a p ace n environment (that is, the environment that supports the VHDL system) where compiled units are stor stored. ed. The Th e si simu mula lato torr si sim mul ula ates an en enti tity ty,, rep eprres esen entted by an en enti tity ty‐ar arcchitect ctu ure pair conf co nfig igur urat atio ion, n, by rea eadi ding ng in it itss co comp mpil iled ed de desc scri ript ptio ion n fr from om th the e de desi sign gn li libr brar ary y an performing the following steps: 1. Elaboration . 3. Simulation EXAMPLES
Entity Declaration: Declaration: The entity declaration specifies the name of the entity being mode lists the set of interface ports. Ports are signals through which the entity communicat the other models in its external environment.
Here is an example of of an an entity declaration for the half ‐adder circuit shown in Fig above HALF _ADDER ADDER is entit HALF port (A, B: in BIT; SUM, CARRY: out BIT); end HALF_ADDER; ‐‐ This is a comment line.
The entity, called HALF_ADDER, has two input ports, A and B (the mode in specifie port), and two output ports, SUM and CARRY (the mode out specifies output port). predefined type of the language; it is an enumeration type containing the character lite and '1'. The port types for this entity have been specified to be of type BIT, which mea the ports can take the values, '0' or '1'.
Architecture Body: The entity declaration specifies the name of the entity being model lists the set of interface ports. Ports are signals through which the entity communicat the other models in its external environment. architecture HA_Archbody of HALF_ADDER is begin SUM <= A xor B after 8 ns;
Here a dataflow model is used where the HALF_ADDER is described using two conc signal assignment. In a signal assignment statement, the symbol <= implies an assignme value to a signal. The value of the expression on the right ‐hand‐side of the statem compu e an s ass gne o e s gna on e e ‐ an ‐s e, e, ca e e arg rge e con oncu curr rren entt si sign gnal al as assi sign gnme men nt stat atem emen entt is exec ecut uted ed on only ly wh when en an any y si sign gnal al us used ed expression on the right ‐hand ‐side has an event on it, that is, the value for the signal cha
Configuration Declaration is used to select one of the possibly many architecture bodi an entity may have, and to bind components, used to represent structure in that archi body, to entities represented by an entity‐architecture pair or by a configuration, that re . _
The first statement is a library context clause that makes the library names CMOS_L MY_L MY _LIB IB vi visi sibl ble e wi with thin in th the e co conf nfig igur urat atio ion n de decl clar arat atio ion. n. Th The e na name me of th the e co conf nfig igur ur
The first statement (for X1: . . . end for) binds the component instantiation, with label X entit en tity y re repr prese esent nted ed by the en entit tity y‐ar arch chit itect ectur ure e pai pairr, XOR_ OR_GA GATE TE en entit tity y de decla clara ratio tion n DATAF AFLLOW ar arch chit itec ectu ture re bo body dy,, th that at re resi side dess in th the e CM CMOS OS_L _LIB IB de desi sign gn li libr brar ary y. component in insstanti tia atio ion n A1 is bound to a config igu uratio ion n of an en enti tity ty de defi fin ned configuration configur ation declaration, declaration, with name AND_CONFIG, residing in the MY_LIB design librar
components, types, procedures, and functions. These declarations can then be import other design units using a context clause. Here is an example of a package declaration.
The name of the package declared is EXAMPLE_PACK. It contains type, component, co and function declarations. Notice that the behavior of the function INT2BIT_VEC do
Package Body: A package body is primarily used to store the definitions of function proc pr oced edur ures es tha thatt wer were e dec declar lared ed in the co corr rresp espon ondi ding ng pac packa kage ge dec decla lara ratio tion, n, an and d al com let ete e con onsstan antt decla larrati tio ons for an deferred con constants tha that a ear in th the e decla de clara ratio tion. n. Th Ther eref efor ore, e, a pa pack ckag age e bod body y is al alwa ways ys ass assoc ocia iate ted d wit with h a pac packa kage ge dec declar lar furthermore, a package declaration can have at most one package body associated with
MODELING STYLES The Th e ar arch chit itec ectur tural al bod body y whi which ch de dete term rmine iness the in inte tern rnal al ch char arac acte teri rist stics ics of an en entit tity y modeled using different modeling styles as described below 1. As a set 1. As set of of interconnected interconnected components components (to represent structural style ), style ), 2. As 2. As a set set of of concurrent concurrent assignment assignment statements statements (to represent dataflow style dataflow style ), ), 3. As 3. As a set set o o se uen uentia tial l as assi si nme nment nt statements statements to re re rese sent nt behavioral behavioral st le
Structural Style of Modeling of Modeling In th the e str tru uctu turral sty tyle le of model eliing, an en enttit ity y is desc scrribed as a se sett of in intterc com co m on onen ents ts.. Su Such ch a mo mode dell for th the e HA HALF LF _AD ADDE DER R as di disc scus usse sed d be beffor ore e is desc descri ribe be architecture body as shown below.
The name of the architecture body is HA_STRUCTURE. The entity declaration for HALF_ (presented in the previous section) specifies the interface ports for this architecture bo architecture body is composed of two parts: the declarative part (before the keyword
the dec declar larat ativ ive e par partt of the ar arch chit itect ectur ure e bo body dy.. The These se dec declar larat ation ionss spe speci cify fy the in inte te components that are used in the architecture body. The components XOR2 and AND either be predefined components in a library, or if they do not exist, they may later be
The first component instantiation statement, labeled XI, shows that signals A and B (th ports of the HALF_ADDER), are connected to the X and Y input ports of a XOR2 comp while output port Z of this component is connected to output port SUM of the HALF_ en y. m ar y, n e secon componen ns an a on on s a emen , s gna s an connected to ports L and M of the AND2 component, while port N is connected to the port of the HALF_ADDER.
Dataflow Style of Modeling of Modeling In th this is mo mode deli ling ng st styl yle, e, th the e fl flow ow of da data ta th thrrou ough gh th the e en enti tity ty is exp xpre ress ssed ed pr prim imar ar concurrent signal assignment statements. The structure of the entity is not explicitly sp , . architecture body for the HALF..ADDER entity that uses this style.
The dataflow model for the HALF_ADDER is described using two concurrent signal assig s a emen s sequen a s gna ass gnmen s a emen s are escr e n e nex sec signal assignment statement, the symbol <= implies an assignment of a value to a sign value of the expression on the right‐hand‐side of the statement is computed and is assig the signal on the left‐hand‐sid side, e, ca calle lled d th the e ta targe rgett sig signa nal. l. A co concu ncurre rrent nt sig signal nal as
Behavioral Style of Modeling of Modeling In con ontr tras astt to th the e st le less of mo mode deli lin n de desc scri ribe bed d ea earl rlie ierr th the e be beha havi vior oral al st le of specifies the behavior of an entity as a set of statements that are executed sequentially spec sp ecif ifie ied d or orde derr. Th This is se sett of se seq que uen nti tial al st stat atem emen ents ts,, th that at ar are e sp spec ecif ifie ied d in insi side de a stat st atem emen ent, t, do no nott exp xpli lici citl tly y sp spec ecif ify y th the e st stru ruct ctur ure e of th the e en enti tity ty bu butt me mere rely ly sp spec ec unc on o na y. process s a emen s a concurren s a emen a can appear w architecture body. For example, consider the following behavioral model for the DECOD entity.
Basic language Elements These include data objects that store values of a given type, type, literals that represent co , . type. Data Objects
Data Types Data types categorically divides different forms of data to be associated with data o .
Scalar Types
Composite Types
Operators Operators are mathematical or logical functions which give action to data objects or relate two
Logical Operators
Relational Operators
Adding Operators
Multiplying Operators
Miscellaneous Operators
